init commit.
Проект каким он достался от Димы.
This commit is contained in:
commit
b8a0477c5c
1
.gitignore
vendored
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1
.gitignore
vendored
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./Debug
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253
ADC.c
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253
ADC.c
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#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP281x Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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#include "ADC.h"
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#include "log_to_mem.h"
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#include "RS485.h"
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#include "filter_bat2.h"
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#include "measure.h"
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#include "message.h"
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#include "package.h"
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#include "peripher.h"
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#define SIZE_ADC_BUF 1000
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Uint16 ADC_table[24];
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Uint16 raw_table[24];
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Uint16 ConversionCount;
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int MAY=0;
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// Prototype statements for functions found within this file.
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interrupt void adc_isr(void);
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void setup_adc()
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{
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long CLKdiv,HSPCLKdiv,Rate;
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#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
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#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
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#endif
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#if (CPU_FRQ_100MHZ)
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#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
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#endif
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// Specific clock setting for this example:
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// EALLOW;
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// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
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// EDIS;
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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EALLOW; // This is needed to write to EALLOW protected register
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PieVectTable.ADCINT = &adc_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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InitAdc(); // For this example, init the ADC
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// Enable ADCINT in PIE
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PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
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IER |= M_INT1; // Enable CPU Interrupt 1
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// EINT; // Enable Global interrupt INTM
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// ERTM; // Enable Global realtime interrupt DBGM
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// Configure ADC
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if(Desk==dsk_COMM)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0B; // Äàëüøå òåìïåðàòóðû
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0A;
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x09;
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x08;
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x00;
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x01;
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x04;
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AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x03;
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AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x05;
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AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x02;
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AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x06;
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AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x07;
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AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0F; // Òîêè-íàïðÿæåíèÿ
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AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D;
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AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E;
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AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0C;
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}
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if(Desk==dsk_SHKF)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000E; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x6; // 380Â Ô1
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x7; // 380Â Ô2
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // 220Â Ô1
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // 220Â Ô2 ?
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x5; // 31Â
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x4; // 31Â UC
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0xF; // 24Â ÏÌ
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AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0xD; // +24Â Äò
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AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0xB; // -24Â Äò
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AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x8; // 24Â ÏÊ
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AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // 24Â ÏÌÓ
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AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xA; // 24Â ÏÓ
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AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x9; // 15Â Äð
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AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x1; // ÄÒ° 1
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AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0; // ÄÒ° 2
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}
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AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode
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//AdcRegs.ADCTRL1.bit.ACQ_PS=15;
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//AdcRegs.ADCTRL1.bit.CPS=1;
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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// Assumes ePWM1 clock is already enabled in InitSysCtrl();
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EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
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EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
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EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
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EPwm1Regs.TBCTL.bit.HSPCLKDIV=4;
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EPwm1Regs.TBCTL.bit.CLKDIV=1;
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CLKdiv = 1<<EPwm1Regs.TBCTL.bit.CLKDIV;
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if(EPwm1Regs.TBCTL.bit.HSPCLKDIV) HSPCLKdiv = 2*EPwm1Regs.TBCTL.bit.HSPCLKDIV;
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else HSPCLKdiv = 1;
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Rate = (SYSCLKOUT/(HSPCLKdiv*CLKdiv))/ADC_FREQ;
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EPwm1Regs.TBPRD = Rate;//0x4000; // Set period for ePWM1
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EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
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}
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interrupt void adc_isr(void)
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{
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// static int count_run_one_canal=0;
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// static int number_tpl_canal=0;
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static long zero_cownt[4]={0,0,0,0};
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static long prenumb[4]={0,0,0,0};
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static float filtar[4]={0,0,0,0};
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float Temper;
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int Numb;
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int i;
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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if(MAY)
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{
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if(Desk==dsk_SHKF)
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{
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for(i=0;i<17;i++)
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if(sens_type[i])
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{
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if(sens_type[i]==VIRT_24) Numb = ExtraCanal[i];
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else Numb= *((&AdcRegs.ADCRESULT0)+i) >>4;
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if((sens_type[i]==POWER_380)||(sens_type[i]==POWER_220))
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{
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if(Numb>200/*150*/)
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{
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if(prenumb[i]==0) zero_cownt[i]=0;
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zero_cownt[i]+=2;
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filtar[i] += ((float)Numb-filtar[i])/100.0;
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Numb = filtar[i];
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prenumb[i]=1;
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}
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else
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{
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prenumb[i]=0;
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if(zero_cownt[i])
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{
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zero_cownt[i]--;
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continue;
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}
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}
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}
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raw_table[i] = Numb; Temper = Numb;
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ADC_table[i] = filterbat(&filter[i],Temper);
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if(sens_type[i]==TERMO_AD) Temper_count(i);
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else Power_count(i);
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}
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sig.all = chk.all;
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chk.all = 0;
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if(/*Modbus[127].bit.bitE*/0)
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{
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Test_mem_limit(16);
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for(i=0;i<8;i++)
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{
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Log_to_mem(raw_table[i]);
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Log_to_mem(ADC_table[i]);
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} } }
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/*
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if(Mode==adr_SHKF)
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{
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for(i=0;i<15;i++)
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{
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Temper= *((&AdcRegs.ADCRESULT0)+i) >>4;
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adc_table_lem[i]=filterbat(&filter[i],Temper);
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adc_table_tpl[i]=adc_table_lem[i];
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}
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adc_table_lem[15] = ExtraCanal1;
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adc_table_lem[16] = ExtraCanal2;
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measure_all();
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}
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*/
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if(Desk==dsk_COMM)
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{
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for(i=0;i<24;i++)
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if(sens_type[i])
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{
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|
Temper = *((&AdcRegs.ADCRESULT0)+i) >>4;
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|
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if(sens_type[i] != VOLTAGE)
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Temper = filterbat(&filter[i],Temper);
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ADC_table[i]=(int)Temper;
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|
if(sens_type[i]==VOLTAGE) Current_count(i);
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|
else Temper_count(i);
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|
}
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sig.all = chk.all;
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|
chk.all = 0;
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|
} }
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|
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// Reinitialize for next ADC sequence
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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|
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
|
||||||
|
|
||||||
|
// Restore registers saved:
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||||||
|
DINT;
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||||||
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
6
ADC.h
Normal file
6
ADC.h
Normal file
@ -0,0 +1,6 @@
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|
extern int MAY;
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|
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||||||
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extern Uint16 ADC_table[];
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||||||
|
|
||||||
|
|
||||||
|
void setup_adc(void);
|
||||||
206
F28335.cmd
Normal file
206
F28335.cmd
Normal file
@ -0,0 +1,206 @@
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|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/10 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:56 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: F28335.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For F28335 Device
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28335
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28335 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0: /* Program Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
|
||||||
|
|
||||||
|
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
|
||||||
|
RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */
|
||||||
|
/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
|
||||||
|
// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
|
||||||
|
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
|
||||||
|
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
|
||||||
|
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
|
||||||
|
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
|
||||||
|
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
|
||||||
|
|
||||||
|
PAGE 1 : /* Data Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
|
||||||
|
/* Registers remain on PAGE1 */
|
||||||
|
|
||||||
|
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */
|
||||||
|
/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allocate sections to memory blocks.
|
||||||
|
Note:
|
||||||
|
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
|
||||||
|
execution when booting to flash
|
||||||
|
ramfuncs user defined section to store functions that will be copied from Flash into RAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Allocate program areas: */
|
||||||
|
.cinit : > RAML0 PAGE = 0
|
||||||
|
.pinit : > RAML0 PAGE = 0
|
||||||
|
.text : > RAML0 PAGE = 0
|
||||||
|
codestart : > BEGIN PAGE = 0
|
||||||
|
ramfuncs : LOAD = RAML4,
|
||||||
|
RUN = RAML4,
|
||||||
|
LOAD_START(_RamfuncsLoadStart),
|
||||||
|
LOAD_END(_RamfuncsLoadEnd),
|
||||||
|
RUN_START(_RamfuncsRunStart),
|
||||||
|
PAGE = 0
|
||||||
|
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate uninitalized data sections: */
|
||||||
|
.stack : > RAMM1 PAGE = 1
|
||||||
|
.ebss : > RAML5 PAGE = 1
|
||||||
|
.esysmem : > RAML0 PAGE = 0
|
||||||
|
|
||||||
|
.logg : > ZONE7A PAGE = 1
|
||||||
|
|
||||||
|
/* Initalized sections go in Flash */
|
||||||
|
/* For SDFlash to program these, they must be allocated to page 0 */
|
||||||
|
.econst : > RAML4 PAGE = 0
|
||||||
|
.switch : > RAML4 PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate IQ math areas: */
|
||||||
|
IQmath : > FLASHC PAGE = 0 /* Math Code */
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Allocate DMA-accessible RAM sections: * /
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
/* DMARAML6 : > RAML6, PAGE = 1
|
||||||
|
DMARAML7 : > RAML7, PAGE = 1
|
||||||
|
*/
|
||||||
|
/* Allocate 0x400 of XINTF Zone 7 to storing data */
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
/* .reset is a standard section used by the compiler. It contains the */
|
||||||
|
/* the address of the start of _c_int00 for C Code. /*
|
||||||
|
/* When using the boot ROM this section and the CPU vector */
|
||||||
|
/* table is not needed. Thus the default type is set here to */
|
||||||
|
/* DSECT */
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT
|
||||||
|
vectors : > VECTORS PAGE = 0, TYPE = DSECT
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
|
|
||||||
194
GPIO_table.h
Normal file
194
GPIO_table.h
Normal file
@ -0,0 +1,194 @@
|
|||||||
|
#define COMM_gpio00_dir 0UL
|
||||||
|
#define COMM_gpio01_dir 0UL
|
||||||
|
#define COMM_gpio02_dir 0UL
|
||||||
|
#define COMM_gpio03_dir 0UL
|
||||||
|
#define COMM_gpio04_dir 0UL
|
||||||
|
#define COMM_gpio05_dir 0UL
|
||||||
|
#define COMM_gpio06_dir 0UL
|
||||||
|
#define COMM_gpio07_dir 0UL
|
||||||
|
#define COMM_gpio08_dir 0UL
|
||||||
|
#define COMM_gpio09_dir 0UL
|
||||||
|
#define COMM_gpio10_dir 0UL
|
||||||
|
#define COMM_gpio11_dir 0UL
|
||||||
|
|
||||||
|
#define COMM_gpio19_dir 1UL // 63 — SPI
|
||||||
|
#define COMM_gpio20_dir 0UL // 64 2:9B mode 2
|
||||||
|
#define COMM_gpio21_dir 0UL // 65 2:9A mode 4
|
||||||
|
#define COMM_gpio22_dir 0UL // 66 2:12C mode 1
|
||||||
|
#define COMM_gpio23_dir 0UL // 67 2:12B control -24V
|
||||||
|
#define COMM_gpio24_dir 0UL
|
||||||
|
#define COMM_gpio25_dir 0UL
|
||||||
|
#define COMM_gpio26_dir 0UL // 72 2:11B control +24V
|
||||||
|
#define COMM_gpio27_dir 0UL
|
||||||
|
|
||||||
|
#define COMM_gpio32_dir 1UL // 74 2:10B SDA
|
||||||
|
#define COMM_gpio33_dir 1UL // 75 2:10C SCL
|
||||||
|
#define COMM_gpio34_dir 1UL // 142 — SCI
|
||||||
|
|
||||||
|
#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red
|
||||||
|
#define COMM_gpio49_dir 1UL // 89 2:14B ts2 red
|
||||||
|
#define COMM_gpio50_dir 0UL
|
||||||
|
#define COMM_gpio51_dir 0UL // 91 2:13C mode !8
|
||||||
|
#define COMM_gpio52_dir 1UL // 94 2:13B ts1 green
|
||||||
|
#define COMM_gpio53_dir 0UL
|
||||||
|
|
||||||
|
#define COMM_gpio58_dir 1UL // 100 1:13C led term
|
||||||
|
#define COMM_gpio59_dir 1UL // 110 1:13B gotov
|
||||||
|
#define COMM_gpio60_dir 1UL // 111 1:13A led job
|
||||||
|
#define COMM_gpio61_dir 0UL
|
||||||
|
#define COMM_gpio62_dir 1UL // 113 1:14B alarm
|
||||||
|
#define COMM_gpio63_dir 1UL // 114 1:14A rez out
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
|
||||||
|
#define VEPP_gpio00_dir 0UL // 5 2:7A input
|
||||||
|
#define VEPP_gpio01_dir 0UL // 6 2:4A input
|
||||||
|
#define VEPP_gpio02_dir 0UL // 7 2:7B input
|
||||||
|
#define VEPP_gpio03_dir 0UL // 10 2:4B input
|
||||||
|
#define VEPP_gpio04_dir 0UL // 11 2:7C input
|
||||||
|
#define VEPP_gpio05_dir 0UL // 12 2:4C input
|
||||||
|
#define VEPP_gpio06_dir 0UL // 13 2:6A input
|
||||||
|
#define VEPP_gpio07_dir 0UL // 16 2:3A input
|
||||||
|
#define VEPP_gpio08_dir 0UL // 17 2:6B input
|
||||||
|
#define VEPP_gpio09_dir 0UL // 18 2:3B input
|
||||||
|
#define VEPP_gpio10_dir 0UL // 19 2:6C input
|
||||||
|
#define VEPP_gpio11_dir 0UL // 20 2:3C input
|
||||||
|
|
||||||
|
#define VEPP_gpio19_dir 1UL // 63 — SPI
|
||||||
|
#define VEPP_gpio20_dir 0UL // 64 2:9B mode 2
|
||||||
|
#define VEPP_gpio21_dir 0UL // 65 2:9A mode 4
|
||||||
|
#define VEPP_gpio22_dir 0UL // 66 2:12C mode 1
|
||||||
|
#define VEPP_gpio23_dir 0UL // 67 2:12B input
|
||||||
|
#define VEPP_gpio24_dir 0UL // 68 2:12A input
|
||||||
|
#define VEPP_gpio25_dir 0UL // 69 2:11C input
|
||||||
|
#define VEPP_gpio26_dir 0UL // 72 2:11B input
|
||||||
|
#define VEPP_gpio27_dir 0UL // 73 2:11A input
|
||||||
|
|
||||||
|
#define VEPP_gpio32_dir 0UL // 74 2:10B input
|
||||||
|
#define VEPP_gpio33_dir 0UL // 75 2:10C input
|
||||||
|
#define VEPP_gpio34_dir 1UL // 142 — SCI
|
||||||
|
|
||||||
|
#define VEPP_gpio48_dir 1UL // 88 2:14C DIOD red
|
||||||
|
#define VEPP_gpio49_dir 0UL // 89 2:14B input
|
||||||
|
#define VEPP_gpio50_dir 0UL // 90 2:14A input
|
||||||
|
#define VEPP_gpio51_dir 0UL // 91 2:13C mode !8
|
||||||
|
#define VEPP_gpio52_dir 0UL // 94 2:13B input
|
||||||
|
#define VEPP_gpio53_dir 0UL // 95 2:13A input
|
||||||
|
|
||||||
|
#define VEPP_gpio58_dir 0UL // 100 1:13C input
|
||||||
|
#define VEPP_gpio59_dir 0UL
|
||||||
|
#define VEPP_gpio60_dir 1UL // 111 1:13A gotov
|
||||||
|
#define VEPP_gpio61_dir 0UL // 112 1:14C input
|
||||||
|
#define VEPP_gpio62_dir 1UL // 113 1:14C rezout
|
||||||
|
#define VEPP_gpio63_dir 1UL // 114 1:14A ledjob
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
|
||||||
|
#define ISOL_gpio00_dir 0UL // 5 2:7A
|
||||||
|
#define ISOL_gpio01_dir 0UL // 6 2:4A
|
||||||
|
#define ISOL_gpio02_dir 0UL // 7 2:7B
|
||||||
|
#define ISOL_gpio03_dir 0UL // 10 2:4B
|
||||||
|
#define ISOL_gpio04_dir 0UL // 11 2:7C
|
||||||
|
#define ISOL_gpio05_dir 0UL // 12 2:4C
|
||||||
|
#define ISOL_gpio06_dir 0UL // 13 2:6A
|
||||||
|
#define ISOL_gpio07_dir 0UL // 16 2:3A
|
||||||
|
#define ISOL_gpio08_dir 0UL // 17 2:6B
|
||||||
|
#define ISOL_gpio09_dir 0UL // 18 2:3B
|
||||||
|
#define ISOL_gpio10_dir 0UL // 19 2:6C
|
||||||
|
#define ISOL_gpio11_dir 0UL // 20 2:3C
|
||||||
|
|
||||||
|
#define ISOL_gpio19_dir 1UL // 63 — SPI
|
||||||
|
#define ISOL_gpio20_dir 0UL // 64 2:9B mode 2
|
||||||
|
#define ISOL_gpio21_dir 0UL // 65 2:9A mode 4
|
||||||
|
#define ISOL_gpio22_dir 0UL // 66 2:12C mode 1
|
||||||
|
#define ISOL_gpio23_dir 0UL // 67 2:12B opt input 1
|
||||||
|
#define ISOL_gpio24_dir 1UL // 68 2:12A led 2
|
||||||
|
#define ISOL_gpio25_dir 0UL // 69 2:11C
|
||||||
|
#define ISOL_gpio26_dir 1UL // 72 2:11B opt out 2
|
||||||
|
#define ISOL_gpio27_dir 1UL // 73 2:11A led 1
|
||||||
|
|
||||||
|
#define ISOL_gpio32_dir 1UL // 74 2:10B opt out 1
|
||||||
|
#define ISOL_gpio33_dir 0UL // 75 2:10C
|
||||||
|
#define ISOL_gpio34_dir 1UL // 142 — SCI
|
||||||
|
|
||||||
|
#define ISOL_gpio48_dir 1UL // 88 2:14C DIOD red
|
||||||
|
#define ISOL_gpio49_dir 0UL // 89 2:14B
|
||||||
|
#define ISOL_gpio50_dir 0UL // 90 2:14A
|
||||||
|
#define ISOL_gpio51_dir 0UL // 91 2:13C mode !8
|
||||||
|
#define ISOL_gpio52_dir 0UL // 94 2:13B opt input 2
|
||||||
|
#define ISOL_gpio53_dir 1UL // 95 2:13A led 3
|
||||||
|
|
||||||
|
#define ISOL_gpio58_dir 0UL // 100 1:13C
|
||||||
|
#define ISOL_gpio59_dir 1UL // 110 1:13B gotov
|
||||||
|
#define ISOL_gpio60_dir 0UL // 111 1:13A
|
||||||
|
#define ISOL_gpio61_dir 0UL // 112 1:14C
|
||||||
|
#define ISOL_gpio62_dir 0UL // 113 1:14C input
|
||||||
|
#define ISOL_gpio63_dir 0UL // 114 1:14A
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
|
||||||
|
#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \
|
||||||
|
(COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \
|
||||||
|
(COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \
|
||||||
|
(COMM_gpio19_dir<<19)+ \
|
||||||
|
(COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \
|
||||||
|
(COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27);
|
||||||
|
#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \
|
||||||
|
(COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \
|
||||||
|
(COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \
|
||||||
|
(COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \
|
||||||
|
(COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31);
|
||||||
|
|
||||||
|
#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \
|
||||||
|
(BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \
|
||||||
|
(BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \
|
||||||
|
(BKSD_gpio19_dir<<19)+ \
|
||||||
|
(BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \
|
||||||
|
(BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27);
|
||||||
|
#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \
|
||||||
|
(BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \
|
||||||
|
(BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \
|
||||||
|
(BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \
|
||||||
|
(BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31);
|
||||||
|
|
||||||
|
#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \
|
||||||
|
(PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \
|
||||||
|
(PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \
|
||||||
|
(PULT_gpio19_dir<<19)+ \
|
||||||
|
(PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \
|
||||||
|
(PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27);
|
||||||
|
#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \
|
||||||
|
(PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \
|
||||||
|
(PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \
|
||||||
|
(PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \
|
||||||
|
(PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31);
|
||||||
|
|
||||||
|
#define VEPP_GPADIR (VEPP_gpio00_dir ) + (VEPP_gpio01_dir<<1) + (VEPP_gpio02_dir<<2) + (VEPP_gpio03_dir<<3) + \
|
||||||
|
(VEPP_gpio04_dir<<4) + (VEPP_gpio05_dir<<5) + (VEPP_gpio06_dir<<6) + (VEPP_gpio07_dir<<7) + \
|
||||||
|
(VEPP_gpio08_dir<<8) + (VEPP_gpio09_dir<<9) + (VEPP_gpio10_dir<<10)+ (VEPP_gpio11_dir<<11)+ \
|
||||||
|
(VEPP_gpio19_dir<<19)+ \
|
||||||
|
(VEPP_gpio20_dir<<20)+ (VEPP_gpio21_dir<<21)+ (VEPP_gpio22_dir<<22)+ (VEPP_gpio23_dir<<23)+ \
|
||||||
|
(VEPP_gpio24_dir<<24)+ (VEPP_gpio25_dir<<25)+ (VEPP_gpio26_dir<<26)+ (VEPP_gpio27_dir<<27);
|
||||||
|
#define VEPP_GPBDIR (VEPP_gpio32_dir )+ (VEPP_gpio33_dir<<1) + (VEPP_gpio34_dir<<2 )+ \
|
||||||
|
(VEPP_gpio48_dir<<16)+ (VEPP_gpio49_dir<<17)+ (VEPP_gpio50_dir<<18)+ (VEPP_gpio51_dir<<19)+ \
|
||||||
|
(VEPP_gpio52_dir<<20)+ (VEPP_gpio53_dir<<21)+ \
|
||||||
|
(VEPP_gpio58_dir<<26)+ (VEPP_gpio59_dir<<27)+ \
|
||||||
|
(VEPP_gpio60_dir<<28)+ (VEPP_gpio61_dir<<29)+ (VEPP_gpio62_dir<<30)+ (VEPP_gpio63_dir<<31);
|
||||||
|
|
||||||
|
#define ISOL_GPADIR (ISOL_gpio00_dir ) + (ISOL_gpio01_dir<<1) + (ISOL_gpio02_dir<<2) + (ISOL_gpio03_dir<<3) + \
|
||||||
|
(ISOL_gpio04_dir<<4) + (ISOL_gpio05_dir<<5) + (ISOL_gpio06_dir<<6) + (ISOL_gpio07_dir<<7) + \
|
||||||
|
(ISOL_gpio08_dir<<8) + (ISOL_gpio09_dir<<9) + (ISOL_gpio10_dir<<10)+ (ISOL_gpio11_dir<<11)+ \
|
||||||
|
(ISOL_gpio19_dir<<19)+ \
|
||||||
|
(ISOL_gpio20_dir<<20)+ (ISOL_gpio21_dir<<21)+ (ISOL_gpio22_dir<<22)+ (ISOL_gpio23_dir<<23)+ \
|
||||||
|
(ISOL_gpio24_dir<<24)+ (ISOL_gpio25_dir<<25)+ (ISOL_gpio26_dir<<26)+ (ISOL_gpio27_dir<<27);
|
||||||
|
#define ISOL_GPBDIR (ISOL_gpio32_dir )+ (ISOL_gpio33_dir<<1) + (ISOL_gpio34_dir<<2 )+ \
|
||||||
|
(ISOL_gpio48_dir<<16)+ (ISOL_gpio49_dir<<17)+ (ISOL_gpio50_dir<<18)+ (ISOL_gpio51_dir<<19)+ \
|
||||||
|
(ISOL_gpio52_dir<<20)+ (ISOL_gpio53_dir<<21)+ \
|
||||||
|
(ISOL_gpio58_dir<<26)+ (ISOL_gpio59_dir<<27)+ \
|
||||||
|
(ISOL_gpio60_dir<<28)+ (ISOL_gpio61_dir<<29)+ (ISOL_gpio62_dir<<30)+ (ISOL_gpio63_dir<<31);
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// No more.
|
||||||
|
//===========================================================================
|
||||||
553
RS485.c
Normal file
553
RS485.c
Normal file
@ -0,0 +1,553 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************
|
||||||
|
RS485.ñ
|
||||||
|
****************************************************************
|
||||||
|
* Ïðîöåäóðû ðàáîòû ñ UART *
|
||||||
|
****************************************************************/
|
||||||
|
|
||||||
|
//#include "big_dsp_module.h"
|
||||||
|
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h"
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "bios_dsp.h"
|
||||||
|
#include "cntrl_adr.h"
|
||||||
|
|
||||||
|
#include "tools.h"
|
||||||
|
|
||||||
|
//#include "flash_tools.h"
|
||||||
|
|
||||||
|
|
||||||
|
RS_DATA rs_a,rs_b;
|
||||||
|
|
||||||
|
unsigned int RS_Len[70]={0};
|
||||||
|
|
||||||
|
static char size_cmd15=1;
|
||||||
|
|
||||||
|
void RS_RX_Handler(RS_DATA *rs_arr);
|
||||||
|
void RS_TX_Handler(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */
|
||||||
|
interrupt void RSA_RX_Handler(void)
|
||||||
|
{
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
clear_timer_rs_live(&rs_a);
|
||||||
|
RS_RX_Handler(&rs_a);
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void RSB_RX_Handler(void)
|
||||||
|
{
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
clear_timer_rs_live(&rs_b);
|
||||||
|
RS_RX_Handler(&rs_b);
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void RSA_TX_Handler(void)
|
||||||
|
{
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
clear_timer_rs_live(&rs_a);
|
||||||
|
RS_TX_Handler(&rs_a);
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void RSB_TX_Handler(void)
|
||||||
|
{
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
clear_timer_rs_live(&rs_b);
|
||||||
|
RS_TX_Handler(&rs_b);
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */
|
||||||
|
void RS_RX_Handler(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
char Rc;
|
||||||
|
char RS_BytePtr;
|
||||||
|
|
||||||
|
// led1_on();
|
||||||
|
|
||||||
|
for(;;) // 'goto' ýòî íå îïåðàòîð àçûêà Ñ
|
||||||
|
{
|
||||||
|
if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag
|
||||||
|
{
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
|
||||||
|
return; // êñòàòè ýòî åäèíñòâåííûé âûõîä èç ïðåðûâàíèà
|
||||||
|
}
|
||||||
|
|
||||||
|
Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // ×èòàåì ñèìâîë â ëþáîì ñëó÷àå
|
||||||
|
|
||||||
|
if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag
|
||||||
|
{
|
||||||
|
rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI
|
||||||
|
rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(rs_arr->RS_DataReady) continue; // Íå çàáðàëè äàííûå
|
||||||
|
|
||||||
|
if (rs_arr->RS_Flag9bit==1) // äëà RS485????????
|
||||||
|
{
|
||||||
|
// Èíèöèàëèçèðóåì ïåðåìåííûå è ôëàãè
|
||||||
|
rs_arr->RS_FlagBegin = true; // Æäåì çàãîëîâîê
|
||||||
|
rs_arr->RS_RecvLen = 0;
|
||||||
|
rs_arr->RS_FlagSkiping = false;
|
||||||
|
rs_arr->RS_HeaderCnt = 0;
|
||||||
|
rs_arr->RS_Cmd = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(rs_arr->RS_FlagSkiping) continue; // Íå íàì
|
||||||
|
|
||||||
|
if (rs_arr->RS_FlagBegin) // Çàãîëîâîê
|
||||||
|
{
|
||||||
|
if (rs_arr->RS_HeaderCnt==0) // Àäðåñ êîíòðîëëåðà èëè ñòàíäàðòíàà êîìàíäà
|
||||||
|
{
|
||||||
|
if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING)
|
||||||
|
|| ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING))
|
||||||
|
|
||||||
|
{
|
||||||
|
rs_arr->addr_recive=Rc; // çàïîìíèëè àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè
|
||||||
|
rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Ïåðâûé áàéò
|
||||||
|
RS_SetBitMode(rs_arr,8); // ïåðåñòðîèëèñü â 8-áèò ðåæèì
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rs_arr->RS_FlagSkiping = true; // Íå íàøåìó êîíòðîëëåðó
|
||||||
|
rs_arr->RS_FlagBegin = false; // îñòàëèñü â 9-áèò ðåæèìå
|
||||||
|
// led1_off();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Âòîðîé áàéò è ò.ä.
|
||||||
|
|
||||||
|
if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING)
|
||||||
|
{
|
||||||
|
RS_Len[CMD_MODBUS_16] = (10+Rc);
|
||||||
|
}
|
||||||
|
|
||||||
|
// åñëè âòîðîé áàéò - ýòî êîìàíäà
|
||||||
|
if (rs_arr->RS_HeaderCnt == 2)
|
||||||
|
{
|
||||||
|
rs_arr->RS_Cmd = Rc;
|
||||||
|
// Ïðîâåðêà äëèíû ïîñûëêè
|
||||||
|
// CMD_LOAD - ìëàäøàà íà äàííûé ìîìåíò
|
||||||
|
// CMD_STD_ANS - ñòàðøàà íà äàííûé ìîìåíò
|
||||||
|
if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3)
|
||||||
|
|| ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD))
|
||||||
|
)
|
||||||
|
{
|
||||||
|
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||||
|
rs_arr->RS_HeaderCnt = 0; // Ïîòîìó ÷òî êîìàíäà íå òà
|
||||||
|
rs_arr->RS_FlagBegin = true;
|
||||||
|
rs_arr->RS_FlagSkiping = false;
|
||||||
|
rs_arr->RS_Cmd=0;
|
||||||
|
// led1_off();
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (rs_arr->RS_Cmd == CMD_LOAD) // Äëà ýòîé êîìàíäû çàãîëîâîê î÷åíü êîðîòêèé
|
||||||
|
rs_arr->RS_FlagBegin = false;// äàëüøå èäóò äàííûå
|
||||||
|
}
|
||||||
|
|
||||||
|
if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) ||
|
||||||
|
(rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header)))
|
||||||
|
{ // Ïîëó÷èëè çàãîëîâîê
|
||||||
|
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||||
|
rs_arr->RS_FlagBegin = false;
|
||||||
|
rs_arr->RS_FlagSkiping = true;
|
||||||
|
rs_arr->RS_DataReady = true;
|
||||||
|
rs_arr->RS_Cmd=0;
|
||||||
|
// led1_off();
|
||||||
|
} } }
|
||||||
|
else // Ïîòîê äàííûõ
|
||||||
|
{
|
||||||
|
if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End)
|
||||||
|
{
|
||||||
|
rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé
|
||||||
|
rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé
|
||||||
|
}
|
||||||
|
if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // Ìû çäåñü îêàçàëèñü ïî êàêîé-òî ÷óäîâèùíîé îøèáêå
|
||||||
|
|
||||||
|
if(rs_arr->RS_DataReady) // Åñëè äàííûå â îñíîâíîì öèêëå íå çàáðàíû,
|
||||||
|
{ // òî ïðîïóñêàåì ñëåäóþùóþ ïîñûëêó
|
||||||
|
rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà
|
||||||
|
// led1_off();
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
RS_BytePtr = rs_arr->RS_RecvLen++ % 2;
|
||||||
|
if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // Ïîëó÷èëè ñëîâî
|
||||||
|
else *rs_arr->pRS_RecvPtr = Rc<<8;
|
||||||
|
|
||||||
|
if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // Êîíåö ïîñûëêè
|
||||||
|
{
|
||||||
|
rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD;
|
||||||
|
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå äàííûå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||||
|
rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà
|
||||||
|
rs_arr->RS_DataReady = true; // Ôëàã â îñíîâíîé öèêë - äàííûå ïîëó÷åíû
|
||||||
|
// led1_off();
|
||||||
|
} } } }
|
||||||
|
|
||||||
|
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïîñëàíî */
|
||||||
|
void RS_TX_Handler(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
char RS_BytePtr;
|
||||||
|
// unsigned int i;
|
||||||
|
|
||||||
|
if(rs_arr->RS_SendBlockMode == BM_CHAR32)
|
||||||
|
{
|
||||||
|
if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||||
|
{
|
||||||
|
enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||||
|
}
|
||||||
|
SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++));
|
||||||
|
|
||||||
|
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||||
|
{
|
||||||
|
RS_Wait4OK(rs_arr);
|
||||||
|
// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||||
|
|
||||||
|
RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/
|
||||||
|
RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */
|
||||||
|
|
||||||
|
rs_arr->flag_TIMEOUT_to_Send=false; /* ñáðîñèëè ôëàã îæèäàíèà òàéìàóòà */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else /* BM_PACKED */
|
||||||
|
{
|
||||||
|
|
||||||
|
RS_BytePtr = (rs_arr->RS_SendLen++) % 2;
|
||||||
|
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||||
|
{
|
||||||
|
enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||||
|
}
|
||||||
|
if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) ));
|
||||||
|
else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr ));
|
||||||
|
|
||||||
|
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||||
|
{
|
||||||
|
RS_Wait4OK(rs_arr);
|
||||||
|
// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||||
|
// RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/
|
||||||
|
// RS_Line_to_receive(); /* ðåæèì ïðèåìà RS485 */
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Èíèöèàëèçàöèà ìàññèâà äëèí êîìàíä */
|
||||||
|
void setup_arr_cmd_length()
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i=0;i<70;i++) RS_Len[i]=i;
|
||||||
|
|
||||||
|
RS_Len[CMD_LOAD] = 12;
|
||||||
|
RS_Len[CMD_UPLOAD] = 12;
|
||||||
|
RS_Len[CMD_RUN] = 8;
|
||||||
|
RS_Len[CMD_XFLASH] = 9;
|
||||||
|
RS_Len[CMD_TFLASH] = 16;
|
||||||
|
RS_Len[CMD_PEEK] = 8;
|
||||||
|
RS_Len[CMD_POKE] = 12;
|
||||||
|
RS_Len[CMD_INITLOAD] = 12;
|
||||||
|
RS_Len[CMD_INIT] = 5;
|
||||||
|
RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2;
|
||||||
|
RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1;
|
||||||
|
RS_Len[CMD_IMPULSE] = 8;
|
||||||
|
RS_Len[CMD_MODBUS_3] = 8;
|
||||||
|
RS_Len[CMD_MODBUS_6] = 8;
|
||||||
|
RS_Len[CMD_MODBUS_16] = 13;
|
||||||
|
RS_Len[CMD_MODBUS_15] = 27;
|
||||||
|
RS_Len[CMD_EXTEND] = 18;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */
|
||||||
|
void RS_SetBitMode(RS_DATA *rs_arr,int n)
|
||||||
|
{
|
||||||
|
if(n == 8)
|
||||||
|
{
|
||||||
|
RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */
|
||||||
|
rs_arr->RS_Flag9bit=0;
|
||||||
|
}
|
||||||
|
if(n == 9)
|
||||||
|
{
|
||||||
|
RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */
|
||||||
|
rs_arr->RS_Flag9bit=1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
/** Ïîñûëêà áëîêà áàéòîâ.
|
||||||
|
Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0.
|
||||||
|
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||||
|
@param buf àäðåñ ìàññèâà
|
||||||
|
@param len êîëè÷åñòâî áàéò
|
||||||
|
@see RS_BSend, RS_TRANSMIT_INTR */
|
||||||
|
int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
for (i=0; i <= 30000; i++){} /* Ïàóçà äëà PC */
|
||||||
|
|
||||||
|
RS_Line_to_send(rs_arr); /* ðåæèì ïåðåäà÷è RS485 */
|
||||||
|
|
||||||
|
for (i=0; i <= 10000; i++){} /* Ïàóçà äëà PC */
|
||||||
|
|
||||||
|
rs_arr->RS_SLength = len; /* Íàñòðàèâàåì ïåðåìåííûå */
|
||||||
|
rs_arr->pRS_SendPtr = pBuf + 1;
|
||||||
|
|
||||||
|
rs_arr->RS_SendBlockMode = BM_CHAR32;
|
||||||
|
|
||||||
|
RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà */
|
||||||
|
RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */
|
||||||
|
|
||||||
|
rs_arr->RS_SendLen = 1; /* Äâà áàéòà óæå ïåðåäàëè */
|
||||||
|
if(len > 1)
|
||||||
|
{
|
||||||
|
enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||||
|
SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ
|
||||||
|
RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà áåç ïðåðûâàíèà */
|
||||||
|
for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||||
|
RS_SetBitMode(rs_arr,9); /* Îáðàòíî â 9-áèò ðåæèì */
|
||||||
|
RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ
|
||||||
|
int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len)
|
||||||
|
{
|
||||||
|
|
||||||
|
RS_Line_to_send(rs_arr); // ðåæèì ïåðåäà÷è RS485
|
||||||
|
|
||||||
|
rs_arr->RS_SLength = len; // Íàñòðàèâàåì ïåðåìåííûå
|
||||||
|
rs_arr->pRS_SendPtr = pBuf;
|
||||||
|
rs_arr->RS_SendBlockMode = BM_PACKED;
|
||||||
|
|
||||||
|
RS_Wait4OK(rs_arr); // Îæèäàåì î÷èñòêè è óõîäà ïîñëåäíåãî áàéòà
|
||||||
|
RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */
|
||||||
|
|
||||||
|
rs_arr->RS_SendLen = 1; // Îäèí áàéò óæå ïåðåäàëè
|
||||||
|
|
||||||
|
enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||||
|
|
||||||
|
SCI_send(rs_arr,HIBYTE(*pBuf));// Ïåðåäàåì ïåðâûé áàéò
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà.
|
||||||
|
@param speed ñêîðîñòü RS â áîä */
|
||||||
|
/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà.
|
||||||
|
@param speed ñêîðîñòü RS â áîä */
|
||||||
|
void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed)
|
||||||
|
{
|
||||||
|
long SciBaud;
|
||||||
|
|
||||||
|
SciBaud = LSPCLK/(speed*8.0);
|
||||||
|
|
||||||
|
// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++;
|
||||||
|
|
||||||
|
rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud);
|
||||||
|
rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||||
|
void create_uart_vars(char size_cmd15_set)
|
||||||
|
{
|
||||||
|
size_cmd15=size_cmd15_set;
|
||||||
|
rs_a.commnumber=COM_1;
|
||||||
|
rs_b.commnumber=COM_2;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||||
|
|
||||||
|
void setup_uart(char commnumber, unsigned long speed_baud)
|
||||||
|
{
|
||||||
|
volatile struct SCI_REGS *SciRegs;
|
||||||
|
RS_DATA *rs_arr;
|
||||||
|
|
||||||
|
if(commnumber==COM_1)
|
||||||
|
{
|
||||||
|
rs_a.SciRegs = &SciaRegs;
|
||||||
|
rs_arr = &rs_a;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O)
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I)
|
||||||
|
|
||||||
|
PieVectTable.SCIRXINTA = &RSA_RX_Handler;
|
||||||
|
PieVectTable.SCITXINTA = &RSA_TX_Handler;
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
|
||||||
|
IER |= M_INT9; // Enable CPU INT
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(commnumber==COM_2)
|
||||||
|
{
|
||||||
|
rs_b.SciRegs = &ScibRegs;
|
||||||
|
rs_arr = &rs_b;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O)
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default)
|
||||||
|
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output
|
||||||
|
|
||||||
|
PieVectTable.SCIRXINTB = &RSB_RX_Handler;
|
||||||
|
PieVectTable.SCITXINTB = &RSB_TX_Handler;
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4
|
||||||
|
IER |= M_INT9; // Enable CPU INT
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
rs_arr->commnumber = commnumber;
|
||||||
|
SciRegs = rs_arr->SciRegs;
|
||||||
|
RS_SetLineMode(rs_arr,8,'N',1);
|
||||||
|
|
||||||
|
// enable TX, RX, internal SCICLK,
|
||||||
|
// Disable RX ERR, SLEEP, TXWAKE
|
||||||
|
|
||||||
|
SciRegs->SCIFFCT.bit.ABDCLR=1;
|
||||||
|
SciRegs->SCIFFCT.bit.CDC=0;
|
||||||
|
|
||||||
|
SciRegs->SCICTL1.bit.RXERRINTENA=0;
|
||||||
|
SciRegs->SCICTL1.bit.SWRESET=0;
|
||||||
|
SciRegs->SCICTL1.bit.TXWAKE=0;
|
||||||
|
SciRegs->SCICTL1.bit.SLEEP=0;
|
||||||
|
SciRegs->SCICTL1.bit.TXENA=1;
|
||||||
|
SciRegs->SCICTL1.bit.RXENA=1;
|
||||||
|
|
||||||
|
SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off
|
||||||
|
SciRegs->SCIFFRX.bit.RXFFIL=1; // Äëèíà íàèìåíüøåé êîìàíäû
|
||||||
|
|
||||||
|
setup_arr_cmd_length();
|
||||||
|
RS_SetLineSpeed(rs_arr,speed_baud); // ñêîðîñòü ëèíèè
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
enableUARTInt(rs_arr); // ðàçðåøåíèå ïðåðûâàíèé UART
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
rs_arr->RS_PrevCmd = 0; // íå áûëî íèêàêèõ êîìàíä
|
||||||
|
rs_arr->flag_TIMEOUT_to_Send = 0;
|
||||||
|
rs_arr->flag_LEADING = 0;
|
||||||
|
|
||||||
|
SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
|
||||||
|
SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Íàñòðîéêà ðåæèìà ëèíèè.
|
||||||
|
@param bit êîëè÷åñòâî áèò äàííûõ
|
||||||
|
@param parity ðåæèì ÷åòíîñòè (N,O,E,M,S)
|
||||||
|
@param stop êîëè÷åñòâî ñòîïîâûõ áèò */
|
||||||
|
void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop)
|
||||||
|
{
|
||||||
|
volatile struct SCI_REGS *SciRegs;
|
||||||
|
/*
|
||||||
|
SCICCR - SCI Communication Control Register
|
||||||
|
Bit Bit Name Designation Functions
|
||||||
|
2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits).
|
||||||
|
3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications.
|
||||||
|
4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin.
|
||||||
|
5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0.
|
||||||
|
6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1.
|
||||||
|
7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1.
|
||||||
|
*/
|
||||||
|
|
||||||
|
SciRegs = rs_arr->SciRegs;
|
||||||
|
|
||||||
|
if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1;
|
||||||
|
|
||||||
|
switch(parity)
|
||||||
|
{
|
||||||
|
case 'N': SciRegs->SCICCR.bit.PARITYENA = 0;
|
||||||
|
break;
|
||||||
|
case 'O': SciRegs->SCICCR.bit.PARITYENA = 1;
|
||||||
|
SciRegs->SCICCR.bit.PARITY = 0;
|
||||||
|
break;
|
||||||
|
case 'E': SciRegs->SCICCR.bit.PARITYENA = 1;
|
||||||
|
SciRegs->SCICCR.bit.PARITY = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0;
|
||||||
|
if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1;
|
||||||
|
|
||||||
|
SciRegs->SCICCR.bit.LOOPBKENA = 0; //0
|
||||||
|
SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void clear_timer_rs_live(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
rs_arr->time_wait_rs_out=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ïðîâåðêà íà æèâó÷åñòü RS */
|
||||||
|
void test_rs_live(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT)
|
||||||
|
rs_arr->time_wait_rs_out++;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rs_arr->time_wait_rs_out=0;
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
}*/ }
|
||||||
138
RS485.h
Normal file
138
RS485.h
Normal file
@ -0,0 +1,138 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************
|
||||||
|
RS485.h
|
||||||
|
****************************************************************
|
||||||
|
* Ïðîöåäóðû ðàáîòû ñ UART *
|
||||||
|
****************************************************************/
|
||||||
|
#ifndef _RS485
|
||||||
|
#define _RS485
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||||
|
//#include "DSP2833x_Sci.h"
|
||||||
|
//#include "cntrl_adr.h"
|
||||||
|
//#include "params.h"
|
||||||
|
|
||||||
|
#define COM_1 1
|
||||||
|
#define COM_2 2
|
||||||
|
|
||||||
|
#define MAX_RECEIVE_LENGTH 400 // 80 //150
|
||||||
|
#define MAX_SEND_LENGTH 400 //150
|
||||||
|
|
||||||
|
#define TIME_WAIT_RS_BYTE_OUT 1000
|
||||||
|
#define TIME_WAIT_RS_LOST_BYTE 100
|
||||||
|
#define RS_TIME_OUT (SECOND*10)
|
||||||
|
|
||||||
|
#define Rec_Bloc_Begin 0x200000
|
||||||
|
#define Rec_Bloc_End 0x2F0000
|
||||||
|
#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin)
|
||||||
|
|
||||||
|
/* Message RS declaration */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
volatile struct SCI_REGS *SciRegs;
|
||||||
|
|
||||||
|
unsigned int commnumber; // Íîìåð ïîðòà
|
||||||
|
unsigned long RS_Length; // Äëèíà ïàêåòà
|
||||||
|
|
||||||
|
unsigned int *pRS_RecvPtr; // Áóôåð ïðèåìà
|
||||||
|
unsigned int *pRS_SendPtr; // Áóôåð ïîñûëêè
|
||||||
|
unsigned int *pRecvPtr;
|
||||||
|
|
||||||
|
unsigned int RS_PrevCmd; // Ïðåäûäóùàà êîììàíäà
|
||||||
|
unsigned int RS_Cmd; // Òåêóùàà êîììàíäà
|
||||||
|
unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Çàãîëîâîê
|
||||||
|
unsigned int flag_TIMEOUT_to_Send; // Ôëàã îæèäàíèà òàéìàóòà íà îòñûëêó
|
||||||
|
unsigned int flag_TIMEOUT_to_Receive; // Ôëàã îæèäàíèà òàéìàóòà íà ïðèåì
|
||||||
|
unsigned int RS_DataReady; // Ôëàã ãîòîâíîñòè RS äàííûõ
|
||||||
|
unsigned int buffer[MAX_SEND_LENGTH]; // Áóôåð äëà îòñûëêè ïî RS
|
||||||
|
|
||||||
|
unsigned int addr_answer; // àäðåñ êóäà îòâå÷àòü â ðåæèìå âåäóùåãî
|
||||||
|
unsigned int addr_recive; // àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè
|
||||||
|
unsigned int flag_LEADING; // Ôëàã ðåæèìà êîíòðîëëåðà (ïî óìîë÷àíèþ âåäîìûé)
|
||||||
|
unsigned long RS_RecvLen;
|
||||||
|
unsigned long RS_SLength; // Äëèíà ïàêåòà äëà ïîñûëêè
|
||||||
|
unsigned long RS_SendLen; // Êîëè÷åñòâî áàéò óæå ïåðåäàëè
|
||||||
|
char RS_SendBlockMode; // Ðåæèì ïåðåäà÷è
|
||||||
|
char RS_Flag9bit; // äëà RS485????????
|
||||||
|
int BS_LoadOK; // Ôëàã óñïåøíîñòè ïðèåìà áëîêà
|
||||||
|
int RS_FlagBegin;
|
||||||
|
int RS_HeaderCnt;
|
||||||
|
int RS_FlagSkiping;
|
||||||
|
unsigned long curr_baud;
|
||||||
|
unsigned long time_wait_rs_out;
|
||||||
|
|
||||||
|
} RS_DATA;
|
||||||
|
|
||||||
|
extern RS_DATA rs_a,rs_b;
|
||||||
|
|
||||||
|
extern unsigned int
|
||||||
|
RS_Len[70]; /* Äåéñòâèòåëüíàà äëèíà êîìàíäû (îòëàäî÷íîé) + 1 */
|
||||||
|
|
||||||
|
interrupt void RSA_RX_Handler(void);
|
||||||
|
interrupt void RSA_TX_Handler(void);
|
||||||
|
interrupt void RSB_RX_Handler(void);
|
||||||
|
interrupt void RSB_TX_Handler(void);
|
||||||
|
|
||||||
|
/* èíèöèëèçàöèà ïåðåìåííûõ rs_a,rs_b*/
|
||||||
|
void create_uart_vars(char size_cmd15);
|
||||||
|
|
||||||
|
/** Ïîâòîðíàà èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà, èñïîëüçóåòñà ïîñëå ïîäâèñà */
|
||||||
|
/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */
|
||||||
|
void RS_SetBitMode(RS_DATA *rs_arr, int n);
|
||||||
|
|
||||||
|
/** Ïîñûëêà áëîêà áàéòîâ.
|
||||||
|
Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0.
|
||||||
|
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||||
|
@param buf àäðåñ ìàññèâà
|
||||||
|
@param len êîëè÷åñòâî áàéò
|
||||||
|
@see RS_BSend, RS_TRANSMIT_INTR
|
||||||
|
*/
|
||||||
|
int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
|
||||||
|
|
||||||
|
/** Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ.
|
||||||
|
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||||
|
@param buf àäðåñ ìàññèâà
|
||||||
|
@param len êîëè÷åñòâî 8-áèòíûõ áàéò
|
||||||
|
@see RS_Send, RS_TRANSMIT_INTR
|
||||||
|
*/
|
||||||
|
int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
|
||||||
|
|
||||||
|
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||||
|
void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - ñêîðîñòü ëèíèè â áîäàõ */
|
||||||
|
|
||||||
|
void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop);
|
||||||
|
void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed);
|
||||||
|
|
||||||
|
// Transmit a character from the SCI'
|
||||||
|
#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y)
|
||||||
|
|
||||||
|
// Îæèäàíèå çàâåðøåíèà ïåðåäà÷è UART
|
||||||
|
// wait for TRDY =1 for empty state
|
||||||
|
#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY))
|
||||||
|
|
||||||
|
/** Ïåðåêëþ÷åíèå ëèíèè íà ïðèåì */
|
||||||
|
#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
|
||||||
|
|
||||||
|
/** Ïåðåêëþ÷åíèå ëèíèè íà ïåðåäà÷ó */
|
||||||
|
#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0;
|
||||||
|
|
||||||
|
/** Ðàçðåøåíèå ïðåðûâàíèé ïî ïîëó÷åíèþ ñèìâîëà è îøèáêàì îò UART */
|
||||||
|
#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2
|
||||||
|
#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1
|
||||||
|
|
||||||
|
void clear_timer_rs_live(RS_DATA *rs_arr);
|
||||||
|
void test_rs_live(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _RS485 */
|
||||||
|
|
||||||
BIN
bin/HEX2BIN.EXE
Normal file
BIN
bin/HEX2BIN.EXE
Normal file
Binary file not shown.
5
bin/create_rs.bat
Normal file
5
bin/create_rs.bat
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
set iname=BalzamUMPLeonardTMS320F28335
|
||||||
|
set oname=BalzamUMPLeonardTMS320F28335
|
||||||
|
|
||||||
|
hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i
|
||||||
|
hex2bin %oname%.hex %oname%.bin
|
||||||
BIN
bin/hex2000.exe
Normal file
BIN
bin/hex2000.exe
Normal file
Binary file not shown.
BIN
bin/ice.bin
Normal file
BIN
bin/ice.bin
Normal file
Binary file not shown.
981
bin/ice.hex
Normal file
981
bin/ice.hex
Normal file
@ -0,0 +1,981 @@
|
|||||||
|
:20000000AA080000000000000000000000000000000000002BB8F5010000E2B900FF80DD5E
|
||||||
|
:2000200000000000C1C081C1400101C3C003800241C201C6C006800741C70005C1C581C4C4
|
||||||
|
:20004000400401CCC00C800D41CD000FC1CF81CE400E000AC1CA81CB400B01C9C0098008A5
|
||||||
|
:2000600041C801D8C018801941D9001BC1DB81DA401A001EC1DE81DF401F01DDC01D801CD4
|
||||||
|
:2000800041DC0014C1D481D5401501D7C017801641D601D2C012801341D30011C1D181D053
|
||||||
|
:2000A000401001F0C030803141F10033C1F381F240320036C1F681F7403701F5C0358034E5
|
||||||
|
:2000C00041F4003CC1FC81FD403D01FFC03F803E41FE01FAC03A803B41FB0039C1F981F8A3
|
||||||
|
:2000E00040380028C1E881E9402901EBC02B802A41EA01EEC02E802F41EF002DC1ED81EC34
|
||||||
|
:20010000402C01E4C024802541E50027C1E781E640260022C1E281E3402301E1C021802054
|
||||||
|
:2001200041E001A0C060806141A10063C1A381A240620066C1A681A7406701A5C065806443
|
||||||
|
:2001400041A4006CC1AC81AD406D01AFC06F806E41AE01AAC06A806B41AB0069C1A981A8A2
|
||||||
|
:2001600040680078C1B881B9407901BBC07B807A41BA01BEC07E807F41BF007DC1BD81BCD3
|
||||||
|
:20018000407C01B4C074807541B50077C1B781B640760072C1B281B3407301B1C071807054
|
||||||
|
:2001A00041B00050C190819140510193C053805241920196C056805741970055C1958194A2
|
||||||
|
:2001C0004054019CC05C805D419D005FC19F819E405E005AC19A819B405B0199C0598058A4
|
||||||
|
:2001E00041980188C04880494189004BC18B818A404A004EC18E818F404F018DC04D804C33
|
||||||
|
:20020000418C0044C184818540450187C047804641860182C042804341830041C181818051
|
||||||
|
:200220004040FFFF80D700000000EEFF58D80000E6127D391358FA3F6AEF74BF00000000EE
|
||||||
|
:200240000000000000000000000000000000000000000000FFFFBED700000000FFFFBFD777
|
||||||
|
:2002600000000000FFFFF0D700000000FEFF76D8000000000000FFFFFFD700000000FFFF9C
|
||||||
|
:20028000B1DE00000000F8FFB2DE000000000000000000000000000000000000F8FFC0DEB3
|
||||||
|
:2002A000000000000000000000000000000000000000F8FFC8DE00000000000000000000A1
|
||||||
|
:2002C0000000000000000000F4FF42DD00000000000000000000609F0000E49F0000B99F32
|
||||||
|
:2002E0000000BE9F0000FFFF5ADD00000000FFFF5BDD00000000FFFF5CDD00000000FFFF01
|
||||||
|
:200300005DDD00000000FEFFD4DE000000000000FEFFD6DE000000000000FEFFD8DE000090
|
||||||
|
:2003200000000000FEFFDADE000000000000FFFFDCDE00000000FFFFDDDE00000000FFFF99
|
||||||
|
:2003400049D700000000FFFF4AD700000000FFFF4BD700000000FFFF4CD700000000FCFF22
|
||||||
|
:2003600068D700000000000000000000FFFFECDE00000100FFFFEDDE00000000FFFFF6DEDA
|
||||||
|
:2003800000000000FDFFDEDE0000400000000000FFFFE1DE00000000FEFF7ADD0000DDB9BE
|
||||||
|
:2003A0000000FEFF7CDD0000DDB90000FEFFF8DE000000000000FEFFFADE000000000000A9
|
||||||
|
:2003C000FEFF7CD7000001000100FFFF7ED700000000FFFF00D700000000FFFF44D300008E
|
||||||
|
:2003E0000100FFFF76DD00000A00FFFF77DD00000100FFFF7FD700000000FFFFFEDB000023
|
||||||
|
:06040000000000000000F6
|
||||||
|
:20040600E239000000801F765D030792025206ED1F76BF010D1A0010056F1F76BF010D1AEA
|
||||||
|
:20042600000806001F765D030792025206ED1F76BF010F1A0010056F1F76BF010F1A00084B
|
||||||
|
:20044600060008FE03E2440103E2420010E7400000776FE800F0007703E24600AFE24202CD
|
||||||
|
:2004660001E8E8FA20E751000DE8B89E00E70800007703E24800AFE24803AFE24600AFE231
|
||||||
|
:20048600460100E3484200E79900007710E740004076F8B802E8010250E80000407675B608
|
||||||
|
:2004A60088FE060002FE412B419218521363013B008FA6D741850156A400C42B4185418804
|
||||||
|
:2004C600008FC0D70156A400C47E410A41921852EF641F765E03BF56260B1F765E03BF5691
|
||||||
|
:2004E600270B82FE060004FE2276008F49B01F7634001AA81A7669FF1F766F030F8F404272
|
||||||
|
:20050600380642A8C000A9B8A9BD120F0077007702E8D11B008F66DD89E6000040763AB65A
|
||||||
|
:200526001F7630000C282040237600101F765E03BF5601021F765E030228E8031F765E03A4
|
||||||
|
:20054600BF5603501F765E030428F4011F765E03008F4C1D08A81F765E0319020A1E1F76AA
|
||||||
|
:200566005E03008FA8610CA8432B439218521363013B008FA6D743850156A400C42B4385E3
|
||||||
|
:200586004388008FC0D70156A400C47E430A43921852EF641F765D030692015203EC025225
|
||||||
|
:2005A60059ED1F765E03BF5626091F765E03BF5627091F765E03BF5628091F765E03BF5633
|
||||||
|
:2005C60029091F765E03BF562A091F765E03BF562B091F765E03BF562E0A1F765E03BF5618
|
||||||
|
:2005E6002F0A1F765E03BF56300A1F765E03BF56310A1F765E03BF5632021F765F03BF56E6
|
||||||
|
:200606000C0D1F765E03BF5633021F765F03BF560D0C1F765E03BF5634021F765F03BF5609
|
||||||
|
:200626000E0F1F765E03BF5635021F765F03BF560F0E1F7670030C1A00401F7670030D1A8F
|
||||||
|
:2006460000401F7670030E1A00401F7670030F1A0040035203EC04522DED1F765E03BF56B4
|
||||||
|
:2006660026091F765E03BF5627091F765E03BF5628091F765E03BF5629091F765E03BF5686
|
||||||
|
:200686002A091F765E03BF562B091F765E03BF562D0A1F765E03BF562E0A1F765E03BF5652
|
||||||
|
:2006A6002F0A1F765E03BF56300A1F765E03BF56310A055254ED1F765E03BF5626031F760F
|
||||||
|
:2006C6005F03BF5600011F765E03BF5627031F765F03012B1F765E03BF5628041F765F0316
|
||||||
|
:2006E600BF5602031F765E03BF5629041F765F03BF5603021F765E03BF562A051F765E0361
|
||||||
|
:20070600BF562B051F765E03BF562C061F765E03BF562D061F765E03BF562E061F765E03DE
|
||||||
|
:20072600BF562F061F765E03BF5630061F765E03BF5631061F765E03BF5632081F765E03AB
|
||||||
|
:20074600BF5633091F765E03BF5634091F765E03BF5635071F765E03BF563607432B439228
|
||||||
|
:2007660004520E63013B00BE008F8ED7035643010156A400C4C2430A43920452F464432B62
|
||||||
|
:20078600439206520F63013B008F9AD790E5035643010156A40003E2C400430A4392065248
|
||||||
|
:2007A600F364432B43921C520E63013B00BE008FC0DB035643010156A400C4C2430A439256
|
||||||
|
:2007C6001C52F464432B439220520E63013B00BE008F00D8035643010156A400C4C2430A5B
|
||||||
|
:2007E60043922052F464432B439228521063432D008FC0D8408F58D812350156A400120238
|
||||||
|
:2008060040763DB9430A43922852F264432B439218520D63013B008F00DC43850156A400AD
|
||||||
|
:20082600C41800E0430A43921852F5641F765E03BF56000C84FE060002FE412B41920352DE
|
||||||
|
:200846001863422B429209521063412D008FA4DC013B09350156A40042850156A400C42B65
|
||||||
|
:20086600420A42920952F264410A41920352EA64412B419218523763013B008FA6D741858F
|
||||||
|
:200886000156A400C4922BEC4193A892008DA4DCA2FFCBFFA894A3FFA9850156A00041928E
|
||||||
|
:2008A600109BC0002CB9A92D019A66FFC0984192415C013B189C008DA4DCA993A2FFCBFFA0
|
||||||
|
:2008C60018DCA894A3FFA9850156A000109BA492C0002CB9A92D019A66FFC098410A419249
|
||||||
|
:2008E6001852CB64412B419203521463013B4185415C408FA4DC0156A50003DCC588A4850F
|
||||||
|
:20090600008FADDC0156A400C47E410A41920352EE641F765D030792015205ED1F767203DA
|
||||||
|
:20092600251A8000035205ED1F767203251A0F001F767203BF5633F31F767203342800C0E8
|
||||||
|
:2009460082FE060006FE467D459744A8419600520EEC448A013B4585C40F0362019A116F32
|
||||||
|
:20096600448A01020156C40046920B6F448AC40603ED009A066F448A01024156C400469298
|
||||||
|
:2009860086FE060008FE44A84196C492459647961F7672031E8A013B41850156A400C44D30
|
||||||
|
:2009A60014EE1F7672031E8A41850156A400C4CC00E046961F7672031E8A41850156A400FD
|
||||||
|
:2009C600469247CAC4960A6F1F76720341851EA30156AB004792A4A9C498474800BE00B63D
|
||||||
|
:2009E6000AEF1F7672031E8A41850156A400C44E02EE01B6A79302ED01BE1F767203215663
|
||||||
|
:200A060041001E06AC07A98AA6920190C4CDFFFD88FFA8CAC4961F7672031E8A418500BEA6
|
||||||
|
:200A260000B60156A400C44902EF01B6A79202ED01BE1F765E030592A9CD01001F765E0369
|
||||||
|
:200A4600A6CBA9CCFEFF0191A9CB059788FE060006FEA68E437C42974196442B1F765D0374
|
||||||
|
:200A66000B9204ECBF56450A036F452888134392AB28010042540A63649BC0001BB9A828F6
|
||||||
|
:200A8600FF0FA99F42550265AB2B1F767203013B008FC0DB1E83035641010156A4004185B9
|
||||||
|
:200AA6000156A500C5CD0100A85D4593AB9240769F82005203EC441A0100AD5CA93A84DCC4
|
||||||
|
:200AC60004ECC492A08AC49686FE060008FE44974396462B472B013B008FE4D7438501567A
|
||||||
|
:200AE600A400C492445423624385008FE4D70156A400C488008FF7D743850156A400A69228
|
||||||
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||||||
|
:206DA60069FF0156A400407678A71F7633002192A9CDFFFE1F763300C7FF019001500190A6
|
||||||
|
:206DC60087FFA8CA2196103B44921F763300329684FEAFE2BE03AFE2BE02AFE2BE01AFE247
|
||||||
|
:206DE600BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF177602761B76F0FF00E2BD00C5
|
||||||
|
:206E060030E6000602FE422916561F7633003292419623760001267600011F763300329253
|
||||||
|
:206E26001F763300322B1F7633002128FFFF102901021F768001061E1F767B031C0A1F76D4
|
||||||
|
:206E460033002192A9CDFFFE1F763300C7FF01900150019087FFA8CA2196103B41921F7670
|
||||||
|
:206E66003300329682FE80E2BE00F1FF177602761B76F0FF00E2BD0030E60006422916566A
|
||||||
|
:206E860080E2BE00F1FF177602761B76F0FF00E2BD0030E600064229165680E2BE00F1FFB5
|
||||||
|
:206EA600177602761F765D030792025206ED1F76BF010D1A0010056F1F76BF010D1A00086E
|
||||||
|
:206EC60006001F765D030792025206ED1F76BF010F1A0010056F1F76BF010F1A0008060043
|
||||||
|
:206EE60002FE42974196009A005300BE02EC019A005202ED01BE427E41920DEC429206EC56
|
||||||
|
:206F06001F76BF01031A0004116F1F76BF01051A00040C6F429206EC1F76BF010A1A010042
|
||||||
|
:206F2600056F1F76BF010C1A010082FE060002FE419600520CEC009A009B1F76BF010944DD
|
||||||
|
:206F460002EF019B00530DED019A0B6F009A009B1F76BF01014702EF019B005302ED019A00
|
||||||
|
:206F660082FE060002FE4196005206EC1F76BF010F1A2000056F1F76BF01071A000182FE61
|
||||||
|
:206F8600060002FE2276008F91A91F7634001AA81A7669FF1F766F030F8F4042380642A8B2
|
||||||
|
:206FA600C000A9B8A9BD120F0077007702E8D11F008F66DD89E6000040763AB61F763000AF
|
||||||
|
:206FC6000C282040237600101F765E03BF56010182FE0600008F000C1F7675031EA800026B
|
||||||
|
:206FE6001F7630000119021E1F763000062B1F763000072B1F763000041A10001F763000E7
|
||||||
|
:20700600041A20001F7675030002201E1F767503008F080C26A81F767503008F100C2EA8D3
|
||||||
|
:207026001F76300001190A1E1F76300000020119121E1F7630000E2B1F7630000F2B1F76A0
|
||||||
|
:207046003000162B1F763000172B1F7630000C1A10001F763000141A10001F7630000C1AC9
|
||||||
|
:2070660020001F763000141A20001F7675030002281E1F767503301E060008FE03E24601EF
|
||||||
|
:2070860003E2440042A8428A4406E41E428A4606F41EAFE24400AFE2460100E70800007782
|
||||||
|
:2070A60088E60000007703E24800428AC48A4806D41E428AC48AF42B428AC48AFC2B428A18
|
||||||
|
:2070C600C48AE41A1000428AC48AE41A2000428AC48AE418FFFB428AC48AE418FFF7428A2E
|
||||||
|
:2070E600C48AE41A0040428A0002D41E88FE0600BD3ABDB2BDAABDA202FE0129A9BF120FD3
|
||||||
|
:2071060058FF5B61A85C7F91A8088000421EA493D6FFA85CA9BF160F6761A85D7F91A80888
|
||||||
|
:207126008000A859A958A593D6FFA85DA493A571A8180001A697A418FF00A518FF007FDC98
|
||||||
|
:20714600A492A59EA7964D64A90801FF3E62A193A09236FFA859A958420635FF0EF6A11F94
|
||||||
|
:20716600A95BA3010AF6A11F2D56A204A32DA03640FF0BF6A11F33FF009B30FF54FFA20CD5
|
||||||
|
:20718600A39540FFA70801001FF677FF200940FFA70801001FF677FF5AFFA7922265A908CA
|
||||||
|
:2071A60001FF1363A9A946FF7F91A85BA95AA625A79596FFA20CA395A9BD120F82FEBE82DD
|
||||||
|
:2071C600BE86BE8BBE8E0600009B57FFA8087FFF5AFFA693F260A8280080AA71AB92ED6FC3
|
||||||
|
:2071E60020FF0000EA6F5AFFA493A818000196FFA85CA9A9A8087FFFA81C0080A4CBDD6FA8
|
||||||
|
:207206001F76C001201A00104076E5A822761F762C003518F8FF1F762C00341A03001F7641
|
||||||
|
:207226002C003418F7FF1F762C003418FBFF1F762C002ECC9FFF1F762C0020502E961F76F0
|
||||||
|
:207246002C002ECCE3FF1F762C0008502E961F762C002ECCFCFF1F762C0001502E961F7622
|
||||||
|
:207266002C002ECCFFCF1F762C00A91A00102E961F762C002ECCFFF11F762C00A91A000687
|
||||||
|
:207286002E961F762C002E187FFE1F762C002F18BFFF1F762C002E18FFBF1F762C002E180E
|
||||||
|
:2072A600FF7F1F762C002F1A03001A7607F6007769FF060022761F76BE011618FCFF1F7621
|
||||||
|
:2072C600BE011818FCFF1F76BE011A1A01001F76BE011B1A01001A7669FF060004FE421E4B
|
||||||
|
:2072E6000129420640FF421E0002441E4206440F0A6928024076DEB901024407441E420696
|
||||||
|
:20730600440FF86684FE0600103B1F7633002018FEFF1F763300222B1F763300242B1F7625
|
||||||
|
:207326003300262B1F763300282B1F7633002A2B1F7633002C2B1F7633002E2B1F76330083
|
||||||
|
:20734600302B1F763300322B1F763300342B1F763300362B1F763300382B1F763300232B16
|
||||||
|
:207366001F763300252B1F763300272B1F763300292B1F7633002B2B1F7633002D2B1F76E6
|
||||||
|
:2073860033002F2B1F763300312B1F763300332B1F763300352B1F763300372B1F763300F6
|
||||||
|
:2073A600392B69FF06001F763300201A01001F7633002128FFFF102969FF0600BDB2BDAA66
|
||||||
|
:2073C600BDA203E2BD0403E2BD0503E2BD0606FE03E2440042A808D04283428A42C442C5C6
|
||||||
|
:2073E60042864282AFE29502AFE2F40050E801000CD0428AAFE2440010E3D64B0ED114E3AE
|
||||||
|
:20740600974C07E3C41000E3E245AFE29B0641E77101007710E74000007703E24600428AD3
|
||||||
|
:2074260042830CD094060ED0951E428A0CD04606941E4283428A08D0F506941E428A4406A8
|
||||||
|
:20744600F41EAFE2460086FEAFE2BE06AFE2BE05AFE2BE04BE82BE86BE8B0600AD28000411
|
||||||
|
:2074660069FF1F5616561A5610E6000240291F76000002291B762276A928E2B9A8280000C7
|
||||||
|
:2074860001091B61C076E2B904290F6F009BA92401DF046C0429A82401DFA61EA1F786244D
|
||||||
|
:2074A600A706A1810109A71EA92403635CFF043BA95901DF0900ECFF1A76A928FFFFA82856
|
||||||
|
:2074C600FFFF01090E61FF76FFFF066F01DFBDC3A71E673EBEC5A92401DFA82458FFF760D3
|
||||||
|
:2074E600407697B94076B2B91B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0070
|
||||||
|
:2075060003E2BD0103E2BD0203E2BD0330E6000669FF42291656227601021F76750301561F
|
||||||
|
:207526003000008F42DD69FF1F76750308C5673E1A76AFE2BE03AFE2BE02AFE2BE01AFE26C
|
||||||
|
:20754600BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF17760276022904295F565AFF16
|
||||||
|
:2075660042065F56421E00021FF617564200AB06325602292076022904295F565AFF42063A
|
||||||
|
:2075860056FF421E00021FF6175642003256022920765AFF00021FF617564200A9A920761A
|
||||||
|
:2075A6005AFF00021FF617564200207602FE208F00001F767B032EA81F767B03208F00F0C6
|
||||||
|
:2075C60030A81F767B032E061F767B03321E1F767B03342B1F767B032E06421E066F428AC9
|
||||||
|
:2075E600C42B01024207421E1F767B033006420FF76682FE060002FEA0E514AD0962A0E537
|
||||||
|
:207606001F766F0314AD90E5B4563E01166F05BE92E601004FE803C00CB5A60000E7CA000B
|
||||||
|
:20762600007700E78A000077CFE812F0007700E75100007700E7400082FE0600A85CA9713B
|
||||||
|
:20764600A697013BA98556FFA95DA48556FFA95CA5920FF6A41FA64F026C5CFF2076A69610
|
||||||
|
:20766600A85C013BA98556FFA95DA48556FFA95CA5920FF6A41FA64F026C5DFFA89220762A
|
||||||
|
:207686005AFFAB92A48EA4C507ECFF9CA988859287960E00FEFFAB92A988A9A9A60F10EC44
|
||||||
|
:2076A600AA930EECA9A9FF9DA85CBF76FEFF859287960E00FEFF859287960C00F8FFA08AC9
|
||||||
|
:2076C600060022761F76C0011C1A080069FF787680001A761F76C4011CCCFF3F1F76C40132
|
||||||
|
:2076E600A91A00401C961F76C401BF5618E069FF028FE649A9A84076DEB9060006FE008F09
|
||||||
|
:2077060000C044A8008F000D46A82276412B419280520D634683448AA9A084C4020944A8F5
|
||||||
|
:20772600461EC5C2410A41928052F5641A7686FE69FF0600AB28FFFFAA28FFFFA928FFFF1D
|
||||||
|
:20774600A828FFFFAB0F04ED00BE00D4096FAB28FFFFAA28FFFFA4A9C4880209A98AA692F0
|
||||||
|
:207766004076DFA306000077006F1F767503BDB23CC5A959673E1F767B033A0604ECA71EB3
|
||||||
|
:20778600A192673E1F767B03380603ECA71E673E4076B0B9BE8B060002FE429741961F76AE
|
||||||
|
:2077A6007503379642921F767503369682FE06001F7675033AA806001F7675033CA806005F
|
||||||
|
:0A77C60006000119C356FFFF06007C
|
||||||
|
:2077D0000301000000C017910000179100001791000017910000179100001791000017913D
|
||||||
|
:2077F0000000179100001791000017910000179100001791000017910000A6880000B38820
|
||||||
|
:207810000000C0880000CD8800002B910000E5880000F0880000FB8800000689000011896E
|
||||||
|
:2078300000001C89000027890000328900003D89000048890000538900005E8900006989DC
|
||||||
|
:207850000000748900007F890000A08900002B910000C1890000E2890000018A0000228A42
|
||||||
|
:207870000000458A0000668A0000878A0000A88A0000C98A0000EC8A00000D8B00002B91D9
|
||||||
|
:2078900000002B9100002E8B00004F8B0000728B0000958B0000B68B0000D78B00002B910D
|
||||||
|
:2078B00000002B910000FA8B00001B8C00003E8C00005F8C0000808C0000A18C00002B9126
|
||||||
|
:2078D00000002B910000C28C0000E38C00002B9100002B9100002B9100002B9100002B9173
|
||||||
|
:2078F00000002B910000068D0000278D00004A8D00006B8D00008C8D0000AD8D00002B9197
|
||||||
|
:2079100000002B910000D08D0000F18D0000128E0000338E0000548E0000758E00002B91BE
|
||||||
|
:2079300000002B910000988E0000BB8E00002B9100002B910000DC8E0000FD8E00002B91E3
|
||||||
|
:2079500000002B9100001E8F0000418F0000628F0000838F0000A48F0000C78F0000EA8FD9
|
||||||
|
:2079700000000B9000002B9100002B9100002B9100002B9100002B9100002B9100002B9138
|
||||||
|
:2079900000002B9100002B9100002B9100002B9100002B9100002B9100002B9100002B91F7
|
||||||
|
:2079B00000002B9100002C9000004D9000006E9000008F900000B09000002B910000D390E6
|
||||||
|
:0C79D0000000F490000033000B000A00DF
|
||||||
|
:2079DC002800000004C1E89F000007A0000019A000002EA0000044A0000055A0000069A007
|
||||||
|
:2079FC0000007AA0000095A00000B7A00000CDA00000DEA00000EBA000000CA100001EA1E3
|
||||||
|
:187A1C0000002EA1000041A1000050A1000060A1000076A10000000098
|
||||||
|
:00000001FF
|
||||||
33
bin/ice.map
Normal file
33
bin/ice.map
Normal file
@ -0,0 +1,33 @@
|
|||||||
|
********************************************************************************
|
||||||
|
TMS320C2000 Hex Converter v5.2.1
|
||||||
|
********************************************************************************
|
||||||
|
|
||||||
|
INPUT FILE NAME: <D:\Projects\Ledokol\Docs\UKSS\ICE_19_03_2018\bin\ice.out>
|
||||||
|
OUTPUT FORMAT: Binary
|
||||||
|
|
||||||
|
PHYSICAL MEMORY PARAMETERS
|
||||||
|
Default data width : 16
|
||||||
|
Default memory width : 8 (LS-->MS)
|
||||||
|
Default output width : 8
|
||||||
|
|
||||||
|
BOOT LOADER PARAMETERS
|
||||||
|
Table Type: SERIAL PORT (SCI 8 bit Mode)
|
||||||
|
Entry Point: 0x0000b82b
|
||||||
|
|
||||||
|
|
||||||
|
OUTPUT TRANSLATION MAP
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
00000000..003fffff Page=0 Memory Width=8 ROM Width=8
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
OUTPUT FILES: D:\Projects\Ledokol\Docs\UKSS\ICE_19_03_2018\bin\ice.bin [b0..b7]
|
||||||
|
|
||||||
|
CONTENTS: 00000000..00007a33 BOOT TABLE
|
||||||
|
.cinit : dest=0000b9e2 size=000001f5 width=00000002
|
||||||
|
.text : dest=00008000 size=000039e2 width=00000002
|
||||||
|
.econst : dest=0000c000 size=00000103 width=00000002
|
||||||
|
.switch : dest=0000c104 size=00000028 width=00000002
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*"
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
NO CONTENTS
|
||||||
BIN
bin/ice.out
Normal file
BIN
bin/ice.out
Normal file
Binary file not shown.
450
bios.c
Normal file
450
bios.c
Normal file
@ -0,0 +1,450 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************
|
||||||
|
Bios.c
|
||||||
|
**************************************************************
|
||||||
|
Îñíîâíûå êîììàíäû BIOS *
|
||||||
|
äëà ðàáîòû ñ RS232
|
||||||
|
****************************************************************/
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "bios_dsp.h"
|
||||||
|
#include "crc16.h"
|
||||||
|
#include "spise2p.h"
|
||||||
|
#include "i2c.h"
|
||||||
|
|
||||||
|
//#include "flash_tools.h"
|
||||||
|
//#include "spartan_tools.h"
|
||||||
|
//#include "big_dsp_module.h"
|
||||||
|
|
||||||
|
int flag_DEBUG = false; /* Ôëàã îòëàäî÷íîãî ðåæèìà */
|
||||||
|
|
||||||
|
|
||||||
|
//static unsigned int *RecvPtr;
|
||||||
|
//static int BS_LoadOK = false; /** Ôëàã óñïåøíîñòè ïðèåìà áëîêà */
|
||||||
|
|
||||||
|
/**********************************************************/
|
||||||
|
/* Ïðîòîòèïû ôóíêöèé, èñïîëüçóåìûõ è îïðåäåëåííûõ â ôàéëå */
|
||||||
|
/**********************************************************/
|
||||||
|
//static int _getbyte(int *addr, int offs);
|
||||||
|
|
||||||
|
unsigned int read_memory(unsigned long addr)
|
||||||
|
{
|
||||||
|
return (*(volatile int *)(addr));
|
||||||
|
}
|
||||||
|
|
||||||
|
void write_memory(unsigned long addr, unsigned int data)
|
||||||
|
{
|
||||||
|
(*(volatile int *)( addr )) = data;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */
|
||||||
|
int get_command(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
int cmd;
|
||||||
|
unsigned int crc, rcrc;
|
||||||
|
|
||||||
|
if(rs_arr->RS_DataReady) // Äàííûå ïî RS ïðèøëè
|
||||||
|
{
|
||||||
|
rs_arr->RS_DataReady = false;
|
||||||
|
cmd = rs_arr->RS_Header[1]; // Ïðî÷èòàëè íîìåð êîìàíäû
|
||||||
|
|
||||||
|
// Ïðîâåðàåì äëèíó êîìàíäû äëà ñ÷èòûâàíèà CRC
|
||||||
|
if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH))
|
||||||
|
{
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(cmd == CMD_LOAD) // Åñëè êîìàíäà çàãðóçêè
|
||||||
|
{
|
||||||
|
rs_arr->RS_PrevCmd = cmd;
|
||||||
|
return cmd; // Íåò ïðîâåðêè crc
|
||||||
|
}
|
||||||
|
else // Âñå îñòàëüíûå êîìàíäû
|
||||||
|
{
|
||||||
|
// Ñ÷èòûâàåì crc èç ïîñûëêè
|
||||||
|
crc = (rs_arr->RS_Header[RS_Len[cmd]-1] << 8) |
|
||||||
|
(rs_arr->RS_Header[RS_Len[cmd]-2]) ;
|
||||||
|
}
|
||||||
|
// Ðàññ÷èòûâàåì crc èç ïîñûëêè
|
||||||
|
rcrc = 0xffff;
|
||||||
|
rcrc = get_crc_16( rcrc, rs_arr->RS_Header, (RS_Len[cmd]-2) );
|
||||||
|
|
||||||
|
if(crc == rcrc) // Ïðîâåðàåì crc
|
||||||
|
{
|
||||||
|
rs_arr->RS_PrevCmd = cmd;
|
||||||
|
return cmd;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
} }
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */
|
||||||
|
void Answer(RS_DATA *rs_arr,int n)
|
||||||
|
{
|
||||||
|
int crc;
|
||||||
|
|
||||||
|
flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR;
|
||||||
|
rs_arr->buffer[1] = n;
|
||||||
|
|
||||||
|
crc = 0xffff;
|
||||||
|
crc = get_crc_16( crc, rs_arr->buffer, 2);
|
||||||
|
|
||||||
|
rs_arr->buffer[2] = LOBYTE(crc);
|
||||||
|
rs_arr->buffer[3] = HIBYTE(crc);
|
||||||
|
|
||||||
|
rs_arr->buffer[4] = 0;
|
||||||
|
rs_arr->buffer[5] = 0;
|
||||||
|
RS_Send(rs_arr,rs_arr->buffer, 6);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Âíóòðåííàà ô-öèà */
|
||||||
|
static char _getbyte(unsigned int *addr, int32 offs)
|
||||||
|
{
|
||||||
|
unsigned int *address;
|
||||||
|
unsigned int byte;
|
||||||
|
|
||||||
|
address = addr + offs/2;
|
||||||
|
byte = *address;
|
||||||
|
if(offs%2) return LOBYTE(byte);
|
||||||
|
else return HIBYTE(byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/
|
||||||
|
void init(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
if(rs_arr->RS_Header[2]==3)
|
||||||
|
{
|
||||||
|
if (rs_arr->curr_baud!=57600)
|
||||||
|
{ RS_SetLineSpeed(rs_arr,57600);
|
||||||
|
rs_arr->curr_baud= 57600;
|
||||||
|
} }
|
||||||
|
|
||||||
|
if(rs_arr->RS_Header[2]==4)
|
||||||
|
{
|
||||||
|
if (rs_arr->curr_baud!=115200)
|
||||||
|
{ RS_SetLineSpeed(rs_arr,115200);
|
||||||
|
rs_arr->curr_baud= 115200;
|
||||||
|
} }
|
||||||
|
|
||||||
|
Answer(rs_arr,CMD_INIT);
|
||||||
|
rs_arr->BS_LoadOK = false;
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**@name Êîììàíäû
|
||||||
|
* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë
|
||||||
|
*/
|
||||||
|
//@{
|
||||||
|
|
||||||
|
/** Èíèöèèðîâàòü çàãðóçêó áëîêà.
|
||||||
|
Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */
|
||||||
|
void initload(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned long Address;
|
||||||
|
|
||||||
|
Address = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
rs_arr->RS_Length = rs_arr->RS_Header[9] & 0xFF;
|
||||||
|
rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[8] & 0xFF);
|
||||||
|
rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[7] & 0xFF);
|
||||||
|
rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[6] & 0xFF);
|
||||||
|
|
||||||
|
rs_arr->RS_Length += 2;
|
||||||
|
rs_arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address;
|
||||||
|
rs_arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address;
|
||||||
|
|
||||||
|
Answer(rs_arr,CMD_INITLOAD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Çàãðóçêà áëîêà.
|
||||||
|
Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */
|
||||||
|
void load(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned int rcrc, crc;
|
||||||
|
|
||||||
|
crc = (_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-1) << 8) +
|
||||||
|
_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-2);
|
||||||
|
|
||||||
|
rs_arr->RS_Header[0] = rs_arr->addr_recive;
|
||||||
|
|
||||||
|
// CNTRL_ADDR;
|
||||||
|
rs_arr->RS_Header[1]=CMD_LOAD;
|
||||||
|
|
||||||
|
rcrc = 0xffff;
|
||||||
|
rcrc = get_crc_16( rcrc, rs_arr->RS_Header, 2);
|
||||||
|
rcrc = get_crc_16b( rcrc, rs_arr->pRecvPtr, rs_arr->RS_Length-2);
|
||||||
|
|
||||||
|
if(rcrc == crc)
|
||||||
|
{
|
||||||
|
Answer(rs_arr,CMD_LOAD);
|
||||||
|
rs_arr->BS_LoadOK = true;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rs_arr->BS_LoadOK = false;
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
} }
|
||||||
|
|
||||||
|
/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load
|
||||||
|
@see load */
|
||||||
|
void run (RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ïðî÷èòàòü à÷åéêó ïàìàòè */
|
||||||
|
void peek(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned long Address;
|
||||||
|
unsigned int Data, crc;
|
||||||
|
|
||||||
|
flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà
|
||||||
|
|
||||||
|
Address = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
|
||||||
|
if(Address>=0x20000000)
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFFF;
|
||||||
|
Data = I2CA_ReadData(Address);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
if(Address>=0x10000000)
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFFF;
|
||||||
|
Seeprom_read(Address,(unsigned int *)&Data,2);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFFF;
|
||||||
|
Data = read_memory(Address);
|
||||||
|
}
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR;
|
||||||
|
rs_arr->buffer[1] = CMD_PEEK;
|
||||||
|
|
||||||
|
rs_arr->buffer[2] = LOBYTE(Data);
|
||||||
|
rs_arr->buffer[3] = HIBYTE(Data);
|
||||||
|
|
||||||
|
rs_arr->buffer[4] = 0;//LOBYTE(CpuTimer2.InterruptCount);
|
||||||
|
rs_arr->buffer[5] = 0;//HIBYTE(CpuTimer2.InterruptCount);
|
||||||
|
|
||||||
|
crc = 0xffff;
|
||||||
|
crc = get_crc_16(crc, rs_arr->buffer, 6);
|
||||||
|
|
||||||
|
rs_arr->buffer[6] = LOBYTE(crc);
|
||||||
|
rs_arr->buffer[7] = HIBYTE(crc);
|
||||||
|
rs_arr->buffer[8] = 0;
|
||||||
|
rs_arr->buffer[9] = 0;
|
||||||
|
|
||||||
|
RS_Send(rs_arr,rs_arr->buffer, 10);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Çàïèñàòü â à÷åéêó ïàìàòè */
|
||||||
|
void poke(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned long Address;
|
||||||
|
unsigned int Data;
|
||||||
|
|
||||||
|
Address = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
Data = 0;
|
||||||
|
Data = (Data<<8) | (rs_arr->RS_Header[7] & 0xFF);
|
||||||
|
Data = (Data<<8) | (rs_arr->RS_Header[6] & 0xFF);
|
||||||
|
|
||||||
|
if(Address>=0x2000000)
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFF;
|
||||||
|
I2CA_WriteData(Address,Data);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
if(Address>=0x1000000)
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFF;
|
||||||
|
Seeprom_write(Address,(unsigned int *)&Data,2);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Address&=0xFFFFFF;
|
||||||
|
write_memory(Address,Data);
|
||||||
|
}
|
||||||
|
|
||||||
|
Answer(rs_arr,CMD_POKE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ïåðåäàòü áëîê ïàìàòè */
|
||||||
|
void upload(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
int32 Address, Length, crc;
|
||||||
|
|
||||||
|
flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà
|
||||||
|
// stopp=1;
|
||||||
|
|
||||||
|
Address = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
Length = rs_arr->RS_Header[9] & 0xFF;
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[8] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[7] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[6] & 0xFF);
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR;
|
||||||
|
rs_arr->buffer[1] = CMD_UPLOAD;
|
||||||
|
|
||||||
|
crc = 0xffff;
|
||||||
|
crc = get_crc_16( crc, rs_arr->buffer, 2);
|
||||||
|
crc = get_crc_16b( crc, (unsigned int *)Address, Length);
|
||||||
|
|
||||||
|
RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = CMD_UPLOAD;
|
||||||
|
RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó
|
||||||
|
|
||||||
|
RS_Wait4OK(rs_arr);
|
||||||
|
RS_BSend(rs_arr,(unsigned int*)Address, Length);
|
||||||
|
RS_Wait4OK(rs_arr);
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = LOBYTE(crc);
|
||||||
|
rs_arr->buffer[1] = HIBYTE(crc);
|
||||||
|
rs_arr->buffer[2] = 0;
|
||||||
|
rs_arr->buffer[3] = 0;
|
||||||
|
RS_Send(rs_arr,rs_arr->buffer, 4+2);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ïðîøèòü XILINX.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load,
|
||||||
|
òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè
|
||||||
|
@see load */
|
||||||
|
void xflash(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ïðîøèòü TMS.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load
|
||||||
|
@see load */
|
||||||
|
void tflash(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
// volatile unsigned long Address1,Address2;
|
||||||
|
// volatile unsigned long Length, LengthW;
|
||||||
|
/*
|
||||||
|
if(!rs_arr->BS_LoadOK)
|
||||||
|
{
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Address1 = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
Address2 = rs_arr->RS_Header[9] & 0xFF;
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF);
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF);
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF);
|
||||||
|
|
||||||
|
Length = rs_arr->RS_Header[13] & 0xFF;
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF);
|
||||||
|
|
||||||
|
LengthW = Length/2;
|
||||||
|
if (LengthW*2<Length) LengthW++;
|
||||||
|
|
||||||
|
if( (Address2 < 0x100000) || (Address2 > 0x180000) || ((Address2+LengthW) > 0x180000) )
|
||||||
|
{
|
||||||
|
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||||
|
RS_SetBitMode(rs_arr,9);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
run_flash_data(Address1,Address2, LengthW );
|
||||||
|
|
||||||
|
Answer(rs_arr,CMD_TFLASH);
|
||||||
|
*/
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Ïðîøèòü TMS.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load
|
||||||
|
@see load */
|
||||||
|
void extendbios(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
volatile unsigned long Address1,Address2,Length;
|
||||||
|
unsigned int code;
|
||||||
|
|
||||||
|
Address1 = rs_arr->RS_Header[5] & 0xFF;
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF);
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF);
|
||||||
|
Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF);
|
||||||
|
|
||||||
|
Address2 = rs_arr->RS_Header[9] & 0xFF;
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF);
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF);
|
||||||
|
Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF);
|
||||||
|
|
||||||
|
Length = rs_arr->RS_Header[13] & 0xFF;
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF);
|
||||||
|
Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF);
|
||||||
|
|
||||||
|
code=rs_arr->RS_Header[14] & 0xFF;
|
||||||
|
|
||||||
|
switch ( code )
|
||||||
|
{
|
||||||
|
// Ïðîøèâàåì EPROM Èç RAM
|
||||||
|
case 4: Seeprom_write(Address1,(unsigned int*)Address2,Length);
|
||||||
|
break;
|
||||||
|
// ×èòàåì èç EPROM â RAM
|
||||||
|
case 5: Seeprom_read(Address1,(unsigned int*)Address2,Length);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Answer(rs_arr,CMD_EXTEND);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
//@}
|
||||||
120
bios_dsp.h
Normal file
120
bios_dsp.h
Normal file
@ -0,0 +1,120 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************/
|
||||||
|
/* Bios_dsp.h */
|
||||||
|
/****************************************************************/
|
||||||
|
/* Îñíîâíûå êîììàíäû BIOS */
|
||||||
|
/****************************************************************/
|
||||||
|
#ifndef _BIOS_DSP
|
||||||
|
#define _BIOS_DSP
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define BM_PACKED 1
|
||||||
|
#define BM_CHAR32 0
|
||||||
|
|
||||||
|
#define CHIEF 1
|
||||||
|
#define SLAVE 0
|
||||||
|
|
||||||
|
#define ADR_FOR_SPECIAL 0x100
|
||||||
|
#define CMD_MODBUS_3 3
|
||||||
|
#define ANS_MODBUS_3 4
|
||||||
|
#define CMD_MODBUS_15 5
|
||||||
|
#define CMD_MODBUS_6 6
|
||||||
|
#define ANS_MODBUS_6 7
|
||||||
|
#define CMD_MODBUS_16 16
|
||||||
|
/*
|
||||||
|
|
||||||
|
CMD_MODBUS_3 = 3,
|
||||||
|
ANS_MODBUS_3 = 4,
|
||||||
|
CMD_MODBUS_15 = 5,
|
||||||
|
CMD_MODBUS_6 = 6,
|
||||||
|
ANS_MODBUS_6 = 7,
|
||||||
|
CMD_MODBUS_16 = 16,
|
||||||
|
*/
|
||||||
|
enum {
|
||||||
|
CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH,
|
||||||
|
CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND,
|
||||||
|
|
||||||
|
CMD_VECTOR=61,
|
||||||
|
CMD_IMPULSE,
|
||||||
|
/* ñòàíäàðòíûå êîìàíäû */
|
||||||
|
CMD_STD=65, CMD_STD_ANS
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {false=0, true};
|
||||||
|
|
||||||
|
|
||||||
|
/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */
|
||||||
|
int get_command(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */
|
||||||
|
void Answer(RS_DATA *rs_arr,int n);
|
||||||
|
|
||||||
|
/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/
|
||||||
|
void init(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/**@name Êîììàíäû
|
||||||
|
* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë*/
|
||||||
|
//@{
|
||||||
|
|
||||||
|
/** Èíèöèèðîâàòü çàãðóçêó áëîêà.
|
||||||
|
Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */
|
||||||
|
void initload(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Çàãðóçêà áëîêà.
|
||||||
|
Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */
|
||||||
|
void load(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load
|
||||||
|
@see load */
|
||||||
|
void run (RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Ïðî÷èòàòü à÷åéêó ïàìàòè */
|
||||||
|
void peek(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Çàïèñàòü â à÷åéêó ïàìàòè */
|
||||||
|
void poke(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Ïåðåäàòü áëîê ïàìàòè */
|
||||||
|
void upload(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Ïðîøèòü XILINX.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load,
|
||||||
|
òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè
|
||||||
|
@see load */
|
||||||
|
void xflash(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
/** Ïðîøèòü TMS.
|
||||||
|
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
|
||||||
|
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
|
||||||
|
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load
|
||||||
|
@see load */
|
||||||
|
void tflash(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
|
||||||
|
/* ðàñøèðåííûå êîìàíäû äëà áèîñà */
|
||||||
|
void extendbios(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
|
||||||
|
void write_memory(unsigned long addr, unsigned int data);
|
||||||
|
unsigned int read_memory(unsigned long addr);
|
||||||
|
|
||||||
|
|
||||||
|
//@}
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif/* _BIOS_DSP */
|
||||||
3
cc_build_Debug.log
Normal file
3
cc_build_Debug.log
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
------------------------------ ice.pjt - Debug ------------------------------
|
||||||
|
Build Complete,
|
||||||
|
0 Errors, 0 Warnings, 0 Remarks.
|
||||||
43
cntrl_adr.c
Normal file
43
cntrl_adr.c
Normal file
@ -0,0 +1,43 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************
|
||||||
|
cntrl_adr.c
|
||||||
|
****************************************************************
|
||||||
|
* Àäðåñ êîíòðîëëåðà *
|
||||||
|
****************************************************************/
|
||||||
|
|
||||||
|
#include "cntrl_adr.h"
|
||||||
|
|
||||||
|
#define ADDR_FOR_ALL_DEF 10
|
||||||
|
#define ADDR_ANSWER_DEF 0x33
|
||||||
|
#define ADDR_TERMINAL_DEF 11
|
||||||
|
#define ADDR_UNIVERSAL_DEF 10
|
||||||
|
|
||||||
|
|
||||||
|
/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */
|
||||||
|
int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF;
|
||||||
|
|
||||||
|
/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè îòâåòà */
|
||||||
|
const int ADDR_ANSWER = ADDR_ANSWER_DEF;
|
||||||
|
|
||||||
|
/** Óñòàíîâêà àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */
|
||||||
|
const int ADDR_TERMINAL = ADDR_TERMINAL_DEF;
|
||||||
|
|
||||||
|
/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */
|
||||||
|
const int CNTRL_ADDR_UNIVERSAL=ADDR_UNIVERSAL_DEF;
|
||||||
|
|
||||||
|
/* Àäðåñ êîíòðîëëåðà */
|
||||||
|
int CNTRL_ADDR=1;
|
||||||
|
|
||||||
|
int cntr_addr_c;
|
||||||
|
int cntr_addr_c_all;
|
||||||
|
|
||||||
|
/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */
|
||||||
|
void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all)
|
||||||
|
{
|
||||||
|
CNTRL_ADDR = cntrl_addr;
|
||||||
|
ADDR_FOR_ALL = cntrl_addr_for_all;
|
||||||
|
}
|
||||||
|
|
||||||
44
cntrl_adr.h
Normal file
44
cntrl_adr.h
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||||
|
/****************************************************************
|
||||||
|
cntrl_adr.h
|
||||||
|
****************************************************************
|
||||||
|
* Àäðåñ êîíòðîëëåðà *
|
||||||
|
****************************************************************/
|
||||||
|
|
||||||
|
#ifndef _CNTRL_ADR
|
||||||
|
#define _CNTRL_ADR
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */
|
||||||
|
extern int ADDR_FOR_ALL;
|
||||||
|
|
||||||
|
/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè îòâåòà */
|
||||||
|
extern const int ADDR_ANSWER;
|
||||||
|
|
||||||
|
/** àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */
|
||||||
|
extern const int ADDR_TERMINAL;
|
||||||
|
|
||||||
|
/* Àäðåñ êîíòðîëëåðà */
|
||||||
|
extern int CNTRL_ADDR;
|
||||||
|
|
||||||
|
/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */
|
||||||
|
extern const int CNTRL_ADDR_UNIVERSAL;
|
||||||
|
|
||||||
|
/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */
|
||||||
|
void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all);
|
||||||
|
|
||||||
|
|
||||||
|
extern int cntr_addr_c;
|
||||||
|
extern int cntr_addr_c_all;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _CNTRL_ADR */
|
||||||
221
crc16.c
Normal file
221
crc16.c
Normal file
@ -0,0 +1,221 @@
|
|||||||
|
#include "crc16.h"
|
||||||
|
#define MAKE_TABS 0 /* Builds tables below */
|
||||||
|
#define FAST_CRC 1 /* If fast CRC should be used */
|
||||||
|
#define ONLY_CRC16 1
|
||||||
|
|
||||||
|
#define Poln 0xA001
|
||||||
|
|
||||||
|
|
||||||
|
#if FAST_CRC & !MAKE_TABS
|
||||||
|
|
||||||
|
#if !ONLY_CRC16
|
||||||
|
|
||||||
|
static WORD crc_ccitt_tab[] = {
|
||||||
|
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
|
||||||
|
0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
|
||||||
|
0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
|
||||||
|
0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
|
||||||
|
0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
|
||||||
|
0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
|
||||||
|
0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
|
||||||
|
0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
|
||||||
|
0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
|
||||||
|
0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
|
||||||
|
0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
|
||||||
|
0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
|
||||||
|
0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
|
||||||
|
0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
|
||||||
|
0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
|
||||||
|
0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
|
||||||
|
0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
|
||||||
|
0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
|
||||||
|
0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
|
||||||
|
0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
|
||||||
|
0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
|
||||||
|
0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
|
||||||
|
0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
|
||||||
|
0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
|
||||||
|
0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
|
||||||
|
0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
|
||||||
|
0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
|
||||||
|
0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
|
||||||
|
0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
|
||||||
|
0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
|
||||||
|
0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
|
||||||
|
0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WORD crc_16_tab[] = {
|
||||||
|
0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241,
|
||||||
|
0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440,
|
||||||
|
0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40,
|
||||||
|
0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841,
|
||||||
|
0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40,
|
||||||
|
0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41,
|
||||||
|
0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641,
|
||||||
|
0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040,
|
||||||
|
0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240,
|
||||||
|
0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441,
|
||||||
|
0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41,
|
||||||
|
0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840,
|
||||||
|
0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41,
|
||||||
|
0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40,
|
||||||
|
0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640,
|
||||||
|
0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041,
|
||||||
|
0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240,
|
||||||
|
0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441,
|
||||||
|
0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41,
|
||||||
|
0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840,
|
||||||
|
0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41,
|
||||||
|
0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40,
|
||||||
|
0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640,
|
||||||
|
0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041,
|
||||||
|
0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241,
|
||||||
|
0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440,
|
||||||
|
0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40,
|
||||||
|
0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841,
|
||||||
|
0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40,
|
||||||
|
0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41,
|
||||||
|
0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641,
|
||||||
|
0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if !ONLY_CRC16
|
||||||
|
|
||||||
|
/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */
|
||||||
|
/* are sent MSB to LSB. */
|
||||||
|
unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size )
|
||||||
|
{
|
||||||
|
#if !(FAST_CRC & !MAKE_TABS)
|
||||||
|
register int i;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
while (size--) {
|
||||||
|
#if FAST_CRC & !MAKE_TABS
|
||||||
|
crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ];
|
||||||
|
#else
|
||||||
|
crc ^= (WORD)(*buf++) << 8;
|
||||||
|
for (i = 0; i < 8; i++) {
|
||||||
|
if (crc & 0x8000)
|
||||||
|
crc = (crc << 1) ^ 0x1021;
|
||||||
|
else
|
||||||
|
crc <<= 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
} return crc;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */
|
||||||
|
/* sent LSB to MSB. */
|
||||||
|
unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size )
|
||||||
|
{
|
||||||
|
#if !(FAST_CRC & !MAKE_TABS)
|
||||||
|
register unsigned int i;
|
||||||
|
register unsigned int ch;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
while (size--) {
|
||||||
|
#if FAST_CRC & !MAKE_TABS
|
||||||
|
|
||||||
|
crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ];
|
||||||
|
crc = crc & 0xffff;
|
||||||
|
#else
|
||||||
|
ch = *buf++;
|
||||||
|
for (i = 0; i < 8; i++) {
|
||||||
|
if ((crc ^ ch) & 1)
|
||||||
|
crc = (crc >> 1) ^ 0xa001;
|
||||||
|
else
|
||||||
|
crc >>= 1;
|
||||||
|
ch >>= 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
} return (crc & 0xffff);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size )
|
||||||
|
{
|
||||||
|
|
||||||
|
unsigned int x, dword, byte;
|
||||||
|
unsigned long i;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
for (i = 0; i < size; i++)
|
||||||
|
{
|
||||||
|
x = i % 2;
|
||||||
|
|
||||||
|
dword = buf[i/2];
|
||||||
|
// dword = *buf;
|
||||||
|
|
||||||
|
|
||||||
|
if (x == 0)
|
||||||
|
{
|
||||||
|
byte = ((dword >> 8)&0xFF);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (x == 1)
|
||||||
|
{
|
||||||
|
byte = (dword & 0xFF);
|
||||||
|
}
|
||||||
|
|
||||||
|
crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ];
|
||||||
|
crc = crc & 0xffff;
|
||||||
|
|
||||||
|
// crc = crc + ((byte) & 0xff);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
return (crc & 0xffff);
|
||||||
|
}
|
||||||
|
|
||||||
|
int get_crc16(unsigned int *buf, int size )
|
||||||
|
{
|
||||||
|
unsigned int crc16,i,j;
|
||||||
|
|
||||||
|
|
||||||
|
crc16=0xFFFF;
|
||||||
|
for(i=0;i<size;i++)
|
||||||
|
{
|
||||||
|
crc16=crc16^(buf[i]&0xFF);
|
||||||
|
for (j=0;j<8;j++)
|
||||||
|
if(crc16&1) crc16=(crc16>>1)^Poln;
|
||||||
|
else crc16=crc16>>1;
|
||||||
|
|
||||||
|
crc16=crc16^((buf[i]>>8)&0xFF);
|
||||||
|
for (j=0;j<8;j++)
|
||||||
|
if(crc16&1) crc16=(crc16>>1)^Poln;
|
||||||
|
else crc16=crc16>>1;
|
||||||
|
}
|
||||||
|
return crc16;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned int get_crc32(unsigned long *num)
|
||||||
|
{
|
||||||
|
volatile unsigned long crc32,key, num_vol;
|
||||||
|
num_vol = *num;
|
||||||
|
|
||||||
|
int i;
|
||||||
|
|
||||||
|
crc32 = 0xFF000000 | (num_vol >> 8);
|
||||||
|
|
||||||
|
for(i=0;i<32;i++)
|
||||||
|
{
|
||||||
|
key = crc32 & 0x80000000;
|
||||||
|
if(key) key = 0x31000000; // 00110001
|
||||||
|
|
||||||
|
crc32 = (crc32<<1) ^key;
|
||||||
|
}
|
||||||
|
|
||||||
|
crc32 = ((crc32 >> 24) & 0x000000FF) | (num_vol & 0xFFFFFF00);
|
||||||
|
|
||||||
|
if (crc32 == num_vol) return 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
10
crc16.h
Normal file
10
crc16.h
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
typedef unsigned short WORD;
|
||||||
|
typedef unsigned char byte;
|
||||||
|
|
||||||
|
|
||||||
|
unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size );
|
||||||
|
unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size );
|
||||||
|
unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size );
|
||||||
|
int get_crc16(unsigned int *buf, int size );
|
||||||
|
|
||||||
|
unsigned int get_crc32(unsigned long *num);
|
||||||
5
create_rs.bat
Normal file
5
create_rs.bat
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
set iname=debug\lampa
|
||||||
|
set oname=bin\lampa
|
||||||
|
|
||||||
|
d:\CCStudio_v3.3\C2000\cgtools\bin\hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i
|
||||||
|
d:\CCStudio_v3.3\C2000\cgtools\bin\hex2bin %oname%.hex %oname%.bin
|
||||||
355
ecan.c
Normal file
355
ecan.c
Normal file
@ -0,0 +1,355 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "package.h" // DSP281x Headerfile Include File
|
||||||
|
#include "peripher.h" // DSP281x Headerfile Include File
|
||||||
|
|
||||||
|
#include "ecan.h" // DSP281x Headerfile Include File
|
||||||
|
#include "tools.h" // DSP281x Headerfile Include File
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "message.h"
|
||||||
|
|
||||||
|
|
||||||
|
// Prototype statements for functions found within this file.
|
||||||
|
interrupt void CANa_handler(void);
|
||||||
|
interrupt void CANa_reset_err(void);
|
||||||
|
interrupt void CANb_handler(void);
|
||||||
|
interrupt void CANb_reset_err(void);
|
||||||
|
|
||||||
|
// Global variable for this example
|
||||||
|
Uint32 ErrorCount;
|
||||||
|
Uint32 MessageReceivedCount;
|
||||||
|
Uint32 MessageTransivedCount=0;
|
||||||
|
|
||||||
|
Uint32 TestMbox1 = 0;
|
||||||
|
Uint32 TestMbox2 = 0;
|
||||||
|
Uint32 TestMbox3 = 0;
|
||||||
|
|
||||||
|
int CanTimeOutErrorTR = 0;
|
||||||
|
|
||||||
|
int wait=0;
|
||||||
|
|
||||||
|
void Init_Can(int Port, int DevNum)
|
||||||
|
{
|
||||||
|
struct ECAN_REGS ECanShadow;
|
||||||
|
|
||||||
|
volatile struct ECAN_REGS * ECanRegs;
|
||||||
|
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||||
|
volatile struct MOTO_REGS * ECanMOTORegs;
|
||||||
|
|
||||||
|
long id = 0x801CE000;
|
||||||
|
|
||||||
|
if(DevNum<0)DevNum=0;
|
||||||
|
if(DevNum>15)DevNum=15;
|
||||||
|
|
||||||
|
// Configure CAN pins using GPIO regs here
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
if(!Port)
|
||||||
|
{
|
||||||
|
ECanRegs = &ECanaRegs;
|
||||||
|
ECanMboxes = &ECanaMboxes;
|
||||||
|
ECanMOTORegs = &ECanaMOTORegs;
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ECanRegs = &ECanbRegs;
|
||||||
|
ECanMboxes = &ECanbMboxes;
|
||||||
|
ECanMOTORegs = &ECanbMOTORegs;
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Configure the eCAN RX and TX pins for eCAN transmissions
|
||||||
|
ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant
|
||||||
|
ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant
|
||||||
|
|
||||||
|
// Specify that 8 bits will be sent/received
|
||||||
|
ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008;
|
||||||
|
ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008;
|
||||||
|
ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008;
|
||||||
|
|
||||||
|
// Disable all Mailboxes
|
||||||
|
// Required before writing the MSGIDs
|
||||||
|
ECanRegs->CANME.all = 0;
|
||||||
|
|
||||||
|
// çàäàåì àäðåñ 0 àùèêa íà ïåðåäà÷ó
|
||||||
|
ECanMboxes->MBOX0.MSGID.all = id + DevNum;
|
||||||
|
|
||||||
|
// çàäàåì àäðåñ 1 àùèêa íà ïðèåì
|
||||||
|
ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum;
|
||||||
|
|
||||||
|
// çàäàåì àäðåñ 2 àùèêa íà ïðèåì
|
||||||
|
ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1);
|
||||||
|
|
||||||
|
// çàäàåì ðåæèìû ðàáîòû àùèêa 0 íà ïåðåäà÷ó, îñòàëüíûå íà ïðèåì
|
||||||
|
ECanRegs->CANMD.all = 0xFFFFFFFE;
|
||||||
|
|
||||||
|
// âûáèðàåì òîëüêî 3 àùèêa äëà ðàáîòû, îñòàëüíûå çàïðåùàåì
|
||||||
|
ECanRegs->CANME.all = 0x00000007;
|
||||||
|
|
||||||
|
// Clear all TAn bits
|
||||||
|
ECanRegs->CANTA.all = 0xFFFFFFFF;
|
||||||
|
// Clear all RMPn bits
|
||||||
|
ECanRegs->CANRMP.all = 0xFFFFFFFF;
|
||||||
|
// Clear all interrupt flag bits
|
||||||
|
ECanRegs->CANGIF0.all = 0xFFFFFFFF;
|
||||||
|
ECanRegs->CANGIF1.all = 0xFFFFFFFF;
|
||||||
|
// Clear all error and status bits
|
||||||
|
ECanRegs->CANES.all=0xffffffff;
|
||||||
|
|
||||||
|
// Request permission to change the configuration registers
|
||||||
|
ECanShadow.CANMC.all = 0;
|
||||||
|
ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit
|
||||||
|
ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit
|
||||||
|
ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
|
||||||
|
ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity
|
||||||
|
ECanShadow.CANMC.bit.ABO = 1; // Auto bus on
|
||||||
|
ECanShadow.CANMC.bit.CCR = 1;
|
||||||
|
// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back
|
||||||
|
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||||
|
while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set..
|
||||||
|
|
||||||
|
// íàñòðèâàåì ñêîðîñòü CAN
|
||||||
|
ECanShadow.CANBTC.all = ECanRegs->CANBTC.all;
|
||||||
|
ECanShadow.CANBTC.bit.BRPREG = 14;//49; // (BRPREG + 1) = 10 feeds a 15 MHz CAN clock
|
||||||
|
ECanShadow.CANBTC.bit.TSEG2REG = 2; // to the CAN module. (150 / 10 = 15)
|
||||||
|
ECanShadow.CANBTC.bit.TSEG1REG = 15;//10; // Bit time = 15
|
||||||
|
ECanShadow.CANBTC.bit.SJWREG=1;
|
||||||
|
// 14,2,15 äë¤ äîáðûõ ëþäåé. 49 2 10 for 745
|
||||||
|
|
||||||
|
ECanRegs->CANBTC.all = ECanShadow.CANBTC.all;
|
||||||
|
ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0
|
||||||
|
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||||
|
while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared..
|
||||||
|
|
||||||
|
// çàäàåì òàéìàóòû äëà îæèäàíèà îòïðàâêè ïîëó÷åíèà ïîñûëêè
|
||||||
|
ECanMOTORegs->MOTO0 = 550000;
|
||||||
|
ECanMOTORegs->MOTO1 = 550000;
|
||||||
|
|
||||||
|
ECanRegs->CANTOC.all = 1;
|
||||||
|
ECanRegs->CANTOS.all = 0; // clear all time-out flags
|
||||||
|
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||||
|
|
||||||
|
ECanShadow.CANGIM.all = 0;
|
||||||
|
|
||||||
|
ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1
|
||||||
|
ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0.
|
||||||
|
ECanShadow.CANGIM.bit.I0EN = 1;
|
||||||
|
|
||||||
|
ECanShadow.CANGIM.bit.MTOM = 1;
|
||||||
|
ECanShadow.CANGIM.bit.I1EN = 1;
|
||||||
|
ECanShadow.CANGIM.bit.GIL = 1;
|
||||||
|
ECanRegs->CANGIM.all = ECanShadow.CANGIM.all;
|
||||||
|
|
||||||
|
if(!Port)
|
||||||
|
{
|
||||||
|
PieVectTable.ECAN0INTA = &CANa_handler;
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6
|
||||||
|
PieVectTable.ECAN1INTA = &CANa_reset_err;
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PieVectTable.ECAN0INTB = &CANb_handler;
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6
|
||||||
|
PieVectTable.ECAN1INTB = &CANb_reset_err;
|
||||||
|
PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6
|
||||||
|
}
|
||||||
|
IER |= M_INT9; // Enable CPU INT
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
// çàâåðøèëè íàñòðîéêó CAN àùèêîâ
|
||||||
|
|
||||||
|
MessageReceivedCount = 0;
|
||||||
|
ErrorCount = 0;
|
||||||
|
CanTimeOutErrorTR=0;
|
||||||
|
MessageTransivedCount=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void CAN_send(int Port, int data[], int Addr)
|
||||||
|
{
|
||||||
|
unsigned long hiword,loword;
|
||||||
|
volatile struct ECAN_REGS * ECanRegs;
|
||||||
|
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||||
|
|
||||||
|
if(!Port)
|
||||||
|
{
|
||||||
|
ECanRegs = &ECanaRegs;
|
||||||
|
ECanMboxes = &ECanaMboxes;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#ifdef TUBER
|
||||||
|
ECanRegs = &ECanbRegs;
|
||||||
|
ECanMboxes = &ECanbMboxes;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
if(wait)
|
||||||
|
if(!(ECanRegs->CANTA.all & 1))
|
||||||
|
if(!(ECanRegs->CANAA.all & 1))
|
||||||
|
return;
|
||||||
|
|
||||||
|
ECanRegs->CANTA.all = 1;
|
||||||
|
ECanRegs->CANAA.all = 1;
|
||||||
|
|
||||||
|
hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 |
|
||||||
|
((((Uint32)data[Addr ]) & 0xffff) );
|
||||||
|
loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)|
|
||||||
|
((((Uint32)data[Addr+2]) & 0xffff) );
|
||||||
|
|
||||||
|
ECanMboxes->MBOX0.MDH.all = hiword;
|
||||||
|
ECanMboxes->MBOX0.MDL.all = loword;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
ECanRegs->CANTRS.all = 1; // çàïóñòèòü ïåðåäà÷ó
|
||||||
|
|
||||||
|
wait=1;
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1;
|
||||||
|
if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1;
|
||||||
|
if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;
|
||||||
|
// led1_toggle();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void Handlai(volatile struct MBOX * ECanMbox)
|
||||||
|
{
|
||||||
|
unsigned int adr;
|
||||||
|
unsigned int bit[3];
|
||||||
|
unsigned long hiword,loword;
|
||||||
|
int Data[3];
|
||||||
|
|
||||||
|
hiword = ECanMbox->MDH.all;
|
||||||
|
loword = ECanMbox->MDL.all;
|
||||||
|
|
||||||
|
adr = (hiword >> 16);
|
||||||
|
|
||||||
|
bit[0] = adr & 0x8000;
|
||||||
|
bit[1] = adr & 0x4000;
|
||||||
|
bit[2] = adr & 0x2000;
|
||||||
|
|
||||||
|
adr &= 0x1fff;
|
||||||
|
|
||||||
|
Data[0] = (hiword ) & 0xffff;
|
||||||
|
Data[1] = (loword>>16) & 0xffff;
|
||||||
|
Data[2] = (loword ) & 0xffff;
|
||||||
|
|
||||||
|
if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++;
|
||||||
|
if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++;
|
||||||
|
if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2];
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1;
|
||||||
|
else
|
||||||
|
led2_toggle();
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void CANa_handler(void)
|
||||||
|
{
|
||||||
|
unsigned long mask=1;
|
||||||
|
int box;
|
||||||
|
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
box = ECanaRegs.CANGIF0.bit.MIV0;
|
||||||
|
mask <<= box;
|
||||||
|
ECanaRegs.CANRMP.all = mask;
|
||||||
|
|
||||||
|
Handlai(&ECanaMboxes.MBOX0 + box);
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void CANa_reset_err(void)
|
||||||
|
{
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
ECanaRegs.CANTRR.all = 1;
|
||||||
|
CanTimeOutErrorTR++;
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void CANb_handler(void)
|
||||||
|
{
|
||||||
|
#ifdef TUBER
|
||||||
|
unsigned long mask=1;
|
||||||
|
int box;
|
||||||
|
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
box = ECanbRegs.CANGIF0.bit.MIV0;
|
||||||
|
mask <<= box;
|
||||||
|
ECanbRegs.CANRMP.all = mask;
|
||||||
|
|
||||||
|
Handlai(&ECanbMboxes.MBOX0 + box);
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void CANb_reset_err(void)
|
||||||
|
{
|
||||||
|
#ifdef TUBER
|
||||||
|
// Set interrupt priority:
|
||||||
|
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||||
|
IER |= M_INT9;
|
||||||
|
IER &= MINT9; // Set "global" priority
|
||||||
|
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
|
||||||
|
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||||
|
EINT;
|
||||||
|
|
||||||
|
ECanbRegs.CANTRR.all = 1;
|
||||||
|
CanTimeOutErrorTR++;
|
||||||
|
|
||||||
|
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||||
|
|
||||||
|
// Restore registers saved:
|
||||||
|
DINT;
|
||||||
|
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// No more.
|
||||||
|
//===========================================================================
|
||||||
3
ecan.h
Normal file
3
ecan.h
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
void Init_Can(int Port, int DevNum);
|
||||||
|
void CAN_send(int Port, int data[], int Addr);
|
||||||
|
extern int CAN_input_data[];
|
||||||
19
filter_bat2.c
Normal file
19
filter_bat2.c
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
#include "filter_bat2.h"
|
||||||
|
|
||||||
|
float filterbat(FILTERBAT *b, float InpVarCurr)
|
||||||
|
{
|
||||||
|
float y;
|
||||||
|
|
||||||
|
y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) +
|
||||||
|
(b->k_1 * b->u_0) + (b->k_2 * b->u_1);
|
||||||
|
|
||||||
|
b->u_1=b->u_0;
|
||||||
|
b->u_0=y;
|
||||||
|
b->i_1=b->i_0;
|
||||||
|
b->i_0=InpVarCurr;
|
||||||
|
|
||||||
|
return y;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
49
filter_bat2.h
Normal file
49
filter_bat2.h
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
#ifndef _FILTER_BAT2
|
||||||
|
#define _FILTER_BAT2
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define K1_FILTER_BATTER2_1HZ 0.0000096
|
||||||
|
#define K2_FILTER_BATTER2_1HZ 1.94468056
|
||||||
|
#define K3_FILTER_BATTER2_1HZ -0.94471895
|
||||||
|
|
||||||
|
#define K1_FILTER_BATTER2_3HZ 0.00008766
|
||||||
|
#define K2_FILTER_BATTER2_3HZ 1.97347532
|
||||||
|
#define K3_FILTER_BATTER2_3HZ -0.97382594
|
||||||
|
|
||||||
|
#define K1_FILTER_BATTER2_5HZ 0.00024135
|
||||||
|
#define K2_FILTER_BATTER2_5HZ 1.95581276
|
||||||
|
#define K3_FILTER_BATTER2_5HZ -0.95677816
|
||||||
|
|
||||||
|
#define K1_FILTER_BATTER2_10HZ 0.00094411
|
||||||
|
#define K2_FILTER_BATTER2_10HZ 1.91126422
|
||||||
|
#define K3_FILTER_BATTER2_10HZ -0.91504065
|
||||||
|
|
||||||
|
typedef struct { float k_0;
|
||||||
|
float k_1;
|
||||||
|
float k_2;
|
||||||
|
float i_0;
|
||||||
|
float i_1;
|
||||||
|
float i_2;
|
||||||
|
float u_0;
|
||||||
|
float u_1;
|
||||||
|
float u_2;
|
||||||
|
} FILTERBAT;
|
||||||
|
|
||||||
|
|
||||||
|
#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \
|
||||||
|
K2_FILTER_BATTER2_5HZ, \
|
||||||
|
K3_FILTER_BATTER2_5HZ, \
|
||||||
|
0,0,0,0,0,0}
|
||||||
|
|
||||||
|
float filterbat(FILTERBAT *b, float InpVarCurr);
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _FILTER_BAT2 */
|
||||||
|
|
||||||
142
i2c.c
Normal file
142
i2c.c
Normal file
@ -0,0 +1,142 @@
|
|||||||
|
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
|
||||||
|
#include "i2c.h" // Device Headerfile and Examples Include File
|
||||||
|
|
||||||
|
void InitI2CGpio()
|
||||||
|
{
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
|
||||||
|
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
|
||||||
|
|
||||||
|
/* Set qualification for selected pins to asynch only */
|
||||||
|
// This will select asynch (no qualification) for the selected pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
|
||||||
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
|
||||||
|
|
||||||
|
/* Configure SCI pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be I2C functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
|
||||||
|
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void I2CA_Init(void)
|
||||||
|
{
|
||||||
|
InitI2CGpio();
|
||||||
|
|
||||||
|
// Initialize I2C
|
||||||
|
I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code
|
||||||
|
|
||||||
|
I2caRegs.I2CMDR.bit.IRS = 0; // IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR).
|
||||||
|
#if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT
|
||||||
|
I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz)
|
||||||
|
#endif
|
||||||
|
#if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT
|
||||||
|
I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
|
||||||
|
I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
|
||||||
|
|
||||||
|
I2caRegs.I2CMDR.all = 0x0000;
|
||||||
|
|
||||||
|
I2caRegs.I2CMDR.bit.MST = 1;
|
||||||
|
|
||||||
|
I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset
|
||||||
|
// Stop I2C when suspended
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
Uint16 I2CA_WriteData(unsigned int Addr, int Data)
|
||||||
|
{
|
||||||
|
|
||||||
|
// Wait until the STP bit is cleared from any previous master communication.
|
||||||
|
// Clearing of this bit by the module is delayed until after the SCD bit is
|
||||||
|
// set. If this bit is not checked prior to initiating a new message, the
|
||||||
|
// I2C could get confused.
|
||||||
|
if (I2caRegs.I2CMDR.bit.STP == 1)
|
||||||
|
{
|
||||||
|
return I2C_STP_NOT_READY_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check if bus busy
|
||||||
|
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||||||
|
{
|
||||||
|
return I2C_BUS_BUSY_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Setup number of bytes to send
|
||||||
|
// MsgBuffer + Address
|
||||||
|
I2caRegs.I2CCNT = 4;
|
||||||
|
|
||||||
|
// Send start as master transmitter
|
||||||
|
I2caRegs.I2CMDR.all = 0x6E20;
|
||||||
|
|
||||||
|
// Setup data to send
|
||||||
|
I2caRegs.I2CDXR = (Addr*2)>>8;
|
||||||
|
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||||
|
I2caRegs.I2CDXR = (Addr*2);
|
||||||
|
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||||
|
I2caRegs.I2CDXR = Data>>8;
|
||||||
|
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||||
|
I2caRegs.I2CDXR = Data;
|
||||||
|
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||||
|
while(I2caRegs.I2CMDR.bit.STP == 1);
|
||||||
|
while(I2caRegs.I2CSTR.bit.BB == 1);
|
||||||
|
|
||||||
|
return I2C_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int I2CA_ReadData(unsigned int Addr)
|
||||||
|
{
|
||||||
|
WORDE data;
|
||||||
|
|
||||||
|
// Wait until the STP bit is cleared from any previous master communication.
|
||||||
|
// Clearing of this bit by the module is delayed until after the SCD bit is
|
||||||
|
// set. If this bit is not checked prior to initiating a new message, the
|
||||||
|
// I2C could get confused.
|
||||||
|
if (I2caRegs.I2CMDR.bit.STP == 1)
|
||||||
|
{
|
||||||
|
return I2C_STP_NOT_READY_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check if bus busy
|
||||||
|
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||||||
|
{
|
||||||
|
return I2C_BUS_BUSY_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
I2caRegs.I2CCNT = 2;
|
||||||
|
I2caRegs.I2CMDR.all = 0x6E20; // Send data to setup EEPROM address 0x6620
|
||||||
|
I2caRegs.I2CDXR = (Addr*2)>>8;
|
||||||
|
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||||
|
I2caRegs.I2CDXR = (Addr*2);
|
||||||
|
while(I2caRegs.I2CMDR.bit.STP == 1);
|
||||||
|
|
||||||
|
I2caRegs.I2CCNT = 2;
|
||||||
|
I2caRegs.I2CMDR.all = 0x6C20; // Send restart as master receiver
|
||||||
|
|
||||||
|
while(!I2caRegs.I2CSTR.bit.RRDY);
|
||||||
|
data.byt.byte_1 = I2caRegs.I2CDRR;
|
||||||
|
while(!I2caRegs.I2CSTR.bit.RRDY);
|
||||||
|
data.byt.byte_0 = I2caRegs.I2CDRR;
|
||||||
|
|
||||||
|
return data.all;
|
||||||
|
}
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// No more.
|
||||||
|
//===========================================================================
|
||||||
4
i2c.h
Normal file
4
i2c.h
Normal file
@ -0,0 +1,4 @@
|
|||||||
|
void I2CA_Init(void);
|
||||||
|
Uint16 I2CA_WriteData(unsigned int Addr, int Data);
|
||||||
|
int I2CA_ReadData(unsigned int Addr);
|
||||||
|
|
||||||
BIN
ice.CS_/FILE.CDX
Normal file
BIN
ice.CS_/FILE.CDX
Normal file
Binary file not shown.
BIN
ice.CS_/FILE.DBF
Normal file
BIN
ice.CS_/FILE.DBF
Normal file
Binary file not shown.
BIN
ice.CS_/FILE.FPT
Normal file
BIN
ice.CS_/FILE.FPT
Normal file
Binary file not shown.
BIN
ice.CS_/SYMBOL.CDX
Normal file
BIN
ice.CS_/SYMBOL.CDX
Normal file
Binary file not shown.
BIN
ice.CS_/SYMBOL.DBF
Normal file
BIN
ice.CS_/SYMBOL.DBF
Normal file
Binary file not shown.
BIN
ice.CS_/SYMBOL.FPT
Normal file
BIN
ice.CS_/SYMBOL.FPT
Normal file
Binary file not shown.
71
ice.pjt
Normal file
71
ice.pjt
Normal file
@ -0,0 +1,71 @@
|
|||||||
|
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
|
||||||
|
|
||||||
|
[Project Settings]
|
||||||
|
ProjectDir="F:\ICE\"
|
||||||
|
ProjectType=Executable
|
||||||
|
CPUFamily=TMS320C28XX
|
||||||
|
Tool="Compiler"
|
||||||
|
Tool="CustomBuilder"
|
||||||
|
Tool="DspBiosBuilder"
|
||||||
|
Tool="Linker"
|
||||||
|
Config="Debug"
|
||||||
|
Config="Release"
|
||||||
|
|
||||||
|
[Source Files]
|
||||||
|
Source="ADC.c"
|
||||||
|
Source="bios.c"
|
||||||
|
Source="cntrl_adr.c"
|
||||||
|
Source="crc16.c"
|
||||||
|
Source="ecan.c"
|
||||||
|
Source="filter_bat2.c"
|
||||||
|
Source="i2c.c"
|
||||||
|
Source="isolatio.c"
|
||||||
|
Source="log_to_mem.c"
|
||||||
|
Source="main.c"
|
||||||
|
Source="measure.c"
|
||||||
|
Source="message.c"
|
||||||
|
Source="peripher.c"
|
||||||
|
Source="RS485.c"
|
||||||
|
Source="spise2p.c"
|
||||||
|
Source="tools.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_Adc.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_CpuTimers.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_PieCtrl.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_SysCtrl.c"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_usDelay.asm"
|
||||||
|
Source="v120\DSP2833x_common\source\DSP2833x_Xintf.c"
|
||||||
|
Source="v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
|
||||||
|
Source="F28335.cmd"
|
||||||
|
Source="v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
|
||||||
|
|
||||||
|
["Debug" Settings]
|
||||||
|
FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.hex -i
|
||||||
|
FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.bin -b
|
||||||
|
|
||||||
|
["Compiler" Settings: "Debug"]
|
||||||
|
Options=-g -pdsw225 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\v120\DSP2833x_headers\include" -i"$(Proj_dir)\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32
|
||||||
|
|
||||||
|
["Compiler" Settings: "Release"]
|
||||||
|
Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28
|
||||||
|
|
||||||
|
["Linker" Settings: "Debug"]
|
||||||
|
Options=-c -e_c_int00 -m".\Debug\ice.map" -o".\bin\ice.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib"
|
||||||
|
|
||||||
|
["Linker" Settings: "Release"]
|
||||||
|
Options=-c -m".\Release\UKSS745.1TMS320F28335.map" -o".\Release\UKSS745.1TMS320F28335.out" -w -x
|
||||||
|
|
||||||
|
["F28335.cmd" Settings: "Debug"]
|
||||||
|
LinkOrder=1
|
||||||
|
|
||||||
|
["F28335.cmd" Settings: "Release"]
|
||||||
|
LinkOrder=1
|
||||||
|
|
||||||
|
["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"]
|
||||||
|
LinkOrder=2
|
||||||
|
|
||||||
|
["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"]
|
||||||
|
LinkOrder=1
|
||||||
|
|
||||||
148
isolatio.c
Normal file
148
isolatio.c
Normal file
@ -0,0 +1,148 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "message.h"
|
||||||
|
#include "package.h"
|
||||||
|
#include "peripher.h"
|
||||||
|
#include "crc16.h"
|
||||||
|
#include "isolatio.h"
|
||||||
|
#include <math.h> // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!!
|
||||||
|
|
||||||
|
OPTOCANAL opt[2];
|
||||||
|
|
||||||
|
void DCLK(int i, int x)
|
||||||
|
{
|
||||||
|
x=!x;
|
||||||
|
|
||||||
|
if(i)
|
||||||
|
{
|
||||||
|
if(x) GpioDataRegs.GPASET.bit.GPIO26=1;
|
||||||
|
else GpioDataRegs.GPACLEAR.bit.GPIO26=1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(x) GpioDataRegs.GPBSET.bit.GPIO32=1;
|
||||||
|
else GpioDataRegs.GPBCLEAR.bit.GPIO32=1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
int DIN(int i)
|
||||||
|
{
|
||||||
|
if(i) return !GpioDataRegs.GPBDAT.bit.GPIO52;
|
||||||
|
else return !GpioDataRegs.GPADAT.bit.GPIO23;
|
||||||
|
}
|
||||||
|
|
||||||
|
void BLIN(int i)
|
||||||
|
{
|
||||||
|
if(i) GpioDataRegs.GPBTOGGLE.bit.GPIO53=1;
|
||||||
|
else GpioDataRegs.GPATOGGLE.bit.GPIO24=1;
|
||||||
|
}
|
||||||
|
|
||||||
|
interrupt void cpu_timer1_isr_ISOL(void)
|
||||||
|
{
|
||||||
|
ERROR error;
|
||||||
|
float Riso=0,kff=1;
|
||||||
|
static float fRiso[2];
|
||||||
|
static int ist[2] = {1,1};
|
||||||
|
long numb=0;
|
||||||
|
int i;
|
||||||
|
static unsigned int count_ready=0;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
CpuTimer1.InterruptCount++;
|
||||||
|
IER |= MINT13; // Set "global" priority
|
||||||
|
EINT;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
ServiceDog();
|
||||||
|
|
||||||
|
if(++count_ready >= period_ready)
|
||||||
|
{
|
||||||
|
count_ready=0;
|
||||||
|
|
||||||
|
if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
|
||||||
|
else set_READY();
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=0;i<2;i++)
|
||||||
|
{
|
||||||
|
if(sens_error[i].bit.Bypas)
|
||||||
|
{
|
||||||
|
sens_error[i].all = 0;
|
||||||
|
sens_error[i].bit.Bypas = 1;
|
||||||
|
Modbus[i+DATASTART].all = 0;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(opt[i].Wait)
|
||||||
|
{
|
||||||
|
opt[i].Wait--;
|
||||||
|
opt[i].bit = 0;
|
||||||
|
opt[i].clk = 0;
|
||||||
|
DCLK(i,0);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
opt[i].clk=!opt[i].clk;
|
||||||
|
DCLK(i,opt[i].clk);
|
||||||
|
if(!opt[i].clk)
|
||||||
|
{
|
||||||
|
opt[i].Numb = (opt[i].Numb<<1) | DIN(i);
|
||||||
|
if(++opt[i].bit>=32)
|
||||||
|
{
|
||||||
|
error.all = 0;
|
||||||
|
|
||||||
|
opt[i].Wait = (TELE_FREQ/1000)*optopowse;
|
||||||
|
opt[!i].Wait =(TELE_FREQ/2000)*optopowse;
|
||||||
|
if(get_crc32(&(opt[i].Numb)))
|
||||||
|
{
|
||||||
|
numb = opt[i].Numb;
|
||||||
|
numb = numb / 256; // óäàëÿåì êîíòðîëüíóþ ñóììó
|
||||||
|
Riso=numb;
|
||||||
|
|
||||||
|
if(ist[i]) { kff=1; ist[i]=0; }
|
||||||
|
else kff = optofiltr;
|
||||||
|
fRiso[i] += (Riso-fRiso[i])/kff;
|
||||||
|
|
||||||
|
numb = (long)fRiso[i];
|
||||||
|
Modbus[i*2+0x10].all = (int)(numb & 0xFFFF);
|
||||||
|
Modbus[i*2+0x11].all = (int)(numb>>16);
|
||||||
|
|
||||||
|
Riso=numb;
|
||||||
|
Riso = Riso/256; // ïðåäïîëîæèì
|
||||||
|
Modbus[i+DATASTART].all = Riso;
|
||||||
|
opt[i].ers = 0; BLIN(i);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(++opt[i].ers > 20)
|
||||||
|
{
|
||||||
|
opt[i].ers = 20;
|
||||||
|
error.bit.Tear = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
reset_errs(i,error);
|
||||||
|
|
||||||
|
} }
|
||||||
|
}
|
||||||
|
|
||||||
|
sig.all = chk.all;
|
||||||
|
chk.all = 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
void timer_Init()
|
||||||
|
{
|
||||||
|
EALLOW; // This is needed to write to EALLOW protected registers
|
||||||
|
PieVectTable.XINT13 = &cpu_timer1_isr_ISOL;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/TELE_FREQ);
|
||||||
|
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||||
|
IER |= M_INT13;
|
||||||
|
|
||||||
|
period_ready = TELE_FREQ / (READY_FREQ * 2);
|
||||||
|
|
||||||
|
}
|
||||||
13
isolatio.h
Normal file
13
isolatio.h
Normal file
@ -0,0 +1,13 @@
|
|||||||
|
void timer_Init(void);
|
||||||
|
int get_isolatio(void);
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned int clk;
|
||||||
|
unsigned int bit;
|
||||||
|
unsigned int ers;
|
||||||
|
unsigned Wait;
|
||||||
|
unsigned long Numb;
|
||||||
|
} OPTOCANAL;
|
||||||
|
|
||||||
|
#define TELE_FREQ 2000 // Ãö
|
||||||
164
kanal.c
Normal file
164
kanal.c
Normal file
@ -0,0 +1,164 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "message.h"
|
||||||
|
#include "kanal.h"
|
||||||
|
#include "test.h"
|
||||||
|
#include "package.h"
|
||||||
|
#include "tools.h"
|
||||||
|
|
||||||
|
#include "peripher.h"
|
||||||
|
|
||||||
|
int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0};
|
||||||
|
|
||||||
|
void DCLK(int x)
|
||||||
|
{
|
||||||
|
if(x) GpioDataRegs.GPASET.bit.GPIO6=1;
|
||||||
|
else GpioDataRegs.GPACLEAR.bit.GPIO6=1;
|
||||||
|
DSP28x_usDelay(1L);
|
||||||
|
}
|
||||||
|
|
||||||
|
void DOUT(int x)
|
||||||
|
{
|
||||||
|
if(x) GpioDataRegs.GPASET.bit.GPIO8=1;
|
||||||
|
else GpioDataRegs.GPACLEAR.bit.GPIO8=1;
|
||||||
|
DSP28x_usDelay(1L);
|
||||||
|
}
|
||||||
|
|
||||||
|
void RESET()
|
||||||
|
{
|
||||||
|
DCLK(0); DOUT(1);
|
||||||
|
DCLK(0); DOUT(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SENDBIT(int x)
|
||||||
|
{
|
||||||
|
DOUT(x); DCLK(1);
|
||||||
|
DOUT(0); DCLK(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void kanal_Send(int adr, long dat, int dot)
|
||||||
|
{
|
||||||
|
long Word,data,aliq_part,dg[4];
|
||||||
|
int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len;
|
||||||
|
|
||||||
|
if(adr>1) // Ëàìïî÷êè
|
||||||
|
{
|
||||||
|
Word =dat;
|
||||||
|
}
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
{
|
||||||
|
if(dot<0 || dot>13) // Îøèáêà: -Å...
|
||||||
|
{
|
||||||
|
dg[3] = 0xA; dg[2] = 0xE;
|
||||||
|
dg[1] = 0xF; dg[0] = 0xF;
|
||||||
|
punkt = 0x7;
|
||||||
|
}
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
{
|
||||||
|
if(dat<0) sgn=1;
|
||||||
|
data = labs(dat);
|
||||||
|
|
||||||
|
aliq_part = data;
|
||||||
|
for(i=0;i<dot;i++) aliq_part/=10;
|
||||||
|
|
||||||
|
dat = aliq_part;
|
||||||
|
while(dat>0)
|
||||||
|
{
|
||||||
|
aliq_len++; dat/=10;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(aliq_len+sgn>4)
|
||||||
|
{
|
||||||
|
if(sgn) dg[3] = 0xA;
|
||||||
|
else dg[3] = 0xF;
|
||||||
|
|
||||||
|
dat = aliq_part;
|
||||||
|
for(i=1;i<aliq_len;i++) dat/=10;
|
||||||
|
|
||||||
|
dg[2] = dat;
|
||||||
|
dg[1] = 0xE;
|
||||||
|
dg[0] = aliq_len-1;
|
||||||
|
punkt=0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
dat = data;
|
||||||
|
|
||||||
|
full_len = aliq_len+sgn;
|
||||||
|
if(full_len==0) full_len=1;
|
||||||
|
full_len += dot;
|
||||||
|
|
||||||
|
for(i=0; i<(full_len-4);i++)
|
||||||
|
{
|
||||||
|
dot--; dat/=10;
|
||||||
|
}
|
||||||
|
if(dot<0) dot=0;
|
||||||
|
punkt = 1<<dot;
|
||||||
|
if(punkt==1) punkt=0;
|
||||||
|
|
||||||
|
dg[3] = (dat)/1000;
|
||||||
|
dg[2] = (dat%1000)/100;
|
||||||
|
dg[1] = (dat%100)/10;
|
||||||
|
dg[0] = (dat%10);
|
||||||
|
|
||||||
|
if(dg[0]+dg[1]+dg[2]+dg[3]==0)
|
||||||
|
{
|
||||||
|
punkt=0; dot=0; sgn=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=3;i>0;i--)
|
||||||
|
{
|
||||||
|
if((dg[i]==0)&&(i!=dot))
|
||||||
|
dg[i]=0xF; // Ýòî çíà÷èò ïóñòî
|
||||||
|
else break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(sgn)
|
||||||
|
for(i=1;i<4;i++)
|
||||||
|
{
|
||||||
|
if( (dg[i]==0xF)||(i==3))
|
||||||
|
{
|
||||||
|
dg[i]=0xA; // Ýòî çíà÷èò ìèíóñ
|
||||||
|
break;
|
||||||
|
} } } }
|
||||||
|
|
||||||
|
for(i=0;i<4;i++)
|
||||||
|
{
|
||||||
|
dg[i] = digits[dg[i]];
|
||||||
|
if((punkt>>i)&1) dg[i]+= 128;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) |
|
||||||
|
((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i=0;i<4;i++)
|
||||||
|
{
|
||||||
|
if(addr>0x10) break;
|
||||||
|
|
||||||
|
for (j=0;j<8;j++)
|
||||||
|
{
|
||||||
|
bit = Word & 1; Word >>= 1;
|
||||||
|
SENDBIT(bit);
|
||||||
|
}
|
||||||
|
|
||||||
|
byt = addr;
|
||||||
|
for (j=0;j<6;j++)
|
||||||
|
{
|
||||||
|
bit = byt & 1; byt >>= 1;
|
||||||
|
SENDBIT(bit);
|
||||||
|
}
|
||||||
|
addr++;
|
||||||
|
|
||||||
|
RESET();
|
||||||
|
}
|
||||||
|
}
|
||||||
7
kanal.h
Normal file
7
kanal.h
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
void kanal_Send(int adr, long dat, int dot);
|
||||||
|
|
||||||
|
#define adr_diod1 0x00 // Ïåðâûå 4 äèîäíûõ ïëàòû
|
||||||
|
#define adr_diod2 0x04 // Âòîðûå 4 äèîäíûõ ïëàòû
|
||||||
|
#define adr_digg1 0x08 // Ïåðâûå 4 öèôðû
|
||||||
|
#define adr_digg2 0x0C // Âòîðûå 4 öèôðû
|
||||||
|
#define adr_lamps 0x10 // Ëàìïû
|
||||||
34
log_to_mem.c
Normal file
34
log_to_mem.c
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */
|
||||||
|
/****************************************************************/
|
||||||
|
/* log_to_mem.c
|
||||||
|
****************************************************************
|
||||||
|
* Çàïèñü ëîãîâ â ïàìyòü *
|
||||||
|
****************************************************************/
|
||||||
|
|
||||||
|
#include "log_to_mem.h"
|
||||||
|
|
||||||
|
int no_write = 1,
|
||||||
|
never_write = 0; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî)
|
||||||
|
|
||||||
|
#pragma DATA_SECTION(logs_block,".logg");
|
||||||
|
unsigned int logs_block[0xF000];
|
||||||
|
|
||||||
|
LOG Log;
|
||||||
|
unsigned int flog=0;
|
||||||
|
|
||||||
|
// Î÷èùåíèå ïàìàòè, ãäå ëîãè ëåæàò
|
||||||
|
void clear_mem()
|
||||||
|
{
|
||||||
|
unsigned long i;
|
||||||
|
|
||||||
|
Log.Start = LOG_PAGE_START;
|
||||||
|
Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN;
|
||||||
|
Log.Adres = Log.Start;
|
||||||
|
Log.Circl = 0;
|
||||||
|
|
||||||
|
for (i=Log.Start; i<Log.Finis; i++)
|
||||||
|
*(volatile int *)i = 0;
|
||||||
|
}
|
||||||
48
log_to_mem.h
Normal file
48
log_to_mem.h
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
/****************************************************************/
|
||||||
|
/* TMS320C32 */
|
||||||
|
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||||
|
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */
|
||||||
|
/****************************************************************/
|
||||||
|
/* log_to_mem.h
|
||||||
|
****************************************************************
|
||||||
|
* Çàïèñü ëîãîâ â ïàìyòü *
|
||||||
|
****************************************************************/
|
||||||
|
|
||||||
|
#ifndef _LOG_TO_MEM
|
||||||
|
#define _LOG_TO_MEM
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Îïðåäåëåíèa äëa ðàáîòû ëîããåðà */
|
||||||
|
#define LOG_PAGE_START 0x0200000
|
||||||
|
#define LOG_PAGE_LEN 0xF000
|
||||||
|
|
||||||
|
extern int no_write, never_write; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî)
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned long Start;
|
||||||
|
unsigned long Finis;
|
||||||
|
unsigned long Adres;
|
||||||
|
unsigned int Circl;
|
||||||
|
|
||||||
|
} LOG;
|
||||||
|
|
||||||
|
extern LOG Log;
|
||||||
|
|
||||||
|
/* Çàïèñü ñëîâa â ïàìàòü, ãäå ëîãè ëåæàò */
|
||||||
|
#define Log_to_mem(x) *(int *)(Log.Adres++) = x
|
||||||
|
|
||||||
|
/* Ïðîâåðêà ãðàíèöû ïàìàòè äëà ëîãîâ */
|
||||||
|
#define Test_mem_limit(x) if(Log.Adres > (Log.Finis - x)) Log.Adres = Log.Start
|
||||||
|
|
||||||
|
/* Î÷èñòêà ïàìàòè (îáíóëåíèå) */
|
||||||
|
void clear_mem();
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _LOG_TO_MEM */
|
||||||
180
main.c
Normal file
180
main.c
Normal file
@ -0,0 +1,180 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
|
||||||
|
#include "cntrl_adr.h"
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "BIOS_DSP.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "Message.h"
|
||||||
|
#include "package.h"
|
||||||
|
|
||||||
|
#include "spise2p.h"
|
||||||
|
#include "i2c.h"
|
||||||
|
|
||||||
|
#include "tools.h"
|
||||||
|
#include "peripher.h"
|
||||||
|
#include "ADC.h"
|
||||||
|
|
||||||
|
#include "ecan.h"
|
||||||
|
#include "log_to_mem.h"
|
||||||
|
|
||||||
|
#include "measure.h"
|
||||||
|
#include "isolatio.h"
|
||||||
|
|
||||||
|
extern void DSP28x_usDelay(Uint32 Count);
|
||||||
|
|
||||||
|
int kaka[3]={64,0,0};
|
||||||
|
|
||||||
|
void main()
|
||||||
|
{
|
||||||
|
int i,j;
|
||||||
|
static int canpowse=0,cancount[3],cancell[3],circ[3];
|
||||||
|
RS_DATA * rs;
|
||||||
|
|
||||||
|
|
||||||
|
InitSysCtrl();
|
||||||
|
|
||||||
|
// Disable CPU interrupts and clear all CPU interrupt flags:
|
||||||
|
DINT;
|
||||||
|
|
||||||
|
InitPieCtrl();
|
||||||
|
|
||||||
|
IER = 0x0000;
|
||||||
|
IFR = 0x0000;
|
||||||
|
|
||||||
|
InitPieVectTable();
|
||||||
|
|
||||||
|
init_zone7();
|
||||||
|
|
||||||
|
setup_leds_line();
|
||||||
|
led1_on();
|
||||||
|
led2_off();
|
||||||
|
for (i=0;i<10;i++)
|
||||||
|
{
|
||||||
|
pause_us(50000);
|
||||||
|
led2_toggle();
|
||||||
|
led1_toggle();
|
||||||
|
}
|
||||||
|
led1_off();
|
||||||
|
led2_off();
|
||||||
|
|
||||||
|
get_Mode();
|
||||||
|
set_cntrl_addr(Mode,16);
|
||||||
|
create_uart_vars(sizeof(CMD_TO_TMS));
|
||||||
|
setup_uart(COM_1,115200);
|
||||||
|
setup_uart(COM_2,115200);
|
||||||
|
Init_Can(0,Addrr);
|
||||||
|
Init_Seeprom();
|
||||||
|
clear_mem();
|
||||||
|
|
||||||
|
EnableInterrupts();
|
||||||
|
|
||||||
|
if(Desk!=dsk_ISOL)
|
||||||
|
{
|
||||||
|
setup_adc();
|
||||||
|
Init_sensors();
|
||||||
|
I2CA_Init(); pause_us(500000);
|
||||||
|
Load_caliber();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
timer_Init();
|
||||||
|
Init_optic();
|
||||||
|
}
|
||||||
|
|
||||||
|
Load_params();
|
||||||
|
Init_packMask();
|
||||||
|
|
||||||
|
LastMode = Addrr;
|
||||||
|
|
||||||
|
for(i=0;i<3;i++)
|
||||||
|
{
|
||||||
|
cancount[i]= 0;
|
||||||
|
cancell[i] = CAN_send_start;
|
||||||
|
}
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
SysCtrlRegs.WDCR= 0x2F;
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
MAY=1;
|
||||||
|
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
if(canpowse) canpowse--;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
canpowse = 0x1000;
|
||||||
|
for(i=0;i<3;i++)
|
||||||
|
{
|
||||||
|
if(cancount[i]) cancount[i]--;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
cancount[i] = Cancount[i]; circ[i] = 0;
|
||||||
|
|
||||||
|
while( !((Maska[i][cancell[i]/16]>>(cancell[i]%16))&1) && circ[i] < 2 )
|
||||||
|
if(cancell[i]>CAN_send_finis)
|
||||||
|
{
|
||||||
|
cancell[i] = CAN_send_start; circ[i]++;
|
||||||
|
}
|
||||||
|
else cancell[i]++;
|
||||||
|
|
||||||
|
if(cancell[i]<=CAN_send_finis && circ[i] < 2)
|
||||||
|
{
|
||||||
|
CAN_send(0,(int *)Modbus,cancell[i]);
|
||||||
|
cancell[i]+=3;
|
||||||
|
} } } }
|
||||||
|
|
||||||
|
if(cSaveParam)
|
||||||
|
{
|
||||||
|
cSaveParam=0;
|
||||||
|
Save_params();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(cReadCal)
|
||||||
|
{
|
||||||
|
cReadCal=0;
|
||||||
|
Load_caliber();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(cDefParam)
|
||||||
|
{
|
||||||
|
cDefParam=0;
|
||||||
|
Default_params();
|
||||||
|
}
|
||||||
|
|
||||||
|
get_Inputs();
|
||||||
|
|
||||||
|
if(Desk!=dsk_SHKF)
|
||||||
|
{
|
||||||
|
Modbus[23].all = Inputs.wrd.word_0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=0;i<2;i++)
|
||||||
|
{
|
||||||
|
if(i) rs = &rs_a;
|
||||||
|
else rs = &rs_b;
|
||||||
|
|
||||||
|
j = get_command(rs);
|
||||||
|
|
||||||
|
if(j!=-1)
|
||||||
|
switch(j)
|
||||||
|
{
|
||||||
|
case CMD_INIT: init(rs); led2_toggle();break; // íà÷àëüíûå óñòàíîâêè
|
||||||
|
case CMD_INITLOAD: initload(rs); led2_toggle();break; // íàñòðîéêà çàãðóçêè
|
||||||
|
case CMD_RUN: run(rs); led2_toggle();break; // çàãðóçèòü áëîê
|
||||||
|
case CMD_LOAD: load(rs); led2_toggle();break; // çàãðóçèòü áëîê
|
||||||
|
case CMD_PEEK: peek(rs); led2_toggle();break; // ïðî÷èòàòü à÷åéêó ïàìàòè
|
||||||
|
case CMD_POKE: poke(rs); led2_toggle();break; // çàïèñàòü â à÷åéêó ïàìàòè
|
||||||
|
case CMD_UPLOAD: upload(rs); led2_toggle();break; // ïåðåäàòü áëîê ïàìàòè
|
||||||
|
case CMD_EXTEND: extendbios(rs); led2_toggle();break; // ðàñøèðåííûå êîìàíäû äëà áèîñà
|
||||||
|
|
||||||
|
case CMD_TFLASH: tflash(rs); led2_toggle();break; // ïðîøèòü TMS
|
||||||
|
|
||||||
|
// case CMD_STD: ReceiveCommand(rs); led2_toggle();break;
|
||||||
|
case CMD_MODBUS_3: ReceiveCommandModbus3(rs); led2_toggle();break;
|
||||||
|
case CMD_MODBUS_6: ReceiveCommandModbus6(rs); led2_toggle();break;
|
||||||
|
|
||||||
|
default: break;
|
||||||
|
} } } }
|
||||||
|
|
||||||
656
measure.c
Normal file
656
measure.c
Normal file
@ -0,0 +1,656 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "package.h"
|
||||||
|
|
||||||
|
#include "measure.h"
|
||||||
|
#include "package.h"
|
||||||
|
|
||||||
|
#include "peripher.h"
|
||||||
|
#include "ADC.h"
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "message.h"
|
||||||
|
#include "log_to_mem.h"
|
||||||
|
|
||||||
|
#include <math.h> // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!!
|
||||||
|
|
||||||
|
int MAX_TPL_CANAL=0; // Êîëè÷åñòâî òåìïåðàòóðíûõ êàíàëîâ
|
||||||
|
int period_ready, period_blink, period_dac, time_dac;
|
||||||
|
|
||||||
|
FLAG chk,sig;
|
||||||
|
long time_1_5sec, time_5msec, time_5sec;
|
||||||
|
|
||||||
|
long err_count[6];
|
||||||
|
float lev_count[6];
|
||||||
|
|
||||||
|
int sens_type[24];
|
||||||
|
int sens_pair[24];
|
||||||
|
long din_count[32];
|
||||||
|
|
||||||
|
int adc0[24];
|
||||||
|
int tmp0[24];
|
||||||
|
float tmpK[24];
|
||||||
|
|
||||||
|
FILTERBAT def_FILTERBAT = DEF_FILTERBAT;
|
||||||
|
FILTERBAT filter[40];
|
||||||
|
|
||||||
|
long sens_count[28];
|
||||||
|
|
||||||
|
interrupt void cpu_timer1_isr_SENS(void);
|
||||||
|
|
||||||
|
/********************************************************************/
|
||||||
|
/* Ðàñ÷åò ìîäóëà òîêà èç ïîêàçàíèé äâóõ ôàç */
|
||||||
|
/********************************************************************/
|
||||||
|
float im_calc(float ia,float ib)
|
||||||
|
{
|
||||||
|
float isa,isb;
|
||||||
|
|
||||||
|
isa = - 1.5 * (ia + ib);
|
||||||
|
isb = COSPi6 * (ia - ib);
|
||||||
|
return (2*sqrt(isa*isa+isb*isb)/3);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
interrupt void cpu_timer1_isr_SENS(void)
|
||||||
|
{
|
||||||
|
static unsigned int
|
||||||
|
count_ready=0, count_blink=0, count_bright=0, count_mode,
|
||||||
|
blink_over, blink_alarm, work_lamp, heat_lamp, errr_lamp;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
CpuTimer1.InterruptCount++;
|
||||||
|
IER |= MINT13; // Set "global" priority
|
||||||
|
EINT;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
if(++count_ready >= period_ready)
|
||||||
|
{
|
||||||
|
count_ready=0;
|
||||||
|
|
||||||
|
if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
|
||||||
|
else set_READY();
|
||||||
|
ServiceDog();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(++count_bright == maximum_bright)
|
||||||
|
{
|
||||||
|
count_bright = 0 ;
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM)
|
||||||
|
{
|
||||||
|
if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO60=1;
|
||||||
|
else GpioDataRegs.GPBSET.bit.GPIO60=1;
|
||||||
|
if(heat_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO58=1;
|
||||||
|
else GpioDataRegs.GPBSET.bit.GPIO58=1;
|
||||||
|
if(errr_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
|
||||||
|
else GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Mode==adr_SHKF)
|
||||||
|
{
|
||||||
|
if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
|
||||||
|
else GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
if(count_bright == Brightness)
|
||||||
|
{
|
||||||
|
if(Desk==dsk_COMM)
|
||||||
|
{
|
||||||
|
GpioDataRegs.GPBSET.bit.GPIO60=1;
|
||||||
|
GpioDataRegs.GPBSET.bit.GPIO58=1;
|
||||||
|
GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Desk==dsk_SHKF)
|
||||||
|
{
|
||||||
|
GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
if(++count_blink >= period_blink)
|
||||||
|
{
|
||||||
|
count_blink=0;
|
||||||
|
count_mode++;
|
||||||
|
blink_over = (count_mode & 1)?1:0;
|
||||||
|
blink_alarm = (count_mode & 7)?1:0;
|
||||||
|
|
||||||
|
if(cExtLamp)
|
||||||
|
{
|
||||||
|
work_lamp = cExtLite;
|
||||||
|
heat_lamp = cExtLite;
|
||||||
|
errr_lamp = cExtLite;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(cTestLamp)
|
||||||
|
{
|
||||||
|
work_lamp = blink_over;
|
||||||
|
heat_lamp = blink_over;
|
||||||
|
errr_lamp = blink_over;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(Mode==adr_SHKF)
|
||||||
|
{
|
||||||
|
if(sig.bit.Error) work_lamp = blink_over;
|
||||||
|
else work_lamp = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(sig.bit.Error) work_lamp = 0;//blink_over;
|
||||||
|
// else if(sig.bit.Alarm) work_lamp = blink_alarm;
|
||||||
|
else work_lamp = 1;
|
||||||
|
|
||||||
|
if(sig.bit.OverHeat) heat_lamp = 1;
|
||||||
|
else if(sig.bit.SubHeat) heat_lamp = blink_over;
|
||||||
|
else if(sig.bit.OutHeat) heat_lamp = !blink_alarm;
|
||||||
|
else heat_lamp = 0;
|
||||||
|
} } } } }
|
||||||
|
|
||||||
|
void Init_optic()
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i=0;i<24;i++)
|
||||||
|
{
|
||||||
|
sens_type[i]=0;
|
||||||
|
sens_pair[i]=i;
|
||||||
|
}
|
||||||
|
|
||||||
|
sens_type[0] = OPTIC;
|
||||||
|
sens_type[1] = OPTIC;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Init_sensors()
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
EALLOW; // This is needed to write to EALLOW protected registers
|
||||||
|
PieVectTable.XINT13 = &cpu_timer1_isr_SENS;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
ConfigCpuTimer(&CpuTimer1, (SYSCLKOUT/1000000), 1000000/SIG_FREQ);
|
||||||
|
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||||
|
IER |= M_INT13;
|
||||||
|
|
||||||
|
period_ready = SIG_FREQ / (READY_FREQ * 2);
|
||||||
|
period_blink = SIG_FREQ / (BLINK_FREQ * 2);
|
||||||
|
|
||||||
|
period_dac = SIG_FREQ / (DAC_FREQ);
|
||||||
|
time_dac = LOAD_TIME * DAC_FREQ;
|
||||||
|
|
||||||
|
time_1_5sec = (3 * ADC_FREQ) / 2;
|
||||||
|
time_5msec = (5 * ADC_FREQ) / 1000;
|
||||||
|
time_5sec = (5 * ADC_FREQ);
|
||||||
|
|
||||||
|
for(i=0;i<24;i++)
|
||||||
|
{
|
||||||
|
sens_type[i]=0;
|
||||||
|
sens_pair[i]=i;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((Mode==adr_REC1)||(Mode==adr_REC2))
|
||||||
|
{
|
||||||
|
sens_type[0]=TERMO_AD;
|
||||||
|
sens_type[1]=TERMO_AD;
|
||||||
|
sens_type[2]=TERMO_AD;
|
||||||
|
sens_type[3]=TERMO_AD;
|
||||||
|
|
||||||
|
sens_type[4]=TERMO_AD;
|
||||||
|
sens_type[5]=TERMO_AD;
|
||||||
|
|
||||||
|
//sens_type[6]=TERMO_AD;
|
||||||
|
//sens_type[7]=TERMO_AD;
|
||||||
|
|
||||||
|
|
||||||
|
sens_type[8]=TERMO_RS;
|
||||||
|
sens_type[9]=TERMO_RS;
|
||||||
|
sens_type[10]=TERMO_RS;
|
||||||
|
sens_type[11]=TERMO_RS;
|
||||||
|
|
||||||
|
sens_type[12]=VOLTAGE; sens_pair[12]=13;
|
||||||
|
sens_type[13]=VOLTAGE; sens_pair[13]=12;
|
||||||
|
sens_type[14]=VOLTAGE; sens_pair[14]=15;
|
||||||
|
sens_type[15]=VOLTAGE; sens_pair[15]=14;
|
||||||
|
|
||||||
|
Modbus[12].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[13].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[14].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[15].bit.bitE = 1; // Ignore
|
||||||
|
}
|
||||||
|
|
||||||
|
if((Mode==adr_INV1)||(Mode==adr_INV2))
|
||||||
|
{
|
||||||
|
sens_type[0]=TERMO_AD;
|
||||||
|
sens_type[1]=TERMO_AD;
|
||||||
|
sens_type[2]=TERMO_AD;
|
||||||
|
sens_type[3]=TERMO_AD;
|
||||||
|
|
||||||
|
sens_type[4]=TERMO_AD;
|
||||||
|
sens_type[5]=TERMO_AD;
|
||||||
|
//sens_type[6]=TERMO_AD;
|
||||||
|
|
||||||
|
sens_type[7]=TERMO_RS;
|
||||||
|
sens_type[8]=TERMO_RS;
|
||||||
|
sens_type[9]=TERMO_RS;
|
||||||
|
sens_type[10]=TERMO_RS;
|
||||||
|
sens_type[11]=TERMO_RS;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Mode==adr_SHKF)
|
||||||
|
{
|
||||||
|
sens_type[0 ] = POWER_380; sens_pair[0]=1;
|
||||||
|
sens_type[1 ] = POWER_380; sens_pair[1]=0;
|
||||||
|
sens_type[2 ] = POWER_220; sens_pair[2]=3;
|
||||||
|
sens_type[3 ] = POWER_220; sens_pair[3]=2;
|
||||||
|
sens_type[4 ] = POWER_31;
|
||||||
|
sens_type[5 ] = POWER_31;
|
||||||
|
sens_type[6 ] = POWER_24;
|
||||||
|
sens_type[7 ] = POWER_24;
|
||||||
|
sens_type[8 ] = POWER_24;
|
||||||
|
sens_type[9 ] = POWER_24;
|
||||||
|
sens_type[10] = POWER_24;
|
||||||
|
sens_type[11] = POWER_24;
|
||||||
|
sens_type[12] = POWER_15;
|
||||||
|
sens_type[13] = TERMO_AD;
|
||||||
|
sens_type[14] = TERMO_AD;
|
||||||
|
sens_type[15] = VIRT_24;
|
||||||
|
sens_type[16] = VIRT_24;
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=0;i<4; i++) err_count[i] = 0;
|
||||||
|
for(i=0;i<6; i++) lev_count[i] = 0;
|
||||||
|
for(i=0;i<28;i++) sens_count[i] = 0;
|
||||||
|
for(i=0;i<32;i++) din_count[i] = 0;
|
||||||
|
for(i=0;i<40;i++) filter[i] = def_FILTERBAT;
|
||||||
|
|
||||||
|
for(i=0;i<DATASTART;i++) Modbus[i].all &= NOER;
|
||||||
|
|
||||||
|
MAX_TPL_CANAL = 12;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Init_packMask()
|
||||||
|
{
|
||||||
|
int i,j;
|
||||||
|
|
||||||
|
for(i=0;i<3; i++)
|
||||||
|
for(j=0;j<9;j++) { Maska[i][j]=0; }
|
||||||
|
|
||||||
|
for(i=0;i<24;i++)
|
||||||
|
if(sens_type[i])
|
||||||
|
{
|
||||||
|
Maska[0][ i /16]|=(1<<( i %16));
|
||||||
|
Maska[0][(i+24)/16]|=(1<<((i+24)%16));
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=0;i<3; i++)
|
||||||
|
Maska[1][i+3] = Maska[0][i];
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM) Maska[0][1]|=0x80; // OilSensor, ButtsPressed
|
||||||
|
|
||||||
|
if(Desk==dsk_ISOL) Maska[0][1]|=0x0F; // raw data
|
||||||
|
|
||||||
|
Maska[1][6] = 0x00F3;
|
||||||
|
Maska[1][7] = 0xC000;
|
||||||
|
}
|
||||||
|
|
||||||
|
int er_anal(int term, long * count, int edge, int pre)
|
||||||
|
{
|
||||||
|
if (term)
|
||||||
|
{
|
||||||
|
if((*count)>=edge) return 1;
|
||||||
|
(*count)++; return pre;
|
||||||
|
}
|
||||||
|
if( (*count) == 0 ) return 0;
|
||||||
|
(*count)--; return pre;
|
||||||
|
}
|
||||||
|
|
||||||
|
void reset_errs(int sens, ERROR er)
|
||||||
|
{
|
||||||
|
// unsigned long report;
|
||||||
|
unsigned int set;
|
||||||
|
ERROR err;
|
||||||
|
|
||||||
|
err=er;
|
||||||
|
|
||||||
|
if(!sens_error[sens].bit.Latch)
|
||||||
|
{
|
||||||
|
set = sens_error[sens].all & NOER;
|
||||||
|
sens_error[sens].all = err.all | set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
sens_error[sens].all |= err.all;
|
||||||
|
}
|
||||||
|
sens_error[sens].bit.Ready = !(err.bit.Stop && (!sens_error[sens].bit.Ignor));
|
||||||
|
chk.bit.Error|= !(sens_error[sens].bit.Ready);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
ERROR control_ADC(int sens, int number, int zero)
|
||||||
|
{
|
||||||
|
ERROR err;
|
||||||
|
int erwait;
|
||||||
|
|
||||||
|
err.all = 0;
|
||||||
|
|
||||||
|
if(TermoSW) erwait = SENS_ERR_WAIT;
|
||||||
|
else erwait = ADC_FREQ;
|
||||||
|
|
||||||
|
// Êàíàë îáîðâàí
|
||||||
|
if(er_anal(((number <= zero)||(number >= (0x0FFF-(zero/100)))),
|
||||||
|
&sens_count[sens],erwait,
|
||||||
|
sens_error[sens].bit.Tear))
|
||||||
|
{
|
||||||
|
err.bit.Tear = 1;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
// ÀÖÏ çàëèï
|
||||||
|
if(er_anal( (sens_prev[sens] == number),
|
||||||
|
&sens_count[sens][1],ADC_FREQ,
|
||||||
|
sens_error[sens].bit.Stick))
|
||||||
|
{
|
||||||
|
err.bit.Stick = 1;
|
||||||
|
}
|
||||||
|
sens_prev[sens] = number;
|
||||||
|
*/
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
int input_freq(int chan, int Volt)
|
||||||
|
{
|
||||||
|
static int prevolt[4],tics[4],tacs[4],tic[4],tac[4];
|
||||||
|
static long Freq = 0;
|
||||||
|
int i,sum=0,bum=0;
|
||||||
|
|
||||||
|
if(Volt >= Zero_lev[chan])
|
||||||
|
if(prevolt[chan]< Zero_lev[chan])
|
||||||
|
{
|
||||||
|
tics[chan] = tic[chan]; tic[chan] = 0; bum = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Volt < Zero_lev[chan])
|
||||||
|
if(prevolt[chan]>= Zero_lev[chan])
|
||||||
|
{
|
||||||
|
tacs[chan] = tac[chan]; tac[chan] = 0; bum = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(bum)
|
||||||
|
{
|
||||||
|
for(i=0;i<4;i++) sum += tics[i] + tacs[i];
|
||||||
|
Freq = (80L * ADC_FREQ) / sum;
|
||||||
|
}
|
||||||
|
|
||||||
|
prevolt[chan] = Volt;
|
||||||
|
tic[chan]++;
|
||||||
|
tac[chan]++;
|
||||||
|
|
||||||
|
return Freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void Current_count(int sens)
|
||||||
|
{
|
||||||
|
float Numb,Current,fAmpl;
|
||||||
|
static float aCurrent,Amplitude;
|
||||||
|
static int prezer0=0;
|
||||||
|
int chan, pair, ist, thrd, i, ignor;
|
||||||
|
int freq=0;
|
||||||
|
|
||||||
|
ERROR error;
|
||||||
|
|
||||||
|
error.all = 0;
|
||||||
|
|
||||||
|
chan = sens - MAX_TPL_CANAL;
|
||||||
|
pair = sens_pair[sens] - MAX_TPL_CANAL;
|
||||||
|
ist = !(chan & 1);
|
||||||
|
thrd= (chan >>1) + 4;
|
||||||
|
|
||||||
|
if(sens_error[sens].bit.Bypas)
|
||||||
|
{
|
||||||
|
sens_error[sens].all = 0;
|
||||||
|
sens_error[sens].bit.Bypas = 1;
|
||||||
|
Modbus[sens+DATASTART].all = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Numb = ADC_table[sens];
|
||||||
|
|
||||||
|
if(cTermoCal||cSetZero)
|
||||||
|
{
|
||||||
|
if(!prezer0)
|
||||||
|
for(i=0;i<4;i++) lev_count[i] = Numb;
|
||||||
|
lev_count[chan] += (Numb-lev_count[chan])/1000.0;
|
||||||
|
adc0[sens] = (int)(filterbat(&filter[sens],lev_count[chan]));
|
||||||
|
Zero_lev[chan] = adc0[sens];
|
||||||
|
Modbus[sens+DATASTART].all = adc0[sens];
|
||||||
|
}
|
||||||
|
prezer0 = (cTermoCal||cSetZero);
|
||||||
|
|
||||||
|
Current = (Numb - adc0[sens]) * tmpK[sens];
|
||||||
|
|
||||||
|
if(!(cTermoCal||cSetZero))
|
||||||
|
{
|
||||||
|
freq = input_freq(chan,Numb);
|
||||||
|
|
||||||
|
|
||||||
|
lev_count[chan] += (fabs(Current)-lev_count[chan])/1000.0;
|
||||||
|
|
||||||
|
// Çàïîìíèì
|
||||||
|
if(ist)
|
||||||
|
{
|
||||||
|
aCurrent = -Current; // Çàïîìíèëè ìãíîâåííîå çíà÷åíèå - äëà àìïëèòóäû
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// Âû÷èñëåíèå àìïëèòóäû
|
||||||
|
Amplitude = im_calc(Current,aCurrent);
|
||||||
|
fAmpl = filterbat(&filter[sens],Amplitude);
|
||||||
|
|
||||||
|
if(fAmpl<100)
|
||||||
|
{
|
||||||
|
fAmpl=0; freq=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Modbus[sens+DATASTART-1].all = (int)fAmpl;//(int)Amplitude;
|
||||||
|
Modbus[sens+DATASTART-1].all = (int)(fAmpl/RADIX2);
|
||||||
|
|
||||||
|
// Òðåòüÿ ôàçà äëÿ ïðîâåðîê
|
||||||
|
lev_count[thrd] += (fabs(-Current-aCurrent)-lev_count[thrd])/1000.0;
|
||||||
|
|
||||||
|
i=(8-((sens+DATASTART-1)%8));
|
||||||
|
Modbus[sens+DATASTART+i-1+(thrd-4)*3].all = lev_count[chan];
|
||||||
|
Modbus[sens+DATASTART+i +(thrd-4)*3].all = lev_count[pair];
|
||||||
|
Modbus[sens+DATASTART+i+1+(thrd-4)*3].all = lev_count[thrd];
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
Modbus[sens+DATASTART].all = freq;
|
||||||
|
|
||||||
|
// Çàøèòû!
|
||||||
|
if(Current > 1.1 * sens_hi_edge[sens])
|
||||||
|
{
|
||||||
|
error.bit.Hyper = 1;
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
Numb = lev_count[chan];
|
||||||
|
if(Numb<lev_count[pair]) Numb = lev_count[pair];
|
||||||
|
if(Numb<lev_count[thrd]) Numb = lev_count[thrd];
|
||||||
|
|
||||||
|
ignor = sens_error[sens].bit.Ignor;
|
||||||
|
|
||||||
|
|
||||||
|
if(er_anal( ((Numb-lev_count[chan])/Numb > 0.2) && (Numb>100),
|
||||||
|
&err_count[chan],time_1_5sec,0))
|
||||||
|
{
|
||||||
|
error.bit.Wry = 1;
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.2) && (Numb>100),
|
||||||
|
&err_count[thrd],time_1_5sec,0))
|
||||||
|
{
|
||||||
|
error.bit.Wry = 1;
|
||||||
|
if(!ignor)
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(!ist)
|
||||||
|
{
|
||||||
|
if(Amplitude > sens_hi_edge[sens])
|
||||||
|
{
|
||||||
|
error.bit.Hyper = 1;
|
||||||
|
if(!ignor)
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Amplitude < sens_lo_edge[sens])
|
||||||
|
{
|
||||||
|
error.bit.Out = 1;
|
||||||
|
if(!ignor)
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
} } }
|
||||||
|
|
||||||
|
reset_errs(sens,error);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void Temper_count(int chan)
|
||||||
|
{
|
||||||
|
float Numb;
|
||||||
|
int Temper;
|
||||||
|
int ignor;
|
||||||
|
ERROR error;
|
||||||
|
int zer0;
|
||||||
|
|
||||||
|
if(!chan)
|
||||||
|
{
|
||||||
|
sig.all = chk.all;
|
||||||
|
chk.all = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(chan<MAX_TPL_CANAL*2)
|
||||||
|
if(sens_error[chan].bit.Bypas)
|
||||||
|
{
|
||||||
|
sens_error[chan].all = 0;
|
||||||
|
sens_error[chan].bit.Bypas = 1;
|
||||||
|
Modbus[chan+DATASTART].all = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Numb = ADC_table[chan];
|
||||||
|
|
||||||
|
if(cTermoCal)
|
||||||
|
{
|
||||||
|
Modbus[chan+DATASTART].all = (int)(Numb);
|
||||||
|
return; // øòîáû ñòðóêòóðà îøèáîê íå âëåçàëà â äàííûå
|
||||||
|
}
|
||||||
|
|
||||||
|
Numb = (Numb-adc0[chan])*tmpK[chan]+tmp0[chan]-273;
|
||||||
|
Modbus[chan+DATASTART].all = (int)(Numb*10);
|
||||||
|
|
||||||
|
Temper = (int)Numb;
|
||||||
|
|
||||||
|
error.all = 0;
|
||||||
|
if(sens_type[chan]==TERMO_AD) zer0=500;
|
||||||
|
if(sens_type[chan]==TERMO_RS) zer0=10;
|
||||||
|
error = control_ADC(chan, ADC_table[chan], zer0);
|
||||||
|
|
||||||
|
if(!error.all)
|
||||||
|
{
|
||||||
|
ignor = sens_error[chan].bit.Ignor;
|
||||||
|
if(((Temper>sens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) ||
|
||||||
|
(Temper>sens_hi_edge[chan]) )
|
||||||
|
{
|
||||||
|
error.bit.Hyper = 1;
|
||||||
|
if(!ignor)
|
||||||
|
{
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
chk.bit.OverHeat= 1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
// Ïðåäóïðåæäåíèå ïî òåìïåðàòóðå
|
||||||
|
|
||||||
|
if(Temper>sens_lo_edge[chan])
|
||||||
|
{
|
||||||
|
error.bit.Over = 1;
|
||||||
|
if(!ignor)
|
||||||
|
chk.bit.SubHeat = 1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
if(error.all) chk.bit.OutHeat = 1;
|
||||||
|
|
||||||
|
reset_errs(chan,error);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void Power_count(int chan)
|
||||||
|
{
|
||||||
|
float Numb;
|
||||||
|
int Power,ignor,bitt;
|
||||||
|
ERROR error;
|
||||||
|
|
||||||
|
if(sens_error[chan].bit.Bypas)
|
||||||
|
{
|
||||||
|
sens_error[chan].all = 0;
|
||||||
|
sens_error[chan].bit.Bypas = 1;
|
||||||
|
Modbus[chan+DATASTART].all = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Numb = ADC_table[chan];
|
||||||
|
|
||||||
|
if(cTermoCal)
|
||||||
|
{
|
||||||
|
Modbus[chan+DATASTART].all = (int)(Numb);
|
||||||
|
return; // øòîáû ñòðóêòóðà îøèáîê íå âëåçàëà â äàííûå
|
||||||
|
}
|
||||||
|
|
||||||
|
Power = (Numb * tmpK[chan]+5)/10.0; // powK[sens_type[chan]];
|
||||||
|
|
||||||
|
Modbus[chan+DATASTART].all = Power;
|
||||||
|
|
||||||
|
error.all = 0;
|
||||||
|
ignor = sens_error[chan].bit.Ignor;
|
||||||
|
|
||||||
|
if(Power <sens_lo_edge[chan])
|
||||||
|
{
|
||||||
|
error.bit.Out = 1;
|
||||||
|
|
||||||
|
if(sens_error[sens_pair[chan]].bit.Out)
|
||||||
|
{
|
||||||
|
if(!ignor)
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
} }
|
||||||
|
|
||||||
|
// Ïîâûøåííîå íàïðàæåíèå
|
||||||
|
if(Power > sens_hi_edge[chan])
|
||||||
|
{
|
||||||
|
error.bit.Hyper = 1;
|
||||||
|
if(!ignor)
|
||||||
|
error.bit.Stop = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(chan>3)
|
||||||
|
{
|
||||||
|
bitt = (chan-4)*2;
|
||||||
|
error.bit.Contr1 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++;
|
||||||
|
error.bit.Contr2 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(error.all)
|
||||||
|
if(!ignor)
|
||||||
|
chk.bit.Alarm = 1;
|
||||||
|
reset_errs(chan,error);
|
||||||
|
}
|
||||||
136
measure.h
Normal file
136
measure.h
Normal file
@ -0,0 +1,136 @@
|
|||||||
|
// âãâ
|
||||||
|
#ifndef _MEASURE
|
||||||
|
#define _MEASURE
|
||||||
|
|
||||||
|
void Init_sensors(void);
|
||||||
|
void Init_optic(void);
|
||||||
|
void Init_packMask(void);
|
||||||
|
void Temper_count(int chan);
|
||||||
|
void Current_count(int chan);
|
||||||
|
void Power_count(int chan);
|
||||||
|
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
unsigned int Tear :1;
|
||||||
|
unsigned int Stick :1;
|
||||||
|
unsigned int Wry :1;
|
||||||
|
unsigned int Out :1;
|
||||||
|
unsigned int Over :1;
|
||||||
|
unsigned int Hyper :1;
|
||||||
|
unsigned int Contr1 :1;
|
||||||
|
unsigned int Contr2 :1;
|
||||||
|
|
||||||
|
unsigned int Stop :1;
|
||||||
|
unsigned int Ready :1;
|
||||||
|
unsigned int res :3;
|
||||||
|
unsigned int Latch :1;
|
||||||
|
unsigned int Ignor :1;
|
||||||
|
unsigned int Bypas :1;
|
||||||
|
|
||||||
|
} bit;
|
||||||
|
unsigned int all;
|
||||||
|
|
||||||
|
} ERROR;
|
||||||
|
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
unsigned int Error :1;
|
||||||
|
unsigned int Alarm :1;
|
||||||
|
unsigned int OverHeat :1;
|
||||||
|
unsigned int SubHeat :1;
|
||||||
|
unsigned int OutHeat :1;
|
||||||
|
unsigned int Test_lamp :1;
|
||||||
|
|
||||||
|
} bit;
|
||||||
|
unsigned int all;
|
||||||
|
|
||||||
|
} FLAG;
|
||||||
|
|
||||||
|
#define NOER 0xE000
|
||||||
|
#define EROR 0x01FF
|
||||||
|
|
||||||
|
#define SIG_FREQ 4000 // Ãö
|
||||||
|
#define READY_FREQ 1000 // Ãö
|
||||||
|
#define BLINK_FREQ 2 // Ãö
|
||||||
|
#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // Ãö (777*5)
|
||||||
|
#define DAC_FREQ 50 // Ãö
|
||||||
|
|
||||||
|
#define LOAD_TIME 10 // sec
|
||||||
|
|
||||||
|
|
||||||
|
#define SENS_ERR_WAIT 10
|
||||||
|
|
||||||
|
#define maximum_bright 10
|
||||||
|
|
||||||
|
/*
|
||||||
|
#define SNOW 1720.0 //1920.0
|
||||||
|
#define BOIL 2360.0 //2561.0
|
||||||
|
|
||||||
|
#define tmp_T_0 0.0
|
||||||
|
#define tmp_T_1 200.00
|
||||||
|
#define tmp_A1_0 978.0
|
||||||
|
#define tmp_A1_1 1686.0
|
||||||
|
#define tmp_A2_0 1017.0
|
||||||
|
#define tmp_A2_1 1736.0
|
||||||
|
#define eta_A1 1002.0
|
||||||
|
#define eta_A2 1542.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define tmp_T_0 84.31 // 68Om
|
||||||
|
#define tmp_T_1 234.19 // 100Om
|
||||||
|
#define tmp_A1_0 540.0 // êàíàë 1 68Îì
|
||||||
|
#define tmp_A2_0 500.0 // êàíàë 1 100Îì
|
||||||
|
#define tmp_A1_1 1055.0 // êàíàë 2 68Îì
|
||||||
|
#define tmp_A2_1 1060.0 // êàíàë 2 100Îì
|
||||||
|
|
||||||
|
|
||||||
|
#define ZERO 27
|
||||||
|
|
||||||
|
#define mka300 2040
|
||||||
|
#define mka400 2700
|
||||||
|
|
||||||
|
#define C100 650
|
||||||
|
#define C150 2370
|
||||||
|
|
||||||
|
#define Cooling 5 // (°Ñ) Ãèñòåðåçèñ ïî ñíàòèþ ïåðåãðåâà
|
||||||
|
|
||||||
|
#define COSPi6 0.86602540378443864676372317075294
|
||||||
|
|
||||||
|
#define RADIX2 1.4142135623730950488016887242097
|
||||||
|
|
||||||
|
#define CURRENT 1 // òîê
|
||||||
|
#define VOLTAGE 2 // íàïðàæåíèå
|
||||||
|
|
||||||
|
#define POWER_380 3 // ïèòàíèå 380Â
|
||||||
|
#define POWER_220 4 // ïèòàíèå 220Â
|
||||||
|
#define POWER_31 5 // ïèòàíèå 31Â
|
||||||
|
#define POWER_24 6 // ïèòàíèå 24Â
|
||||||
|
#define VIRT_24 7 // ïèòàíèå 24Â
|
||||||
|
#define POWER_15 8 // ïèòàíèå 15Â
|
||||||
|
#define TERMO_AD 9 // òåðìîäàò÷èê ìåëêîñõåìà
|
||||||
|
#define TERMO_RS 10 // òåðìîäàò÷èê ðåçèñòîð
|
||||||
|
#define OPTIC 11 // îïòîêàíàë ìåãîììåòðà
|
||||||
|
|
||||||
|
extern int MAX_TPL_CANAL;
|
||||||
|
|
||||||
|
extern FILTERBAT filter[];
|
||||||
|
|
||||||
|
extern ERROR * sens_error;
|
||||||
|
extern int * sens_hi_edge;
|
||||||
|
extern int * sens_lo_edge;
|
||||||
|
|
||||||
|
extern int adc0[],tmp0[];
|
||||||
|
|
||||||
|
#define Zero_lev (adc0+12) //((int *)&Modbus[0x74])
|
||||||
|
|
||||||
|
extern float tmpK[];
|
||||||
|
extern FLAG chk,sig;
|
||||||
|
extern int sens_type[];
|
||||||
|
|
||||||
|
extern int period_ready;
|
||||||
|
|
||||||
|
#endif //_MEASURE
|
||||||
355
message.c
Normal file
355
message.c
Normal file
@ -0,0 +1,355 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "package.h"
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "crc16.h"
|
||||||
|
#include "cntrl_adr.h"
|
||||||
|
#include "bios_dsp.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "message.h"
|
||||||
|
|
||||||
|
|
||||||
|
#include "ADC.h"
|
||||||
|
#include "peripher.h"
|
||||||
|
|
||||||
|
#include "ecan.h"
|
||||||
|
#include "spise2p.h"
|
||||||
|
#include "i2c.h"
|
||||||
|
|
||||||
|
WORDE Modbus[ANSWER_LEN+1];
|
||||||
|
WORDE reply[REPLY_LEN];
|
||||||
|
|
||||||
|
unsigned int param[ANSWER_LEN+1];
|
||||||
|
|
||||||
|
LONGE* outputs;
|
||||||
|
|
||||||
|
int DataAnalog1,DataAnalog2;
|
||||||
|
|
||||||
|
ERROR * sens_error;
|
||||||
|
int * sens_hi_edge;
|
||||||
|
int * sens_lo_edge;
|
||||||
|
|
||||||
|
unsigned int Maska[3][9];
|
||||||
|
|
||||||
|
void Default_params()
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for(i=0;i<ANSWER_LEN;i++)
|
||||||
|
{
|
||||||
|
Modbus[i].all = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
Brightness = 5;
|
||||||
|
|
||||||
|
LastMode = Addrr;
|
||||||
|
|
||||||
|
Cancount[0] = 10; // ïàóçà ìåæäó ïîñûëêàìè CAN
|
||||||
|
Cancount[1] = 95; // ïàóçà ìåæäó ïîñûëêàìè CAN
|
||||||
|
Cancount[2] = 1; // ïàóçà ìåæäó ïîñûëêàìè CAN
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM)
|
||||||
|
{
|
||||||
|
sens_hi_edge[0 ] = 55;
|
||||||
|
sens_hi_edge[1 ] = 55;
|
||||||
|
sens_hi_edge[2 ] = 55;
|
||||||
|
sens_hi_edge[3 ] = 55;
|
||||||
|
|
||||||
|
sens_hi_edge[4 ] = 65;
|
||||||
|
sens_hi_edge[5 ] = 65;
|
||||||
|
|
||||||
|
sens_hi_edge[7 ] = 50;
|
||||||
|
sens_hi_edge[8 ] = 50;
|
||||||
|
sens_hi_edge[9 ] = 50;
|
||||||
|
sens_hi_edge[10] = 50;
|
||||||
|
sens_hi_edge[11] = 50;
|
||||||
|
|
||||||
|
sens_lo_edge[0 ] = 50;
|
||||||
|
sens_lo_edge[1 ] = 50;
|
||||||
|
sens_lo_edge[2 ] = 50;
|
||||||
|
sens_lo_edge[3 ] = 50;
|
||||||
|
|
||||||
|
sens_lo_edge[4 ] = 60;
|
||||||
|
sens_lo_edge[5 ] = 60;
|
||||||
|
|
||||||
|
sens_lo_edge[7 ] = 45;
|
||||||
|
sens_lo_edge[8 ] = 45;
|
||||||
|
sens_lo_edge[9 ] = 45;
|
||||||
|
sens_lo_edge[10] = 45;
|
||||||
|
sens_lo_edge[11] = 45;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Currentoz)
|
||||||
|
{
|
||||||
|
for(i=12;i<16;i++)
|
||||||
|
{
|
||||||
|
sens_hi_edge[i] = 2428;
|
||||||
|
sens_lo_edge[i] = 1462;
|
||||||
|
}
|
||||||
|
|
||||||
|
Modbus[12].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[13].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[14].bit.bitE = 1; // Ignore
|
||||||
|
Modbus[15].bit.bitE = 1; // Ignore
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Mode==adr_ISOL)
|
||||||
|
{
|
||||||
|
optopowse = 200;
|
||||||
|
optofiltr = 20; //200;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Mode==adr_SHKF)
|
||||||
|
{
|
||||||
|
Modbus[0x02].bit.bitE = 1; // Ignore êëèìàò êîíòðîëü
|
||||||
|
Modbus[0x03].bit.bitE = 1; // Ignore êëèìàò êîíòðîëü
|
||||||
|
|
||||||
|
for(i=0;i<17;i++)
|
||||||
|
{
|
||||||
|
if(sens_type[i]==POWER_380)
|
||||||
|
{ sens_lo_edge[i] = 300;
|
||||||
|
sens_hi_edge[i] = 430; }
|
||||||
|
if(sens_type[i]==POWER_220)
|
||||||
|
{ sens_lo_edge[i] = 170;
|
||||||
|
sens_hi_edge[i] = 250; }
|
||||||
|
if(sens_type[i]==POWER_31)
|
||||||
|
{ sens_lo_edge[i] = 20;
|
||||||
|
sens_hi_edge[i] = 40; }
|
||||||
|
if(sens_type[i]==POWER_24 || sens_type[i]==VIRT_24)
|
||||||
|
{ sens_lo_edge[i] = 15;
|
||||||
|
sens_hi_edge[i] = 30; }
|
||||||
|
if(sens_type[i]==POWER_15)
|
||||||
|
{ sens_lo_edge[i] = 10;
|
||||||
|
sens_hi_edge[i] = 20; }
|
||||||
|
if(sens_type[i]==TERMO_AD)
|
||||||
|
{ sens_lo_edge[i] = 60;
|
||||||
|
sens_hi_edge[i] = 65;
|
||||||
|
} } } }
|
||||||
|
|
||||||
|
void Load_params()
|
||||||
|
{
|
||||||
|
unsigned int i,crc;
|
||||||
|
|
||||||
|
sens_error = ((ERROR *)&Modbus[start_sens_error]);
|
||||||
|
sens_hi_edge = ((int *)&Modbus[start_sens_hi_edge]);
|
||||||
|
sens_lo_edge = ((int *)&Modbus[start_sens_lo_edge]);
|
||||||
|
|
||||||
|
Seeprom_read(0x3FFF-(ANSWER_LEN+1), param, (ANSWER_LEN+1)*2);
|
||||||
|
crc = get_crc16(param,ANSWER_LEN);
|
||||||
|
if( (crc==param[ANSWER_LEN]) &&
|
||||||
|
(crc !=0xFFFF) &&
|
||||||
|
(Addrr == param[126]) )
|
||||||
|
{
|
||||||
|
for(i=0;i<ANSWER_LEN;i++) Modbus[i].all = param[i];
|
||||||
|
Commands=0;
|
||||||
|
|
||||||
|
if(Desk==dsk_ISOL)
|
||||||
|
{
|
||||||
|
if(optopowse==0) optopowse=200;
|
||||||
|
if(optofiltr==0) optofiltr=20; //200
|
||||||
|
} }
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Default_params();
|
||||||
|
Commands=0;
|
||||||
|
Save_params();
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=0;i<4;i++) Zeroes[i] = adc0[12+i];
|
||||||
|
}
|
||||||
|
|
||||||
|
void Save_params()
|
||||||
|
{
|
||||||
|
unsigned int i,dif=0;
|
||||||
|
|
||||||
|
for(i=0;i<ANSWER_LEN;i++)
|
||||||
|
if(param[i] != (unsigned int)Modbus[i].all)
|
||||||
|
{
|
||||||
|
param[i] = Modbus[i].all;
|
||||||
|
dif=1;
|
||||||
|
}
|
||||||
|
if(dif)
|
||||||
|
{
|
||||||
|
param[ANSWER_LEN] = get_crc16(param,ANSWER_LEN);
|
||||||
|
Seeprom_write(0x3FFF-(ANSWER_LEN+1),param,(ANSWER_LEN+1)*2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void Load_caliber()
|
||||||
|
{
|
||||||
|
unsigned int buf[2],crc;
|
||||||
|
int i,line;
|
||||||
|
int adcLOW,adcHI;
|
||||||
|
float tmpLOW,tmpHI;
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM)
|
||||||
|
{
|
||||||
|
for(i=0;i<12;i++)
|
||||||
|
{
|
||||||
|
line = i*4;
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
if(sens_type[i]==TERMO_AD) { buf[0] = 330; buf[1] = 30; }
|
||||||
|
else { buf[0] = 0; buf[1] = 273; }
|
||||||
|
}
|
||||||
|
adcLOW = buf[0];
|
||||||
|
tmpLOW = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
if(sens_type[i]==TERMO_AD) { buf[0] = 4000; buf[1] = 360; }
|
||||||
|
else { buf[0] = 3790; buf[1] = 473; }
|
||||||
|
}
|
||||||
|
adcHI = buf[0];
|
||||||
|
tmpHI = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
adc0[i] = adcLOW;
|
||||||
|
tmp0[i] = tmpLOW;
|
||||||
|
tmpK[i] = (tmpHI - tmpLOW)/(adcHI - adcLOW);
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=12;i<16;i++)
|
||||||
|
{
|
||||||
|
line = i*4;
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
buf[0] = 2047; buf[1] = 0;
|
||||||
|
}
|
||||||
|
adcLOW = buf[0];
|
||||||
|
tmpLOW = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
buf[0] = 2310; buf[1] = 0; // #define cur_K 2.31//2.352
|
||||||
|
}
|
||||||
|
adcHI = buf[0];
|
||||||
|
tmpHI = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
adc0[i] = adcLOW;
|
||||||
|
tmp0[i] = tmpLOW;
|
||||||
|
tmpK[i] = adcHI/1000.0;
|
||||||
|
}
|
||||||
|
for(i=0;i<4;i++) Zeroes[i] = adc0[12+i];
|
||||||
|
}
|
||||||
|
if(Desk==dsk_SHKF)
|
||||||
|
for(i=0;i<17;i++)
|
||||||
|
{
|
||||||
|
line = i*4;
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
if(sens_type[i]==TERMO_AD) { buf[0] = 1635; buf[1] = 240; }
|
||||||
|
else { buf[0] = 0; buf[1] = 0; }
|
||||||
|
}
|
||||||
|
adcLOW = buf[0];
|
||||||
|
tmpLOW = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||||
|
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||||
|
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||||
|
if(crc!=get_crc16(buf,2))
|
||||||
|
{
|
||||||
|
if(sens_type[i]==TERMO_AD) { buf[0] = 4019; buf[1] = 590; } else
|
||||||
|
if(sens_type[i]==POWER_380) { buf[0] = 2450; buf[1] = 3800; } else
|
||||||
|
if(sens_type[i]==POWER_220) { buf[0] = 2450; buf[1] = 2200; } else
|
||||||
|
if(sens_type[i]==VIRT_24) { buf[0] = 1; buf[1] = 240; } else
|
||||||
|
{ buf[0] = 2450; buf[1] = 240; }
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
//if(sens_type[i]==VIRT_24) { buf[0] = 1; buf[1] = 240; }
|
||||||
|
|
||||||
|
adcHI = buf[0];
|
||||||
|
tmpHI = buf[1];
|
||||||
|
//-------------------------------------------------------------------
|
||||||
|
adc0[i] = adcLOW;
|
||||||
|
tmp0[i] = tmpLOW;
|
||||||
|
tmpK[i] = (tmpHI - tmpLOW)/(adcHI - adcLOW);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/***************************************************************/
|
||||||
|
/* Ïåðåäà÷à äàííûõ ïî ïðîòîêîëó ModBus - êîìàíäà 3
|
||||||
|
×òåíèå à÷ååê äàííûõ */
|
||||||
|
/***************************************************************/
|
||||||
|
void ReceiveCommandModbus3(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned int crc, Address_MB, Length_MB, i;
|
||||||
|
|
||||||
|
// ïîëó÷èëè íà÷àëüíûé àäðåñ ÷òåíèà
|
||||||
|
Address_MB =/*(rs_arr->RS_Header[2] << 8) |*/ rs_arr->RS_Header[3];
|
||||||
|
|
||||||
|
// ïîëó÷èëè êîëè÷åñòâî ñëîâ äàííûõ
|
||||||
|
Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
// Îòñûëêà
|
||||||
|
/* Ïîñ÷èòàëè êîíòðîëüíóþ ñóììó ïåðåä ñàìîé ïîñûëêîé */
|
||||||
|
|
||||||
|
rs_arr->buffer[0] = CNTRL_ADDR;
|
||||||
|
rs_arr->buffer[1] = CMD_MODBUS_3;
|
||||||
|
rs_arr->buffer[2] = Length_MB*2;
|
||||||
|
|
||||||
|
for (i=0;i<Length_MB;i++)
|
||||||
|
{
|
||||||
|
rs_arr->buffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi);
|
||||||
|
rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo);
|
||||||
|
}
|
||||||
|
|
||||||
|
crc = 0xffff;
|
||||||
|
crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3);
|
||||||
|
|
||||||
|
rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc);
|
||||||
|
rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc);
|
||||||
|
|
||||||
|
rs_arr->buffer[Length_MB*2+5] = 0;
|
||||||
|
rs_arr->buffer[Length_MB*2+6] = 0;
|
||||||
|
rs_arr->buffer[Length_MB*2+7] = 0;
|
||||||
|
rs_arr->buffer[Length_MB*2+8] = 0;
|
||||||
|
|
||||||
|
rs_arr->flag_TIMEOUT_to_Send=true;
|
||||||
|
RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ReceiveCommandModbus6(RS_DATA *rs_arr)
|
||||||
|
{
|
||||||
|
unsigned int Address_MB, Data_MB, i;
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
// Îòñûëêà
|
||||||
|
/* Îòïðàâëàåì íàçàä òî æå ñàìîå */
|
||||||
|
|
||||||
|
for (i=0;i<8;i++)
|
||||||
|
rs_arr->buffer[i] = rs_arr->RS_Header[i];
|
||||||
|
|
||||||
|
// ïîëó÷èëè íà÷àëüíûé àäðåñ çàïèñè
|
||||||
|
Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]);
|
||||||
|
|
||||||
|
// ïîëó÷èëè ñëîâî äàííûõ
|
||||||
|
Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
|
||||||
|
|
||||||
|
Modbus[Address_MB].all = Data_MB;
|
||||||
|
|
||||||
|
rs_arr->flag_TIMEOUT_to_Send=true;
|
||||||
|
RS_Send(rs_arr, rs_arr->buffer, 10);
|
||||||
|
}
|
||||||
51
message.h
Normal file
51
message.h
Normal file
@ -0,0 +1,51 @@
|
|||||||
|
#ifndef MESSAGE_H
|
||||||
|
#define MESSAGE_H
|
||||||
|
|
||||||
|
typedef unsigned char CHAR;
|
||||||
|
|
||||||
|
#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6
|
||||||
|
#define REPLY_LEN 0x19
|
||||||
|
|
||||||
|
#define byte_hi byte_1
|
||||||
|
#define byte_lo byte_0
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned char Address; // Àäðåñ êîíòðîëëåðà
|
||||||
|
unsigned char Number; // Íîìåð êîìàíäû
|
||||||
|
|
||||||
|
BAITE byte0;
|
||||||
|
BAITE byte1;
|
||||||
|
BAITE byte2;
|
||||||
|
BAITE byte3;
|
||||||
|
BAITE byte4;
|
||||||
|
BAITE byte5;
|
||||||
|
BAITE byte6;
|
||||||
|
BAITE byte7;
|
||||||
|
|
||||||
|
unsigned char crc_lo;
|
||||||
|
unsigned char crc_hi;
|
||||||
|
unsigned char add_byte;
|
||||||
|
} CMD_TO_TMS;
|
||||||
|
|
||||||
|
extern WORDE Modbus[];
|
||||||
|
extern WORDE reply[];
|
||||||
|
|
||||||
|
extern LONGE* outputs;
|
||||||
|
|
||||||
|
extern int DataAnalog1,DataAnalog2;
|
||||||
|
|
||||||
|
extern unsigned int Maska[][9];
|
||||||
|
|
||||||
|
//void ReceiveCommand(RS_DATA *rs_arr);
|
||||||
|
void ReceiveCommandModbus3(RS_DATA *rs_arr);
|
||||||
|
void ReceiveCommandModbus6(RS_DATA *rs_arr);
|
||||||
|
|
||||||
|
void reset_errs(int sens, ERROR er);
|
||||||
|
|
||||||
|
void Save_params(void);
|
||||||
|
void Load_params(void);
|
||||||
|
void Load_caliber(void);
|
||||||
|
void Default_params(void);
|
||||||
|
|
||||||
|
#endif //MESSAGE_H
|
||||||
56
package.h
Normal file
56
package.h
Normal file
@ -0,0 +1,56 @@
|
|||||||
|
#ifndef PACKAGE
|
||||||
|
#define PACKAGE
|
||||||
|
|
||||||
|
#define TERMOPAIR 14
|
||||||
|
#define CURRENTOS (TERMOPAIR*2)
|
||||||
|
#define DATASTART 24
|
||||||
|
|
||||||
|
//-----------------------------------------------
|
||||||
|
#define adr_REC1 1
|
||||||
|
#define adr_REC2 2
|
||||||
|
#define adr_INV1 3
|
||||||
|
#define adr_INV2 4
|
||||||
|
#define adr_SHKF 5
|
||||||
|
#define adr_ISOL 6
|
||||||
|
//-----------------------------------------------
|
||||||
|
|
||||||
|
//-----------------------------------------------
|
||||||
|
#define dsk_COMM 1
|
||||||
|
#define dsk_SHKF 2
|
||||||
|
#define dsk_ISOL 3
|
||||||
|
//-----------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#define CAN_send_start 0 // Àäðåñ ïåðâîãî ïåðåäàâàåìîãî
|
||||||
|
#define CAN_send_finis 0x6F // Àäðåñ ïîñëåäíåãî ïåðåäàâàåìîãî
|
||||||
|
|
||||||
|
#define start_sens_error 0
|
||||||
|
#define start_sens_hi_edge 48
|
||||||
|
#define start_sens_lo_edge 72
|
||||||
|
|
||||||
|
#define optopowse Modbus[0x60].all // ïàóçà ìåæäó çàïðîñàìè, ms
|
||||||
|
#define optofiltr Modbus[0x61].all // êîýôôèöèåíò ôèëüòðàöèè
|
||||||
|
|
||||||
|
#define Brightness Modbus[0x64].all // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê
|
||||||
|
|
||||||
|
#define Cancount ((int *)&Modbus[0x65])
|
||||||
|
|
||||||
|
#define Zeroes ((int *)&Modbus[0x70])
|
||||||
|
|
||||||
|
#define LastMode Modbus[126].all
|
||||||
|
|
||||||
|
#define Commands Modbus[127].all
|
||||||
|
#define cTestLamp Modbus[127].bit.bit0
|
||||||
|
#define cSetZero Modbus[127].bit.bit1
|
||||||
|
#define cSaveParam Modbus[127].bit.bit2
|
||||||
|
#define cDefParam Modbus[127].bit.bit3
|
||||||
|
|
||||||
|
#define cTermoCal Modbus[127].bit.bit4
|
||||||
|
#define cReadCal Modbus[127].bit.bit5
|
||||||
|
|
||||||
|
#define cExtLamp Modbus[127].bit.bit6
|
||||||
|
#define cExtLite Modbus[127].bit.bit7
|
||||||
|
|
||||||
|
|
||||||
|
#endif //PACKAGE
|
||||||
|
|
||||||
143
peripher.c
Normal file
143
peripher.c
Normal file
@ -0,0 +1,143 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "message.h"
|
||||||
|
|
||||||
|
#include "package.h"
|
||||||
|
|
||||||
|
#include "peripher.h"
|
||||||
|
#include "GPIO_table.h"
|
||||||
|
|
||||||
|
|
||||||
|
int Mode,Desk,Addrr,TermoAD=0,TermoRS=0,TermoSW=0,Currentoz=0;
|
||||||
|
LONGE Inputs;
|
||||||
|
|
||||||
|
int ExtraCanal[24];
|
||||||
|
|
||||||
|
void get_Mode()
|
||||||
|
{
|
||||||
|
int i,qua;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 00—11
|
||||||
|
GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 19—27
|
||||||
|
GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFCC0; // 32—34, 36
|
||||||
|
GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 48—53, 58—63
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPADIR.bit.GPIO20 = 0;
|
||||||
|
GpioCtrlRegs.GPADIR.bit.GPIO21 = 0;
|
||||||
|
GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
|
||||||
|
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
Mode=0;
|
||||||
|
|
||||||
|
qua=0;
|
||||||
|
for(i=0;i<100;i++)
|
||||||
|
qua += !GpioDataRegs.GPADAT.bit.GPIO22;
|
||||||
|
if(qua>50) Mode += 1;
|
||||||
|
|
||||||
|
qua=0;
|
||||||
|
for(i=0;i<100;i++)
|
||||||
|
qua += !GpioDataRegs.GPADAT.bit.GPIO20;
|
||||||
|
if(qua>50) Mode += 2;
|
||||||
|
|
||||||
|
qua=0;
|
||||||
|
for(i=0;i<100;i++)
|
||||||
|
qua += !GpioDataRegs.GPADAT.bit.GPIO21;
|
||||||
|
if(qua>50) Mode += 4;
|
||||||
|
|
||||||
|
Addrr = Mode*2;
|
||||||
|
|
||||||
|
Mode+= 1;
|
||||||
|
|
||||||
|
qua=0;
|
||||||
|
for(i=0;i<100;i++)
|
||||||
|
qua += !GpioDataRegs.GPBDAT.bit.GPIO51;
|
||||||
|
if(qua>50) Addrr += 1;
|
||||||
|
|
||||||
|
if( (Mode==adr_REC1)||(Mode==adr_REC2)) Currentoz = 1;
|
||||||
|
if( (Mode==adr_REC1)||(Mode==adr_REC2)||
|
||||||
|
(Mode==adr_INV1)||(Mode==adr_INV2)) Desk = dsk_COMM;
|
||||||
|
if (Mode==adr_SHKF) Desk = dsk_SHKF;
|
||||||
|
if (Mode==adr_ISOL) Desk = dsk_ISOL;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
switch(Desk)
|
||||||
|
{
|
||||||
|
case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR;
|
||||||
|
GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break;
|
||||||
|
|
||||||
|
case dsk_SHKF: GpioCtrlRegs.GPADIR.all = VEPP_GPADIR;
|
||||||
|
GpioCtrlRegs.GPBDIR.all = VEPP_GPBDIR; break;
|
||||||
|
|
||||||
|
case dsk_ISOL: GpioCtrlRegs.GPADIR.all = ISOL_GPADIR;
|
||||||
|
GpioCtrlRegs.GPBDIR.all = ISOL_GPBDIR; break;
|
||||||
|
}
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void get_Inputs()
|
||||||
|
{
|
||||||
|
static long butthurt[2] ={0,0};
|
||||||
|
unsigned long butt=0;
|
||||||
|
|
||||||
|
if(Desk==dsk_COMM)
|
||||||
|
{
|
||||||
|
if(!GpioDataRegs.GPADAT.bit.GPIO7) butthurt[0]=0;
|
||||||
|
else if(butthurt[0]<MAX_BUTTHURT) butthurt[0]++;
|
||||||
|
if(butthurt[0]<MAX_BUTTHURT) butt =1;
|
||||||
|
|
||||||
|
if(!GpioDataRegs.GPADAT.bit.GPIO6) butthurt[1]=0;
|
||||||
|
else if(butthurt[1]<MAX_BUTTHURT) butthurt[1]++;
|
||||||
|
if(butthurt[1]<MAX_BUTTHURT) butt +=2;
|
||||||
|
|
||||||
|
if(Mode<adr_INV1)
|
||||||
|
{
|
||||||
|
if(!GpioDataRegs.GPADAT.bit.GPIO26) butt += 4;
|
||||||
|
if(!GpioDataRegs.GPADAT.bit.GPIO23) butt += 8;
|
||||||
|
} }
|
||||||
|
|
||||||
|
if(Desk==dsk_SHKF)
|
||||||
|
{
|
||||||
|
if(GpioDataRegs.GPBDAT.bit.GPIO58) butt += 0x0000001;
|
||||||
|
if(GpioDataRegs.GPBDAT.bit.GPIO61) butt += 0x0000002;
|
||||||
|
|
||||||
|
if(GpioDataRegs.GPBDAT.bit.GPIO53) butt += 0x00000010;
|
||||||
|
if(GpioDataRegs.GPBDAT.bit.GPIO52) butt += 0x00000020;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO24) butt += 0x00000040;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO23) butt += 0x00000080;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO27) butt += 0x00000100;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO26) butt += 0x00000200;
|
||||||
|
if(GpioDataRegs.GPBDAT.bit.GPIO36) butt += 0x00000400;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO25) butt += 0x00000800;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO0) butt += 0x00001000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO2) butt += 0x00002000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO4) butt += 0x00004000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO6) butt += 0x00008000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO8) butt += 0x00010000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO10) butt += 0x00020000;
|
||||||
|
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO1) butt += 0x00400000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO3) butt += 0x00800000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO7) butt += 0x01000000;
|
||||||
|
if(GpioDataRegs.GPADAT.bit.GPIO9) butt += 0x02000000;
|
||||||
|
|
||||||
|
// ExtraCanal1 = !GpioDataRegs.GPADAT.bit.GPIO5;
|
||||||
|
// ExtraCanal2 = !GpioDataRegs.GPADAT.bit.GPIO11;
|
||||||
|
|
||||||
|
ExtraCanal[15] = (!GpioDataRegs.GPADAT.bit.GPIO1) | (!GpioDataRegs.GPADAT.bit.GPIO3);
|
||||||
|
ExtraCanal[16] = (!GpioDataRegs.GPADAT.bit.GPIO7) | (!GpioDataRegs.GPADAT.bit.GPIO9);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Desk==dsk_ISOL)
|
||||||
|
{
|
||||||
|
if(!GpioDataRegs.GPBDAT.bit.GPIO62) butt += 0x0000001;
|
||||||
|
}
|
||||||
|
|
||||||
|
Inputs.all = butt;
|
||||||
|
}
|
||||||
|
|
||||||
28
peripher.h
Normal file
28
peripher.h
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||||
|
|
||||||
|
extern int Mode,Desk,Addrr,TermoAD,TermoRS,TermoSW,Currentoz;
|
||||||
|
extern int ExtraCanal[];
|
||||||
|
|
||||||
|
// READY ---------------------------------------------------------
|
||||||
|
static inline void dat_READY(int x)
|
||||||
|
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBDAT.bit.GPIO60=!x; else
|
||||||
|
GpioDataRegs.GPBDAT.bit.GPIO59=!x; }
|
||||||
|
static inline void set_READY(void)
|
||||||
|
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBCLEAR.bit.GPIO60=1; else
|
||||||
|
GpioDataRegs.GPBCLEAR.bit.GPIO59=1; }
|
||||||
|
static inline void clear_READY(void)
|
||||||
|
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBSET.bit.GPIO60=1; else
|
||||||
|
GpioDataRegs.GPBSET.bit.GPIO59=1; }
|
||||||
|
static inline void toggle_READY(void)
|
||||||
|
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO60=1;else
|
||||||
|
GpioDataRegs.GPBTOGGLE.bit.GPIO59=1;}
|
||||||
|
|
||||||
|
|
||||||
|
extern LONGE Inputs;
|
||||||
|
|
||||||
|
void select_tpl_canal(int n_tpl);
|
||||||
|
|
||||||
|
void get_Mode(void);
|
||||||
|
void get_Inputs(void);
|
||||||
|
|
||||||
|
#define MAX_BUTTHURT 250000
|
||||||
471
spise2p.c
Normal file
471
spise2p.c
Normal file
@ -0,0 +1,471 @@
|
|||||||
|
/*=================================================================
|
||||||
|
File name : SPISE2PD.C
|
||||||
|
|
||||||
|
Originator : Settu Duraisamy
|
||||||
|
C2000 Applications Team
|
||||||
|
Texas Instruments
|
||||||
|
|
||||||
|
Description : This file contains the SPI bus Serial EEPROM driver
|
||||||
|
implemented using Virtual SPI driver
|
||||||
|
|
||||||
|
Date : 6/30/2003 (DD/MM/YYYY)
|
||||||
|
====================================================================*/
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
|
||||||
|
#include "spise2p.h"
|
||||||
|
//#include "pins.h"
|
||||||
|
|
||||||
|
/* Instance the SPI bus serial EEPROM driver */
|
||||||
|
static SPISE2P_DRV se2p=SPISE2P_DRV_DEFAULTS;
|
||||||
|
|
||||||
|
/* Instance serial EEPROm data transfer structure */
|
||||||
|
static SE2P_DATA writeData, readData;
|
||||||
|
|
||||||
|
// Prototype statements for functions found within this file.
|
||||||
|
interrupt void PRD_TICK(void);
|
||||||
|
interrupt void cpu_timer2_isr(void);
|
||||||
|
|
||||||
|
int ccc=0;
|
||||||
|
|
||||||
|
/********************************************************************/
|
||||||
|
/******* SPI bus Serial EEPROM driver Initialization routine ********/
|
||||||
|
/********************************************************************/
|
||||||
|
|
||||||
|
void Seeprom_write( unsigned int adres,
|
||||||
|
unsigned int buf[],
|
||||||
|
unsigned int size)
|
||||||
|
{
|
||||||
|
unsigned int len;
|
||||||
|
|
||||||
|
// diod2_on();
|
||||||
|
|
||||||
|
CpuTimer2.InterruptCount=0;
|
||||||
|
CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||||
|
|
||||||
|
while(!spiSe2pFree(&se2p));
|
||||||
|
|
||||||
|
size = (size / WORD_LEN) + (size % WORD_LEN);
|
||||||
|
while(size)
|
||||||
|
{
|
||||||
|
len = PAGE_LEN - (adres % PAGE_LEN);
|
||||||
|
if(len > size) len=size;
|
||||||
|
|
||||||
|
writeData.dataPtr = buf;
|
||||||
|
writeData.nrData = len;
|
||||||
|
writeData.se2pAddr = adres * WORD_LEN;
|
||||||
|
|
||||||
|
spiSe2pWrite(&se2p, &writeData);
|
||||||
|
while(!spiSe2pFree(&se2p));
|
||||||
|
|
||||||
|
buf += len;
|
||||||
|
adres += len;
|
||||||
|
size -= len;
|
||||||
|
}
|
||||||
|
CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
|
||||||
|
// diod2_off();
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void Seeprom_read( unsigned int adres,
|
||||||
|
unsigned int buf[],
|
||||||
|
unsigned int size)
|
||||||
|
{
|
||||||
|
unsigned int len;
|
||||||
|
|
||||||
|
// diod2_on();
|
||||||
|
CpuTimer2.InterruptCount=0;
|
||||||
|
CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||||
|
|
||||||
|
while(!spiSe2pFree(&se2p));
|
||||||
|
|
||||||
|
size = (size / WORD_LEN) + (size % WORD_LEN);
|
||||||
|
while(size)
|
||||||
|
{
|
||||||
|
len = PAGE_LEN - (adres % PAGE_LEN);
|
||||||
|
if(len > size) len=size;
|
||||||
|
|
||||||
|
readData.dataPtr = buf;
|
||||||
|
readData.nrData = len;
|
||||||
|
readData.se2pAddr = adres * WORD_LEN;
|
||||||
|
|
||||||
|
spiSe2pRead(&se2p, &readData);
|
||||||
|
while(!spiSe2pFree(&se2p));
|
||||||
|
|
||||||
|
buf += len;
|
||||||
|
adres += len;
|
||||||
|
size -= len;
|
||||||
|
}
|
||||||
|
CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
|
||||||
|
// diod2_off();
|
||||||
|
}
|
||||||
|
|
||||||
|
void Init_Seeprom()
|
||||||
|
{
|
||||||
|
se2p.init(&se2p);
|
||||||
|
|
||||||
|
EALLOW; // This is needed to write to EALLOW protected registers
|
||||||
|
PieVectTable.TINT2 = &cpu_timer2_isr;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
InitCpuTimers(); // For this example, only initialize the Cpu Timers
|
||||||
|
// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
|
||||||
|
// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 10);
|
||||||
|
ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
|
||||||
|
|
||||||
|
IER |= M_INT14;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPISE2P_DRV_init(SPISE2P_DRV *eeprom)
|
||||||
|
{
|
||||||
|
/* Configure SPI-A pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be SPI functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
EALLOW;
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O)
|
||||||
|
GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output
|
||||||
|
GpioDataRegs.GPADAT.bit.GPIO19 = 0;
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
/* Configure the SPI: 8-bit, Rising edge with delay */
|
||||||
|
SpiaRegs.SPICCR.all=0x0007;
|
||||||
|
SpiaRegs.SPICTL.all=0x001F;
|
||||||
|
SpiaRegs.SPISTS.all=0x00;
|
||||||
|
|
||||||
|
SpiaRegs.SPIBRR = (LSPCLK / SPIBAUD_RATE) - 1;
|
||||||
|
|
||||||
|
SpiaRegs.SPIFFTX.all=0x8000;
|
||||||
|
SpiaRegs.SPIFFRX.all=0x0000;
|
||||||
|
SpiaRegs.SPIFFCT.all=0x00;
|
||||||
|
SpiaRegs.SPIPRI.all=0x0010;
|
||||||
|
|
||||||
|
/* Disable Chip Select of Serial EEPROM */
|
||||||
|
eeprom->csr=0;
|
||||||
|
eeprom->msgPtr=0;
|
||||||
|
|
||||||
|
SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPISE2P_DRV_csset()
|
||||||
|
{
|
||||||
|
GpioDataRegs.GPADAT.bit.GPIO19 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPISE2P_DRV_csclr()
|
||||||
|
{
|
||||||
|
GpioDataRegs.GPADAT.bit.GPIO19 = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned int spiSe2pFree(SPISE2P_DRV *se2p)
|
||||||
|
{
|
||||||
|
if(se2p->csr&0x3) return(0);
|
||||||
|
else return(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
|
||||||
|
{
|
||||||
|
se2p->msgPtr=msgPtr;
|
||||||
|
se2p->csr|=0x1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
|
||||||
|
{
|
||||||
|
se2p->msgPtr=msgPtr;
|
||||||
|
se2p->csr|=0x2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************/
|
||||||
|
/******* SPI bus Serial EEPROM driver Tick function *****************/
|
||||||
|
/********************************************************************/
|
||||||
|
|
||||||
|
interrupt void cpu_timer2_isr(void)
|
||||||
|
{ EALLOW;
|
||||||
|
CpuTimer2.InterruptCount++;
|
||||||
|
|
||||||
|
se2p.tick(&se2p);
|
||||||
|
|
||||||
|
// The CPU acknowledges the interrupt.
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom)
|
||||||
|
{
|
||||||
|
static unsigned int step=0;
|
||||||
|
static unsigned int dataCount=0;
|
||||||
|
static volatile unsigned int dummy=0;
|
||||||
|
|
||||||
|
switch(step)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
/* If write request is SET, then trigger the Write operation
|
||||||
|
If read request is SET, then trigger the Read operation
|
||||||
|
If Read request is also not SET, then continue to poll */
|
||||||
|
|
||||||
|
if(eeprom->csr&SPISE2P_WRRQ)
|
||||||
|
{ step=1;
|
||||||
|
eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/
|
||||||
|
eeprom->csclr();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(eeprom->csr&SPISE2P_RDRQ)
|
||||||
|
{ step=13;
|
||||||
|
eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */
|
||||||
|
eeprom->csclr();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
/************************************************************
|
||||||
|
*********** SPI bus EEPROM Write Starts from here ***********
|
||||||
|
*************************************************************
|
||||||
|
Prier to any attempt to write data to SPI serial EEPROM
|
||||||
|
Write Enable Latch must be set by issuing the WREN command */
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
|
||||||
|
step=2;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
/* Wait for VSPI State machine to send the WREN command and
|
||||||
|
serial EEPROM Chip Select must be brought to HIGH to set
|
||||||
|
the WREN latch */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{
|
||||||
|
dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
eeprom->csset();
|
||||||
|
|
||||||
|
step=3;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3:
|
||||||
|
/* Assert CS of Serial EEPROM and send WRITE command */
|
||||||
|
|
||||||
|
eeprom->csclr();
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
|
||||||
|
step=4;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
/* Wait for VSPI State machine to send the WRITE command */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
step=5;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 5:
|
||||||
|
/* Send Address */
|
||||||
|
|
||||||
|
#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||||
|
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
|
||||||
|
#endif
|
||||||
|
#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=6;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 6:
|
||||||
|
/* Wait for VSPI State machine to send the Address */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
step=7;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 7:
|
||||||
|
/* Send Data */
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT;
|
||||||
|
SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dataCount++;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=8;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 8:
|
||||||
|
/* Wait for VSPI State machine to send the Data.
|
||||||
|
If all the data are sent, then set the CS pin to HIGH
|
||||||
|
to program or write the data in EEPROM array */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
|
||||||
|
if (dataCount==eeprom->msgPtr->nrData)
|
||||||
|
{ eeprom->csset();
|
||||||
|
step=9;}
|
||||||
|
else
|
||||||
|
step=7; /* Write next data */
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
|
||||||
|
case 9:
|
||||||
|
/* Read the EEPROM status register to check whether the
|
||||||
|
data sent are indeed programmed to the EEPROM array.
|
||||||
|
Hence, send RDSR command to EEPROM to read status reg. */
|
||||||
|
|
||||||
|
eeprom->csclr();
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=10;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 10:
|
||||||
|
/* Wait for VSPI State machine to send RDSR command */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
step=11;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 11:
|
||||||
|
/* Send dummy Data to read Status reg. */
|
||||||
|
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=12;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 12:
|
||||||
|
/* Wait for VSPI State machine to clock out status reg.
|
||||||
|
Check, whether the data are written to the EEPROM array,
|
||||||
|
If written, then reset the WRIP(write in progress) and
|
||||||
|
WRRQ(Write request bit) and go back to STATE0 */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ eeprom->csset();
|
||||||
|
|
||||||
|
if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK )
|
||||||
|
step=9;
|
||||||
|
else
|
||||||
|
{ eeprom->csr&=(~SPISE2P_WRIP);
|
||||||
|
eeprom->csr&=(~SPISE2P_WRRQ);
|
||||||
|
step=0;
|
||||||
|
dataCount=0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 13:
|
||||||
|
/************************************************************
|
||||||
|
*********** SPI bus EEPROM Read Starts from here ***********
|
||||||
|
*************************************************************
|
||||||
|
Send READ Command to SPI bus serail EEPROM */
|
||||||
|
|
||||||
|
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_READ_CMD;
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=14;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 14:
|
||||||
|
/* Wait for VSPI State machine to send READ command */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
step=15;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 15:
|
||||||
|
/* Send Address */
|
||||||
|
|
||||||
|
#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||||
|
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
|
||||||
|
#endif
|
||||||
|
#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=16;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 16:
|
||||||
|
/* Wait for VSPI State machine to send Address */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||||
|
step=17;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 17:
|
||||||
|
/* Send Dummy value to clock out data from serial EEPROM */
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||||
|
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||||
|
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||||
|
step=18;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 18:
|
||||||
|
/* Wait for VSPI State machine to clk out data from EEPROM */
|
||||||
|
|
||||||
|
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||||
|
{
|
||||||
|
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||||
|
*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||||
|
*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF;
|
||||||
|
#endif
|
||||||
|
dataCount++;
|
||||||
|
step=19;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 19:
|
||||||
|
/* If all the data are read, terminate the read operation by
|
||||||
|
rising the CS. Then reset the RDIP (Read in progress) bit
|
||||||
|
and reset the RDRQ(Read request) bit and go back to STATE0 */
|
||||||
|
|
||||||
|
if (dataCount==eeprom->msgPtr->nrData)
|
||||||
|
{ eeprom->csset();
|
||||||
|
step=0;
|
||||||
|
dataCount=0;
|
||||||
|
eeprom->csr&=(~SPISE2P_RDIP);
|
||||||
|
eeprom->csr&=(~SPISE2P_RDRQ);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
step=17;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
134
spise2p.h
Normal file
134
spise2p.h
Normal file
@ -0,0 +1,134 @@
|
|||||||
|
/*=====================================================================
|
||||||
|
File name : SPISE2P.H
|
||||||
|
|
||||||
|
Originator : Settu Duraisamy
|
||||||
|
C2000 Applications Team
|
||||||
|
Texas Instruments
|
||||||
|
|
||||||
|
Description :
|
||||||
|
Header file containing object definitions, proto type
|
||||||
|
declaration and default object initializers for
|
||||||
|
SPI Serial EEPROM driver using VSPI
|
||||||
|
|
||||||
|
Date : 30/6/2003 (DD/MM/YYYY)
|
||||||
|
=======================================================================*/
|
||||||
|
|
||||||
|
#ifndef __SPISE2P_H__
|
||||||
|
|
||||||
|
#define __SPISE2P_H__
|
||||||
|
|
||||||
|
// ¨ìêîñòü ïàìàòè â áàéòàõ
|
||||||
|
#define SEEPROM_LEN 0x10000
|
||||||
|
|
||||||
|
#define NULL 0
|
||||||
|
|
||||||
|
#define SIXTEEN_BIT 15
|
||||||
|
#define EIGHT_BIT 07
|
||||||
|
|
||||||
|
/***************************************************************/
|
||||||
|
/* Configurable Parameter for SPI bus Serial EEPROM */
|
||||||
|
/***************************************************************/
|
||||||
|
#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT
|
||||||
|
#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT
|
||||||
|
#define SPIBAUD_REG_VAL 1//12
|
||||||
|
#define SPICLK_PHASE 1
|
||||||
|
#define SPICLK_POLARITY 0
|
||||||
|
|
||||||
|
#define SPIBAUD_RATE 100000
|
||||||
|
//10000000
|
||||||
|
|
||||||
|
/**************************************************************/
|
||||||
|
/**************************************************************/
|
||||||
|
|
||||||
|
/* Serial EEPROM Command words, left justified */
|
||||||
|
#define SPISE2P_READ_CMD 0x0300
|
||||||
|
#define SPISE2P_WRITE_CMD 0x0200
|
||||||
|
#define SPISE2P_WRDI_CMD 0x0400
|
||||||
|
#define SPISE2P_WREN_CMD 0x0600
|
||||||
|
#define SPISE2P_RDSR_CMD 0x0500
|
||||||
|
#define SPISE2P_WRSR_CMD 0x0100
|
||||||
|
|
||||||
|
#define SPISE2P_RDID_CMD 0x0A00
|
||||||
|
|
||||||
|
#define SPISE2P_DUMMY_DATA 0x0000
|
||||||
|
#define SPISE2P_BUSY_MASK 0x01
|
||||||
|
|
||||||
|
/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/
|
||||||
|
#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT
|
||||||
|
#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT
|
||||||
|
|
||||||
|
/* Status valus */
|
||||||
|
#define SPISE2P_WRRQ 1 /* Write Requset */
|
||||||
|
#define SPISE2P_RDRQ 2 /* Read request */
|
||||||
|
#define SPISE2P_WRIP 4 /* Write in progress */
|
||||||
|
#define SPISE2P_RDIP 8 /* Read in progress */
|
||||||
|
|
||||||
|
/* Message declaration */
|
||||||
|
typedef struct {
|
||||||
|
unsigned int *dataPtr; /* Data pointer */
|
||||||
|
unsigned long nrData; /* number of data */
|
||||||
|
unsigned long se2pAddr; /* se2pAddr */
|
||||||
|
}SE2P_DATA;
|
||||||
|
|
||||||
|
|
||||||
|
/* Object declaration */
|
||||||
|
typedef struct {
|
||||||
|
SE2P_DATA *msgPtr;
|
||||||
|
unsigned int csr; /* control/status register */
|
||||||
|
void (*init)(void *);
|
||||||
|
void (*tick)(void *);
|
||||||
|
void (*csset)(void);
|
||||||
|
void (*csclr)(void);
|
||||||
|
}SPISE2P_DRV;
|
||||||
|
|
||||||
|
#define SPISE2P_DRV_DEFAULTS { NULL,\
|
||||||
|
0,\
|
||||||
|
(void (*)(void *))SPISE2P_DRV_init,\
|
||||||
|
(void (*)(void *))SPISE2P_DRV_tick,\
|
||||||
|
(void (*)(void))SPISE2P_DRV_csset,\
|
||||||
|
(void (*)(void))SPISE2P_DRV_csclr}
|
||||||
|
|
||||||
|
typedef SPISE2P_DRV *SPISE2P_DRV_handle;
|
||||||
|
|
||||||
|
void SPISE2P_DRV_init(SPISE2P_DRV * );
|
||||||
|
void SPISE2P_DRV_tick(SPISE2P_DRV *);
|
||||||
|
void SPISE2P_DRV_csset(void);
|
||||||
|
void SPISE2P_DRV_csclr(void);
|
||||||
|
|
||||||
|
unsigned int spiSe2pFree(SPISE2P_DRV *se2p);
|
||||||
|
void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data);
|
||||||
|
void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data);
|
||||||
|
|
||||||
|
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||||
|
#define PROM_LEN 0x8000
|
||||||
|
#define PAGE_LEN 0x20
|
||||||
|
#define WORD_LEN 2
|
||||||
|
#else
|
||||||
|
#define PROM_LEN 0x4000
|
||||||
|
#define PAGE_LEN 0x40
|
||||||
|
#define WORD_LEN 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Óñòàíîâêà äðàéâåðà ñåðèàëüíîé EEPROM. **
|
||||||
|
** Èíèöèàëèçàöèà SPI è ïðî÷. Òàêæå íàñòðîéêà òàéìåðà. **
|
||||||
|
** Äðàéâåð ðàáîòàåò íà ïðåðûâàíèàõ îò òàéìåðà 2! */
|
||||||
|
void Init_Seeprom(void);
|
||||||
|
|
||||||
|
/* Çàïèñü áëîêà â SEEPROM. Ïàðàìåòðû òàêîâû: **
|
||||||
|
** adres - àäðåñ â åïðîìêå, êóäà ïèñàòü. **
|
||||||
|
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
|
||||||
|
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
|
||||||
|
** buf - óêàçàòåëü íà ïàìàòü, îòêóäà ïèñàòü. **
|
||||||
|
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
|
||||||
|
void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size);
|
||||||
|
|
||||||
|
/* ×òåíèå áëîêà èç SEEPROM. Ïàðàìåòðû òàêîâû: **
|
||||||
|
** adres - àäðåñ â åïðîìêå, îòêóäà ÷èòàòü. **
|
||||||
|
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
|
||||||
|
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
|
||||||
|
** buf - óêàçàòåëü íà ïàìàòü, êóäà ÷èòàòü. **
|
||||||
|
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
|
||||||
|
void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
183
test.c
Normal file
183
test.c
Normal file
@ -0,0 +1,183 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||||
|
|
||||||
|
#include "RS485.h"
|
||||||
|
#include "message.h"
|
||||||
|
#include "filter_bat2.h"
|
||||||
|
#include "measure.h"
|
||||||
|
#include "package.h"
|
||||||
|
#include "test.h"
|
||||||
|
#include "kanal.h"
|
||||||
|
#include "peripher.h"
|
||||||
|
|
||||||
|
WORDE PRES;
|
||||||
|
|
||||||
|
int isMask = 1;
|
||||||
|
int isLamp = 0;
|
||||||
|
int isBrit = 0;
|
||||||
|
int isNumb = 1111;
|
||||||
|
|
||||||
|
long cownt=0;
|
||||||
|
|
||||||
|
unsigned int Light = 0xFFFF;
|
||||||
|
|
||||||
|
int quaLamp = 6;
|
||||||
|
|
||||||
|
void what_is()
|
||||||
|
{
|
||||||
|
static int numb=0;
|
||||||
|
|
||||||
|
if(keyTest)
|
||||||
|
{
|
||||||
|
if(keyNext & !preNext)
|
||||||
|
{
|
||||||
|
if(!isBrit)
|
||||||
|
{
|
||||||
|
isBrit=1;
|
||||||
|
isMask=1;
|
||||||
|
isLamp=0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
isMask<<=1;
|
||||||
|
|
||||||
|
if(++isLamp >= quaLamp)
|
||||||
|
{
|
||||||
|
isMask=1;
|
||||||
|
isLamp=0;
|
||||||
|
} } }
|
||||||
|
|
||||||
|
if(isBrit)
|
||||||
|
{
|
||||||
|
if(keyUp && !preUp)
|
||||||
|
if(Bright[isLamp]<10) Bright[isLamp]++;
|
||||||
|
|
||||||
|
if(keyDown & !preDown)
|
||||||
|
if(Bright[isLamp]>0) Bright[isLamp]--;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(cownt) cownt--;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
cownt = BLN_FREQ/4;
|
||||||
|
|
||||||
|
numb++; if(numb==10) numb=1;
|
||||||
|
isNumb = numb*1111;
|
||||||
|
|
||||||
|
if(!isMask) isMask = 0xFFFF;
|
||||||
|
else isMask = 0;
|
||||||
|
} } }
|
||||||
|
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(isBrit)
|
||||||
|
{
|
||||||
|
isBrit=0;
|
||||||
|
Save_params();
|
||||||
|
} }
|
||||||
|
|
||||||
|
PRES = KEYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
interrupt void cpu_timer1_isr_PULT(void)
|
||||||
|
{
|
||||||
|
static int count_bright=0;
|
||||||
|
unsigned int light=0, i;
|
||||||
|
static LONGE Diod1,Diod2;
|
||||||
|
static unsigned int Cownt,cownt;
|
||||||
|
int dig1,dig2;
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
CpuTimer1.InterruptCount++;
|
||||||
|
IER |= MINT13; // Set "global" priority
|
||||||
|
EINT;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
GpioDataRegs.GPATOGGLE.bit.GPIO0=1; // Ready
|
||||||
|
|
||||||
|
if(count_bright) count_bright --;
|
||||||
|
else count_bright = 9;
|
||||||
|
for(i=0; i<quaLamp; i++)
|
||||||
|
{
|
||||||
|
if(count_bright < Bright[i]) light+=(1<<i);
|
||||||
|
}
|
||||||
|
Light = light;
|
||||||
|
|
||||||
|
Modbus[16].all = Inputs.all | cTestLamp;
|
||||||
|
|
||||||
|
if(Modbus[16].bit.bit4) GpioDataRegs.GPASET.bit.GPIO2=1; //
|
||||||
|
else GpioDataRegs.GPACLEAR.bit.GPIO2=1; //
|
||||||
|
|
||||||
|
Cownt++; cownt = Cownt&3;
|
||||||
|
|
||||||
|
what_is();
|
||||||
|
|
||||||
|
if(isBrit)
|
||||||
|
{
|
||||||
|
if(cownt==0) kanal_Send(adr_digg1,isLamp,0);
|
||||||
|
if(cownt==1) kanal_Send(adr_digg2,Bright[isLamp],0);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(keyTest)
|
||||||
|
{
|
||||||
|
dig1 = isNumb;
|
||||||
|
dig2 = isNumb;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
dig1 = Modbus[0].all;
|
||||||
|
dig2 = Modbus[1].all;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(cownt==0) kanal_Send(adr_digg1,dig1,0);
|
||||||
|
if(cownt==1) kanal_Send(adr_digg2,dig2,0);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(keyTest) kanal_Send(adr_lamps, isMask & Light,0);
|
||||||
|
else kanal_Send(adr_lamps, Modbus[2].all & Light,0);
|
||||||
|
|
||||||
|
if(Mode==adr_PLT1)
|
||||||
|
{
|
||||||
|
if(keyTest)
|
||||||
|
{
|
||||||
|
Diod1.wrd.word_0 = isMask;
|
||||||
|
Diod1.wrd.word_1 = isMask;
|
||||||
|
Diod2.wrd.word_0 = isMask;
|
||||||
|
Diod2.wrd.word_1 = isMask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Diod1.wrd.word_0 = Modbus[3].all;
|
||||||
|
Diod1.wrd.word_1 = Modbus[4].all;
|
||||||
|
Diod2.wrd.word_0 = Modbus[5].all;
|
||||||
|
Diod2.wrd.word_1 = Modbus[6].all;
|
||||||
|
}
|
||||||
|
if(cownt==2) kanal_Send(adr_diod1,Diod1.all,0);
|
||||||
|
if(cownt==3) kanal_Send(adr_diod2,Diod2.all,0);
|
||||||
|
}
|
||||||
|
|
||||||
|
ServiceDog();
|
||||||
|
}
|
||||||
|
|
||||||
|
void timer_Init()
|
||||||
|
{
|
||||||
|
|
||||||
|
#ifdef TUBER
|
||||||
|
if(Mode==adr_PLT2) quaLamp = 4;
|
||||||
|
#endif
|
||||||
|
#ifdef P20183
|
||||||
|
if(Mode==adr_PLT2) quaLamp = 4;
|
||||||
|
if(Mode==adr_PLT3) quaLamp = 4;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
EALLOW; // This is needed to write to EALLOW protected registers
|
||||||
|
PieVectTable.XINT13 = &cpu_timer1_isr_PULT;
|
||||||
|
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||||
|
|
||||||
|
ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/BLN_FREQ);
|
||||||
|
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||||
|
IER |= M_INT13;
|
||||||
|
}
|
||||||
17
test.h
Normal file
17
test.h
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
#define KEYS Modbus[16]
|
||||||
|
#define keyTest KEYS.bit.bit0
|
||||||
|
#define keyUp KEYS.bit.bit1
|
||||||
|
#define keyDown KEYS.bit.bit2
|
||||||
|
#define keyNext KEYS.bit.bit3
|
||||||
|
|
||||||
|
#define preTest PRES.bit.bit0
|
||||||
|
#define preUp PRES.bit.bit1
|
||||||
|
#define preDown PRES.bit.bit2
|
||||||
|
#define preNext PRES.bit.bit3
|
||||||
|
|
||||||
|
#define BLN_FREQ 2000//500 // 2000
|
||||||
|
|
||||||
|
void what_is(void);
|
||||||
|
void timer_Init(void);
|
||||||
|
|
||||||
|
//extern int isMask, isLamp, isBrit;
|
||||||
84
tools.c
Normal file
84
tools.c
Normal file
@ -0,0 +1,84 @@
|
|||||||
|
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||||
|
|
||||||
|
// Configure the timing paramaters for Zone 7.
|
||||||
|
// Notes:
|
||||||
|
// This function should not be executed from XINTF
|
||||||
|
// Adjust the timing based on the data manual and
|
||||||
|
// external device requirements.
|
||||||
|
void init_zone7(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
// Make sure the XINTF clock is enabled
|
||||||
|
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
|
||||||
|
|
||||||
|
// Configure the GPIO for XINTF with a 16-bit data bus
|
||||||
|
// This function is in DSP2833x_Xintf.c
|
||||||
|
InitXintf16Gpio();
|
||||||
|
EALLOW;
|
||||||
|
// All Zones---------------------------------
|
||||||
|
// Timing for all zones based on XTIMCLK = SYSCLKOUT
|
||||||
|
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
|
||||||
|
// Buffer up to 3 writes
|
||||||
|
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
|
||||||
|
// XCLKOUT is enabled
|
||||||
|
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||||
|
// XCLKOUT = XTIMCLK
|
||||||
|
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
|
||||||
|
|
||||||
|
// Zone 7------------------------------------
|
||||||
|
// When using ready, ACTIVE must be 1 or greater
|
||||||
|
// Lead must always be 1 or greater
|
||||||
|
// Zone write timing
|
||||||
|
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
|
||||||
|
XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
|
||||||
|
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
|
||||||
|
// Zone read timing
|
||||||
|
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
|
||||||
|
XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
|
||||||
|
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
|
||||||
|
|
||||||
|
// don't double all Zone read/write lead/active/trail timing
|
||||||
|
XintfRegs.XTIMING7.bit.X2TIMING = 0;
|
||||||
|
|
||||||
|
// Zone will not sample XREADY signal
|
||||||
|
XintfRegs.XTIMING7.bit.USEREADY = 0;
|
||||||
|
XintfRegs.XTIMING7.bit.READYMODE = 0;
|
||||||
|
|
||||||
|
// 1,1 = x16 data bus
|
||||||
|
// 0,1 = x32 data bus
|
||||||
|
// other values are reserved
|
||||||
|
XintfRegs.XTIMING7.bit.XSIZE = 3;
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
//Force a pipeline flush to ensure that the write to
|
||||||
|
//the last register configured occurs before returning.
|
||||||
|
asm(" RPT #7 || NOP");
|
||||||
|
}
|
||||||
|
|
||||||
|
void setup_leds_line()
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0;
|
||||||
|
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0;
|
||||||
|
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1;
|
||||||
|
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void pause_us(unsigned long t)
|
||||||
|
{
|
||||||
|
unsigned long i;
|
||||||
|
|
||||||
|
//unsigned long powse;
|
||||||
|
|
||||||
|
t = t >> 1;
|
||||||
|
|
||||||
|
for (i = 0; i < t; i++)
|
||||||
|
{
|
||||||
|
DSP28x_usDelay(40L);
|
||||||
|
// powse=40L;
|
||||||
|
// for(powse=0; powse<40; powse++);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
26
tools.h
Normal file
26
tools.h
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
#ifndef TOOLS_H
|
||||||
|
#define TOOLS_H
|
||||||
|
|
||||||
|
void init_zone7(void);
|
||||||
|
|
||||||
|
void setup_leds_line(void);
|
||||||
|
|
||||||
|
void pause_us(unsigned long t);
|
||||||
|
|
||||||
|
#ifndef TUBER
|
||||||
|
#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||||
|
#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1
|
||||||
|
#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||||
|
#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1
|
||||||
|
#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||||
|
#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1
|
||||||
|
#else
|
||||||
|
#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||||
|
#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||||
|
#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||||
|
#define led2_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||||
|
#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||||
|
#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //TOOLS_H
|
||||||
176
v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd
Normal file
176
v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd
Normal file
@ -0,0 +1,176 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/9 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:25 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: 28332_RAM_lnk.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For 28332 examples that run out of RAM
|
||||||
|
//
|
||||||
|
// This ONLY includes all SARAM blocks on the 28332 device.
|
||||||
|
// This does not include flash or OTP.
|
||||||
|
//
|
||||||
|
// Keep in mind that L0 and L1 are protected by the code
|
||||||
|
// security module.
|
||||||
|
//
|
||||||
|
// What this means is in most cases you will want to move to
|
||||||
|
// another memory map file which has more memory defined.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28332
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28332 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0 :
|
||||||
|
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||||
|
/* BOOT_RSVD is used by the boot ROM for stack. */
|
||||||
|
/* This section is only reserved to keep the BOOT ROM from */
|
||||||
|
/* corrupting this area during the debug process */
|
||||||
|
|
||||||
|
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
|
||||||
|
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0
|
||||||
|
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000
|
||||||
|
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
|
||||||
|
BOOTROM : origin = 0x3FF27C, length = 0x000D44
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
PAGE 1 :
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Setup for "boot to SARAM" mode:
|
||||||
|
The codestart section (found in DSP28_CodeStartBranch.asm)
|
||||||
|
re-directs execution to the start of user code. */
|
||||||
|
codestart : > BEGIN, PAGE = 0
|
||||||
|
ramfuncs : > RAML0, PAGE = 0
|
||||||
|
.text : > RAML1, PAGE = 0
|
||||||
|
.cinit : > RAML0, PAGE = 0
|
||||||
|
.pinit : > RAML0, PAGE = 0
|
||||||
|
.switch : > RAML0, PAGE = 0
|
||||||
|
|
||||||
|
.stack : > RAMM1, PAGE = 1
|
||||||
|
.ebss : > RAML4, PAGE = 1
|
||||||
|
.econst : > RAML5, PAGE = 1
|
||||||
|
.esysmem : > RAMM1, PAGE = 1
|
||||||
|
|
||||||
|
IQmath : > RAML1, PAGE = 0
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
178
v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd
Normal file
178
v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd
Normal file
@ -0,0 +1,178 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/8 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:30 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: 28334_RAM_lnk.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For 28334 examples that run out of RAM
|
||||||
|
//
|
||||||
|
// This ONLY includes all SARAM blocks on the 28334 device.
|
||||||
|
// This does not include flash or OTP.
|
||||||
|
//
|
||||||
|
// Keep in mind that L0 and L1 are protected by the code
|
||||||
|
// security module.
|
||||||
|
//
|
||||||
|
// What this means is in most cases you will want to move to
|
||||||
|
// another memory map file which has more memory defined.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28334
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28334 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0 :
|
||||||
|
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||||
|
/* BOOT_RSVD is used by the boot ROM for stack. */
|
||||||
|
/* This section is only reserved to keep the BOOT ROM from */
|
||||||
|
/* corrupting this area during the debug process */
|
||||||
|
|
||||||
|
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
|
||||||
|
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0
|
||||||
|
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000
|
||||||
|
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
|
||||||
|
BOOTROM : origin = 0x3FF27C, length = 0x000D44
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
PAGE 1 :
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000
|
||||||
|
RAML6 : origin = 0x00E000, length = 0x001000
|
||||||
|
RAML7 : origin = 0x00F000, length = 0x001000
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Setup for "boot to SARAM" mode:
|
||||||
|
The codestart section (found in DSP28_CodeStartBranch.asm)
|
||||||
|
re-directs execution to the start of user code. */
|
||||||
|
codestart : > BEGIN, PAGE = 0
|
||||||
|
ramfuncs : > RAML0, PAGE = 0
|
||||||
|
.text : > RAML1, PAGE = 0
|
||||||
|
.cinit : > RAML0, PAGE = 0
|
||||||
|
.pinit : > RAML0, PAGE = 0
|
||||||
|
.switch : > RAML0, PAGE = 0
|
||||||
|
|
||||||
|
.stack : > RAMM1, PAGE = 1
|
||||||
|
.ebss : > RAML4, PAGE = 1
|
||||||
|
.econst : > RAML5, PAGE = 1
|
||||||
|
.esysmem : > RAMM1, PAGE = 1
|
||||||
|
|
||||||
|
IQmath : > RAML1, PAGE = 0
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
DMARAML6 : > RAML6, PAGE = 1
|
||||||
|
DMARAML7 : > RAML7, PAGE = 1
|
||||||
|
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
176
v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd
Normal file
176
v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd
Normal file
@ -0,0 +1,176 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/10 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:36 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: 28335_RAM_lnk.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For 28335 examples that run out of RAM
|
||||||
|
//
|
||||||
|
// This ONLY includes all SARAM blocks on the 28335 device.
|
||||||
|
// This does not include flash or OTP.
|
||||||
|
//
|
||||||
|
// Keep in mind that L0 and L1 are protected by the code
|
||||||
|
// security module.
|
||||||
|
//
|
||||||
|
// What this means is in most cases you will want to move to
|
||||||
|
// another memory map file which has more memory defined.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28335
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28335 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0 :
|
||||||
|
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||||
|
/* BOOT_RSVD is used by the boot ROM for stack. */
|
||||||
|
/* This section is only reserved to keep the BOOT ROM from */
|
||||||
|
/* corrupting this area during the debug process */
|
||||||
|
|
||||||
|
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
|
||||||
|
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0
|
||||||
|
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000
|
||||||
|
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
|
||||||
|
BOOTROM : origin = 0x3FF27C, length = 0x000D44
|
||||||
|
|
||||||
|
|
||||||
|
PAGE 1 :
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000
|
||||||
|
RAML6 : origin = 0x00E000, length = 0x001000
|
||||||
|
RAML7 : origin = 0x00F000, length = 0x001000
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Setup for "boot to SARAM" mode:
|
||||||
|
The codestart section (found in DSP28_CodeStartBranch.asm)
|
||||||
|
re-directs execution to the start of user code. */
|
||||||
|
codestart : > BEGIN, PAGE = 0
|
||||||
|
ramfuncs : > RAML0, PAGE = 0
|
||||||
|
.text : > RAML1, PAGE = 0
|
||||||
|
.cinit : > RAML0, PAGE = 0
|
||||||
|
.pinit : > RAML0, PAGE = 0
|
||||||
|
.switch : > RAML0, PAGE = 0
|
||||||
|
|
||||||
|
.stack : > RAMM1, PAGE = 1
|
||||||
|
.ebss : > RAML4, PAGE = 1
|
||||||
|
.econst : > RAML5, PAGE = 1
|
||||||
|
.esysmem : > RAMM1, PAGE = 1
|
||||||
|
|
||||||
|
IQmath : > RAML1, PAGE = 0
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
DMARAML6 : > RAML6, PAGE = 1
|
||||||
|
DMARAML7 : > RAML7, PAGE = 1
|
||||||
|
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
197
v120/DSP2833x_common/cmd/F28332.cmd
Normal file
197
v120/DSP2833x_common/cmd/F28332.cmd
Normal file
@ -0,0 +1,197 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/9 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:41 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: F28332.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For F28332 Device
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28332
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28332 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0: /* Program Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
|
||||||
|
|
||||||
|
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
|
||||||
|
ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */
|
||||||
|
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
|
||||||
|
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
|
||||||
|
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
|
||||||
|
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
|
||||||
|
|
||||||
|
PAGE 1 : /* Data Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
|
||||||
|
/* Registers remain on PAGE1 */
|
||||||
|
|
||||||
|
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */
|
||||||
|
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allocate sections to memory blocks.
|
||||||
|
Note:
|
||||||
|
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
|
||||||
|
execution when booting to flash
|
||||||
|
ramfuncs user defined section to store functions that will be copied from Flash into RAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Allocate program areas: */
|
||||||
|
.cinit : > FLASHA PAGE = 0
|
||||||
|
.pinit : > FLASHA, PAGE = 0
|
||||||
|
.text : > FLASHA PAGE = 0
|
||||||
|
codestart : > BEGIN PAGE = 0
|
||||||
|
ramfuncs : LOAD = FLASHD,
|
||||||
|
RUN = RAML0,
|
||||||
|
LOAD_START(_RamfuncsLoadStart),
|
||||||
|
LOAD_END(_RamfuncsLoadEnd),
|
||||||
|
RUN_START(_RamfuncsRunStart),
|
||||||
|
PAGE = 0
|
||||||
|
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate uninitalized data sections: */
|
||||||
|
.stack : > RAMM1 PAGE = 1
|
||||||
|
.ebss : > RAML4 PAGE = 1
|
||||||
|
.esysmem : > RAMM1 PAGE = 1
|
||||||
|
|
||||||
|
/* Initalized sections go in Flash */
|
||||||
|
/* For SDFlash to program these, they must be allocated to page 0 */
|
||||||
|
.econst : > FLASHA PAGE = 0
|
||||||
|
.switch : > FLASHA PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate IQ math areas: */
|
||||||
|
IQmath : > FLASHC PAGE = 0 /* Math Code */
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Allocate DMA-accessible RAM sections: */
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
|
||||||
|
/* Allocate 0x400 of XINTF Zone 7 to storing data */
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
/* .reset is a standard section used by the compiler. It contains the */
|
||||||
|
/* the address of the start of _c_int00 for C Code. /*
|
||||||
|
/* When using the boot ROM this section and the CPU vector */
|
||||||
|
/* table is not needed. Thus the default type is set here to */
|
||||||
|
/* DSECT */
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT
|
||||||
|
vectors : > VECTORS PAGE = 0, TYPE = DSECT
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
|
|
||||||
203
v120/DSP2833x_common/cmd/F28334.cmd
Normal file
203
v120/DSP2833x_common/cmd/F28334.cmd
Normal file
@ -0,0 +1,203 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/9 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:49 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: F28334.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For F28334 Device
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28334
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28334 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0: /* Program Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
|
||||||
|
|
||||||
|
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
|
||||||
|
ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */
|
||||||
|
ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */
|
||||||
|
FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
|
||||||
|
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
|
||||||
|
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
|
||||||
|
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
|
||||||
|
|
||||||
|
PAGE 1 : /* Data Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
|
||||||
|
/* Registers remain on PAGE1 */
|
||||||
|
|
||||||
|
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allocate sections to memory blocks.
|
||||||
|
Note:
|
||||||
|
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
|
||||||
|
execution when booting to flash
|
||||||
|
ramfuncs user defined section to store functions that will be copied from Flash into RAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Allocate program areas: */
|
||||||
|
.cinit : > FLASHA PAGE = 0
|
||||||
|
.pinit : > FLASHA, PAGE = 0
|
||||||
|
.text : > FLASHA PAGE = 0
|
||||||
|
codestart : > BEGIN PAGE = 0
|
||||||
|
ramfuncs : LOAD = FLASHD,
|
||||||
|
RUN = RAML0,
|
||||||
|
LOAD_START(_RamfuncsLoadStart),
|
||||||
|
LOAD_END(_RamfuncsLoadEnd),
|
||||||
|
RUN_START(_RamfuncsRunStart),
|
||||||
|
PAGE = 0
|
||||||
|
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate uninitalized data sections: */
|
||||||
|
.stack : > RAMM1 PAGE = 1
|
||||||
|
.ebss : > RAML4 PAGE = 1
|
||||||
|
.esysmem : > RAMM1 PAGE = 1
|
||||||
|
|
||||||
|
/* Initalized sections go in Flash */
|
||||||
|
/* For SDFlash to program these, they must be allocated to page 0 */
|
||||||
|
.econst : > FLASHA PAGE = 0
|
||||||
|
.switch : > FLASHA PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate IQ math areas: */
|
||||||
|
IQmath : > FLASHC PAGE = 0 /* Math Code */
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Allocate DMA-accessible RAM sections: */
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
DMARAML6 : > RAML6, PAGE = 1
|
||||||
|
DMARAML7 : > RAML7, PAGE = 1
|
||||||
|
|
||||||
|
/* Allocate 0x400 of XINTF Zone 7 to storing data */
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
/* .reset is a standard section used by the compiler. It contains the */
|
||||||
|
/* the address of the start of _c_int00 for C Code. /*
|
||||||
|
/* When using the boot ROM this section and the CPU vector */
|
||||||
|
/* table is not needed. Thus the default type is set here to */
|
||||||
|
/* DSECT */
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT
|
||||||
|
vectors : > VECTORS PAGE = 0, TYPE = DSECT
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
|
|
||||||
203
v120/DSP2833x_common/cmd/F28335.cmd
Normal file
203
v120/DSP2833x_common/cmd/F28335.cmd
Normal file
@ -0,0 +1,203 @@
|
|||||||
|
/*
|
||||||
|
// TI File $Revision: /main/10 $
|
||||||
|
// Checkin $Date: July 9, 2008 13:43:56 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: F28335.cmd
|
||||||
|
//
|
||||||
|
// TITLE: Linker Command File For F28335 Device
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio V2.2 and later
|
||||||
|
// ---------------------------------------
|
||||||
|
// In addition to this memory linker command file,
|
||||||
|
// add the header linker command file directly to the project.
|
||||||
|
// The header linker command file is required to link the
|
||||||
|
// peripheral structures to the proper locations within
|
||||||
|
// the memory map.
|
||||||
|
//
|
||||||
|
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||||
|
//
|
||||||
|
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||||
|
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||||
|
========================================================= */
|
||||||
|
|
||||||
|
/* ======================================================
|
||||||
|
// For Code Composer Studio prior to V2.2
|
||||||
|
// --------------------------------------
|
||||||
|
// 1) Use one of the following -l statements to include the
|
||||||
|
// header linker command file in the project. The header linker
|
||||||
|
// file is required to link the peripheral structures to the proper
|
||||||
|
// locations within the memory map */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for non-BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||||
|
|
||||||
|
/* Uncomment this line to include file only for BIOS applications */
|
||||||
|
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||||
|
|
||||||
|
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||||
|
library search path under project->build options, linker tab,
|
||||||
|
library search path (-i).
|
||||||
|
/*========================================================= */
|
||||||
|
|
||||||
|
/* Define the memory block start/length for the F28335
|
||||||
|
PAGE 0 will be used to organize program sections
|
||||||
|
PAGE 1 will be used to organize data sections
|
||||||
|
|
||||||
|
Notes:
|
||||||
|
Memory blocks on F28335 are uniform (ie same
|
||||||
|
physical memory) in both PAGE 0 and PAGE 1.
|
||||||
|
That is the same memory region should not be
|
||||||
|
defined for both PAGE 0 and PAGE 1.
|
||||||
|
Doing so will result in corruption of program
|
||||||
|
and/or data.
|
||||||
|
|
||||||
|
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||||
|
they can be accessed in high memory or low memory.
|
||||||
|
For simplicity only one instance is used in this
|
||||||
|
linker file.
|
||||||
|
|
||||||
|
Contiguous SARAM memory blocks can be combined
|
||||||
|
if required to create a larger memory block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
PAGE 0: /* Program Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
|
||||||
|
|
||||||
|
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
|
||||||
|
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
|
||||||
|
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
|
||||||
|
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
|
||||||
|
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
|
||||||
|
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||||
|
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
|
||||||
|
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||||
|
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
|
||||||
|
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||||
|
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
|
||||||
|
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
|
||||||
|
|
||||||
|
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
|
||||||
|
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
|
||||||
|
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
|
||||||
|
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
|
||||||
|
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
|
||||||
|
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
|
||||||
|
|
||||||
|
PAGE 1 : /* Data Memory */
|
||||||
|
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
|
||||||
|
/* Registers remain on PAGE1 */
|
||||||
|
|
||||||
|
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
|
||||||
|
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
|
||||||
|
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||||
|
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
|
||||||
|
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||||
|
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allocate sections to memory blocks.
|
||||||
|
Note:
|
||||||
|
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
|
||||||
|
execution when booting to flash
|
||||||
|
ramfuncs user defined section to store functions that will be copied from Flash into RAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Allocate program areas: */
|
||||||
|
.cinit : > FLASHA PAGE = 0
|
||||||
|
.pinit : > FLASHA, PAGE = 0
|
||||||
|
.text : > FLASHA PAGE = 0
|
||||||
|
codestart : > BEGIN PAGE = 0
|
||||||
|
ramfuncs : LOAD = FLASHD,
|
||||||
|
RUN = RAML0,
|
||||||
|
LOAD_START(_RamfuncsLoadStart),
|
||||||
|
LOAD_END(_RamfuncsLoadEnd),
|
||||||
|
RUN_START(_RamfuncsRunStart),
|
||||||
|
PAGE = 0
|
||||||
|
|
||||||
|
csmpasswds : > CSM_PWL PAGE = 0
|
||||||
|
csm_rsvd : > CSM_RSVD PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate uninitalized data sections: */
|
||||||
|
.stack : > RAMM1 PAGE = 1
|
||||||
|
.ebss : > RAML4 PAGE = 1
|
||||||
|
.esysmem : > RAMM1 PAGE = 1
|
||||||
|
|
||||||
|
/* Initalized sections go in Flash */
|
||||||
|
/* For SDFlash to program these, they must be allocated to page 0 */
|
||||||
|
.econst : > FLASHA PAGE = 0
|
||||||
|
.switch : > FLASHA PAGE = 0
|
||||||
|
|
||||||
|
/* Allocate IQ math areas: */
|
||||||
|
IQmath : > FLASHC PAGE = 0 /* Math Code */
|
||||||
|
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||||
|
functions from the IQMath.lib library in order to utilize the
|
||||||
|
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||||
|
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||||
|
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||||
|
up space, but 0 wait-state is possible.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||||
|
{
|
||||||
|
|
||||||
|
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||||
|
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
/* Allocate DMA-accessible RAM sections: */
|
||||||
|
DMARAML4 : > RAML4, PAGE = 1
|
||||||
|
DMARAML5 : > RAML5, PAGE = 1
|
||||||
|
DMARAML6 : > RAML6, PAGE = 1
|
||||||
|
DMARAML7 : > RAML7, PAGE = 1
|
||||||
|
|
||||||
|
/* Allocate 0x400 of XINTF Zone 7 to storing data */
|
||||||
|
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||||
|
|
||||||
|
/* .reset is a standard section used by the compiler. It contains the */
|
||||||
|
/* the address of the start of _c_int00 for C Code. /*
|
||||||
|
/* When using the boot ROM this section and the CPU vector */
|
||||||
|
/* table is not needed. Thus the default type is set here to */
|
||||||
|
/* DSECT */
|
||||||
|
.reset : > RESET, PAGE = 0, TYPE = DSECT
|
||||||
|
vectors : > VECTORS PAGE = 0, TYPE = DSECT
|
||||||
|
|
||||||
|
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||||
|
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
|
*/
|
||||||
|
|
||||||
2822
v120/DSP2833x_common/gel/f28232.gel
Normal file
2822
v120/DSP2833x_common/gel/f28232.gel
Normal file
File diff suppressed because it is too large
Load Diff
2930
v120/DSP2833x_common/gel/f28234.gel
Normal file
2930
v120/DSP2833x_common/gel/f28234.gel
Normal file
File diff suppressed because it is too large
Load Diff
2939
v120/DSP2833x_common/gel/f28235.gel
Normal file
2939
v120/DSP2833x_common/gel/f28235.gel
Normal file
File diff suppressed because it is too large
Load Diff
2845
v120/DSP2833x_common/gel/f28332.gel
Normal file
2845
v120/DSP2833x_common/gel/f28332.gel
Normal file
File diff suppressed because it is too large
Load Diff
2951
v120/DSP2833x_common/gel/f28334.gel
Normal file
2951
v120/DSP2833x_common/gel/f28334.gel
Normal file
File diff suppressed because it is too large
Load Diff
2960
v120/DSP2833x_common/gel/f28335.gel
Normal file
2960
v120/DSP2833x_common/gel/f28335.gel
Normal file
File diff suppressed because it is too large
Load Diff
147
v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h
Normal file
147
v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h
Normal file
@ -0,0 +1,147 @@
|
|||||||
|
// TI File $Revision: /main/1 $
|
||||||
|
// Checkin $Date: August 18, 2006 13:45:37 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_DefaultIsr.h
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_DEFAULT_ISR_H
|
||||||
|
#define DSP2833x_DEFAULT_ISR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Default Interrupt Service Routine Declarations:
|
||||||
|
//
|
||||||
|
// The following function prototypes are for the
|
||||||
|
// default ISR routines used with the default PIE vector table.
|
||||||
|
// This default vector table is found in the DSP2833x_PieVect.h
|
||||||
|
// file.
|
||||||
|
//
|
||||||
|
|
||||||
|
// Non-Peripheral Interrupts:
|
||||||
|
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
|
||||||
|
interrupt void INT14_ISR(void); // CPU-Timer2
|
||||||
|
interrupt void DATALOG_ISR(void); // Datalogging interrupt
|
||||||
|
interrupt void RTOSINT_ISR(void); // RTOS interrupt
|
||||||
|
interrupt void EMUINT_ISR(void); // Emulation interrupt
|
||||||
|
interrupt void NMI_ISR(void); // Non-maskable interrupt
|
||||||
|
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
|
||||||
|
interrupt void USER1_ISR(void); // User Defined trap 1
|
||||||
|
interrupt void USER2_ISR(void); // User Defined trap 2
|
||||||
|
interrupt void USER3_ISR(void); // User Defined trap 3
|
||||||
|
interrupt void USER4_ISR(void); // User Defined trap 4
|
||||||
|
interrupt void USER5_ISR(void); // User Defined trap 5
|
||||||
|
interrupt void USER6_ISR(void); // User Defined trap 6
|
||||||
|
interrupt void USER7_ISR(void); // User Defined trap 7
|
||||||
|
interrupt void USER8_ISR(void); // User Defined trap 8
|
||||||
|
interrupt void USER9_ISR(void); // User Defined trap 9
|
||||||
|
interrupt void USER10_ISR(void); // User Defined trap 10
|
||||||
|
interrupt void USER11_ISR(void); // User Defined trap 11
|
||||||
|
interrupt void USER12_ISR(void); // User Defined trap 12
|
||||||
|
|
||||||
|
// Group 1 PIE Interrupt Service Routines:
|
||||||
|
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
|
||||||
|
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
|
||||||
|
interrupt void XINT1_ISR(void); // External interrupt 1
|
||||||
|
interrupt void XINT2_ISR(void); // External interrupt 2
|
||||||
|
interrupt void ADCINT_ISR(void); // ADC
|
||||||
|
interrupt void TINT0_ISR(void); // Timer 0
|
||||||
|
interrupt void WAKEINT_ISR(void); // WD
|
||||||
|
|
||||||
|
// Group 2 PIE Interrupt Service Routines:
|
||||||
|
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
|
||||||
|
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
|
||||||
|
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
|
||||||
|
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
|
||||||
|
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
|
||||||
|
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
|
||||||
|
|
||||||
|
// Group 3 PIE Interrupt Service Routines:
|
||||||
|
interrupt void EPWM1_INT_ISR(void); // EPWM-1
|
||||||
|
interrupt void EPWM2_INT_ISR(void); // EPWM-2
|
||||||
|
interrupt void EPWM3_INT_ISR(void); // EPWM-3
|
||||||
|
interrupt void EPWM4_INT_ISR(void); // EPWM-4
|
||||||
|
interrupt void EPWM5_INT_ISR(void); // EPWM-5
|
||||||
|
interrupt void EPWM6_INT_ISR(void); // EPWM-6
|
||||||
|
|
||||||
|
// Group 4 PIE Interrupt Service Routines:
|
||||||
|
interrupt void ECAP1_INT_ISR(void); // ECAP-1
|
||||||
|
interrupt void ECAP2_INT_ISR(void); // ECAP-2
|
||||||
|
interrupt void ECAP3_INT_ISR(void); // ECAP-3
|
||||||
|
interrupt void ECAP4_INT_ISR(void); // ECAP-4
|
||||||
|
interrupt void ECAP5_INT_ISR(void); // ECAP-5
|
||||||
|
interrupt void ECAP6_INT_ISR(void); // ECAP-6
|
||||||
|
|
||||||
|
// Group 5 PIE Interrupt Service Routines:
|
||||||
|
interrupt void EQEP1_INT_ISR(void); // EQEP-1
|
||||||
|
interrupt void EQEP2_INT_ISR(void); // EQEP-2
|
||||||
|
|
||||||
|
// Group 6 PIE Interrupt Service Routines:
|
||||||
|
interrupt void SPIRXINTA_ISR(void); // SPI-A
|
||||||
|
interrupt void SPITXINTA_ISR(void); // SPI-A
|
||||||
|
interrupt void MRINTA_ISR(void); // McBSP-A
|
||||||
|
interrupt void MXINTA_ISR(void); // McBSP-A
|
||||||
|
interrupt void MRINTB_ISR(void); // McBSP-B
|
||||||
|
interrupt void MXINTB_ISR(void); // McBSP-B
|
||||||
|
|
||||||
|
// Group 7 PIE Interrupt Service Routines:
|
||||||
|
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
|
||||||
|
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
|
||||||
|
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
|
||||||
|
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
|
||||||
|
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
|
||||||
|
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
|
||||||
|
|
||||||
|
// Group 8 PIE Interrupt Service Routines:
|
||||||
|
interrupt void I2CINT1A_ISR(void); // I2C-A
|
||||||
|
interrupt void I2CINT2A_ISR(void); // I2C-A
|
||||||
|
interrupt void SCIRXINTC_ISR(void); // SCI-C
|
||||||
|
interrupt void SCITXINTC_ISR(void); // SCI-C
|
||||||
|
|
||||||
|
// Group 9 PIE Interrupt Service Routines:
|
||||||
|
interrupt void SCIRXINTA_ISR(void); // SCI-A
|
||||||
|
interrupt void SCITXINTA_ISR(void); // SCI-A
|
||||||
|
interrupt void SCIRXINTB_ISR(void); // SCI-B
|
||||||
|
interrupt void SCITXINTB_ISR(void); // SCI-B
|
||||||
|
interrupt void ECAN0INTA_ISR(void); // eCAN-A
|
||||||
|
interrupt void ECAN1INTA_ISR(void); // eCAN-A
|
||||||
|
interrupt void ECAN0INTB_ISR(void); // eCAN-B
|
||||||
|
interrupt void ECAN1INTB_ISR(void); // eCAN-B
|
||||||
|
|
||||||
|
// Group 10 PIE Interrupt Service Routines:
|
||||||
|
|
||||||
|
// Group 11 PIE Interrupt Service Routines:
|
||||||
|
|
||||||
|
// Group 12 PIE Interrupt Service Routines:
|
||||||
|
interrupt void XINT3_ISR(void); // External interrupt 3
|
||||||
|
interrupt void XINT4_ISR(void); // External interrupt 4
|
||||||
|
interrupt void XINT5_ISR(void); // External interrupt 5
|
||||||
|
interrupt void XINT6_ISR(void); // External interrupt 6
|
||||||
|
interrupt void XINT7_ISR(void); // External interrupt 7
|
||||||
|
interrupt void LVF_ISR(void); // Latched overflow flag
|
||||||
|
interrupt void LUF_ISR(void); // Latched underflow flag
|
||||||
|
|
||||||
|
// Catch-all for Reserved Locations For testing purposes:
|
||||||
|
interrupt void PIE_RESERVED(void); // Reserved for test
|
||||||
|
interrupt void rsvd_ISR(void); // for test
|
||||||
|
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
|
|
||||||
|
#endif // end of DSP2833x_DEFAULT_ISR_H definition
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
81
v120/DSP2833x_common/include/DSP2833x_Dma_defines.h
Normal file
81
v120/DSP2833x_common/include/DSP2833x_Dma_defines.h
Normal file
@ -0,0 +1,81 @@
|
|||||||
|
// TI File $Revision: /main/2 $
|
||||||
|
// Checkin $Date: August 14, 2007 16:32:29 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_Dma_defines.h
|
||||||
|
//
|
||||||
|
// TITLE: #defines used in DMA examples
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_DMA_DEFINES_H
|
||||||
|
#define DSP2833x_DMA_DEFINES_H
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// MODE
|
||||||
|
//==========================
|
||||||
|
// PERINTSEL bits
|
||||||
|
#define DMA_SEQ1INT 1
|
||||||
|
#define DMA_SEQ2INT 2
|
||||||
|
#define DMA_XINT1 3
|
||||||
|
#define DMA_XINT2 4
|
||||||
|
#define DMA_XINT3 5
|
||||||
|
#define DMA_XINT4 6
|
||||||
|
#define DMA_XINT5 7
|
||||||
|
#define DMA_XINT6 8
|
||||||
|
#define DMA_XINT7 9
|
||||||
|
#define DMA_XINT13 10
|
||||||
|
#define DMA_TINT0 11
|
||||||
|
#define DMA_TINT1 12
|
||||||
|
#define DMA_TINT2 13
|
||||||
|
#define DMA_MXEVTA 14
|
||||||
|
#define DMA_MREVTA 15
|
||||||
|
#define DMA_MXREVTB 16
|
||||||
|
#define DMA_MREVTB 17
|
||||||
|
// OVERINTE bit
|
||||||
|
#define OVRFLOW_DISABLE 0x0
|
||||||
|
#define OVEFLOW_ENABLE 0x1
|
||||||
|
// PERINTE bit
|
||||||
|
#define PERINT_DISABLE 0x0
|
||||||
|
#define PERINT_ENABLE 0x1
|
||||||
|
// CHINTMODE bits
|
||||||
|
#define CHINT_BEGIN 0x0
|
||||||
|
#define CHINT_END 0x1
|
||||||
|
// ONESHOT bits
|
||||||
|
#define ONESHOT_DISABLE 0x0
|
||||||
|
#define ONESHOT_ENABLE 0x1
|
||||||
|
// CONTINOUS bit
|
||||||
|
#define CONT_DISABLE 0x0
|
||||||
|
#define CONT_ENABLE 0x1
|
||||||
|
// SYNCE bit
|
||||||
|
#define SYNC_DISABLE 0x0
|
||||||
|
#define SYNC_ENABLE 0x1
|
||||||
|
// SYNCSEL bit
|
||||||
|
#define SYNC_SRC 0x0
|
||||||
|
#define SYNC_DST 0x1
|
||||||
|
// DATASIZE bit
|
||||||
|
#define SIXTEEN_BIT 0x0
|
||||||
|
#define THIRTYTWO_BIT 0x1
|
||||||
|
// CHINTE bit
|
||||||
|
#define CHINT_DISABLE 0x0
|
||||||
|
#define CHINT_ENABLE 0x1
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
|
|
||||||
|
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
Normal file
164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
Normal file
@ -0,0 +1,164 @@
|
|||||||
|
// TI File $Revision: /main/1 $
|
||||||
|
// Checkin $Date: August 18, 2006 13:45:39 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_EPwm_defines.h
|
||||||
|
//
|
||||||
|
// TITLE: #defines used in ePWM examples examples
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_EPWM_DEFINES_H
|
||||||
|
#define DSP2833x_EPWM_DEFINES_H
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// TBCTL (Time-Base Control)
|
||||||
|
//==========================
|
||||||
|
// CTRMODE bits
|
||||||
|
#define TB_COUNT_UP 0x0
|
||||||
|
#define TB_COUNT_DOWN 0x1
|
||||||
|
#define TB_COUNT_UPDOWN 0x2
|
||||||
|
#define TB_FREEZE 0x3
|
||||||
|
// PHSEN bit
|
||||||
|
#define TB_DISABLE 0x0
|
||||||
|
#define TB_ENABLE 0x1
|
||||||
|
// PRDLD bit
|
||||||
|
#define TB_SHADOW 0x0
|
||||||
|
#define TB_IMMEDIATE 0x1
|
||||||
|
// SYNCOSEL bits
|
||||||
|
#define TB_SYNC_IN 0x0
|
||||||
|
#define TB_CTR_ZERO 0x1
|
||||||
|
#define TB_CTR_CMPB 0x2
|
||||||
|
#define TB_SYNC_DISABLE 0x3
|
||||||
|
// HSPCLKDIV and CLKDIV bits
|
||||||
|
#define TB_DIV1 0x0
|
||||||
|
#define TB_DIV2 0x1
|
||||||
|
#define TB_DIV4 0x2
|
||||||
|
// PHSDIR bit
|
||||||
|
#define TB_DOWN 0x0
|
||||||
|
#define TB_UP 0x1
|
||||||
|
|
||||||
|
// CMPCTL (Compare Control)
|
||||||
|
//==========================
|
||||||
|
// LOADAMODE and LOADBMODE bits
|
||||||
|
#define CC_CTR_ZERO 0x0
|
||||||
|
#define CC_CTR_PRD 0x1
|
||||||
|
#define CC_CTR_ZERO_PRD 0x2
|
||||||
|
#define CC_LD_DISABLE 0x3
|
||||||
|
// SHDWAMODE and SHDWBMODE bits
|
||||||
|
#define CC_SHADOW 0x0
|
||||||
|
#define CC_IMMEDIATE 0x1
|
||||||
|
|
||||||
|
// AQCTLA and AQCTLB (Action Qualifier Control)
|
||||||
|
//=============================================
|
||||||
|
// ZRO, PRD, CAU, CAD, CBU, CBD bits
|
||||||
|
#define AQ_NO_ACTION 0x0
|
||||||
|
#define AQ_CLEAR 0x1
|
||||||
|
#define AQ_SET 0x2
|
||||||
|
#define AQ_TOGGLE 0x3
|
||||||
|
|
||||||
|
// DBCTL (Dead-Band Control)
|
||||||
|
//==========================
|
||||||
|
// OUT MODE bits
|
||||||
|
#define DB_DISABLE 0x0
|
||||||
|
#define DBA_ENABLE 0x1
|
||||||
|
#define DBB_ENABLE 0x2
|
||||||
|
#define DB_FULL_ENABLE 0x3
|
||||||
|
// POLSEL bits
|
||||||
|
#define DB_ACTV_HI 0x0
|
||||||
|
#define DB_ACTV_LOC 0x1
|
||||||
|
#define DB_ACTV_HIC 0x2
|
||||||
|
#define DB_ACTV_LO 0x3
|
||||||
|
// IN MODE
|
||||||
|
#define DBA_ALL 0x0
|
||||||
|
#define DBB_RED_DBA_FED 0x1
|
||||||
|
#define DBA_RED_DBB_FED 0x2
|
||||||
|
#define DBB_ALL 0x3
|
||||||
|
|
||||||
|
// CHPCTL (chopper control)
|
||||||
|
//==========================
|
||||||
|
// CHPEN bit
|
||||||
|
#define CHP_DISABLE 0x0
|
||||||
|
#define CHP_ENABLE 0x1
|
||||||
|
// CHPFREQ bits
|
||||||
|
#define CHP_DIV1 0x0
|
||||||
|
#define CHP_DIV2 0x1
|
||||||
|
#define CHP_DIV3 0x2
|
||||||
|
#define CHP_DIV4 0x3
|
||||||
|
#define CHP_DIV5 0x4
|
||||||
|
#define CHP_DIV6 0x5
|
||||||
|
#define CHP_DIV7 0x6
|
||||||
|
#define CHP_DIV8 0x7
|
||||||
|
// CHPDUTY bits
|
||||||
|
#define CHP1_8TH 0x0
|
||||||
|
#define CHP2_8TH 0x1
|
||||||
|
#define CHP3_8TH 0x2
|
||||||
|
#define CHP4_8TH 0x3
|
||||||
|
#define CHP5_8TH 0x4
|
||||||
|
#define CHP6_8TH 0x5
|
||||||
|
#define CHP7_8TH 0x6
|
||||||
|
|
||||||
|
// TZSEL (Trip Zone Select)
|
||||||
|
//==========================
|
||||||
|
// CBCn and OSHTn bits
|
||||||
|
#define TZ_DISABLE 0x0
|
||||||
|
#define TZ_ENABLE 0x1
|
||||||
|
|
||||||
|
// TZCTL (Trip Zone Control)
|
||||||
|
//==========================
|
||||||
|
// TZA and TZB bits
|
||||||
|
#define TZ_HIZ 0x0
|
||||||
|
#define TZ_FORCE_HI 0x1
|
||||||
|
#define TZ_FORCE_LO 0x2
|
||||||
|
#define TZ_NO_CHANGE 0x3
|
||||||
|
|
||||||
|
// ETSEL (Event Trigger Select)
|
||||||
|
//=============================
|
||||||
|
#define ET_CTR_ZERO 0x1
|
||||||
|
#define ET_CTR_PRD 0x2
|
||||||
|
#define ET_CTRU_CMPA 0x4
|
||||||
|
#define ET_CTRD_CMPA 0x5
|
||||||
|
#define ET_CTRU_CMPB 0x6
|
||||||
|
#define ET_CTRD_CMPB 0x7
|
||||||
|
|
||||||
|
// ETPS (Event Trigger Pre-scale)
|
||||||
|
//===============================
|
||||||
|
// INTPRD, SOCAPRD, SOCBPRD bits
|
||||||
|
#define ET_DISABLE 0x0
|
||||||
|
#define ET_1ST 0x1
|
||||||
|
#define ET_2ND 0x2
|
||||||
|
#define ET_3RD 0x3
|
||||||
|
|
||||||
|
|
||||||
|
//--------------------------------
|
||||||
|
// HRPWM (High Resolution PWM)
|
||||||
|
//================================
|
||||||
|
// HRCNFG
|
||||||
|
#define HR_Disable 0x0
|
||||||
|
#define HR_REP 0x1
|
||||||
|
#define HR_FEP 0x2
|
||||||
|
#define HR_BEP 0x3
|
||||||
|
|
||||||
|
#define HR_CMP 0x0
|
||||||
|
#define HR_PHS 0x1
|
||||||
|
|
||||||
|
#define HR_CTR_ZERO 0x0
|
||||||
|
#define HR_CTR_PRD 0x1
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
|
|
||||||
|
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
141
v120/DSP2833x_common/include/DSP2833x_Examples.h
Normal file
141
v120/DSP2833x_common/include/DSP2833x_Examples.h
Normal file
@ -0,0 +1,141 @@
|
|||||||
|
// TI File $Revision: /main/9 $
|
||||||
|
// Checkin $Date: July 2, 2008 14:31:12 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_Examples.h
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x Device Definitions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_EXAMPLES_H
|
||||||
|
#define DSP2833x_EXAMPLES_H
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
|
||||||
|
-----------------------------------------------------------------------------*/
|
||||||
|
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
|
||||||
|
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
|
||||||
|
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
|
||||||
|
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
|
||||||
|
|
||||||
|
#define DSP28_PLLCR 10
|
||||||
|
//#define DSP28_PLLCR 9
|
||||||
|
//#define DSP28_PLLCR 8
|
||||||
|
//#define DSP28_PLLCR 7
|
||||||
|
//#define DSP28_PLLCR 6
|
||||||
|
//#define DSP28_PLLCR 5
|
||||||
|
//#define DSP28_PLLCR 4
|
||||||
|
//#define DSP28_PLLCR 3
|
||||||
|
//#define DSP28_PLLCR 2
|
||||||
|
//#define DSP28_PLLCR 1
|
||||||
|
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
|
||||||
|
|
||||||
|
Take into account the input clock frequency and the PLL multiplier
|
||||||
|
selected in step 1.
|
||||||
|
|
||||||
|
Use one of the values provided, or define your own.
|
||||||
|
The trailing L is required tells the compiler to treat
|
||||||
|
the number as a 64-bit value.
|
||||||
|
|
||||||
|
Only one statement should be uncommented.
|
||||||
|
|
||||||
|
Example 1:150 MHz devices:
|
||||||
|
CLKIN is a 30MHz crystal.
|
||||||
|
|
||||||
|
In step 1 the user specified PLLCR = 0xA for a
|
||||||
|
150Mhz CPU clock (SYSCLKOUT = 150MHz).
|
||||||
|
|
||||||
|
In this case, the CPU_RATE will be 6.667L
|
||||||
|
Uncomment the line: #define CPU_RATE 6.667L
|
||||||
|
|
||||||
|
Example 2: 100 MHz devices:
|
||||||
|
CLKIN is a 20MHz crystal.
|
||||||
|
|
||||||
|
In step 1 the user specified PLLCR = 0xA for a
|
||||||
|
100Mhz CPU clock (SYSCLKOUT = 100MHz).
|
||||||
|
|
||||||
|
In this case, the CPU_RATE will be 10.000L
|
||||||
|
Uncomment the line: #define CPU_RATE 10.000L
|
||||||
|
-----------------------------------------------------------------------------*/
|
||||||
|
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
|
||||||
|
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
Target device (in DSP2833x_Device.h) determines CPU frequency
|
||||||
|
(for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
|
||||||
|
(for 28332). User does not have to change anything here.
|
||||||
|
-----------------------------------------------------------------------------*/
|
||||||
|
#if DSP28_28332 // DSP28_28332 device only
|
||||||
|
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
|
||||||
|
#define CPU_FRQ_150MHZ 0
|
||||||
|
#else
|
||||||
|
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
|
||||||
|
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Include Example Header Files:
|
||||||
|
//
|
||||||
|
|
||||||
|
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
|
||||||
|
// .c files.
|
||||||
|
|
||||||
|
#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
|
||||||
|
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
|
||||||
|
#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
|
||||||
|
|
||||||
|
#define PARTNO_28335 0xEF
|
||||||
|
#define PARTNO_28334 0xEE
|
||||||
|
#define PARTNO_28332 0xED
|
||||||
|
#define PARTNO_28235 0xE8
|
||||||
|
#define PARTNO_28234 0xE7
|
||||||
|
#define PARTNO_28232 0xE6
|
||||||
|
|
||||||
|
|
||||||
|
// Include files not used with DSP/BIOS
|
||||||
|
#ifndef DSP28_BIOS
|
||||||
|
#include "DSP2833x_DefaultISR.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
// DO NOT MODIFY THIS LINE.
|
||||||
|
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
|
|
||||||
|
#endif // end of DSP2833x_EXAMPLES_H definition
|
||||||
|
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
207
v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
Normal file
207
v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
Normal file
@ -0,0 +1,207 @@
|
|||||||
|
// TI File $Revision: /main/11 $
|
||||||
|
// Checkin $Date: May 12, 2008 14:30:08 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_GlobalPrototypes.h
|
||||||
|
//
|
||||||
|
// TITLE: Global prototypes for DSP2833x Examples
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_GLOBALPROTOTYPES_H
|
||||||
|
#define DSP2833x_GLOBALPROTOTYPES_H
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*---- shared global function prototypes -----------------------------------*/
|
||||||
|
extern void InitAdc(void);
|
||||||
|
|
||||||
|
extern void DMAInitialize(void);
|
||||||
|
// DMA Channel 1
|
||||||
|
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH1(void);
|
||||||
|
// DMA Channel 2
|
||||||
|
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH2(void);
|
||||||
|
// DMA Channel 3
|
||||||
|
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH3(void);
|
||||||
|
// DMA Channel 4
|
||||||
|
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH4(void);
|
||||||
|
// DMA Channel 5
|
||||||
|
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH5(void);
|
||||||
|
// DMA Channel 6
|
||||||
|
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||||
|
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
|
||||||
|
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||||
|
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||||
|
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||||
|
extern void StartDMACH6(void);
|
||||||
|
|
||||||
|
extern void InitPeripherals(void);
|
||||||
|
#if DSP28_ECANA
|
||||||
|
extern void InitECan(void);
|
||||||
|
extern void InitECana(void);
|
||||||
|
extern void InitECanGpio(void);
|
||||||
|
extern void InitECanaGpio(void);
|
||||||
|
#endif // endif DSP28_ECANA
|
||||||
|
#if DSP28_ECANB
|
||||||
|
extern void InitECanb(void);
|
||||||
|
extern void InitECanbGpio(void);
|
||||||
|
#endif // endif DSP28_ECANB
|
||||||
|
extern void InitECap(void);
|
||||||
|
extern void InitECapGpio(void);
|
||||||
|
extern void InitECap1Gpio(void);
|
||||||
|
extern void InitECap2Gpio(void);
|
||||||
|
#if DSP28_ECAP3
|
||||||
|
extern void InitECap3Gpio(void);
|
||||||
|
#endif // endif DSP28_ECAP3
|
||||||
|
#if DSP28_ECAP4
|
||||||
|
extern void InitECap4Gpio(void);
|
||||||
|
#endif // endif DSP28_ECAP4
|
||||||
|
#if DSP28_ECAP5
|
||||||
|
extern void InitECap5Gpio(void);
|
||||||
|
#endif // endif DSP28_ECAP5
|
||||||
|
#if DSP28_ECAP6
|
||||||
|
extern void InitECap6Gpio(void);
|
||||||
|
#endif // endif DSP28_ECAP6
|
||||||
|
extern void InitEPwm(void);
|
||||||
|
extern void InitEPwmGpio(void);
|
||||||
|
extern void InitEPwm1Gpio(void);
|
||||||
|
extern void InitEPwm2Gpio(void);
|
||||||
|
extern void InitEPwm3Gpio(void);
|
||||||
|
#if DSP28_EPWM4
|
||||||
|
extern void InitEPwm4Gpio(void);
|
||||||
|
#endif // endif DSP28_EPWM4
|
||||||
|
#if DSP28_EPWM5
|
||||||
|
extern void InitEPwm5Gpio(void);
|
||||||
|
#endif // endif DSP28_EPWM5
|
||||||
|
#if DSP28_EPWM6
|
||||||
|
extern void InitEPwm6Gpio(void);
|
||||||
|
#endif // endif DSP28_EPWM6
|
||||||
|
#if DSP28_EQEP1
|
||||||
|
extern void InitEQep(void);
|
||||||
|
extern void InitEQepGpio(void);
|
||||||
|
extern void InitEQep1Gpio(void);
|
||||||
|
#endif // if DSP28_EQEP1
|
||||||
|
#if DSP28_EQEP2
|
||||||
|
extern void InitEQep2Gpio(void);
|
||||||
|
#endif // endif DSP28_EQEP2
|
||||||
|
extern void InitGpio(void);
|
||||||
|
extern void InitI2CGpio(void);
|
||||||
|
|
||||||
|
extern void InitMcbsp(void);
|
||||||
|
extern void InitMcbspa(void);
|
||||||
|
extern void delay_loop(void);
|
||||||
|
extern void InitMcbspaGpio(void);
|
||||||
|
extern void InitMcbspa8bit(void);
|
||||||
|
extern void InitMcbspa12bit(void);
|
||||||
|
extern void InitMcbspa16bit(void);
|
||||||
|
extern void InitMcbspa20bit(void);
|
||||||
|
extern void InitMcbspa24bit(void);
|
||||||
|
extern void InitMcbspa32bit(void);
|
||||||
|
#if DSP28_MCBSPB
|
||||||
|
extern void InitMcbspb(void);
|
||||||
|
extern void InitMcbspbGpio(void);
|
||||||
|
extern void InitMcbspb8bit(void);
|
||||||
|
extern void InitMcbspb12bit(void);
|
||||||
|
extern void InitMcbspb16bit(void);
|
||||||
|
extern void InitMcbspb20bit(void);
|
||||||
|
extern void InitMcbspb24bit(void);
|
||||||
|
extern void InitMcbspb32bit(void);
|
||||||
|
#endif // endif DSP28_MCBSPB
|
||||||
|
|
||||||
|
extern void InitPieCtrl(void);
|
||||||
|
extern void InitPieVectTable(void);
|
||||||
|
|
||||||
|
extern void InitSci(void);
|
||||||
|
extern void InitSciGpio(void);
|
||||||
|
extern void InitSciaGpio(void);
|
||||||
|
#if DSP28_SCIB
|
||||||
|
extern void InitScibGpio(void);
|
||||||
|
#endif // endif DSP28_SCIB
|
||||||
|
#if DSP28_SCIC
|
||||||
|
extern void InitScicGpio(void);
|
||||||
|
#endif
|
||||||
|
extern void InitSpi(void);
|
||||||
|
extern void InitSpiGpio(void);
|
||||||
|
extern void InitSpiaGpio(void);
|
||||||
|
extern void InitSysCtrl(void);
|
||||||
|
extern void InitTzGpio(void);
|
||||||
|
extern void InitXIntrupt(void);
|
||||||
|
extern void XintfInit(void);
|
||||||
|
extern void InitXintf16Gpio();
|
||||||
|
extern void InitXintf32Gpio();
|
||||||
|
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
|
||||||
|
extern void InitPeripheralClocks(void);
|
||||||
|
extern void EnableInterrupts(void);
|
||||||
|
extern void DSP28x_usDelay(Uint32 Count);
|
||||||
|
extern void ADC_cal (void);
|
||||||
|
#define KickDog ServiceDog // For compatiblity with previous versions
|
||||||
|
extern void ServiceDog(void);
|
||||||
|
extern void DisableDog(void);
|
||||||
|
extern Uint16 CsmUnlock(void);
|
||||||
|
|
||||||
|
// DSP28_DBGIER.asm
|
||||||
|
extern void SetDBGIER(Uint16 dbgier);
|
||||||
|
|
||||||
|
// CAUTION
|
||||||
|
// This function MUST be executed out of RAM. Executing it
|
||||||
|
// out of OTP/Flash will yield unpredictable results
|
||||||
|
extern void InitFlash(void);
|
||||||
|
|
||||||
|
|
||||||
|
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// External symbols created by the linker cmd file
|
||||||
|
// DSP28 examples will use these to relocate code from one LOAD location
|
||||||
|
// in either Flash or XINTF to a different RUN location in internal
|
||||||
|
// RAM
|
||||||
|
extern Uint16 RamfuncsLoadStart;
|
||||||
|
extern Uint16 RamfuncsLoadEnd;
|
||||||
|
extern Uint16 RamfuncsRunStart;
|
||||||
|
|
||||||
|
extern Uint16 XintffuncsLoadStart;
|
||||||
|
extern Uint16 XintffuncsLoadEnd;
|
||||||
|
extern Uint16 XintffuncsRunStart;
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
|
|
||||||
|
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
117
v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
Normal file
117
v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
Normal file
@ -0,0 +1,117 @@
|
|||||||
|
// TI File $Revision: /main/2 $
|
||||||
|
// Checkin $Date: April 16, 2008 17:16:47 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_I2cExample.h
|
||||||
|
//
|
||||||
|
// TITLE: 2833x I2C Example Code Definitions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP2833x_I2C_DEFINES_H
|
||||||
|
#define DSP2833x_I2C_DEFINES_H
|
||||||
|
|
||||||
|
//--------------------------------------------
|
||||||
|
// Defines
|
||||||
|
//--------------------------------------------
|
||||||
|
|
||||||
|
// Error Messages
|
||||||
|
#define I2C_ERROR 0xFFFF
|
||||||
|
#define I2C_ARB_LOST_ERROR 0x0001
|
||||||
|
#define I2C_NACK_ERROR 0x0002
|
||||||
|
#define I2C_BUS_BUSY_ERROR 0x1000
|
||||||
|
#define I2C_STP_NOT_READY_ERROR 0x5555
|
||||||
|
#define I2C_NO_FLAGS 0xAAAA
|
||||||
|
#define I2C_SUCCESS 0x0000
|
||||||
|
|
||||||
|
// Clear Status Flags
|
||||||
|
#define I2C_CLR_AL_BIT 0x0001
|
||||||
|
#define I2C_CLR_NACK_BIT 0x0002
|
||||||
|
#define I2C_CLR_ARDY_BIT 0x0004
|
||||||
|
#define I2C_CLR_RRDY_BIT 0x0008
|
||||||
|
#define I2C_CLR_SCD_BIT 0x0020
|
||||||
|
|
||||||
|
// Interrupt Source Messages
|
||||||
|
#define I2C_NO_ISRC 0x0000
|
||||||
|
#define I2C_ARB_ISRC 0x0001
|
||||||
|
#define I2C_NACK_ISRC 0x0002
|
||||||
|
#define I2C_ARDY_ISRC 0x0003
|
||||||
|
#define I2C_RX_ISRC 0x0004
|
||||||
|
#define I2C_TX_ISRC 0x0005
|
||||||
|
#define I2C_SCD_ISRC 0x0006
|
||||||
|
#define I2C_AAS_ISRC 0x0007
|
||||||
|
|
||||||
|
// I2CMSG structure defines
|
||||||
|
#define I2C_NO_STOP 0
|
||||||
|
#define I2C_YES_STOP 1
|
||||||
|
#define I2C_RECEIVE 0
|
||||||
|
#define I2C_TRANSMIT 1
|
||||||
|
#define I2C_MAX_BUFFER_SIZE 16
|
||||||
|
|
||||||
|
// I2C Slave State defines
|
||||||
|
#define I2C_NOTSLAVE 0
|
||||||
|
#define I2C_ADDR_AS_SLAVE 1
|
||||||
|
#define I2C_ST_MSG_READY 2
|
||||||
|
|
||||||
|
// I2C Slave Receiver messages defines
|
||||||
|
#define I2C_SND_MSG1 1
|
||||||
|
#define I2C_SND_MSG2 2
|
||||||
|
|
||||||
|
// I2C State defines
|
||||||
|
#define I2C_IDLE 0
|
||||||
|
#define I2C_SLAVE_RECEIVER 1
|
||||||
|
#define I2C_SLAVE_TRANSMITTER 2
|
||||||
|
#define I2C_MASTER_RECEIVER 3
|
||||||
|
#define I2C_MASTER_TRANSMITTER 4
|
||||||
|
|
||||||
|
// I2C Message Commands for I2CMSG struct
|
||||||
|
#define I2C_MSGSTAT_INACTIVE 0x0000
|
||||||
|
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
|
||||||
|
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
|
||||||
|
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
|
||||||
|
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
|
||||||
|
#define I2C_MSGSTAT_RESTART 0x0022
|
||||||
|
#define I2C_MSGSTAT_READ_BUSY 0x0023
|
||||||
|
|
||||||
|
// Generic defines
|
||||||
|
#define I2C_TRUE 1
|
||||||
|
#define I2C_FALSE 0
|
||||||
|
#define I2C_YES 1
|
||||||
|
#define I2C_NO 0
|
||||||
|
#define I2C_DUMMY_BYTE 0
|
||||||
|
|
||||||
|
|
||||||
|
//--------------------------------------------
|
||||||
|
// Structures
|
||||||
|
//--------------------------------------------
|
||||||
|
|
||||||
|
// I2C Message Structure
|
||||||
|
struct I2CMSG {
|
||||||
|
Uint16 MsgStatus; // Word stating what state msg is in:
|
||||||
|
// I2C_MSGCMD_INACTIVE = do not send msg
|
||||||
|
// I2C_MSGCMD_BUSY = msg start has been sent,
|
||||||
|
// awaiting stop
|
||||||
|
// I2C_MSGCMD_SEND_WITHSTOP = command to send
|
||||||
|
// master trans msg complete with a stop bit
|
||||||
|
// I2C_MSGCMD_SEND_NOSTOP = command to send
|
||||||
|
// master trans msg without the stop bit
|
||||||
|
// I2C_MSGCMD_RESTART = command to send a restart
|
||||||
|
// as a master receiver with a stop bit
|
||||||
|
Uint16 SlaveAddress; // I2C address of slave msg is intended for
|
||||||
|
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
|
||||||
|
Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
|
||||||
|
Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
|
||||||
|
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
|
||||||
|
// MAX_BUFFER_SIZE can be is 16 due to
|
||||||
|
// the FIFO's
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
#endif // end of DSP2833x_I2C_DEFINES_H definition
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
5850
v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
Normal file
5850
v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
Normal file
File diff suppressed because it is too large
Load Diff
22
v120/DSP2833x_common/include/DSP28x_Project.h
Normal file
22
v120/DSP2833x_common/include/DSP28x_Project.h
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
|
||||||
|
// TI File $Revision: /main/1 $
|
||||||
|
// Checkin $Date: April 22, 2008 14:35:56 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP28x_Project.h
|
||||||
|
//
|
||||||
|
// TITLE: DSP28x Project Headerfile and Examples Include File
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#ifndef DSP28x_PROJECT_H
|
||||||
|
#define DSP28x_PROJECT_H
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||||
|
|
||||||
|
#endif // end of DSP28x_PROJECT_H definition
|
||||||
|
|
||||||
4493
v120/DSP2833x_common/include/IQmathLib.h
Normal file
4493
v120/DSP2833x_common/include/IQmathLib.h
Normal file
File diff suppressed because it is too large
Load Diff
52
v120/DSP2833x_common/include/SFO.h
Normal file
52
v120/DSP2833x_common/include/SFO.h
Normal file
@ -0,0 +1,52 @@
|
|||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: SFO.H
|
||||||
|
//
|
||||||
|
// TITLE: Scale Factor Optimizer Library Interface Header
|
||||||
|
//
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// Ver | dd mmm yyyy | Who | Description of changes
|
||||||
|
// =====|=============|======|===============================================
|
||||||
|
// 0.01| 09 Jan 2004 | TI | New module
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Description: This header provides the function call interface
|
||||||
|
// for the scale factor optimizer for the 'F2833x.
|
||||||
|
//============================================================================
|
||||||
|
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Multiple include Guard
|
||||||
|
//============================================================================
|
||||||
|
#ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___
|
||||||
|
#define __4090522384024n8273240x3438jx43087401r34ru32r0___
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// C++ namespace
|
||||||
|
//============================================================================
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Function prototypes for MEP SFO
|
||||||
|
//============================================================================
|
||||||
|
void SFO_MepEn(int nEpwmModule);
|
||||||
|
void SFO_MepDis(int nEpwmModule);
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Multiple include Guard
|
||||||
|
//============================================================================
|
||||||
|
#endif // End: Multiple include Guard
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// C++ namespace
|
||||||
|
//============================================================================
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
70
v120/DSP2833x_common/include/SFO_V5.h
Normal file
70
v120/DSP2833x_common/include/SFO_V5.h
Normal file
@ -0,0 +1,70 @@
|
|||||||
|
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: SFO_V5.H
|
||||||
|
//
|
||||||
|
// TITLE: Scale Factor Optimizer Library V5 Interface Header
|
||||||
|
//
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// Ver | dd mmm yyyy | Who | Description of changes
|
||||||
|
// =====|=============|======|===============================================
|
||||||
|
// 0.01| 09 Jan 2004 | TI | New module
|
||||||
|
// 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Description: This header provides the function call interface
|
||||||
|
// for the scale factor optimizer V5. For more
|
||||||
|
// information on the SFO function usage and
|
||||||
|
// limitations, see the HRPWM Reference Guide
|
||||||
|
// (spru924) on the TI website.
|
||||||
|
//============================================================================
|
||||||
|
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Multiple include Guard
|
||||||
|
//============================================================================
|
||||||
|
#ifndef _SFO_V5_H
|
||||||
|
#define _SFO_V5_H
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// C++ namespace
|
||||||
|
//============================================================================
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1
|
||||||
|
//============================================================================
|
||||||
|
#define PWM_CH 7 // Equal # of HRPWM channels PLUS 1
|
||||||
|
// i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc.
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Function prototypes for MEP SFO
|
||||||
|
//============================================================================
|
||||||
|
|
||||||
|
int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function
|
||||||
|
int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Useful Defines when Using SFO Functions
|
||||||
|
//============================================================================
|
||||||
|
#define SFO_INCOMPLETE 0
|
||||||
|
#define SFO_COMPLETE 1
|
||||||
|
#define SFO_OUTRANGE_ERROR 2
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// Multiple include Guard
|
||||||
|
//============================================================================
|
||||||
|
#endif // End: Multiple include Guard
|
||||||
|
|
||||||
|
//============================================================================
|
||||||
|
// C++ namespace
|
||||||
|
//============================================================================
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* extern "C" */
|
||||||
BIN
v120/DSP2833x_common/lib/IQmath.lib
Normal file
BIN
v120/DSP2833x_common/lib/IQmath.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/IQmath_fpu32.lib
Normal file
BIN
v120/DSP2833x_common/lib/IQmath_fpu32.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib
Normal file
Binary file not shown.
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib
Normal file
BIN
v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib
Normal file
Binary file not shown.
42
v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
Normal file
42
v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
Normal file
@ -0,0 +1,42 @@
|
|||||||
|
;; TI File $Revision: /main/1 $
|
||||||
|
;; Checkin $Date: July 30, 2007 10:29:23 $
|
||||||
|
;;###########################################################################
|
||||||
|
;;
|
||||||
|
;; FILE: ADC_cal.asm
|
||||||
|
;;
|
||||||
|
;; TITLE: 2833x Boot Rom ADC Cal routine.
|
||||||
|
;;
|
||||||
|
;; Functions:
|
||||||
|
;;
|
||||||
|
;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers
|
||||||
|
;; Notes:
|
||||||
|
;;
|
||||||
|
;;###########################################################################
|
||||||
|
;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
;; $Release Date: August 1, 2008 $
|
||||||
|
;;###########################################################################
|
||||||
|
|
||||||
|
.def _ADC_cal
|
||||||
|
.asg "0x711C", ADCREFSEL_LOC
|
||||||
|
|
||||||
|
;-----------------------------------------------
|
||||||
|
; _ADC_cal
|
||||||
|
;-----------------------------------------------
|
||||||
|
;-----------------------------------------------
|
||||||
|
; This is the ADC cal routine.This routine is programmed into
|
||||||
|
; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
|
||||||
|
; holders for calibration data.
|
||||||
|
;The actual values programmed by TI are device specific.
|
||||||
|
;
|
||||||
|
; This function assumes that the clocks have been
|
||||||
|
; enabled to the ADC module.
|
||||||
|
;-----------------------------------------------
|
||||||
|
|
||||||
|
.sect ".adc_cal"
|
||||||
|
|
||||||
|
_ADC_cal
|
||||||
|
MOVW DP, #ADCREFSEL_LOC >> 6
|
||||||
|
MOV @28, #0xAAAA ; actual value may not be 0xAAAA
|
||||||
|
MOV @29, #0xBBBB ; actual value may not be 0xBBBB
|
||||||
|
LRETR
|
||||||
|
;eof ----------
|
||||||
65
v120/DSP2833x_common/source/DSP2833x_Adc.c
Normal file
65
v120/DSP2833x_common/source/DSP2833x_Adc.c
Normal file
@ -0,0 +1,65 @@
|
|||||||
|
// TI File $Revision: /main/5 $
|
||||||
|
// Checkin $Date: October 23, 2007 13:34:09 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_Adc.c
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x ADC Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||||
|
|
||||||
|
#define ADC_usDELAY 5000L
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// InitAdc:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes ADC to a known state.
|
||||||
|
//
|
||||||
|
void InitAdc(void)
|
||||||
|
{
|
||||||
|
extern void DSP28x_usDelay(Uint32 Count);
|
||||||
|
|
||||||
|
|
||||||
|
// *IMPORTANT*
|
||||||
|
// The ADC_cal function, which copies the ADC calibration values from TI reserved
|
||||||
|
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
|
||||||
|
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
|
||||||
|
// following function MUST be called for the ADC to function according
|
||||||
|
// to specification. The clocks to the ADC MUST be enabled before calling this
|
||||||
|
// function.
|
||||||
|
// See the device data manual and/or the ADC Reference
|
||||||
|
// Manual for more information.
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
|
||||||
|
ADC_cal();
|
||||||
|
EDIS;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// To powerup the ADC the ADCENCLK bit should be set first to enable
|
||||||
|
// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
|
||||||
|
// Before the first conversion is performed a 5ms delay must be observed
|
||||||
|
// after power up to give all analog circuits time to power up and settle
|
||||||
|
|
||||||
|
// Please note that for the delay function below to operate correctly the
|
||||||
|
// CPU_RATE define statement in the DSP2833x_Examples.h file must
|
||||||
|
// contain the correct CPU clock period in nanoseconds.
|
||||||
|
|
||||||
|
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01;
|
||||||
|
AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
|
||||||
|
DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
|
||||||
|
//pause_us(50L);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
67
v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm
Normal file
67
v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
;// TI File $Revision: /main/3 $
|
||||||
|
;// Checkin $Date: June 26, 2007 16:41:07 $
|
||||||
|
;//###########################################################################
|
||||||
|
;//
|
||||||
|
;// FILE: DSP2833x_CSMPasswords.asm
|
||||||
|
;//
|
||||||
|
;// TITLE: DSP2833x Code Security Module Passwords.
|
||||||
|
;//
|
||||||
|
;// DESCRIPTION:
|
||||||
|
;//
|
||||||
|
;// This file is used to specify password values to
|
||||||
|
;// program into the CSM password locations in Flash
|
||||||
|
;// at 0x33FFF8 - 0x33FFFF.
|
||||||
|
;//
|
||||||
|
;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are
|
||||||
|
;// all programmed to 0x0000
|
||||||
|
;//
|
||||||
|
;//###########################################################################
|
||||||
|
;//
|
||||||
|
;// Original source based on D.A.
|
||||||
|
;//
|
||||||
|
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
;// $Release Date: August 1, 2008 $
|
||||||
|
;//###########################################################################
|
||||||
|
|
||||||
|
; The "csmpasswords" section contains the actual CSM passwords that will be
|
||||||
|
; linked and programmed into to the CSM password locations (PWL) in flash.
|
||||||
|
; These passwords must be known in order to unlock the CSM module.
|
||||||
|
; All 0xFFFF's (erased) is the default value for the password locations (PWL).
|
||||||
|
|
||||||
|
; It is recommended that all passwords be left as 0xFFFF during code
|
||||||
|
; development. Passwords of 0xFFFF do not activate code security and dummy
|
||||||
|
; reads of the CSM PWL registers is all that is required to unlock the CSM.
|
||||||
|
; When code development is complete, modify the passwords to activate the
|
||||||
|
; code security module.
|
||||||
|
|
||||||
|
.sect "csmpasswds"
|
||||||
|
|
||||||
|
.int 0xFFFF ;PWL0 (LSW of 128-bit password)
|
||||||
|
.int 0xFFFF ;PWL1
|
||||||
|
.int 0xFFFF ;PWL2
|
||||||
|
.int 0xFFFF ;PWL3
|
||||||
|
.int 0xFFFF ;PWL4
|
||||||
|
.int 0xFFFF ;PWL5
|
||||||
|
.int 0xFFFF ;PWL6
|
||||||
|
.int 0xFFFF ;PWL7 (MSW of 128-bit password)
|
||||||
|
|
||||||
|
;----------------------------------------------------------------------
|
||||||
|
|
||||||
|
; For code security operation, all addresses between 0x33FF80 and
|
||||||
|
; 0X33fff5 cannot be used as program code or data. These locations
|
||||||
|
; must be programmed to 0x0000 when the code security password locations
|
||||||
|
; (PWL) are programmed. If security is not a concern, then these addresses
|
||||||
|
; can be used for code or data.
|
||||||
|
|
||||||
|
; The section "csm_rsvd" can be used to program these locations to 0x0000.
|
||||||
|
|
||||||
|
.sect "csm_rsvd"
|
||||||
|
.loop (33FFF5h - 33FF80h + 1)
|
||||||
|
.int 0x0000
|
||||||
|
.endloop
|
||||||
|
|
||||||
|
;//===========================================================================
|
||||||
|
;// End of file.
|
||||||
|
;//===========================================================================
|
||||||
|
|
||||||
|
|
||||||
86
v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm
Normal file
86
v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm
Normal file
@ -0,0 +1,86 @@
|
|||||||
|
;// TI File $Revision: /main/1 $
|
||||||
|
;// Checkin $Date: August 18, 2006 13:45:55 $
|
||||||
|
;//###########################################################################
|
||||||
|
;//
|
||||||
|
;// FILE: DSP2833x_CodeStartBranch.asm
|
||||||
|
;//
|
||||||
|
;// TITLE: Branch for redirecting code execution after boot.
|
||||||
|
;//
|
||||||
|
;// For these examples, code_start is the first code that is executed after
|
||||||
|
;// exiting the boot ROM code.
|
||||||
|
;//
|
||||||
|
;// The codestart section in the linker cmd file is used to physically place
|
||||||
|
;// this code at the correct memory location. This section should be placed
|
||||||
|
;// at the location the BOOT ROM will re-direct the code to. For example,
|
||||||
|
;// for boot to FLASH this code will be located at 0x3f7ff6.
|
||||||
|
;//
|
||||||
|
;// In addition, the example DSP2833x projects are setup such that the codegen
|
||||||
|
;// entry point is also set to the code_start label. This is done by linker
|
||||||
|
;// option -e in the project build options. When the debugger loads the code,
|
||||||
|
;// it will automatically set the PC to the "entry point" address indicated by
|
||||||
|
;// the -e linker option. In this case the debugger is simply assigning the PC,
|
||||||
|
;// it is not the same as a full reset of the device.
|
||||||
|
;//
|
||||||
|
;// The compiler may warn that the entry point for the project is other then
|
||||||
|
;// _c_init00. _c_init00 is the C environment setup and is run before
|
||||||
|
;// main() is entered. The code_start code will re-direct the execution
|
||||||
|
;// to _c_init00 and thus there is no worry and this warning can be ignored.
|
||||||
|
;//
|
||||||
|
;//###########################################################################
|
||||||
|
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
;// $Release Date: August 1, 2008 $
|
||||||
|
;//###########################################################################
|
||||||
|
|
||||||
|
|
||||||
|
***********************************************************************
|
||||||
|
|
||||||
|
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
|
||||||
|
|
||||||
|
.ref _c_int00
|
||||||
|
.global code_start
|
||||||
|
|
||||||
|
***********************************************************************
|
||||||
|
* Function: codestart section
|
||||||
|
*
|
||||||
|
* Description: Branch to code starting point
|
||||||
|
***********************************************************************
|
||||||
|
|
||||||
|
.sect "codestart"
|
||||||
|
|
||||||
|
code_start:
|
||||||
|
.if WD_DISABLE == 1
|
||||||
|
LB wd_disable ;Branch to watchdog disable code
|
||||||
|
.else
|
||||||
|
LB _c_int00 ;Branch to start of boot.asm in RTS library
|
||||||
|
.endif
|
||||||
|
|
||||||
|
;end codestart section
|
||||||
|
|
||||||
|
|
||||||
|
***********************************************************************
|
||||||
|
* Function: wd_disable
|
||||||
|
*
|
||||||
|
* Description: Disables the watchdog timer
|
||||||
|
***********************************************************************
|
||||||
|
.if WD_DISABLE == 1
|
||||||
|
|
||||||
|
.text
|
||||||
|
wd_disable:
|
||||||
|
SETC OBJMODE ;Set OBJMODE for 28x object code
|
||||||
|
EALLOW ;Enable EALLOW protected register access
|
||||||
|
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
|
||||||
|
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
|
||||||
|
EDIS ;Disable EALLOW protected register access
|
||||||
|
LB _c_int00 ;Branch to start of boot.asm in RTS library
|
||||||
|
|
||||||
|
.endif
|
||||||
|
|
||||||
|
;end wd_disable
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
||||||
|
;//===========================================================================
|
||||||
|
;// End of file.
|
||||||
|
;//===========================================================================
|
||||||
115
v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
Normal file
115
v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
Normal file
@ -0,0 +1,115 @@
|
|||||||
|
// TI File $Revision: /main/3 $
|
||||||
|
// Checkin $Date: March 16, 2007 08:37:30 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_CpuTimers.c
|
||||||
|
//
|
||||||
|
// TITLE: CPU 32-bit Timers Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
|
||||||
|
// other realtime operating systems.
|
||||||
|
//
|
||||||
|
// Do not use these two timers in your application if you ever plan
|
||||||
|
// on integrating DSP-BIOS or another realtime OS.
|
||||||
|
//
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // Examples Include File
|
||||||
|
|
||||||
|
struct CPUTIMER_VARS CpuTimer0;
|
||||||
|
|
||||||
|
// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS.
|
||||||
|
struct CPUTIMER_VARS CpuTimer1;
|
||||||
|
struct CPUTIMER_VARS CpuTimer2;
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// InitCpuTimers:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes all three CPU timers to a known state.
|
||||||
|
//
|
||||||
|
void InitCpuTimers(void)
|
||||||
|
{
|
||||||
|
// CPU Timer 0
|
||||||
|
// Initialize address pointers to respective timer registers:
|
||||||
|
CpuTimer0.RegsAddr = &CpuTimer0Regs;
|
||||||
|
// Initialize timer period to maximum:
|
||||||
|
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
|
||||||
|
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||||
|
CpuTimer0Regs.TPR.all = 0;
|
||||||
|
CpuTimer0Regs.TPRH.all = 0;
|
||||||
|
// Make sure timer is stopped:
|
||||||
|
CpuTimer0Regs.TCR.bit.TSS = 1;
|
||||||
|
// Reload all counter register with period value:
|
||||||
|
CpuTimer0Regs.TCR.bit.TRB = 1;
|
||||||
|
// Reset interrupt counters:
|
||||||
|
CpuTimer0.InterruptCount = 0;
|
||||||
|
|
||||||
|
|
||||||
|
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
|
||||||
|
// Do not use these two timers if you ever plan on integrating
|
||||||
|
// DSP-BIOS or another realtime OS.
|
||||||
|
//
|
||||||
|
// Initialize address pointers to respective timer registers:
|
||||||
|
CpuTimer1.RegsAddr = &CpuTimer1Regs;
|
||||||
|
CpuTimer2.RegsAddr = &CpuTimer2Regs;
|
||||||
|
// Initialize timer period to maximum:
|
||||||
|
CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
|
||||||
|
CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
|
||||||
|
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||||
|
CpuTimer1Regs.TPR.all = 0;
|
||||||
|
CpuTimer1Regs.TPRH.all = 0;
|
||||||
|
CpuTimer2Regs.TPR.all = 0;
|
||||||
|
CpuTimer2Regs.TPRH.all = 0;
|
||||||
|
// Make sure timers are stopped:
|
||||||
|
CpuTimer1Regs.TCR.bit.TSS = 1;
|
||||||
|
CpuTimer2Regs.TCR.bit.TSS = 1;
|
||||||
|
// Reload all counter register with period value:
|
||||||
|
CpuTimer1Regs.TCR.bit.TRB = 1;
|
||||||
|
CpuTimer2Regs.TCR.bit.TRB = 1;
|
||||||
|
// Reset interrupt counters:
|
||||||
|
CpuTimer1.InterruptCount = 0;
|
||||||
|
CpuTimer2.InterruptCount = 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// ConfigCpuTimer:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes the selected timer to the period specified
|
||||||
|
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
|
||||||
|
// and the period in "uSeconds". The timer is held in the stopped state
|
||||||
|
// after configuration.
|
||||||
|
//
|
||||||
|
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
|
||||||
|
{
|
||||||
|
Uint32 temp;
|
||||||
|
|
||||||
|
// Initialize timer period:
|
||||||
|
Timer->CPUFreqInMHz = Freq;
|
||||||
|
Timer->PeriodInUSec = Period;
|
||||||
|
temp = (long) (Freq * Period);
|
||||||
|
Timer->RegsAddr->PRD.all = temp;
|
||||||
|
|
||||||
|
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||||
|
Timer->RegsAddr->TPR.all = 0;
|
||||||
|
Timer->RegsAddr->TPRH.all = 0;
|
||||||
|
|
||||||
|
// Initialize timer control register:
|
||||||
|
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
|
||||||
|
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
|
||||||
|
Timer->RegsAddr->TCR.bit.SOFT = 0;
|
||||||
|
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
|
||||||
|
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
|
||||||
|
|
||||||
|
// Reset interrupt counter:
|
||||||
|
Timer->InterruptCount = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
28
v120/DSP2833x_common/source/DSP2833x_DBGIER.asm
Normal file
28
v120/DSP2833x_common/source/DSP2833x_DBGIER.asm
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
;// TI File $Revision: /main/1 $
|
||||||
|
;// Checkin $Date: August 18, 2006 13:46:03 $
|
||||||
|
;//###########################################################################
|
||||||
|
;//
|
||||||
|
;// FILE: DSP2833x_DBGIER.asm
|
||||||
|
;//
|
||||||
|
;// TITLE: Set the DBGIER register
|
||||||
|
;//
|
||||||
|
;// DESCRIPTION:
|
||||||
|
;//
|
||||||
|
;// Function to set the DBGIER register (for realtime emulation).
|
||||||
|
;// Function Prototype: void SetDBGIER(Uint16)
|
||||||
|
;// Useage: SetDBGIER(value);
|
||||||
|
;// Input Parameters: Uint16 value = value to put in DBGIER register.
|
||||||
|
;// Return Value: none
|
||||||
|
;//
|
||||||
|
;//###########################################################################
|
||||||
|
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
;// $Release Date: August 1, 2008 $
|
||||||
|
;//###########################################################################
|
||||||
|
.global _SetDBGIER
|
||||||
|
.text
|
||||||
|
|
||||||
|
_SetDBGIER:
|
||||||
|
MOV *SP++,AL
|
||||||
|
POP DBGIER
|
||||||
|
LRETR
|
||||||
|
|
||||||
590
v120/DSP2833x_common/source/DSP2833x_DMA.c
Normal file
590
v120/DSP2833x_common/source/DSP2833x_DMA.c
Normal file
@ -0,0 +1,590 @@
|
|||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_DMA.c
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x Device DMA Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // Examples Include File
|
||||||
|
|
||||||
|
// This function initializes the DMA to a known state.
|
||||||
|
//
|
||||||
|
void DMAInitialize(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Perform a hard reset on DMA
|
||||||
|
DmaRegs.DMACTRL.bit.HARDRESET = 1;
|
||||||
|
asm (" nop"); // one NOP required after HARDRESET
|
||||||
|
|
||||||
|
// Allow DMA to run free on emulation suspend
|
||||||
|
DmaRegs.DEBUGCTRL.bit.FREE = 1;
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH1.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH1.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
// This function starts DMA Channel 1.
|
||||||
|
void StartDMACH1(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH1.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH2.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH2.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH2.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH2.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH2.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// This function starts DMA Channel 2.
|
||||||
|
void StartDMACH2(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH2.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH3.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH3.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH3.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH3.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
// This function starts DMA Channel 3.
|
||||||
|
void StartDMACH3(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH3.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// This function starts DMA Channel 4.
|
||||||
|
void StartDMACH4(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH4.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
// This function starts DMA Channel 5.
|
||||||
|
void StartDMACH5(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH5.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up SOURCE address:
|
||||||
|
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||||
|
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||||
|
|
||||||
|
// Set up DESTINATION address:
|
||||||
|
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||||
|
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up BURST registers:
|
||||||
|
DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||||
|
DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||||
|
DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||||
|
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up TRANSFER registers:
|
||||||
|
DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||||
|
DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up WRAP registers:
|
||||||
|
DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||||
|
DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||||
|
|
||||||
|
DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||||
|
DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
// Set up MODE Register:
|
||||||
|
DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||||
|
DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||||
|
DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||||
|
DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||||
|
DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||||
|
DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||||
|
DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||||
|
DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||||
|
DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||||
|
DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||||
|
|
||||||
|
// Clear any spurious flags:
|
||||||
|
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||||
|
DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||||
|
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||||
|
|
||||||
|
// Initialize PIE vector for CPU interrupt:
|
||||||
|
PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
// This function starts DMA Channel 6.
|
||||||
|
void StartDMACH6(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
DmaRegs.CH6.CONTROL.bit.RUN = 1;
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// No more.
|
||||||
|
//===========================================================================
|
||||||
1187
v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c
Normal file
1187
v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c
Normal file
File diff suppressed because it is too large
Load Diff
65
v120/DSP2833x_common/source/DSP2833x_DisInt.asm
Normal file
65
v120/DSP2833x_common/source/DSP2833x_DisInt.asm
Normal file
@ -0,0 +1,65 @@
|
|||||||
|
;// TI File $Revision: /main/1 $
|
||||||
|
;// Checkin $Date: August 18, 2006 13:46:09 $
|
||||||
|
;//###########################################################################
|
||||||
|
;//
|
||||||
|
;// FILE: DSP2833x_DisInt.asm
|
||||||
|
;//
|
||||||
|
;// TITLE: Disable and Restore INTM and DBGM
|
||||||
|
;//
|
||||||
|
;// Function Prototypes:
|
||||||
|
;//
|
||||||
|
;// Uint16 DSP28x_DisableInt();
|
||||||
|
;// and void DSP28x_RestoreInt(Uint16 Stat0);
|
||||||
|
;//
|
||||||
|
;// Usage:
|
||||||
|
;//
|
||||||
|
;// DSP28x_DisableInt() sets both the INTM and DBGM
|
||||||
|
;// bits to disable maskable interrupts. Before doing
|
||||||
|
;// this, the current value of ST1 is stored on the stack
|
||||||
|
;// so that the values can be restored later. The value
|
||||||
|
;// of ST1 before the masks are set is returned to the
|
||||||
|
;// user in AL. This is then used to restore their state
|
||||||
|
;// via the DSP28x_RestoreInt(Uint16 ST1) function.
|
||||||
|
;//
|
||||||
|
;// Example
|
||||||
|
;//
|
||||||
|
;// Uint16 StatusReg1
|
||||||
|
;// StatusReg1 = DSP28x_DisableInt();
|
||||||
|
;//
|
||||||
|
;// ... May also want to disable INTM here
|
||||||
|
;//
|
||||||
|
;// ... code here
|
||||||
|
;//
|
||||||
|
;// DSP28x_RestoreInt(StatusReg1);
|
||||||
|
;//
|
||||||
|
;// ... Restore INTM enable
|
||||||
|
;//
|
||||||
|
;//###########################################################################
|
||||||
|
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
;// $Release Date: August 1, 2008 $
|
||||||
|
;//###########################################################################
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
.def _DSP28x_DisableInt
|
||||||
|
.def _DSP28x_RestoreInt
|
||||||
|
|
||||||
|
|
||||||
|
_DSP28x_DisableInt:
|
||||||
|
PUSH ST1
|
||||||
|
SETC INTM,DBGM
|
||||||
|
MOV AL, *--SP
|
||||||
|
LRETR
|
||||||
|
|
||||||
|
_DSP28x_RestoreInt:
|
||||||
|
MOV *SP++, AL
|
||||||
|
POP ST1
|
||||||
|
LRETR
|
||||||
|
|
||||||
|
|
||||||
|
;//===========================================================================
|
||||||
|
;// End of file.
|
||||||
|
;//===========================================================================
|
||||||
|
|
||||||
|
|
||||||
404
v120/DSP2833x_common/source/DSP2833x_ECan.c
Normal file
404
v120/DSP2833x_common/source/DSP2833x_ECan.c
Normal file
@ -0,0 +1,404 @@
|
|||||||
|
// TI File $Revision: /main/8 $
|
||||||
|
// Checkin $Date: June 25, 2008 15:19:07 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_ECan.c
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// InitECan:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes the eCAN module to a known state.
|
||||||
|
//
|
||||||
|
void InitECan(void)
|
||||||
|
{
|
||||||
|
InitECana();
|
||||||
|
#if DSP28_ECANB
|
||||||
|
InitECanb();
|
||||||
|
#endif // if DSP28_ECANB
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitECana(void) // Initialize eCAN-A module
|
||||||
|
{
|
||||||
|
/* Create a shadow register structure for the CAN control registers. This is
|
||||||
|
needed, since only 32-bit access is allowed to these registers. 16-bit access
|
||||||
|
to these registers could potentially corrupt the register contents or return
|
||||||
|
false data. This is especially true while writing to/reading from a bit
|
||||||
|
(or group of bits) among bits 16 - 31 */
|
||||||
|
|
||||||
|
struct ECAN_REGS ECanaShadow;
|
||||||
|
|
||||||
|
EALLOW; // EALLOW enables access to protected bits
|
||||||
|
|
||||||
|
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
|
||||||
|
|
||||||
|
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
|
||||||
|
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
|
||||||
|
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
|
||||||
|
|
||||||
|
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
|
||||||
|
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
|
||||||
|
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
|
||||||
|
|
||||||
|
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
|
||||||
|
// HECC mode also enables time-stamping feature
|
||||||
|
|
||||||
|
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||||
|
ECanaShadow.CANMC.bit.SCB = 1;
|
||||||
|
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||||
|
|
||||||
|
/* Initialize all bits of 'Master Control Field' to zero */
|
||||||
|
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
|
||||||
|
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
|
||||||
|
|
||||||
|
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||||
|
|
||||||
|
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||||
|
// as a matter of precaution.
|
||||||
|
|
||||||
|
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
|
||||||
|
|
||||||
|
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
|
||||||
|
|
||||||
|
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
|
||||||
|
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure bit timing parameters for eCANA*/
|
||||||
|
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||||
|
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||||
|
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||||
|
|
||||||
|
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||||
|
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
|
||||||
|
|
||||||
|
ECanaShadow.CANBTC.all = 0;
|
||||||
|
|
||||||
|
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||||
|
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
|
||||||
|
See Note at End of File */
|
||||||
|
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||||
|
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
|
||||||
|
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
|
||||||
|
#endif
|
||||||
|
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||||
|
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
|
||||||
|
See Note at End of File */
|
||||||
|
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||||
|
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
|
||||||
|
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
ECanaShadow.CANBTC.bit.SAM = 1;
|
||||||
|
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
|
||||||
|
|
||||||
|
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||||
|
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||||
|
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||||
|
|
||||||
|
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||||
|
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
|
||||||
|
|
||||||
|
/* Disable all Mailboxes */
|
||||||
|
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (DSP28_ECANB)
|
||||||
|
void InitECanb(void) // Initialize eCAN-B module
|
||||||
|
{
|
||||||
|
/* Create a shadow register structure for the CAN control registers. This is
|
||||||
|
needed, since only 32-bit access is allowed to these registers. 16-bit access
|
||||||
|
to these registers could potentially corrupt the register contents or return
|
||||||
|
false data. This is especially true while writing to/reading from a bit
|
||||||
|
(or group of bits) among bits 16 - 31 */
|
||||||
|
|
||||||
|
struct ECAN_REGS ECanbShadow;
|
||||||
|
|
||||||
|
EALLOW; // EALLOW enables access to protected bits
|
||||||
|
|
||||||
|
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
|
||||||
|
|
||||||
|
ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
|
||||||
|
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
|
||||||
|
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
|
||||||
|
|
||||||
|
ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
|
||||||
|
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
|
||||||
|
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
|
||||||
|
|
||||||
|
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
|
||||||
|
|
||||||
|
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||||
|
ECanbShadow.CANMC.bit.SCB = 1;
|
||||||
|
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||||
|
|
||||||
|
/* Initialize all bits of 'Master Control Field' to zero */
|
||||||
|
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
|
||||||
|
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
|
||||||
|
|
||||||
|
ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||||
|
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||||
|
|
||||||
|
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||||
|
// as a matter of precaution.
|
||||||
|
|
||||||
|
ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
|
||||||
|
|
||||||
|
ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
|
||||||
|
|
||||||
|
ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
|
||||||
|
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure bit timing parameters for eCANB*/
|
||||||
|
|
||||||
|
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||||
|
ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||||
|
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||||
|
|
||||||
|
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||||
|
} while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared..
|
||||||
|
|
||||||
|
|
||||||
|
ECanbShadow.CANBTC.all = 0;
|
||||||
|
|
||||||
|
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||||
|
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
|
||||||
|
See Note at end of file */
|
||||||
|
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||||
|
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
|
||||||
|
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
|
||||||
|
#endif
|
||||||
|
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||||
|
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
|
||||||
|
See Note at end of file */
|
||||||
|
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||||
|
ECanbShadow.CANBTC.bit.TSEG2REG = 1;
|
||||||
|
ECanbShadow.CANBTC.bit.TSEG1REG = 6;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ECanbShadow.CANBTC.bit.SAM = 1;
|
||||||
|
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
|
||||||
|
|
||||||
|
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||||
|
ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||||
|
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||||
|
|
||||||
|
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||||
|
} while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
|
||||||
|
|
||||||
|
|
||||||
|
/* Disable all Mailboxes */
|
||||||
|
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // if DSP28_ECANB
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Example: InitECanGpio:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes GPIO pins to function as eCAN pins
|
||||||
|
//
|
||||||
|
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||||
|
// peripheral functional pins. By default all pins come up as GPIO
|
||||||
|
// inputs after reset.
|
||||||
|
//
|
||||||
|
// Caution:
|
||||||
|
// Only one GPIO pin should be enabled for CANTXA/B operation.
|
||||||
|
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
|
||||||
|
void InitECanGpio(void)
|
||||||
|
{
|
||||||
|
InitECanaGpio();
|
||||||
|
#if (DSP28_ECANB)
|
||||||
|
InitECanbGpio();
|
||||||
|
#endif // if DSP28_ECANB
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitECanaGpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected CAN pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA)
|
||||||
|
|
||||||
|
/* Set qualification for selected CAN pins to asynch only */
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// This will select asynch (no qualification) for the selected pins.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure eCAN-A pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAN functional pins.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (DSP28_ECANB)
|
||||||
|
void InitECanbGpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected CAN pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB)
|
||||||
|
|
||||||
|
/* Set qualification for selected CAN pins to asynch only */
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// This will select asynch (no qualification) for the selected pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
|
||||||
|
|
||||||
|
/* Configure eCAN-B pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAN functional pins.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // if DSP28_ECANB
|
||||||
|
|
||||||
|
/*
|
||||||
|
Note: Bit timing parameters must be chosen based on the network parameters such
|
||||||
|
as the sampling point desired and the propagation delay of the network.
|
||||||
|
The propagation delay is a function of length of the cable, delay introduced by
|
||||||
|
the transceivers and opto/galvanic-isolators (if any).
|
||||||
|
|
||||||
|
The parameters used in this file must be changed taking into account the above
|
||||||
|
mentioned factors in order to arrive at the bit-timing parameters suitable
|
||||||
|
for a network.
|
||||||
|
|
||||||
|
*/
|
||||||
255
v120/DSP2833x_common/source/DSP2833x_ECap.c
Normal file
255
v120/DSP2833x_common/source/DSP2833x_ECap.c
Normal file
@ -0,0 +1,255 @@
|
|||||||
|
// TI File $Revision: /main/2 $
|
||||||
|
// Checkin $Date: March 15, 2007 16:54:36 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_ECap.c
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x eCAP Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// InitECap:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes the eCAP(s) to a known state.
|
||||||
|
//
|
||||||
|
void InitECap(void)
|
||||||
|
{
|
||||||
|
// Initialize eCAP1/2/3
|
||||||
|
|
||||||
|
//tbd...
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Example: InitECapGpio:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes GPIO pins to function as ECAP pins
|
||||||
|
//
|
||||||
|
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||||
|
// peripheral functional pins. By default all pins come up as GPIO
|
||||||
|
// inputs after reset.
|
||||||
|
//
|
||||||
|
// Caution:
|
||||||
|
// For each eCAP peripheral
|
||||||
|
// Only one GPIO pin should be enabled for ECAP operation.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
void InitECapGpio()
|
||||||
|
{
|
||||||
|
|
||||||
|
InitECap1Gpio();
|
||||||
|
#if (DSP28_ECAP2)
|
||||||
|
InitECap2Gpio();
|
||||||
|
#endif // endif DSP28_ECAP2
|
||||||
|
#if (DSP28_ECAP3)
|
||||||
|
InitECap3Gpio();
|
||||||
|
#endif // endif DSP28_ECAP3
|
||||||
|
#if (DSP28_ECAP4)
|
||||||
|
InitECap4Gpio();
|
||||||
|
#endif // endif DSP28_ECAP4
|
||||||
|
#if (DSP28_ECAP5)
|
||||||
|
InitECap5Gpio();
|
||||||
|
#endif // endif DSP28_ECAP5
|
||||||
|
#if (DSP28_ECAP6)
|
||||||
|
InitECap6Gpio();
|
||||||
|
#endif // endif DSP28_ECAP6
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitECap1Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1)
|
||||||
|
// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1)
|
||||||
|
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; // Synch to SYSCLKOUT GPIO5 (CAP1)
|
||||||
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1)
|
||||||
|
// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Synch to SYSCLKOUT GPIO34 (CAP1)
|
||||||
|
|
||||||
|
/* Configure eCAP-1 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP1 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1
|
||||||
|
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if DSP28_ECAP2
|
||||||
|
void InitECap2Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2)
|
||||||
|
// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2)
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT GPIO7 (CAP2)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Synch to SYSCLKOUT GPIO25 (CAP2)
|
||||||
|
// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Synch to SYSCLKOUT GPIO37 (CAP2)
|
||||||
|
|
||||||
|
/* Configure eCAP-2 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP2 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2
|
||||||
|
// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_ECAP2
|
||||||
|
|
||||||
|
#if DSP28_ECAP3
|
||||||
|
void InitECap3Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3)
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3)
|
||||||
|
|
||||||
|
/* Configure eCAP-3 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_ECAP3
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_ECAP4
|
||||||
|
void InitECap4Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4)
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
|
||||||
|
|
||||||
|
/* Configure eCAP-4 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_ECAP4
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_ECAP5
|
||||||
|
void InitECap5Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5)
|
||||||
|
// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5)
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5)
|
||||||
|
// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
|
||||||
|
|
||||||
|
/* Configure eCAP-5 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5
|
||||||
|
// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_ECAP5
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_ECAP6
|
||||||
|
void InitECap6Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6)
|
||||||
|
// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6)
|
||||||
|
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6)
|
||||||
|
// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
|
||||||
|
|
||||||
|
/* Configure eCAP-5 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6
|
||||||
|
// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_ECAP6
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
316
v120/DSP2833x_common/source/DSP2833x_EPwm.c
Normal file
316
v120/DSP2833x_common/source/DSP2833x_EPwm.c
Normal file
@ -0,0 +1,316 @@
|
|||||||
|
// TI File $Revision: /main/1 $
|
||||||
|
// Checkin $Date: August 18, 2006 13:46:19 $
|
||||||
|
//###########################################################################
|
||||||
|
//
|
||||||
|
// FILE: DSP2833x_EPwm.c
|
||||||
|
//
|
||||||
|
// TITLE: DSP2833x ePWM Initialization & Support Functions.
|
||||||
|
//
|
||||||
|
//###########################################################################
|
||||||
|
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||||
|
// $Release Date: August 1, 2008 $
|
||||||
|
//###########################################################################
|
||||||
|
|
||||||
|
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||||
|
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// InitEPwm:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes the ePWM(s) to a known state.
|
||||||
|
//
|
||||||
|
void InitEPwm(void)
|
||||||
|
{
|
||||||
|
// Initialize ePWM1/2/3/4/5/6
|
||||||
|
|
||||||
|
//tbd...
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Example: InitEPwmGpio:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes GPIO pins to function as ePWM pins
|
||||||
|
//
|
||||||
|
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||||
|
// peripheral functional pins. By default all pins come up as GPIO
|
||||||
|
// inputs after reset.
|
||||||
|
//
|
||||||
|
|
||||||
|
void InitEPwmGpio(void)
|
||||||
|
{
|
||||||
|
InitEPwm1Gpio();
|
||||||
|
InitEPwm2Gpio();
|
||||||
|
InitEPwm3Gpio();
|
||||||
|
#if DSP28_EPWM4
|
||||||
|
InitEPwm4Gpio();
|
||||||
|
#endif // endif DSP28_EPWM4
|
||||||
|
#if DSP28_EPWM5
|
||||||
|
InitEPwm5Gpio();
|
||||||
|
#endif // endif DSP28_EPWM5
|
||||||
|
#if DSP28_EPWM6
|
||||||
|
InitEPwm6Gpio();
|
||||||
|
#endif // endif DSP28_EPWM6
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitEPwm1Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)
|
||||||
|
|
||||||
|
/* Configure ePWM-1 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM1 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitEPwm2Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B)
|
||||||
|
|
||||||
|
/* Configure ePWM-2 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM2 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitEPwm3Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B)
|
||||||
|
|
||||||
|
/* Configure ePWM-3 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM3 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_EPWM4
|
||||||
|
void InitEPwm4Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B)
|
||||||
|
|
||||||
|
/* Configure ePWM-4 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM4 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_EPWM4
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_EPWM5
|
||||||
|
void InitEPwm5Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B)
|
||||||
|
|
||||||
|
/* Configure ePWM-5 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM5 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_EPWM5
|
||||||
|
|
||||||
|
|
||||||
|
#if DSP28_EPWM6
|
||||||
|
void InitEPwm6Gpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B)
|
||||||
|
|
||||||
|
/* Configure ePWM-6 pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be ePWM6 functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
#endif // endif DSP28_EPWM6
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Example: InitEPwmSyncGpio:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes GPIO pins to function as ePWM Synch pins
|
||||||
|
//
|
||||||
|
|
||||||
|
void InitEPwmSyncGpio(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Configure EPWMSYNCI */
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNCI)
|
||||||
|
// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO32 (EPWMSYNCI)
|
||||||
|
|
||||||
|
/* Set qualification for selected pins to asynch only */
|
||||||
|
// This will select synch to SYSCLKOUT for the selected pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
|
||||||
|
// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)
|
||||||
|
|
||||||
|
/* Configure EPwmSync pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be EPwmSync functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; // Enable pull-up on GPIO6 (EPWMSYNCI)
|
||||||
|
// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2; // Enable pull-up on GPIO32 (EPWMSYNCI)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure EPWMSYNC0 */
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||||
|
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||||
|
|
||||||
|
// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||||
|
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Example: InitTzGpio:
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// This function initializes GPIO pins to function as Trip Zone (TZ) pins
|
||||||
|
//
|
||||||
|
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||||
|
// peripheral functional pins. By default all pins come up as GPIO
|
||||||
|
// inputs after reset.
|
||||||
|
//
|
||||||
|
|
||||||
|
void InitTzGpio(void)
|
||||||
|
{
|
||||||
|
EALLOW;
|
||||||
|
|
||||||
|
/* Enable internal pull-up for the selected pins */
|
||||||
|
// Pull-ups can be enabled or disabled by the user.
|
||||||
|
// This will enable the pullups for the specified pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3)
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6)
|
||||||
|
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6)
|
||||||
|
|
||||||
|
/* Set qualification for selected pins to asynch only */
|
||||||
|
// Inputs are synchronized to SYSCLKOUT by default.
|
||||||
|
// This will select asynch (no qualification) for the selected pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3)
|
||||||
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5)
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6)
|
||||||
|
// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6)
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure TZ pins using GPIO regs*/
|
||||||
|
// This specifies which of the possible GPIO pins will be TZ functional pins.
|
||||||
|
// Comment out other unwanted lines.
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3
|
||||||
|
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5
|
||||||
|
|
||||||
|
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6
|
||||||
|
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6
|
||||||
|
|
||||||
|
EDIS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//===========================================================================
|
||||||
|
// End of file.
|
||||||
|
//===========================================================================
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user