165 lines
3.7 KiB
C
165 lines
3.7 KiB
C
// TI File $Revision: /main/1 $
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// Checkin $Date: August 18, 2006 13:45:39 $
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//###########################################################################
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//
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// FILE: DSP2833x_EPwm_defines.h
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//
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// TITLE: #defines used in ePWM examples examples
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_EPWM_DEFINES_H
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#define DSP2833x_EPWM_DEFINES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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// TBCTL (Time-Base Control)
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//==========================
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// CTRMODE bits
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#define TB_COUNT_UP 0x0
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#define TB_COUNT_DOWN 0x1
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#define TB_COUNT_UPDOWN 0x2
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#define TB_FREEZE 0x3
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// PHSEN bit
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#define TB_DISABLE 0x0
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#define TB_ENABLE 0x1
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// PRDLD bit
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#define TB_SHADOW 0x0
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#define TB_IMMEDIATE 0x1
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// SYNCOSEL bits
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#define TB_SYNC_IN 0x0
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#define TB_CTR_ZERO 0x1
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#define TB_CTR_CMPB 0x2
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#define TB_SYNC_DISABLE 0x3
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// HSPCLKDIV and CLKDIV bits
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#define TB_DIV1 0x0
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#define TB_DIV2 0x1
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#define TB_DIV4 0x2
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// PHSDIR bit
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#define TB_DOWN 0x0
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#define TB_UP 0x1
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// CMPCTL (Compare Control)
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//==========================
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// LOADAMODE and LOADBMODE bits
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#define CC_CTR_ZERO 0x0
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#define CC_CTR_PRD 0x1
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#define CC_CTR_ZERO_PRD 0x2
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#define CC_LD_DISABLE 0x3
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// SHDWAMODE and SHDWBMODE bits
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#define CC_SHADOW 0x0
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#define CC_IMMEDIATE 0x1
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// AQCTLA and AQCTLB (Action Qualifier Control)
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//=============================================
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// ZRO, PRD, CAU, CAD, CBU, CBD bits
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#define AQ_NO_ACTION 0x0
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#define AQ_CLEAR 0x1
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#define AQ_SET 0x2
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#define AQ_TOGGLE 0x3
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// DBCTL (Dead-Band Control)
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//==========================
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// OUT MODE bits
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#define DB_DISABLE 0x0
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#define DBA_ENABLE 0x1
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#define DBB_ENABLE 0x2
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#define DB_FULL_ENABLE 0x3
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// POLSEL bits
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#define DB_ACTV_HI 0x0
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#define DB_ACTV_LOC 0x1
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#define DB_ACTV_HIC 0x2
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#define DB_ACTV_LO 0x3
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// IN MODE
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#define DBA_ALL 0x0
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#define DBB_RED_DBA_FED 0x1
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#define DBA_RED_DBB_FED 0x2
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#define DBB_ALL 0x3
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// CHPCTL (chopper control)
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//==========================
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// CHPEN bit
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#define CHP_DISABLE 0x0
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#define CHP_ENABLE 0x1
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// CHPFREQ bits
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#define CHP_DIV1 0x0
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#define CHP_DIV2 0x1
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#define CHP_DIV3 0x2
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#define CHP_DIV4 0x3
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#define CHP_DIV5 0x4
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#define CHP_DIV6 0x5
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#define CHP_DIV7 0x6
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#define CHP_DIV8 0x7
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// CHPDUTY bits
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#define CHP1_8TH 0x0
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#define CHP2_8TH 0x1
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#define CHP3_8TH 0x2
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#define CHP4_8TH 0x3
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#define CHP5_8TH 0x4
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#define CHP6_8TH 0x5
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#define CHP7_8TH 0x6
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// TZSEL (Trip Zone Select)
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//==========================
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// CBCn and OSHTn bits
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#define TZ_DISABLE 0x0
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#define TZ_ENABLE 0x1
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// TZCTL (Trip Zone Control)
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//==========================
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// TZA and TZB bits
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#define TZ_HIZ 0x0
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#define TZ_FORCE_HI 0x1
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#define TZ_FORCE_LO 0x2
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#define TZ_NO_CHANGE 0x3
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// ETSEL (Event Trigger Select)
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//=============================
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#define ET_CTR_ZERO 0x1
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#define ET_CTR_PRD 0x2
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#define ET_CTRU_CMPA 0x4
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#define ET_CTRD_CMPA 0x5
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#define ET_CTRU_CMPB 0x6
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#define ET_CTRD_CMPB 0x7
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// ETPS (Event Trigger Pre-scale)
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//===============================
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// INTPRD, SOCAPRD, SOCBPRD bits
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#define ET_DISABLE 0x0
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#define ET_1ST 0x1
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#define ET_2ND 0x2
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#define ET_3RD 0x3
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//--------------------------------
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// HRPWM (High Resolution PWM)
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//================================
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// HRCNFG
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#define HR_Disable 0x0
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#define HR_REP 0x1
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#define HR_FEP 0x2
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#define HR_BEP 0x3
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#define HR_CMP 0x0
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#define HR_PHS 0x1
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#define HR_CTR_ZERO 0x0
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#define HR_CTR_PRD 0x1
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // - end of DSP2833x_EPWM_DEFINES_H
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//===========================================================================
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// End of file.
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//===========================================================================
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