commit b8a0477c5cfd116e7b667ec976daf2ce28247a95 Author: nelolik Date: Mon Feb 15 09:56:02 2021 +0300 init commit. Проект каким он достался от Димы. diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..20749d1 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +./Debug diff --git a/ADC.c b/ADC.c new file mode 100644 index 0000000..60bb8df --- /dev/null +++ b/ADC.c @@ -0,0 +1,253 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP281x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "ADC.h" + +#include "log_to_mem.h" +#include "RS485.h" +#include "filter_bat2.h" + +#include "measure.h" +#include "message.h" +#include "package.h" + +#include "peripher.h" + +#define SIZE_ADC_BUF 1000 +Uint16 ADC_table[24]; +Uint16 raw_table[24]; +Uint16 ConversionCount; + +int MAY=0; + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +void setup_adc() +{ + long CLKdiv,HSPCLKdiv,Rate; + + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + +// Specific clock setting for this example: +// EALLOW; +// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK +// EDIS; + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitAdc(); // For this example, init the ADC + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 +// EINT; // Enable Global interrupt INTM +// ERTM; // Enable Global realtime interrupt DBGM + +// Configure ADC + + if(Desk==dsk_COMM) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1 + + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0B; // + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0A; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x09; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x08; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x00; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x01; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x04; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x03; + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x05; + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x02; + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x06; + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x07; + + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0F; // - + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D; + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E; + AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0C; + + } + + if(Desk==dsk_SHKF) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000E; // Setup 2 conv's on SEQ1 + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x6; // 380 1 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x7; // 380 2 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // 220 1 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // 220 2 ? + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x5; // 31 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x4; // 31 UC + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0xF; // 24 + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0xD; // +24 + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0xB; // -24 + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x8; // 24 + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // 24 + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xA; // 24 + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x9; // 15 + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x1; // Ұ 1 + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0; // Ұ 2 + } + + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + +//AdcRegs.ADCTRL1.bit.ACQ_PS=15; +//AdcRegs.ADCTRL1.bit.CPS=1; + + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + + EPwm1Regs.TBCTL.bit.HSPCLKDIV=4; + EPwm1Regs.TBCTL.bit.CLKDIV=1; + + CLKdiv = 1<>4; + + if((sens_type[i]==POWER_380)||(sens_type[i]==POWER_220)) + { + if(Numb>200/*150*/) + { + if(prenumb[i]==0) zero_cownt[i]=0; + zero_cownt[i]+=2; + filtar[i] += ((float)Numb-filtar[i])/100.0; + Numb = filtar[i]; + prenumb[i]=1; + } + else + { + prenumb[i]=0; + if(zero_cownt[i]) + { + zero_cownt[i]--; + continue; + } + } + } + + raw_table[i] = Numb; Temper = Numb; + ADC_table[i] = filterbat(&filter[i],Temper); + + if(sens_type[i]==TERMO_AD) Temper_count(i); + else Power_count(i); + } + sig.all = chk.all; + chk.all = 0; + + if(/*Modbus[127].bit.bitE*/0) + { + Test_mem_limit(16); + for(i=0;i<8;i++) + { + Log_to_mem(raw_table[i]); + Log_to_mem(ADC_table[i]); + } } } +/* + if(Mode==adr_SHKF) + { + for(i=0;i<15;i++) + { + Temper= *((&AdcRegs.ADCRESULT0)+i) >>4; + adc_table_lem[i]=filterbat(&filter[i],Temper); + adc_table_tpl[i]=adc_table_lem[i]; + } + adc_table_lem[15] = ExtraCanal1; + adc_table_lem[16] = ExtraCanal2; + + measure_all(); + } +*/ + if(Desk==dsk_COMM) + { + for(i=0;i<24;i++) + if(sens_type[i]) + { + Temper = *((&AdcRegs.ADCRESULT0)+i) >>4; + + if(sens_type[i] != VOLTAGE) + Temper = filterbat(&filter[i],Temper); + + ADC_table[i]=(int)Temper; + + if(sens_type[i]==VOLTAGE) Current_count(i); + else Temper_count(i); + } + + sig.all = chk.all; + chk.all = 0; + } } + +// Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + return; +} diff --git a/ADC.h b/ADC.h new file mode 100644 index 0000000..7d2de8f --- /dev/null +++ b/ADC.h @@ -0,0 +1,6 @@ +extern int MAY; + +extern Uint16 ADC_table[]; + + +void setup_adc(void); diff --git a/F28335.cmd b/F28335.cmd new file mode 100644 index 0000000..fffa02b --- /dev/null +++ b/F28335.cmd @@ -0,0 +1,206 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */ +/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ +// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */ +/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > RAML0 PAGE = 0 + .pinit : > RAML0 PAGE = 0 + .text : > RAML0 PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = RAML4, + RUN = RAML4, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML5 PAGE = 1 + .esysmem : > RAML0 PAGE = 0 + + .logg : > ZONE7A PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > RAML4 PAGE = 0 + .switch : > RAML4 PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: * / + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 +/* DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 +*/ + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/GPIO_table.h b/GPIO_table.h new file mode 100644 index 0000000..c6cfa83 --- /dev/null +++ b/GPIO_table.h @@ -0,0 +1,194 @@ +#define COMM_gpio00_dir 0UL +#define COMM_gpio01_dir 0UL +#define COMM_gpio02_dir 0UL +#define COMM_gpio03_dir 0UL +#define COMM_gpio04_dir 0UL +#define COMM_gpio05_dir 0UL +#define COMM_gpio06_dir 0UL +#define COMM_gpio07_dir 0UL +#define COMM_gpio08_dir 0UL +#define COMM_gpio09_dir 0UL +#define COMM_gpio10_dir 0UL +#define COMM_gpio11_dir 0UL + +#define COMM_gpio19_dir 1UL // 63 SPI +#define COMM_gpio20_dir 0UL // 64 2:9B mode 2 +#define COMM_gpio21_dir 0UL // 65 2:9A mode 4 +#define COMM_gpio22_dir 0UL // 66 2:12C mode 1 +#define COMM_gpio23_dir 0UL // 67 2:12B control -24V +#define COMM_gpio24_dir 0UL +#define COMM_gpio25_dir 0UL +#define COMM_gpio26_dir 0UL // 72 2:11B control +24V +#define COMM_gpio27_dir 0UL + +#define COMM_gpio32_dir 1UL // 74 2:10B SDA +#define COMM_gpio33_dir 1UL // 75 2:10C SCL +#define COMM_gpio34_dir 1UL // 142 SCI + +#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red +#define COMM_gpio49_dir 1UL // 89 2:14B ts2 red +#define COMM_gpio50_dir 0UL +#define COMM_gpio51_dir 0UL // 91 2:13C mode !8 +#define COMM_gpio52_dir 1UL // 94 2:13B ts1 green +#define COMM_gpio53_dir 0UL + +#define COMM_gpio58_dir 1UL // 100 1:13C led term +#define COMM_gpio59_dir 1UL // 110 1:13B gotov +#define COMM_gpio60_dir 1UL // 111 1:13A led job +#define COMM_gpio61_dir 0UL +#define COMM_gpio62_dir 1UL // 113 1:14B alarm +#define COMM_gpio63_dir 1UL // 114 1:14A rez out + +//=========================================================================== + +#define VEPP_gpio00_dir 0UL // 5 2:7A input +#define VEPP_gpio01_dir 0UL // 6 2:4A input +#define VEPP_gpio02_dir 0UL // 7 2:7B input +#define VEPP_gpio03_dir 0UL // 10 2:4B input +#define VEPP_gpio04_dir 0UL // 11 2:7C input +#define VEPP_gpio05_dir 0UL // 12 2:4C input +#define VEPP_gpio06_dir 0UL // 13 2:6A input +#define VEPP_gpio07_dir 0UL // 16 2:3A input +#define VEPP_gpio08_dir 0UL // 17 2:6B input +#define VEPP_gpio09_dir 0UL // 18 2:3B input +#define VEPP_gpio10_dir 0UL // 19 2:6C input +#define VEPP_gpio11_dir 0UL // 20 2:3C input + +#define VEPP_gpio19_dir 1UL // 63 SPI +#define VEPP_gpio20_dir 0UL // 64 2:9B mode 2 +#define VEPP_gpio21_dir 0UL // 65 2:9A mode 4 +#define VEPP_gpio22_dir 0UL // 66 2:12C mode 1 +#define VEPP_gpio23_dir 0UL // 67 2:12B input +#define VEPP_gpio24_dir 0UL // 68 2:12A input +#define VEPP_gpio25_dir 0UL // 69 2:11C input +#define VEPP_gpio26_dir 0UL // 72 2:11B input +#define VEPP_gpio27_dir 0UL // 73 2:11A input + +#define VEPP_gpio32_dir 0UL // 74 2:10B input +#define VEPP_gpio33_dir 0UL // 75 2:10C input +#define VEPP_gpio34_dir 1UL // 142 SCI + +#define VEPP_gpio48_dir 1UL // 88 2:14C DIOD red +#define VEPP_gpio49_dir 0UL // 89 2:14B input +#define VEPP_gpio50_dir 0UL // 90 2:14A input +#define VEPP_gpio51_dir 0UL // 91 2:13C mode !8 +#define VEPP_gpio52_dir 0UL // 94 2:13B input +#define VEPP_gpio53_dir 0UL // 95 2:13A input + +#define VEPP_gpio58_dir 0UL // 100 1:13C input +#define VEPP_gpio59_dir 0UL +#define VEPP_gpio60_dir 1UL // 111 1:13A gotov +#define VEPP_gpio61_dir 0UL // 112 1:14C input +#define VEPP_gpio62_dir 1UL // 113 1:14C rezout +#define VEPP_gpio63_dir 1UL // 114 1:14A ledjob + +//=========================================================================== + +#define ISOL_gpio00_dir 0UL // 5 2:7A +#define ISOL_gpio01_dir 0UL // 6 2:4A +#define ISOL_gpio02_dir 0UL // 7 2:7B +#define ISOL_gpio03_dir 0UL // 10 2:4B +#define ISOL_gpio04_dir 0UL // 11 2:7C +#define ISOL_gpio05_dir 0UL // 12 2:4C +#define ISOL_gpio06_dir 0UL // 13 2:6A +#define ISOL_gpio07_dir 0UL // 16 2:3A +#define ISOL_gpio08_dir 0UL // 17 2:6B +#define ISOL_gpio09_dir 0UL // 18 2:3B +#define ISOL_gpio10_dir 0UL // 19 2:6C +#define ISOL_gpio11_dir 0UL // 20 2:3C + +#define ISOL_gpio19_dir 1UL // 63 SPI +#define ISOL_gpio20_dir 0UL // 64 2:9B mode 2 +#define ISOL_gpio21_dir 0UL // 65 2:9A mode 4 +#define ISOL_gpio22_dir 0UL // 66 2:12C mode 1 +#define ISOL_gpio23_dir 0UL // 67 2:12B opt input 1 +#define ISOL_gpio24_dir 1UL // 68 2:12A led 2 +#define ISOL_gpio25_dir 0UL // 69 2:11C +#define ISOL_gpio26_dir 1UL // 72 2:11B opt out 2 +#define ISOL_gpio27_dir 1UL // 73 2:11A led 1 + +#define ISOL_gpio32_dir 1UL // 74 2:10B opt out 1 +#define ISOL_gpio33_dir 0UL // 75 2:10C +#define ISOL_gpio34_dir 1UL // 142 SCI + +#define ISOL_gpio48_dir 1UL // 88 2:14C DIOD red +#define ISOL_gpio49_dir 0UL // 89 2:14B +#define ISOL_gpio50_dir 0UL // 90 2:14A +#define ISOL_gpio51_dir 0UL // 91 2:13C mode !8 +#define ISOL_gpio52_dir 0UL // 94 2:13B opt input 2 +#define ISOL_gpio53_dir 1UL // 95 2:13A led 3 + +#define ISOL_gpio58_dir 0UL // 100 1:13C +#define ISOL_gpio59_dir 1UL // 110 1:13B gotov +#define ISOL_gpio60_dir 0UL // 111 1:13A +#define ISOL_gpio61_dir 0UL // 112 1:14C +#define ISOL_gpio62_dir 0UL // 113 1:14C input +#define ISOL_gpio63_dir 0UL // 114 1:14A + +//=========================================================================== + +//=========================================================================== + +#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \ + (COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \ + (COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \ + (COMM_gpio19_dir<<19)+ \ + (COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \ + (COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27); +#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \ + (COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \ + (COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \ + (COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \ + (COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31); + +#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \ + (BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \ + (BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \ + (BKSD_gpio19_dir<<19)+ \ + (BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \ + (BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27); +#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \ + (BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \ + (BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \ + (BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \ + (BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31); + +#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \ + (PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \ + (PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \ + (PULT_gpio19_dir<<19)+ \ + (PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \ + (PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27); +#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \ + (PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \ + (PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \ + (PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \ + (PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31); + +#define VEPP_GPADIR (VEPP_gpio00_dir ) + (VEPP_gpio01_dir<<1) + (VEPP_gpio02_dir<<2) + (VEPP_gpio03_dir<<3) + \ + (VEPP_gpio04_dir<<4) + (VEPP_gpio05_dir<<5) + (VEPP_gpio06_dir<<6) + (VEPP_gpio07_dir<<7) + \ + (VEPP_gpio08_dir<<8) + (VEPP_gpio09_dir<<9) + (VEPP_gpio10_dir<<10)+ (VEPP_gpio11_dir<<11)+ \ + (VEPP_gpio19_dir<<19)+ \ + (VEPP_gpio20_dir<<20)+ (VEPP_gpio21_dir<<21)+ (VEPP_gpio22_dir<<22)+ (VEPP_gpio23_dir<<23)+ \ + (VEPP_gpio24_dir<<24)+ (VEPP_gpio25_dir<<25)+ (VEPP_gpio26_dir<<26)+ (VEPP_gpio27_dir<<27); +#define VEPP_GPBDIR (VEPP_gpio32_dir )+ (VEPP_gpio33_dir<<1) + (VEPP_gpio34_dir<<2 )+ \ + (VEPP_gpio48_dir<<16)+ (VEPP_gpio49_dir<<17)+ (VEPP_gpio50_dir<<18)+ (VEPP_gpio51_dir<<19)+ \ + (VEPP_gpio52_dir<<20)+ (VEPP_gpio53_dir<<21)+ \ + (VEPP_gpio58_dir<<26)+ (VEPP_gpio59_dir<<27)+ \ + (VEPP_gpio60_dir<<28)+ (VEPP_gpio61_dir<<29)+ (VEPP_gpio62_dir<<30)+ (VEPP_gpio63_dir<<31); + +#define ISOL_GPADIR (ISOL_gpio00_dir ) + (ISOL_gpio01_dir<<1) + (ISOL_gpio02_dir<<2) + (ISOL_gpio03_dir<<3) + \ + (ISOL_gpio04_dir<<4) + (ISOL_gpio05_dir<<5) + (ISOL_gpio06_dir<<6) + (ISOL_gpio07_dir<<7) + \ + (ISOL_gpio08_dir<<8) + (ISOL_gpio09_dir<<9) + (ISOL_gpio10_dir<<10)+ (ISOL_gpio11_dir<<11)+ \ + (ISOL_gpio19_dir<<19)+ \ + (ISOL_gpio20_dir<<20)+ (ISOL_gpio21_dir<<21)+ (ISOL_gpio22_dir<<22)+ (ISOL_gpio23_dir<<23)+ \ + (ISOL_gpio24_dir<<24)+ (ISOL_gpio25_dir<<25)+ (ISOL_gpio26_dir<<26)+ (ISOL_gpio27_dir<<27); +#define ISOL_GPBDIR (ISOL_gpio32_dir )+ (ISOL_gpio33_dir<<1) + (ISOL_gpio34_dir<<2 )+ \ + (ISOL_gpio48_dir<<16)+ (ISOL_gpio49_dir<<17)+ (ISOL_gpio50_dir<<18)+ (ISOL_gpio51_dir<<19)+ \ + (ISOL_gpio52_dir<<20)+ (ISOL_gpio53_dir<<21)+ \ + (ISOL_gpio58_dir<<26)+ (ISOL_gpio59_dir<<27)+ \ + (ISOL_gpio60_dir<<28)+ (ISOL_gpio61_dir<<29)+ (ISOL_gpio62_dir<<30)+ (ISOL_gpio63_dir<<31); + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/RS485.c b/RS485.c new file mode 100644 index 0000000..4e57f4a --- /dev/null +++ b/RS485.c @@ -0,0 +1,553 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/**************************************************************** + RS485. + **************************************************************** + * UART * + ****************************************************************/ + +//#include "big_dsp_module.h" + + +#include "DSP2833x_Device.h" +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "bios_dsp.h" +#include "cntrl_adr.h" + +#include "tools.h" + +//#include "flash_tools.h" + + +RS_DATA rs_a,rs_b; + +unsigned int RS_Len[70]={0}; + +static char size_cmd15=1; + +void RS_RX_Handler(RS_DATA *rs_arr); +void RS_TX_Handler(RS_DATA *rs_arr); + +/** UART - */ +interrupt void RSA_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_RX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_RX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSA_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_TX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_TX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +/** UART - */ +void RS_RX_Handler(RS_DATA *rs_arr) +{ + char Rc; + char RS_BytePtr; + +// led1_on(); + + for(;;) // 'goto' + { + if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag + { + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + return; // + } + + Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // + + if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag + { + rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI + rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + + continue; + } + + if(rs_arr->RS_DataReady) continue; // + + if (rs_arr->RS_Flag9bit==1) // RS485???????? + { + // + rs_arr->RS_FlagBegin = true; // + rs_arr->RS_RecvLen = 0; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_HeaderCnt = 0; + rs_arr->RS_Cmd = 0; + } + + if(rs_arr->RS_FlagSkiping) continue; // + + if (rs_arr->RS_FlagBegin) // + { + if (rs_arr->RS_HeaderCnt==0) // + { + if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING) + || ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING)) + + { + rs_arr->addr_recive=Rc; // + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // + RS_SetBitMode(rs_arr,8); // 8- + } + else + { + rs_arr->RS_FlagSkiping = true; // + rs_arr->RS_FlagBegin = false; // 9- +// led1_off(); + } + } + else + { + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // .. + + if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING) + { + RS_Len[CMD_MODBUS_16] = (10+Rc); + } + + // - + if (rs_arr->RS_HeaderCnt == 2) + { + rs_arr->RS_Cmd = Rc; + // + // CMD_LOAD - + // CMD_STD_ANS - + if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3) + || ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD)) + ) + { + RS_SetBitMode(rs_arr,9); // 9- RS485? + rs_arr->RS_HeaderCnt = 0; // + rs_arr->RS_FlagBegin = true; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_Cmd=0; +// led1_off(); + continue; + } + if (rs_arr->RS_Cmd == CMD_LOAD) // + rs_arr->RS_FlagBegin = false;// + } + + if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) || + (rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header))) + { // + RS_SetBitMode(rs_arr,9); // 9- RS485? + rs_arr->RS_FlagBegin = false; + rs_arr->RS_FlagSkiping = true; + rs_arr->RS_DataReady = true; + rs_arr->RS_Cmd=0; +// led1_off(); + } } } + else // + { + if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End) + { + rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // , + rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // , + } + if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // - + + if(rs_arr->RS_DataReady) // , + { // + rs_arr->RS_FlagSkiping = true; // +// led1_off(); + continue; + } + RS_BytePtr = rs_arr->RS_RecvLen++ % 2; + if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // + else *rs_arr->pRS_RecvPtr = Rc<<8; + + if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // + { + rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD; + RS_SetBitMode(rs_arr,9); // 9- RS485? + rs_arr->RS_FlagSkiping = true; // + rs_arr->RS_DataReady = true; // - +// led1_off(); +} } } } + +/** UART - */ +void RS_TX_Handler(RS_DATA *rs_arr) +{ + char RS_BytePtr; +// unsigned int i; + + if(rs_arr->RS_SendBlockMode == BM_CHAR32) + { + if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* */ + } + SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++)); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* PC */ + + RS_SetBitMode(rs_arr,9); /* 9- RS485?*/ + RS_Line_to_receive(rs_arr); /* RS485 */ + + rs_arr->flag_TIMEOUT_to_Send=false; /* */ + } + } + else /* BM_PACKED */ + { + + RS_BytePtr = (rs_arr->RS_SendLen++) % 2; + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* */ + } + if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) )); + else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr )); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* PC */ +// RS_SetBitMode(rs_arr,9); /* 9- RS485?*/ +// RS_Line_to_receive(); /* RS485 */ + + } + } + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; +// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag +} + +/** */ +void setup_arr_cmd_length() +{ + int i; + + for (i=0;i<70;i++) RS_Len[i]=i; + + RS_Len[CMD_LOAD] = 12; + RS_Len[CMD_UPLOAD] = 12; + RS_Len[CMD_RUN] = 8; + RS_Len[CMD_XFLASH] = 9; + RS_Len[CMD_TFLASH] = 16; + RS_Len[CMD_PEEK] = 8; + RS_Len[CMD_POKE] = 12; + RS_Len[CMD_INITLOAD] = 12; + RS_Len[CMD_INIT] = 5; + RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2; + RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1; + RS_Len[CMD_IMPULSE] = 8; + RS_Len[CMD_MODBUS_3] = 8; + RS_Len[CMD_MODBUS_6] = 8; + RS_Len[CMD_MODBUS_16] = 13; + RS_Len[CMD_MODBUS_15] = 27; + RS_Len[CMD_EXTEND] = 18; +} + +/** / */ +void RS_SetBitMode(RS_DATA *rs_arr,int n) +{ + if(n == 8) + { + RS_SetLineMode(rs_arr,8,'N',1); /* */ + rs_arr->RS_Flag9bit=0; + } + if(n == 9) + { + RS_SetLineMode(rs_arr,8,'N',1); /* */ + rs_arr->RS_Flag9bit=1; +} } + +/** . + 32- 0. + @precondition - RS_TRANSMIT_INTR + @param buf + @param len + @see RS_BSend, RS_TRANSMIT_INTR */ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len) +{ + unsigned int i; + for (i=0; i <= 30000; i++){} /* PC */ + + RS_Line_to_send(rs_arr); /* RS485 */ + + for (i=0; i <= 10000; i++){} /* PC */ + + rs_arr->RS_SLength = len; /* */ + rs_arr->pRS_SendPtr = pBuf + 1; + + rs_arr->RS_SendBlockMode = BM_CHAR32; + + RS_Wait4OK(rs_arr); /* */ + RS_SetBitMode(rs_arr,8); /* 8- */ + + rs_arr->RS_SendLen = 1; /* */ + if(len > 1) + { + enableUARTIntW(rs_arr); /* */ + SCI_send(rs_arr, *pBuf); // + } + else + { + SCI_send(rs_arr, *pBuf); // + RS_Wait4OK(rs_arr); /* */ + for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* PC */ + RS_SetBitMode(rs_arr,9); /* 9- */ + RS_Line_to_receive(rs_arr); /* RS485 */ + } + return 0; +} + +// +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len) +{ + + RS_Line_to_send(rs_arr); // RS485 + + rs_arr->RS_SLength = len; // + rs_arr->pRS_SendPtr = pBuf; + rs_arr->RS_SendBlockMode = BM_PACKED; + + RS_Wait4OK(rs_arr); // + RS_SetBitMode(rs_arr,8); /* 8- */ + + rs_arr->RS_SendLen = 1; // + + enableUARTIntW(rs_arr); /* */ + + SCI_send(rs_arr,HIBYTE(*pBuf));// + + return 0; +} + +/** . + @param speed RS */ +/** . + @param speed RS */ +void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed) +{ + long SciBaud; + + SciBaud = LSPCLK/(speed*8.0); + +// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++; + + rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud); + rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud); +} + + +/** */ +void create_uart_vars(char size_cmd15_set) +{ + size_cmd15=size_cmd15_set; + rs_a.commnumber=COM_1; + rs_b.commnumber=COM_2; +} + + + +/** */ + +void setup_uart(char commnumber, unsigned long speed_baud) +{ + volatile struct SCI_REGS *SciRegs; + RS_DATA *rs_arr; + + if(commnumber==COM_1) + { + rs_a.SciRegs = &SciaRegs; + rs_arr = &rs_a; + + EALLOW; + + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O) + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I) + + PieVectTable.SCIRXINTA = &RSA_RX_Handler; + PieVectTable.SCITXINTA = &RSA_TX_Handler; + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + if(commnumber==COM_2) + { + rs_b.SciRegs = &ScibRegs; + rs_arr = &rs_b; + + EALLOW; + + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O) + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I) + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default) + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output + + PieVectTable.SCIRXINTB = &RSB_RX_Handler; + PieVectTable.SCITXINTB = &RSB_TX_Handler; + + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + rs_arr->commnumber = commnumber; + SciRegs = rs_arr->SciRegs; + RS_SetLineMode(rs_arr,8,'N',1); + +// enable TX, RX, internal SCICLK, +// Disable RX ERR, SLEEP, TXWAKE + + SciRegs->SCIFFCT.bit.ABDCLR=1; + SciRegs->SCIFFCT.bit.CDC=0; + + SciRegs->SCICTL1.bit.RXERRINTENA=0; + SciRegs->SCICTL1.bit.SWRESET=0; + SciRegs->SCICTL1.bit.TXWAKE=0; + SciRegs->SCICTL1.bit.SLEEP=0; + SciRegs->SCICTL1.bit.TXENA=1; + SciRegs->SCICTL1.bit.RXENA=1; + + SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off + SciRegs->SCIFFRX.bit.RXFFIL=1; // + + setup_arr_cmd_length(); + RS_SetLineSpeed(rs_arr,speed_baud); // + RS_Line_to_receive(rs_arr); // RS485 + enableUARTInt(rs_arr); // UART + RS_SetBitMode(rs_arr,9); + rs_arr->RS_PrevCmd = 0; // + rs_arr->flag_TIMEOUT_to_Send = 0; + rs_arr->flag_LEADING = 0; + + SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset +} + +/** . + @param bit + @param parity (N,O,E,M,S) + @param stop */ +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop) +{ + volatile struct SCI_REGS *SciRegs; +/* +SCICCR - SCI Communication Control Register +Bit Bit Name Designation Functions +2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits). +3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications. +4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin. +5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0. +6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. +7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1. +*/ + + SciRegs = rs_arr->SciRegs; + + if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1; + + switch(parity) + { + case 'N': SciRegs->SCICCR.bit.PARITYENA = 0; + break; + case 'O': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 0; + break; + case 'E': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 1; + break; + } + + if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0; + if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1; + + SciRegs->SCICCR.bit.LOOPBKENA = 0; //0 + SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0; +} + +void clear_timer_rs_live(RS_DATA *rs_arr) +{ + rs_arr->time_wait_rs_out=0; +} + +/* RS */ +void test_rs_live(RS_DATA *rs_arr) +{ +/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT) + rs_arr->time_wait_rs_out++; + else + { + rs_arr->time_wait_rs_out=0; + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); +}*/ } diff --git a/RS485.h b/RS485.h new file mode 100644 index 0000000..3e4ca38 --- /dev/null +++ b/RS485.h @@ -0,0 +1,138 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/**************************************************************** + RS485.h + **************************************************************** + * UART * + ****************************************************************/ +#ifndef _RS485 +#define _RS485 + +#ifdef __cplusplus + extern "C" { +#endif + +//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +//#include "DSP2833x_Sci.h" +//#include "cntrl_adr.h" +//#include "params.h" + +#define COM_1 1 +#define COM_2 2 + +#define MAX_RECEIVE_LENGTH 400 // 80 //150 +#define MAX_SEND_LENGTH 400 //150 + +#define TIME_WAIT_RS_BYTE_OUT 1000 +#define TIME_WAIT_RS_LOST_BYTE 100 +#define RS_TIME_OUT (SECOND*10) + +#define Rec_Bloc_Begin 0x200000 +#define Rec_Bloc_End 0x2F0000 +#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin) + +/* Message RS declaration */ +typedef struct +{ + volatile struct SCI_REGS *SciRegs; + + unsigned int commnumber; // + unsigned long RS_Length; // + + unsigned int *pRS_RecvPtr; // + unsigned int *pRS_SendPtr; // + unsigned int *pRecvPtr; + + unsigned int RS_PrevCmd; // + unsigned int RS_Cmd; // + unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // + unsigned int flag_TIMEOUT_to_Send; // + unsigned int flag_TIMEOUT_to_Receive; // + unsigned int RS_DataReady; // RS + unsigned int buffer[MAX_SEND_LENGTH]; // RS + + unsigned int addr_answer; // + unsigned int addr_recive; // + unsigned int flag_LEADING; // ( ) + unsigned long RS_RecvLen; + unsigned long RS_SLength; // + unsigned long RS_SendLen; // + char RS_SendBlockMode; // + char RS_Flag9bit; // RS485???????? + int BS_LoadOK; // + int RS_FlagBegin; + int RS_HeaderCnt; + int RS_FlagSkiping; + unsigned long curr_baud; + unsigned long time_wait_rs_out; + +} RS_DATA; + +extern RS_DATA rs_a,rs_b; + +extern unsigned int + RS_Len[70]; /* () + 1 */ + +interrupt void RSA_RX_Handler(void); +interrupt void RSA_TX_Handler(void); +interrupt void RSB_RX_Handler(void); +interrupt void RSB_TX_Handler(void); + +/* rs_a,rs_b*/ +void create_uart_vars(char size_cmd15); + +/** , */ +/** / */ +void RS_SetBitMode(RS_DATA *rs_arr, int n); + +/** . + 32- 0. + @precondition - RS_TRANSMIT_INTR + @param buf + @param len + @see RS_BSend, RS_TRANSMIT_INTR +*/ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** . + @precondition - RS_TRANSMIT_INTR + @param buf + @param len 8- + @see RS_Send, RS_TRANSMIT_INTR + */ +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** */ +void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - */ + +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop); +void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed); + +// Transmit a character from the SCI' +#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y) + +// UART +// wait for TRDY =1 for empty state +#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY)) + +/** */ +#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1; + +/** */ +#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0; + +/** UART */ +#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2 +#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1 + +void clear_timer_rs_live(RS_DATA *rs_arr); +void test_rs_live(RS_DATA *rs_arr); + +#ifdef __cplusplus + } +#endif + +#endif /* _RS485 */ + diff --git a/bin/HEX2BIN.EXE b/bin/HEX2BIN.EXE new file mode 100644 index 0000000..0a3799a Binary files /dev/null and b/bin/HEX2BIN.EXE differ diff --git a/bin/create_rs.bat b/bin/create_rs.bat new file mode 100644 index 0000000..98959b3 --- /dev/null +++ b/bin/create_rs.bat @@ -0,0 +1,5 @@ +set iname=BalzamUMPLeonardTMS320F28335 +set oname=BalzamUMPLeonardTMS320F28335 + +hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +hex2bin %oname%.hex %oname%.bin diff --git a/bin/hex2000.exe b/bin/hex2000.exe new file mode 100644 index 0000000..7072690 Binary files /dev/null and b/bin/hex2000.exe differ diff --git a/bin/ice.bin b/bin/ice.bin new file mode 100644 index 0000000..2ae21aa Binary files /dev/null and b/bin/ice.bin differ diff --git a/bin/ice.hex b/bin/ice.hex new file mode 100644 index 0000000..e8ce077 --- /dev/null +++ b/bin/ice.hex @@ -0,0 +1,981 @@ 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+:2079B00000002B9100002C9000004D9000006E9000008F900000B09000002B910000D390E6 +:0C79D0000000F490000033000B000A00DF +:2079DC002800000004C1E89F000007A0000019A000002EA0000044A0000055A0000069A007 +:2079FC0000007AA0000095A00000B7A00000CDA00000DEA00000EBA000000CA100001EA1E3 +:187A1C0000002EA1000041A1000050A1000060A1000076A10000000098 +:00000001FF diff --git a/bin/ice.map b/bin/ice.map new file mode 100644 index 0000000..cd0ba3f --- /dev/null +++ b/bin/ice.map @@ -0,0 +1,33 @@ +******************************************************************************** +TMS320C2000 Hex Converter v5.2.1 +******************************************************************************** + +INPUT FILE NAME: +OUTPUT FORMAT: Binary + +PHYSICAL MEMORY PARAMETERS + Default data width : 16 + Default memory width : 8 (LS-->MS) + Default output width : 8 + +BOOT LOADER PARAMETERS + Table Type: SERIAL PORT (SCI 8 bit Mode) + Entry Point: 0x0000b82b + + +OUTPUT TRANSLATION MAP +-------------------------------------------------------------------------------- +00000000..003fffff Page=0 Memory Width=8 ROM Width=8 +-------------------------------------------------------------------------------- + OUTPUT FILES: D:\Projects\Ledokol\Docs\UKSS\ICE_19_03_2018\bin\ice.bin [b0..b7] + + CONTENTS: 00000000..00007a33 BOOT TABLE + .cinit : dest=0000b9e2 size=000001f5 width=00000002 + .text : dest=00008000 size=000039e2 width=00000002 + .econst : dest=0000c000 size=00000103 width=00000002 + .switch : dest=0000c104 size=00000028 width=00000002 + +-------------------------------------------------------------------------------- +00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*" +-------------------------------------------------------------------------------- + NO CONTENTS diff --git a/bin/ice.out b/bin/ice.out new file mode 100644 index 0000000..b378f47 Binary files /dev/null and b/bin/ice.out differ diff --git a/bios.c b/bios.c new file mode 100644 index 0000000..42ffb72 --- /dev/null +++ b/bios.c @@ -0,0 +1,450 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/**************************************************************** + Bios.c + ************************************************************** + BIOS * + RS232 +****************************************************************/ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "RS485.h" +#include "bios_dsp.h" +#include "crc16.h" +#include "spise2p.h" +#include "i2c.h" + +//#include "flash_tools.h" +//#include "spartan_tools.h" +//#include "big_dsp_module.h" + +int flag_DEBUG = false; /* */ + + +//static unsigned int *RecvPtr; +//static int BS_LoadOK = false; /** */ + +/**********************************************************/ +/* , */ +/**********************************************************/ +//static int _getbyte(int *addr, int offs); + +unsigned int read_memory(unsigned long addr) +{ + return (*(volatile int *)(addr)); +} + +void write_memory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)( addr )) = data; +} + + +/** , -1 */ +int get_command(RS_DATA *rs_arr) +{ + int cmd; + unsigned int crc, rcrc; + + if(rs_arr->RS_DataReady) // RS + { + rs_arr->RS_DataReady = false; + cmd = rs_arr->RS_Header[1]; // + + // CRC + if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH)) + { + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); + return -1; + } + + if(cmd == CMD_LOAD) // + { + rs_arr->RS_PrevCmd = cmd; + return cmd; // crc + } + else // + { + // crc + crc = (rs_arr->RS_Header[RS_Len[cmd]-1] << 8) | + (rs_arr->RS_Header[RS_Len[cmd]-2]) ; + } + // crc + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, (RS_Len[cmd]-2) ); + + if(crc == rcrc) // crc + { + rs_arr->RS_PrevCmd = cmd; + return cmd; + } + else + { + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); + } } + + return -1; +} + +/** , */ +void Answer(RS_DATA *rs_arr,int n) +{ + int crc; + + flag_DEBUG = true; // + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = n; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + + rs_arr->buffer[2] = LOBYTE(crc); + rs_arr->buffer[3] = HIBYTE(crc); + + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 0; + RS_Send(rs_arr,rs_arr->buffer, 6); +} + +/* - */ +static char _getbyte(unsigned int *addr, int32 offs) +{ + unsigned int *address; + unsigned int byte; + + address = addr + offs/2; + byte = *address; + if(offs%2) return LOBYTE(byte); + else return HIBYTE(byte); +} + + +/* ( )*/ +void init(RS_DATA *rs_arr) +{ +/* + if(rs_arr->RS_Header[2]==3) + { + if (rs_arr->curr_baud!=57600) + { RS_SetLineSpeed(rs_arr,57600); + rs_arr->curr_baud= 57600; + } } + + if(rs_arr->RS_Header[2]==4) + { + if (rs_arr->curr_baud!=115200) + { RS_SetLineSpeed(rs_arr,115200); + rs_arr->curr_baud= 115200; + } } + + Answer(rs_arr,CMD_INIT); + rs_arr->BS_LoadOK = false; +*/ +} + +/**@name +* , +*/ +//@{ + +/** . + */ +void initload(RS_DATA *rs_arr) +{ + unsigned long Address; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + rs_arr->RS_Length = rs_arr->RS_Header[9] & 0xFF; + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->RS_Length += 2; + rs_arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + rs_arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + + Answer(rs_arr,CMD_INITLOAD); +} + +/** . + RS */ +void load(RS_DATA *rs_arr) +{ + unsigned int rcrc, crc; + + crc = (_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-1) << 8) + + _getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + rs_arr->RS_Header[0] = rs_arr->addr_recive; + +// CNTRL_ADDR; + rs_arr->RS_Header[1]=CMD_LOAD; + + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, 2); + rcrc = get_crc_16b( rcrc, rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + if(rcrc == crc) + { + Answer(rs_arr,CMD_LOAD); + rs_arr->BS_LoadOK = true; + } + else + { + rs_arr->BS_LoadOK = false; + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); +} } + +/** Serial Boot. + @precondition + + RecvPtr, - load + @see load */ +void run (RS_DATA *rs_arr) +{ + return; +} + +/** */ +void peek(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data, crc; + + flag_DEBUG = true; // + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + + if(Address>=0x20000000) + { + Address&=0xFFFFFFF; + Data = I2CA_ReadData(Address); + } + else + if(Address>=0x10000000) + { + Address&=0xFFFFFFF; + Seeprom_read(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFFF; + Data = read_memory(Address); + } + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_PEEK; + + rs_arr->buffer[2] = LOBYTE(Data); + rs_arr->buffer[3] = HIBYTE(Data); + + rs_arr->buffer[4] = 0;//LOBYTE(CpuTimer2.InterruptCount); + rs_arr->buffer[5] = 0;//HIBYTE(CpuTimer2.InterruptCount); + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + RS_Send(rs_arr,rs_arr->buffer, 10); + +} + +/** */ +void poke(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = (Data<<8) | (rs_arr->RS_Header[7] & 0xFF); + Data = (Data<<8) | (rs_arr->RS_Header[6] & 0xFF); + + if(Address>=0x2000000) + { + Address&=0xFFFFFF; + I2CA_WriteData(Address,Data); + } + else + if(Address>=0x1000000) + { + Address&=0xFFFFFF; + Seeprom_write(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFF; + write_memory(Address,Data); + } + + Answer(rs_arr,CMD_POKE); +} + +/** */ +void upload(RS_DATA *rs_arr) +{ + int32 Address, Length, crc; + + flag_DEBUG = true; // +// stopp=1; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Length = rs_arr->RS_Header[9] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_UPLOAD; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + crc = get_crc_16b( crc, (unsigned int *)Address, Length); + + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 + + rs_arr->buffer[0] = CMD_UPLOAD; + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 + + RS_Wait4OK(rs_arr); + RS_BSend(rs_arr,(unsigned int*)Address, Length); + RS_Wait4OK(rs_arr); + + rs_arr->buffer[0] = LOBYTE(crc); + rs_arr->buffer[1] = HIBYTE(crc); + rs_arr->buffer[2] = 0; + rs_arr->buffer[3] = 0; + RS_Send(rs_arr,rs_arr->buffer, 4+2); + +} + +/** XILINX. + @precondition + + RecvPtr Length, - load, + + @see load */ +void xflash(RS_DATA *rs_arr) +{ + return; +} + +/** TMS. + @precondition + + RecvPtr Length, - load + @see load */ +void tflash(RS_DATA *rs_arr) +{ +// volatile unsigned long Address1,Address2; +// volatile unsigned long Length, LengthW; +/* + if(!rs_arr->BS_LoadOK) + { + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + RS_Line_to_receive(rs_arr); // RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + run_flash_data(Address1,Address2, LengthW ); + + Answer(rs_arr,CMD_TFLASH); +*/ + return; +} + +/** TMS. + @precondition + + RecvPtr Length, - load + @see load */ +void extendbios(RS_DATA *rs_arr) +{ + volatile unsigned long Address1,Address2,Length; + unsigned int code; + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + code=rs_arr->RS_Header[14] & 0xFF; + + switch ( code ) + { + // EPROM RAM + case 4: Seeprom_write(Address1,(unsigned int*)Address2,Length); + break; + // EPROM RAM + case 5: Seeprom_read(Address1,(unsigned int*)Address2,Length); + break; + + default: + return; + } + + Answer(rs_arr,CMD_EXTEND); + return; +} + +//@} diff --git a/bios_dsp.h b/bios_dsp.h new file mode 100644 index 0000000..9ed9601 --- /dev/null +++ b/bios_dsp.h @@ -0,0 +1,120 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/****************************************************************/ +/* Bios_dsp.h */ +/****************************************************************/ + /* BIOS */ +/****************************************************************/ +#ifndef _BIOS_DSP +#define _BIOS_DSP + +#ifdef __cplusplus + extern "C" { +#endif + +#define BM_PACKED 1 +#define BM_CHAR32 0 + +#define CHIEF 1 +#define SLAVE 0 + +#define ADR_FOR_SPECIAL 0x100 +#define CMD_MODBUS_3 3 +#define ANS_MODBUS_3 4 +#define CMD_MODBUS_15 5 +#define CMD_MODBUS_6 6 +#define ANS_MODBUS_6 7 +#define CMD_MODBUS_16 16 +/* + +CMD_MODBUS_3 = 3, + ANS_MODBUS_3 = 4, + CMD_MODBUS_15 = 5, + CMD_MODBUS_6 = 6, + ANS_MODBUS_6 = 7, + CMD_MODBUS_16 = 16, + */ +enum { + CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH, + CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND, + + CMD_VECTOR=61, + CMD_IMPULSE, + /* */ + CMD_STD=65, CMD_STD_ANS + }; + +enum {false=0, true}; + + +/** , -1 */ +int get_command(RS_DATA *rs_arr); + +/** , */ +void Answer(RS_DATA *rs_arr,int n); + +/* ( )*/ +void init(RS_DATA *rs_arr); + +/**@name +* , */ +//@{ + +/** . + */ +void initload(RS_DATA *rs_arr); + +/** . + RS */ +void load(RS_DATA *rs_arr); + +/** Serial Boot. + @precondition + + RecvPtr, - load + @see load */ +void run (RS_DATA *rs_arr); + +/** */ +void peek(RS_DATA *rs_arr); + +/** */ +void poke(RS_DATA *rs_arr); + +/** */ +void upload(RS_DATA *rs_arr); + +/** XILINX. + @precondition + + RecvPtr Length, - load, + + @see load */ +void xflash(RS_DATA *rs_arr); + +/** TMS. + @precondition + + RecvPtr Length, - load + @see load */ +void tflash(RS_DATA *rs_arr); + + +/* */ +void extendbios(RS_DATA *rs_arr); + + +void write_memory(unsigned long addr, unsigned int data); +unsigned int read_memory(unsigned long addr); + + +//@} + + +#ifdef __cplusplus + } +#endif + +#endif/* _BIOS_DSP */ diff --git a/cc_build_Debug.log b/cc_build_Debug.log new file mode 100644 index 0000000..152a2fb --- /dev/null +++ b/cc_build_Debug.log @@ -0,0 +1,3 @@ +------------------------------ ice.pjt - Debug ------------------------------ +Build Complete, + 0 Errors, 0 Warnings, 0 Remarks. diff --git a/cntrl_adr.c b/cntrl_adr.c new file mode 100644 index 0000000..2f29cdb --- /dev/null +++ b/cntrl_adr.c @@ -0,0 +1,43 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/**************************************************************** + cntrl_adr.c + **************************************************************** + * * + ****************************************************************/ + +#include "cntrl_adr.h" + +#define ADDR_FOR_ALL_DEF 10 +#define ADDR_ANSWER_DEF 0x33 +#define ADDR_TERMINAL_DEF 11 +#define ADDR_UNIVERSAL_DEF 10 + + +/** */ +int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF; + +/** */ +const int ADDR_ANSWER = ADDR_ANSWER_DEF; + +/** */ +const int ADDR_TERMINAL = ADDR_TERMINAL_DEF; + +/* */ +const int CNTRL_ADDR_UNIVERSAL=ADDR_UNIVERSAL_DEF; + +/* */ +int CNTRL_ADDR=1; + +int cntr_addr_c; +int cntr_addr_c_all; + +/** */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all) +{ + CNTRL_ADDR = cntrl_addr; + ADDR_FOR_ALL = cntrl_addr_for_all; +} + diff --git a/cntrl_adr.h b/cntrl_adr.h new file mode 100644 index 0000000..100021f --- /dev/null +++ b/cntrl_adr.h @@ -0,0 +1,44 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2000 . */ +/**************************************************************** + cntrl_adr.h + **************************************************************** + * * + ****************************************************************/ + +#ifndef _CNTRL_ADR +#define _CNTRL_ADR + +#ifdef __cplusplus + extern "C" { +#endif + +/** */ +extern int ADDR_FOR_ALL; + +/** */ +extern const int ADDR_ANSWER; + +/** */ +extern const int ADDR_TERMINAL; + +/* */ +extern int CNTRL_ADDR; + +/* */ +extern const int CNTRL_ADDR_UNIVERSAL; + +/** */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all); + + +extern int cntr_addr_c; +extern int cntr_addr_c_all; + +#ifdef __cplusplus + } +#endif + +#endif /* _CNTRL_ADR */ diff --git a/crc16.c b/crc16.c new file mode 100644 index 0000000..a69f55f --- /dev/null +++ b/crc16.c @@ -0,0 +1,221 @@ +#include "crc16.h" +#define MAKE_TABS 0 /* Builds tables below */ +#define FAST_CRC 1 /* If fast CRC should be used */ +#define ONLY_CRC16 1 + +#define Poln 0xA001 + + +#if FAST_CRC & !MAKE_TABS + +#if !ONLY_CRC16 + +static WORD crc_ccitt_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; +#endif + +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; +#endif + + +#if !ONLY_CRC16 + +/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */ +/* are sent MSB to LSB. */ +unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register int i; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ]; +#else + crc ^= (WORD)(*buf++) << 8; + for (i = 0; i < 8; i++) { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } +#endif + } return crc; +} +#endif + + +/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */ +/* sent LSB to MSB. */ +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register unsigned int i; + register unsigned int ch; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; +#else + ch = *buf++; + for (i = 0; i < 8; i++) { + if ((crc ^ ch) & 1) + crc = (crc >> 1) ^ 0xa001; + else + crc >>= 1; + ch >>= 1; + } +#endif + } return (crc & 0xffff); +} + + + +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + +int get_crc16(unsigned int *buf, int size ) +{ + unsigned int crc16,i,j; + + + crc16=0xFFFF; + for(i=0;i>1)^Poln; + else crc16=crc16>>1; + + crc16=crc16^((buf[i]>>8)&0xFF); + for (j=0;j<8;j++) + if(crc16&1) crc16=(crc16>>1)^Poln; + else crc16=crc16>>1; + } + return crc16; +} + +unsigned int get_crc32(unsigned long *num) +{ + volatile unsigned long crc32,key, num_vol; + num_vol = *num; + + int i; + + crc32 = 0xFF000000 | (num_vol >> 8); + + for(i=0;i<32;i++) + { + key = crc32 & 0x80000000; + if(key) key = 0x31000000; // 00110001 + + crc32 = (crc32<<1) ^key; + } + + crc32 = ((crc32 >> 24) & 0x000000FF) | (num_vol & 0xFFFFFF00); + + if (crc32 == num_vol) return 1; + return 0; +} + diff --git a/crc16.h b/crc16.h new file mode 100644 index 0000000..148c7d6 --- /dev/null +++ b/crc16.h @@ -0,0 +1,10 @@ +typedef unsigned short WORD; +typedef unsigned char byte; + + +unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size ); +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ); +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ); +int get_crc16(unsigned int *buf, int size ); + +unsigned int get_crc32(unsigned long *num); diff --git a/create_rs.bat b/create_rs.bat new file mode 100644 index 0000000..eaa0571 --- /dev/null +++ b/create_rs.bat @@ -0,0 +1,5 @@ +set iname=debug\lampa +set oname=bin\lampa + +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2bin %oname%.hex %oname%.bin diff --git a/ecan.c b/ecan.c new file mode 100644 index 0000000..26e58c7 --- /dev/null +++ b/ecan.c @@ -0,0 +1,355 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" // DSP281x Headerfile Include File +#include "peripher.h" // DSP281x Headerfile Include File + +#include "ecan.h" // DSP281x Headerfile Include File +#include "tools.h" // DSP281x Headerfile Include File + +#include "RS485.h" +#include "message.h" + + +// Prototype statements for functions found within this file. +interrupt void CANa_handler(void); +interrupt void CANa_reset_err(void); +interrupt void CANb_handler(void); +interrupt void CANb_reset_err(void); + +// Global variable for this example +Uint32 ErrorCount; +Uint32 MessageReceivedCount; +Uint32 MessageTransivedCount=0; + +Uint32 TestMbox1 = 0; +Uint32 TestMbox2 = 0; +Uint32 TestMbox3 = 0; + +int CanTimeOutErrorTR = 0; + +int wait=0; + +void Init_Can(int Port, int DevNum) +{ + struct ECAN_REGS ECanShadow; + + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + volatile struct MOTO_REGS * ECanMOTORegs; + + long id = 0x801CE000; + + if(DevNum<0)DevNum=0; + if(DevNum>15)DevNum=15; + +// Configure CAN pins using GPIO regs here + EALLOW; + + if(!Port) + { + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + ECanMOTORegs = &ECanaMOTORegs; + + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; + } + else + { + ECanRegs = &ECanbRegs; + ECanMboxes = &ECanbMboxes; + ECanMOTORegs = &ECanbMOTORegs; + + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; + } + +// Configure the eCAN RX and TX pins for eCAN transmissions + ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant + ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant + +// Specify that 8 bits will be sent/received + ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008; + ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008; + ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008; + +// Disable all Mailboxes +// Required before writing the MSGIDs + ECanRegs->CANME.all = 0; + +// 0 a + ECanMboxes->MBOX0.MSGID.all = id + DevNum; + +// 1 a + ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum; + +// 2 a + ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1); + +// a 0 , + ECanRegs->CANMD.all = 0xFFFFFFFE; + +// 3 a , + ECanRegs->CANME.all = 0x00000007; + +// Clear all TAn bits + ECanRegs->CANTA.all = 0xFFFFFFFF; +// Clear all RMPn bits + ECanRegs->CANRMP.all = 0xFFFFFFFF; +// Clear all interrupt flag bits + ECanRegs->CANGIF0.all = 0xFFFFFFFF; + ECanRegs->CANGIF1.all = 0xFFFFFFFF; +// Clear all error and status bits + ECanRegs->CANES.all=0xffffffff; + +// Request permission to change the configuration registers + ECanShadow.CANMC.all = 0; + ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit + ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit + ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes) + ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity + ECanShadow.CANMC.bit.ABO = 1; // Auto bus on + ECanShadow.CANMC.bit.CCR = 1; +// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set.. + +// CAN + ECanShadow.CANBTC.all = ECanRegs->CANBTC.all; + ECanShadow.CANBTC.bit.BRPREG = 14;//49; // (BRPREG + 1) = 10 feeds a 15 MHz CAN clock + ECanShadow.CANBTC.bit.TSEG2REG = 2; // to the CAN module. (150 / 10 = 15) + ECanShadow.CANBTC.bit.TSEG1REG = 15;//10; // Bit time = 15 + ECanShadow.CANBTC.bit.SJWREG=1; +// 14,2,15 . 49 2 10 for 745 + + ECanRegs->CANBTC.all = ECanShadow.CANBTC.all; + ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0 + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared.. + +// + ECanMOTORegs->MOTO0 = 550000; + ECanMOTORegs->MOTO1 = 550000; + + ECanRegs->CANTOC.all = 1; + ECanRegs->CANTOS.all = 0; // clear all time-out flags + ECanRegs->CANTSC = 0; // clear time-out counter + + ECanShadow.CANGIM.all = 0; + + ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1 + ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0. + ECanShadow.CANGIM.bit.I0EN = 1; + + ECanShadow.CANGIM.bit.MTOM = 1; + ECanShadow.CANGIM.bit.I1EN = 1; + ECanShadow.CANGIM.bit.GIL = 1; + ECanRegs->CANGIM.all = ECanShadow.CANGIM.all; + + if(!Port) + { + PieVectTable.ECAN0INTA = &CANa_handler; + PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6 + PieVectTable.ECAN1INTA = &CANa_reset_err; + PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6 + } + else + { + PieVectTable.ECAN0INTB = &CANb_handler; + PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6 + PieVectTable.ECAN1INTB = &CANb_reset_err; + PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6 + } + IER |= M_INT9; // Enable CPU INT + + EDIS; + +// CAN + + MessageReceivedCount = 0; + ErrorCount = 0; + CanTimeOutErrorTR=0; + MessageTransivedCount=0; +} + +void CAN_send(int Port, int data[], int Addr) +{ + unsigned long hiword,loword; + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + + if(!Port) + { + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + } + else + { +#ifdef TUBER + ECanRegs = &ECanbRegs; + ECanMboxes = &ECanbMboxes; +#endif + } + + if(wait) + if(!(ECanRegs->CANTA.all & 1)) + if(!(ECanRegs->CANAA.all & 1)) + return; + + ECanRegs->CANTA.all = 1; + ECanRegs->CANAA.all = 1; + + hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 | + ((((Uint32)data[Addr ]) & 0xffff) ); + loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)| + ((((Uint32)data[Addr+2]) & 0xffff) ); + + ECanMboxes->MBOX0.MDH.all = hiword; + ECanMboxes->MBOX0.MDL.all = loword; + + EALLOW; + ECanRegs->CANTSC = 0; // clear time-out counter + EDIS; + + ECanRegs->CANTRS.all = 1; // + + wait=1; + + if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1; + if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1; + if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1; +// led1_toggle(); +} + + +void Handlai(volatile struct MBOX * ECanMbox) +{ + unsigned int adr; + unsigned int bit[3]; + unsigned long hiword,loword; + int Data[3]; + + hiword = ECanMbox->MDH.all; + loword = ECanMbox->MDL.all; + + adr = (hiword >> 16); + + bit[0] = adr & 0x8000; + bit[1] = adr & 0x4000; + bit[2] = adr & 0x2000; + + adr &= 0x1fff; + + Data[0] = (hiword ) & 0xffff; + Data[1] = (loword>>16) & 0xffff; + Data[2] = (loword ) & 0xffff; + + if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++; + if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++; + if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2]; + + if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1; + else + led2_toggle(); +} + +interrupt void CANa_handler(void) +{ + unsigned long mask=1; + int box; + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + box = ECanaRegs.CANGIF0.bit.MIV0; + mask <<= box; + ECanaRegs.CANRMP.all = mask; + + Handlai(&ECanaMboxes.MBOX0 + box); + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void CANa_reset_err(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + ECanaRegs.CANTRR.all = 1; + CanTimeOutErrorTR++; + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void CANb_handler(void) +{ +#ifdef TUBER + unsigned long mask=1; + int box; + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + box = ECanbRegs.CANGIF0.bit.MIV0; + mask <<= box; + ECanbRegs.CANRMP.all = mask; + + Handlai(&ECanbMboxes.MBOX0 + box); + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +#endif +} + +interrupt void CANb_reset_err(void) +{ +#ifdef TUBER + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + ECanbRegs.CANTRR.all = 1; + CanTimeOutErrorTR++; + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +#endif +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/ecan.h b/ecan.h new file mode 100644 index 0000000..b9bd676 --- /dev/null +++ b/ecan.h @@ -0,0 +1,3 @@ +void Init_Can(int Port, int DevNum); +void CAN_send(int Port, int data[], int Addr); +extern int CAN_input_data[]; diff --git a/filter_bat2.c b/filter_bat2.c new file mode 100644 index 0000000..a577836 --- /dev/null +++ b/filter_bat2.c @@ -0,0 +1,19 @@ +#include "filter_bat2.h" + +float filterbat(FILTERBAT *b, float InpVarCurr) +{ + float y; + + y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) + + (b->k_1 * b->u_0) + (b->k_2 * b->u_1); + + b->u_1=b->u_0; + b->u_0=y; + b->i_1=b->i_0; + b->i_0=InpVarCurr; + + return y; +} + + + diff --git a/filter_bat2.h b/filter_bat2.h new file mode 100644 index 0000000..a9ed52d --- /dev/null +++ b/filter_bat2.h @@ -0,0 +1,49 @@ +#ifndef _FILTER_BAT2 +#define _FILTER_BAT2 + +#ifdef __cplusplus + extern "C" { +#endif + +#define K1_FILTER_BATTER2_1HZ 0.0000096 +#define K2_FILTER_BATTER2_1HZ 1.94468056 +#define K3_FILTER_BATTER2_1HZ -0.94471895 + +#define K1_FILTER_BATTER2_3HZ 0.00008766 +#define K2_FILTER_BATTER2_3HZ 1.97347532 +#define K3_FILTER_BATTER2_3HZ -0.97382594 + +#define K1_FILTER_BATTER2_5HZ 0.00024135 +#define K2_FILTER_BATTER2_5HZ 1.95581276 +#define K3_FILTER_BATTER2_5HZ -0.95677816 + +#define K1_FILTER_BATTER2_10HZ 0.00094411 +#define K2_FILTER_BATTER2_10HZ 1.91126422 +#define K3_FILTER_BATTER2_10HZ -0.91504065 + +typedef struct { float k_0; + float k_1; + float k_2; + float i_0; + float i_1; + float i_2; + float u_0; + float u_1; + float u_2; + } FILTERBAT; + + +#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \ + K2_FILTER_BATTER2_5HZ, \ + K3_FILTER_BATTER2_5HZ, \ + 0,0,0,0,0,0} + +float filterbat(FILTERBAT *b, float InpVarCurr); + + +#ifdef __cplusplus + } +#endif + +#endif /* _FILTER_BAT2 */ + diff --git a/i2c.c b/i2c.c new file mode 100644 index 0000000..c39b484 --- /dev/null +++ b/i2c.c @@ -0,0 +1,142 @@ +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "i2c.h" // Device Headerfile and Examples Include File + +void InitI2CGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + +/* Configure SCI pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be I2C functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation + + EDIS; +} + + +void I2CA_Init(void) +{ + InitI2CGpio(); + +// Initialize I2C + I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code + + I2caRegs.I2CMDR.bit.IRS = 0; // IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). + #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) + #endif + #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) + #endif + + I2caRegs.I2CCLKL = 10; // NOTE: must be non zero + I2caRegs.I2CCLKH = 5; // NOTE: must be non zero + + I2caRegs.I2CMDR.all = 0x0000; + + I2caRegs.I2CMDR.bit.MST = 1; + + I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset + // Stop I2C when suspended + return; +} + + +Uint16 I2CA_WriteData(unsigned int Addr, int Data) +{ + +// Wait until the STP bit is cleared from any previous master communication. +// Clearing of this bit by the module is delayed until after the SCD bit is +// set. If this bit is not checked prior to initiating a new message, the +// I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + +// Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + +// Setup number of bytes to send +// MsgBuffer + Address + I2caRegs.I2CCNT = 4; + +// Send start as master transmitter + I2caRegs.I2CMDR.all = 0x6E20; + +// Setup data to send + I2caRegs.I2CDXR = (Addr*2)>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = (Addr*2); + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = Data>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = Data; + while(!I2caRegs.I2CSTR.bit.XRDY); + while(I2caRegs.I2CMDR.bit.STP == 1); + while(I2caRegs.I2CSTR.bit.BB == 1); + + return I2C_SUCCESS; +} + + +int I2CA_ReadData(unsigned int Addr) +{ + WORDE data; + +// Wait until the STP bit is cleared from any previous master communication. +// Clearing of this bit by the module is delayed until after the SCD bit is +// set. If this bit is not checked prior to initiating a new message, the +// I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + +// Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + + I2caRegs.I2CCNT = 2; + I2caRegs.I2CMDR.all = 0x6E20; // Send data to setup EEPROM address 0x6620 + I2caRegs.I2CDXR = (Addr*2)>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = (Addr*2); + while(I2caRegs.I2CMDR.bit.STP == 1); + + I2caRegs.I2CCNT = 2; + I2caRegs.I2CMDR.all = 0x6C20; // Send restart as master receiver + + while(!I2caRegs.I2CSTR.bit.RRDY); + data.byt.byte_1 = I2caRegs.I2CDRR; + while(!I2caRegs.I2CSTR.bit.RRDY); + data.byt.byte_0 = I2caRegs.I2CDRR; + + return data.all; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/i2c.h b/i2c.h new file mode 100644 index 0000000..d358a9e --- /dev/null +++ b/i2c.h @@ -0,0 +1,4 @@ +void I2CA_Init(void); +Uint16 I2CA_WriteData(unsigned int Addr, int Data); +int I2CA_ReadData(unsigned int Addr); + diff --git a/ice.CS_/FILE.CDX b/ice.CS_/FILE.CDX new file mode 100644 index 0000000..43d7932 Binary files /dev/null and b/ice.CS_/FILE.CDX differ diff --git a/ice.CS_/FILE.DBF b/ice.CS_/FILE.DBF new file mode 100644 index 0000000..a201a53 Binary files /dev/null and b/ice.CS_/FILE.DBF differ diff --git a/ice.CS_/FILE.FPT b/ice.CS_/FILE.FPT new file mode 100644 index 0000000..29669d4 Binary files /dev/null and b/ice.CS_/FILE.FPT differ diff --git a/ice.CS_/SYMBOL.CDX b/ice.CS_/SYMBOL.CDX new file mode 100644 index 0000000..8584e97 Binary files /dev/null and b/ice.CS_/SYMBOL.CDX differ diff --git a/ice.CS_/SYMBOL.DBF b/ice.CS_/SYMBOL.DBF new file mode 100644 index 0000000..143b8f6 Binary files /dev/null and b/ice.CS_/SYMBOL.DBF differ diff --git a/ice.CS_/SYMBOL.FPT b/ice.CS_/SYMBOL.FPT new file mode 100644 index 0000000..f6526dd Binary files /dev/null and b/ice.CS_/SYMBOL.FPT differ diff --git a/ice.paf2 b/ice.paf2 new file mode 100644 index 0000000..7bccbda Binary files /dev/null and b/ice.paf2 differ diff --git a/ice.pjt b/ice.pjt new file mode 100644 index 0000000..14a6688 --- /dev/null +++ b/ice.pjt @@ -0,0 +1,71 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectDir="F:\ICE\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="ADC.c" +Source="bios.c" +Source="cntrl_adr.c" +Source="crc16.c" +Source="ecan.c" +Source="filter_bat2.c" +Source="i2c.c" +Source="isolatio.c" +Source="log_to_mem.c" +Source="main.c" +Source="measure.c" +Source="message.c" +Source="peripher.c" +Source="RS485.c" +Source="spise2p.c" +Source="tools.c" +Source="v120\DSP2833x_common\source\DSP2833x_Adc.c" +Source="v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="v120\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="v120\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c" +Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c" +Source="v120\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="v120\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="v120\DSP2833x_common\source\DSP2833x_Xintf.c" +Source="v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="F28335.cmd" +Source="v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Debug" Settings] +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.hex -i +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.bin -b + +["Compiler" Settings: "Debug"] +Options=-g -pdsw225 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\v120\DSP2833x_headers\include" -i"$(Proj_dir)\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28 + +["Linker" Settings: "Debug"] +Options=-c -e_c_int00 -m".\Debug\ice.map" -o".\bin\ice.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-c -m".\Release\UKSS745.1TMS320F28335.map" -o".\Release\UKSS745.1TMS320F28335.out" -w -x + +["F28335.cmd" Settings: "Debug"] +LinkOrder=1 + +["F28335.cmd" Settings: "Release"] +LinkOrder=1 + +["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + +["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/ice.sbl b/ice.sbl new file mode 100644 index 0000000..d753984 Binary files /dev/null and b/ice.sbl differ diff --git a/isolatio.c b/isolatio.c new file mode 100644 index 0000000..ae46038 --- /dev/null +++ b/isolatio.c @@ -0,0 +1,148 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "filter_bat2.h" +#include "measure.h" +#include "message.h" +#include "package.h" +#include "peripher.h" +#include "crc16.h" +#include "isolatio.h" +#include // ! sqrt !!! + +OPTOCANAL opt[2]; + +void DCLK(int i, int x) +{ + x=!x; + + if(i) + { + if(x) GpioDataRegs.GPASET.bit.GPIO26=1; + else GpioDataRegs.GPACLEAR.bit.GPIO26=1; + } + else + { + if(x) GpioDataRegs.GPBSET.bit.GPIO32=1; + else GpioDataRegs.GPBCLEAR.bit.GPIO32=1; +} } + +int DIN(int i) +{ + if(i) return !GpioDataRegs.GPBDAT.bit.GPIO52; + else return !GpioDataRegs.GPADAT.bit.GPIO23; +} + +void BLIN(int i) +{ + if(i) GpioDataRegs.GPBTOGGLE.bit.GPIO53=1; + else GpioDataRegs.GPATOGGLE.bit.GPIO24=1; +} + +interrupt void cpu_timer1_isr_ISOL(void) +{ + ERROR error; + float Riso=0,kff=1; + static float fRiso[2]; + static int ist[2] = {1,1}; + long numb=0; + int i; + static unsigned int count_ready=0; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + ServiceDog(); + + if(++count_ready >= period_ready) + { + count_ready=0; + + if((!sig.bit.Error)|(cTestLamp)) toggle_READY(); + else set_READY(); + } + + for(i=0;i<2;i++) + { + if(sens_error[i].bit.Bypas) + { + sens_error[i].all = 0; + sens_error[i].bit.Bypas = 1; + Modbus[i+DATASTART].all = 0; + continue; + } + + if(opt[i].Wait) + { + opt[i].Wait--; + opt[i].bit = 0; + opt[i].clk = 0; + DCLK(i,0); + continue; + } + + opt[i].clk=!opt[i].clk; + DCLK(i,opt[i].clk); + if(!opt[i].clk) + { + opt[i].Numb = (opt[i].Numb<<1) | DIN(i); + if(++opt[i].bit>=32) + { + error.all = 0; + + opt[i].Wait = (TELE_FREQ/1000)*optopowse; + opt[!i].Wait =(TELE_FREQ/2000)*optopowse; + if(get_crc32(&(opt[i].Numb))) + { + numb = opt[i].Numb; + numb = numb / 256; // + Riso=numb; + + if(ist[i]) { kff=1; ist[i]=0; } + else kff = optofiltr; + fRiso[i] += (Riso-fRiso[i])/kff; + + numb = (long)fRiso[i]; + Modbus[i*2+0x10].all = (int)(numb & 0xFFFF); + Modbus[i*2+0x11].all = (int)(numb>>16); + + Riso=numb; + Riso = Riso/256; // + Modbus[i+DATASTART].all = Riso; + opt[i].ers = 0; BLIN(i); + } + else + { + if(++opt[i].ers > 20) + { + opt[i].ers = 20; + error.bit.Tear = 1; + } + } + + reset_errs(i,error); + + } } + } + + sig.all = chk.all; + chk.all = 0; + +} +void timer_Init() +{ + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT13 = &cpu_timer1_isr_ISOL; + EDIS; // This is needed to disable write to EALLOW protected registers + + ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/TELE_FREQ); + CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + IER |= M_INT13; + + period_ready = TELE_FREQ / (READY_FREQ * 2); + +} diff --git a/isolatio.h b/isolatio.h new file mode 100644 index 0000000..1b2e1ad --- /dev/null +++ b/isolatio.h @@ -0,0 +1,13 @@ +void timer_Init(void); +int get_isolatio(void); + +typedef struct +{ + unsigned int clk; + unsigned int bit; + unsigned int ers; + unsigned Wait; + unsigned long Numb; +} OPTOCANAL; + +#define TELE_FREQ 2000 // diff --git a/kanal.c b/kanal.c new file mode 100644 index 0000000..704f829 --- /dev/null +++ b/kanal.c @@ -0,0 +1,164 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "measure.h" + +#include "RS485.h" +#include "message.h" +#include "kanal.h" +#include "test.h" +#include "package.h" +#include "tools.h" + +#include "peripher.h" + +int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0}; + +void DCLK(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO6=1; + else GpioDataRegs.GPACLEAR.bit.GPIO6=1; + DSP28x_usDelay(1L); +} + +void DOUT(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO8=1; + else GpioDataRegs.GPACLEAR.bit.GPIO8=1; + DSP28x_usDelay(1L); +} + +void RESET() +{ + DCLK(0); DOUT(1); + DCLK(0); DOUT(0); +} + +void SENDBIT(int x) +{ + DOUT(x); DCLK(1); + DOUT(0); DCLK(0); +} + +void kanal_Send(int adr, long dat, int dot) +{ + long Word,data,aliq_part,dg[4]; + int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len; + + if(adr>1) // + { + Word =dat; + } + + else + + { + if(dot<0 || dot>13) // : -... + { + dg[3] = 0xA; dg[2] = 0xE; + dg[1] = 0xF; dg[0] = 0xF; + punkt = 0x7; + } + + else + + { + if(dat<0) sgn=1; + data = labs(dat); + + aliq_part = data; + for(i=0;i0) + { + aliq_len++; dat/=10; + } + + if(aliq_len+sgn>4) + { + if(sgn) dg[3] = 0xA; + else dg[3] = 0xF; + + dat = aliq_part; + for(i=1;i0;i--) + { + if((dg[i]==0)&&(i!=dot)) + dg[i]=0xF; // + else break; + } + + if(sgn) + for(i=1;i<4;i++) + { + if( (dg[i]==0xF)||(i==3)) + { + dg[i]=0xA; // + break; + } } } } + + for(i=0;i<4;i++) + { + dg[i] = digits[dg[i]]; + if((punkt>>i)&1) dg[i]+= 128; + + } + + Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) | + ((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000); + } + + for (i=0;i<4;i++) + { + if(addr>0x10) break; + + for (j=0;j<8;j++) + { + bit = Word & 1; Word >>= 1; + SENDBIT(bit); + } + + byt = addr; + for (j=0;j<6;j++) + { + bit = byt & 1; byt >>= 1; + SENDBIT(bit); + } + addr++; + + RESET(); + } +} diff --git a/kanal.h b/kanal.h new file mode 100644 index 0000000..44cb4e7 --- /dev/null +++ b/kanal.h @@ -0,0 +1,7 @@ +void kanal_Send(int adr, long dat, int dot); + +#define adr_diod1 0x00 // 4 +#define adr_diod2 0x04 // 4 +#define adr_digg1 0x08 // 4 +#define adr_digg2 0x0C // 4 +#define adr_lamps 0x10 // diff --git a/log_to_mem.c b/log_to_mem.c new file mode 100644 index 0000000..c26404b --- /dev/null +++ b/log_to_mem.c @@ -0,0 +1,34 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2001. */ +/****************************************************************/ +/* log_to_mem.c + **************************************************************** + * y * + ****************************************************************/ + +#include "log_to_mem.h" + +int no_write = 1, + never_write = 0; // , ( ) + +#pragma DATA_SECTION(logs_block,".logg"); +unsigned int logs_block[0xF000]; + +LOG Log; +unsigned int flog=0; + +// , +void clear_mem() +{ + unsigned long i; + + Log.Start = LOG_PAGE_START; + Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN; + Log.Adres = Log.Start; + Log.Circl = 0; + + for (i=Log.Start; i (Log.Finis - x)) Log.Adres = Log.Start + +/* () */ +void clear_mem(); + +#ifdef __cplusplus + } +#endif + +#endif /* _LOG_TO_MEM */ diff --git a/main.c b/main.c new file mode 100644 index 0000000..d574b57 --- /dev/null +++ b/main.c @@ -0,0 +1,180 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +#include "cntrl_adr.h" +#include "RS485.h" +#include "BIOS_DSP.h" +#include "filter_bat2.h" +#include "measure.h" +#include "Message.h" +#include "package.h" + +#include "spise2p.h" +#include "i2c.h" + +#include "tools.h" +#include "peripher.h" +#include "ADC.h" + +#include "ecan.h" +#include "log_to_mem.h" + +#include "measure.h" +#include "isolatio.h" + +extern void DSP28x_usDelay(Uint32 Count); + +int kaka[3]={64,0,0}; + +void main() +{ + int i,j; + static int canpowse=0,cancount[3],cancell[3],circ[3]; + RS_DATA * rs; + + + InitSysCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + DINT; + + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + init_zone7(); + + setup_leds_line(); + led1_on(); + led2_off(); + for (i=0;i<10;i++) + { + pause_us(50000); + led2_toggle(); + led1_toggle(); + } + led1_off(); + led2_off(); + + get_Mode(); + set_cntrl_addr(Mode,16); + create_uart_vars(sizeof(CMD_TO_TMS)); + setup_uart(COM_1,115200); + setup_uart(COM_2,115200); + Init_Can(0,Addrr); + Init_Seeprom(); + clear_mem(); + + EnableInterrupts(); + + if(Desk!=dsk_ISOL) + { + setup_adc(); + Init_sensors(); + I2CA_Init(); pause_us(500000); + Load_caliber(); + } + else + { + timer_Init(); + Init_optic(); + } + + Load_params(); + Init_packMask(); + + LastMode = Addrr; + + for(i=0;i<3;i++) + { + cancount[i]= 0; + cancell[i] = CAN_send_start; + } + + EALLOW; + SysCtrlRegs.WDCR= 0x2F; + EDIS; + + MAY=1; + + while(1) + { + if(canpowse) canpowse--; + else + { + canpowse = 0x1000; + for(i=0;i<3;i++) + { + if(cancount[i]) cancount[i]--; + else + { + cancount[i] = Cancount[i]; circ[i] = 0; + + while( !((Maska[i][cancell[i]/16]>>(cancell[i]%16))&1) && circ[i] < 2 ) + if(cancell[i]>CAN_send_finis) + { + cancell[i] = CAN_send_start; circ[i]++; + } + else cancell[i]++; + + if(cancell[i]<=CAN_send_finis && circ[i] < 2) + { + CAN_send(0,(int *)Modbus,cancell[i]); + cancell[i]+=3; + } } } } + + if(cSaveParam) + { + cSaveParam=0; + Save_params(); + } + + if(cReadCal) + { + cReadCal=0; + Load_caliber(); + } + + if(cDefParam) + { + cDefParam=0; + Default_params(); + } + + get_Inputs(); + + if(Desk!=dsk_SHKF) + { + Modbus[23].all = Inputs.wrd.word_0; + } + + for(i=0;i<2;i++) + { + if(i) rs = &rs_a; + else rs = &rs_b; + + j = get_command(rs); + + if(j!=-1) + switch(j) + { + case CMD_INIT: init(rs); led2_toggle();break; // + case CMD_INITLOAD: initload(rs); led2_toggle();break; // + case CMD_RUN: run(rs); led2_toggle();break; // + case CMD_LOAD: load(rs); led2_toggle();break; // + case CMD_PEEK: peek(rs); led2_toggle();break; // + case CMD_POKE: poke(rs); led2_toggle();break; // + case CMD_UPLOAD: upload(rs); led2_toggle();break; // + case CMD_EXTEND: extendbios(rs); led2_toggle();break; // + + case CMD_TFLASH: tflash(rs); led2_toggle();break; // TMS + +// case CMD_STD: ReceiveCommand(rs); led2_toggle();break; + case CMD_MODBUS_3: ReceiveCommandModbus3(rs); led2_toggle();break; + case CMD_MODBUS_6: ReceiveCommandModbus6(rs); led2_toggle();break; + + default: break; +} } } } + diff --git a/measure.c b/measure.c new file mode 100644 index 0000000..a08046a --- /dev/null +++ b/measure.c @@ -0,0 +1,656 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "package.h" + +#include "measure.h" +#include "package.h" + +#include "peripher.h" +#include "ADC.h" + +#include "RS485.h" +#include "message.h" +#include "log_to_mem.h" + +#include // ! sqrt !!! + +int MAX_TPL_CANAL=0; // +int period_ready, period_blink, period_dac, time_dac; + +FLAG chk,sig; +long time_1_5sec, time_5msec, time_5sec; + +long err_count[6]; +float lev_count[6]; + +int sens_type[24]; +int sens_pair[24]; +long din_count[32]; + +int adc0[24]; +int tmp0[24]; +float tmpK[24]; + +FILTERBAT def_FILTERBAT = DEF_FILTERBAT; +FILTERBAT filter[40]; + +long sens_count[28]; + +interrupt void cpu_timer1_isr_SENS(void); + +/********************************************************************/ +/* */ +/********************************************************************/ +float im_calc(float ia,float ib) +{ + float isa,isb; + + isa = - 1.5 * (ia + ib); + isb = COSPi6 * (ia - ib); + return (2*sqrt(isa*isa+isb*isb)/3); +} + + +interrupt void cpu_timer1_isr_SENS(void) +{ + static unsigned int + count_ready=0, count_blink=0, count_bright=0, count_mode, + blink_over, blink_alarm, work_lamp, heat_lamp, errr_lamp; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + if(++count_ready >= period_ready) + { + count_ready=0; + + if((!sig.bit.Error)|(cTestLamp)) toggle_READY(); + else set_READY(); + ServiceDog(); + } + + if(++count_bright == maximum_bright) + { + count_bright = 0 ; + + if(Desk==dsk_COMM) + { + if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO60=1; + else GpioDataRegs.GPBSET.bit.GPIO60=1; + if(heat_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO58=1; + else GpioDataRegs.GPBSET.bit.GPIO58=1; + if(errr_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; + else GpioDataRegs.GPBSET.bit.GPIO62=1; + } + + if(Mode==adr_SHKF) + { + if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; + else GpioDataRegs.GPBSET.bit.GPIO62=1; + } } + + if(count_bright == Brightness) + { + if(Desk==dsk_COMM) + { + GpioDataRegs.GPBSET.bit.GPIO60=1; + GpioDataRegs.GPBSET.bit.GPIO58=1; + GpioDataRegs.GPBSET.bit.GPIO62=1; + } + + if(Desk==dsk_SHKF) + { + GpioDataRegs.GPBSET.bit.GPIO62=1; + } } + + if(++count_blink >= period_blink) + { + count_blink=0; + count_mode++; + blink_over = (count_mode & 1)?1:0; + blink_alarm = (count_mode & 7)?1:0; + + if(cExtLamp) + { + work_lamp = cExtLite; + heat_lamp = cExtLite; + errr_lamp = cExtLite; + } + else + { + if(cTestLamp) + { + work_lamp = blink_over; + heat_lamp = blink_over; + errr_lamp = blink_over; + } + else + { + if(Mode==adr_SHKF) + { + if(sig.bit.Error) work_lamp = blink_over; + else work_lamp = 1; + } + else + { + if(sig.bit.Error) work_lamp = 0;//blink_over; +// else if(sig.bit.Alarm) work_lamp = blink_alarm; + else work_lamp = 1; + + if(sig.bit.OverHeat) heat_lamp = 1; + else if(sig.bit.SubHeat) heat_lamp = blink_over; + else if(sig.bit.OutHeat) heat_lamp = !blink_alarm; + else heat_lamp = 0; +} } } } } + +void Init_optic() +{ + int i; + + for(i=0;i<24;i++) + { + sens_type[i]=0; + sens_pair[i]=i; + } + + sens_type[0] = OPTIC; + sens_type[1] = OPTIC; +} + +void Init_sensors() +{ + int i; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT13 = &cpu_timer1_isr_SENS; + EDIS; // This is needed to disable write to EALLOW protected registers + + ConfigCpuTimer(&CpuTimer1, (SYSCLKOUT/1000000), 1000000/SIG_FREQ); + CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + IER |= M_INT13; + + period_ready = SIG_FREQ / (READY_FREQ * 2); + period_blink = SIG_FREQ / (BLINK_FREQ * 2); + + period_dac = SIG_FREQ / (DAC_FREQ); + time_dac = LOAD_TIME * DAC_FREQ; + + time_1_5sec = (3 * ADC_FREQ) / 2; + time_5msec = (5 * ADC_FREQ) / 1000; + time_5sec = (5 * ADC_FREQ); + + for(i=0;i<24;i++) + { + sens_type[i]=0; + sens_pair[i]=i; + } + + if((Mode==adr_REC1)||(Mode==adr_REC2)) + { + sens_type[0]=TERMO_AD; + sens_type[1]=TERMO_AD; + sens_type[2]=TERMO_AD; + sens_type[3]=TERMO_AD; + + sens_type[4]=TERMO_AD; + sens_type[5]=TERMO_AD; + +//sens_type[6]=TERMO_AD; +//sens_type[7]=TERMO_AD; + + + sens_type[8]=TERMO_RS; + sens_type[9]=TERMO_RS; + sens_type[10]=TERMO_RS; + sens_type[11]=TERMO_RS; + + sens_type[12]=VOLTAGE; sens_pair[12]=13; + sens_type[13]=VOLTAGE; sens_pair[13]=12; + sens_type[14]=VOLTAGE; sens_pair[14]=15; + sens_type[15]=VOLTAGE; sens_pair[15]=14; + + Modbus[12].bit.bitE = 1; // Ignore + Modbus[13].bit.bitE = 1; // Ignore + Modbus[14].bit.bitE = 1; // Ignore + Modbus[15].bit.bitE = 1; // Ignore + } + + if((Mode==adr_INV1)||(Mode==adr_INV2)) + { + sens_type[0]=TERMO_AD; + sens_type[1]=TERMO_AD; + sens_type[2]=TERMO_AD; + sens_type[3]=TERMO_AD; + + sens_type[4]=TERMO_AD; + sens_type[5]=TERMO_AD; +//sens_type[6]=TERMO_AD; + + sens_type[7]=TERMO_RS; + sens_type[8]=TERMO_RS; + sens_type[9]=TERMO_RS; + sens_type[10]=TERMO_RS; + sens_type[11]=TERMO_RS; + } + + if(Mode==adr_SHKF) + { + sens_type[0 ] = POWER_380; sens_pair[0]=1; + sens_type[1 ] = POWER_380; sens_pair[1]=0; + sens_type[2 ] = POWER_220; sens_pair[2]=3; + sens_type[3 ] = POWER_220; sens_pair[3]=2; + sens_type[4 ] = POWER_31; + sens_type[5 ] = POWER_31; + sens_type[6 ] = POWER_24; + sens_type[7 ] = POWER_24; + sens_type[8 ] = POWER_24; + sens_type[9 ] = POWER_24; + sens_type[10] = POWER_24; + sens_type[11] = POWER_24; + sens_type[12] = POWER_15; + sens_type[13] = TERMO_AD; + sens_type[14] = TERMO_AD; + sens_type[15] = VIRT_24; + sens_type[16] = VIRT_24; + } + + for(i=0;i<4; i++) err_count[i] = 0; + for(i=0;i<6; i++) lev_count[i] = 0; + for(i=0;i<28;i++) sens_count[i] = 0; + for(i=0;i<32;i++) din_count[i] = 0; + for(i=0;i<40;i++) filter[i] = def_FILTERBAT; + + for(i=0;i=edge) return 1; + (*count)++; return pre; + } + if( (*count) == 0 ) return 0; + (*count)--; return pre; +} + +void reset_errs(int sens, ERROR er) +{ +// unsigned long report; + unsigned int set; + ERROR err; + + err=er; + + if(!sens_error[sens].bit.Latch) + { + set = sens_error[sens].all & NOER; + sens_error[sens].all = err.all | set; + } + else + { + sens_error[sens].all |= err.all; + } + sens_error[sens].bit.Ready = !(err.bit.Stop && (!sens_error[sens].bit.Ignor)); + chk.bit.Error|= !(sens_error[sens].bit.Ready); +} + + +ERROR control_ADC(int sens, int number, int zero) +{ + ERROR err; + int erwait; + + err.all = 0; + + if(TermoSW) erwait = SENS_ERR_WAIT; + else erwait = ADC_FREQ; + +// + if(er_anal(((number <= zero)||(number >= (0x0FFF-(zero/100)))), + &sens_count[sens],erwait, + sens_error[sens].bit.Tear)) + { + err.bit.Tear = 1; + } +/* +// + if(er_anal( (sens_prev[sens] == number), + &sens_count[sens][1],ADC_FREQ, + sens_error[sens].bit.Stick)) + { + err.bit.Stick = 1; + } + sens_prev[sens] = number; +*/ + return err; +} + + + + + + +int input_freq(int chan, int Volt) +{ + static int prevolt[4],tics[4],tacs[4],tic[4],tac[4]; + static long Freq = 0; + int i,sum=0,bum=0; + + if(Volt >= Zero_lev[chan]) + if(prevolt[chan]< Zero_lev[chan]) + { + tics[chan] = tic[chan]; tic[chan] = 0; bum = 1; + } + + if(Volt < Zero_lev[chan]) + if(prevolt[chan]>= Zero_lev[chan]) + { + tacs[chan] = tac[chan]; tac[chan] = 0; bum = 1; + } + + if(bum) + { + for(i=0;i<4;i++) sum += tics[i] + tacs[i]; + Freq = (80L * ADC_FREQ) / sum; + } + + prevolt[chan] = Volt; + tic[chan]++; + tac[chan]++; + + return Freq; +} + + + + +void Current_count(int sens) +{ + float Numb,Current,fAmpl; + static float aCurrent,Amplitude; + static int prezer0=0; + int chan, pair, ist, thrd, i, ignor; + int freq=0; + + ERROR error; + + error.all = 0; + + chan = sens - MAX_TPL_CANAL; + pair = sens_pair[sens] - MAX_TPL_CANAL; + ist = !(chan & 1); + thrd= (chan >>1) + 4; + + if(sens_error[sens].bit.Bypas) + { + sens_error[sens].all = 0; + sens_error[sens].bit.Bypas = 1; + Modbus[sens+DATASTART].all = 0; + return; + } + + Numb = ADC_table[sens]; + + if(cTermoCal||cSetZero) + { + if(!prezer0) + for(i=0;i<4;i++) lev_count[i] = Numb; + lev_count[chan] += (Numb-lev_count[chan])/1000.0; + adc0[sens] = (int)(filterbat(&filter[sens],lev_count[chan])); + Zero_lev[chan] = adc0[sens]; + Modbus[sens+DATASTART].all = adc0[sens]; + } + prezer0 = (cTermoCal||cSetZero); + + Current = (Numb - adc0[sens]) * tmpK[sens]; + + if(!(cTermoCal||cSetZero)) + { + freq = input_freq(chan,Numb); + + + lev_count[chan] += (fabs(Current)-lev_count[chan])/1000.0; + +// + if(ist) + { + aCurrent = -Current; // - + } + else + { +// + Amplitude = im_calc(Current,aCurrent); + fAmpl = filterbat(&filter[sens],Amplitude); + + if(fAmpl<100) + { + fAmpl=0; freq=0; + } + + +// Modbus[sens+DATASTART-1].all = (int)fAmpl;//(int)Amplitude; + Modbus[sens+DATASTART-1].all = (int)(fAmpl/RADIX2); + +// + lev_count[thrd] += (fabs(-Current-aCurrent)-lev_count[thrd])/1000.0; + +i=(8-((sens+DATASTART-1)%8)); +Modbus[sens+DATASTART+i-1+(thrd-4)*3].all = lev_count[chan]; +Modbus[sens+DATASTART+i +(thrd-4)*3].all = lev_count[pair]; +Modbus[sens+DATASTART+i+1+(thrd-4)*3].all = lev_count[thrd]; + + } + + Modbus[sens+DATASTART].all = freq; + +// ! + if(Current > 1.1 * sens_hi_edge[sens]) + { + error.bit.Hyper = 1; + error.bit.Stop = 1; + } + + Numb = lev_count[chan]; + if(Numb 0.2) && (Numb>100), + &err_count[chan],time_1_5sec,0)) + { + error.bit.Wry = 1; + error.bit.Stop = 1; + } + + if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.2) && (Numb>100), + &err_count[thrd],time_1_5sec,0)) + { + error.bit.Wry = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(!ist) + { + if(Amplitude > sens_hi_edge[sens]) + { + error.bit.Hyper = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(Amplitude < sens_lo_edge[sens]) + { + error.bit.Out = 1; + if(!ignor) + error.bit.Stop = 1; + } } } + + reset_errs(sens,error); + +} + +void Temper_count(int chan) +{ + float Numb; + int Temper; + int ignor; + ERROR error; + int zer0; + + if(!chan) + { + sig.all = chk.all; + chk.all = 0; + } + + if(chansens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) || + (Temper>sens_hi_edge[chan]) ) + { + error.bit.Hyper = 1; + if(!ignor) + { + error.bit.Stop = 1; + chk.bit.OverHeat= 1; + } } + + else + +// + + if(Temper>sens_lo_edge[chan]) + { + error.bit.Over = 1; + if(!ignor) + chk.bit.SubHeat = 1; + } } + + if(error.all) chk.bit.OutHeat = 1; + + reset_errs(chan,error); + +} + +void Power_count(int chan) +{ + float Numb; + int Power,ignor,bitt; + ERROR error; + + if(sens_error[chan].bit.Bypas) + { + sens_error[chan].all = 0; + sens_error[chan].bit.Bypas = 1; + Modbus[chan+DATASTART].all = 0; + return; + } + + Numb = ADC_table[chan]; + + if(cTermoCal) + { + Modbus[chan+DATASTART].all = (int)(Numb); + return; // + } + + Power = (Numb * tmpK[chan]+5)/10.0; // powK[sens_type[chan]]; + + Modbus[chan+DATASTART].all = Power; + + error.all = 0; + ignor = sens_error[chan].bit.Ignor; + + if(Power sens_hi_edge[chan]) + { + error.bit.Hyper = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(chan>3) + { + bitt = (chan-4)*2; + error.bit.Contr1 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + error.bit.Contr2 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); + } + + if(error.all) + if(!ignor) + chk.bit.Alarm = 1; + reset_errs(chan,error); +} diff --git a/measure.h b/measure.h new file mode 100644 index 0000000..ce5b7c4 --- /dev/null +++ b/measure.h @@ -0,0 +1,136 @@ +// +#ifndef _MEASURE +#define _MEASURE + +void Init_sensors(void); +void Init_optic(void); +void Init_packMask(void); +void Temper_count(int chan); +void Current_count(int chan); +void Power_count(int chan); + +typedef union +{ + struct + { + unsigned int Tear :1; + unsigned int Stick :1; + unsigned int Wry :1; + unsigned int Out :1; + unsigned int Over :1; + unsigned int Hyper :1; + unsigned int Contr1 :1; + unsigned int Contr2 :1; + + unsigned int Stop :1; + unsigned int Ready :1; + unsigned int res :3; + unsigned int Latch :1; + unsigned int Ignor :1; + unsigned int Bypas :1; + + } bit; + unsigned int all; + +} ERROR; + +typedef union +{ + struct + { + unsigned int Error :1; + unsigned int Alarm :1; + unsigned int OverHeat :1; + unsigned int SubHeat :1; + unsigned int OutHeat :1; + unsigned int Test_lamp :1; + + } bit; + unsigned int all; + +} FLAG; + +#define NOER 0xE000 +#define EROR 0x01FF + +#define SIG_FREQ 4000 // +#define READY_FREQ 1000 // +#define BLINK_FREQ 2 // +#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // (777*5) +#define DAC_FREQ 50 // + +#define LOAD_TIME 10 // sec + + +#define SENS_ERR_WAIT 10 + +#define maximum_bright 10 + +/* +#define SNOW 1720.0 //1920.0 +#define BOIL 2360.0 //2561.0 + +#define tmp_T_0 0.0 +#define tmp_T_1 200.00 +#define tmp_A1_0 978.0 +#define tmp_A1_1 1686.0 +#define tmp_A2_0 1017.0 +#define tmp_A2_1 1736.0 +#define eta_A1 1002.0 +#define eta_A2 1542.0 +*/ + +#define tmp_T_0 84.31 // 68Om +#define tmp_T_1 234.19 // 100Om +#define tmp_A1_0 540.0 // 1 68 +#define tmp_A2_0 500.0 // 1 100 +#define tmp_A1_1 1055.0 // 2 68 +#define tmp_A2_1 1060.0 // 2 100 + + +#define ZERO 27 + +#define mka300 2040 +#define mka400 2700 + +#define C100 650 +#define C150 2370 + +#define Cooling 5 // () + +#define COSPi6 0.86602540378443864676372317075294 + +#define RADIX2 1.4142135623730950488016887242097 + +#define CURRENT 1 // +#define VOLTAGE 2 // + +#define POWER_380 3 // 380 +#define POWER_220 4 // 220 +#define POWER_31 5 // 31 +#define POWER_24 6 // 24 +#define VIRT_24 7 // 24 +#define POWER_15 8 // 15 +#define TERMO_AD 9 // +#define TERMO_RS 10 // +#define OPTIC 11 // + +extern int MAX_TPL_CANAL; + +extern FILTERBAT filter[]; + +extern ERROR * sens_error; +extern int * sens_hi_edge; +extern int * sens_lo_edge; + +extern int adc0[],tmp0[]; + +#define Zero_lev (adc0+12) //((int *)&Modbus[0x74]) + +extern float tmpK[]; +extern FLAG chk,sig; +extern int sens_type[]; + +extern int period_ready; + +#endif //_MEASURE diff --git a/message.c b/message.c new file mode 100644 index 0000000..74251dc --- /dev/null +++ b/message.c @@ -0,0 +1,355 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "package.h" +#include "RS485.h" +#include "crc16.h" +#include "cntrl_adr.h" +#include "bios_dsp.h" +#include "filter_bat2.h" +#include "measure.h" +#include "message.h" + + +#include "ADC.h" +#include "peripher.h" + +#include "ecan.h" +#include "spise2p.h" +#include "i2c.h" + +WORDE Modbus[ANSWER_LEN+1]; +WORDE reply[REPLY_LEN]; + +unsigned int param[ANSWER_LEN+1]; + +LONGE* outputs; + +int DataAnalog1,DataAnalog2; + +ERROR * sens_error; +int * sens_hi_edge; +int * sens_lo_edge; + +unsigned int Maska[3][9]; + +void Default_params() +{ + unsigned int i; + + for(i=0;iRS_Header[2] << 8) |*/ rs_arr->RS_Header[3]; + +// + Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // + /* */ + + rs_arr->buffer[0] = CNTRL_ADDR; + rs_arr->buffer[1] = CMD_MODBUS_3; + rs_arr->buffer[2] = Length_MB*2; + + for (i=0;ibuffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi); + rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo); + } + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3); + + rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc); + rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc); + + rs_arr->buffer[Length_MB*2+5] = 0; + rs_arr->buffer[Length_MB*2+6] = 0; + rs_arr->buffer[Length_MB*2+7] = 0; + rs_arr->buffer[Length_MB*2+8] = 0; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8); + + return; +} + +void ReceiveCommandModbus6(RS_DATA *rs_arr) +{ + unsigned int Address_MB, Data_MB, i; + + ///////////////////////////////////////////////// + // + /* */ + + for (i=0;i<8;i++) + rs_arr->buffer[i] = rs_arr->RS_Header[i]; + +// + Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]); + +// + Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + Modbus[Address_MB].all = Data_MB; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, 10); +} diff --git a/message.h b/message.h new file mode 100644 index 0000000..2b694a5 --- /dev/null +++ b/message.h @@ -0,0 +1,51 @@ +#ifndef MESSAGE_H +#define MESSAGE_H + +typedef unsigned char CHAR; + +#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6 +#define REPLY_LEN 0x19 + +#define byte_hi byte_1 +#define byte_lo byte_0 + +typedef struct +{ + unsigned char Address; // + unsigned char Number; // + + BAITE byte0; + BAITE byte1; + BAITE byte2; + BAITE byte3; + BAITE byte4; + BAITE byte5; + BAITE byte6; + BAITE byte7; + + unsigned char crc_lo; + unsigned char crc_hi; + unsigned char add_byte; +} CMD_TO_TMS; + +extern WORDE Modbus[]; +extern WORDE reply[]; + +extern LONGE* outputs; + +extern int DataAnalog1,DataAnalog2; + +extern unsigned int Maska[][9]; + +//void ReceiveCommand(RS_DATA *rs_arr); +void ReceiveCommandModbus3(RS_DATA *rs_arr); +void ReceiveCommandModbus6(RS_DATA *rs_arr); + +void reset_errs(int sens, ERROR er); + +void Save_params(void); +void Load_params(void); +void Load_caliber(void); +void Default_params(void); + +#endif //MESSAGE_H diff --git a/package.h b/package.h new file mode 100644 index 0000000..bec9f68 --- /dev/null +++ b/package.h @@ -0,0 +1,56 @@ +#ifndef PACKAGE +#define PACKAGE + +#define TERMOPAIR 14 +#define CURRENTOS (TERMOPAIR*2) +#define DATASTART 24 + +//----------------------------------------------- +#define adr_REC1 1 +#define adr_REC2 2 +#define adr_INV1 3 +#define adr_INV2 4 +#define adr_SHKF 5 +#define adr_ISOL 6 +//----------------------------------------------- + +//----------------------------------------------- +#define dsk_COMM 1 +#define dsk_SHKF 2 +#define dsk_ISOL 3 +//----------------------------------------------- + + +#define CAN_send_start 0 // +#define CAN_send_finis 0x6F // + +#define start_sens_error 0 +#define start_sens_hi_edge 48 +#define start_sens_lo_edge 72 + +#define optopowse Modbus[0x60].all // , ms +#define optofiltr Modbus[0x61].all // + +#define Brightness Modbus[0x64].all // + +#define Cancount ((int *)&Modbus[0x65]) + +#define Zeroes ((int *)&Modbus[0x70]) + +#define LastMode Modbus[126].all + +#define Commands Modbus[127].all +#define cTestLamp Modbus[127].bit.bit0 +#define cSetZero Modbus[127].bit.bit1 +#define cSaveParam Modbus[127].bit.bit2 +#define cDefParam Modbus[127].bit.bit3 + +#define cTermoCal Modbus[127].bit.bit4 +#define cReadCal Modbus[127].bit.bit5 + +#define cExtLamp Modbus[127].bit.bit6 +#define cExtLite Modbus[127].bit.bit7 + + +#endif //PACKAGE + diff --git a/peripher.c b/peripher.c new file mode 100644 index 0000000..70048b1 --- /dev/null +++ b/peripher.c @@ -0,0 +1,143 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "filter_bat2.h" +#include "measure.h" +#include "RS485.h" +#include "message.h" + +#include "package.h" + +#include "peripher.h" +#include "GPIO_table.h" + + +int Mode,Desk,Addrr,TermoAD=0,TermoRS=0,TermoSW=0,Currentoz=0; +LONGE Inputs; + +int ExtraCanal[24]; + +void get_Mode() +{ + int i,qua; + + EALLOW; + + GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 0011 + GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 1927 + GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFCC0; // 3234, 36 + GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 4853, 5863 + + GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO21 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; + + EDIS; + + Mode=0; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO22; + if(qua>50) Mode += 1; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO20; + if(qua>50) Mode += 2; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO21; + if(qua>50) Mode += 4; + + Addrr = Mode*2; + + Mode+= 1; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPBDAT.bit.GPIO51; + if(qua>50) Addrr += 1; + + if( (Mode==adr_REC1)||(Mode==adr_REC2)) Currentoz = 1; + if( (Mode==adr_REC1)||(Mode==adr_REC2)|| + (Mode==adr_INV1)||(Mode==adr_INV2)) Desk = dsk_COMM; + if (Mode==adr_SHKF) Desk = dsk_SHKF; + if (Mode==adr_ISOL) Desk = dsk_ISOL; + + EALLOW; + switch(Desk) + { + case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR; + GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break; + + case dsk_SHKF: GpioCtrlRegs.GPADIR.all = VEPP_GPADIR; + GpioCtrlRegs.GPBDIR.all = VEPP_GPBDIR; break; + + case dsk_ISOL: GpioCtrlRegs.GPADIR.all = ISOL_GPADIR; + GpioCtrlRegs.GPBDIR.all = ISOL_GPBDIR; break; + } + EDIS; +} + +void get_Inputs() +{ + static long butthurt[2] ={0,0}; + unsigned long butt=0; + + if(Desk==dsk_COMM) + { + if(!GpioDataRegs.GPADAT.bit.GPIO7) butthurt[0]=0; + else if(butthurt[0] size) len=size; + + writeData.dataPtr = buf; + writeData.nrData = len; + writeData.se2pAddr = adres * WORD_LEN; + + spiSe2pWrite(&se2p, &writeData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +// diod2_off(); + +} + +void Seeprom_read( unsigned int adres, + unsigned int buf[], + unsigned int size) +{ + unsigned int len; + +// diod2_on(); + CpuTimer2.InterruptCount=0; + CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + + while(!spiSe2pFree(&se2p)); + + size = (size / WORD_LEN) + (size % WORD_LEN); + while(size) + { + len = PAGE_LEN - (adres % PAGE_LEN); + if(len > size) len=size; + + readData.dataPtr = buf; + readData.nrData = len; + readData.se2pAddr = adres * WORD_LEN; + + spiSe2pRead(&se2p, &readData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +// diod2_off(); +} + +void Init_Seeprom() +{ + se2p.init(&se2p); + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitCpuTimers(); // For this example, only initialize the Cpu Timers +// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100); +// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 10); + ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100); + + IER |= M_INT14; +} + +void SPISE2P_DRV_init(SPISE2P_DRV *eeprom) +{ +/* Configure SPI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SPI functional pins. +// Comment out other unwanted lines. + EALLOW; + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O) + GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output + GpioDataRegs.GPADAT.bit.GPIO19 = 0; + EDIS; + + /* Configure the SPI: 8-bit, Rising edge with delay */ + SpiaRegs.SPICCR.all=0x0007; + SpiaRegs.SPICTL.all=0x001F; + SpiaRegs.SPISTS.all=0x00; + + SpiaRegs.SPIBRR = (LSPCLK / SPIBAUD_RATE) - 1; + + SpiaRegs.SPIFFTX.all=0x8000; + SpiaRegs.SPIFFRX.all=0x0000; + SpiaRegs.SPIFFCT.all=0x00; + SpiaRegs.SPIPRI.all=0x0010; + + /* Disable Chip Select of Serial EEPROM */ + eeprom->csr=0; + eeprom->msgPtr=0; + + SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI +} + +void SPISE2P_DRV_csset() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 1; +} + +void SPISE2P_DRV_csclr() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 0; +} + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p) +{ + if(se2p->csr&0x3) return(0); + else return(1); +} + +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x1; +} + +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x2; +} + +/********************************************************************/ +/******* SPI bus Serial EEPROM driver Tick function *****************/ +/********************************************************************/ + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + + se2p.tick(&se2p); + + // The CPU acknowledges the interrupt. + EDIS; +} + +void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom) +{ + static unsigned int step=0; + static unsigned int dataCount=0; + static volatile unsigned int dummy=0; + + switch(step) + { + case 0: + /* If write request is SET, then trigger the Write operation + If read request is SET, then trigger the Read operation + If Read request is also not SET, then continue to poll */ + + if(eeprom->csr&SPISE2P_WRRQ) + { step=1; + eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/ + eeprom->csclr(); + } + + if(eeprom->csr&SPISE2P_RDRQ) + { step=13; + eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */ + eeprom->csclr(); + } + break; + + case 1: + /************************************************************ + *********** SPI bus EEPROM Write Starts from here *********** + ************************************************************* + Prier to any attempt to write data to SPI serial EEPROM + Write Enable Latch must be set by issuing the WREN command */ + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=2; + break; + + case 2: + /* Wait for VSPI State machine to send the WREN command and + serial EEPROM Chip Select must be brought to HIGH to set + the WREN latch */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + eeprom->csset(); + + step=3; + } + break; + + case 3: + /* Assert CS of Serial EEPROM and send WRITE command */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=4; + break; + + case 4: + /* Wait for VSPI State machine to send the WRITE command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=5; + } + break; + + case 5: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=6; + break; + + case 6: + /* Wait for VSPI State machine to send the Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=7; + } + break; + + case 7: + /* Send Data */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount); + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8; + #endif + + dataCount++; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=8; + break; + + case 8: + /* Wait for VSPI State machine to send the Data. + If all the data are sent, then set the CS pin to HIGH + to program or write the data in EEPROM array */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=9;} + else + step=7; /* Write next data */ + } + break; + + + case 9: + /* Read the EEPROM status register to check whether the + data sent are indeed programmed to the EEPROM array. + Hence, send RDSR command to EEPROM to read status reg. */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=10; + break; + + case 10: + /* Wait for VSPI State machine to send RDSR command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=11; + } + break; + + case 11: + /* Send dummy Data to read Status reg. */ + + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=12; + break; + + case 12: + /* Wait for VSPI State machine to clock out status reg. + Check, whether the data are written to the EEPROM array, + If written, then reset the WRIP(write in progress) and + WRRQ(Write request bit) and go back to STATE0 */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { eeprom->csset(); + + if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK ) + step=9; + else + { eeprom->csr&=(~SPISE2P_WRIP); + eeprom->csr&=(~SPISE2P_WRRQ); + step=0; + dataCount=0; + } + } + break; + + case 13: + /************************************************************ + *********** SPI bus EEPROM Read Starts from here *********** + ************************************************************* + Send READ Command to SPI bus serail EEPROM */ + + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_READ_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=14; + break; + + case 14: + /* Wait for VSPI State machine to send READ command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=15; + } + break; + + case 15: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=16; + break; + + case 16: + /* Wait for VSPI State machine to send Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=17; + } + break; + + case 17: + /* Send Dummy value to clock out data from serial EEPROM */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=18; + break; + + case 18: + /* Wait for VSPI State machine to clk out data from EEPROM */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF; + #endif + dataCount++; + step=19; + } + break; + + case 19: + /* If all the data are read, terminate the read operation by + rising the CS. Then reset the RDIP (Read in progress) bit + and reset the RDRQ(Read request) bit and go back to STATE0 */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=0; + dataCount=0; + eeprom->csr&=(~SPISE2P_RDIP); + eeprom->csr&=(~SPISE2P_RDRQ); + } + else + step=17; + break; + } +} + diff --git a/spise2p.h b/spise2p.h new file mode 100644 index 0000000..6cf27e4 --- /dev/null +++ b/spise2p.h @@ -0,0 +1,134 @@ +/*===================================================================== +File name : SPISE2P.H + +Originator : Settu Duraisamy + C2000 Applications Team + Texas Instruments + +Description : + Header file containing object definitions, proto type + declaration and default object initializers for + SPI Serial EEPROM driver using VSPI + +Date : 30/6/2003 (DD/MM/YYYY) +=======================================================================*/ + +#ifndef __SPISE2P_H__ + +#define __SPISE2P_H__ + +// +#define SEEPROM_LEN 0x10000 + +#define NULL 0 + +#define SIXTEEN_BIT 15 +#define EIGHT_BIT 07 + +/***************************************************************/ +/* Configurable Parameter for SPI bus Serial EEPROM */ +/***************************************************************/ +#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT +#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT +#define SPIBAUD_REG_VAL 1//12 +#define SPICLK_PHASE 1 +#define SPICLK_POLARITY 0 + +#define SPIBAUD_RATE 100000 +//10000000 + +/**************************************************************/ +/**************************************************************/ + +/* Serial EEPROM Command words, left justified */ +#define SPISE2P_READ_CMD 0x0300 +#define SPISE2P_WRITE_CMD 0x0200 +#define SPISE2P_WRDI_CMD 0x0400 +#define SPISE2P_WREN_CMD 0x0600 +#define SPISE2P_RDSR_CMD 0x0500 +#define SPISE2P_WRSR_CMD 0x0100 + +#define SPISE2P_RDID_CMD 0x0A00 + +#define SPISE2P_DUMMY_DATA 0x0000 +#define SPISE2P_BUSY_MASK 0x01 + +/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/ +#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT +#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT + +/* Status valus */ +#define SPISE2P_WRRQ 1 /* Write Requset */ +#define SPISE2P_RDRQ 2 /* Read request */ +#define SPISE2P_WRIP 4 /* Write in progress */ +#define SPISE2P_RDIP 8 /* Read in progress */ + +/* Message declaration */ +typedef struct { + unsigned int *dataPtr; /* Data pointer */ + unsigned long nrData; /* number of data */ + unsigned long se2pAddr; /* se2pAddr */ + }SE2P_DATA; + + +/* Object declaration */ +typedef struct { + SE2P_DATA *msgPtr; + unsigned int csr; /* control/status register */ + void (*init)(void *); + void (*tick)(void *); + void (*csset)(void); + void (*csclr)(void); + }SPISE2P_DRV; + +#define SPISE2P_DRV_DEFAULTS { NULL,\ + 0,\ + (void (*)(void *))SPISE2P_DRV_init,\ + (void (*)(void *))SPISE2P_DRV_tick,\ + (void (*)(void))SPISE2P_DRV_csset,\ + (void (*)(void))SPISE2P_DRV_csclr} + +typedef SPISE2P_DRV *SPISE2P_DRV_handle; + +void SPISE2P_DRV_init(SPISE2P_DRV * ); +void SPISE2P_DRV_tick(SPISE2P_DRV *); +void SPISE2P_DRV_csset(void); +void SPISE2P_DRV_csclr(void); + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p); +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data); +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data); + +#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + #define PROM_LEN 0x8000 + #define PAGE_LEN 0x20 + #define WORD_LEN 2 +#else + #define PROM_LEN 0x4000 + #define PAGE_LEN 0x40 + #define WORD_LEN 1 +#endif + +/* EEPROM. ** +** SPI . . ** +** 2! */ +void Init_Seeprom(void); + +/* SEEPROM. : ** +** adres - , . ** +** adres = 0..0x8000, 8 ** +** adres = 0..0x4000, 16 ** +** buf - , . ** +** size - . - ! */ +void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size); + +/* SEEPROM. : ** +** adres - , . ** +** adres = 0..0x8000, 8 ** +** adres = 0..0x4000, 16 ** +** buf - , . ** +** size - . - ! */ +void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size); + +#endif + diff --git a/test.c b/test.c new file mode 100644 index 0000000..5427b15 --- /dev/null +++ b/test.c @@ -0,0 +1,183 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "message.h" +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" +#include "test.h" +#include "kanal.h" +#include "peripher.h" + +WORDE PRES; + +int isMask = 1; +int isLamp = 0; +int isBrit = 0; +int isNumb = 1111; + +long cownt=0; + +unsigned int Light = 0xFFFF; + +int quaLamp = 6; + +void what_is() +{ + static int numb=0; + + if(keyTest) + { + if(keyNext & !preNext) + { + if(!isBrit) + { + isBrit=1; + isMask=1; + isLamp=0; + } + else + { + isMask<<=1; + + if(++isLamp >= quaLamp) + { + isMask=1; + isLamp=0; + } } } + + if(isBrit) + { + if(keyUp && !preUp) + if(Bright[isLamp]<10) Bright[isLamp]++; + + if(keyDown & !preDown) + if(Bright[isLamp]>0) Bright[isLamp]--; + } + else + { + if(cownt) cownt--; + else + { + cownt = BLN_FREQ/4; + + numb++; if(numb==10) numb=1; + isNumb = numb*1111; + + if(!isMask) isMask = 0xFFFF; + else isMask = 0; + } } } + + else + { + if(isBrit) + { + isBrit=0; + Save_params(); + } } + + PRES = KEYS; +} + + +interrupt void cpu_timer1_isr_PULT(void) +{ + static int count_bright=0; + unsigned int light=0, i; + static LONGE Diod1,Diod2; + static unsigned int Cownt,cownt; + int dig1,dig2; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + GpioDataRegs.GPATOGGLE.bit.GPIO0=1; // Ready + + if(count_bright) count_bright --; + else count_bright = 9; + for(i=0; i> 1; + + for (i = 0; i < t; i++) + { + DSP28x_usDelay(40L); +// powse=40L; +// for(powse=0; powse<40; powse++); + } +} + + diff --git a/tools.h b/tools.h new file mode 100644 index 0000000..2107dc4 --- /dev/null +++ b/tools.h @@ -0,0 +1,26 @@ +#ifndef TOOLS_H +#define TOOLS_H + +void init_zone7(void); + +void setup_leds_line(void); + +void pause_us(unsigned long t); + +#ifndef TUBER +#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1 +#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1 +#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1 +#else +#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led2_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#endif + +#endif //TOOLS_H diff --git a/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd new file mode 100644 index 0000000..b3707a7 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd @@ -0,0 +1,176 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:25 $ +//########################################################################### +// +// FILE: 28332_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28332 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28332 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd new file mode 100644 index 0000000..25f0fc9 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd @@ -0,0 +1,178 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: July 9, 2008 13:43:30 $ +//########################################################################### +// +// FILE: 28334_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28334 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28334 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd new file mode 100644 index 0000000..b469211 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd @@ -0,0 +1,176 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:36 $ +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/F28332.cmd b/v120/DSP2833x_common/cmd/F28332.cmd new file mode 100644 index 0000000..ecdc06e --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28332.cmd @@ -0,0 +1,197 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:41 $ +//########################################################################### +// +// FILE: F28332.cmd +// +// TITLE: Linker Command File For F28332 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ + +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/cmd/F28334.cmd b/v120/DSP2833x_common/cmd/F28334.cmd new file mode 100644 index 0000000..ec4d6c3 --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28334.cmd @@ -0,0 +1,203 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:49 $ +//########################################################################### +// +// FILE: F28334.cmd +// +// TITLE: Linker Command File For F28334 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */ + FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */ + FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */ + FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/cmd/F28335.cmd b/v120/DSP2833x_common/cmd/F28335.cmd new file mode 100644 index 0000000..b00d2a5 --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28335.cmd @@ -0,0 +1,203 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/gel/f28232.gel b/v120/DSP2833x_common/gel/f28232.gel new file mode 100644 index 0000000..9ad95bf --- /dev/null +++ b/v120/DSP2833x_common/gel/f28232.gel @@ -0,0 +1,2822 @@ +/********************************************************************/ +/* f28232.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28232 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28232_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28232 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28232 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x330000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28232_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28232_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28232 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28234.gel b/v120/DSP2833x_common/gel/f28234.gel new file mode 100644 index 0000000..cd5726a --- /dev/null +++ b/v120/DSP2833x_common/gel/f28234.gel @@ -0,0 +1,2930 @@ +/********************************************************************/ +/* f28234.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28234 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28234_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28234 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28234 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x320000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28234_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28234_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28234 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} + +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28235.gel b/v120/DSP2833x_common/gel/f28235.gel new file mode 100644 index 0000000..9d35fee --- /dev/null +++ b/v120/DSP2833x_common/gel/f28235.gel @@ -0,0 +1,2939 @@ +/********************************************************************/ +/* f28235.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28235 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); + +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28235_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28235 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28235 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */ +/* 0x300000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28235_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28235_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate."); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + + +} + + + + + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28235 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28332.gel b/v120/DSP2833x_common/gel/f28332.gel new file mode 100644 index 0000000..9a9d2fb --- /dev/null +++ b/v120/DSP2833x_common/gel/f28332.gel @@ -0,0 +1,2845 @@ +/********************************************************************/ +/* f28332.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28332 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28332_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28332 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28332 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x330000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28332_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28332_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28332 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28334.gel b/v120/DSP2833x_common/gel/f28334.gel new file mode 100644 index 0000000..fde0000 --- /dev/null +++ b/v120/DSP2833x_common/gel/f28334.gel @@ -0,0 +1,2951 @@ +/********************************************************************/ +/* f28334.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28334 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28334_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28334 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28334 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x320000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28334_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28334_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28334 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} + +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28335.gel b/v120/DSP2833x_common/gel/f28335.gel new file mode 100644 index 0000000..a3c37ec --- /dev/null +++ b/v120/DSP2833x_common/gel/f28335.gel @@ -0,0 +1,2960 @@ +/********************************************************************/ +/* f28335.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28335 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); + +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28335_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28335 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28335 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */ +/* 0x300000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28335_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28335_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate."); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + + +} + + + + + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28335 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..8919b97 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h @@ -0,0 +1,147 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// Non-Peripheral Interrupts: +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// Group 1 PIE Interrupt Service Routines: +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// Group 2 PIE Interrupt Service Routines: +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// Group 3 PIE Interrupt Service Routines: +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// Group 4 PIE Interrupt Service Routines: +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// Group 5 PIE Interrupt Service Routines: +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// Group 6 PIE Interrupt Service Routines: +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// Group 7 PIE Interrupt Service Routines: +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// Group 8 PIE Interrupt Service Routines: +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// Group 9 PIE Interrupt Service Routines: +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// Group 10 PIE Interrupt Service Routines: + +// Group 11 PIE Interrupt Service Routines: + +// Group 12 PIE Interrupt Service Routines: +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// Catch-all for Reserved Locations For testing purposes: +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..7b8dfaf --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h @@ -0,0 +1,81 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// MODE +//========================== +// PERINTSEL bits +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 +// OVERINTE bit +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 +// PERINTE bit +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 +// CHINTMODE bits +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 +// ONESHOT bits +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 +// CONTINOUS bit +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 +// SYNCE bit +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 +// SYNCSEL bit +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 +// DATASIZE bit +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 +// CHINTE bit +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h new file mode 100644 index 0000000..061842f --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h @@ -0,0 +1,164 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// TBCTL (Time-Base Control) +//========================== +// CTRMODE bits +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 +// PHSEN bit +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 +// PRDLD bit +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 +// SYNCOSEL bits +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 +// HSPCLKDIV and CLKDIV bits +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 +// PHSDIR bit +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// CMPCTL (Compare Control) +//========================== +// LOADAMODE and LOADBMODE bits +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 +// SHDWAMODE and SHDWBMODE bits +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// AQCTLA and AQCTLB (Action Qualifier Control) +//============================================= +// ZRO, PRD, CAU, CAD, CBU, CBD bits +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// DBCTL (Dead-Band Control) +//========================== +// OUT MODE bits +#define DB_DISABLE 0x0 +#define DBA_ENABLE 0x1 +#define DBB_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 +// POLSEL bits +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 +// IN MODE +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// CHPCTL (chopper control) +//========================== +// CHPEN bit +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 +// CHPFREQ bits +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 +// CHPDUTY bits +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// TZSEL (Trip Zone Select) +//========================== +// CBCn and OSHTn bits +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// TZCTL (Trip Zone Control) +//========================== +// TZA and TZB bits +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// ETSEL (Event Trigger Select) +//============================= +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// ETPS (Event Trigger Pre-scale) +//=============================== +// INTPRD, SOCAPRD, SOCBPRD bits +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + + +//-------------------------------- +// HRPWM (High Resolution PWM) +//================================ +// HRCNFG +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_Examples.h b/v120/DSP2833x_common/include/DSP2833x_Examples.h new file mode 100644 index 0000000..c38ebb1 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_Examples.h @@ -0,0 +1,141 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------- + Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +-----------------------------------------------------------------------------*/ +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode +//---------------------------------------------------------------------------- + + +/*----------------------------------------------------------------------------- + Specify the clock rate of the CPU (SYSCLKOUT) in nS. + + Take into account the input clock frequency and the PLL multiplier + selected in step 1. + + Use one of the values provided, or define your own. + The trailing L is required tells the compiler to treat + the number as a 64-bit value. + + Only one statement should be uncommented. + + Example 1:150 MHz devices: + CLKIN is a 30MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 150Mhz CPU clock (SYSCLKOUT = 150MHz). + + In this case, the CPU_RATE will be 6.667L + Uncomment the line: #define CPU_RATE 6.667L + + Example 2: 100 MHz devices: + CLKIN is a 20MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 100Mhz CPU clock (SYSCLKOUT = 100MHz). + + In this case, the CPU_RATE will be 10.000L + Uncomment the line: #define CPU_RATE 10.000L +-----------------------------------------------------------------------------*/ +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +//---------------------------------------------------------------------------- + +/*----------------------------------------------------------------------------- + Target device (in DSP2833x_Device.h) determines CPU frequency + (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz + (for 28332). User does not have to change anything here. +-----------------------------------------------------------------------------*/ +#if DSP28_28332 // DSP28_28332 device only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + + +//--------------------------------------------------------------------------- +// Include Example Header Files: +// + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + // .c files. + +#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28332 0xED +#define PARTNO_28235 0xE8 +#define PARTNO_28234 0xE7 +#define PARTNO_28232 0xE6 + + +// Include files not used with DSP/BIOS +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultISR.h" +#endif + + +// DO NOT MODIFY THIS LINE. +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h new file mode 100644 index 0000000..9c90607 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h @@ -0,0 +1,207 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---- shared global function prototypes -----------------------------------*/ +extern void InitAdc(void); + +extern void DMAInitialize(void); +// DMA Channel 1 +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH1(void); +// DMA Channel 2 +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH2(void); +// DMA Channel 3 +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH3(void); +// DMA Channel 4 +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH4(void); +// DMA Channel 5 +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH5(void); +// DMA Channel 6 +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// DSP28_DBGIER.asm +extern void SetDBGIER(Uint16 dbgier); + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +extern void InitFlash(void); + + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + + +//--------------------------------------------------------------------------- +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h new file mode 100644 index 0000000..ce3f1f7 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h @@ -0,0 +1,117 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +//-------------------------------------------- +// Defines +//-------------------------------------------- + +// Error Messages +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// Clear Status Flags +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// Interrupt Source Messages +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// I2CMSG structure defines +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// I2C Slave State defines +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// I2C Slave Receiver messages defines +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// I2C State defines +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// I2C Message Commands for I2CMSG struct +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// Generic defines +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +//-------------------------------------------- +// Structures +//-------------------------------------------- + +// I2C Message Structure +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000..c3f3ea1 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h @@ -0,0 +1,5850 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:21 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedIsrLevels.h +// +// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SW_PRIORITZIED_ISR_H +#define DSP2833x_SW_PRIORITZIED_ISR_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//------------------------------------------------------------------------------- +// Interrupt Enable Register Allocation For 2833x Devices: +//------------------------------------------------------------------------------- +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +//------------------------------------------------------------------------------- +//------------------------------------------------------------------------------- +// Set "Global" Interrupt Priority Level (IER register): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 0 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 0 // reserved +#define INT8PL 0 // reserved +#define INT9PL 1 // Group9 Interrupts (PIEIER9) +#define INT10PL 0 // reserved +#define INT11PL 0 // reserved +#define INT12PL 0 // reserved +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +//------------------------------------------------------------------------------- +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 8 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG11 to MG18 +// MG21 to MG28 +// MG31 to MG38 +// MG41 to MG48 +// MG51 to MG58 +// MG61 to MG68 +// MG71 to MG78 +// MG81 to MG88 +// MG91 to MG98 +// MG101 to MG108 +// MG111 to MG118 +// MG121 to MG128 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 8 = lowest priority +// +#define G11PL 7 // SEQ1INT (ADC) +#define G12PL 6 // SEQ2INT (ADC) +#define G13PL 0 // reserved +#define G14PL 1 // XINT1 (External) +#define G15PL 3 // XINT2 (External) +#define G16PL 2 // ADCINT (ADC) +#define G17PL 1 // TINT0 (CPU Timer 0) +#define G18PL 5 // WAKEINT (WD/LPM) + +#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip) +#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip) +#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip) +#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip) +#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip) +#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip) +#define G27PL 0 // reserved +#define G28PL 0 // reserved + +#define G31PL 4 // EPWM1_INT (ePWM1 Int) +#define G32PL 1 // EPWM2_INT (ePWM2 Int) +#define G33PL 1 // EPWM3_INT (ePWM3 Int) +#define G34PL 2 // EPWM4_INT (ePWM4 Int) +#define G35PL 2 // EPWM5_INT (ePWM5 Int) +#define G36PL 1 // EPWM6_INT (ePWM6 Int) +#define G37PL 0 // reserved +#define G38PL 0 // reserved + +#define G41PL 2 // ECAP1_INT (eCAP1 Int) +#define G42PL 1 // ECAP2_INT (eCAP2 Int) +#define G43PL 3 // ECAP3_INT (eCAP3 Int) +#define G44PL 3 // ECAP4_INT (eCAP4 Int) +#define G45PL 5 // ECAP5_INT (eCAP5 Int) +#define G46PL 5 // ECAP6_INT (eCAP6 Int) +#define G47PL 0 // reserved +#define G48PL 0 // reserved + +#define G51PL 2 // EQEP1_INT (eQEP1 Int) +#define G52PL 1 // EQEP2_INT (eQEP2 Int) +#define G53PL 0 // reserved +#define G54PL 0 // reserved +#define G55PL 0 // reserved +#define G56PL 0 // reserved +#define G57PL 0 // reserved +#define G58PL 0 // reserved + +#define G61PL 3 // SPIRXINTA (SPI-A) +#define G62PL 1 // SPITXINTA (SPI-A) +#define G63PL 4 // MRINTB (McBSP-B) +#define G64PL 6 // MXINTB (McBSP-B) +#define G65PL 2 // MRINTA (McBSP-A) +#define G66PL 1 // MXINTA (McBSP-A) +#define G67PL 0 // reserved +#define G68PL 0 // reserved + +#define G71PL 5 // DINTCH1 (DMA) +#define G72PL 4 // DINTCH2 (DMA) +#define G73PL 4 // DINTCH3 (DMA) +#define G74PL 2 // DINTCH4 (DMA) +#define G75PL 3 // DINTCH5 (DMA) +#define G76PL 1 // DINTCH6 (DMA) +#define G77PL 0 // reserved +#define G78PL 0 // reserved + +#define G81PL 1 // I2CINT1A (I2C-A) +#define G82PL 2 // I2CINT2A (I2C-A) +#define G83PL 0 // reserved +#define G84PL 0 // reserved +#define G85PL 4 // SCIRXINTC (SCI-C) +#define G86PL 3 // SCITXINTC (SCI-C) +#define G87PL 0 // reserved +#define G88PL 0 // reserved + +#define G91PL 1 // SCIRXINTA (SCI-A) +#define G92PL 5 // SCITXINTA (SCI-A) +#define G93PL 3 // SCIRXINTB (SCI-B) +#define G94PL 4 // SCITXINTB (SCI-B) +#define G95PL 1 // ECAN0INTA (ECAN-A) +#define G96PL 1 // ECAN1INTA (ECAN-A) +#define G97PL 2 // ECAN0INTB (ECAN-B) +#define G98PL 4 // ECAN1INTB (ECAN-B) + +#define G101PL 0 // reserved +#define G102PL 0 // reserved +#define G103PL 0 // reserved +#define G104PL 0 // reserved +#define G105PL 0 // reserved +#define G106PL 0 // reserved +#define G107PL 0 // reserved +#define G108PL 0 // reserved + +#define G111PL 0 // reserved +#define G112PL 0 // reserved +#define G113PL 0 // reserved +#define G114PL 0 // reserved +#define G115PL 0 // reserved +#define G116PL 0 // reserved +#define G117PL 0 // reserved +#define G118PL 0 // reserved + +#define G121PL 5 // XINT3 (External) +#define G122PL 3 // XINT4 (External) +#define G123PL 2 // XINT5 (External) +#define G124PL 2 // XINT6 (External) +#define G125PL 1 // XINT7 (External) +#define G126PL 0 // reserved +#define G127PL 6 // LVF (FPA32) +#define G128PL 1 // LUF (FPA32) + + +// There should be no need to modify code below this line +//------------------------------------------------------------------------------- +// Automatically generate IER interrupt masks MINT1 to MINT16: +// + +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#define MINT13_12PL ~(1 << 11) + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG11 to MG18: + +// Beginning of MG11: +#if (G12PL >= G11PL) || (G12PL == 0) +#define MG11_12PL ~(1 << 1) +#else +#define MG11_12PL 0xFFFF +#endif + +#if (G13PL >= G11PL) || (G13PL == 0) +#define MG11_13PL ~(1 << 2) +#else +#define MG11_13PL 0xFFFF +#endif + +#if (G14PL >= G11PL) || (G14PL == 0) +#define MG11_14PL ~(1 << 3) +#else +#define MG11_14PL 0xFFFF +#endif + +#if (G15PL >= G11PL) || (G15PL == 0) +#define MG11_15PL ~(1 << 4) +#else +#define MG11_15PL 0xFFFF +#endif + +#if (G16PL >= G11PL) || (G16PL == 0) +#define MG11_16PL ~(1 << 5) +#else +#define MG11_16PL 0xFFFF +#endif + +#if (G17PL >= G11PL) || (G17PL == 0) +#define MG11_17PL ~(1 << 6) +#else +#define MG11_17PL 0xFFFF +#endif + +#if (G18PL >= G11PL) || (G18PL == 0) +#define MG11_18PL ~(1 << 7) +#else +#define MG11_18PL 0xFFFF +#endif + +#define MG11_11PL 0x00FE +#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \ + MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL) +// End of MG11: + +// Beginning of MG12: +#if (G11PL >= G12PL) || (G11PL == 0) +#define MG12_11PL ~(1) +#else +#define MG12_11PL 0xFFFF +#endif +#if (G13PL >= G12PL) || (G13PL == 0) +#define MG12_13PL ~(1 << 2) +#else +#define MG12_13PL 0xFFFF +#endif +#if (G14PL >= G12PL) || (G14PL == 0) +#define MG12_14PL ~(1 << 3) +#else +#define MG12_14PL 0xFFFF +#endif +#if (G15PL >= G12PL) || (G15PL == 0) +#define MG12_15PL ~(1 << 4) +#else +#define MG12_15PL 0xFFFF +#endif +#if (G16PL >= G12PL) || (G16PL == 0) +#define MG12_16PL ~(1 << 5) +#else +#define MG12_16PL 0xFFFF +#endif +#if (G17PL >= G12PL) || (G17PL == 0) +#define MG12_17PL ~(1 << 6) +#else +#define MG12_17PL 0xFFFF +#endif +#if (G18PL >= G12PL) || (G18PL == 0) +#define MG12_18PL ~(1 << 7) +#else +#define MG12_18PL 0xFFFF +#endif +#define MG12_12PL 0x00FD +#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \ + MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL) +// End of MG12: + +// Beginning of MG13: +#if (G11PL >= G13PL) || (G11PL == 0) +#define MG13_11PL ~(1) +#else +#define MG13_11PL 0xFFFF +#endif +#if (G12PL >= G13PL) || (G12PL == 0) +#define MG13_12PL ~(1 << 1) +#else +#define MG13_12PL 0xFFFF +#endif +#if (G14PL >= G13PL) || (G14PL == 0) +#define MG13_14PL ~(1 << 3) +#else +#define MG13_14PL 0xFFFF +#endif +#if (G15PL >= G13PL) || (G15PL == 0) +#define MG13_15PL ~(1 << 4) +#else +#define MG13_15PL 0xFFFF +#endif +#if (G16PL >= G13PL) || (G16PL == 0) +#define MG13_16PL ~(1 << 5) +#else +#define MG13_16PL 0xFFFF +#endif +#if (G17PL >= G13PL) || (G17PL == 0) +#define MG13_17PL ~(1 << 6) +#else +#define MG13_17PL 0xFFFF +#endif +#if (G18PL >= G13PL) || (G18PL == 0) +#define MG13_18PL ~(1 << 7) +#else +#define MG13_18PL 0xFFFF +#endif +#define MG13_13PL 0x00FB +#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \ + MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL) +// End of MG13: + +// Beginning of MG14: +#if (G11PL >= G14PL) || (G11PL == 0) +#define MG14_11PL ~(1) +#else +#define MG14_11PL 0xFFFF +#endif +#if (G12PL >= G14PL) || (G12PL == 0) +#define MG14_12PL ~(1 << 1) +#else +#define MG14_12PL 0xFFFF +#endif +#if (G13PL >= G14PL) || (G13PL == 0) +#define MG14_13PL ~(1 << 2) +#else +#define MG14_13PL 0xFFFF +#endif +#if (G15PL >= G14PL) || (G15PL == 0) +#define MG14_15PL ~(1 << 4) +#else +#define MG14_15PL 0xFFFF +#endif +#if (G16PL >= G14PL) || (G16PL == 0) +#define MG14_16PL ~(1 << 5) +#else +#define MG14_16PL 0xFFFF +#endif +#if (G17PL >= G14PL) || (G17PL == 0) +#define MG14_17PL ~(1 << 6) +#else +#define MG14_17PL 0xFFFF +#endif +#if (G18PL >= G14PL) || (G18PL == 0) +#define MG14_18PL ~(1 << 7) +#else +#define MG14_18PL 0xFFFF +#endif +#define MG14_14PL 0x00F7 +#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \ + MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL) +// End of MG14: + +// Beginning of MG15: +#if (G11PL >= G15PL) || (G11PL == 0) +#define MG15_11PL ~(1) +#else +#define MG15_11PL 0xFFFF +#endif +#if (G12PL >= G15PL) || (G12PL == 0) +#define MG15_12PL ~(1 << 1) +#else +#define MG15_12PL 0xFFFF +#endif +#if (G13PL >= G15PL) || (G13PL == 0) +#define MG15_13PL ~(1 << 2) +#else +#define MG15_13PL 0xFFFF +#endif +#if (G14PL >= G15PL) || (G14PL == 0) +#define MG15_14PL ~(1 << 3) +#else +#define MG15_14PL 0xFFFF +#endif +#if (G16PL >= G15PL) || (G16PL == 0) +#define MG15_16PL ~(1 << 5) +#else +#define MG15_16PL 0xFFFF +#endif +#if (G17PL >= G15PL) || (G17PL == 0) +#define MG15_17PL ~(1 << 6) +#else +#define MG15_17PL 0xFFFF +#endif +#if (G18PL >= G15PL) || (G18PL == 0) +#define MG15_18PL ~(1 << 7) +#else +#define MG15_18PL 0xFFFF +#endif +#define MG15_15PL 0x00EF +#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \ + MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL) +// End of MG15: + +// Beginning of MG16: +#if (G11PL >= G16PL) || (G11PL == 0) +#define MG16_11PL ~(1) +#else +#define MG16_11PL 0xFFFF +#endif +#if (G12PL >= G16PL) || (G12PL == 0) +#define MG16_12PL ~(1 << 1) +#else +#define MG16_12PL 0xFFFF +#endif +#if (G13PL >= G16PL) || (G13PL == 0) +#define MG16_13PL ~(1 << 2) +#else +#define MG16_13PL 0xFFFF +#endif +#if (G14PL >= G16PL) || (G14PL == 0) +#define MG16_14PL ~(1 << 3) +#else +#define MG16_14PL 0xFFFF +#endif +#if (G15PL >= G16PL) || (G15PL == 0) +#define MG16_15PL ~(1 << 4) +#else +#define MG16_15PL 0xFFFF +#endif +#if (G17PL >= G16PL) || (G17PL == 0) +#define MG16_17PL ~(1 << 6) +#else +#define MG16_17PL 0xFFFF +#endif +#if (G18PL >= G16PL) || (G18PL == 0) +#define MG16_18PL ~(1 << 7) +#else +#define MG16_18PL 0xFFFF +#endif +#define MG16_16PL 0x00DF +#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \ + MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL) +// End of MG16: + +// Beginning of MG17: +#if (G11PL >= G17PL) || (G11PL == 0) +#define MG17_11PL ~(1) +#else +#define MG17_11PL 0xFFFF +#endif +#if (G12PL >= G17PL) || (G12PL == 0) +#define MG17_12PL ~(1 << 1) +#else +#define MG17_12PL 0xFFFF +#endif +#if (G13PL >= G17PL) || (G13PL == 0) +#define MG17_13PL ~(1 << 2) +#else +#define MG17_13PL 0xFFFF +#endif +#if (G14PL >= G17PL) || (G14PL == 0) +#define MG17_14PL ~(1 << 3) +#else +#define MG17_14PL 0xFFFF +#endif +#if (G15PL >= G17PL) || (G15PL == 0) +#define MG17_15PL ~(1 << 4) +#else +#define MG17_15PL 0xFFFF +#endif +#if (G16PL >= G17PL) || (G16PL == 0) +#define MG17_16PL ~(1 << 5) +#else +#define MG17_16PL 0xFFFF +#endif +#if (G18PL >= G17PL) || (G18PL == 0) +#define MG17_18PL ~(1 << 7) +#else +#define MG17_18PL 0xFFFF +#endif +#define MG17_17PL 0x00BF +#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \ + MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL) +// End of MG17: + +// Beginning of MG18: +#if (G11PL >= G18PL) || (G11PL == 0) +#define MG18_11PL ~(1) +#else +#define MG18_11PL 0xFFFF +#endif +#if (G12PL >= G18PL) || (G12PL == 0) +#define MG18_12PL ~(1 << 1) +#else +#define MG18_12PL 0xFFFF +#endif +#if (G13PL >= G18PL) || (G13PL == 0) +#define MG18_13PL ~(1 << 2) +#else +#define MG18_13PL 0xFFFF +#endif +#if (G14PL >= G18PL) || (G14PL == 0) +#define MG18_14PL ~(1 << 3) +#else +#define MG18_14PL 0xFFFF +#endif +#if (G15PL >= G18PL) || (G15PL == 0) +#define MG18_15PL ~(1 << 4) +#else +#define MG18_15PL 0xFFFF +#endif +#if (G16PL >= G18PL) || (G16PL == 0) +#define MG18_16PL ~(1 << 5) +#else +#define MG18_16PL 0xFFFF +#endif +#if (G17PL >= G18PL) || (G17PL == 0) +#define MG18_17PL ~(1 << 6) +#else +#define MG18_17PL 0xFFFF +#endif +#define MG18_18PL 0x007F +#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \ + MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL) +// End of MG18: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG21 to MG28: +// + +// Beginning of MG21: +#if (G22PL >= G21PL) || (G22PL == 0) +#define MG21_12PL ~(1 << 1) +#else +#define MG21_12PL 0xFFFF +#endif +#if (G23PL >= G21PL) || (G23PL == 0) +#define MG21_13PL ~(1 << 2) +#else +#define MG21_13PL 0xFFFF +#endif +#if (G24PL >= G21PL) || (G24PL == 0) +#define MG21_14PL ~(1 << 3) +#else +#define MG21_14PL 0xFFFF +#endif +#if (G25PL >= G21PL) || (G25PL == 0) +#define MG21_15PL ~(1 << 4) +#else +#define MG21_15PL 0xFFFF +#endif +#if (G26PL >= G21PL) || (G26PL == 0) +#define MG21_16PL ~(1 << 5) +#else +#define MG21_16PL 0xFFFF +#endif +#if (G27PL >= G21PL) || (G27PL == 0) +#define MG21_17PL ~(1 << 6) +#else +#define MG21_17PL 0xFFFF +#endif +#if (G28PL >= G21PL) || (G28PL == 0) +#define MG21_18PL ~(1 << 7) +#else +#define MG21_18PL 0xFFFF +#endif +#define MG21_11PL 0x00FE +#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \ + MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL) +// End of MG21: + +// Beginning of MG22: +#if (G21PL >= G22PL) || (G21PL == 0) +#define MG22_11PL ~(1) +#else +#define MG22_11PL 0xFFFF +#endif +#if (G23PL >= G22PL) || (G23PL == 0) +#define MG22_13PL ~(1 << 2) +#else +#define MG22_13PL 0xFFFF +#endif +#if (G24PL >= G22PL) || (G24PL == 0) +#define MG22_14PL ~(1 << 3) +#else +#define MG22_14PL 0xFFFF +#endif +#if (G25PL >= G22PL) || (G25PL == 0) +#define MG22_15PL ~(1 << 4) +#else +#define MG22_15PL 0xFFFF +#endif +#if (G26PL >= G22PL) || (G26PL == 0) +#define MG22_16PL ~(1 << 5) +#else +#define MG22_16PL 0xFFFF +#endif +#if (G27PL >= G22PL) || (G27PL == 0) +#define MG22_17PL ~(1 << 6) +#else +#define MG22_17PL 0xFFFF +#endif +#if (G28PL >= G22PL) || (G28PL == 0) +#define MG22_18PL ~(1 << 7) +#else +#define MG22_18PL 0xFFFF +#endif +#define MG22_12PL 0x00FD +#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \ + MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL) +// End of MG22: + +// Beginning of MG23: +#if (G21PL >= G23PL) || (G21PL == 0) +#define MG23_11PL ~(1) +#else +#define MG23_11PL 0xFFFF +#endif +#if (G22PL >= G23PL) || (G22PL == 0) +#define MG23_12PL ~(1 << 1) +#else +#define MG23_12PL 0xFFFF +#endif +#if (G24PL >= G23PL) || (G24PL == 0) +#define MG23_14PL ~(1 << 3) +#else +#define MG23_14PL 0xFFFF +#endif +#if (G25PL >= G23PL) || (G25PL == 0) +#define MG23_15PL ~(1 << 4) +#else +#define MG23_15PL 0xFFFF +#endif +#if (G26PL >= G23PL) || (G26PL == 0) +#define MG23_16PL ~(1 << 5) +#else +#define MG23_16PL 0xFFFF +#endif +#if (G27PL >= G23PL) || (G27PL == 0) +#define MG23_17PL ~(1 << 6) +#else +#define MG23_17PL 0xFFFF +#endif +#if (G28PL >= G23PL) || (G28PL == 0) +#define MG23_18PL ~(1 << 7) +#else +#define MG23_18PL 0xFFFF +#endif +#define MG23_13PL 0x00FB +#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \ + MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL) +// End of MG23: + +// Beginning of MG24: +#if (G21PL >= G24PL) || (G21PL == 0) +#define MG24_11PL ~(1) +#else +#define MG24_11PL 0xFFFF +#endif +#if (G22PL >= G24PL) || (G22PL == 0) +#define MG24_12PL ~(1 << 1) +#else +#define MG24_12PL 0xFFFF +#endif +#if (G23PL >= G24PL) || (G23PL == 0) +#define MG24_13PL ~(1 << 2) +#else +#define MG24_13PL 0xFFFF +#endif +#if (G25PL >= G24PL) || (G25PL == 0) +#define MG24_15PL ~(1 << 4) +#else +#define MG24_15PL 0xFFFF +#endif +#if (G26PL >= G24PL) || (G26PL == 0) +#define MG24_16PL ~(1 << 5) +#else +#define MG24_16PL 0xFFFF +#endif +#if (G27PL >= G24PL) || (G27PL == 0) +#define MG24_17PL ~(1 << 6) +#else +#define MG24_17PL 0xFFFF +#endif +#if (G28PL >= G24PL) || (G28PL == 0) +#define MG24_18PL ~(1 << 7) +#else +#define MG24_18PL 0xFFFF +#endif +#define MG24_14PL 0x00F7 +#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \ + MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL) +// End of MG24: + +// Beginning of MG25: +#if (G21PL >= G25PL) || (G21PL == 0) +#define MG25_11PL ~(1) +#else +#define MG25_11PL 0xFFFF +#endif +#if (G22PL >= G25PL) || (G22PL == 0) +#define MG25_12PL ~(1 << 1) +#else +#define MG25_12PL 0xFFFF +#endif +#if (G23PL >= G25PL) || (G23PL == 0) +#define MG25_13PL ~(1 << 2) +#else +#define MG25_13PL 0xFFFF +#endif +#if (G24PL >= G25PL) || (G24PL == 0) +#define MG25_14PL ~(1 << 3) +#else +#define MG25_14PL 0xFFFF +#endif +#if (G26PL >= G25PL) || (G26PL == 0) +#define MG25_16PL ~(1 << 5) +#else +#define MG25_16PL 0xFFFF +#endif +#if (G27PL >= G25PL) || (G27PL == 0) +#define MG25_17PL ~(1 << 6) +#else +#define MG25_17PL 0xFFFF +#endif +#if (G28PL >= G25PL) || (G28PL == 0) +#define MG25_18PL ~(1 << 7) +#else +#define MG25_18PL 0xFFFF +#endif +#define MG25_15PL 0x00EF +#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \ + MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL) +// End of MG25: + +// Beginning of MG26: +#if (G21PL >= G26PL) || (G21PL == 0) +#define MG26_11PL ~(1) +#else +#define MG26_11PL 0xFFFF +#endif +#if (G22PL >= G26PL) || (G22PL == 0) +#define MG26_12PL ~(1 << 1) +#else +#define MG26_12PL 0xFFFF +#endif +#if (G23PL >= G26PL) || (G23PL == 0) +#define MG26_13PL ~(1 << 2) +#else +#define MG26_13PL 0xFFFF +#endif +#if (G24PL >= G26PL) || (G24PL == 0) +#define MG26_14PL ~(1 << 3) +#else +#define MG26_14PL 0xFFFF +#endif +#if (G25PL >= G26PL) || (G25PL == 0) +#define MG26_15PL ~(1 << 4) +#else +#define MG26_15PL 0xFFFF +#endif +#if (G27PL >= G26PL) || (G27PL == 0) +#define MG26_17PL ~(1 << 6) +#else +#define MG26_17PL 0xFFFF +#endif +#if (G28PL >= G26PL) || (G28PL == 0) +#define MG26_18PL ~(1 << 7) +#else +#define MG26_18PL 0xFFFF +#endif +#define MG26_16PL 0x00DF +#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \ + MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL) +// End of MG26: + +// Beginning of MG27: +#if (G21PL >= G27PL) || (G21PL == 0) +#define MG27_11PL ~(1) +#else +#define MG27_11PL 0xFFFF +#endif +#if (G22PL >= G27PL) || (G22PL == 0) +#define MG27_12PL ~(1 << 1) +#else +#define MG27_12PL 0xFFFF +#endif +#if (G23PL >= G27PL) || (G23PL == 0) +#define MG27_13PL ~(1 << 2) +#else +#define MG27_13PL 0xFFFF +#endif +#if (G24PL >= G27PL) || (G24PL == 0) +#define MG27_14PL ~(1 << 3) +#else +#define MG27_14PL 0xFFFF +#endif +#if (G25PL >= G27PL) || (G25PL == 0) +#define MG27_15PL ~(1 << 4) +#else +#define MG27_15PL 0xFFFF +#endif +#if (G26PL >= G27PL) || (G26PL == 0) +#define MG27_16PL ~(1 << 5) +#else +#define MG27_16PL 0xFFFF +#endif +#if (G28PL >= G27PL) || (G28PL == 0) +#define MG27_18PL ~(1 << 7) +#else +#define MG27_18PL 0xFFFF +#endif +#define MG27_17PL 0x00BF +#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \ + MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL) +// End of MG27: + +// Beginning of MG28: +#if (G21PL >= G28PL) || (G21PL == 0) +#define MG28_11PL ~(1) +#else +#define MG28_11PL 0xFFFF +#endif +#if (G22PL >= G28PL) || (G22PL == 0) +#define MG28_12PL ~(1 << 1) +#else +#define MG28_12PL 0xFFFF +#endif +#if (G23PL >= G28PL) || (G23PL == 0) +#define MG28_13PL ~(1 << 2) +#else +#define MG28_13PL 0xFFFF +#endif +#if (G24PL >= G28PL) || (G24PL == 0) +#define MG28_14PL ~(1 << 3) +#else +#define MG28_14PL 0xFFFF +#endif +#if (G25PL >= G28PL) || (G25PL == 0) +#define MG28_15PL ~(1 << 4) +#else +#define MG28_15PL 0xFFFF +#endif +#if (G26PL >= G28PL) || (G26PL == 0) +#define MG28_16PL ~(1 << 5) +#else +#define MG28_16PL 0xFFFF +#endif +#if (G27PL >= G28PL) || (G27PL == 0) +#define MG28_17PL ~(1 << 6) +#else +#define MG28_17PL 0xFFFF +#endif +#define MG28_18PL 0x007F +#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \ + MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL) +// End of MG28: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG31 to MG38: +// + +// Beginning of MG31: +#if (G32PL >= G31PL) || (G32PL == 0) +#define MG31_12PL ~(1 << 1) +#else +#define MG31_12PL 0xFFFF +#endif +#if (G33PL >= G31PL) || (G33PL == 0) +#define MG31_13PL ~(1 << 2) +#else +#define MG31_13PL 0xFFFF +#endif +#if (G34PL >= G31PL) || (G34PL == 0) +#define MG31_14PL ~(1 << 3) +#else +#define MG31_14PL 0xFFFF +#endif +#if (G35PL >= G31PL) || (G35PL == 0) +#define MG31_15PL ~(1 << 4) +#else +#define MG31_15PL 0xFFFF +#endif +#if (G36PL >= G31PL) || (G36PL == 0) +#define MG31_16PL ~(1 << 5) +#else +#define MG31_16PL 0xFFFF +#endif +#if (G37PL >= G31PL) || (G37PL == 0) +#define MG31_17PL ~(1 << 6) +#else +#define MG31_17PL 0xFFFF +#endif +#if (G38PL >= G31PL) || (G38PL == 0) +#define MG31_18PL ~(1 << 7) +#else +#define MG31_18PL 0xFFFF +#endif +#define MG31_11PL 0x00FE +#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \ + MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL) +// End of MG31: + +// Beginning of MG32: +#if (G31PL >= G32PL) || (G31PL == 0) +#define MG32_11PL ~(1) +#else +#define MG32_11PL 0xFFFF +#endif +#if (G33PL >= G32PL) || (G33PL == 0) +#define MG32_13PL ~(1 << 2) +#else +#define MG32_13PL 0xFFFF +#endif +#if (G34PL >= G32PL) || (G34PL == 0) +#define MG32_14PL ~(1 << 3) +#else +#define MG32_14PL 0xFFFF +#endif +#if (G35PL >= G32PL) || (G35PL == 0) +#define MG32_15PL ~(1 << 4) +#else +#define MG32_15PL 0xFFFF +#endif +#if (G36PL >= G32PL) || (G36PL == 0) +#define MG32_16PL ~(1 << 5) +#else +#define MG32_16PL 0xFFFF +#endif +#if (G37PL >= G32PL) || (G37PL == 0) +#define MG32_17PL ~(1 << 6) +#else +#define MG32_17PL 0xFFFF +#endif +#if (G38PL >= G32PL) || (G38PL == 0) +#define MG32_18PL ~(1 << 7) +#else +#define MG32_18PL 0xFFFF +#endif +#define MG32_12PL 0x00FD +#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \ + MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL) +// End of MG32: + +// Beginning of MG33: +#if (G31PL >= G33PL) || (G31PL == 0) +#define MG33_11PL ~(1) +#else +#define MG33_11PL 0xFFFF +#endif +#if (G32PL >= G33PL) || (G32PL == 0) +#define MG33_12PL ~(1 << 1) +#else +#define MG33_12PL 0xFFFF +#endif +#if (G34PL >= G33PL) || (G34PL == 0) +#define MG33_14PL ~(1 << 3) +#else +#define MG33_14PL 0xFFFF +#endif +#if (G35PL >= G33PL) || (G35PL == 0) +#define MG33_15PL ~(1 << 4) +#else +#define MG33_15PL 0xFFFF +#endif +#if (G36PL >= G33PL) || (G36PL == 0) +#define MG33_16PL ~(1 << 5) +#else +#define MG33_16PL 0xFFFF +#endif +#if (G37PL >= G33PL) || (G37PL == 0) +#define MG33_17PL ~(1 << 6) +#else +#define MG33_17PL 0xFFFF +#endif +#if (G38PL >= G33PL) || (G38PL == 0) +#define MG33_18PL ~(1 << 7) +#else +#define MG33_18PL 0xFFFF +#endif +#define MG33_13PL 0x00FB +#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \ + MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL) +// End of MG33: + +// Beginning of MG34: +#if (G31PL >= G34PL) || (G31PL == 0) +#define MG34_11PL ~(1) +#else +#define MG34_11PL 0xFFFF +#endif +#if (G32PL >= G34PL) || (G32PL == 0) +#define MG34_12PL ~(1 << 1) +#else +#define MG34_12PL 0xFFFF +#endif +#if (G33PL >= G34PL) || (G33PL == 0) +#define MG34_13PL ~(1 << 2) +#else +#define MG34_13PL 0xFFFF +#endif +#if (G35PL >= G34PL) || (G35PL == 0) +#define MG34_15PL ~(1 << 4) +#else +#define MG34_15PL 0xFFFF +#endif +#if (G36PL >= G34PL) || (G36PL == 0) +#define MG34_16PL ~(1 << 5) +#else +#define MG34_16PL 0xFFFF +#endif +#if (G37PL >= G34PL) || (G37PL == 0) +#define MG34_17PL ~(1 << 6) +#else +#define MG34_17PL 0xFFFF +#endif +#if (G38PL >= G34PL) || (G38PL == 0) +#define MG34_18PL ~(1 << 7) +#else +#define MG34_18PL 0xFFFF +#endif +#define MG34_14PL 0x00F7 +#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \ + MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL) +// End of MG34: + +// Beginning of MG35: +#if (G31PL >= G35PL) || (G31PL == 0) +#define MG35_11PL ~(1) +#else +#define MG35_11PL 0xFFFF +#endif +#if (G32PL >= G35PL) || (G32PL == 0) +#define MG35_12PL ~(1 << 1) +#else +#define MG35_12PL 0xFFFF +#endif +#if (G33PL >= G35PL) || (G33PL == 0) +#define MG35_13PL ~(1 << 2) +#else +#define MG35_13PL 0xFFFF +#endif +#if (G34PL >= G35PL) || (G34PL == 0) +#define MG35_14PL ~(1 << 3) +#else +#define MG35_14PL 0xFFFF +#endif +#if (G36PL >= G35PL) || (G36PL == 0) +#define MG35_16PL ~(1 << 5) +#else +#define MG35_16PL 0xFFFF +#endif +#if (G37PL >= G35PL) || (G37PL == 0) +#define MG35_17PL ~(1 << 6) +#else +#define MG35_17PL 0xFFFF +#endif +#if (G38PL >= G35PL) || (G38PL == 0) +#define MG35_18PL ~(1 << 7) +#else +#define MG35_18PL 0xFFFF +#endif +#define MG35_15PL 0x00EF +#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \ + MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL) +// End of MG35: + +// Beginning of MG36: +#if (G31PL >= G36PL) || (G31PL == 0) +#define MG36_11PL ~(1) +#else +#define MG36_11PL 0xFFFF +#endif +#if (G32PL >= G36PL) || (G32PL == 0) +#define MG36_12PL ~(1 << 1) +#else +#define MG36_12PL 0xFFFF +#endif +#if (G33PL >= G36PL) || (G33PL == 0) +#define MG36_13PL ~(1 << 2) +#else +#define MG36_13PL 0xFFFF +#endif +#if (G34PL >= G36PL) || (G34PL == 0) +#define MG36_14PL ~(1 << 3) +#else +#define MG36_14PL 0xFFFF +#endif +#if (G35PL >= G36PL) || (G35PL == 0) +#define MG36_15PL ~(1 << 4) +#else +#define MG36_15PL 0xFFFF +#endif +#if (G37PL >= G36PL) || (G37PL == 0) +#define MG36_17PL ~(1 << 6) +#else +#define MG36_17PL 0xFFFF +#endif +#if (G38PL >= G36PL) || (G38PL == 0) +#define MG36_18PL ~(1 << 7) +#else +#define MG36_18PL 0xFFFF +#endif +#define MG36_16PL 0x00DF +#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \ + MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL) +// End of MG36: + +// Beginning of MG37: +#if (G31PL >= G37PL) || (G31PL == 0) +#define MG37_11PL ~(1) +#else +#define MG37_11PL 0xFFFF +#endif +#if (G32PL >= G37PL) || (G32PL == 0) +#define MG37_12PL ~(1 << 1) +#else +#define MG37_12PL 0xFFFF +#endif +#if (G33PL >= G37PL) || (G33PL == 0) +#define MG37_13PL ~(1 << 2) +#else +#define MG37_13PL 0xFFFF +#endif +#if (G34PL >= G37PL) || (G34PL == 0) +#define MG37_14PL ~(1 << 3) +#else +#define MG37_14PL 0xFFFF +#endif +#if (G35PL >= G37PL) || (G35PL == 0) +#define MG37_15PL ~(1 << 4) +#else +#define MG37_15PL 0xFFFF +#endif +#if (G36PL >= G37PL) || (G36PL == 0) +#define MG37_16PL ~(1 << 5) +#else +#define MG37_16PL 0xFFFF +#endif +#if (G38PL >= G37PL) || (G38PL == 0) +#define MG37_18PL ~(1 << 7) +#else +#define MG37_18PL 0xFFFF +#endif +#define MG37_17PL 0x00BF +#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \ + MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL) +// End of MG37: + +// Beginning of MG38: +#if (G31PL >= G38PL) || (G31PL == 0) +#define MG38_11PL ~(1) +#else +#define MG38_11PL 0xFFFF +#endif +#if (G32PL >= G38PL) || (G32PL == 0) +#define MG38_12PL ~(1 << 1) +#else +#define MG38_12PL 0xFFFF +#endif +#if (G33PL >= G38PL) || (G33PL == 0) +#define MG38_13PL ~(1 << 2) +#else +#define MG38_13PL 0xFFFF +#endif +#if (G34PL >= G38PL) || (G34PL == 0) +#define MG38_14PL ~(1 << 3) +#else +#define MG38_14PL 0xFFFF +#endif +#if (G35PL >= G38PL) || (G35PL == 0) +#define MG38_15PL ~(1 << 4) +#else +#define MG38_15PL 0xFFFF +#endif +#if (G36PL >= G38PL) || (G36PL == 0) +#define MG38_16PL ~(1 << 5) +#else +#define MG38_16PL 0xFFFF +#endif +#if (G37PL >= G38PL) || (G37PL == 0) +#define MG38_17PL ~(1 << 6) +#else +#define MG38_17PL 0xFFFF +#endif +#define MG38_18PL 0x007F +#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \ + MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL) +// End of MG38: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG41 to MG48: +// + +// Beginning of MG41: +#if (G42PL >= G41PL) || (G42PL == 0) +#define MG41_12PL ~(1 << 1) +#else +#define MG41_12PL 0xFFFF +#endif +#if (G43PL >= G41PL) || (G43PL == 0) +#define MG41_13PL ~(1 << 2) +#else +#define MG41_13PL 0xFFFF +#endif +#if (G44PL >= G41PL) || (G44PL == 0) +#define MG41_14PL ~(1 << 3) +#else +#define MG41_14PL 0xFFFF +#endif +#if (G45PL >= G41PL) || (G45PL == 0) +#define MG41_15PL ~(1 << 4) +#else +#define MG41_15PL 0xFFFF +#endif +#if (G46PL >= G41PL) || (G46PL == 0) +#define MG41_16PL ~(1 << 5) +#else +#define MG41_16PL 0xFFFF +#endif +#if (G47PL >= G41PL) || (G47PL == 0) +#define MG41_17PL ~(1 << 6) +#else +#define MG41_17PL 0xFFFF +#endif +#if (G48PL >= G41PL) || (G48PL == 0) +#define MG41_18PL ~(1 << 7) +#else +#define MG41_18PL 0xFFFF +#endif +#define MG41_11PL 0x00FE +#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \ + MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL) +// End of MG41: + +// Beginning of MG42: +#if (G41PL >= G42PL) || (G41PL == 0) +#define MG42_11PL ~(1) +#else +#define MG42_11PL 0xFFFF +#endif +#if (G43PL >= G42PL) || (G43PL == 0) +#define MG42_13PL ~(1 << 2) +#else +#define MG42_13PL 0xFFFF +#endif +#if (G44PL >= G42PL) || (G44PL == 0) +#define MG42_14PL ~(1 << 3) +#else +#define MG42_14PL 0xFFFF +#endif +#if (G45PL >= G42PL) || (G45PL == 0) +#define MG42_15PL ~(1 << 4) +#else +#define MG42_15PL 0xFFFF +#endif +#if (G46PL >= G42PL) || (G46PL == 0) +#define MG42_16PL ~(1 << 5) +#else +#define MG42_16PL 0xFFFF +#endif +#if (G47PL >= G42PL) || (G47PL == 0) +#define MG42_17PL ~(1 << 6) +#else +#define MG42_17PL 0xFFFF +#endif +#if (G48PL >= G42PL) || (G48PL == 0) +#define MG42_18PL ~(1 << 7) +#else +#define MG42_18PL 0xFFFF +#endif +#define MG42_12PL 0x00FD +#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \ + MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL) +// End of MG42: + +// Beginning of MG43: +#if (G41PL >= G43PL) || (G41PL == 0) +#define MG43_11PL ~(1) +#else +#define MG43_11PL 0xFFFF +#endif +#if (G42PL >= G43PL) || (G42PL == 0) +#define MG43_12PL ~(1 << 1) +#else +#define MG43_12PL 0xFFFF +#endif +#if (G44PL >= G43PL) || (G44PL == 0) +#define MG43_14PL ~(1 << 3) +#else +#define MG43_14PL 0xFFFF +#endif +#if (G45PL >= G43PL) || (G45PL == 0) +#define MG43_15PL ~(1 << 4) +#else +#define MG43_15PL 0xFFFF +#endif +#if (G46PL >= G43PL) || (G46PL == 0) +#define MG43_16PL ~(1 << 5) +#else +#define MG43_16PL 0xFFFF +#endif +#if (G47PL >= G43PL) || (G47PL == 0) +#define MG43_17PL ~(1 << 6) +#else +#define MG43_17PL 0xFFFF +#endif +#if (G48PL >= G43PL) || (G48PL == 0) +#define MG43_18PL ~(1 << 7) +#else +#define MG43_18PL 0xFFFF +#endif +#define MG43_13PL 0x00FB +#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \ + MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL) +// End of MG43: + +// Beginning of MG44: +#if (G41PL >= G44PL) || (G41PL == 0) +#define MG44_11PL ~(1) +#else +#define MG44_11PL 0xFFFF +#endif +#if (G42PL >= G44PL) || (G42PL == 0) +#define MG44_12PL ~(1 << 1) +#else +#define MG44_12PL 0xFFFF +#endif +#if (G43PL >= G44PL) || (G43PL == 0) +#define MG44_13PL ~(1 << 2) +#else +#define MG44_13PL 0xFFFF +#endif +#if (G45PL >= G44PL) || (G45PL == 0) +#define MG44_15PL ~(1 << 4) +#else +#define MG44_15PL 0xFFFF +#endif +#if (G46PL >= G44PL) || (G46PL == 0) +#define MG44_16PL ~(1 << 5) +#else +#define MG44_16PL 0xFFFF +#endif +#if (G47PL >= G44PL) || (G47PL == 0) +#define MG44_17PL ~(1 << 6) +#else +#define MG44_17PL 0xFFFF +#endif +#if (G48PL >= G44PL) || (G48PL == 0) +#define MG44_18PL ~(1 << 7) +#else +#define MG44_18PL 0xFFFF +#endif +#define MG44_14PL 0x00F7 +#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \ + MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL) +// End of MG44: + +// Beginning of MG45: +#if (G41PL >= G45PL) || (G41PL == 0) +#define MG45_11PL ~(1) +#else +#define MG45_11PL 0xFFFF +#endif +#if (G42PL >= G45PL) || (G42PL == 0) +#define MG45_12PL ~(1 << 1) +#else +#define MG45_12PL 0xFFFF +#endif +#if (G43PL >= G45PL) || (G43PL == 0) +#define MG45_13PL ~(1 << 2) +#else +#define MG45_13PL 0xFFFF +#endif +#if (G44PL >= G45PL) || (G44PL == 0) +#define MG45_14PL ~(1 << 3) +#else +#define MG45_14PL 0xFFFF +#endif +#if (G46PL >= G45PL) || (G46PL == 0) +#define MG45_16PL ~(1 << 5) +#else +#define MG45_16PL 0xFFFF +#endif +#if (G47PL >= G45PL) || (G47PL == 0) +#define MG45_17PL ~(1 << 6) +#else +#define MG45_17PL 0xFFFF +#endif +#if (G48PL >= G45PL) || (G48PL == 0) +#define MG45_18PL ~(1 << 7) +#else +#define MG45_18PL 0xFFFF +#endif +#define MG45_15PL 0x00EF +#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \ + MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL) +// End of MG45: + +// Beginning of MG46: +#if (G41PL >= G46PL) || (G41PL == 0) +#define MG46_11PL ~(1) +#else +#define MG46_11PL 0xFFFF +#endif +#if (G42PL >= G46PL) || (G42PL == 0) +#define MG46_12PL ~(1 << 1) +#else +#define MG46_12PL 0xFFFF +#endif +#if (G43PL >= G46PL) || (G43PL == 0) +#define MG46_13PL ~(1 << 2) +#else +#define MG46_13PL 0xFFFF +#endif +#if (G44PL >= G46PL) || (G44PL == 0) +#define MG46_14PL ~(1 << 3) +#else +#define MG46_14PL 0xFFFF +#endif +#if (G45PL >= G46PL) || (G45PL == 0) +#define MG46_15PL ~(1 << 4) +#else +#define MG46_15PL 0xFFFF +#endif +#if (G47PL >= G46PL) || (G47PL == 0) +#define MG46_17PL ~(1 << 6) +#else +#define MG46_17PL 0xFFFF +#endif +#if (G48PL >= G46PL) || (G48PL == 0) +#define MG46_18PL ~(1 << 7) +#else +#define MG46_18PL 0xFFFF +#endif +#define MG46_16PL 0x00DF +#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \ + MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL) +// End of MG46: + +// Beginning of MG47: +#if (G41PL >= G47PL) || (G41PL == 0) +#define MG47_11PL ~(1) +#else +#define MG47_11PL 0xFFFF +#endif +#if (G42PL >= G47PL) || (G42PL == 0) +#define MG47_12PL ~(1 << 1) +#else +#define MG47_12PL 0xFFFF +#endif +#if (G43PL >= G47PL) || (G43PL == 0) +#define MG47_13PL ~(1 << 2) +#else +#define MG47_13PL 0xFFFF +#endif +#if (G44PL >= G47PL) || (G44PL == 0) +#define MG47_14PL ~(1 << 3) +#else +#define MG47_14PL 0xFFFF +#endif +#if (G45PL >= G47PL) || (G45PL == 0) +#define MG47_15PL ~(1 << 4) +#else +#define MG47_15PL 0xFFFF +#endif +#if (G46PL >= G47PL) || (G46PL == 0) +#define MG47_16PL ~(1 << 5) +#else +#define MG47_16PL 0xFFFF +#endif +#if (G48PL >= G47PL) || (G48PL == 0) +#define MG47_18PL ~(1 << 7) +#else +#define MG47_18PL 0xFFFF +#endif +#define MG47_17PL 0x00BF +#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \ + MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL) +// End of MG47: + +// Beginning of MG48: +#if (G41PL >= G48PL) || (G41PL == 0) +#define MG48_11PL ~(1) +#else +#define MG48_11PL 0xFFFF +#endif +#if (G42PL >= G48PL) || (G42PL == 0) +#define MG48_12PL ~(1 << 1) +#else +#define MG48_12PL 0xFFFF +#endif +#if (G43PL >= G48PL) || (G43PL == 0) +#define MG48_13PL ~(1 << 2) +#else +#define MG48_13PL 0xFFFF +#endif +#if (G44PL >= G48PL) || (G44PL == 0) +#define MG48_14PL ~(1 << 3) +#else +#define MG48_14PL 0xFFFF +#endif +#if (G45PL >= G48PL) || (G45PL == 0) +#define MG48_15PL ~(1 << 4) +#else +#define MG48_15PL 0xFFFF +#endif +#if (G46PL >= G48PL) || (G46PL == 0) +#define MG48_16PL ~(1 << 5) +#else +#define MG48_16PL 0xFFFF +#endif +#if (G47PL >= G48PL) || (G47PL == 0) +#define MG48_17PL ~(1 << 6) +#else +#define MG48_17PL 0xFFFF +#endif +#define MG48_18PL 0x007F +#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \ + MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL) +// End of MG48: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG51 to MG58: +// + +// Beginning of MG51: +#if (G52PL >= G51PL) || (G52PL == 0) +#define MG51_12PL ~(1 << 1) +#else +#define MG51_12PL 0xFFFF +#endif +#if (G53PL >= G51PL) || (G53PL == 0) +#define MG51_13PL ~(1 << 2) +#else +#define MG51_13PL 0xFFFF +#endif +#if (G54PL >= G51PL) || (G54PL == 0) +#define MG51_14PL ~(1 << 3) +#else +#define MG51_14PL 0xFFFF +#endif +#if (G55PL >= G51PL) || (G55PL == 0) +#define MG51_15PL ~(1 << 4) +#else +#define MG51_15PL 0xFFFF +#endif +#if (G56PL >= G51PL) || (G56PL == 0) +#define MG51_16PL ~(1 << 5) +#else +#define MG51_16PL 0xFFFF +#endif +#if (G57PL >= G51PL) || (G57PL == 0) +#define MG51_17PL ~(1 << 6) +#else +#define MG51_17PL 0xFFFF +#endif +#if (G58PL >= G51PL) || (G58PL == 0) +#define MG51_18PL ~(1 << 7) +#else +#define MG51_18PL 0xFFFF +#endif +#define MG51_11PL 0x00FE +#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \ + MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL) +// End of MG51: + +// Beginning of MG52: +#if (G51PL >= G52PL) || (G51PL == 0) +#define MG52_11PL ~(1) +#else +#define MG52_11PL 0xFFFF +#endif +#if (G53PL >= G52PL) || (G53PL == 0) +#define MG52_13PL ~(1 << 2) +#else +#define MG52_13PL 0xFFFF +#endif +#if (G54PL >= G52PL) || (G54PL == 0) +#define MG52_14PL ~(1 << 3) +#else +#define MG52_14PL 0xFFFF +#endif +#if (G55PL >= G52PL) || (G55PL == 0) +#define MG52_15PL ~(1 << 4) +#else +#define MG52_15PL 0xFFFF +#endif +#if (G56PL >= G52PL) || (G56PL == 0) +#define MG52_16PL ~(1 << 5) +#else +#define MG52_16PL 0xFFFF +#endif +#if (G57PL >= G52PL) || (G57PL == 0) +#define MG52_17PL ~(1 << 6) +#else +#define MG52_17PL 0xFFFF +#endif +#if (G58PL >= G52PL) || (G58PL == 0) +#define MG52_18PL ~(1 << 7) +#else +#define MG52_18PL 0xFFFF +#endif +#define MG52_12PL 0x00FD +#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \ + MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL) +// End of MG52: + +// Beginning of MG53: +#if (G51PL >= G53PL) || (G51PL == 0) +#define MG53_11PL ~(1) +#else +#define MG53_11PL 0xFFFF +#endif +#if (G52PL >= G53PL) || (G52PL == 0) +#define MG53_12PL ~(1 << 1) +#else +#define MG53_12PL 0xFFFF +#endif +#if (G54PL >= G53PL) || (G54PL == 0) +#define MG53_14PL ~(1 << 3) +#else +#define MG53_14PL 0xFFFF +#endif +#if (G55PL >= G53PL) || (G55PL == 0) +#define MG53_15PL ~(1 << 4) +#else +#define MG53_15PL 0xFFFF +#endif +#if (G56PL >= G53PL) || (G56PL == 0) +#define MG53_16PL ~(1 << 5) +#else +#define MG53_16PL 0xFFFF +#endif +#if (G57PL >= G53PL) || (G57PL == 0) +#define MG53_17PL ~(1 << 6) +#else +#define MG53_17PL 0xFFFF +#endif +#if (G58PL >= G53PL) || (G58PL == 0) +#define MG53_18PL ~(1 << 7) +#else +#define MG53_18PL 0xFFFF +#endif +#define MG53_13PL 0x00FB +#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \ + MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL) +// End of MG53: + +// Beginning of MG54: +#if (G51PL >= G54PL) || (G51PL == 0) +#define MG54_11PL ~(1) +#else +#define MG54_11PL 0xFFFF +#endif +#if (G52PL >= G54PL) || (G52PL == 0) +#define MG54_12PL ~(1 << 1) +#else +#define MG54_12PL 0xFFFF +#endif +#if (G53PL >= G54PL) || (G53PL == 0) +#define MG54_13PL ~(1 << 2) +#else +#define MG54_13PL 0xFFFF +#endif +#if (G55PL >= G54PL) || (G55PL == 0) +#define MG54_15PL ~(1 << 4) +#else +#define MG54_15PL 0xFFFF +#endif +#if (G56PL >= G54PL) || (G56PL == 0) +#define MG54_16PL ~(1 << 5) +#else +#define MG54_16PL 0xFFFF +#endif +#if (G57PL >= G54PL) || (G57PL == 0) +#define MG54_17PL ~(1 << 6) +#else +#define MG54_17PL 0xFFFF +#endif +#if (G58PL >= G54PL) || (G58PL == 0) +#define MG54_18PL ~(1 << 7) +#else +#define MG54_18PL 0xFFFF +#endif +#define MG54_14PL 0x00F7 +#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \ + MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL) +// End of MG54: + +// Beginning of MG55: +#if (G51PL >= G55PL) || (G51PL == 0) +#define MG55_11PL ~(1) +#else +#define MG55_11PL 0xFFFF +#endif +#if (G52PL >= G55PL) || (G52PL == 0) +#define MG55_12PL ~(1 << 1) +#else +#define MG55_12PL 0xFFFF +#endif +#if (G53PL >= G55PL) || (G53PL == 0) +#define MG55_13PL ~(1 << 2) +#else +#define MG55_13PL 0xFFFF +#endif +#if (G54PL >= G55PL) || (G54PL == 0) +#define MG55_14PL ~(1 << 3) +#else +#define MG55_14PL 0xFFFF +#endif +#if (G56PL >= G55PL) || (G56PL == 0) +#define MG55_16PL ~(1 << 5) +#else +#define MG55_16PL 0xFFFF +#endif +#if (G57PL >= G55PL) || (G57PL == 0) +#define MG55_17PL ~(1 << 6) +#else +#define MG55_17PL 0xFFFF +#endif +#if (G58PL >= G55PL) || (G58PL == 0) +#define MG55_18PL ~(1 << 7) +#else +#define MG55_18PL 0xFFFF +#endif +#define MG55_15PL 0x00EF +#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \ + MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL) +// End of MG55: + +// Beginning of MG56: +#if (G51PL >= G56PL) || (G51PL == 0) +#define MG56_11PL ~(1) +#else +#define MG56_11PL 0xFFFF +#endif +#if (G52PL >= G56PL) || (G52PL == 0) +#define MG56_12PL ~(1 << 1) +#else +#define MG56_12PL 0xFFFF +#endif +#if (G53PL >= G56PL) || (G53PL == 0) +#define MG56_13PL ~(1 << 2) +#else +#define MG56_13PL 0xFFFF +#endif +#if (G54PL >= G56PL) || (G54PL == 0) +#define MG56_14PL ~(1 << 3) +#else +#define MG56_14PL 0xFFFF +#endif +#if (G55PL >= G56PL) || (G55PL == 0) +#define MG56_15PL ~(1 << 4) +#else +#define MG56_15PL 0xFFFF +#endif +#if (G57PL >= G56PL) || (G57PL == 0) +#define MG56_17PL ~(1 << 6) +#else +#define MG56_17PL 0xFFFF +#endif +#if (G58PL >= G56PL) || (G58PL == 0) +#define MG56_18PL ~(1 << 7) +#else +#define MG56_18PL 0xFFFF +#endif +#define MG56_16PL 0x00DF +#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \ + MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL) +// End of MG56: + +// Beginning of MG57: +#if (G51PL >= G57PL) || (G51PL == 0) +#define MG57_11PL ~(1) +#else +#define MG57_11PL 0xFFFF +#endif +#if (G52PL >= G57PL) || (G52PL == 0) +#define MG57_12PL ~(1 << 1) +#else +#define MG57_12PL 0xFFFF +#endif +#if (G53PL >= G57PL) || (G53PL == 0) +#define MG57_13PL ~(1 << 2) +#else +#define MG57_13PL 0xFFFF +#endif +#if (G54PL >= G57PL) || (G54PL == 0) +#define MG57_14PL ~(1 << 3) +#else +#define MG57_14PL 0xFFFF +#endif +#if (G55PL >= G57PL) || (G55PL == 0) +#define MG57_15PL ~(1 << 4) +#else +#define MG57_15PL 0xFFFF +#endif +#if (G56PL >= G57PL) || (G56PL == 0) +#define MG57_16PL ~(1 << 5) +#else +#define MG57_16PL 0xFFFF +#endif +#if (G58PL >= G57PL) || (G58PL == 0) +#define MG57_18PL ~(1 << 7) +#else +#define MG57_18PL 0xFFFF +#endif +#define MG57_17PL 0x00BF +#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \ + MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL) +// End of MG57: + +// Beginning of MG58: +#if (G51PL >= G58PL) || (G51PL == 0) +#define MG58_11PL ~(1) +#else +#define MG58_11PL 0xFFFF +#endif +#if (G52PL >= G58PL) || (G52PL == 0) +#define MG58_12PL ~(1 << 1) +#else +#define MG58_12PL 0xFFFF +#endif +#if (G53PL >= G58PL) || (G53PL == 0) +#define MG58_13PL ~(1 << 2) +#else +#define MG58_13PL 0xFFFF +#endif +#if (G54PL >= G58PL) || (G54PL == 0) +#define MG58_14PL ~(1 << 3) +#else +#define MG58_14PL 0xFFFF +#endif +#if (G55PL >= G58PL) || (G55PL == 0) +#define MG58_15PL ~(1 << 4) +#else +#define MG58_15PL 0xFFFF +#endif +#if (G56PL >= G58PL) || (G56PL == 0) +#define MG58_16PL ~(1 << 5) +#else +#define MG58_16PL 0xFFFF +#endif +#if (G57PL >= G58PL) || (G57PL == 0) +#define MG58_17PL ~(1 << 6) +#else +#define MG58_17PL 0xFFFF +#endif +#define MG58_18PL 0x007F +#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \ + MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL) +// End of MG58: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG61 to MG68: +// + +// Beginning of MG61: +#if (G62PL >= G61PL) || (G62PL == 0) +#define MG61_12PL ~(1 << 1) +#else +#define MG61_12PL 0xFFFF +#endif +#if (G63PL >= G61PL) || (G63PL == 0) +#define MG61_13PL ~(1 << 2) +#else +#define MG61_13PL 0xFFFF +#endif +#if (G64PL >= G61PL) || (G64PL == 0) +#define MG61_14PL ~(1 << 3) +#else +#define MG61_14PL 0xFFFF +#endif +#if (G65PL >= G61PL) || (G65PL == 0) +#define MG61_15PL ~(1 << 4) +#else +#define MG61_15PL 0xFFFF +#endif +#if (G66PL >= G61PL) || (G66PL == 0) +#define MG61_16PL ~(1 << 5) +#else +#define MG61_16PL 0xFFFF +#endif +#if (G67PL >= G61PL) || (G67PL == 0) +#define MG61_17PL ~(1 << 6) +#else +#define MG61_17PL 0xFFFF +#endif +#if (G68PL >= G61PL) || (G68PL == 0) +#define MG61_18PL ~(1 << 7) +#else +#define MG61_18PL 0xFFFF +#endif +#define MG61_11PL 0x00FE +#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \ + MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL) +// End of MG61: + +// Beginning of MG62: +#if (G61PL >= G62PL) || (G61PL == 0) +#define MG62_11PL ~(1) +#else +#define MG62_11PL 0xFFFF +#endif +#if (G63PL >= G62PL) || (G63PL == 0) +#define MG62_13PL ~(1 << 2) +#else +#define MG62_13PL 0xFFFF +#endif +#if (G64PL >= G62PL) || (G64PL == 0) +#define MG62_14PL ~(1 << 3) +#else +#define MG62_14PL 0xFFFF +#endif +#if (G65PL >= G62PL) || (G65PL == 0) +#define MG62_15PL ~(1 << 4) +#else +#define MG62_15PL 0xFFFF +#endif +#if (G66PL >= G62PL) || (G66PL == 0) +#define MG62_16PL ~(1 << 5) +#else +#define MG62_16PL 0xFFFF +#endif +#if (G67PL >= G62PL) || (G67PL == 0) +#define MG62_17PL ~(1 << 6) +#else +#define MG62_17PL 0xFFFF +#endif +#if (G68PL >= G62PL) || (G68PL == 0) +#define MG62_18PL ~(1 << 7) +#else +#define MG62_18PL 0xFFFF +#endif +#define MG62_12PL 0x00FD +#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \ + MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL) +// End of MG62: + +// Beginning of MG63: +#if (G61PL >= G63PL) || (G61PL == 0) +#define MG63_11PL ~(1) +#else +#define MG63_11PL 0xFFFF +#endif +#if (G62PL >= G63PL) || (G62PL == 0) +#define MG63_12PL ~(1 << 1) +#else +#define MG63_12PL 0xFFFF +#endif +#if (G64PL >= G63PL) || (G64PL == 0) +#define MG63_14PL ~(1 << 3) +#else +#define MG63_14PL 0xFFFF +#endif +#if (G65PL >= G63PL) || (G65PL == 0) +#define MG63_15PL ~(1 << 4) +#else +#define MG63_15PL 0xFFFF +#endif +#if (G66PL >= G63PL) || (G66PL == 0) +#define MG63_16PL ~(1 << 5) +#else +#define MG63_16PL 0xFFFF +#endif +#if (G67PL >= G63PL) || (G67PL == 0) +#define MG63_17PL ~(1 << 6) +#else +#define MG63_17PL 0xFFFF +#endif +#if (G68PL >= G63PL) || (G68PL == 0) +#define MG63_18PL ~(1 << 7) +#else +#define MG63_18PL 0xFFFF +#endif +#define MG63_13PL 0x00FB +#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \ + MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL) +// End of MG63: + +// Beginning of MG64: +#if (G61PL >= G64PL) || (G61PL == 0) +#define MG64_11PL ~(1) +#else +#define MG64_11PL 0xFFFF +#endif +#if (G62PL >= G64PL) || (G62PL == 0) +#define MG64_12PL ~(1 << 1) +#else +#define MG64_12PL 0xFFFF +#endif +#if (G63PL >= G64PL) || (G63PL == 0) +#define MG64_13PL ~(1 << 2) +#else +#define MG64_13PL 0xFFFF +#endif +#if (G65PL >= G64PL) || (G65PL == 0) +#define MG64_15PL ~(1 << 4) +#else +#define MG64_15PL 0xFFFF +#endif +#if (G66PL >= G64PL) || (G66PL == 0) +#define MG64_16PL ~(1 << 5) +#else +#define MG64_16PL 0xFFFF +#endif +#if (G67PL >= G64PL) || (G67PL == 0) +#define MG64_17PL ~(1 << 6) +#else +#define MG64_17PL 0xFFFF +#endif +#if (G68PL >= G64PL) || (G68PL == 0) +#define MG64_18PL ~(1 << 7) +#else +#define MG64_18PL 0xFFFF +#endif +#define MG64_14PL 0x00F7 +#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \ + MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL) +// End of MG64: + +// Beginning of MG65: +#if (G61PL >= G65PL) || (G61PL == 0) +#define MG65_11PL ~(1) +#else +#define MG65_11PL 0xFFFF +#endif +#if (G62PL >= G65PL) || (G62PL == 0) +#define MG65_12PL ~(1 << 1) +#else +#define MG65_12PL 0xFFFF +#endif +#if (G63PL >= G65PL) || (G63PL == 0) +#define MG65_13PL ~(1 << 2) +#else +#define MG65_13PL 0xFFFF +#endif +#if (G64PL >= G65PL) || (G64PL == 0) +#define MG65_14PL ~(1 << 3) +#else +#define MG65_14PL 0xFFFF +#endif +#if (G66PL >= G65PL) || (G66PL == 0) +#define MG65_16PL ~(1 << 5) +#else +#define MG65_16PL 0xFFFF +#endif +#if (G67PL >= G65PL) || (G67PL == 0) +#define MG65_17PL ~(1 << 6) +#else +#define MG65_17PL 0xFFFF +#endif +#if (G68PL >= G65PL) || (G68PL == 0) +#define MG65_18PL ~(1 << 7) +#else +#define MG65_18PL 0xFFFF +#endif +#define MG65_15PL 0x00EF +#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \ + MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL) +// End of MG65: + +// Beginning of MG66: +#if (G61PL >= G66PL) || (G61PL == 0) +#define MG66_11PL ~(1) +#else +#define MG66_11PL 0xFFFF +#endif +#if (G62PL >= G66PL) || (G62PL == 0) +#define MG66_12PL ~(1 << 1) +#else +#define MG66_12PL 0xFFFF +#endif +#if (G63PL >= G66PL) || (G63PL == 0) +#define MG66_13PL ~(1 << 2) +#else +#define MG66_13PL 0xFFFF +#endif +#if (G64PL >= G66PL) || (G64PL == 0) +#define MG66_14PL ~(1 << 3) +#else +#define MG66_14PL 0xFFFF +#endif +#if (G65PL >= G66PL) || (G65PL == 0) +#define MG66_15PL ~(1 << 4) +#else +#define MG66_15PL 0xFFFF +#endif +#if (G67PL >= G66PL) || (G67PL == 0) +#define MG66_17PL ~(1 << 6) +#else +#define MG66_17PL 0xFFFF +#endif +#if (G68PL >= G66PL) || (G68PL == 0) +#define MG66_18PL ~(1 << 7) +#else +#define MG66_18PL 0xFFFF +#endif +#define MG66_16PL 0x00DF +#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \ + MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL) +// End of MG66: + +// Beginning of MG67: +#if (G61PL >= G67PL) || (G61PL == 0) +#define MG67_11PL ~(1) +#else +#define MG67_11PL 0xFFFF +#endif +#if (G62PL >= G67PL) || (G62PL == 0) +#define MG67_12PL ~(1 << 1) +#else +#define MG67_12PL 0xFFFF +#endif +#if (G63PL >= G67PL) || (G63PL == 0) +#define MG67_13PL ~(1 << 2) +#else +#define MG67_13PL 0xFFFF +#endif +#if (G64PL >= G67PL) || (G64PL == 0) +#define MG67_14PL ~(1 << 3) +#else +#define MG67_14PL 0xFFFF +#endif +#if (G65PL >= G67PL) || (G65PL == 0) +#define MG67_15PL ~(1 << 4) +#else +#define MG67_15PL 0xFFFF +#endif +#if (G66PL >= G67PL) || (G66PL == 0) +#define MG67_16PL ~(1 << 5) +#else +#define MG67_16PL 0xFFFF +#endif +#if (G68PL >= G67PL) || (G68PL == 0) +#define MG67_18PL ~(1 << 7) +#else +#define MG67_18PL 0xFFFF +#endif +#define MG67_17PL 0x00BF +#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \ + MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL) +// End of MG67: + +// Beginning of MG68: +#if (G61PL >= G68PL) || (G61PL == 0) +#define MG68_11PL ~(1) +#else +#define MG68_11PL 0xFFFF +#endif +#if (G62PL >= G68PL) || (G62PL == 0) +#define MG68_12PL ~(1 << 1) +#else +#define MG68_12PL 0xFFFF +#endif +#if (G63PL >= G68PL) || (G63PL == 0) +#define MG68_13PL ~(1 << 2) +#else +#define MG68_13PL 0xFFFF +#endif +#if (G64PL >= G68PL) || (G64PL == 0) +#define MG68_14PL ~(1 << 3) +#else +#define MG68_14PL 0xFFFF +#endif +#if (G65PL >= G68PL) || (G65PL == 0) +#define MG68_15PL ~(1 << 4) +#else +#define MG68_15PL 0xFFFF +#endif +#if (G66PL >= G68PL) || (G66PL == 0) +#define MG68_16PL ~(1 << 5) +#else +#define MG68_16PL 0xFFFF +#endif +#if (G67PL >= G68PL) || (G67PL == 0) +#define MG68_17PL ~(1 << 6) +#else +#define MG68_17PL 0xFFFF +#endif +#define MG68_18PL 0x007F +#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \ + MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL) +// End of MG68: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG71 to MG78: +// + +// Beginning of MG71: +#if (G72PL >= G71PL) || (G72PL == 0) +#define MG71_12PL ~(1 << 1) +#else +#define MG71_12PL 0xFFFF +#endif +#if (G73PL >= G71PL) || (G73PL == 0) +#define MG71_13PL ~(1 << 2) +#else +#define MG71_13PL 0xFFFF +#endif +#if (G74PL >= G71PL) || (G74PL == 0) +#define MG71_14PL ~(1 << 3) +#else +#define MG71_14PL 0xFFFF +#endif +#if (G75PL >= G71PL) || (G75PL == 0) +#define MG71_15PL ~(1 << 4) +#else +#define MG71_15PL 0xFFFF +#endif +#if (G76PL >= G71PL) || (G76PL == 0) +#define MG71_16PL ~(1 << 5) +#else +#define MG71_16PL 0xFFFF +#endif +#if (G77PL >= G71PL) || (G77PL == 0) +#define MG71_17PL ~(1 << 6) +#else +#define MG71_17PL 0xFFFF +#endif +#if (G78PL >= G71PL) || (G78PL == 0) +#define MG71_18PL ~(1 << 7) +#else +#define MG71_18PL 0xFFFF +#endif +#define MG71_11PL 0x00FE +#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \ + MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL) +// End of MG71: + +// Beginning of MG72: +#if (G71PL >= G72PL) || (G71PL == 0) +#define MG72_11PL ~(1) +#else +#define MG72_11PL 0xFFFF +#endif +#if (G73PL >= G72PL) || (G73PL == 0) +#define MG72_13PL ~(1 << 2) +#else +#define MG72_13PL 0xFFFF +#endif +#if (G74PL >= G72PL) || (G74PL == 0) +#define MG72_14PL ~(1 << 3) +#else +#define MG72_14PL 0xFFFF +#endif +#if (G75PL >= G72PL) || (G75PL == 0) +#define MG72_15PL ~(1 << 4) +#else +#define MG72_15PL 0xFFFF +#endif +#if (G76PL >= G72PL) || (G76PL == 0) +#define MG72_16PL ~(1 << 5) +#else +#define MG72_16PL 0xFFFF +#endif +#if (G77PL >= G72PL) || (G77PL == 0) +#define MG72_17PL ~(1 << 6) +#else +#define MG72_17PL 0xFFFF +#endif +#if (G78PL >= G72PL) || (G78PL == 0) +#define MG72_18PL ~(1 << 7) +#else +#define MG72_18PL 0xFFFF +#endif +#define MG72_12PL 0x00FD +#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \ + MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL) +// End of MG72: + +// Beginning of MG73: +#if (G71PL >= G73PL) || (G71PL == 0) +#define MG73_11PL ~(1) +#else +#define MG73_11PL 0xFFFF +#endif +#if (G72PL >= G73PL) || (G72PL == 0) +#define MG73_12PL ~(1 << 1) +#else +#define MG73_12PL 0xFFFF +#endif +#if (G74PL >= G73PL) || (G74PL == 0) +#define MG73_14PL ~(1 << 3) +#else +#define MG73_14PL 0xFFFF +#endif +#if (G75PL >= G73PL) || (G75PL == 0) +#define MG73_15PL ~(1 << 4) +#else +#define MG73_15PL 0xFFFF +#endif +#if (G76PL >= G73PL) || (G76PL == 0) +#define MG73_16PL ~(1 << 5) +#else +#define MG73_16PL 0xFFFF +#endif +#if (G77PL >= G73PL) || (G77PL == 0) +#define MG73_17PL ~(1 << 6) +#else +#define MG73_17PL 0xFFFF +#endif +#if (G78PL >= G73PL) || (G78PL == 0) +#define MG73_18PL ~(1 << 7) +#else +#define MG73_18PL 0xFFFF +#endif +#define MG73_13PL 0x00FB +#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \ + MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL) +// End of MG73: + +// Beginning of MG74: +#if (G71PL >= G74PL) || (G71PL == 0) +#define MG74_11PL ~(1) +#else +#define MG74_11PL 0xFFFF +#endif +#if (G72PL >= G74PL) || (G72PL == 0) +#define MG74_12PL ~(1 << 1) +#else +#define MG74_12PL 0xFFFF +#endif +#if (G73PL >= G74PL) || (G73PL == 0) +#define MG74_13PL ~(1 << 2) +#else +#define MG74_13PL 0xFFFF +#endif +#if (G75PL >= G74PL) || (G75PL == 0) +#define MG74_15PL ~(1 << 4) +#else +#define MG74_15PL 0xFFFF +#endif +#if (G76PL >= G74PL) || (G76PL == 0) +#define MG74_16PL ~(1 << 5) +#else +#define MG74_16PL 0xFFFF +#endif +#if (G77PL >= G74PL) || (G77PL == 0) +#define MG74_17PL ~(1 << 6) +#else +#define MG74_17PL 0xFFFF +#endif +#if (G78PL >= G74PL) || (G78PL == 0) +#define MG74_18PL ~(1 << 7) +#else +#define MG74_18PL 0xFFFF +#endif +#define MG74_14PL 0x00F7 +#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \ + MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL) +// End of MG74: + +// Beginning of MG75: +#if (G71PL >= G75PL) || (G71PL == 0) +#define MG75_11PL ~(1) +#else +#define MG75_11PL 0xFFFF +#endif +#if (G72PL >= G75PL) || (G72PL == 0) +#define MG75_12PL ~(1 << 1) +#else +#define MG75_12PL 0xFFFF +#endif +#if (G73PL >= G75PL) || (G73PL == 0) +#define MG75_13PL ~(1 << 2) +#else +#define MG75_13PL 0xFFFF +#endif +#if (G74PL >= G75PL) || (G74PL == 0) +#define MG75_14PL ~(1 << 3) +#else +#define MG75_14PL 0xFFFF +#endif +#if (G76PL >= G75PL) || (G76PL == 0) +#define MG75_16PL ~(1 << 5) +#else +#define MG75_16PL 0xFFFF +#endif +#if (G77PL >= G75PL) || (G77PL == 0) +#define MG75_17PL ~(1 << 6) +#else +#define MG75_17PL 0xFFFF +#endif +#if (G78PL >= G75PL) || (G78PL == 0) +#define MG75_18PL ~(1 << 7) +#else +#define MG75_18PL 0xFFFF +#endif +#define MG75_15PL 0x00EF +#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \ + MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL) +// End of MG75: + +// Beginning of MG76: +#if (G71PL >= G76PL) || (G71PL == 0) +#define MG76_11PL ~(1) +#else +#define MG76_11PL 0xFFFF +#endif +#if (G72PL >= G76PL) || (G72PL == 0) +#define MG76_12PL ~(1 << 1) +#else +#define MG76_12PL 0xFFFF +#endif +#if (G73PL >= G76PL) || (G73PL == 0) +#define MG76_13PL ~(1 << 2) +#else +#define MG76_13PL 0xFFFF +#endif +#if (G74PL >= G76PL) || (G74PL == 0) +#define MG76_14PL ~(1 << 3) +#else +#define MG76_14PL 0xFFFF +#endif +#if (G75PL >= G76PL) || (G75PL == 0) +#define MG76_15PL ~(1 << 4) +#else +#define MG76_15PL 0xFFFF +#endif +#if (G77PL >= G76PL) || (G77PL == 0) +#define MG76_17PL ~(1 << 6) +#else +#define MG76_17PL 0xFFFF +#endif +#if (G78PL >= G76PL) || (G78PL == 0) +#define MG76_18PL ~(1 << 7) +#else +#define MG76_18PL 0xFFFF +#endif +#define MG76_16PL 0x00DF +#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \ + MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL) +// End of MG76: + +// Beginning of MG77: +#if (G71PL >= G77PL) || (G71PL == 0) +#define MG77_11PL ~(1) +#else +#define MG77_11PL 0xFFFF +#endif +#if (G72PL >= G77PL) || (G72PL == 0) +#define MG77_12PL ~(1 << 1) +#else +#define MG77_12PL 0xFFFF +#endif +#if (G73PL >= G77PL) || (G73PL == 0) +#define MG77_13PL ~(1 << 2) +#else +#define MG77_13PL 0xFFFF +#endif +#if (G74PL >= G77PL) || (G74PL == 0) +#define MG77_14PL ~(1 << 3) +#else +#define MG77_14PL 0xFFFF +#endif +#if (G75PL >= G77PL) || (G75PL == 0) +#define MG77_15PL ~(1 << 4) +#else +#define MG77_15PL 0xFFFF +#endif +#if (G76PL >= G77PL) || (G76PL == 0) +#define MG77_16PL ~(1 << 5) +#else +#define MG77_16PL 0xFFFF +#endif +#if (G78PL >= G77PL) || (G78PL == 0) +#define MG77_18PL ~(1 << 7) +#else +#define MG77_18PL 0xFFFF +#endif +#define MG77_17PL 0x00BF +#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \ + MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL) +// End of MG77: + +// Beginning of MG78: +#if (G71PL >= G78PL) || (G71PL == 0) +#define MG78_11PL ~(1) +#else +#define MG78_11PL 0xFFFF +#endif +#if (G72PL >= G78PL) || (G72PL == 0) +#define MG78_12PL ~(1 << 1) +#else +#define MG78_12PL 0xFFFF +#endif +#if (G73PL >= G78PL) || (G73PL == 0) +#define MG78_13PL ~(1 << 2) +#else +#define MG78_13PL 0xFFFF +#endif +#if (G74PL >= G78PL) || (G74PL == 0) +#define MG78_14PL ~(1 << 3) +#else +#define MG78_14PL 0xFFFF +#endif +#if (G75PL >= G78PL) || (G75PL == 0) +#define MG78_15PL ~(1 << 4) +#else +#define MG78_15PL 0xFFFF +#endif +#if (G76PL >= G78PL) || (G76PL == 0) +#define MG78_16PL ~(1 << 5) +#else +#define MG78_16PL 0xFFFF +#endif +#if (G77PL >= G78PL) || (G77PL == 0) +#define MG78_17PL ~(1 << 6) +#else +#define MG78_17PL 0xFFFF +#endif +#define MG78_18PL 0x007F +#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \ + MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL) +// End of MG78: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG81 to MG88: +// + +// Beginning of MG81: +#if (G82PL >= G81PL) || (G82PL == 0) +#define MG81_12PL ~(1 << 1) +#else +#define MG81_12PL 0xFFFF +#endif +#if (G83PL >= G81PL) || (G83PL == 0) +#define MG81_13PL ~(1 << 2) +#else +#define MG81_13PL 0xFFFF +#endif +#if (G84PL >= G81PL) || (G84PL == 0) +#define MG81_14PL ~(1 << 3) +#else +#define MG81_14PL 0xFFFF +#endif +#if (G85PL >= G81PL) || (G85PL == 0) +#define MG81_15PL ~(1 << 4) +#else +#define MG81_15PL 0xFFFF +#endif +#if (G86PL >= G81PL) || (G86PL == 0) +#define MG81_16PL ~(1 << 5) +#else +#define MG81_16PL 0xFFFF +#endif +#if (G87PL >= G81PL) || (G87PL == 0) +#define MG81_17PL ~(1 << 6) +#else +#define MG81_17PL 0xFFFF +#endif +#if (G88PL >= G81PL) || (G88PL == 0) +#define MG81_18PL ~(1 << 7) +#else +#define MG81_18PL 0xFFFF +#endif +#define MG81_11PL 0x00FE +#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \ + MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL) +// End of MG81: + +// Beginning of MG82: +#if (G81PL >= G82PL) || (G81PL == 0) +#define MG82_11PL ~(1) +#else +#define MG82_11PL 0xFFFF +#endif +#if (G83PL >= G82PL) || (G83PL == 0) +#define MG82_13PL ~(1 << 2) +#else +#define MG82_13PL 0xFFFF +#endif +#if (G84PL >= G82PL) || (G84PL == 0) +#define MG82_14PL ~(1 << 3) +#else +#define MG82_14PL 0xFFFF +#endif +#if (G85PL >= G82PL) || (G85PL == 0) +#define MG82_15PL ~(1 << 4) +#else +#define MG82_15PL 0xFFFF +#endif +#if (G86PL >= G82PL) || (G86PL == 0) +#define MG82_16PL ~(1 << 5) +#else +#define MG82_16PL 0xFFFF +#endif +#if (G87PL >= G82PL) || (G87PL == 0) +#define MG82_17PL ~(1 << 6) +#else +#define MG82_17PL 0xFFFF +#endif +#if (G88PL >= G82PL) || (G88PL == 0) +#define MG82_18PL ~(1 << 7) +#else +#define MG82_18PL 0xFFFF +#endif +#define MG82_12PL 0x00FD +#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \ + MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL) +// End of MG82: + +// Beginning of MG83: +#if (G81PL >= G83PL) || (G81PL == 0) +#define MG83_11PL ~(1) +#else +#define MG83_11PL 0xFFFF +#endif +#if (G82PL >= G83PL) || (G82PL == 0) +#define MG83_12PL ~(1 << 1) +#else +#define MG83_12PL 0xFFFF +#endif +#if (G84PL >= G83PL) || (G84PL == 0) +#define MG83_14PL ~(1 << 3) +#else +#define MG83_14PL 0xFFFF +#endif +#if (G85PL >= G83PL) || (G85PL == 0) +#define MG83_15PL ~(1 << 4) +#else +#define MG83_15PL 0xFFFF +#endif +#if (G86PL >= G83PL) || (G86PL == 0) +#define MG83_16PL ~(1 << 5) +#else +#define MG83_16PL 0xFFFF +#endif +#if (G87PL >= G83PL) || (G87PL == 0) +#define MG83_17PL ~(1 << 6) +#else +#define MG83_17PL 0xFFFF +#endif +#if (G88PL >= G83PL) || (G88PL == 0) +#define MG83_18PL ~(1 << 7) +#else +#define MG83_18PL 0xFFFF +#endif +#define MG83_13PL 0x00FB +#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \ + MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL) +// End of MG83: + +// Beginning of MG84: +#if (G81PL >= G84PL) || (G81PL == 0) +#define MG84_11PL ~(1) +#else +#define MG84_11PL 0xFFFF +#endif +#if (G82PL >= G84PL) || (G82PL == 0) +#define MG84_12PL ~(1 << 1) +#else +#define MG84_12PL 0xFFFF +#endif +#if (G83PL >= G84PL) || (G83PL == 0) +#define MG84_13PL ~(1 << 2) +#else +#define MG84_13PL 0xFFFF +#endif +#if (G85PL >= G84PL) || (G85PL == 0) +#define MG84_15PL ~(1 << 4) +#else +#define MG84_15PL 0xFFFF +#endif +#if (G86PL >= G84PL) || (G86PL == 0) +#define MG84_16PL ~(1 << 5) +#else +#define MG84_16PL 0xFFFF +#endif +#if (G87PL >= G84PL) || (G87PL == 0) +#define MG84_17PL ~(1 << 6) +#else +#define MG84_17PL 0xFFFF +#endif +#if (G88PL >= G84PL) || (G88PL == 0) +#define MG84_18PL ~(1 << 7) +#else +#define MG84_18PL 0xFFFF +#endif +#define MG84_14PL 0x00F7 +#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \ + MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL) +// End of MG84: + +// Beginning of MG85: +#if (G81PL >= G85PL) || (G81PL == 0) +#define MG85_11PL ~(1) +#else +#define MG85_11PL 0xFFFF +#endif +#if (G82PL >= G85PL) || (G82PL == 0) +#define MG85_12PL ~(1 << 1) +#else +#define MG85_12PL 0xFFFF +#endif +#if (G83PL >= G85PL) || (G83PL == 0) +#define MG85_13PL ~(1 << 2) +#else +#define MG85_13PL 0xFFFF +#endif +#if (G84PL >= G85PL) || (G84PL == 0) +#define MG85_14PL ~(1 << 3) +#else +#define MG85_14PL 0xFFFF +#endif +#if (G86PL >= G85PL) || (G86PL == 0) +#define MG85_16PL ~(1 << 5) +#else +#define MG85_16PL 0xFFFF +#endif +#if (G87PL >= G85PL) || (G87PL == 0) +#define MG85_17PL ~(1 << 6) +#else +#define MG85_17PL 0xFFFF +#endif +#if (G88PL >= G85PL) || (G88PL == 0) +#define MG85_18PL ~(1 << 7) +#else +#define MG85_18PL 0xFFFF +#endif +#define MG85_15PL 0x00EF +#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \ + MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL) +// End of MG85: + +// Beginning of MG86: +#if (G81PL >= G86PL) || (G81PL == 0) +#define MG86_11PL ~(1) +#else +#define MG86_11PL 0xFFFF +#endif +#if (G82PL >= G86PL) || (G82PL == 0) +#define MG86_12PL ~(1 << 1) +#else +#define MG86_12PL 0xFFFF +#endif +#if (G83PL >= G86PL) || (G83PL == 0) +#define MG86_13PL ~(1 << 2) +#else +#define MG86_13PL 0xFFFF +#endif +#if (G84PL >= G86PL) || (G84PL == 0) +#define MG86_14PL ~(1 << 3) +#else +#define MG86_14PL 0xFFFF +#endif +#if (G85PL >= G86PL) || (G85PL == 0) +#define MG86_15PL ~(1 << 4) +#else +#define MG86_15PL 0xFFFF +#endif +#if (G87PL >= G86PL) || (G87PL == 0) +#define MG86_17PL ~(1 << 6) +#else +#define MG86_17PL 0xFFFF +#endif +#if (G88PL >= G86PL) || (G88PL == 0) +#define MG86_18PL ~(1 << 7) +#else +#define MG86_18PL 0xFFFF +#endif +#define MG86_16PL 0x00DF +#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \ + MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL) +// End of MG86: + +// Beginning of MG87: +#if (G81PL >= G87PL) || (G81PL == 0) +#define MG87_11PL ~(1) +#else +#define MG87_11PL 0xFFFF +#endif +#if (G82PL >= G87PL) || (G82PL == 0) +#define MG87_12PL ~(1 << 1) +#else +#define MG87_12PL 0xFFFF +#endif +#if (G83PL >= G87PL) || (G83PL == 0) +#define MG87_13PL ~(1 << 2) +#else +#define MG87_13PL 0xFFFF +#endif +#if (G84PL >= G87PL) || (G84PL == 0) +#define MG87_14PL ~(1 << 3) +#else +#define MG87_14PL 0xFFFF +#endif +#if (G85PL >= G87PL) || (G85PL == 0) +#define MG87_15PL ~(1 << 4) +#else +#define MG87_15PL 0xFFFF +#endif +#if (G86PL >= G87PL) || (G86PL == 0) +#define MG87_16PL ~(1 << 5) +#else +#define MG87_16PL 0xFFFF +#endif +#if (G88PL >= G87PL) || (G88PL == 0) +#define MG87_18PL ~(1 << 7) +#else +#define MG87_18PL 0xFFFF +#endif +#define MG87_17PL 0x00BF +#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \ + MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL) +// End of MG87: + +// Beginning of MG88: +#if (G81PL >= G88PL) || (G81PL == 0) +#define MG88_11PL ~(1) +#else +#define MG88_11PL 0xFFFF +#endif +#if (G82PL >= G88PL) || (G82PL == 0) +#define MG88_12PL ~(1 << 1) +#else +#define MG88_12PL 0xFFFF +#endif +#if (G83PL >= G88PL) || (G83PL == 0) +#define MG88_13PL ~(1 << 2) +#else +#define MG88_13PL 0xFFFF +#endif +#if (G84PL >= G88PL) || (G84PL == 0) +#define MG88_14PL ~(1 << 3) +#else +#define MG88_14PL 0xFFFF +#endif +#if (G85PL >= G88PL) || (G85PL == 0) +#define MG88_15PL ~(1 << 4) +#else +#define MG88_15PL 0xFFFF +#endif +#if (G86PL >= G88PL) || (G86PL == 0) +#define MG88_16PL ~(1 << 5) +#else +#define MG88_16PL 0xFFFF +#endif +#if (G87PL >= G88PL) || (G87PL == 0) +#define MG88_17PL ~(1 << 6) +#else +#define MG88_17PL 0xFFFF +#endif +#define MG88_18PL 0x007F +#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \ + MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL) +// End of MG88: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG91 to MG98: +// + +// Beginning of MG91: +#if (G92PL >= G91PL) || (G92PL == 0) +#define MG91_12PL ~(1 << 1) +#else +#define MG91_12PL 0xFFFF +#endif +#if (G93PL >= G91PL) || (G93PL == 0) +#define MG91_13PL ~(1 << 2) +#else +#define MG91_13PL 0xFFFF +#endif +#if (G94PL >= G91PL) || (G94PL == 0) +#define MG91_14PL ~(1 << 3) +#else +#define MG91_14PL 0xFFFF +#endif +#if (G95PL >= G91PL) || (G95PL == 0) +#define MG91_15PL ~(1 << 4) +#else +#define MG91_15PL 0xFFFF +#endif +#if (G96PL >= G91PL) || (G96PL == 0) +#define MG91_16PL ~(1 << 5) +#else +#define MG91_16PL 0xFFFF +#endif +#if (G97PL >= G91PL) || (G97PL == 0) +#define MG91_17PL ~(1 << 6) +#else +#define MG91_17PL 0xFFFF +#endif +#if (G98PL >= G91PL) || (G98PL == 0) +#define MG91_18PL ~(1 << 7) +#else +#define MG91_18PL 0xFFFF +#endif +#define MG91_11PL 0x00FE +#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \ + MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL) +// End of MG91: + +// Beginning of MG92: +#if (G91PL >= G92PL) || (G91PL == 0) +#define MG92_11PL ~(1) +#else +#define MG92_11PL 0xFFFF +#endif +#if (G93PL >= G92PL) || (G93PL == 0) +#define MG92_13PL ~(1 << 2) +#else +#define MG92_13PL 0xFFFF +#endif +#if (G94PL >= G92PL) || (G94PL == 0) +#define MG92_14PL ~(1 << 3) +#else +#define MG92_14PL 0xFFFF +#endif +#if (G95PL >= G92PL) || (G95PL == 0) +#define MG92_15PL ~(1 << 4) +#else +#define MG92_15PL 0xFFFF +#endif +#if (G96PL >= G92PL) || (G96PL == 0) +#define MG92_16PL ~(1 << 5) +#else +#define MG92_16PL 0xFFFF +#endif +#if (G97PL >= G92PL) || (G97PL == 0) +#define MG92_17PL ~(1 << 6) +#else +#define MG92_17PL 0xFFFF +#endif +#if (G98PL >= G92PL) || (G98PL == 0) +#define MG92_18PL ~(1 << 7) +#else +#define MG92_18PL 0xFFFF +#endif +#define MG92_12PL 0x00FD +#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \ + MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL) +// End of MG92: + +// Beginning of MG93: +#if (G91PL >= G93PL) || (G91PL == 0) +#define MG93_11PL ~(1) +#else +#define MG93_11PL 0xFFFF +#endif +#if (G92PL >= G93PL) || (G92PL == 0) +#define MG93_12PL ~(1 << 1) +#else +#define MG93_12PL 0xFFFF +#endif +#if (G94PL >= G93PL) || (G94PL == 0) +#define MG93_14PL ~(1 << 3) +#else +#define MG93_14PL 0xFFFF +#endif +#if (G95PL >= G93PL) || (G95PL == 0) +#define MG93_15PL ~(1 << 4) +#else +#define MG93_15PL 0xFFFF +#endif +#if (G96PL >= G93PL) || (G96PL == 0) +#define MG93_16PL ~(1 << 5) +#else +#define MG93_16PL 0xFFFF +#endif +#if (G97PL >= G93PL) || (G97PL == 0) +#define MG93_17PL ~(1 << 6) +#else +#define MG93_17PL 0xFFFF +#endif +#if (G98PL >= G93PL) || (G98PL == 0) +#define MG93_18PL ~(1 << 7) +#else +#define MG93_18PL 0xFFFF +#endif +#define MG93_13PL 0x00FB +#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \ + MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL) +// End of MG93: + +// Beginning of MG94: +#if (G91PL >= G94PL) || (G91PL == 0) +#define MG94_11PL ~(1) +#else +#define MG94_11PL 0xFFFF +#endif +#if (G92PL >= G94PL) || (G92PL == 0) +#define MG94_12PL ~(1 << 1) +#else +#define MG94_12PL 0xFFFF +#endif +#if (G93PL >= G94PL) || (G93PL == 0) +#define MG94_13PL ~(1 << 2) +#else +#define MG94_13PL 0xFFFF +#endif +#if (G95PL >= G94PL) || (G95PL == 0) +#define MG94_15PL ~(1 << 4) +#else +#define MG94_15PL 0xFFFF +#endif +#if (G96PL >= G94PL) || (G96PL == 0) +#define MG94_16PL ~(1 << 5) +#else +#define MG94_16PL 0xFFFF +#endif +#if (G97PL >= G94PL) || (G97PL == 0) +#define MG94_17PL ~(1 << 6) +#else +#define MG94_17PL 0xFFFF +#endif +#if (G98PL >= G94PL) || (G98PL == 0) +#define MG94_18PL ~(1 << 7) +#else +#define MG94_18PL 0xFFFF +#endif +#define MG94_14PL 0x00F7 +#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \ + MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL) +// End of MG94: + +// Beginning of MG95: +#if (G91PL >= G95PL) || (G91PL == 0) +#define MG95_11PL ~(1) +#else +#define MG95_11PL 0xFFFF +#endif +#if (G92PL >= G95PL) || (G92PL == 0) +#define MG95_12PL ~(1 << 1) +#else +#define MG95_12PL 0xFFFF +#endif +#if (G93PL >= G95PL) || (G93PL == 0) +#define MG95_13PL ~(1 << 2) +#else +#define MG95_13PL 0xFFFF +#endif +#if (G94PL >= G95PL) || (G94PL == 0) +#define MG95_14PL ~(1 << 3) +#else +#define MG95_14PL 0xFFFF +#endif +#if (G96PL >= G95PL) || (G96PL == 0) +#define MG95_16PL ~(1 << 5) +#else +#define MG95_16PL 0xFFFF +#endif +#if (G97PL >= G95PL) || (G97PL == 0) +#define MG95_17PL ~(1 << 6) +#else +#define MG95_17PL 0xFFFF +#endif +#if (G98PL >= G95PL) || (G98PL == 0) +#define MG95_18PL ~(1 << 7) +#else +#define MG95_18PL 0xFFFF +#endif +#define MG95_15PL 0x00EF +#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \ + MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL) +// End of MG95: + +// Beginning of MG96: +#if (G91PL >= G96PL) || (G91PL == 0) +#define MG96_11PL ~(1) +#else +#define MG96_11PL 0xFFFF +#endif +#if (G92PL >= G96PL) || (G92PL == 0) +#define MG96_12PL ~(1 << 1) +#else +#define MG96_12PL 0xFFFF +#endif +#if (G93PL >= G96PL) || (G93PL == 0) +#define MG96_13PL ~(1 << 2) +#else +#define MG96_13PL 0xFFFF +#endif +#if (G94PL >= G96PL) || (G94PL == 0) +#define MG96_14PL ~(1 << 3) +#else +#define MG96_14PL 0xFFFF +#endif +#if (G95PL >= G96PL) || (G95PL == 0) +#define MG96_15PL ~(1 << 4) +#else +#define MG96_15PL 0xFFFF +#endif +#if (G97PL >= G96PL) || (G97PL == 0) +#define MG96_17PL ~(1 << 6) +#else +#define MG96_17PL 0xFFFF +#endif +#if (G98PL >= G96PL) || (G98PL == 0) +#define MG96_18PL ~(1 << 7) +#else +#define MG96_18PL 0xFFFF +#endif +#define MG96_16PL 0x00DF +#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \ + MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL) +// End of MG96: + +// Beginning of MG97: +#if (G91PL >= G97PL) || (G91PL == 0) +#define MG97_11PL ~(1) +#else +#define MG97_11PL 0xFFFF +#endif +#if (G92PL >= G97PL) || (G92PL == 0) +#define MG97_12PL ~(1 << 1) +#else +#define MG97_12PL 0xFFFF +#endif +#if (G93PL >= G97PL) || (G93PL == 0) +#define MG97_13PL ~(1 << 2) +#else +#define MG97_13PL 0xFFFF +#endif +#if (G94PL >= G97PL) || (G94PL == 0) +#define MG97_14PL ~(1 << 3) +#else +#define MG97_14PL 0xFFFF +#endif +#if (G95PL >= G97PL) || (G95PL == 0) +#define MG97_15PL ~(1 << 4) +#else +#define MG97_15PL 0xFFFF +#endif +#if (G96PL >= G97PL) || (G96PL == 0) +#define MG97_16PL ~(1 << 5) +#else +#define MG97_16PL 0xFFFF +#endif +#if (G98PL >= G97PL) || (G98PL == 0) +#define MG97_18PL ~(1 << 7) +#else +#define MG97_18PL 0xFFFF +#endif +#define MG97_17PL 0x00BF +#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \ + MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL) +// End of MG97: + +// Beginning of MG98: +#if (G91PL >= G98PL) || (G91PL == 0) +#define MG98_11PL ~(1) +#else +#define MG98_11PL 0xFFFF +#endif +#if (G92PL >= G98PL) || (G92PL == 0) +#define MG98_12PL ~(1 << 1) +#else +#define MG98_12PL 0xFFFF +#endif +#if (G93PL >= G98PL) || (G93PL == 0) +#define MG98_13PL ~(1 << 2) +#else +#define MG98_13PL 0xFFFF +#endif +#if (G94PL >= G98PL) || (G94PL == 0) +#define MG98_14PL ~(1 << 3) +#else +#define MG98_14PL 0xFFFF +#endif +#if (G95PL >= G98PL) || (G95PL == 0) +#define MG98_15PL ~(1 << 4) +#else +#define MG98_15PL 0xFFFF +#endif +#if (G96PL >= G98PL) || (G96PL == 0) +#define MG98_16PL ~(1 << 5) +#else +#define MG98_16PL 0xFFFF +#endif +#if (G97PL >= G98PL) || (G97PL == 0) +#define MG98_17PL ~(1 << 6) +#else +#define MG98_17PL 0xFFFF +#endif +#define MG98_18PL 0x007F +#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \ + MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL) +// End of MG98: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG101 to MG108: +// + +// Beginning of MG101: +#if (G102PL >= G101PL) || (G102PL == 0) +#define MG101_12PL ~(1 << 1) +#else +#define MG101_12PL 0xFFFF +#endif +#if (G103PL >= G101PL) || (G103PL == 0) +#define MG101_13PL ~(1 << 2) +#else +#define MG101_13PL 0xFFFF +#endif +#if (G104PL >= G101PL) || (G104PL == 0) +#define MG101_14PL ~(1 << 3) +#else +#define MG101_14PL 0xFFFF +#endif +#if (G105PL >= G101PL) || (G105PL == 0) +#define MG101_15PL ~(1 << 4) +#else +#define MG101_15PL 0xFFFF +#endif +#if (G106PL >= G101PL) || (G106PL == 0) +#define MG101_16PL ~(1 << 5) +#else +#define MG101_16PL 0xFFFF +#endif +#if (G107PL >= G101PL) || (G107PL == 0) +#define MG101_17PL ~(1 << 6) +#else +#define MG101_17PL 0xFFFF +#endif +#if (G108PL >= G101PL) || (G108PL == 0) +#define MG101_18PL ~(1 << 7) +#else +#define MG101_18PL 0xFFFF +#endif +#define MG101_11PL 0x00FE +#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \ + MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL) +// End of MG101: + +// Beginning of MG102: +#if (G101PL >= G102PL) || (G101PL == 0) +#define MG102_11PL ~(1) +#else +#define MG102_11PL 0xFFFF +#endif +#if (G103PL >= G102PL) || (G103PL == 0) +#define MG102_13PL ~(1 << 2) +#else +#define MG102_13PL 0xFFFF +#endif +#if (G104PL >= G102PL) || (G104PL == 0) +#define MG102_14PL ~(1 << 3) +#else +#define MG102_14PL 0xFFFF +#endif +#if (G105PL >= G102PL) || (G105PL == 0) +#define MG102_15PL ~(1 << 4) +#else +#define MG102_15PL 0xFFFF +#endif +#if (G106PL >= G102PL) || (G106PL == 0) +#define MG102_16PL ~(1 << 5) +#else +#define MG102_16PL 0xFFFF +#endif +#if (G107PL >= G102PL) || (G107PL == 0) +#define MG102_17PL ~(1 << 6) +#else +#define MG102_17PL 0xFFFF +#endif +#if (G108PL >= G102PL) || (G108PL == 0) +#define MG102_18PL ~(1 << 7) +#else +#define MG102_18PL 0xFFFF +#endif +#define MG102_12PL 0x00FD +#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \ + MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL) +// End of MG102: + +// Beginning of MG103: +#if (G101PL >= G103PL) || (G101PL == 0) +#define MG103_11PL ~(1) +#else +#define MG103_11PL 0xFFFF +#endif +#if (G102PL >= G103PL) || (G102PL == 0) +#define MG103_12PL ~(1 << 1) +#else +#define MG103_12PL 0xFFFF +#endif +#if (G104PL >= G103PL) || (G104PL == 0) +#define MG103_14PL ~(1 << 3) +#else +#define MG103_14PL 0xFFFF +#endif +#if (G105PL >= G103PL) || (G105PL == 0) +#define MG103_15PL ~(1 << 4) +#else +#define MG103_15PL 0xFFFF +#endif +#if (G106PL >= G103PL) || (G106PL == 0) +#define MG103_16PL ~(1 << 5) +#else +#define MG103_16PL 0xFFFF +#endif +#if (G107PL >= G103PL) || (G107PL == 0) +#define MG103_17PL ~(1 << 6) +#else +#define MG103_17PL 0xFFFF +#endif +#if (G108PL >= G103PL) || (G108PL == 0) +#define MG103_18PL ~(1 << 7) +#else +#define MG103_18PL 0xFFFF +#endif +#define MG103_13PL 0x00FB +#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \ + MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL) +// End of MG103: + +// Beginning of MG104: +#if (G101PL >= G104PL) || (G101PL == 0) +#define MG104_11PL ~(1) +#else +#define MG104_11PL 0xFFFF +#endif +#if (G102PL >= G104PL) || (G102PL == 0) +#define MG104_12PL ~(1 << 1) +#else +#define MG104_12PL 0xFFFF +#endif +#if (G103PL >= G104PL) || (G103PL == 0) +#define MG104_13PL ~(1 << 2) +#else +#define MG104_13PL 0xFFFF +#endif +#if (G105PL >= G104PL) || (G105PL == 0) +#define MG104_15PL ~(1 << 4) +#else +#define MG104_15PL 0xFFFF +#endif +#if (G106PL >= G104PL) || (G106PL == 0) +#define MG104_16PL ~(1 << 5) +#else +#define MG104_16PL 0xFFFF +#endif +#if (G107PL >= G104PL) || (G107PL == 0) +#define MG104_17PL ~(1 << 6) +#else +#define MG104_17PL 0xFFFF +#endif +#if (G108PL >= G104PL) || (G108PL == 0) +#define MG104_18PL ~(1 << 7) +#else +#define MG104_18PL 0xFFFF +#endif +#define MG104_14PL 0x00F7 +#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \ + MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL) +// End of MG104: + +// Beginning of MG105: +#if (G101PL >= G105PL) || (G101PL == 0) +#define MG105_11PL ~(1) +#else +#define MG105_11PL 0xFFFF +#endif +#if (G102PL >= G105PL) || (G102PL == 0) +#define MG105_12PL ~(1 << 1) +#else +#define MG105_12PL 0xFFFF +#endif +#if (G103PL >= G105PL) || (G103PL == 0) +#define MG105_13PL ~(1 << 2) +#else +#define MG105_13PL 0xFFFF +#endif +#if (G104PL >= G105PL) || (G104PL == 0) +#define MG105_14PL ~(1 << 3) +#else +#define MG105_14PL 0xFFFF +#endif +#if (G106PL >= G105PL) || (G106PL == 0) +#define MG105_16PL ~(1 << 5) +#else +#define MG105_16PL 0xFFFF +#endif +#if (G107PL >= G105PL) || (G107PL == 0) +#define MG105_17PL ~(1 << 6) +#else +#define MG105_17PL 0xFFFF +#endif +#if (G108PL >= G105PL) || (G108PL == 0) +#define MG105_18PL ~(1 << 7) +#else +#define MG105_18PL 0xFFFF +#endif +#define MG105_15PL 0x00EF +#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \ + MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL) +// End of MG105: + +// Beginning of MG106: +#if (G101PL >= G106PL) || (G101PL == 0) +#define MG106_11PL ~(1) +#else +#define MG106_11PL 0xFFFF +#endif +#if (G102PL >= G106PL) || (G102PL == 0) +#define MG106_12PL ~(1 << 1) +#else +#define MG106_12PL 0xFFFF +#endif +#if (G103PL >= G106PL) || (G103PL == 0) +#define MG106_13PL ~(1 << 2) +#else +#define MG106_13PL 0xFFFF +#endif +#if (G104PL >= G106PL) || (G104PL == 0) +#define MG106_14PL ~(1 << 3) +#else +#define MG106_14PL 0xFFFF +#endif +#if (G105PL >= G106PL) || (G105PL == 0) +#define MG106_15PL ~(1 << 4) +#else +#define MG106_15PL 0xFFFF +#endif +#if (G107PL >= G106PL) || (G107PL == 0) +#define MG106_17PL ~(1 << 6) +#else +#define MG106_17PL 0xFFFF +#endif +#if (G108PL >= G106PL) || (G108PL == 0) +#define MG106_18PL ~(1 << 7) +#else +#define MG106_18PL 0xFFFF +#endif +#define MG106_16PL 0x00DF +#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \ + MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL) +// End of MG106: + +// Beginning of MG107: +#if (G101PL >= G107PL) || (G101PL == 0) +#define MG107_11PL ~(1) +#else +#define MG107_11PL 0xFFFF +#endif +#if (G102PL >= G107PL) || (G102PL == 0) +#define MG107_12PL ~(1 << 1) +#else +#define MG107_12PL 0xFFFF +#endif +#if (G103PL >= G107PL) || (G103PL == 0) +#define MG107_13PL ~(1 << 2) +#else +#define MG107_13PL 0xFFFF +#endif +#if (G104PL >= G107PL) || (G104PL == 0) +#define MG107_14PL ~(1 << 3) +#else +#define MG107_14PL 0xFFFF +#endif +#if (G105PL >= G107PL) || (G105PL == 0) +#define MG107_15PL ~(1 << 4) +#else +#define MG107_15PL 0xFFFF +#endif +#if (G106PL >= G107PL) || (G106PL == 0) +#define MG107_16PL ~(1 << 5) +#else +#define MG107_16PL 0xFFFF +#endif +#if (G108PL >= G107PL) || (G108PL == 0) +#define MG107_18PL ~(1 << 7) +#else +#define MG107_18PL 0xFFFF +#endif +#define MG107_17PL 0x00BF +#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \ + MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL) +// End of MG107: + +// Beginning of MG108: +#if (G101PL >= G108PL) || (G101PL == 0) +#define MG108_11PL ~(1) +#else +#define MG108_11PL 0xFFFF +#endif +#if (G102PL >= G108PL) || (G102PL == 0) +#define MG108_12PL ~(1 << 1) +#else +#define MG108_12PL 0xFFFF +#endif +#if (G103PL >= G108PL) || (G103PL == 0) +#define MG108_13PL ~(1 << 2) +#else +#define MG108_13PL 0xFFFF +#endif +#if (G104PL >= G108PL) || (G104PL == 0) +#define MG108_14PL ~(1 << 3) +#else +#define MG108_14PL 0xFFFF +#endif +#if (G105PL >= G108PL) || (G105PL == 0) +#define MG108_15PL ~(1 << 4) +#else +#define MG108_15PL 0xFFFF +#endif +#if (G106PL >= G108PL) || (G106PL == 0) +#define MG108_16PL ~(1 << 5) +#else +#define MG108_16PL 0xFFFF +#endif +#if (G107PL >= G108PL) || (G107PL == 0) +#define MG108_17PL ~(1 << 6) +#else +#define MG108_17PL 0xFFFF +#endif +#define MG108_18PL 0x007F +#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \ + MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL) +// End of MG108: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG111 to MG118: +// + +// Beginning of MG111: +#if (G112PL >= G111PL) || (G112PL == 0) +#define MG111_12PL ~(1 << 1) +#else +#define MG111_12PL 0xFFFF +#endif +#if (G113PL >= G111PL) || (G113PL == 0) +#define MG111_13PL ~(1 << 2) +#else +#define MG111_13PL 0xFFFF +#endif +#if (G114PL >= G111PL) || (G114PL == 0) +#define MG111_14PL ~(1 << 3) +#else +#define MG111_14PL 0xFFFF +#endif +#if (G115PL >= G111PL) || (G115PL == 0) +#define MG111_15PL ~(1 << 4) +#else +#define MG111_15PL 0xFFFF +#endif +#if (G116PL >= G111PL) || (G116PL == 0) +#define MG111_16PL ~(1 << 5) +#else +#define MG111_16PL 0xFFFF +#endif +#if (G117PL >= G111PL) || (G117PL == 0) +#define MG111_17PL ~(1 << 6) +#else +#define MG111_17PL 0xFFFF +#endif +#if (G118PL >= G111PL) || (G118PL == 0) +#define MG111_18PL ~(1 << 7) +#else +#define MG111_18PL 0xFFFF +#endif +#define MG111_11PL 0x00FE +#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \ + MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL) +// End of MG111: + +// Beginning of MG112: +#if (G111PL >= G112PL) || (G111PL == 0) +#define MG112_11PL ~(1) +#else +#define MG112_11PL 0xFFFF +#endif +#if (G113PL >= G112PL) || (G113PL == 0) +#define MG112_13PL ~(1 << 2) +#else +#define MG112_13PL 0xFFFF +#endif +#if (G114PL >= G112PL) || (G114PL == 0) +#define MG112_14PL ~(1 << 3) +#else +#define MG112_14PL 0xFFFF +#endif +#if (G115PL >= G112PL) || (G115PL == 0) +#define MG112_15PL ~(1 << 4) +#else +#define MG112_15PL 0xFFFF +#endif +#if (G116PL >= G112PL) || (G116PL == 0) +#define MG112_16PL ~(1 << 5) +#else +#define MG112_16PL 0xFFFF +#endif +#if (G117PL >= G112PL) || (G117PL == 0) +#define MG112_17PL ~(1 << 6) +#else +#define MG112_17PL 0xFFFF +#endif +#if (G118PL >= G112PL) || (G118PL == 0) +#define MG112_18PL ~(1 << 7) +#else +#define MG112_18PL 0xFFFF +#endif +#define MG112_12PL 0x00FD +#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \ + MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL) +// End of MG112: + +// Beginning of MG113: +#if (G111PL >= G113PL) || (G111PL == 0) +#define MG113_11PL ~(1) +#else +#define MG113_11PL 0xFFFF +#endif +#if (G112PL >= G113PL) || (G112PL == 0) +#define MG113_12PL ~(1 << 1) +#else +#define MG113_12PL 0xFFFF +#endif +#if (G114PL >= G113PL) || (G114PL == 0) +#define MG113_14PL ~(1 << 3) +#else +#define MG113_14PL 0xFFFF +#endif +#if (G115PL >= G113PL) || (G115PL == 0) +#define MG113_15PL ~(1 << 4) +#else +#define MG113_15PL 0xFFFF +#endif +#if (G116PL >= G113PL) || (G116PL == 0) +#define MG113_16PL ~(1 << 5) +#else +#define MG113_16PL 0xFFFF +#endif +#if (G117PL >= G113PL) || (G117PL == 0) +#define MG113_17PL ~(1 << 6) +#else +#define MG113_17PL 0xFFFF +#endif +#if (G118PL >= G113PL) || (G118PL == 0) +#define MG113_18PL ~(1 << 7) +#else +#define MG113_18PL 0xFFFF +#endif +#define MG113_13PL 0x00FB +#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \ + MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL) +// End of MG113: + +// Beginning of MG114: +#if (G111PL >= G114PL) || (G111PL == 0) +#define MG114_11PL ~(1) +#else +#define MG114_11PL 0xFFFF +#endif +#if (G112PL >= G114PL) || (G112PL == 0) +#define MG114_12PL ~(1 << 1) +#else +#define MG114_12PL 0xFFFF +#endif +#if (G113PL >= G114PL) || (G113PL == 0) +#define MG114_13PL ~(1 << 2) +#else +#define MG114_13PL 0xFFFF +#endif +#if (G115PL >= G114PL) || (G115PL == 0) +#define MG114_15PL ~(1 << 4) +#else +#define MG114_15PL 0xFFFF +#endif +#if (G116PL >= G114PL) || (G116PL == 0) +#define MG114_16PL ~(1 << 5) +#else +#define MG114_16PL 0xFFFF +#endif +#if (G117PL >= G114PL) || (G117PL == 0) +#define MG114_17PL ~(1 << 6) +#else +#define MG114_17PL 0xFFFF +#endif +#if (G118PL >= G114PL) || (G118PL == 0) +#define MG114_18PL ~(1 << 7) +#else +#define MG114_18PL 0xFFFF +#endif +#define MG114_14PL 0x00F7 +#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \ + MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL) +// End of MG114: + +// Beginning of MG115: +#if (G111PL >= G115PL) || (G111PL == 0) +#define MG115_11PL ~(1) +#else +#define MG115_11PL 0xFFFF +#endif +#if (G112PL >= G115PL) || (G112PL == 0) +#define MG115_12PL ~(1 << 1) +#else +#define MG115_12PL 0xFFFF +#endif +#if (G113PL >= G115PL) || (G113PL == 0) +#define MG115_13PL ~(1 << 2) +#else +#define MG115_13PL 0xFFFF +#endif +#if (G114PL >= G115PL) || (G114PL == 0) +#define MG115_14PL ~(1 << 3) +#else +#define MG115_14PL 0xFFFF +#endif +#if (G116PL >= G115PL) || (G116PL == 0) +#define MG115_16PL ~(1 << 5) +#else +#define MG115_16PL 0xFFFF +#endif +#if (G117PL >= G115PL) || (G117PL == 0) +#define MG115_17PL ~(1 << 6) +#else +#define MG115_17PL 0xFFFF +#endif +#if (G118PL >= G115PL) || (G118PL == 0) +#define MG115_18PL ~(1 << 7) +#else +#define MG115_18PL 0xFFFF +#endif +#define MG115_15PL 0x00EF +#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \ + MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL) +// End of MG115: + +// Beginning of MG116: +#if (G111PL >= G116PL) || (G111PL == 0) +#define MG116_11PL ~(1) +#else +#define MG116_11PL 0xFFFF +#endif +#if (G112PL >= G116PL) || (G112PL == 0) +#define MG116_12PL ~(1 << 1) +#else +#define MG116_12PL 0xFFFF +#endif +#if (G113PL >= G116PL) || (G113PL == 0) +#define MG116_13PL ~(1 << 2) +#else +#define MG116_13PL 0xFFFF +#endif +#if (G114PL >= G116PL) || (G114PL == 0) +#define MG116_14PL ~(1 << 3) +#else +#define MG116_14PL 0xFFFF +#endif +#if (G115PL >= G116PL) || (G115PL == 0) +#define MG116_15PL ~(1 << 4) +#else +#define MG116_15PL 0xFFFF +#endif +#if (G117PL >= G116PL) || (G117PL == 0) +#define MG116_17PL ~(1 << 6) +#else +#define MG116_17PL 0xFFFF +#endif +#if (G118PL >= G116PL) || (G118PL == 0) +#define MG116_18PL ~(1 << 7) +#else +#define MG116_18PL 0xFFFF +#endif +#define MG116_16PL 0x00DF +#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \ + MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL) +// End of MG116: + +// Beginning of MG117: +#if (G111PL >= G117PL) || (G111PL == 0) +#define MG117_11PL ~(1) +#else +#define MG117_11PL 0xFFFF +#endif +#if (G112PL >= G117PL) || (G112PL == 0) +#define MG117_12PL ~(1 << 1) +#else +#define MG117_12PL 0xFFFF +#endif +#if (G113PL >= G117PL) || (G113PL == 0) +#define MG117_13PL ~(1 << 2) +#else +#define MG117_13PL 0xFFFF +#endif +#if (G114PL >= G117PL) || (G114PL == 0) +#define MG117_14PL ~(1 << 3) +#else +#define MG117_14PL 0xFFFF +#endif +#if (G115PL >= G117PL) || (G115PL == 0) +#define MG117_15PL ~(1 << 4) +#else +#define MG117_15PL 0xFFFF +#endif +#if (G116PL >= G117PL) || (G116PL == 0) +#define MG117_16PL ~(1 << 5) +#else +#define MG117_16PL 0xFFFF +#endif +#if (G118PL >= G117PL) || (G118PL == 0) +#define MG117_18PL ~(1 << 7) +#else +#define MG117_18PL 0xFFFF +#endif +#define MG117_17PL 0x00BF +#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \ + MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL) +// End of MG117: + +// Beginning of MG118: +#if (G111PL >= G118PL) || (G111PL == 0) +#define MG118_11PL ~(1) +#else +#define MG118_11PL 0xFFFF +#endif +#if (G112PL >= G118PL) || (G112PL == 0) +#define MG118_12PL ~(1 << 1) +#else +#define MG118_12PL 0xFFFF +#endif +#if (G113PL >= G118PL) || (G113PL == 0) +#define MG118_13PL ~(1 << 2) +#else +#define MG118_13PL 0xFFFF +#endif +#if (G114PL >= G118PL) || (G114PL == 0) +#define MG118_14PL ~(1 << 3) +#else +#define MG118_14PL 0xFFFF +#endif +#if (G115PL >= G118PL) || (G115PL == 0) +#define MG118_15PL ~(1 << 4) +#else +#define MG118_15PL 0xFFFF +#endif +#if (G116PL >= G118PL) || (G116PL == 0) +#define MG118_16PL ~(1 << 5) +#else +#define MG118_16PL 0xFFFF +#endif +#if (G117PL >= G118PL) || (G117PL == 0) +#define MG118_17PL ~(1 << 6) +#else +#define MG118_17PL 0xFFFF +#endif +#define MG118_18PL 0x007F +#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \ + MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL) +// End of MG118: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG121 to MG128: +// + +// Beginning of MG121: +#if (G122PL >= G121PL) || (G122PL == 0) +#define MG121_12PL ~(1 << 1) +#else +#define MG121_12PL 0xFFFF +#endif +#if (G123PL >= G121PL) || (G123PL == 0) +#define MG121_13PL ~(1 << 2) +#else +#define MG121_13PL 0xFFFF +#endif +#if (G124PL >= G121PL) || (G124PL == 0) +#define MG121_14PL ~(1 << 3) +#else +#define MG121_14PL 0xFFFF +#endif +#if (G125PL >= G121PL) || (G125PL == 0) +#define MG121_15PL ~(1 << 4) +#else +#define MG121_15PL 0xFFFF +#endif +#if (G126PL >= G121PL) || (G126PL == 0) +#define MG121_16PL ~(1 << 5) +#else +#define MG121_16PL 0xFFFF +#endif +#if (G127PL >= G121PL) || (G127PL == 0) +#define MG121_17PL ~(1 << 6) +#else +#define MG121_17PL 0xFFFF +#endif +#if (G128PL >= G121PL) || (G128PL == 0) +#define MG121_18PL ~(1 << 7) +#else +#define MG121_18PL 0xFFFF +#endif +#define MG121_11PL 0x00FE +#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \ + MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL) +// End of MG121: + +// Beginning of MG121: +#if (G121PL >= G122PL) || (G121PL == 0) +#define MG122_11PL ~(1) +#else +#define MG122_11PL 0xFFFF +#endif +#if (G123PL >= G122PL) || (G123PL == 0) +#define MG122_13PL ~(1 << 2) +#else +#define MG122_13PL 0xFFFF +#endif +#if (G124PL >= G122PL) || (G124PL == 0) +#define MG122_14PL ~(1 << 3) +#else +#define MG122_14PL 0xFFFF +#endif +#if (G125PL >= G122PL) || (G125PL == 0) +#define MG122_15PL ~(1 << 4) +#else +#define MG122_15PL 0xFFFF +#endif +#if (G126PL >= G122PL) || (G126PL == 0) +#define MG122_16PL ~(1 << 5) +#else +#define MG122_16PL 0xFFFF +#endif +#if (G127PL >= G122PL) || (G127PL == 0) +#define MG122_17PL ~(1 << 6) +#else +#define MG122_17PL 0xFFFF +#endif +#if (G128PL >= G122PL) || (G128PL == 0) +#define MG122_18PL ~(1 << 7) +#else +#define MG122_18PL 0xFFFF +#endif +#define MG122_12PL 0x00FD +#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \ + MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL) +// End of MG122: + +// Beginning of MG123: +#if (G121PL >= G123PL) || (G121PL == 0) +#define MG123_11PL ~(1) +#else +#define MG123_11PL 0xFFFF +#endif +#if (G122PL >= G123PL) || (G122PL == 0) +#define MG123_12PL ~(1 << 1) +#else +#define MG123_12PL 0xFFFF +#endif +#if (G124PL >= G123PL) || (G124PL == 0) +#define MG123_14PL ~(1 << 3) +#else +#define MG123_14PL 0xFFFF +#endif +#if (G125PL >= G123PL) || (G125PL == 0) +#define MG123_15PL ~(1 << 4) +#else +#define MG123_15PL 0xFFFF +#endif +#if (G126PL >= G123PL) || (G126PL == 0) +#define MG123_16PL ~(1 << 5) +#else +#define MG123_16PL 0xFFFF +#endif +#if (G127PL >= G123PL) || (G127PL == 0) +#define MG123_17PL ~(1 << 6) +#else +#define MG123_17PL 0xFFFF +#endif +#if (G128PL >= G123PL) || (G128PL == 0) +#define MG123_18PL ~(1 << 7) +#else +#define MG123_18PL 0xFFFF +#endif +#define MG123_13PL 0x00FB +#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \ + MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL) +// End of MG123: + +// Beginning of MG124: +#if (G121PL >= G124PL) || (G121PL == 0) +#define MG124_11PL ~(1) +#else +#define MG124_11PL 0xFFFF +#endif +#if (G122PL >= G124PL) || (G122PL == 0) +#define MG124_12PL ~(1 << 1) +#else +#define MG124_12PL 0xFFFF +#endif +#if (G123PL >= G124PL) || (G123PL == 0) +#define MG124_13PL ~(1 << 2) +#else +#define MG124_13PL 0xFFFF +#endif +#if (G125PL >= G124PL) || (G125PL == 0) +#define MG124_15PL ~(1 << 4) +#else +#define MG124_15PL 0xFFFF +#endif +#if (G126PL >= G124PL) || (G126PL == 0) +#define MG124_16PL ~(1 << 5) +#else +#define MG124_16PL 0xFFFF +#endif +#if (G127PL >= G124PL) || (G127PL == 0) +#define MG124_17PL ~(1 << 6) +#else +#define MG124_17PL 0xFFFF +#endif +#if (G128PL >= G124PL) || (G128PL == 0) +#define MG124_18PL ~(1 << 7) +#else +#define MG124_18PL 0xFFFF +#endif +#define MG124_14PL 0x00F7 +#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \ + MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL) +// End of MG124: + +// Beginning of MG125: +#if (G121PL >= G125PL) || (G121PL == 0) +#define MG125_11PL ~(1) +#else +#define MG125_11PL 0xFFFF +#endif +#if (G122PL >= G125PL) || (G122PL == 0) +#define MG125_12PL ~(1 << 1) +#else +#define MG125_12PL 0xFFFF +#endif +#if (G123PL >= G125PL) || (G123PL == 0) +#define MG125_13PL ~(1 << 2) +#else +#define MG125_13PL 0xFFFF +#endif +#if (G124PL >= G125PL) || (G124PL == 0) +#define MG125_14PL ~(1 << 3) +#else +#define MG125_14PL 0xFFFF +#endif +#if (G126PL >= G125PL) || (G126PL == 0) +#define MG125_16PL ~(1 << 5) +#else +#define MG125_16PL 0xFFFF +#endif +#if (G127PL >= G125PL) || (G127PL == 0) +#define MG125_17PL ~(1 << 6) +#else +#define MG125_17PL 0xFFFF +#endif +#if (G128PL >= G125PL) || (G128PL == 0) +#define MG125_18PL ~(1 << 7) +#else +#define MG125_18PL 0xFFFF +#endif +#define MG125_15PL 0x00EF +#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \ + MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL) +// End of MG125: + +// Beginning of MG126: +#if (G121PL >= G126PL) || (G121PL == 0) +#define MG126_11PL ~(1) +#else +#define MG126_11PL 0xFFFF +#endif +#if (G122PL >= G126PL) || (G122PL == 0) +#define MG126_12PL ~(1 << 1) +#else +#define MG126_12PL 0xFFFF +#endif +#if (G123PL >= G126PL) || (G123PL == 0) +#define MG126_13PL ~(1 << 2) +#else +#define MG126_13PL 0xFFFF +#endif +#if (G124PL >= G126PL) || (G124PL == 0) +#define MG126_14PL ~(1 << 3) +#else +#define MG126_14PL 0xFFFF +#endif +#if (G125PL >= G126PL) || (G125PL == 0) +#define MG126_15PL ~(1 << 4) +#else +#define MG126_15PL 0xFFFF +#endif +#if (G127PL >= G126PL) || (G127PL == 0) +#define MG126_17PL ~(1 << 6) +#else +#define MG126_17PL 0xFFFF +#endif +#if (G128PL >= G126PL) || (G128PL == 0) +#define MG126_18PL ~(1 << 7) +#else +#define MG126_18PL 0xFFFF +#endif +#define MG126_16PL 0x00DF +#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \ + MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL) +// End of MG126: + +// Beginning of MG127: +#if (G121PL >= G127PL) || (G121PL == 0) +#define MG127_11PL ~(1) +#else +#define MG127_11PL 0xFFFF +#endif +#if (G122PL >= G127PL) || (G122PL == 0) +#define MG127_12PL ~(1 << 1) +#else +#define MG127_12PL 0xFFFF +#endif +#if (G123PL >= G127PL) || (G123PL == 0) +#define MG127_13PL ~(1 << 2) +#else +#define MG127_13PL 0xFFFF +#endif +#if (G124PL >= G127PL) || (G124PL == 0) +#define MG127_14PL ~(1 << 3) +#else +#define MG127_14PL 0xFFFF +#endif +#if (G125PL >= G127PL) || (G125PL == 0) +#define MG127_15PL ~(1 << 4) +#else +#define MG127_15PL 0xFFFF +#endif +#if (G126PL >= G127PL) || (G126PL == 0) +#define MG127_16PL ~(1 << 5) +#else +#define MG127_16PL 0xFFFF +#endif +#if (G128PL >= G127PL) || (G128PL == 0) +#define MG127_18PL ~(1 << 7) +#else +#define MG127_18PL 0xFFFF +#endif +#define MG127_17PL 0x00BF +#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \ + MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL) +// End of MG127: + +// Beginning of MG128: +#if (G121PL >= G128PL) || (G121PL == 0) +#define MG128_11PL ~(1) +#else +#define MG128_11PL 0xFFFF +#endif +#if (G122PL >= G128PL) || (G122PL == 0) +#define MG128_12PL ~(1 << 1) +#else +#define MG128_12PL 0xFFFF +#endif +#if (G123PL >= G128PL) || (G123PL == 0) +#define MG128_13PL ~(1 << 2) +#else +#define MG128_13PL 0xFFFF +#endif +#if (G124PL >= G128PL) || (G124PL == 0) +#define MG128_14PL ~(1 << 3) +#else +#define MG128_14PL 0xFFFF +#endif +#if (G125PL >= G128PL) || (G125PL == 0) +#define MG128_15PL ~(1 << 4) +#else +#define MG128_15PL 0xFFFF +#endif +#if (G126PL >= G128PL) || (G126PL == 0) +#define MG128_16PL ~(1 << 5) +#else +#define MG128_16PL 0xFFFF +#endif +#if (G127PL >= G128PL) || (G127PL == 0) +#define MG128_17PL ~(1 << 6) +#else +#define MG128_17PL 0xFFFF +#endif +#define MG128_18PL 0x007F +#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \ + MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL) +// End of MG128: + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP28x_Project.h b/v120/DSP2833x_common/include/DSP28x_Project.h new file mode 100644 index 0000000..399c1db --- /dev/null +++ b/v120/DSP2833x_common/include/DSP28x_Project.h @@ -0,0 +1,22 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/v120/DSP2833x_common/include/IQmathLib.h b/v120/DSP2833x_common/include/IQmathLib.h new file mode 100644 index 0000000..b62ddf8 --- /dev/null +++ b/v120/DSP2833x_common/include/IQmathLib.h @@ -0,0 +1,4493 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: July 10, 2008 10:59:52 $ +//########################################################################### +// +// FILE: IQmathLib.h +// +// TITLE: IQ Math library functions definitions. +// +//########################################################################### +// +// Ver | dd-mmm-yyyy | Who | Description of changes +// =====|=============|=======|============================================== +// 1.3 | 19 Nov 2001 | A. T. | Original Release. +// -----|-------------|-------|---------------------------------------------- +// 1.4 | 17 May 2002 | A. T. | Added new functions and support for +// | | | intrinsics IQmpy, IQxmpy, IQsat. +// -----|-------------|-------|---------------------------------------------- +// 1.4a| 12 Jun 2002 | A. T. | Fixed problem with _IQ() operation on +// | | | variables. +// -----|-------------|-------|---------------------------------------------- +// 1.4b| 18 Jun 2002 | A. T. | Fixed bug with _IQtoIQN() and _IQNtoIQ() +// | | | operations. +// -----|-------------|-------|---------------------------------------------- +// 1.4d| 30 Mar 2003 | DA/SD | 1. Added macro parameters in parentheses +// | | | in number of places where it matters +// | | | 2. Added macro definition to include header +// | | | file multiple times in the program. +// -----|-------------|-------|---------------------------------------------- +// 1.4e| 17 Jun 2004 | AT/DA | Added IQexp function. +// | | | Added IQasin & IQacos functions (thanks DA). +// -----|-------------|-------|---------------------------------------------- +// 1.4f| 10 Mar 2005 | AT | Fixed Bug In IQexp function. +// -----|-------------|-------|---------------------------------------------- +// 1.5 | 30 Jan 2008 | LH | 1. Changed the definion of the _IQatan2PU(A,B) +// | | | macro for FLOAT_MATH so that a call to +// | | | divide will not occur. +// | | | 2. If MATH_TYPE == FLOAT_MATH, then include the +// | | | following standard headers: math.h +// | | | stdlib.h. +// | | | 3. Added missing #defines for the non-global +// | | | _IQatanN() function +// | | | 4. Adding missing definitions for absolute +// | | | value when MATH_TYPE == FLOAT_MATH +// | | | 5. Included limits.h and changed the definition +// | | | of MAX_IQ_NEG to LONG_MIN and MAX_IQ_POS +// | | | to LONG_MAX +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +// +// User needs to configure "MATH_TYPE" and "GLOBAL_Q" values: +// +//--------------------------------------------------------------------------- +// Select math type, IQ_MATH or FLOAT_MATH: +// + +#ifndef __IQMATHLIB_H_INCLUDED__ +#define __IQMATHLIB_H_INCLUDED__ + + +#define FLOAT_MATH 1 +#define IQ_MATH 0 + +#ifndef MATH_TYPE +#define MATH_TYPE IQ_MATH +#endif + +//--------------------------------------------------------------------------- +// Select global Q value and scaling. The Q value is limited to the +// following range for all functions: +// +// 30 <= GLOBAL_Q <= 1 +// +#ifndef GLOBAL_Q +#define GLOBAL_Q 24 +#endif + +//--------------------------------------------------------------------------- +// If using FLOAT_MATH, include standard headers to avoid conversion issues +// +#if MATH_TYPE == FLOAT_MATH +#include +#include +#endif +#include + +//--------------------------------------------------------------------------- +// Various Usefull Constant Definitions: +// +#define QG GLOBAL_Q +#define Q30 30 +#define Q29 29 +#define Q28 28 +#define Q27 27 +#define Q26 26 +#define Q25 25 +#define Q24 24 +#define Q23 23 +#define Q22 22 +#define Q21 21 +#define Q20 20 +#define Q19 19 +#define Q18 18 +#define Q17 17 +#define Q16 16 +#define Q15 15 +#define Q14 14 +#define Q13 13 +#define Q12 12 +#define Q11 11 +#define Q10 10 +#define Q9 9 +#define Q8 8 +#define Q7 7 +#define Q6 6 +#define Q5 5 +#define Q4 4 +#define Q3 3 +#define Q2 2 +#define Q1 1 + +#define MAX_IQ_POS LONG_MAX +#define MAX_IQ_NEG LONG_MIN +#define MIN_IQ_POS 1 +#define MIN_IQ_NEG -1 + +//########################################################################### +#if MATH_TYPE == IQ_MATH +//########################################################################### +// If IQ_MATH is used, the following IQmath library function definitions +// are used: +//=========================================================================== +typedef long _iq; +typedef long _iq30; +typedef long _iq29; +typedef long _iq28; +typedef long _iq27; +typedef long _iq26; +typedef long _iq25; +typedef long _iq24; +typedef long _iq23; +typedef long _iq22; +typedef long _iq21; +typedef long _iq20; +typedef long _iq19; +typedef long _iq18; +typedef long _iq17; +typedef long _iq16; +typedef long _iq15; +typedef long _iq14; +typedef long _iq13; +typedef long _iq12; +typedef long _iq11; +typedef long _iq10; +typedef long _iq9; +typedef long _iq8; +typedef long _iq7; +typedef long _iq6; +typedef long _iq5; +typedef long _iq4; +typedef long _iq3; +typedef long _iq2; +typedef long _iq1; +//--------------------------------------------------------------------------- +#define _IQ30(A) (long) ((A) * 1073741824.0L) +#define _IQ29(A) (long) ((A) * 536870912.0L) +#define _IQ28(A) (long) ((A) * 268435456.0L) +#define _IQ27(A) (long) ((A) * 134217728.0L) +#define _IQ26(A) (long) ((A) * 67108864.0L) +#define _IQ25(A) (long) ((A) * 33554432.0L) +#define _IQ24(A) (long) ((A) * 16777216.0L) +#define _IQ23(A) (long) ((A) * 8388608.0L) +#define _IQ22(A) (long) ((A) * 4194304.0L) +#define _IQ21(A) (long) ((A) * 2097152.0L) +#define _IQ20(A) (long) ((A) * 1048576.0L) +#define _IQ19(A) (long) ((A) * 524288.0L) +#define _IQ18(A) (long) ((A) * 262144.0L) +#define _IQ17(A) (long) ((A) * 131072.0L) +#define _IQ16(A) (long) ((A) * 65536.0L) +#define _IQ15(A) (long) ((A) * 32768.0L) +#define _IQ14(A) (long) ((A) * 16384.0L) +#define _IQ13(A) (long) ((A) * 8192.0L) +#define _IQ12(A) (long) ((A) * 4096.0L) +#define _IQ11(A) (long) ((A) * 2048.0L) +#define _IQ10(A) (long) ((A) * 1024.0L) +#define _IQ9(A) (long) ((A) * 512.0L) +#define _IQ8(A) (long) ((A) * 256.0L) +#define _IQ7(A) (long) ((A) * 128.0L) +#define _IQ6(A) (long) ((A) * 64.0L) +#define _IQ5(A) (long) ((A) * 32.0L) +#define _IQ4(A) (long) ((A) * 16.0L) +#define _IQ3(A) (long) ((A) * 8.0L) +#define _IQ2(A) (long) ((A) * 4.0L) +#define _IQ1(A) (long) ((A) * 2.0L) + +#if GLOBAL_Q == 30 +#define _IQ(A) _IQ30(A) +#endif +#if GLOBAL_Q == 29 +#define _IQ(A) _IQ29(A) +#endif +#if GLOBAL_Q == 28 +#define _IQ(A) _IQ28(A) +#endif +#if GLOBAL_Q == 27 +#define _IQ(A) _IQ27(A) +#endif +#if GLOBAL_Q == 26 +#define _IQ(A) _IQ26(A) +#endif +#if GLOBAL_Q == 25 +#define _IQ(A) _IQ25(A) +#endif +#if GLOBAL_Q == 24 +#define _IQ(A) _IQ24(A) +#endif +#if GLOBAL_Q == 23 +#define _IQ(A) _IQ23(A) +#endif +#if GLOBAL_Q == 22 +#define _IQ(A) _IQ22(A) +#endif +#if GLOBAL_Q == 21 +#define _IQ(A) _IQ21(A) +#endif +#if GLOBAL_Q == 20 +#define _IQ(A) _IQ20(A) +#endif +#if GLOBAL_Q == 19 +#define _IQ(A) _IQ19(A) +#endif +#if GLOBAL_Q == 18 +#define _IQ(A) _IQ18(A) +#endif +#if GLOBAL_Q == 17 +#define _IQ(A) _IQ17(A) +#endif +#if GLOBAL_Q == 16 +#define _IQ(A) _IQ16(A) +#endif +#if GLOBAL_Q == 15 +#define _IQ(A) _IQ15(A) +#endif +#if GLOBAL_Q == 14 +#define _IQ(A) _IQ14(A) +#endif +#if GLOBAL_Q == 13 +#define _IQ(A) _IQ13(A) +#endif +#if GLOBAL_Q == 12 +#define _IQ(A) _IQ12(A) +#endif +#if GLOBAL_Q == 11 +#define _IQ(A) _IQ11(A) +#endif +#if GLOBAL_Q == 10 +#define _IQ(A) _IQ10(A) +#endif +#if GLOBAL_Q == 9 +#define _IQ(A) _IQ9(A) +#endif +#if GLOBAL_Q == 8 +#define _IQ(A) _IQ8(A) +#endif +#if GLOBAL_Q == 7 +#define _IQ(A) _IQ7(A) +#endif +#if GLOBAL_Q == 6 +#define _IQ(A) _IQ6(A) +#endif +#if GLOBAL_Q == 5 +#define _IQ(A) _IQ5(A) +#endif +#if GLOBAL_Q == 4 +#define _IQ(A) _IQ4(A) +#endif +#if GLOBAL_Q == 3 +#define _IQ(A) _IQ3(A) +#endif +#if GLOBAL_Q == 2 +#define _IQ(A) _IQ2(A) +#endif +#if GLOBAL_Q == 1 +#define _IQ(A) _IQ1(A) +#endif +//--------------------------------------------------------------------------- +extern float _IQ30toF(long A); +extern float _IQ29toF(long A); +extern float _IQ28toF(long A); +extern float _IQ27toF(long A); +extern float _IQ26toF(long A); +extern float _IQ25toF(long A); +extern float _IQ24toF(long A); +extern float _IQ23toF(long A); +extern float _IQ22toF(long A); +extern float _IQ21toF(long A); +extern float _IQ20toF(long A); +extern float _IQ19toF(long A); +extern float _IQ18toF(long A); +extern float _IQ17toF(long A); +extern float _IQ16toF(long A); +extern float _IQ15toF(long A); +extern float _IQ14toF(long A); +extern float _IQ13toF(long A); +extern float _IQ12toF(long A); +extern float _IQ11toF(long A); +extern float _IQ10toF(long A); +extern float _IQ9toF(long A); +extern float _IQ8toF(long A); +extern float _IQ7toF(long A); +extern float _IQ6toF(long A); +extern float _IQ5toF(long A); +extern float _IQ4toF(long A); +extern float _IQ3toF(long A); +extern float _IQ2toF(long A); +extern float _IQ1toF(long A); + +#if GLOBAL_Q == 30 +#define _IQtoF(A) _IQ30toF(A) +#endif +#if GLOBAL_Q == 29 +#define _IQtoF(A) _IQ29toF(A) +#endif +#if GLOBAL_Q == 28 +#define _IQtoF(A) _IQ28toF(A) +#endif +#if GLOBAL_Q == 27 +#define _IQtoF(A) _IQ27toF(A) +#endif +#if GLOBAL_Q == 26 +#define _IQtoF(A) _IQ26toF(A) +#endif +#if GLOBAL_Q == 25 +#define _IQtoF(A) _IQ25toF(A) +#endif +#if GLOBAL_Q == 24 +#define _IQtoF(A) _IQ24toF(A) +#endif +#if GLOBAL_Q == 23 +#define _IQtoF(A) _IQ23toF(A) +#endif +#if GLOBAL_Q == 22 +#define _IQtoF(A) _IQ22toF(A) +#endif +#if GLOBAL_Q == 21 +#define _IQtoF(A) _IQ21toF(A) +#endif +#if GLOBAL_Q == 20 +#define _IQtoF(A) _IQ20toF(A) +#endif +#if GLOBAL_Q == 19 +#define _IQtoF(A) _IQ19toF(A) +#endif +#if GLOBAL_Q == 18 +#define _IQtoF(A) _IQ18toF(A) +#endif +#if GLOBAL_Q == 17 +#define _IQtoF(A) _IQ17toF(A) +#endif +#if GLOBAL_Q == 16 +#define _IQtoF(A) _IQ16toF(A) +#endif +#if GLOBAL_Q == 15 +#define _IQtoF(A) _IQ15toF(A) +#endif +#if GLOBAL_Q == 14 +#define _IQtoF(A) _IQ14toF(A) +#endif +#if GLOBAL_Q == 13 +#define _IQtoF(A) _IQ13toF(A) +#endif +#if GLOBAL_Q == 12 +#define _IQtoF(A) _IQ12toF(A) +#endif +#if GLOBAL_Q == 11 +#define _IQtoF(A) _IQ11toF(A) +#endif +#if GLOBAL_Q == 10 +#define _IQtoF(A) _IQ10toF(A) +#endif +#if GLOBAL_Q == 9 +#define _IQtoF(A) _IQ9toF(A) +#endif +#if GLOBAL_Q == 8 +#define _IQtoF(A) _IQ8toF(A) +#endif +#if GLOBAL_Q == 7 +#define _IQtoF(A) _IQ7toF(A) +#endif +#if GLOBAL_Q == 6 +#define _IQtoF(A) _IQ6toF(A) +#endif +#if GLOBAL_Q == 5 +#define _IQtoF(A) _IQ5toF(A) +#endif +#if GLOBAL_Q == 4 +#define _IQtoF(A) _IQ4toF(A) +#endif +#if GLOBAL_Q == 3 +#define _IQtoF(A) _IQ3toF(A) +#endif +#if GLOBAL_Q == 2 +#define _IQtoF(A) _IQ2toF(A) +#endif +#if GLOBAL_Q == 1 +#define _IQtoF(A) _IQ1toF(A) +#endif +//--------------------------------------------------------------------------- +#define _IQsat(A, Pos, Neg) __IQsat(A, Pos, Neg) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) ((long) (A) << (30 - GLOBAL_Q)) +#define _IQ30toIQ(A) ((long) (A) >> (30 - GLOBAL_Q)) + +#if (GLOBAL_Q >= 29) +#define _IQtoIQ29(A) ((long) (A) >> (GLOBAL_Q - 29)) +#define _IQ29toIQ(A) ((long) (A) << (GLOBAL_Q - 29)) +#else +#define _IQtoIQ29(A) ((long) (A) << (29 - GLOBAL_Q)) +#define _IQ29toIQ(A) ((long) (A) >> (29 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 28) +#define _IQtoIQ28(A) ((long) (A) >> (GLOBAL_Q - 28)) +#define _IQ28toIQ(A) ((long) (A) << (GLOBAL_Q - 28)) +#else +#define _IQtoIQ28(A) ((long) (A) << (28 - GLOBAL_Q)) +#define _IQ28toIQ(A) ((long) (A) >> (28 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 27) +#define _IQtoIQ27(A) ((long) (A) >> (GLOBAL_Q - 27)) +#define _IQ27toIQ(A) ((long) (A) << (GLOBAL_Q - 27)) +#else +#define _IQtoIQ27(A) ((long) (A) << (27 - GLOBAL_Q)) +#define _IQ27toIQ(A) ((long) (A) >> (27 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 26) +#define _IQtoIQ26(A) ((long) (A) >> (GLOBAL_Q - 26)) +#define _IQ26toIQ(A) ((long) (A) << (GLOBAL_Q - 26)) +#else +#define _IQtoIQ26(A) ((long) (A) << (26 - GLOBAL_Q)) +#define _IQ26toIQ(A) ((long) (A) >> (26 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 25) +#define _IQtoIQ25(A) ((long) (A) >> (GLOBAL_Q - 25)) +#define _IQ25toIQ(A) ((long) (A) << (GLOBAL_Q - 25)) +#else +#define _IQtoIQ25(A) ((long) (A) << (25 - GLOBAL_Q)) +#define _IQ25toIQ(A) ((long) (A) >> (25 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 24) +#define _IQtoIQ24(A) ((long) (A) >> (GLOBAL_Q - 24)) +#define _IQ24toIQ(A) ((long) (A) << (GLOBAL_Q - 24)) +#else +#define _IQtoIQ24(A) ((long) (A) << (24 - GLOBAL_Q)) +#define _IQ24toIQ(A) ((long) (A) >> (24 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 23) +#define _IQtoIQ23(A) ((long) (A) >> (GLOBAL_Q - 23)) +#define _IQ23toIQ(A) ((long) (A) << (GLOBAL_Q - 23)) +#else +#define _IQtoIQ23(A) ((long) (A) << (23 - GLOBAL_Q)) +#define _IQ23toIQ(A) ((long) (A) >> (23 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 22) +#define _IQtoIQ22(A) ((long) (A) >> (GLOBAL_Q - 22)) +#define _IQ22toIQ(A) ((long) (A) << (GLOBAL_Q - 22)) +#else +#define _IQtoIQ22(A) ((long) (A) << (22 - GLOBAL_Q)) +#define _IQ22toIQ(A) ((long) (A) >> (22 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 21) +#define _IQtoIQ21(A) ((long) (A) >> (GLOBAL_Q - 21)) +#define _IQ21toIQ(A) ((long) (A) << (GLOBAL_Q - 21)) +#else +#define _IQtoIQ21(A) ((long) (A) << (21 - GLOBAL_Q)) +#define _IQ21toIQ(A) ((long) (A) >> (21 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 20) +#define _IQtoIQ20(A) ((long) (A) >> (GLOBAL_Q - 20)) +#define _IQ20toIQ(A) ((long) (A) << (GLOBAL_Q - 20)) +#else +#define _IQtoIQ20(A) ((long) (A) << (20 - GLOBAL_Q)) +#define _IQ20toIQ(A) ((long) (A) >> (20 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 19) +#define _IQtoIQ19(A) ((long) (A) >> (GLOBAL_Q - 19)) +#define _IQ19toIQ(A) ((long) (A) << (GLOBAL_Q - 19)) +#else +#define _IQtoIQ19(A) ((long) (A) << (19 - GLOBAL_Q)) +#define _IQ19toIQ(A) ((long) (A) >> (19 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 18) +#define _IQtoIQ18(A) ((long) (A) >> (GLOBAL_Q - 18)) +#define _IQ18toIQ(A) ((long) (A) << (GLOBAL_Q - 18)) +#else +#define _IQtoIQ18(A) ((long) (A) << (18 - GLOBAL_Q)) +#define _IQ18toIQ(A) ((long) (A) >> (18 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 17) +#define _IQtoIQ17(A) ((long) (A) >> (GLOBAL_Q - 17)) +#define _IQ17toIQ(A) ((long) (A) << (GLOBAL_Q - 17)) +#else +#define _IQtoIQ17(A) ((long) (A) << (17 - GLOBAL_Q)) +#define _IQ17toIQ(A) ((long) (A) >> (17 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 16) +#define _IQtoIQ16(A) ((long) (A) >> (GLOBAL_Q - 16)) +#define _IQ16toIQ(A) ((long) (A) << (GLOBAL_Q - 16)) +#else +#define _IQtoIQ16(A) ((long) (A) << (16 - GLOBAL_Q)) +#define _IQ16toIQ(A) ((long) (A) >> (16 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 15) +#define _IQtoIQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _IQ15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#define _IQtoQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _Q15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#else +#define _IQtoIQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _IQ15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#define _IQtoQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _Q15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 14) +#define _IQtoIQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _IQ14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#define _IQtoQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _Q14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#else +#define _IQtoIQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _IQ14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#define _IQtoQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _Q14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 13) +#define _IQtoIQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _IQ13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#define _IQtoQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _Q13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#else +#define _IQtoIQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _IQ13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#define _IQtoQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _Q13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 12) +#define _IQtoIQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _IQ12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#define _IQtoQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _Q12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#else +#define _IQtoIQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _IQ12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#define _IQtoQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _Q12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 11) +#define _IQtoIQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _IQ11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#define _IQtoQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _Q11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#else +#define _IQtoIQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _IQ11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#define _IQtoQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _Q11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 10) +#define _IQtoIQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _IQ10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#define _IQtoQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _Q10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#else +#define _IQtoIQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _IQ10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#define _IQtoQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _Q10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 9) +#define _IQtoIQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _IQ9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#define _IQtoQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _Q9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#else +#define _IQtoIQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _IQ9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#define _IQtoQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _Q9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 8) +#define _IQtoIQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _IQ8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#define _IQtoQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _Q8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#else +#define _IQtoIQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _IQ8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#define _IQtoQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _Q8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 7) +#define _IQtoIQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _IQ7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#define _IQtoQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _Q7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#else +#define _IQtoIQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _IQ7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#define _IQtoQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _Q7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 6) +#define _IQtoIQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _IQ6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#define _IQtoQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _Q6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#else +#define _IQtoIQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _IQ6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#define _IQtoQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _Q6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 5) +#define _IQtoIQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _IQ5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#define _IQtoQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _Q5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#else +#define _IQtoIQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _IQ5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#define _IQtoQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _Q5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 4) +#define _IQtoIQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _IQ4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#define _IQtoQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _Q4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#else +#define _IQtoIQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _IQ4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#define _IQtoQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _Q4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 3) +#define _IQtoIQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _IQ3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#define _IQtoQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _Q3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#else +#define _IQtoIQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _IQ3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#define _IQtoQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _Q3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 2) +#define _IQtoIQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _IQ2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#define _IQtoQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _Q2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#else +#define _IQtoIQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _IQ2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#define _IQtoQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _Q2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 1) +#define _IQtoQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _Q1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +#else +#define _IQtoQ1(A) ((long) (A) << (1 - GLOBAL_Q)) +#define _Q1toIQ(A) ((long) (A) >> (1 - GLOBAL_Q)) +#endif + +#define _IQtoIQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _IQ1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) __IQmpy(A,B,GLOBAL_Q) +#define _IQ30mpy(A,B) __IQmpy(A,B,30) +#define _IQ29mpy(A,B) __IQmpy(A,B,29) +#define _IQ28mpy(A,B) __IQmpy(A,B,28) +#define _IQ27mpy(A,B) __IQmpy(A,B,27) +#define _IQ26mpy(A,B) __IQmpy(A,B,26) +#define _IQ25mpy(A,B) __IQmpy(A,B,25) +#define _IQ24mpy(A,B) __IQmpy(A,B,24) +#define _IQ23mpy(A,B) __IQmpy(A,B,23) +#define _IQ22mpy(A,B) __IQmpy(A,B,22) +#define _IQ21mpy(A,B) __IQmpy(A,B,21) +#define _IQ20mpy(A,B) __IQmpy(A,B,20) +#define _IQ19mpy(A,B) __IQmpy(A,B,19) +#define _IQ18mpy(A,B) __IQmpy(A,B,18) +#define _IQ17mpy(A,B) __IQmpy(A,B,17) +#define _IQ16mpy(A,B) __IQmpy(A,B,16) +#define _IQ15mpy(A,B) __IQmpy(A,B,15) +#define _IQ14mpy(A,B) __IQmpy(A,B,14) +#define _IQ13mpy(A,B) __IQmpy(A,B,13) +#define _IQ12mpy(A,B) __IQmpy(A,B,12) +#define _IQ11mpy(A,B) __IQmpy(A,B,11) +#define _IQ10mpy(A,B) __IQmpy(A,B,10) +#define _IQ9mpy(A,B) __IQmpy(A,B,9) +#define _IQ8mpy(A,B) __IQmpy(A,B,8) +#define _IQ7mpy(A,B) __IQmpy(A,B,7) +#define _IQ6mpy(A,B) __IQmpy(A,B,6) +#define _IQ5mpy(A,B) __IQmpy(A,B,5) +#define _IQ4mpy(A,B) __IQmpy(A,B,4) +#define _IQ3mpy(A,B) __IQmpy(A,B,3) +#define _IQ2mpy(A,B) __IQmpy(A,B,2) +#define _IQ1mpy(A,B) __IQmpy(A,B,1) +//--------------------------------------------------------------------------- +extern long _IQ30rmpy(long A, long B); +extern long _IQ29rmpy(long A, long B); +extern long _IQ28rmpy(long A, long B); +extern long _IQ27rmpy(long A, long B); +extern long _IQ26rmpy(long A, long B); +extern long _IQ25rmpy(long A, long B); +extern long _IQ24rmpy(long A, long B); +extern long _IQ23rmpy(long A, long B); +extern long _IQ22rmpy(long A, long B); +extern long _IQ21rmpy(long A, long B); +extern long _IQ20rmpy(long A, long B); +extern long _IQ19rmpy(long A, long B); +extern long _IQ18rmpy(long A, long B); +extern long _IQ17rmpy(long A, long B); +extern long _IQ16rmpy(long A, long B); +extern long _IQ15rmpy(long A, long B); +extern long _IQ14rmpy(long A, long B); +extern long _IQ13rmpy(long A, long B); +extern long _IQ12rmpy(long A, long B); +extern long _IQ11rmpy(long A, long B); +extern long _IQ10rmpy(long A, long B); +extern long _IQ9rmpy(long A, long B); +extern long _IQ8rmpy(long A, long B); +extern long _IQ7rmpy(long A, long B); +extern long _IQ6rmpy(long A, long B); +extern long _IQ5rmpy(long A, long B); +extern long _IQ4rmpy(long A, long B); +extern long _IQ3rmpy(long A, long B); +extern long _IQ2rmpy(long A, long B); +extern long _IQ1rmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrmpy(A,B) _IQ30rmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrmpy(A,B) _IQ29rmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrmpy(A,B) _IQ28rmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrmpy(A,B) _IQ27rmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrmpy(A,B) _IQ26rmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrmpy(A,B) _IQ25rmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrmpy(A,B) _IQ24rmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrmpy(A,B) _IQ23rmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrmpy(A,B) _IQ22rmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrmpy(A,B) _IQ21rmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrmpy(A,B) _IQ20rmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrmpy(A,B) _IQ19rmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrmpy(A,B) _IQ18rmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrmpy(A,B) _IQ17rmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrmpy(A,B) _IQ16rmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrmpy(A,B) _IQ15rmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrmpy(A,B) _IQ14rmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrmpy(A,B) _IQ13rmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrmpy(A,B) _IQ12rmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrmpy(A,B) _IQ11rmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrmpy(A,B) _IQ10rmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrmpy(A,B) _IQ9rmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrmpy(A,B) _IQ8rmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrmpy(A,B) _IQ7rmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrmpy(A,B) _IQ6rmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrmpy(A,B) _IQ5rmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrmpy(A,B) _IQ4rmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrmpy(A,B) _IQ3rmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrmpy(A,B) _IQ2rmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrmpy(A,B) _IQ1rmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30rsmpy(long A, long B); +extern long _IQ29rsmpy(long A, long B); +extern long _IQ28rsmpy(long A, long B); +extern long _IQ27rsmpy(long A, long B); +extern long _IQ26rsmpy(long A, long B); +extern long _IQ25rsmpy(long A, long B); +extern long _IQ24rsmpy(long A, long B); +extern long _IQ23rsmpy(long A, long B); +extern long _IQ22rsmpy(long A, long B); +extern long _IQ21rsmpy(long A, long B); +extern long _IQ20rsmpy(long A, long B); +extern long _IQ19rsmpy(long A, long B); +extern long _IQ18rsmpy(long A, long B); +extern long _IQ17rsmpy(long A, long B); +extern long _IQ16rsmpy(long A, long B); +extern long _IQ15rsmpy(long A, long B); +extern long _IQ14rsmpy(long A, long B); +extern long _IQ13rsmpy(long A, long B); +extern long _IQ12rsmpy(long A, long B); +extern long _IQ11rsmpy(long A, long B); +extern long _IQ10rsmpy(long A, long B); +extern long _IQ9rsmpy(long A, long B); +extern long _IQ8rsmpy(long A, long B); +extern long _IQ7rsmpy(long A, long B); +extern long _IQ6rsmpy(long A, long B); +extern long _IQ5rsmpy(long A, long B); +extern long _IQ4rsmpy(long A, long B); +extern long _IQ3rsmpy(long A, long B); +extern long _IQ2rsmpy(long A, long B); +extern long _IQ1rsmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrsmpy(A,B) _IQ30rsmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrsmpy(A,B) _IQ29rsmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrsmpy(A,B) _IQ28rsmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrsmpy(A,B) _IQ27rsmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrsmpy(A,B) _IQ26rsmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrsmpy(A,B) _IQ25rsmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrsmpy(A,B) _IQ24rsmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrsmpy(A,B) _IQ23rsmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrsmpy(A,B) _IQ22rsmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrsmpy(A,B) _IQ21rsmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrsmpy(A,B) _IQ20rsmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrsmpy(A,B) _IQ19rsmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrsmpy(A,B) _IQ18rsmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrsmpy(A,B) _IQ17rsmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrsmpy(A,B) _IQ16rsmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrsmpy(A,B) _IQ15rsmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrsmpy(A,B) _IQ14rsmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrsmpy(A,B) _IQ13rsmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrsmpy(A,B) _IQ12rsmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrsmpy(A,B) _IQ11rsmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrsmpy(A,B) _IQ10rsmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrsmpy(A,B) _IQ9rsmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrsmpy(A,B) _IQ8rsmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrsmpy(A,B) _IQ7rsmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrsmpy(A,B) _IQ6rsmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrsmpy(A,B) _IQ5rsmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrsmpy(A,B) _IQ4rsmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrsmpy(A,B) _IQ3rsmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrsmpy(A,B) _IQ2rsmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrsmpy(A,B) _IQ1rsmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30div(long A, long B); +extern long _IQ29div(long A, long B); +extern long _IQ28div(long A, long B); +extern long _IQ27div(long A, long B); +extern long _IQ26div(long A, long B); +extern long _IQ25div(long A, long B); +extern long _IQ24div(long A, long B); +extern long _IQ23div(long A, long B); +extern long _IQ22div(long A, long B); +extern long _IQ21div(long A, long B); +extern long _IQ20div(long A, long B); +extern long _IQ19div(long A, long B); +extern long _IQ18div(long A, long B); +extern long _IQ17div(long A, long B); +extern long _IQ16div(long A, long B); +extern long _IQ15div(long A, long B); +extern long _IQ14div(long A, long B); +extern long _IQ13div(long A, long B); +extern long _IQ12div(long A, long B); +extern long _IQ11div(long A, long B); +extern long _IQ10div(long A, long B); +extern long _IQ9div(long A, long B); +extern long _IQ8div(long A, long B); +extern long _IQ7div(long A, long B); +extern long _IQ6div(long A, long B); +extern long _IQ5div(long A, long B); +extern long _IQ4div(long A, long B); +extern long _IQ3div(long A, long B); +extern long _IQ2div(long A, long B); +extern long _IQ1div(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQdiv(A,B) _IQ30div(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQdiv(A,B) _IQ29div(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQdiv(A,B) _IQ28div(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQdiv(A,B) _IQ27div(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQdiv(A,B) _IQ26div(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQdiv(A,B) _IQ25div(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQdiv(A,B) _IQ24div(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQdiv(A,B) _IQ23div(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQdiv(A,B) _IQ22div(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQdiv(A,B) _IQ21div(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQdiv(A,B) _IQ20div(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQdiv(A,B) _IQ19div(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQdiv(A,B) _IQ18div(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQdiv(A,B) _IQ17div(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQdiv(A,B) _IQ16div(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQdiv(A,B) _IQ15div(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQdiv(A,B) _IQ14div(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQdiv(A,B) _IQ13div(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQdiv(A,B) _IQ12div(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQdiv(A,B) _IQ11div(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQdiv(A,B) _IQ10div(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQdiv(A,B) _IQ9div(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQdiv(A,B) _IQ8div(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQdiv(A,B) _IQ7div(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQdiv(A,B) _IQ6div(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQdiv(A,B) _IQ5div(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQdiv(A,B) _IQ4div(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQdiv(A,B) _IQ3div(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQdiv(A,B) _IQ2div(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQdiv(A,B) _IQ1div(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sin(long A); +extern long _IQ29sin(long A); +extern long _IQ28sin(long A); +extern long _IQ27sin(long A); +extern long _IQ26sin(long A); +extern long _IQ25sin(long A); +extern long _IQ24sin(long A); +extern long _IQ23sin(long A); +extern long _IQ22sin(long A); +extern long _IQ21sin(long A); +extern long _IQ20sin(long A); +extern long _IQ19sin(long A); +extern long _IQ18sin(long A); +extern long _IQ17sin(long A); +extern long _IQ16sin(long A); +extern long _IQ15sin(long A); +extern long _IQ14sin(long A); +extern long _IQ13sin(long A); +extern long _IQ12sin(long A); +extern long _IQ11sin(long A); +extern long _IQ10sin(long A); +extern long _IQ9sin(long A); +extern long _IQ8sin(long A); +extern long _IQ7sin(long A); +extern long _IQ6sin(long A); +extern long _IQ5sin(long A); +extern long _IQ4sin(long A); +extern long _IQ3sin(long A); +extern long _IQ2sin(long A); +extern long _IQ1sin(long A); + +#if GLOBAL_Q == 30 +#define _IQsin(A) _IQ30sin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsin(A) _IQ29sin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsin(A) _IQ28sin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsin(A) _IQ27sin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsin(A) _IQ26sin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsin(A) _IQ25sin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsin(A) _IQ24sin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsin(A) _IQ23sin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsin(A) _IQ22sin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsin(A) _IQ21sin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsin(A) _IQ20sin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsin(A) _IQ19sin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsin(A) _IQ18sin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsin(A) _IQ17sin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsin(A) _IQ16sin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsin(A) _IQ15sin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsin(A) _IQ14sin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsin(A) _IQ13sin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsin(A) _IQ12sin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsin(A) _IQ11sin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsin(A) _IQ10sin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsin(A) _IQ9sin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsin(A) _IQ8sin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsin(A) _IQ7sin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsin(A) _IQ6sin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsin(A) _IQ5sin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsin(A) _IQ4sin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsin(A) _IQ3sin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsin(A) _IQ2sin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsin(A) _IQ1sin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sinPU(long A); +extern long _IQ29sinPU(long A); +extern long _IQ28sinPU(long A); +extern long _IQ27sinPU(long A); +extern long _IQ26sinPU(long A); +extern long _IQ25sinPU(long A); +extern long _IQ24sinPU(long A); +extern long _IQ23sinPU(long A); +extern long _IQ22sinPU(long A); +extern long _IQ21sinPU(long A); +extern long _IQ20sinPU(long A); +extern long _IQ19sinPU(long A); +extern long _IQ18sinPU(long A); +extern long _IQ17sinPU(long A); +extern long _IQ16sinPU(long A); +extern long _IQ15sinPU(long A); +extern long _IQ14sinPU(long A); +extern long _IQ13sinPU(long A); +extern long _IQ12sinPU(long A); +extern long _IQ11sinPU(long A); +extern long _IQ10sinPU(long A); +extern long _IQ9sinPU(long A); +extern long _IQ8sinPU(long A); +extern long _IQ7sinPU(long A); +extern long _IQ6sinPU(long A); +extern long _IQ5sinPU(long A); +extern long _IQ4sinPU(long A); +extern long _IQ3sinPU(long A); +extern long _IQ2sinPU(long A); +extern long _IQ1sinPU(long A); + +#if GLOBAL_Q == 30 +#define _IQsinPU(A) _IQ30sinPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsinPU(A) _IQ29sinPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsinPU(A) _IQ28sinPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsinPU(A) _IQ27sinPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsinPU(A) _IQ26sinPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsinPU(A) _IQ25sinPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsinPU(A) _IQ24sinPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsinPU(A) _IQ23sinPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsinPU(A) _IQ22sinPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsinPU(A) _IQ21sinPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsinPU(A) _IQ20sinPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsinPU(A) _IQ19sinPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsinPU(A) _IQ18sinPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsinPU(A) _IQ17sinPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsinPU(A) _IQ16sinPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsinPU(A) _IQ15sinPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsinPU(A) _IQ14sinPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsinPU(A) _IQ13sinPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsinPU(A) _IQ12sinPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsinPU(A) _IQ11sinPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsinPU(A) _IQ10sinPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsinPU(A) _IQ9sinPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsinPU(A) _IQ8sinPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsinPU(A) _IQ7sinPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsinPU(A) _IQ6sinPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsinPU(A) _IQ5sinPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsinPU(A) _IQ4sinPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsinPU(A) _IQ3sinPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsinPU(A) _IQ2sinPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsinPU(A) _IQ1sinPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30asin(long A); +extern long _IQ29asin(long A); +extern long _IQ28asin(long A); +extern long _IQ27asin(long A); +extern long _IQ26asin(long A); +extern long _IQ25asin(long A); +extern long _IQ24asin(long A); +extern long _IQ23asin(long A); +extern long _IQ22asin(long A); +extern long _IQ21asin(long A); +extern long _IQ20asin(long A); +extern long _IQ19asin(long A); +extern long _IQ18asin(long A); +extern long _IQ17asin(long A); +extern long _IQ16asin(long A); +extern long _IQ15asin(long A); +extern long _IQ14asin(long A); +extern long _IQ13asin(long A); +extern long _IQ12asin(long A); +extern long _IQ11asin(long A); +extern long _IQ10asin(long A); +extern long _IQ9asin(long A); +extern long _IQ8asin(long A); +extern long _IQ7asin(long A); +extern long _IQ6asin(long A); +extern long _IQ5asin(long A); +extern long _IQ4asin(long A); +extern long _IQ3asin(long A); +extern long _IQ2asin(long A); +extern long _IQ1asin(long A); + +#if GLOBAL_Q == 30 +#define _IQasin(A) _IQ30asin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQasin(A) _IQ29asin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQasin(A) _IQ28asin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQasin(A) _IQ27asin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQasin(A) _IQ26asin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQasin(A) _IQ25asin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQasin(A) _IQ24asin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQasin(A) _IQ23asin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQasin(A) _IQ22asin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQasin(A) _IQ21asin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQasin(A) _IQ20asin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQasin(A) _IQ19asin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQasin(A) _IQ18asin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQasin(A) _IQ17asin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQasin(A) _IQ16asin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQasin(A) _IQ15asin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQasin(A) _IQ14asin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQasin(A) _IQ13asin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQasin(A) _IQ12asin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQasin(A) _IQ11asin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQasin(A) _IQ10asin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQasin(A) _IQ9asin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQasin(A) _IQ8asin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQasin(A) _IQ7asin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQasin(A) _IQ6asin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQasin(A) _IQ5asin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQasin(A) _IQ4asin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQasin(A) _IQ3asin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQasin(A) _IQ2asin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQasin(A) _IQ1asin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cos(long A); +extern long _IQ29cos(long A); +extern long _IQ28cos(long A); +extern long _IQ27cos(long A); +extern long _IQ26cos(long A); +extern long _IQ25cos(long A); +extern long _IQ24cos(long A); +extern long _IQ23cos(long A); +extern long _IQ22cos(long A); +extern long _IQ21cos(long A); +extern long _IQ20cos(long A); +extern long _IQ19cos(long A); +extern long _IQ18cos(long A); +extern long _IQ17cos(long A); +extern long _IQ16cos(long A); +extern long _IQ15cos(long A); +extern long _IQ14cos(long A); +extern long _IQ13cos(long A); +extern long _IQ12cos(long A); +extern long _IQ11cos(long A); +extern long _IQ10cos(long A); +extern long _IQ9cos(long A); +extern long _IQ8cos(long A); +extern long _IQ7cos(long A); +extern long _IQ6cos(long A); +extern long _IQ5cos(long A); +extern long _IQ4cos(long A); +extern long _IQ3cos(long A); +extern long _IQ2cos(long A); +extern long _IQ1cos(long A); + +#if GLOBAL_Q == 30 +#define _IQcos(A) _IQ30cos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcos(A) _IQ29cos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcos(A) _IQ28cos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcos(A) _IQ27cos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcos(A) _IQ26cos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcos(A) _IQ25cos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcos(A) _IQ24cos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcos(A) _IQ23cos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcos(A) _IQ22cos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcos(A) _IQ21cos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcos(A) _IQ20cos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcos(A) _IQ19cos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcos(A) _IQ18cos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcos(A) _IQ17cos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcos(A) _IQ16cos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcos(A) _IQ15cos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcos(A) _IQ14cos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcos(A) _IQ13cos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcos(A) _IQ12cos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcos(A) _IQ11cos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcos(A) _IQ10cos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcos(A) _IQ9cos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcos(A) _IQ8cos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcos(A) _IQ7cos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcos(A) _IQ6cos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcos(A) _IQ5cos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcos(A) _IQ4cos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcos(A) _IQ3cos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcos(A) _IQ2cos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcos(A) _IQ1cos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cosPU(long A); +extern long _IQ29cosPU(long A); +extern long _IQ28cosPU(long A); +extern long _IQ27cosPU(long A); +extern long _IQ26cosPU(long A); +extern long _IQ25cosPU(long A); +extern long _IQ24cosPU(long A); +extern long _IQ23cosPU(long A); +extern long _IQ22cosPU(long A); +extern long _IQ21cosPU(long A); +extern long _IQ20cosPU(long A); +extern long _IQ19cosPU(long A); +extern long _IQ18cosPU(long A); +extern long _IQ17cosPU(long A); +extern long _IQ16cosPU(long A); +extern long _IQ15cosPU(long A); +extern long _IQ14cosPU(long A); +extern long _IQ13cosPU(long A); +extern long _IQ12cosPU(long A); +extern long _IQ11cosPU(long A); +extern long _IQ10cosPU(long A); +extern long _IQ9cosPU(long A); +extern long _IQ8cosPU(long A); +extern long _IQ7cosPU(long A); +extern long _IQ6cosPU(long A); +extern long _IQ5cosPU(long A); +extern long _IQ4cosPU(long A); +extern long _IQ3cosPU(long A); +extern long _IQ2cosPU(long A); +extern long _IQ1cosPU(long A); + +#if GLOBAL_Q == 30 +#define _IQcosPU(A) _IQ30cosPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcosPU(A) _IQ29cosPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcosPU(A) _IQ28cosPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcosPU(A) _IQ27cosPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcosPU(A) _IQ26cosPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcosPU(A) _IQ25cosPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcosPU(A) _IQ24cosPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcosPU(A) _IQ23cosPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcosPU(A) _IQ22cosPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcosPU(A) _IQ21cosPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcosPU(A) _IQ20cosPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcosPU(A) _IQ19cosPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcosPU(A) _IQ18cosPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcosPU(A) _IQ17cosPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcosPU(A) _IQ16cosPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcosPU(A) _IQ15cosPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcosPU(A) _IQ14cosPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcosPU(A) _IQ13cosPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcosPU(A) _IQ12cosPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcosPU(A) _IQ11cosPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcosPU(A) _IQ10cosPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcosPU(A) _IQ9cosPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcosPU(A) _IQ8cosPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcosPU(A) _IQ7cosPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcosPU(A) _IQ6cosPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcosPU(A) _IQ5cosPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcosPU(A) _IQ4cosPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcosPU(A) _IQ3cosPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcosPU(A) _IQ2cosPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcosPU(A) _IQ1cosPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30acos(long A); +extern long _IQ29acos(long A); +extern long _IQ28acos(long A); +extern long _IQ27acos(long A); +extern long _IQ26acos(long A); +extern long _IQ25acos(long A); +extern long _IQ24acos(long A); +extern long _IQ23acos(long A); +extern long _IQ22acos(long A); +extern long _IQ21acos(long A); +extern long _IQ20acos(long A); +extern long _IQ19acos(long A); +extern long _IQ18acos(long A); +extern long _IQ17acos(long A); +extern long _IQ16acos(long A); +extern long _IQ15acos(long A); +extern long _IQ14acos(long A); +extern long _IQ13acos(long A); +extern long _IQ12acos(long A); +extern long _IQ11acos(long A); +extern long _IQ10acos(long A); +extern long _IQ9acos(long A); +extern long _IQ8acos(long A); +extern long _IQ7acos(long A); +extern long _IQ6acos(long A); +extern long _IQ5acos(long A); +extern long _IQ4acos(long A); +extern long _IQ3acos(long A); +extern long _IQ2acos(long A); +extern long _IQ1acos(long A); + +#if GLOBAL_Q == 30 +#define _IQacos(A) _IQ30acos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQacos(A) _IQ29acos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQacos(A) _IQ28acos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQacos(A) _IQ27acos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQacos(A) _IQ26acos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQacos(A) _IQ25acos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQacos(A) _IQ24acos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQacos(A) _IQ23acos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQacos(A) _IQ22acos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQacos(A) _IQ21acos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQacos(A) _IQ20acos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQacos(A) _IQ19acos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQacos(A) _IQ18acos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQacos(A) _IQ17acos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQacos(A) _IQ16acos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQacos(A) _IQ15acos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQacos(A) _IQ14acos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQacos(A) _IQ13acos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQacos(A) _IQ12acos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQacos(A) _IQ11acos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQacos(A) _IQ10acos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQacos(A) _IQ9acos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQacos(A) _IQ8acos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQacos(A) _IQ7acos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQacos(A) _IQ6acos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQacos(A) _IQ5acos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQacos(A) _IQ4acos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQacos(A) _IQ3acos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQacos(A) _IQ2acos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQacos(A) _IQ1acos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2(long A, long B); +extern long _IQ29atan2(long A, long B); +extern long _IQ28atan2(long A, long B); +extern long _IQ27atan2(long A, long B); +extern long _IQ26atan2(long A, long B); +extern long _IQ25atan2(long A, long B); +extern long _IQ24atan2(long A, long B); +extern long _IQ23atan2(long A, long B); +extern long _IQ22atan2(long A, long B); +extern long _IQ21atan2(long A, long B); +extern long _IQ20atan2(long A, long B); +extern long _IQ19atan2(long A, long B); +extern long _IQ18atan2(long A, long B); +extern long _IQ17atan2(long A, long B); +extern long _IQ16atan2(long A, long B); +extern long _IQ15atan2(long A, long B); +extern long _IQ14atan2(long A, long B); +extern long _IQ13atan2(long A, long B); +extern long _IQ12atan2(long A, long B); +extern long _IQ11atan2(long A, long B); +extern long _IQ10atan2(long A, long B); +extern long _IQ9atan2(long A, long B); +extern long _IQ8atan2(long A, long B); +extern long _IQ7atan2(long A, long B); +extern long _IQ6atan2(long A, long B); +extern long _IQ5atan2(long A, long B); +extern long _IQ4atan2(long A, long B); +extern long _IQ3atan2(long A, long B); +extern long _IQ2atan2(long A, long B); +extern long _IQ1atan2(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2(A,B) _IQ30atan2(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2(A,B) _IQ29atan2(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2(A,B) _IQ28atan2(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2(A,B) _IQ27atan2(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2(A,B) _IQ26atan2(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2(A,B) _IQ25atan2(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2(A,B) _IQ24atan2(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2(A,B) _IQ23atan2(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2(A,B) _IQ22atan2(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2(A,B) _IQ21atan2(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2(A,B) _IQ20atan2(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2(A,B) _IQ19atan2(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2(A,B) _IQ18atan2(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2(A,B) _IQ17atan2(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2(A,B) _IQ16atan2(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2(A,B) _IQ15atan2(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2(A,B) _IQ14atan2(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2(A,B) _IQ13atan2(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2(A,B) _IQ12atan2(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2(A,B) _IQ11atan2(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2(A,B) _IQ10atan2(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2(A,B) _IQ9atan2(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2(A,B) _IQ8atan2(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2(A,B) _IQ7atan2(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2(A,B) _IQ6atan2(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2(A,B) _IQ5atan2(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2(A,B) _IQ4atan2(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2(A,B) _IQ3atan2(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2(A,B) _IQ2atan2(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2(A,B) _IQ1atan2(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2PU(long A, long B); +extern long _IQ29atan2PU(long A, long B); +extern long _IQ28atan2PU(long A, long B); +extern long _IQ27atan2PU(long A, long B); +extern long _IQ26atan2PU(long A, long B); +extern long _IQ25atan2PU(long A, long B); +extern long _IQ24atan2PU(long A, long B); +extern long _IQ23atan2PU(long A, long B); +extern long _IQ22atan2PU(long A, long B); +extern long _IQ21atan2PU(long A, long B); +extern long _IQ20atan2PU(long A, long B); +extern long _IQ19atan2PU(long A, long B); +extern long _IQ18atan2PU(long A, long B); +extern long _IQ17atan2PU(long A, long B); +extern long _IQ16atan2PU(long A, long B); +extern long _IQ15atan2PU(long A, long B); +extern long _IQ14atan2PU(long A, long B); +extern long _IQ13atan2PU(long A, long B); +extern long _IQ12atan2PU(long A, long B); +extern long _IQ11atan2PU(long A, long B); +extern long _IQ10atan2PU(long A, long B); +extern long _IQ9atan2PU(long A, long B); +extern long _IQ8atan2PU(long A, long B); +extern long _IQ7atan2PU(long A, long B); +extern long _IQ6atan2PU(long A, long B); +extern long _IQ5atan2PU(long A, long B); +extern long _IQ4atan2PU(long A, long B); +extern long _IQ3atan2PU(long A, long B); +extern long _IQ2atan2PU(long A, long B); +extern long _IQ1atan2PU(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2PU(A,B) _IQ30atan2PU(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2PU(A,B) _IQ29atan2PU(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2PU(A,B) _IQ28atan2PU(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2PU(A,B) _IQ27atan2PU(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2PU(A,B) _IQ26atan2PU(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2PU(A,B) _IQ25atan2PU(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2PU(A,B) _IQ24atan2PU(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2PU(A,B) _IQ23atan2PU(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2PU(A,B) _IQ22atan2PU(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2PU(A,B) _IQ21atan2PU(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2PU(A,B) _IQ20atan2PU(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2PU(A,B) _IQ19atan2PU(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2PU(A,B) _IQ18atan2PU(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2PU(A,B) _IQ17atan2PU(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2PU(A,B) _IQ16atan2PU(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2PU(A,B) _IQ15atan2PU(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2PU(A,B) _IQ14atan2PU(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2PU(A,B) _IQ13atan2PU(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2PU(A,B) _IQ12atan2PU(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2PU(A,B) _IQ11atan2PU(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2PU(A,B) _IQ10atan2PU(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2PU(A,B) _IQ9atan2PU(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2PU(A,B) _IQ8atan2PU(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2PU(A,B) _IQ7atan2PU(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2PU(A,B) _IQ6atan2PU(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2PU(A,B) _IQ5atan2PU(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2PU(A,B) _IQ4atan2PU(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2PU(A,B) _IQ3atan2PU(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2PU(A,B) _IQ2atan2PU(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2PU(A,B) _IQ1atan2PU(A,B) +#endif +//--------------------------------------------------------------------------- +#define _IQ30atan(A) _IQ30atan2(A,_IQ30(1.0)) +#define _IQ29atan(A) _IQ29atan2(A,_IQ29(1.0)) +#define _IQ28atan(A) _IQ28atan2(A,_IQ28(1.0)) +#define _IQ27atan(A) _IQ27atan2(A,_IQ27(1.0)) +#define _IQ26atan(A) _IQ26atan2(A,_IQ26(1.0)) +#define _IQ25atan(A) _IQ25atan2(A,_IQ25(1.0)) +#define _IQ24atan(A) _IQ24atan2(A,_IQ24(1.0)) +#define _IQ23atan(A) _IQ23atan2(A,_IQ23(1.0)) +#define _IQ22atan(A) _IQ22atan2(A,_IQ22(1.0)) +#define _IQ21atan(A) _IQ21atan2(A,_IQ21(1.0)) +#define _IQ20atan(A) _IQ20atan2(A,_IQ20(1.0)) +#define _IQ19atan(A) _IQ19atan2(A,_IQ19(1.0)) +#define _IQ18atan(A) _IQ18atan2(A,_IQ18(1.0)) +#define _IQ17atan(A) _IQ17atan2(A,_IQ17(1.0)) +#define _IQ16atan(A) _IQ16atan2(A,_IQ16(1.0)) +#define _IQ15atan(A) _IQ15atan2(A,_IQ15(1.0)) +#define _IQ14atan(A) _IQ14atan2(A,_IQ14(1.0)) +#define _IQ13atan(A) _IQ13atan2(A,_IQ13(1.0)) +#define _IQ12atan(A) _IQ12atan2(A,_IQ12(1.0)) +#define _IQ11atan(A) _IQ11atan2(A,_IQ11(1.0)) +#define _IQ10atan(A) _IQ10atan2(A,_IQ10(1.0)) +#define _IQ9atan(A) _IQ9atan2(A,_IQ9(1.0)) +#define _IQ8atan(A) _IQ8atan2(A,_IQ8(1.0)) +#define _IQ7atan(A) _IQ7atan2(A,_IQ7(1.0)) +#define _IQ6atan(A) _IQ6atan2(A,_IQ6(1.0)) +#define _IQ5atan(A) _IQ5atan2(A,_IQ5(1.0)) +#define _IQ4atan(A) _IQ4atan2(A,_IQ4(1.0)) +#define _IQ3atan(A) _IQ3atan2(A,_IQ3(1.0)) +#define _IQ2atan(A) _IQ2atan2(A,_IQ2(1.0)) +#define _IQ1atan(A) _IQ1atan2(A,_IQ1(1.0)) +#if GLOBAL_Q == 30 +#define _IQatan(A) _IQ30atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 29 +#define _IQatan(A) _IQ29atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 28 +#define _IQatan(A) _IQ28atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 27 +#define _IQatan(A) _IQ27atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 26 +#define _IQatan(A) _IQ26atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 25 +#define _IQatan(A) _IQ25atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 24 +#define _IQatan(A) _IQ24atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 23 +#define _IQatan(A) _IQ23atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 22 +#define _IQatan(A) _IQ22atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 21 +#define _IQatan(A) _IQ21atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 20 +#define _IQatan(A) _IQ20atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 19 +#define _IQatan(A) _IQ19atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 18 +#define _IQatan(A) _IQ18atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 17 +#define _IQatan(A) _IQ17atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 16 +#define _IQatan(A) _IQ16atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 15 +#define _IQatan(A) _IQ15atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 14 +#define _IQatan(A) _IQ14atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 13 +#define _IQatan(A) _IQ13atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 12 +#define _IQatan(A) _IQ12atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 11 +#define _IQatan(A) _IQ11atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 10 +#define _IQatan(A) _IQ10atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 9 +#define _IQatan(A) _IQ9atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 8 +#define _IQatan(A) _IQ8atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 7 +#define _IQatan(A) _IQ7atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 6 +#define _IQatan(A) _IQ6atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 5 +#define _IQatan(A) _IQ5atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 4 +#define _IQatan(A) _IQ4atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 3 +#define _IQatan(A) _IQ3atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 2 +#define _IQatan(A) _IQ2atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 1 +#define _IQatan(A) _IQ1atan2(A,_IQ(1.0)) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sqrt(long A); +extern long _IQ29sqrt(long A); +extern long _IQ28sqrt(long A); +extern long _IQ27sqrt(long A); +extern long _IQ26sqrt(long A); +extern long _IQ25sqrt(long A); +extern long _IQ24sqrt(long A); +extern long _IQ23sqrt(long A); +extern long _IQ22sqrt(long A); +extern long _IQ21sqrt(long A); +extern long _IQ20sqrt(long A); +extern long _IQ19sqrt(long A); +extern long _IQ18sqrt(long A); +extern long _IQ17sqrt(long A); +extern long _IQ16sqrt(long A); +extern long _IQ15sqrt(long A); +extern long _IQ14sqrt(long A); +extern long _IQ13sqrt(long A); +extern long _IQ12sqrt(long A); +extern long _IQ11sqrt(long A); +extern long _IQ10sqrt(long A); +extern long _IQ9sqrt(long A); +extern long _IQ8sqrt(long A); +extern long _IQ7sqrt(long A); +extern long _IQ6sqrt(long A); +extern long _IQ5sqrt(long A); +extern long _IQ4sqrt(long A); +extern long _IQ3sqrt(long A); +extern long _IQ2sqrt(long A); +extern long _IQ1sqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQsqrt(A) _IQ30sqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsqrt(A) _IQ29sqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsqrt(A) _IQ28sqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsqrt(A) _IQ27sqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsqrt(A) _IQ26sqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsqrt(A) _IQ25sqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsqrt(A) _IQ24sqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsqrt(A) _IQ23sqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsqrt(A) _IQ22sqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsqrt(A) _IQ21sqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsqrt(A) _IQ20sqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsqrt(A) _IQ19sqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsqrt(A) _IQ18sqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsqrt(A) _IQ17sqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsqrt(A) _IQ16sqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsqrt(A) _IQ15sqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsqrt(A) _IQ14sqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsqrt(A) _IQ13sqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsqrt(A) _IQ12sqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsqrt(A) _IQ11sqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsqrt(A) _IQ10sqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsqrt(A) _IQ9sqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsqrt(A) _IQ8sqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsqrt(A) _IQ7sqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsqrt(A) _IQ6sqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsqrt(A) _IQ5sqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsqrt(A) _IQ4sqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsqrt(A) _IQ3sqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsqrt(A) _IQ2sqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsqrt(A) _IQ1sqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30isqrt(long A); +extern long _IQ29isqrt(long A); +extern long _IQ28isqrt(long A); +extern long _IQ27isqrt(long A); +extern long _IQ26isqrt(long A); +extern long _IQ25isqrt(long A); +extern long _IQ24isqrt(long A); +extern long _IQ23isqrt(long A); +extern long _IQ22isqrt(long A); +extern long _IQ21isqrt(long A); +extern long _IQ20isqrt(long A); +extern long _IQ19isqrt(long A); +extern long _IQ18isqrt(long A); +extern long _IQ17isqrt(long A); +extern long _IQ16isqrt(long A); +extern long _IQ15isqrt(long A); +extern long _IQ14isqrt(long A); +extern long _IQ13isqrt(long A); +extern long _IQ12isqrt(long A); +extern long _IQ11isqrt(long A); +extern long _IQ10isqrt(long A); +extern long _IQ9isqrt(long A); +extern long _IQ8isqrt(long A); +extern long _IQ7isqrt(long A); +extern long _IQ6isqrt(long A); +extern long _IQ5isqrt(long A); +extern long _IQ4isqrt(long A); +extern long _IQ3isqrt(long A); +extern long _IQ2isqrt(long A); +extern long _IQ1isqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQisqrt(A) _IQ30isqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQisqrt(A) _IQ29isqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQisqrt(A) _IQ28isqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQisqrt(A) _IQ27isqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQisqrt(A) _IQ26isqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQisqrt(A) _IQ25isqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQisqrt(A) _IQ24isqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQisqrt(A) _IQ23isqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQisqrt(A) _IQ22isqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQisqrt(A) _IQ21isqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQisqrt(A) _IQ20isqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQisqrt(A) _IQ19isqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQisqrt(A) _IQ18isqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQisqrt(A) _IQ17isqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQisqrt(A) _IQ16isqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQisqrt(A) _IQ15isqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQisqrt(A) _IQ14isqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQisqrt(A) _IQ13isqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQisqrt(A) _IQ12isqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQisqrt(A) _IQ11isqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQisqrt(A) _IQ10isqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQisqrt(A) _IQ9isqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQisqrt(A) _IQ8isqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQisqrt(A) _IQ7isqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQisqrt(A) _IQ6isqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQisqrt(A) _IQ5isqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQisqrt(A) _IQ4isqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQisqrt(A) _IQ3isqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQisqrt(A) _IQ2isqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQisqrt(A) _IQ1isqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30exp(long A); +extern long _IQ29exp(long A); +extern long _IQ28exp(long A); +extern long _IQ27exp(long A); +extern long _IQ26exp(long A); +extern long _IQ25exp(long A); +extern long _IQ24exp(long A); +extern long _IQ23exp(long A); +extern long _IQ22exp(long A); +extern long _IQ21exp(long A); +extern long _IQ20exp(long A); +extern long _IQ19exp(long A); +extern long _IQ18exp(long A); +extern long _IQ17exp(long A); +extern long _IQ16exp(long A); +extern long _IQ15exp(long A); +extern long _IQ14exp(long A); +extern long _IQ13exp(long A); +extern long _IQ12exp(long A); +extern long _IQ11exp(long A); +extern long _IQ10exp(long A); +extern long _IQ9exp(long A); +extern long _IQ8exp(long A); +extern long _IQ7exp(long A); +extern long _IQ6exp(long A); +extern long _IQ5exp(long A); +extern long _IQ4exp(long A); +extern long _IQ3exp(long A); +extern long _IQ2exp(long A); +extern long _IQ1exp(long A); + +#if GLOBAL_Q == 30 +#define _IQexp(A) _IQ30exp(A) +#endif +#if GLOBAL_Q == 29 +#define _IQexp(A) _IQ29exp(A) +#endif +#if GLOBAL_Q == 28 +#define _IQexp(A) _IQ28exp(A) +#endif +#if GLOBAL_Q == 27 +#define _IQexp(A) _IQ27exp(A) +#endif +#if GLOBAL_Q == 26 +#define _IQexp(A) _IQ26exp(A) +#endif +#if GLOBAL_Q == 25 +#define _IQexp(A) _IQ25exp(A) +#endif +#if GLOBAL_Q == 24 +#define _IQexp(A) _IQ24exp(A) +#endif +#if GLOBAL_Q == 23 +#define _IQexp(A) _IQ23exp(A) +#endif +#if GLOBAL_Q == 22 +#define _IQexp(A) _IQ22exp(A) +#endif +#if GLOBAL_Q == 21 +#define _IQexp(A) _IQ21exp(A) +#endif +#if GLOBAL_Q == 20 +#define _IQexp(A) _IQ20exp(A) +#endif +#if GLOBAL_Q == 19 +#define _IQexp(A) _IQ19exp(A) +#endif +#if GLOBAL_Q == 18 +#define _IQexp(A) _IQ18exp(A) +#endif +#if GLOBAL_Q == 17 +#define _IQexp(A) _IQ17exp(A) +#endif +#if GLOBAL_Q == 16 +#define _IQexp(A) _IQ16exp(A) +#endif +#if GLOBAL_Q == 15 +#define _IQexp(A) _IQ15exp(A) +#endif +#if GLOBAL_Q == 14 +#define _IQexp(A) _IQ14exp(A) +#endif +#if GLOBAL_Q == 13 +#define _IQexp(A) _IQ13exp(A) +#endif +#if GLOBAL_Q == 12 +#define _IQexp(A) _IQ12exp(A) +#endif +#if GLOBAL_Q == 11 +#define _IQexp(A) _IQ11exp(A) +#endif +#if GLOBAL_Q == 10 +#define _IQexp(A) _IQ10exp(A) +#endif +#if GLOBAL_Q == 9 +#define _IQexp(A) _IQ9exp(A) +#endif +#if GLOBAL_Q == 8 +#define _IQexp(A) _IQ8exp(A) +#endif +#if GLOBAL_Q == 7 +#define _IQexp(A) _IQ7exp(A) +#endif +#if GLOBAL_Q == 6 +#define _IQexp(A) _IQ6exp(A) +#endif +#if GLOBAL_Q == 5 +#define _IQexp(A) _IQ5exp(A) +#endif +#if GLOBAL_Q == 4 +#define _IQexp(A) _IQ4exp(A) +#endif +#if GLOBAL_Q == 3 +#define _IQexp(A) _IQ3exp(A) +#endif +#if GLOBAL_Q == 2 +#define _IQexp(A) _IQ2exp(A) +#endif +#if GLOBAL_Q == 1 +#define _IQexp(A) _IQ1exp(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30int(long A); +extern long _IQ29int(long A); +extern long _IQ28int(long A); +extern long _IQ27int(long A); +extern long _IQ26int(long A); +extern long _IQ25int(long A); +extern long _IQ24int(long A); +extern long _IQ23int(long A); +extern long _IQ22int(long A); +extern long _IQ21int(long A); +extern long _IQ20int(long A); +extern long _IQ19int(long A); +extern long _IQ18int(long A); +extern long _IQ17int(long A); +extern long _IQ16int(long A); +extern long _IQ15int(long A); +extern long _IQ14int(long A); +extern long _IQ13int(long A); +extern long _IQ12int(long A); +extern long _IQ11int(long A); +extern long _IQ10int(long A); +extern long _IQ9int(long A); +extern long _IQ8int(long A); +extern long _IQ7int(long A); +extern long _IQ6int(long A); +extern long _IQ5int(long A); +extern long _IQ4int(long A); +extern long _IQ3int(long A); +extern long _IQ2int(long A); +extern long _IQ1int(long A); + +#if GLOBAL_Q == 30 +#define _IQint(A) _IQ30int(A) +#endif +#if GLOBAL_Q == 29 +#define _IQint(A) _IQ29int(A) +#endif +#if GLOBAL_Q == 28 +#define _IQint(A) _IQ28int(A) +#endif +#if GLOBAL_Q == 27 +#define _IQint(A) _IQ27int(A) +#endif +#if GLOBAL_Q == 26 +#define _IQint(A) _IQ26int(A) +#endif +#if GLOBAL_Q == 25 +#define _IQint(A) _IQ25int(A) +#endif +#if GLOBAL_Q == 24 +#define _IQint(A) _IQ24int(A) +#endif +#if GLOBAL_Q == 23 +#define _IQint(A) _IQ23int(A) +#endif +#if GLOBAL_Q == 22 +#define _IQint(A) _IQ22int(A) +#endif +#if GLOBAL_Q == 21 +#define _IQint(A) _IQ21int(A) +#endif +#if GLOBAL_Q == 20 +#define _IQint(A) _IQ20int(A) +#endif +#if GLOBAL_Q == 19 +#define _IQint(A) _IQ19int(A) +#endif +#if GLOBAL_Q == 18 +#define _IQint(A) _IQ18int(A) +#endif +#if GLOBAL_Q == 17 +#define _IQint(A) _IQ17int(A) +#endif +#if GLOBAL_Q == 16 +#define _IQint(A) _IQ16int(A) +#endif +#if GLOBAL_Q == 15 +#define _IQint(A) _IQ15int(A) +#endif +#if GLOBAL_Q == 14 +#define _IQint(A) _IQ14int(A) +#endif +#if GLOBAL_Q == 13 +#define _IQint(A) _IQ13int(A) +#endif +#if GLOBAL_Q == 12 +#define _IQint(A) _IQ12int(A) +#endif +#if GLOBAL_Q == 11 +#define _IQint(A) _IQ11int(A) +#endif +#if GLOBAL_Q == 10 +#define _IQint(A) _IQ10int(A) +#endif +#if GLOBAL_Q == 9 +#define _IQint(A) _IQ9int(A) +#endif +#if GLOBAL_Q == 8 +#define _IQint(A) _IQ8int(A) +#endif +#if GLOBAL_Q == 7 +#define _IQint(A) _IQ7int(A) +#endif +#if GLOBAL_Q == 6 +#define _IQint(A) _IQ6int(A) +#endif +#if GLOBAL_Q == 5 +#define _IQint(A) _IQ5int(A) +#endif +#if GLOBAL_Q == 4 +#define _IQint(A) _IQ4int(A) +#endif +#if GLOBAL_Q == 3 +#define _IQint(A) _IQ3int(A) +#endif +#if GLOBAL_Q == 2 +#define _IQint(A) _IQ2int(A) +#endif +#if GLOBAL_Q == 1 +#define _IQint(A) _IQ1int(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30frac(long A); +extern long _IQ29frac(long A); +extern long _IQ28frac(long A); +extern long _IQ27frac(long A); +extern long _IQ26frac(long A); +extern long _IQ25frac(long A); +extern long _IQ24frac(long A); +extern long _IQ23frac(long A); +extern long _IQ22frac(long A); +extern long _IQ21frac(long A); +extern long _IQ20frac(long A); +extern long _IQ19frac(long A); +extern long _IQ18frac(long A); +extern long _IQ17frac(long A); +extern long _IQ16frac(long A); +extern long _IQ15frac(long A); +extern long _IQ14frac(long A); +extern long _IQ13frac(long A); +extern long _IQ12frac(long A); +extern long _IQ11frac(long A); +extern long _IQ10frac(long A); +extern long _IQ9frac(long A); +extern long _IQ8frac(long A); +extern long _IQ7frac(long A); +extern long _IQ6frac(long A); +extern long _IQ5frac(long A); +extern long _IQ4frac(long A); +extern long _IQ3frac(long A); +extern long _IQ2frac(long A); +extern long _IQ1frac(long A); + +#if GLOBAL_Q == 30 +#define _IQfrac(A) _IQ30frac(A) +#endif +#if GLOBAL_Q == 29 +#define _IQfrac(A) _IQ29frac(A) +#endif +#if GLOBAL_Q == 28 +#define _IQfrac(A) _IQ28frac(A) +#endif +#if GLOBAL_Q == 27 +#define _IQfrac(A) _IQ27frac(A) +#endif +#if GLOBAL_Q == 26 +#define _IQfrac(A) _IQ26frac(A) +#endif +#if GLOBAL_Q == 25 +#define _IQfrac(A) _IQ25frac(A) +#endif +#if GLOBAL_Q == 24 +#define _IQfrac(A) _IQ24frac(A) +#endif +#if GLOBAL_Q == 23 +#define _IQfrac(A) _IQ23frac(A) +#endif +#if GLOBAL_Q == 22 +#define _IQfrac(A) _IQ22frac(A) +#endif +#if GLOBAL_Q == 21 +#define _IQfrac(A) _IQ21frac(A) +#endif +#if GLOBAL_Q == 20 +#define _IQfrac(A) _IQ20frac(A) +#endif +#if GLOBAL_Q == 19 +#define _IQfrac(A) _IQ19frac(A) +#endif +#if GLOBAL_Q == 18 +#define _IQfrac(A) _IQ18frac(A) +#endif +#if GLOBAL_Q == 17 +#define _IQfrac(A) _IQ17frac(A) +#endif +#if GLOBAL_Q == 16 +#define _IQfrac(A) _IQ16frac(A) +#endif +#if GLOBAL_Q == 15 +#define _IQfrac(A) _IQ15frac(A) +#endif +#if GLOBAL_Q == 14 +#define _IQfrac(A) _IQ14frac(A) +#endif +#if GLOBAL_Q == 13 +#define _IQfrac(A) _IQ13frac(A) +#endif +#if GLOBAL_Q == 12 +#define _IQfrac(A) _IQ12frac(A) +#endif +#if GLOBAL_Q == 11 +#define _IQfrac(A) _IQ11frac(A) +#endif +#if GLOBAL_Q == 10 +#define _IQfrac(A) _IQ10frac(A) +#endif +#if GLOBAL_Q == 9 +#define _IQfrac(A) _IQ9frac(A) +#endif +#if GLOBAL_Q == 8 +#define _IQfrac(A) _IQ8frac(A) +#endif +#if GLOBAL_Q == 7 +#define _IQfrac(A) _IQ7frac(A) +#endif +#if GLOBAL_Q == 6 +#define _IQfrac(A) _IQ6frac(A) +#endif +#if GLOBAL_Q == 5 +#define _IQfrac(A) _IQ5frac(A) +#endif +#if GLOBAL_Q == 4 +#define _IQfrac(A) _IQ4frac(A) +#endif +#if GLOBAL_Q == 3 +#define _IQfrac(A) _IQ3frac(A) +#endif +#if GLOBAL_Q == 2 +#define _IQfrac(A) _IQ2frac(A) +#endif +#if GLOBAL_Q == 1 +#define _IQfrac(A) _IQ1frac(A) +#endif +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (GLOBAL_Q + 32 - IQA - IQB)) +#define _IQ30mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (30 + 32 - IQA - IQB)) +#define _IQ29mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (29 + 32 - IQA - IQB)) +#define _IQ28mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (28 + 32 - IQA - IQB)) +#define _IQ27mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (27 + 32 - IQA - IQB)) +#define _IQ26mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (26 + 32 - IQA - IQB)) +#define _IQ25mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (25 + 32 - IQA - IQB)) +#define _IQ24mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (24 + 32 - IQA - IQB)) +#define _IQ23mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (23 + 32 - IQA - IQB)) +#define _IQ22mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (22 + 32 - IQA - IQB)) +#define _IQ21mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (21 + 32 - IQA - IQB)) +#define _IQ20mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (20 + 32 - IQA - IQB)) +#define _IQ19mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (19 + 32 - IQA - IQB)) +#define _IQ18mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (18 + 32 - IQA - IQB)) +#define _IQ17mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (17 + 32 - IQA - IQB)) +#define _IQ16mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (16 + 32 - IQA - IQB)) +#define _IQ15mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (15 + 32 - IQA - IQB)) +#define _IQ14mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (14 + 32 - IQA - IQB)) +#define _IQ13mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (13 + 32 - IQA - IQB)) +#define _IQ12mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (12 + 32 - IQA - IQB)) +#define _IQ11mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (11 + 32 - IQA - IQB)) +#define _IQ10mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (10 + 32 - IQA - IQB)) +#define _IQ9mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (9 + 32 - IQA - IQB)) +#define _IQ8mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (8 + 32 - IQA - IQB)) +#define _IQ7mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (7 + 32 - IQA - IQB)) +#define _IQ6mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (6 + 32 - IQA - IQB)) +#define _IQ5mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (5 + 32 - IQA - IQB)) +#define _IQ4mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (4 + 32 - IQA - IQB)) +#define _IQ3mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (3 + 32 - IQA - IQB)) +#define _IQ2mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (2 + 32 - IQA - IQB)) +#define _IQ1mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (1 + 32 - IQA - IQB)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A)*(B)) +#define _IQ30mpyI32(A,B) ((A)*(B)) +#define _IQ29mpyI32(A,B) ((A)*(B)) +#define _IQ28mpyI32(A,B) ((A)*(B)) +#define _IQ27mpyI32(A,B) ((A)*(B)) +#define _IQ26mpyI32(A,B) ((A)*(B)) +#define _IQ25mpyI32(A,B) ((A)*(B)) +#define _IQ24mpyI32(A,B) ((A)*(B)) +#define _IQ23mpyI32(A,B) ((A)*(B)) +#define _IQ22mpyI32(A,B) ((A)*(B)) +#define _IQ21mpyI32(A,B) ((A)*(B)) +#define _IQ20mpyI32(A,B) ((A)*(B)) +#define _IQ19mpyI32(A,B) ((A)*(B)) +#define _IQ18mpyI32(A,B) ((A)*(B)) +#define _IQ17mpyI32(A,B) ((A)*(B)) +#define _IQ16mpyI32(A,B) ((A)*(B)) +#define _IQ15mpyI32(A,B) ((A)*(B)) +#define _IQ14mpyI32(A,B) ((A)*(B)) +#define _IQ13mpyI32(A,B) ((A)*(B)) +#define _IQ12mpyI32(A,B) ((A)*(B)) +#define _IQ11mpyI32(A,B) ((A)*(B)) +#define _IQ10mpyI32(A,B) ((A)*(B)) +#define _IQ9mpyI32(A,B) ((A)*(B)) +#define _IQ8mpyI32(A,B) ((A)*(B)) +#define _IQ7mpyI32(A,B) ((A)*(B)) +#define _IQ6mpyI32(A,B) ((A)*(B)) +#define _IQ5mpyI32(A,B) ((A)*(B)) +#define _IQ4mpyI32(A,B) ((A)*(B)) +#define _IQ3mpyI32(A,B) ((A)*(B)) +#define _IQ2mpyI32(A,B) ((A)*(B)) +#define _IQ1mpyI32(A,B) ((A)*(B)) +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32int(long A, long B); +extern long _IQ29mpyI32int(long A, long B); +extern long _IQ28mpyI32int(long A, long B); +extern long _IQ27mpyI32int(long A, long B); +extern long _IQ26mpyI32int(long A, long B); +extern long _IQ25mpyI32int(long A, long B); +extern long _IQ24mpyI32int(long A, long B); +extern long _IQ23mpyI32int(long A, long B); +extern long _IQ22mpyI32int(long A, long B); +extern long _IQ21mpyI32int(long A, long B); +extern long _IQ20mpyI32int(long A, long B); +extern long _IQ19mpyI32int(long A, long B); +extern long _IQ18mpyI32int(long A, long B); +extern long _IQ17mpyI32int(long A, long B); +extern long _IQ16mpyI32int(long A, long B); +extern long _IQ15mpyI32int(long A, long B); +extern long _IQ14mpyI32int(long A, long B); +extern long _IQ13mpyI32int(long A, long B); +extern long _IQ12mpyI32int(long A, long B); +extern long _IQ11mpyI32int(long A, long B); +extern long _IQ10mpyI32int(long A, long B); +extern long _IQ9mpyI32int(long A, long B); +extern long _IQ8mpyI32int(long A, long B); +extern long _IQ7mpyI32int(long A, long B); +extern long _IQ6mpyI32int(long A, long B); +extern long _IQ5mpyI32int(long A, long B); +extern long _IQ4mpyI32int(long A, long B); +extern long _IQ3mpyI32int(long A, long B); +extern long _IQ2mpyI32int(long A, long B); +extern long _IQ1mpyI32int(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32int(A, B) _IQ30mpyI32int(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32int(A, B) _IQ29mpyI32int(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32int(A, B) _IQ28mpyI32int(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32int(A, B) _IQ27mpyI32int(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32int(A, B) _IQ26mpyI32int(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32int(A, B) _IQ25mpyI32int(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32int(A, B) _IQ24mpyI32int(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32int(A, B) _IQ23mpyI32int(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32int(A, B) _IQ22mpyI32int(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32int(A, B) _IQ21mpyI32int(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32int(A, B) _IQ20mpyI32int(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32int(A, B) _IQ19mpyI32int(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32int(A, B) _IQ18mpyI32int(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32int(A, B) _IQ17mpyI32int(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32int(A, B) _IQ16mpyI32int(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32int(A, B) _IQ15mpyI32int(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32int(A, B) _IQ14mpyI32int(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32int(A, B) _IQ13mpyI32int(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32int(A, B) _IQ12mpyI32int(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32int(A, B) _IQ11mpyI32int(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32int(A, B) _IQ10mpyI32int(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32int(A, B) _IQ9mpyI32int(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32int(A, B) _IQ8mpyI32int(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32int(A, B) _IQ7mpyI32int(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32int(A, B) _IQ6mpyI32int(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32int(A, B) _IQ5mpyI32int(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32int(A, B) _IQ4mpyI32int(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32int(A, B) _IQ3mpyI32int(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32int(A, B) _IQ2mpyI32int(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32int(A, B) _IQ1mpyI32int(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32frac(long A, long B); +extern long _IQ29mpyI32frac(long A, long B); +extern long _IQ28mpyI32frac(long A, long B); +extern long _IQ27mpyI32frac(long A, long B); +extern long _IQ26mpyI32frac(long A, long B); +extern long _IQ25mpyI32frac(long A, long B); +extern long _IQ24mpyI32frac(long A, long B); +extern long _IQ23mpyI32frac(long A, long B); +extern long _IQ22mpyI32frac(long A, long B); +extern long _IQ21mpyI32frac(long A, long B); +extern long _IQ20mpyI32frac(long A, long B); +extern long _IQ19mpyI32frac(long A, long B); +extern long _IQ18mpyI32frac(long A, long B); +extern long _IQ17mpyI32frac(long A, long B); +extern long _IQ16mpyI32frac(long A, long B); +extern long _IQ15mpyI32frac(long A, long B); +extern long _IQ14mpyI32frac(long A, long B); +extern long _IQ13mpyI32frac(long A, long B); +extern long _IQ12mpyI32frac(long A, long B); +extern long _IQ11mpyI32frac(long A, long B); +extern long _IQ10mpyI32frac(long A, long B); +extern long _IQ9mpyI32frac(long A, long B); +extern long _IQ8mpyI32frac(long A, long B); +extern long _IQ7mpyI32frac(long A, long B); +extern long _IQ6mpyI32frac(long A, long B); +extern long _IQ5mpyI32frac(long A, long B); +extern long _IQ4mpyI32frac(long A, long B); +extern long _IQ3mpyI32frac(long A, long B); +extern long _IQ2mpyI32frac(long A, long B); +extern long _IQ1mpyI32frac(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32frac(A, B) _IQ30mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32frac(A, B) _IQ29mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32frac(A, B) _IQ28mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32frac(A, B) _IQ27mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32frac(A, B) _IQ26mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32frac(A, B) _IQ25mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32frac(A, B) _IQ24mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32frac(A, B) _IQ23mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32frac(A, B) _IQ22mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32frac(A, B) _IQ21mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32frac(A, B) _IQ20mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32frac(A, B) _IQ19mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32frac(A, B) _IQ18mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32frac(A, B) _IQ17mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32frac(A, B) _IQ16mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32frac(A, B) _IQ15mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32frac(A, B) _IQ14mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32frac(A, B) _IQ13mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32frac(A, B) _IQ12mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32frac(A, B) _IQ11mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32frac(A, B) _IQ10mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32frac(A, B) _IQ9mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32frac(A, B) _IQ8mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32frac(A, B) _IQ7mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32frac(A, B) _IQ6mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32frac(A, B) _IQ5mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32frac(A, B) _IQ4mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32frac(A, B) _IQ3mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32frac(A, B) _IQ2mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32frac(A, B) _IQ1mpyI32frac(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mag(long A, long B); +extern long _IQ29mag(long A, long B); +extern long _IQ28mag(long A, long B); +extern long _IQ27mag(long A, long B); +extern long _IQ26mag(long A, long B); +extern long _IQ25mag(long A, long B); +extern long _IQ24mag(long A, long B); +extern long _IQ23mag(long A, long B); +extern long _IQ22mag(long A, long B); +extern long _IQ21mag(long A, long B); +extern long _IQ20mag(long A, long B); +extern long _IQ19mag(long A, long B); +extern long _IQ18mag(long A, long B); +extern long _IQ17mag(long A, long B); +extern long _IQ16mag(long A, long B); +extern long _IQ15mag(long A, long B); +extern long _IQ14mag(long A, long B); +extern long _IQ13mag(long A, long B); +extern long _IQ12mag(long A, long B); +extern long _IQ11mag(long A, long B); +extern long _IQ10mag(long A, long B); +extern long _IQ9mag(long A, long B); +extern long _IQ8mag(long A, long B); +extern long _IQ7mag(long A, long B); +extern long _IQ6mag(long A, long B); +extern long _IQ5mag(long A, long B); +extern long _IQ4mag(long A, long B); +extern long _IQ3mag(long A, long B); +extern long _IQ2mag(long A, long B); +extern long _IQ1mag(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmag(A, B) _IQ30mag(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmag(A, B) _IQ29mag(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmag(A, B) _IQ28mag(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmag(A, B) _IQ27mag(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmag(A, B) _IQ26mag(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmag(A, B) _IQ25mag(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmag(A, B) _IQ24mag(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmag(A, B) _IQ23mag(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmag(A, B) _IQ22mag(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmag(A, B) _IQ21mag(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmag(A, B) _IQ20mag(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmag(A, B) _IQ19mag(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmag(A, B) _IQ18mag(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmag(A, B) _IQ17mag(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmag(A, B) _IQ16mag(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmag(A, B) _IQ15mag(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmag(A, B) _IQ14mag(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmag(A, B) _IQ13mag(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmag(A, B) _IQ12mag(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmag(A, B) _IQ11mag(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmag(A, B) _IQ10mag(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmag(A, B) _IQ9mag(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmag(A, B) _IQ8mag(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmag(A, B) _IQ7mag(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmag(A, B) _IQ6mag(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmag(A, B) _IQ5mag(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmag(A, B) _IQ4mag(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmag(A, B) _IQ3mag(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmag(A, B) _IQ2mag(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmag(A, B) _IQ1mag(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _atoIQN(const char *A, long q_value); +#define _atoIQ(A) _atoIQN(A, GLOBAL_Q) +#define _atoIQ30(A) _atoIQN(A, 30) +#define _atoIQ29(A) _atoIQN(A, 29) +#define _atoIQ28(A) _atoIQN(A, 28) +#define _atoIQ27(A) _atoIQN(A, 27) +#define _atoIQ26(A) _atoIQN(A, 26) +#define _atoIQ25(A) _atoIQN(A, 25) +#define _atoIQ24(A) _atoIQN(A, 24) +#define _atoIQ23(A) _atoIQN(A, 23) +#define _atoIQ22(A) _atoIQN(A, 22) +#define _atoIQ21(A) _atoIQN(A, 21) +#define _atoIQ20(A) _atoIQN(A, 20) +#define _atoIQ19(A) _atoIQN(A, 19) +#define _atoIQ18(A) _atoIQN(A, 18) +#define _atoIQ17(A) _atoIQN(A, 17) +#define _atoIQ16(A) _atoIQN(A, 16) +#define _atoIQ15(A) _atoIQN(A, 15) +#define _atoIQ14(A) _atoIQN(A, 14) +#define _atoIQ13(A) _atoIQN(A, 13) +#define _atoIQ12(A) _atoIQN(A, 12) +#define _atoIQ11(A) _atoIQN(A, 11) +#define _atoIQ10(A) _atoIQN(A, 10) +#define _atoIQ9(A) _atoIQN(A, 9) +#define _atoIQ8(A) _atoIQN(A, 8) +#define _atoIQ7(A) _atoIQN(A, 7) +#define _atoIQ6(A) _atoIQN(A, 6) +#define _atoIQ5(A) _atoIQN(A, 5) +#define _atoIQ4(A) _atoIQN(A, 4) +#define _atoIQ3(A) _atoIQN(A, 3) +#define _atoIQ2(A) _atoIQN(A, 2) +#define _atoIQ1(A) _atoIQN(A, 1) +//--------------------------------------------------------------------------- +extern int __IQNtoa(char *A, const char *B, long C, int D); +extern int _IQ30toa(char *A, const char *B, long C); +extern int _IQ29toa(char *A, const char *B, long C); +extern int _IQ28toa(char *A, const char *B, long C); +extern int _IQ27toa(char *A, const char *B, long C); +extern int _IQ26toa(char *A, const char *B, long C); +extern int _IQ25toa(char *A, const char *B, long C); +extern int _IQ24toa(char *A, const char *B, long C); +extern int _IQ23toa(char *A, const char *B, long C); +extern int _IQ22toa(char *A, const char *B, long C); +extern int _IQ21toa(char *A, const char *B, long C); +extern int _IQ20toa(char *A, const char *B, long C); +extern int _IQ19toa(char *A, const char *B, long C); +extern int _IQ18toa(char *A, const char *B, long C); +extern int _IQ17toa(char *A, const char *B, long C); +extern int _IQ16toa(char *A, const char *B, long C); +extern int _IQ15toa(char *A, const char *B, long C); +extern int _IQ14toa(char *A, const char *B, long C); +extern int _IQ13toa(char *A, const char *B, long C); +extern int _IQ12toa(char *A, const char *B, long C); +extern int _IQ11toa(char *A, const char *B, long C); +extern int _IQ10toa(char *A, const char *B, long C); +extern int _IQ9toa(char *A, const char *B, long C); +extern int _IQ8toa(char *A, const char *B, long C); +extern int _IQ7toa(char *A, const char *B, long C); +extern int _IQ6toa(char *A, const char *B, long C); +extern int _IQ5toa(char *A, const char *B, long C); +extern int _IQ4toa(char *A, const char *B, long C); +extern int _IQ3toa(char *A, const char *B, long C); +extern int _IQ2toa(char *A, const char *B, long C); +extern int _IQ1toa(char *A, const char *B, long C); + + +#define _IQ30toa(A, B, C) __IQNtoa(A, B, C, 30); +#define _IQ29toa(A, B, C) __IQNtoa(A, B, C, 29); +#define _IQ28toa(A, B, C) __IQNtoa(A, B, C, 28); +#define _IQ27toa(A, B, C) __IQNtoa(A, B, C, 27); +#define _IQ26toa(A, B, C) __IQNtoa(A, B, C, 26); +#define _IQ25toa(A, B, C) __IQNtoa(A, B, C, 25); +#define _IQ24toa(A, B, C) __IQNtoa(A, B, C, 24); +#define _IQ23toa(A, B, C) __IQNtoa(A, B, C, 23); +#define _IQ21toa(A, B, C) __IQNtoa(A, B, C, 21); +#define _IQ22toa(A, B, C) __IQNtoa(A, B, C, 22); +#define _IQ20toa(A, B, C) __IQNtoa(A, B, C, 20); +#define _IQ19toa(A, B, C) __IQNtoa(A, B, C, 19); +#define _IQ18toa(A, B, C) __IQNtoa(A, B, C, 18); +#define _IQ17toa(A, B, C) __IQNtoa(A, B, C, 17); +#define _IQ16toa(A, B, C) __IQNtoa(A, B, C, 16); +#define _IQ15toa(A, B, C) __IQNtoa(A, B, C, 15); +#define _IQ14toa(A, B, C) __IQNtoa(A, B, C, 14); +#define _IQ13toa(A, B, C) __IQNtoa(A, B, C, 13); +#define _IQ12toa(A, B, C) __IQNtoa(A, B, C, 12); +#define _IQ11toa(A, B, C) __IQNtoa(A, B, C, 11); +#define _IQ10toa(A, B, C) __IQNtoa(A, B, C, 10); +#define _IQ9toa(A, B, C) __IQNtoa(A, B, C, 9); +#define _IQ8toa(A, B, C) __IQNtoa(A, B, C, 8); +#define _IQ7toa(A, B, C) __IQNtoa(A, B, C, 7); +#define _IQ6toa(A, B, C) __IQNtoa(A, B, C, 6); +#define _IQ5toa(A, B, C) __IQNtoa(A, B, C, 5); +#define _IQ4toa(A, B, C) __IQNtoa(A, B, C, 4); +#define _IQ3toa(A, B, C) __IQNtoa(A, B, C, 3); +#define _IQ2toa(A, B, C) __IQNtoa(A, B, C, 2); +#define _IQ1toa(A, B, C) __IQNtoa(A, B, C, 1); + + +#if GLOBAL_Q == 30 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 30) +#endif +#if GLOBAL_Q == 29 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 29) +#endif +#if GLOBAL_Q == 28 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 28) +#endif +#if GLOBAL_Q == 27 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 27) +#endif +#if GLOBAL_Q == 26 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 26) +#endif +#if GLOBAL_Q == 25 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 25) +#endif +#if GLOBAL_Q == 24 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 24) +#endif +#if GLOBAL_Q == 23 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 23) +#endif +#if GLOBAL_Q == 22 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 22) +#endif +#if GLOBAL_Q == 21 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 21) +#endif +#if GLOBAL_Q == 20 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 20) +#endif +#if GLOBAL_Q == 19 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 19) +#endif +#if GLOBAL_Q == 18 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 18) +#endif +#if GLOBAL_Q == 17 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 17) +#endif +#if GLOBAL_Q == 16 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 16) +#endif +#if GLOBAL_Q == 15 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 15) +#endif +#if GLOBAL_Q == 14 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 14) +#endif +#if GLOBAL_Q == 13 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 13) +#endif +#if GLOBAL_Q == 12 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 12) +#endif +#if GLOBAL_Q == 11 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 11) +#endif +#if GLOBAL_Q == 10 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 10) +#endif +#if GLOBAL_Q == 9 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 9) +#endif +#if GLOBAL_Q == 8 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 8) +#endif +#if GLOBAL_Q == 7 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 7) +#endif +#if GLOBAL_Q == 6 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 6) +#endif +#if GLOBAL_Q == 5 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 5) +#endif +#if GLOBAL_Q == 4 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 4) +#endif +#if GLOBAL_Q == 3 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 3) +#endif +#if GLOBAL_Q == 2 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 2) +#endif +#if GLOBAL_Q == 1 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 1) +#endif +//--------------------------------------------------------------------------- +#define _IQabs(A) labs(A) +#define _IQ30abs(A) labs(A) +#define _IQ29abs(A) labs(A) +#define _IQ28abs(A) labs(A) +#define _IQ27abs(A) labs(A) +#define _IQ26abs(A) labs(A) +#define _IQ25abs(A) labs(A) +#define _IQ24abs(A) labs(A) +#define _IQ23abs(A) labs(A) +#define _IQ22abs(A) labs(A) +#define _IQ21abs(A) labs(A) +#define _IQ20abs(A) labs(A) +#define _IQ19abs(A) labs(A) +#define _IQ18abs(A) labs(A) +#define _IQ17abs(A) labs(A) +#define _IQ16abs(A) labs(A) +#define _IQ15abs(A) labs(A) +#define _IQ14abs(A) labs(A) +#define _IQ13abs(A) labs(A) +#define _IQ12abs(A) labs(A) +#define _IQ11abs(A) labs(A) +#define _IQ10abs(A) labs(A) +#define _IQ9abs(A) labs(A) +#define _IQ8abs(A) labs(A) +#define _IQ7abs(A) labs(A) +#define _IQ6abs(A) labs(A) +#define _IQ5abs(A) labs(A) +#define _IQ4abs(A) labs(A) +#define _IQ3abs(A) labs(A) +#define _IQ2abs(A) labs(A) +#define _IQ1abs(A) labs(A) +//########################################################################### +#else // MATH_TYPE == FLOAT_MATH +//########################################################################### +// If FLOAT_MATH is used, the IQmath library function are replaced by +// equivalent floating point operations: +//=========================================================================== +typedef float _iq; +typedef float _iq30; +typedef float _iq29; +typedef float _iq28; +typedef float _iq27; +typedef float _iq26; +typedef float _iq25; +typedef float _iq24; +typedef float _iq23; +typedef float _iq22; +typedef float _iq21; +typedef float _iq20; +typedef float _iq19; +typedef float _iq18; +typedef float _iq17; +typedef float _iq16; +typedef float _iq15; +typedef float _iq14; +typedef float _iq13; +typedef float _iq12; +typedef float _iq11; +typedef float _iq10; +typedef float _iq9; +typedef float _iq8; +typedef float _iq7; +typedef float _iq6; +typedef float _iq5; +typedef float _iq4; +typedef float _iq3; +typedef float _iq2; +typedef float _iq1; +//--------------------------------------------------------------------------- +#define _IQ(A) (A) +#define _IQ30(A) (A) +#define _IQ29(A) (A) +#define _IQ28(A) (A) +#define _IQ27(A) (A) +#define _IQ26(A) (A) +#define _IQ25(A) (A) +#define _IQ24(A) (A) +#define _IQ23(A) (A) +#define _IQ22(A) (A) +#define _IQ21(A) (A) +#define _IQ20(A) (A) +#define _IQ19(A) (A) +#define _IQ18(A) (A) +#define _IQ17(A) (A) +#define _IQ16(A) (A) +#define _IQ15(A) (A) +#define _IQ14(A) (A) +#define _IQ13(A) (A) +#define _IQ12(A) (A) +#define _IQ10(A) (A) +#define _IQ9(A) (A) +#define _IQ8(A) (A) +#define _IQ7(A) (A) +#define _IQ6(A) (A) +#define _IQ5(A) (A) +#define _IQ4(A) (A) +#define _IQ3(A) (A) +#define _IQ2(A) (A) +#define _IQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoF(A) (A) +#define _IQ30toF(A) (A) +#define _IQ29toF(A) (A) +#define _IQ28toF(A) (A) +#define _IQ27toF(A) (A) +#define _IQ26toF(A) (A) +#define _IQ25toF(A) (A) +#define _IQ24toF(A) (A) +#define _IQ23toF(A) (A) +#define _IQ22toF(A) (A) +#define _IQ21toF(A) (A) +#define _IQ20toF(A) (A) +#define _IQ19toF(A) (A) +#define _IQ18toF(A) (A) +#define _IQ17toF(A) (A) +#define _IQ16toF(A) (A) +#define _IQ15toF(A) (A) +#define _IQ14toF(A) (A) +#define _IQ13toF(A) (A) +#define _IQ12toF(A) (A) +#define _IQ11toF(A) (A) +#define _IQ10toF(A) (A) +#define _IQ9toF(A) (A) +#define _IQ8toF(A) (A) +#define _IQ7toF(A) (A) +#define _IQ6toF(A) (A) +#define _IQ5toF(A) (A) +#define _IQ4toF(A) (A) +#define _IQ3toF(A) (A) +#define _IQ2toF(A) (A) +#define _IQ1toF(A) (A) +//--------------------------------------------------------------------------- +extern float _satf(float A, float Pos, float Neg); +#define _IQsat(A, Pos, Neg) _satf(A, Pos, Neg) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) (A) +#define _IQtoIQ29(A) (A) +#define _IQtoIQ28(A) (A) +#define _IQtoIQ27(A) (A) +#define _IQtoIQ26(A) (A) +#define _IQtoIQ25(A) (A) +#define _IQtoIQ24(A) (A) +#define _IQtoIQ23(A) (A) +#define _IQtoIQ22(A) (A) +#define _IQtoIQ21(A) (A) +#define _IQtoIQ20(A) (A) +#define _IQtoIQ19(A) (A) +#define _IQtoIQ18(A) (A) +#define _IQtoIQ17(A) (A) +#define _IQtoIQ16(A) (A) +#define _IQtoIQ15(A) (A) +#define _IQtoIQ14(A) (A) +#define _IQtoIQ13(A) (A) +#define _IQtoIQ12(A) (A) +#define _IQtoIQ11(A) (A) +#define _IQtoIQ10(A) (A) +#define _IQtoIQ9(A) (A) +#define _IQtoIQ8(A) (A) +#define _IQtoIQ7(A) (A) +#define _IQtoIQ6(A) (A) +#define _IQtoIQ5(A) (A) +#define _IQtoIQ4(A) (A) +#define _IQtoIQ3(A) (A) +#define _IQtoIQ2(A) (A) +#define _IQtoIQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQ30toIQ(A) (A) +#define _IQ29toIQ(A) (A) +#define _IQ28toIQ(A) (A) +#define _IQ27toIQ(A) (A) +#define _IQ26toIQ(A) (A) +#define _IQ25toIQ(A) (A) +#define _IQ24toIQ(A) (A) +#define _IQ23toIQ(A) (A) +#define _IQ22toIQ(A) (A) +#define _IQ21toIQ(A) (A) +#define _IQ20toIQ(A) (A) +#define _IQ19toIQ(A) (A) +#define _IQ18toIQ(A) (A) +#define _IQ17toIQ(A) (A) +#define _IQ16toIQ(A) (A) +#define _IQ15toIQ(A) (A) +#define _IQ14toIQ(A) (A) +#define _IQ13toIQ(A) (A) +#define _IQ12toIQ(A) (A) +#define _IQ11toIQ(A) (A) +#define _IQ10toIQ(A) (A) +#define _IQ9toIQ(A) (A) +#define _IQ8toIQ(A) (A) +#define _IQ7toIQ(A) (A) +#define _IQ6toIQ(A) (A) +#define _IQ5toIQ(A) (A) +#define _IQ4toIQ(A) (A) +#define _IQ3toIQ(A) (A) +#define _IQ2toIQ(A) (A) +#define _IQ1toIQ(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoQ15(A) (short) ((long)((A) * 32768.0L)) +#define _IQtoQ14(A) (short) ((long)((A) * 16384.0L)) +#define _IQtoQ13(A) (short) ((long)((A) * 8192.0L)) +#define _IQtoQ12(A) (short) ((long)((A) * 4096.0L)) +#define _IQtoQ11(A) (short) ((long)((A) * 2048.0L)) +#define _IQtoQ10(A) (short) ((long)((A) * 1024.0L)) +#define _IQtoQ9(A) (short) ((long)((A) * 512.0L)) +#define _IQtoQ8(A) (short) ((long)((A) * 256.0L)) +#define _IQtoQ7(A) (short) ((long)((A) * 128.0L)) +#define _IQtoQ6(A) (short) ((long)((A) * 64.0L)) +#define _IQtoQ5(A) (short) ((long)((A) * 32.0L)) +#define _IQtoQ4(A) (short) ((long)((A) * 16.0L)) +#define _IQtoQ3(A) (short) ((long)((A) * 8.0L)) +#define _IQtoQ2(A) (short) ((long)((A) * 4.0L)) +#define _IQtoQ1(A) (short) ((long)((A) * 2.0L)) + +//--------------------------------------------------------------------------- +#define _Q15toIQ(A) (((float) (A)) * 0.000030518) +#define _Q14toIQ(A) (((float) (A)) * 0.000061035) +#define _Q13toIQ(A) (((float) (A)) * 0.000122070) +#define _Q12toIQ(A) (((float) (A)) * 0.000244141) +#define _Q11toIQ(A) (((float) (A)) * 0.000488281) +#define _Q10toIQ(A) (((float) (A)) * 0.000976563) +#define _Q9toIQ(A) (((float) (A)) * 0.001953125) +#define _Q8toIQ(A) (((float) (A)) * 0.003906250) +#define _Q7toIQ(A) (((float) (A)) * 0.007812500) +#define _Q6toIQ(A) (((float) (A)) * 0.015625000) +#define _Q5toIQ(A) (((float) (A)) * 0.031250000) +#define _Q4toIQ(A) (((float) (A)) * 0.062500000) +#define _Q3toIQ(A) (((float) (A)) * 0.125000000) +#define _Q2toIQ(A) (((float) (A)) * 0.250000000) +#define _Q1toIQ(A) (((float) (A)) * 0.500000000) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) ((A) * (B)) +#define _IQ30mpy(A,B) ((A) * (B)) +#define _IQ29mpy(A,B) ((A) * (B)) +#define _IQ28mpy(A,B) ((A) * (B)) +#define _IQ27mpy(A,B) ((A) * (B)) +#define _IQ26mpy(A,B) ((A) * (B)) +#define _IQ25mpy(A,B) ((A) * (B)) +#define _IQ24mpy(A,B) ((A) * (B)) +#define _IQ23mpy(A,B) ((A) * (B)) +#define _IQ22mpy(A,B) ((A) * (B)) +#define _IQ21mpy(A,B) ((A) * (B)) +#define _IQ20mpy(A,B) ((A) * (B)) +#define _IQ19mpy(A,B) ((A) * (B)) +#define _IQ18mpy(A,B) ((A) * (B)) +#define _IQ17mpy(A,B) ((A) * (B)) +#define _IQ16mpy(A,B) ((A) * (B)) +#define _IQ15mpy(A,B) ((A) * (B)) +#define _IQ14mpy(A,B) ((A) * (B)) +#define _IQ13mpy(A,B) ((A) * (B)) +#define _IQ12mpy(A,B) ((A) * (B)) +#define _IQ11mpy(A,B) ((A) * (B)) +#define _IQ10mpy(A,B) ((A) * (B)) +#define _IQ9mpy(A,B) ((A) * (B)) +#define _IQ8mpy(A,B) ((A) * (B)) +#define _IQ7mpy(A,B) ((A) * (B)) +#define _IQ6mpy(A,B) ((A) * (B)) +#define _IQ5mpy(A,B) ((A) * (B)) +#define _IQ4mpy(A,B) ((A) * (B)) +#define _IQ3mpy(A,B) ((A) * (B)) +#define _IQ2mpy(A,B) ((A) * (B)) +#define _IQ1mpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrmpy(A,B) ((A) * (B)) +#define _IQ30rmpy(A,B) ((A) * (B)) +#define _IQ29rmpy(A,B) ((A) * (B)) +#define _IQ28rmpy(A,B) ((A) * (B)) +#define _IQ27rmpy(A,B) ((A) * (B)) +#define _IQ26rmpy(A,B) ((A) * (B)) +#define _IQ25rmpy(A,B) ((A) * (B)) +#define _IQ24rmpy(A,B) ((A) * (B)) +#define _IQ23rmpy(A,B) ((A) * (B)) +#define _IQ22rmpy(A,B) ((A) * (B)) +#define _IQ21rmpy(A,B) ((A) * (B)) +#define _IQ20rmpy(A,B) ((A) * (B)) +#define _IQ19rmpy(A,B) ((A) * (B)) +#define _IQ18rmpy(A,B) ((A) * (B)) +#define _IQ17rmpy(A,B) ((A) * (B)) +#define _IQ16rmpy(A,B) ((A) * (B)) +#define _IQ15rmpy(A,B) ((A) * (B)) +#define _IQ14rmpy(A,B) ((A) * (B)) +#define _IQ13rmpy(A,B) ((A) * (B)) +#define _IQ12rmpy(A,B) ((A) * (B)) +#define _IQ11rmpy(A,B) ((A) * (B)) +#define _IQ10rmpy(A,B) ((A) * (B)) +#define _IQ9rmpy(A,B) ((A) * (B)) +#define _IQ8rmpy(A,B) ((A) * (B)) +#define _IQ7rmpy(A,B) ((A) * (B)) +#define _IQ6rmpy(A,B) ((A) * (B)) +#define _IQ5rmpy(A,B) ((A) * (B)) +#define _IQ4rmpy(A,B) ((A) * (B)) +#define _IQ3rmpy(A,B) ((A) * (B)) +#define _IQ2rmpy(A,B) ((A) * (B)) +#define _IQ1rmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrsmpy(A,B) ((A) * (B)) +#define _IQ30rsmpy(A,B) ((A) * (B)) +#define _IQ29rsmpy(A,B) ((A) * (B)) +#define _IQ28rsmpy(A,B) ((A) * (B)) +#define _IQ27rsmpy(A,B) ((A) * (B)) +#define _IQ26rsmpy(A,B) ((A) * (B)) +#define _IQ25rsmpy(A,B) ((A) * (B)) +#define _IQ24rsmpy(A,B) ((A) * (B)) +#define _IQ23rsmpy(A,B) ((A) * (B)) +#define _IQ22rsmpy(A,B) ((A) * (B)) +#define _IQ21rsmpy(A,B) ((A) * (B)) +#define _IQ20rsmpy(A,B) ((A) * (B)) +#define _IQ19rsmpy(A,B) ((A) * (B)) +#define _IQ18rsmpy(A,B) ((A) * (B)) +#define _IQ17rsmpy(A,B) ((A) * (B)) +#define _IQ16rsmpy(A,B) ((A) * (B)) +#define _IQ15rsmpy(A,B) ((A) * (B)) +#define _IQ14rsmpy(A,B) ((A) * (B)) +#define _IQ13rsmpy(A,B) ((A) * (B)) +#define _IQ12rsmpy(A,B) ((A) * (B)) +#define _IQ11rsmpy(A,B) ((A) * (B)) +#define _IQ10rsmpy(A,B) ((A) * (B)) +#define _IQ9rsmpy(A,B) ((A) * (B)) +#define _IQ8rsmpy(A,B) ((A) * (B)) +#define _IQ7rsmpy(A,B) ((A) * (B)) +#define _IQ6rsmpy(A,B) ((A) * (B)) +#define _IQ5rsmpy(A,B) ((A) * (B)) +#define _IQ4rsmpy(A,B) ((A) * (B)) +#define _IQ3rsmpy(A,B) ((A) * (B)) +#define _IQ2rsmpy(A,B) ((A) * (B)) +#define _IQ1rsmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQdiv(A,B) ((A) / (B)) +#define _IQ30div(A,B) ((A) / (B)) +#define _IQ29div(A,B) ((A) / (B)) +#define _IQ28div(A,B) ((A) / (B)) +#define _IQ27div(A,B) ((A) / (B)) +#define _IQ26div(A,B) ((A) / (B)) +#define _IQ25div(A,B) ((A) / (B)) +#define _IQ24div(A,B) ((A) / (B)) +#define _IQ23div(A,B) ((A) / (B)) +#define _IQ22div(A,B) ((A) / (B)) +#define _IQ21div(A,B) ((A) / (B)) +#define _IQ20div(A,B) ((A) / (B)) +#define _IQ19div(A,B) ((A) / (B)) +#define _IQ18div(A,B) ((A) / (B)) +#define _IQ17div(A,B) ((A) / (B)) +#define _IQ16div(A,B) ((A) / (B)) +#define _IQ15div(A,B) ((A) / (B)) +#define _IQ14div(A,B) ((A) / (B)) +#define _IQ13div(A,B) ((A) / (B)) +#define _IQ12div(A,B) ((A) / (B)) +#define _IQ11div(A,B) ((A) / (B)) +#define _IQ10div(A,B) ((A) / (B)) +#define _IQ9div(A,B) ((A) / (B)) +#define _IQ8div(A,B) ((A) / (B)) +#define _IQ7div(A,B) ((A) / (B)) +#define _IQ6div(A,B) ((A) / (B)) +#define _IQ5div(A,B) ((A) / (B)) +#define _IQ4div(A,B) ((A) / (B)) +#define _IQ3div(A,B) ((A) / (B)) +#define _IQ2div(A,B) ((A) / (B)) +#define _IQ1div(A,B) ((A) / (B)) +//--------------------------------------------------------------------------- +#define _IQsin(A) sin(A) +#define _IQ30sin(A) sin(A) +#define _IQ29sin(A) sin(A) +#define _IQ28sin(A) sin(A) +#define _IQ27sin(A) sin(A) +#define _IQ26sin(A) sin(A) +#define _IQ25sin(A) sin(A) +#define _IQ24sin(A) sin(A) +#define _IQ23sin(A) sin(A) +#define _IQ22sin(A) sin(A) +#define _IQ21sin(A) sin(A) +#define _IQ20sin(A) sin(A) +#define _IQ19sin(A) sin(A) +#define _IQ18sin(A) sin(A) +#define _IQ17sin(A) sin(A) +#define _IQ16sin(A) sin(A) +#define _IQ15sin(A) sin(A) +#define _IQ14sin(A) sin(A) +#define _IQ13sin(A) sin(A) +#define _IQ12sin(A) sin(A) +#define _IQ11sin(A) sin(A) +#define _IQ10sin(A) sin(A) +#define _IQ9sin(A) sin(A) +#define _IQ8sin(A) sin(A) +#define _IQ7sin(A) sin(A) +#define _IQ6sin(A) sin(A) +#define _IQ5sin(A) sin(A) +#define _IQ4sin(A) sin(A) +#define _IQ3sin(A) sin(A) +#define _IQ2sin(A) sin(A) +#define _IQ1sin(A) sin(A) +//--------------------------------------------------------------------------- +#define _IQsinPU(A) sin((A)*6.283185307) +#define _IQ30sinPU(A) sin((A)*6.283185307) +#define _IQ29sinPU(A) sin((A)*6.283185307) +#define _IQ28sinPU(A) sin((A)*6.283185307) +#define _IQ27sinPU(A) sin((A)*6.283185307) +#define _IQ26sinPU(A) sin((A)*6.283185307) +#define _IQ25sinPU(A) sin((A)*6.283185307) +#define _IQ24sinPU(A) sin((A)*6.283185307) +#define _IQ23sinPU(A) sin((A)*6.283185307) +#define _IQ22sinPU(A) sin((A)*6.283185307) +#define _IQ21sinPU(A) sin((A)*6.283185307) +#define _IQ20sinPU(A) sin((A)*6.283185307) +#define _IQ19sinPU(A) sin((A)*6.283185307) +#define _IQ18sinPU(A) sin((A)*6.283185307) +#define _IQ17sinPU(A) sin((A)*6.283185307) +#define _IQ16sinPU(A) sin((A)*6.283185307) +#define _IQ15sinPU(A) sin((A)*6.283185307) +#define _IQ14sinPU(A) sin((A)*6.283185307) +#define _IQ13sinPU(A) sin((A)*6.283185307) +#define _IQ12sinPU(A) sin((A)*6.283185307) +#define _IQ11sinPU(A) sin((A)*6.283185307) +#define _IQ10sinPU(A) sin((A)*6.283185307) +#define _IQ9sinPU(A) sin((A)*6.283185307) +#define _IQ8sinPU(A) sin((A)*6.283185307) +#define _IQ7sinPU(A) sin((A)*6.283185307) +#define _IQ6sinPU(A) sin((A)*6.283185307) +#define _IQ5sinPU(A) sin((A)*6.283185307) +#define _IQ4sinPU(A) sin((A)*6.283185307) +#define _IQ3sinPU(A) sin((A)*6.283185307) +#define _IQ2sinPU(A) sin((A)*6.283185307) +#define _IQ1sinPU(A) sin((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQasin(A) asin(A) +#define _IQ29asin(A) asin(A) +#define _IQ28asin(A) asin(A) +#define _IQ27asin(A) asin(A) +#define _IQ26asin(A) asin(A) +#define _IQ25asin(A) asin(A) +#define _IQ24asin(A) asin(A) +#define _IQ23asin(A) asin(A) +#define _IQ22asin(A) asin(A) +#define _IQ21asin(A) asin(A) +#define _IQ20asin(A) asin(A) +#define _IQ19asin(A) asin(A) +#define _IQ18asin(A) asin(A) +#define _IQ17asin(A) asin(A) +#define _IQ16asin(A) asin(A) +#define _IQ15asin(A) asin(A) +#define _IQ14asin(A) asin(A) +#define _IQ13asin(A) asin(A) +#define _IQ12asin(A) asin(A) +#define _IQ11asin(A) asin(A) +#define _IQ10asin(A) asin(A) +#define _IQ9asin(A) asin(A) +#define _IQ8asin(A) asin(A) +#define _IQ7asin(A) asin(A) +#define _IQ6asin(A) asin(A) +#define _IQ5asin(A) asin(A) +#define _IQ4asin(A) asin(A) +#define _IQ3asin(A) asin(A) +#define _IQ2asin(A) asin(A) +#define _IQ1asin(A) asin(A) +//--------------------------------------------------------------------------- +#define _IQcos(A) cos(A) +#define _IQ30cos(A) cos(A) +#define _IQ29cos(A) cos(A) +#define _IQ28cos(A) cos(A) +#define _IQ27cos(A) cos(A) +#define _IQ26cos(A) cos(A) +#define _IQ25cos(A) cos(A) +#define _IQ24cos(A) cos(A) +#define _IQ23cos(A) cos(A) +#define _IQ22cos(A) cos(A) +#define _IQ21cos(A) cos(A) +#define _IQ20cos(A) cos(A) +#define _IQ19cos(A) cos(A) +#define _IQ18cos(A) cos(A) +#define _IQ17cos(A) cos(A) +#define _IQ16cos(A) cos(A) +#define _IQ15cos(A) cos(A) +#define _IQ14cos(A) cos(A) +#define _IQ13cos(A) cos(A) +#define _IQ12cos(A) cos(A) +#define _IQ11cos(A) cos(A) +#define _IQ10cos(A) cos(A) +#define _IQ9cos(A) cos(A) +#define _IQ8cos(A) cos(A) +#define _IQ7cos(A) cos(A) +#define _IQ6cos(A) cos(A) +#define _IQ5cos(A) cos(A) +#define _IQ4cos(A) cos(A) +#define _IQ3cos(A) cos(A) +#define _IQ2cos(A) cos(A) +#define _IQ1cos(A) cos(A) +//--------------------------------------------------------------------------- +#define _IQcosPU(A) cos((A)*6.283185307) +#define _IQ30cosPU(A) cos((A)*6.283185307) +#define _IQ29cosPU(A) cos((A)*6.283185307) +#define _IQ28cosPU(A) cos((A)*6.283185307) +#define _IQ27cosPU(A) cos((A)*6.283185307) +#define _IQ26cosPU(A) cos((A)*6.283185307) +#define _IQ25cosPU(A) cos((A)*6.283185307) +#define _IQ24cosPU(A) cos((A)*6.283185307) +#define _IQ23cosPU(A) cos((A)*6.283185307) +#define _IQ22cosPU(A) cos((A)*6.283185307) +#define _IQ21cosPU(A) cos((A)*6.283185307) +#define _IQ20cosPU(A) cos((A)*6.283185307) +#define _IQ19cosPU(A) cos((A)*6.283185307) +#define _IQ18cosPU(A) cos((A)*6.283185307) +#define _IQ17cosPU(A) cos((A)*6.283185307) +#define _IQ16cosPU(A) cos((A)*6.283185307) +#define _IQ15cosPU(A) cos((A)*6.283185307) +#define _IQ14cosPU(A) cos((A)*6.283185307) +#define _IQ13cosPU(A) cos((A)*6.283185307) +#define _IQ12cosPU(A) cos((A)*6.283185307) +#define _IQ11cosPU(A) cos((A)*6.283185307) +#define _IQ10cosPU(A) cos((A)*6.283185307) +#define _IQ9cosPU(A) cos((A)*6.283185307) +#define _IQ8cosPU(A) cos((A)*6.283185307) +#define _IQ7cosPU(A) cos((A)*6.283185307) +#define _IQ6cosPU(A) cos((A)*6.283185307) +#define _IQ5cosPU(A) cos((A)*6.283185307) +#define _IQ4cosPU(A) cos((A)*6.283185307) +#define _IQ3cosPU(A) cos((A)*6.283185307) +#define _IQ2cosPU(A) cos((A)*6.283185307) +#define _IQ1cosPU(A) cos((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQacos(A) acos(A) +#define _IQ29acos(A) acos(A) +#define _IQ28acos(A) acos(A) +#define _IQ27acos(A) acos(A) +#define _IQ26acos(A) acos(A) +#define _IQ25acos(A) acos(A) +#define _IQ24acos(A) acos(A) +#define _IQ23acos(A) acos(A) +#define _IQ22acos(A) acos(A) +#define _IQ21acos(A) acos(A) +#define _IQ20acos(A) acos(A) +#define _IQ19acos(A) acos(A) +#define _IQ18acos(A) acos(A) +#define _IQ17acos(A) acos(A) +#define _IQ16acos(A) acos(A) +#define _IQ15acos(A) acos(A) +#define _IQ14acos(A) acos(A) +#define _IQ13acos(A) acos(A) +#define _IQ12acos(A) acos(A) +#define _IQ11acos(A) acos(A) +#define _IQ10acos(A) acos(A) +#define _IQ9acos(A) acos(A) +#define _IQ8acos(A) acos(A) +#define _IQ7acos(A) acos(A) +#define _IQ6acos(A) acos(A) +#define _IQ5acos(A) acos(A) +#define _IQ4acos(A) acos(A) +#define _IQ3acos(A) acos(A) +#define _IQ2acos(A) acos(A) +#define _IQ1acos(A) acos(A) +//--------------------------------------------------------------------------- +#define _IQatan(A) atan(A) +#define _IQ30atan(A) atan(A) +#define _IQ29atan(A) atan(A) +#define _IQ28atan(A) atan(A) +#define _IQ27atan(A) atan(A) +#define _IQ26atan(A) atan(A) +#define _IQ25atan(A) atan(A) +#define _IQ24atan(A) atan(A) +#define _IQ23atan(A) atan(A) +#define _IQ22atan(A) atan(A) +#define _IQ21atan(A) atan(A) +#define _IQ20atan(A) atan(A) +#define _IQ19atan(A) atan(A) +#define _IQ18atan(A) atan(A) +#define _IQ17atan(A) atan(A) +#define _IQ16atan(A) atan(A) +#define _IQ15atan(A) atan(A) +#define _IQ14atan(A) atan(A) +#define _IQ13atan(A) atan(A) +#define _IQ12atan(A) atan(A) +#define _IQ11atan(A) atan(A) +#define _IQ10atan(A) atan(A) +#define _IQ9atan(A) atan(A) +#define _IQ8atan(A) atan(A) +#define _IQ7atan(A) atan(A) +#define _IQ6atan(A) atan(A) +#define _IQ5atan(A) atan(A) +#define _IQ4atan(A) atan(A) +#define _IQ3atan(A) atan(A) +#define _IQ2atan(A) atan(A) +#define _IQ1atan(A) atan(A) +//--------------------------------------------------------------------------- +#define _IQatan2(A,B) atan2(A,B) +#define _IQ30atan2(A,B) atan2(A,B) +#define _IQ29atan2(A,B) atan2(A,B) +#define _IQ28atan2(A,B) atan2(A,B) +#define _IQ27atan2(A,B) atan2(A,B) +#define _IQ26atan2(A,B) atan2(A,B) +#define _IQ25atan2(A,B) atan2(A,B) +#define _IQ24atan2(A,B) atan2(A,B) +#define _IQ23atan2(A,B) atan2(A,B) +#define _IQ22atan2(A,B) atan2(A,B) +#define _IQ21atan2(A,B) atan2(A,B) +#define _IQ20atan2(A,B) atan2(A,B) +#define _IQ19atan2(A,B) atan2(A,B) +#define _IQ18atan2(A,B) atan2(A,B) +#define _IQ17atan2(A,B) atan2(A,B) +#define _IQ16atan2(A,B) atan2(A,B) +#define _IQ15atan2(A,B) atan2(A,B) +#define _IQ14atan2(A,B) atan2(A,B) +#define _IQ13atan2(A,B) atan2(A,B) +#define _IQ12atan2(A,B) atan2(A,B) +#define _IQ11atan2(A,B) atan2(A,B) +#define _IQ10atan2(A,B) atan2(A,B) +#define _IQ9atan2(A,B) atan2(A,B) +#define _IQ8atan2(A,B) atan2(A,B) +#define _IQ7atan2(A,B) atan2(A,B) +#define _IQ6atan2(A,B) atan2(A,B) +#define _IQ5atan2(A,B) atan2(A,B) +#define _IQ4atan2(A,B) atan2(A,B) +#define _IQ3atan2(A,B) atan2(A,B) +#define _IQ2atan2(A,B) atan2(A,B) +#define _IQ1atan2(A,B) atan2(A,B) +//--------------------------------------------------------------------------- +#define _IQatan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ30atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ29atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ28atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ27atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ26atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ25atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ24atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ23atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ22atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ21atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ20atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ19atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ18atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ17atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ16atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ15atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ14atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ13atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ12atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ11atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ10atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ9atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ8atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ7atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ6atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ5atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ4atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ3atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ2atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ1atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +//--------------------------------------------------------------------------- +#define _IQsqrt(A) sqrt(A) +#define _IQ30sqrt(A) sqrt(A) +#define _IQ29sqrt(A) sqrt(A) +#define _IQ28sqrt(A) sqrt(A) +#define _IQ27sqrt(A) sqrt(A) +#define _IQ26sqrt(A) sqrt(A) +#define _IQ25sqrt(A) sqrt(A) +#define _IQ24sqrt(A) sqrt(A) +#define _IQ23sqrt(A) sqrt(A) +#define _IQ22sqrt(A) sqrt(A) +#define _IQ21sqrt(A) sqrt(A) +#define _IQ20sqrt(A) sqrt(A) +#define _IQ19sqrt(A) sqrt(A) +#define _IQ18sqrt(A) sqrt(A) +#define _IQ17sqrt(A) sqrt(A) +#define _IQ16sqrt(A) sqrt(A) +#define _IQ15sqrt(A) sqrt(A) +#define _IQ14sqrt(A) sqrt(A) +#define _IQ13sqrt(A) sqrt(A) +#define _IQ12sqrt(A) sqrt(A) +#define _IQ11sqrt(A) sqrt(A) +#define _IQ10sqrt(A) sqrt(A) +#define _IQ9sqrt(A) sqrt(A) +#define _IQ8sqrt(A) sqrt(A) +#define _IQ7sqrt(A) sqrt(A) +#define _IQ6sqrt(A) sqrt(A) +#define _IQ5sqrt(A) sqrt(A) +#define _IQ4sqrt(A) sqrt(A) +#define _IQ3sqrt(A) sqrt(A) +#define _IQ2sqrt(A) sqrt(A) +#define _IQ1sqrt(A) sqrt(A) +//--------------------------------------------------------------------------- +#define _IQisqrt(A) (1.0/sqrt(A)) +#define _IQ30isqrt(A) (1.0/sqrt(A)) +#define _IQ29isqrt(A) (1.0/sqrt(A)) +#define _IQ28isqrt(A) (1.0/sqrt(A)) +#define _IQ27isqrt(A) (1.0/sqrt(A)) +#define _IQ26isqrt(A) (1.0/sqrt(A)) +#define _IQ25isqrt(A) (1.0/sqrt(A)) +#define _IQ24isqrt(A) (1.0/sqrt(A)) +#define _IQ23isqrt(A) (1.0/sqrt(A)) +#define _IQ22isqrt(A) (1.0/sqrt(A)) +#define _IQ21isqrt(A) (1.0/sqrt(A)) +#define _IQ20isqrt(A) (1.0/sqrt(A)) +#define _IQ19isqrt(A) (1.0/sqrt(A)) +#define _IQ18isqrt(A) (1.0/sqrt(A)) +#define _IQ17isqrt(A) (1.0/sqrt(A)) +#define _IQ16isqrt(A) (1.0/sqrt(A)) +#define _IQ15isqrt(A) (1.0/sqrt(A)) +#define _IQ14isqrt(A) (1.0/sqrt(A)) +#define _IQ13isqrt(A) (1.0/sqrt(A)) +#define _IQ12isqrt(A) (1.0/sqrt(A)) +#define _IQ11isqrt(A) (1.0/sqrt(A)) +#define _IQ10isqrt(A) (1.0/sqrt(A)) +#define _IQ9isqrt(A) (1.0/sqrt(A)) +#define _IQ8isqrt(A) (1.0/sqrt(A)) +#define _IQ7isqrt(A) (1.0/sqrt(A)) +#define _IQ6isqrt(A) (1.0/sqrt(A)) +#define _IQ5isqrt(A) (1.0/sqrt(A)) +#define _IQ4isqrt(A) (1.0/sqrt(A)) +#define _IQ3isqrt(A) (1.0/sqrt(A)) +#define _IQ2isqrt(A) (1.0/sqrt(A)) +#define _IQ1isqrt(A) (1.0/sqrt(A)) +//--------------------------------------------------------------------------- +#define _IQexp(A) exp(A) +#define _IQ30exp(A) exp(A) +#define _IQ29exp(A) exp(A) +#define _IQ28exp(A) exp(A) +#define _IQ27exp(A) exp(A) +#define _IQ26exp(A) exp(A) +#define _IQ25exp(A) exp(A) +#define _IQ24exp(A) exp(A) +#define _IQ23exp(A) exp(A) +#define _IQ22exp(A) exp(A) +#define _IQ21exp(A) exp(A) +#define _IQ20exp(A) exp(A) +#define _IQ19exp(A) exp(A) +#define _IQ18exp(A) exp(A) +#define _IQ17exp(A) exp(A) +#define _IQ16exp(A) exp(A) +#define _IQ15exp(A) exp(A) +#define _IQ14exp(A) exp(A) +#define _IQ13exp(A) exp(A) +#define _IQ12exp(A) exp(A) +#define _IQ11exp(A) exp(A) +#define _IQ10exp(A) exp(A) +#define _IQ9exp(A) exp(A) +#define _IQ8exp(A) exp(A) +#define _IQ7exp(A) exp(A) +#define _IQ6exp(A) exp(A) +#define _IQ5exp(A) exp(A) +#define _IQ4exp(A) exp(A) +#define _IQ3exp(A) exp(A) +#define _IQ2exp(A) exp(A) +#define _IQ1exp(A) exp(A) +//--------------------------------------------------------------------------- +#define _IQint(A) ((long) (A)) +#define _IQ30int(A) ((long) (A)) +#define _IQ29int(A) ((long) (A)) +#define _IQ28int(A) ((long) (A)) +#define _IQ27int(A) ((long) (A)) +#define _IQ26int(A) ((long) (A)) +#define _IQ25int(A) ((long) (A)) +#define _IQ24int(A) ((long) (A)) +#define _IQ23int(A) ((long) (A)) +#define _IQ22int(A) ((long) (A)) +#define _IQ21int(A) ((long) (A)) +#define _IQ20int(A) ((long) (A)) +#define _IQ19int(A) ((long) (A)) +#define _IQ18int(A) ((long) (A)) +#define _IQ17int(A) ((long) (A)) +#define _IQ16int(A) ((long) (A)) +#define _IQ15int(A) ((long) (A)) +#define _IQ14int(A) ((long) (A)) +#define _IQ13int(A) ((long) (A)) +#define _IQ12int(A) ((long) (A)) +#define _IQ11int(A) ((long) (A)) +#define _IQ10int(A) ((long) (A)) +#define _IQ9int(A) ((long) (A)) +#define _IQ8int(A) ((long) (A)) +#define _IQ7int(A) ((long) (A)) +#define _IQ6int(A) ((long) (A)) +#define _IQ5int(A) ((long) (A)) +#define _IQ4int(A) ((long) (A)) +#define _IQ3int(A) ((long) (A)) +#define _IQ2int(A) ((long) (A)) +#define _IQ1int(A) ((long) (A)) +//--------------------------------------------------------------------------- +#define _IQfrac(A) ((A) - (float)((long) (A))) +#define _IQ30frac(A) ((A) - (float)((long) (A))) +#define _IQ29frac(A) ((A) - (float)((long) (A))) +#define _IQ28frac(A) ((A) - (float)((long) (A))) +#define _IQ27frac(A) ((A) - (float)((long) (A))) +#define _IQ26frac(A) ((A) - (float)((long) (A))) +#define _IQ25frac(A) ((A) - (float)((long) (A))) +#define _IQ24frac(A) ((A) - (float)((long) (A))) +#define _IQ23frac(A) ((A) - (float)((long) (A))) +#define _IQ22frac(A) ((A) - (float)((long) (A))) +#define _IQ21frac(A) ((A) - (float)((long) (A))) +#define _IQ20frac(A) ((A) - (float)((long) (A))) +#define _IQ19frac(A) ((A) - (float)((long) (A))) +#define _IQ18frac(A) ((A) - (float)((long) (A))) +#define _IQ17frac(A) ((A) - (float)((long) (A))) +#define _IQ16frac(A) ((A) - (float)((long) (A))) +#define _IQ15frac(A) ((A) - (float)((long) (A))) +#define _IQ14frac(A) ((A) - (float)((long) (A))) +#define _IQ13frac(A) ((A) - (float)((long) (A))) +#define _IQ12frac(A) ((A) - (float)((long) (A))) +#define _IQ11frac(A) ((A) - (float)((long) (A))) +#define _IQ10frac(A) ((A) - (float)((long) (A))) +#define _IQ9frac(A) ((A) - (float)((long) (A))) +#define _IQ8frac(A) ((A) - (float)((long) (A))) +#define _IQ7frac(A) ((A) - (float)((long) (A))) +#define _IQ6frac(A) ((A) - (float)((long) (A))) +#define _IQ5frac(A) ((A) - (float)((long) (A))) +#define _IQ4frac(A) ((A) - (float)((long) (A))) +#define _IQ3frac(A) ((A) - (float)((long) (A))) +#define _IQ2frac(A) ((A) - (float)((long) (A))) +#define _IQ1frac(A) ((A) - (float)((long) (A))) +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ30mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ29mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ28mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ27mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ26mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ25mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ24mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ23mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ22mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ21mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ20mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ19mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ18mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ17mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ16mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ15mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ14mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ13mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ12mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ11mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ10mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ9mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ8mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ7mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ6mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ5mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ4mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ3mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ2mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ1mpyIQX(A, IQA, B, IQB) ((A)*(B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A) * (float) (B)) +#define _IQ30mpyI32(A,B) ((A) * (float) (B)) +#define _IQ29mpyI32(A,B) ((A) * (float) (B)) +#define _IQ28mpyI32(A,B) ((A) * (float) (B)) +#define _IQ27mpyI32(A,B) ((A) * (float) (B)) +#define _IQ26mpyI32(A,B) ((A) * (float) (B)) +#define _IQ25mpyI32(A,B) ((A) * (float) (B)) +#define _IQ24mpyI32(A,B) ((A) * (float) (B)) +#define _IQ23mpyI32(A,B) ((A) * (float) (B)) +#define _IQ22mpyI32(A,B) ((A) * (float) (B)) +#define _IQ21mpyI32(A,B) ((A) * (float) (B)) +#define _IQ20mpyI32(A,B) ((A) * (float) (B)) +#define _IQ19mpyI32(A,B) ((A) * (float) (B)) +#define _IQ18mpyI32(A,B) ((A) * (float) (B)) +#define _IQ17mpyI32(A,B) ((A) * (float) (B)) +#define _IQ16mpyI32(A,B) ((A) * (float) (B)) +#define _IQ15mpyI32(A,B) ((A) * (float) (B)) +#define _IQ14mpyI32(A,B) ((A) * (float) (B)) +#define _IQ13mpyI32(A,B) ((A) * (float) (B)) +#define _IQ12mpyI32(A,B) ((A) * (float) (B)) +#define _IQ11mpyI32(A,B) ((A) * (float) (B)) +#define _IQ10mpyI32(A,B) ((A) * (float) (B)) +#define _IQ9mpyI32(A,B) ((A) * (float) (B)) +#define _IQ8mpyI32(A,B) ((A) * (float) (B)) +#define _IQ7mpyI32(A,B) ((A) * (float) (B)) +#define _IQ6mpyI32(A,B) ((A) * (float) (B)) +#define _IQ5mpyI32(A,B) ((A) * (float) (B)) +#define _IQ4mpyI32(A,B) ((A) * (float) (B)) +#define _IQ3mpyI32(A,B) ((A) * (float) (B)) +#define _IQ2mpyI32(A,B) ((A) * (float) (B)) +#define _IQ1mpyI32(A,B) ((A) * (float) (B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ30mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ29mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ28mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ27mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ26mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ25mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ24mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ23mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ22mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ21mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ20mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ19mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ18mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ17mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ16mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ15mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ14mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ13mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ12mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ11mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ10mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ9mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ8mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ7mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ6mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ5mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ4mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ3mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ2mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ1mpyI32int(A,B) ((long) ((A) * (float) (B))) +//--------------------------------------------------------------------------- +#define _IQmpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ30mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ29mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ28mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ27mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ26mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ25mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ24mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ23mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ22mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ21mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ20mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ19mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ18mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ17mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ16mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ15mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ14mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ13mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ12mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ11mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ10mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ9mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ8mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ7mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ6mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ5mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ4mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ3mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ2mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ1mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +//--------------------------------------------------------------------------- +#define _IQmag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ30mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ29mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ28mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ27mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ26mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ25mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ24mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ23mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ22mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ21mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ20mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ19mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ18mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ17mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ16mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ15mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ14mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ13mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ12mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ11mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ10mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ9mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ8mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ7mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ6mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ5mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ4mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ3mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ2mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ1mag(A,B) sqrt((A)*(A) + (B)*(B)) +//--------------------------------------------------------------------------- +#define _atoIQ(A) atof(A) +#define _atoIQ30(A) atof(A) +#define _atoIQ29(A) atof(A) +#define _atoIQ28(A) atof(A) +#define _atoIQ27(A) atof(A) +#define _atoIQ26(A) atof(A) +#define _atoIQ25(A) atof(A) +#define _atoIQ24(A) atof(A) +#define _atoIQ23(A) atof(A) +#define _atoIQ22(A) atof(A) +#define _atoIQ21(A) atof(A) +#define _atoIQ20(A) atof(A) +#define _atoIQ19(A) atof(A) +#define _atoIQ18(A) atof(A) +#define _atoIQ17(A) atof(A) +#define _atoIQ16(A) atof(A) +#define _atoIQ15(A) atof(A) +#define _atoIQ14(A) atof(A) +#define _atoIQ13(A) atof(A) +#define _atoIQ12(A) atof(A) +#define _atoIQ11(A) atof(A) +#define _atoIQ10(A) atof(A) +#define _atoIQ9(A) atof(A) +#define _atoIQ8(A) atof(A) +#define _atoIQ7(A) atof(A) +#define _atoIQ6(A) atof(A) +#define _atoIQ5(A) atof(A) +#define _atoIQ4(A) atof(A) +#define _atoIQ3(A) atof(A) +#define _atoIQ2(A) atof(A) +#define _atoIQ1(A) atof(A) +//--------------------------------------------------------------------------- +#define _IQtoa(A, B, C) sprintf(A, B, C) +#define _IQ30toa(A, B, C) sprintf(A, B, C) +#define _IQ29toa(A, B, C) sprintf(A, B, C) +#define _IQ28toa(A, B, C) sprintf(A, B, C) +#define _IQ27toa(A, B, C) sprintf(A, B, C) +#define _IQ26toa(A, B, C) sprintf(A, B, C) +#define _IQ25toa(A, B, C) sprintf(A, B, C) +#define _IQ24toa(A, B, C) sprintf(A, B, C) +#define _IQ23toa(A, B, C) sprintf(A, B, C) +#define _IQ22toa(A, B, C) sprintf(A, B, C) +#define _IQ21toa(A, B, C) sprintf(A, B, C) +#define _IQ20toa(A, B, C) sprintf(A, B, C) +#define _IQ19toa(A, B, C) sprintf(A, B, C) +#define _IQ18toa(A, B, C) sprintf(A, B, C) +#define _IQ17toa(A, B, C) sprintf(A, B, C) +#define _IQ16toa(A, B, C) sprintf(A, B, C) +#define _IQ15toa(A, B, C) sprintf(A, B, C) +#define _IQ14toa(A, B, C) sprintf(A, B, C) +#define _IQ13toa(A, B, C) sprintf(A, B, C) +#define _IQ12toa(A, B, C) sprintf(A, B, C) +#define _IQ11toa(A, B, C) sprintf(A, B, C) +#define _IQ10toa(A, B, C) sprintf(A, B, C) +#define _IQ9toa(A, B, C) sprintf(A, B, C) +#define _IQ8toa(A, B, C) sprintf(A, B, C) +#define _IQ7toa(A, B, C) sprintf(A, B, C) +#define _IQ6toa(A, B, C) sprintf(A, B, C) +#define _IQ5toa(A, B, C) sprintf(A, B, C) +#define _IQ4toa(A, B, C) sprintf(A, B, C) +#define _IQ3toa(A, B, C) sprintf(A, B, C) +#define _IQ2toa(A, B, C) sprintf(A, B, C) +#define _IQ1toa(A, B, C) sprintf(A, B, C) +//--------------------------------------------------------------------------- +#define _IQabs(A) fabs(A) +#define _IQ30abs(A) fabs(A) +#define _IQ29abs(A) fabs(A) +#define _IQ28abs(A) fabs(A) +#define _IQ27abs(A) fabs(A) +#define _IQ26abs(A) fabs(A) +#define _IQ25abs(A) fabs(A) +#define _IQ24abs(A) fabs(A) +#define _IQ23abs(A) fabs(A) +#define _IQ22abs(A) fabs(A) +#define _IQ21abs(A) fabs(A) +#define _IQ20abs(A) fabs(A) +#define _IQ19abs(A) fabs(A) +#define _IQ18abs(A) fabs(A) +#define _IQ17abs(A) fabs(A) +#define _IQ16abs(A) fabs(A) +#define _IQ15abs(A) fabs(A) +#define _IQ14abs(A) fabs(A) +#define _IQ13abs(A) fabs(A) +#define _IQ12abs(A) fabs(A) +#define _IQ11abs(A) fabs(A) +#define _IQ10abs(A) fabs(A) +#define _IQ9abs(A) fabs(A) +#define _IQ8abs(A) fabs(A) +#define _IQ7abs(A) fabs(A) +#define _IQ6abs(A) fabs(A) +#define _IQ5abs(A) fabs(A) +#define _IQ4abs(A) fabs(A) +#define _IQ3abs(A) fabs(A) +#define _IQ2abs(A) fabs(A) +#define _IQ1abs(A) fabs(A) +//########################################################################### +#endif // No more. +//########################################################################### + +#endif /* __IQMATHLIB_H_INCLUDED__ */ diff --git a/v120/DSP2833x_common/include/SFO.h b/v120/DSP2833x_common/include/SFO.h new file mode 100644 index 0000000..f698526 --- /dev/null +++ b/v120/DSP2833x_common/include/SFO.h @@ -0,0 +1,52 @@ +//########################################################################### +// +// FILE: SFO.H +// +// TITLE: Scale Factor Optimizer Library Interface Header +// +// +//########################################################################### +// +// Ver | dd mmm yyyy | Who | Description of changes +// =====|=============|======|=============================================== +// 0.01| 09 Jan 2004 | TI | New module +//########################################################################### + + +//============================================================================ +// Description: This header provides the function call interface +// for the scale factor optimizer for the 'F2833x. +//============================================================================ + + +//============================================================================ +// Multiple include Guard +//============================================================================ +#ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___ +#define __4090522384024n8273240x3438jx43087401r34ru32r0___ + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +extern "C" { +#endif + + +//============================================================================ +// Function prototypes for MEP SFO +//============================================================================ +void SFO_MepEn(int nEpwmModule); +void SFO_MepDis(int nEpwmModule); + +//============================================================================ +// Multiple include Guard +//============================================================================ +#endif // End: Multiple include Guard + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +} +#endif /* extern "C" */ diff --git a/v120/DSP2833x_common/include/SFO_V5.h b/v120/DSP2833x_common/include/SFO_V5.h new file mode 100644 index 0000000..2374f03 --- /dev/null +++ b/v120/DSP2833x_common/include/SFO_V5.h @@ -0,0 +1,70 @@ + +//########################################################################### +// +// FILE: SFO_V5.H +// +// TITLE: Scale Factor Optimizer Library V5 Interface Header +// +// +//########################################################################### +// +// Ver | dd mmm yyyy | Who | Description of changes +// =====|=============|======|=============================================== +// 0.01| 09 Jan 2004 | TI | New module +// 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels +//########################################################################### + + +//============================================================================ +// Description: This header provides the function call interface +// for the scale factor optimizer V5. For more +// information on the SFO function usage and +// limitations, see the HRPWM Reference Guide +// (spru924) on the TI website. +//============================================================================ + + +//============================================================================ +// Multiple include Guard +//============================================================================ +#ifndef _SFO_V5_H +#define _SFO_V5_H + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +extern "C" { +#endif + +//============================================================================ +// USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1 +//============================================================================ +#define PWM_CH 7 // Equal # of HRPWM channels PLUS 1 + // i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc. + +//============================================================================ +// Function prototypes for MEP SFO +//============================================================================ + +int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function +int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function + +//============================================================================ +// Useful Defines when Using SFO Functions +//============================================================================ +#define SFO_INCOMPLETE 0 +#define SFO_COMPLETE 1 +#define SFO_OUTRANGE_ERROR 2 + +//============================================================================ +// Multiple include Guard +//============================================================================ +#endif // End: Multiple include Guard + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +} +#endif /* extern "C" */ diff --git a/v120/DSP2833x_common/lib/IQmath.lib b/v120/DSP2833x_common/lib/IQmath.lib new file mode 100644 index 0000000..340caf0 Binary files /dev/null and b/v120/DSP2833x_common/lib/IQmath.lib differ diff --git a/v120/DSP2833x_common/lib/IQmath_fpu32.lib b/v120/DSP2833x_common/lib/IQmath_fpu32.lib new file mode 100644 index 0000000..426802a Binary files /dev/null and b/v120/DSP2833x_common/lib/IQmath_fpu32.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build.lib b/v120/DSP2833x_common/lib/SFO_TI_Build.lib new file mode 100644 index 0000000..1956f36 Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib new file mode 100644 index 0000000..66ba460 Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib new file mode 100644 index 0000000..0a8447e Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib new file mode 100644 index 0000000..16f41df Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib new file mode 100644 index 0000000..e35f7f8 Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib differ diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib new file mode 100644 index 0000000..df9e65e Binary files /dev/null and b/v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib differ diff --git a/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..7108ffa --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm @@ -0,0 +1,42 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;; $Release Date: August 1, 2008 $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/v120/DSP2833x_common/source/DSP2833x_Adc.c b/v120/DSP2833x_common/source/DSP2833x_Adc.c new file mode 100644 index 0000000..730415b --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Adc.c @@ -0,0 +1,65 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#define ADC_usDELAY 5000L + +//--------------------------------------------------------------------------- +// InitAdc: +//--------------------------------------------------------------------------- +// This function initializes ADC to a known state. +// +void InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + + + + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. + // Before the first conversion is performed a 5ms delay must be observed + // after power up to give all analog circuits time to power up and settle + + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01; + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +//pause_us(50L); +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm b/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm new file mode 100644 index 0000000..27eb60a --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm @@ -0,0 +1,67 @@ +;// TI File $Revision: /main/3 $ +;// Checkin $Date: June 26, 2007 16:41:07 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CSMPasswords.asm +;// +;// TITLE: DSP2833x Code Security Module Passwords. +;// +;// DESCRIPTION: +;// +;// This file is used to specify password values to +;// program into the CSM password locations in Flash +;// at 0x33FFF8 - 0x33FFFF. +;// +;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are +;// all programmed to 0x0000 +;// +;//########################################################################### +;// +;// Original source based on D.A. +;// +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + +; The "csmpasswords" section contains the actual CSM passwords that will be +; linked and programmed into to the CSM password locations (PWL) in flash. +; These passwords must be known in order to unlock the CSM module. +; All 0xFFFF's (erased) is the default value for the password locations (PWL). + +; It is recommended that all passwords be left as 0xFFFF during code +; development. Passwords of 0xFFFF do not activate code security and dummy +; reads of the CSM PWL registers is all that is required to unlock the CSM. +; When code development is complete, modify the passwords to activate the +; code security module. + + .sect "csmpasswds" + + .int 0xFFFF ;PWL0 (LSW of 128-bit password) + .int 0xFFFF ;PWL1 + .int 0xFFFF ;PWL2 + .int 0xFFFF ;PWL3 + .int 0xFFFF ;PWL4 + .int 0xFFFF ;PWL5 + .int 0xFFFF ;PWL6 + .int 0xFFFF ;PWL7 (MSW of 128-bit password) + +;---------------------------------------------------------------------- + +; For code security operation, all addresses between 0x33FF80 and +; 0X33fff5 cannot be used as program code or data. These locations +; must be programmed to 0x0000 when the code security password locations +; (PWL) are programmed. If security is not a concern, then these addresses +; can be used for code or data. + +; The section "csm_rsvd" can be used to program these locations to 0x0000. + + .sect "csm_rsvd" + .loop (33FFF5h - 33FF80h + 1) + .int 0x0000 + .endloop + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm b/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm new file mode 100644 index 0000000..430efa3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm @@ -0,0 +1,86 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:45:55 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example DSP2833x projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot.asm in RTS library + .endif + +;end codestart section + + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot.asm in RTS library + + .endif + +;end wd_disable + + + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..b0dfd76 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c @@ -0,0 +1,115 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 16, 2007 08:37:30 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS. +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// InitCpuTimers: +//--------------------------------------------------------------------------- +// This function initializes all three CPU timers to a known state. +// +void InitCpuTimers(void) +{ + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + CpuTimer0.RegsAddr = &CpuTimer0Regs; + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer0.InterruptCount = 0; + + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// Initialize address pointers to respective timer registers: + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + // Initialize timer period to maximum: + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + // Make sure timers are stopped: + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; + +} + +//--------------------------------------------------------------------------- +// ConfigCpuTimer: +//--------------------------------------------------------------------------- +// This function initializes the selected timer to the period specified +// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" +// and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // Initialize timer period: + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + Timer->RegsAddr->PRD.all = temp; + + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // Initialize timer control register: + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt + + // Reset interrupt counter: + Timer->InterruptCount = 0; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm b/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm new file mode 100644 index 0000000..7c226ce --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm @@ -0,0 +1,28 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:03 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Useage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + diff --git a/v120/DSP2833x_common/source/DSP2833x_DMA.c b/v120/DSP2833x_common/source/DSP2833x_DMA.c new file mode 100644 index 0000000..83c4f3c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DMA.c @@ -0,0 +1,590 @@ +//########################################################################### +// +// FILE: DSP2833x_DMA.c +// +// TITLE: DSP2833x Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // Perform a hard reset on DMA + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm (" nop"); // one NOP required after HARDRESET + + // Allow DMA to run free on emulation suspend + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + + +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + // Set up SOURCE address: + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH1.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH1.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 1. +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH2.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH2.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH2.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH2.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE + + EDIS; +} + + + +// This function starts DMA Channel 2. +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + + + +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH3.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH3.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH3.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 3. +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + + +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE + + EDIS; +} + + +// This function starts DMA Channel 4. +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + + +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + + // Set up BURST registers: + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + EDIS; +} + +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + + // Set up TRANSFER registers: + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + + // Set up WRAP registers: + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 5. +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + + + +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 6. +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c b/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c new file mode 100644 index 0000000..df76fda --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c @@ -0,0 +1,1187 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: January 14, 2008 11:17:46 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.c +// +// TITLE: DSP2833x Device Default Interrupt Service Routines. +// +// This file contains shell ISR routines for the 2833x PIE vector table. +// Typically these shell ISR routines can be used to populate the entire PIE +// vector table during device debug. In this manner if an interrupt is taken +// during firmware development, there will always be an ISR to catch it. +// +// As develpment progresses, these ISR rotuines can be eliminated and replaced +// with the user's own ISR routines for each interrupt. Since these shell ISRs +// include infinite loops they will typically not be included as-is in the final +// production firmware. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Note CPU-Timer2 is reserved for TI use. +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm(" ESTOP0"); + for(;;); + +} + + +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + + +} + +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// INT1.1 +interrupt void SEQ1INT_ISR(void) //SEQ1 ADC +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + + asm (" ESTOP0"); + for(;;); + +} + +// INT1.2 +interrupt void SEQ2INT_ISR(void) //SEQ2 ADC +{ + + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + + asm(" ESTOP0"); + for(;;); + +} +// INT1.3 - Reserved + +// INT1.4 +interrupt void XINT1_ISR(void) +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT1.5 +interrupt void XINT2_ISR(void) +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT1.6 +interrupt void ADCINT_ISR(void) // ADC +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT1.7 +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT1.8 +interrupt void WAKEINT_ISR(void) // WD, LOW Power +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// INT2.1 +interrupt void EPWM1_TZINT_ISR(void) // EPWM-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.2 +interrupt void EPWM2_TZINT_ISR(void) // EPWM-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.3 +interrupt void EPWM3_TZINT_ISR(void) // EPWM-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT2.4 +interrupt void EPWM4_TZINT_ISR(void) // EPWM-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT2.5 +interrupt void EPWM5_TZINT_ISR(void) // EPWM-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.6 +interrupt void EPWM6_TZINT_ISR(void) // EPWM-6 +{ + // Insert ISR Code here + + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.7 - Reserved +// INT2.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + +// INT 3.1 +interrupt void EPWM1_INT_ISR(void) // EPWM-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.2 +interrupt void EPWM2_INT_ISR(void) // EPWM-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.3 +interrupt void EPWM3_INT_ISR(void) // EPWM-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.4 +interrupt void EPWM4_INT_ISR(void) // EPWM-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.5 +interrupt void EPWM5_INT_ISR(void) // EPWM-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.6 +interrupt void EPWM6_INT_ISR(void) // EPWM-6 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.7 - Reserved +// INT3.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + +// INT 4.1 +interrupt void ECAP1_INT_ISR(void) // ECAP-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.2 +interrupt void ECAP2_INT_ISR(void) // ECAP-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.3 +interrupt void ECAP3_INT_ISR(void) // ECAP-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.4 +interrupt void ECAP4_INT_ISR(void) // ECAP-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.5 +interrupt void ECAP5_INT_ISR(void) // ECAP-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +// INT4.6 +interrupt void ECAP6_INT_ISR(void) // ECAP-6 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +// INT4.7 - Reserved +// INT4.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// INT 5.1 +interrupt void EQEP1_INT_ISR(void) // EQEP-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT5.2 +interrupt void EQEP2_INT_ISR(void) // EQEP-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT5.3 - Reserved +// INT5.4 - Reserved +// INT5.5 - Reserved +// INT5.6 - Reserved +// INT5.7 - Reserved +// INT5.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// INT6.1 +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.2 +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.3 +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.4 +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.5 +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.6 +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.7 - Reserved +// INT6.8 - Reserved + + + + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// INT7.1 +interrupt void DINTCH1_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.2 +interrupt void DINTCH2_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.3 +interrupt void DINTCH3_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.4 +interrupt void DINTCH4_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.5 +interrupt void DINTCH5_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.6 +interrupt void DINTCH6_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.7 - Reserved +// INT7.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// INT8.1 +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT8.2 +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT8.3 - Reserved +// INT8.4 - Reserved + +// INT8.5 +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT8.6 +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT8.7 - Reserved +// INT8.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// INT9.1 +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.2 +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + + +// INT9.3 +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.4 +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.5 +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.6 +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.7 +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.8 +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU INT10 +// ----------------------------------------------------------- + +// INT10.1 - Reserved +// INT10.2 - Reserved +// INT10.3 - Reserved +// INT10.4 - Reserved +// INT10.5 - Reserved +// INT10.6 - Reserved +// INT10.7 - Reserved +// INT10.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU INT11 +// ----------------------------------------------------------- + +// INT11.1 - Reserved +// INT11.2 - Reserved +// INT11.3 - Reserved +// INT11.4 - Reserved +// INT11.5 - Reserved +// INT11.6 - Reserved +// INT11.7 - Reserved +// INT11.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU INT12 +// ----------------------------------------------------------- + +// INT12.1 +interrupt void XINT3_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.2 +interrupt void XINT4_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.3 +interrupt void XINT5_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +// INT12.4 +interrupt void XINT6_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.5 +interrupt void XINT7_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.6 - Reserved +// INT12.7 +interrupt void LVF_ISR(void) // Latched overflow +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +// INT12.8 +interrupt void LUF_ISR(void) // Latched underflow +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_common/source/DSP2833x_DisInt.asm b/v120/DSP2833x_common/source/DSP2833x_DisInt.asm new file mode 100644 index 0000000..2e8e35c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DisInt.asm @@ -0,0 +1,65 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:09 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DisInt.asm +;// +;// TITLE: Disable and Restore INTM and DBGM +;// +;// Function Prototypes: +;// +;// Uint16 DSP28x_DisableInt(); +;// and void DSP28x_RestoreInt(Uint16 Stat0); +;// +;// Usage: +;// +;// DSP28x_DisableInt() sets both the INTM and DBGM +;// bits to disable maskable interrupts. Before doing +;// this, the current value of ST1 is stored on the stack +;// so that the values can be restored later. The value +;// of ST1 before the masks are set is returned to the +;// user in AL. This is then used to restore their state +;// via the DSP28x_RestoreInt(Uint16 ST1) function. +;// +;// Example +;// +;// Uint16 StatusReg1 +;// StatusReg1 = DSP28x_DisableInt(); +;// +;// ... May also want to disable INTM here +;// +;// ... code here +;// +;// DSP28x_RestoreInt(StatusReg1); +;// +;// ... Restore INTM enable +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + + + + .def _DSP28x_DisableInt + .def _DSP28x_RestoreInt + + +_DSP28x_DisableInt: + PUSH ST1 + SETC INTM,DBGM + MOV AL, *--SP + LRETR + +_DSP28x_RestoreInt: + MOV *SP++, AL + POP ST1 + LRETR + + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/v120/DSP2833x_common/source/DSP2833x_ECan.c b/v120/DSP2833x_common/source/DSP2833x_ECan.c new file mode 100644 index 0000000..612ccb1 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ECan.c @@ -0,0 +1,404 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: June 25, 2008 15:19:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.c +// +// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + + +//--------------------------------------------------------------------------- +// InitECan: +//--------------------------------------------------------------------------- +// This function initializes the eCAN module to a known state. +// +void InitECan(void) +{ + InitECana(); +#if DSP28_ECANB + InitECanb(); +#endif // if DSP28_ECANB +} + +void InitECana(void) // Initialize eCAN-A module +{ +/* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + +struct ECAN_REGS ECanaShadow; + + EALLOW; // EALLOW enables access to protected bits + +/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + +/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + +/* Initialize all bits of 'Master Control Field' to zero */ +// Some bits of MSGCTRL register come up in an unknown state. For proper operation, +// all bits (including reserved bits) of MSGCTRL must be initialized to zero + + ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; + +// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again +// as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ + + ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ + + ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFF; + + +/* Configure bit timing parameters for eCANA*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0; + + #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps + See Note at End of File */ + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 2; + ECanaShadow.CANBTC.bit.TSEG1REG = 10; + #endif + #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps + See Note at End of File */ + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 1; + ECanaShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + + ECanaShadow.CANBTC.bit.SAM = 1; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. + +/* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} + + +#if (DSP28_ECANB) +void InitECanb(void) // Initialize eCAN-B module +{ +/* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + +struct ECAN_REGS ECanbShadow; + + EALLOW; // EALLOW enables access to protected bits + +/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + +/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + +/* Initialize all bits of 'Master Control Field' to zero */ +// Some bits of MSGCTRL register come up in an unknown state. For proper operation, +// all bits (including reserved bits) of MSGCTRL must be initialized to zero + + ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000; + +// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again +// as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ + + ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ + + ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFF; + + +/* Configure bit timing parameters for eCANB*/ + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared.. + + + ECanbShadow.CANBTC.all = 0; + + #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps + See Note at end of file */ + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 2; + ECanbShadow.CANBTC.bit.TSEG1REG = 10; + #endif + #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps + See Note at end of file */ + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 1; + ECanbShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanbShadow.CANBTC.bit.SAM = 1; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. + + +/* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} +#endif // if DSP28_ECANB + + +//--------------------------------------------------------------------------- +// Example: InitECanGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as eCAN pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for CANTXA/B operation. +// Only one GPIO pin shoudl be enabled for CANRXA/B operation. +// Comment out other unwanted lines. + + +void InitECanGpio(void) +{ + InitECanaGpio(); +#if (DSP28_ECANB) + InitECanbGpio(); +#endif // if DSP28_ECANB +} + +void InitECanaGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected CAN pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) +// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA) + + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA) +// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA) + +/* Set qualification for selected CAN pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA) + + +/* Configure eCAN-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation + + EDIS; +} + +#if (DSP28_ECANB) +void InitECanbGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected CAN pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB) + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB) + +/* Set qualification for selected CAN pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB) + +/* Configure eCAN-B pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation + + EDIS; +} +#endif // if DSP28_ECANB + +/* +Note: Bit timing parameters must be chosen based on the network parameters such +as the sampling point desired and the propagation delay of the network. +The propagation delay is a function of length of the cable, delay introduced by +the transceivers and opto/galvanic-isolators (if any). + +The parameters used in this file must be changed taking into account the above +mentioned factors in order to arrive at the bit-timing parameters suitable +for a network. + +*/ diff --git a/v120/DSP2833x_common/source/DSP2833x_ECap.c b/v120/DSP2833x_common/source/DSP2833x_ECap.c new file mode 100644 index 0000000..cd1d24d --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ECap.c @@ -0,0 +1,255 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 15, 2007 16:54:36 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.c +// +// TITLE: DSP2833x eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitECap: +//--------------------------------------------------------------------------- +// This function initializes the eCAP(s) to a known state. +// +void InitECap(void) +{ + // Initialize eCAP1/2/3 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitECapGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ECAP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. + +void InitECapGpio() +{ + + InitECap1Gpio(); +#if (DSP28_ECAP2) + InitECap2Gpio(); +#endif // endif DSP28_ECAP2 +#if (DSP28_ECAP3) + InitECap3Gpio(); +#endif // endif DSP28_ECAP3 +#if (DSP28_ECAP4) + InitECap4Gpio(); +#endif // endif DSP28_ECAP4 +#if (DSP28_ECAP5) + InitECap5Gpio(); +#endif // endif DSP28_ECAP5 +#if (DSP28_ECAP6) + InitECap6Gpio(); +#endif // endif DSP28_ECAP6 +} + +void InitECap1Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1) + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1) +// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1) + + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; // Synch to SYSCLKOUT GPIO5 (CAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Synch to SYSCLKOUT GPIO34 (CAP1) + +/* Configure eCAP-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP1 functional pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1 + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1 +// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1 + + EDIS; +} + +#if DSP28_ECAP2 +void InitECap2Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2) +// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2) +// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT GPIO7 (CAP2) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Synch to SYSCLKOUT GPIO25 (CAP2) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Synch to SYSCLKOUT GPIO37 (CAP2) + +/* Configure eCAP-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2 +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2 +// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2 + + EDIS; +} +#endif // endif DSP28_ECAP2 + +#if DSP28_ECAP3 +void InitECap3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3) + +/* Configure eCAP-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3 +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3 + + EDIS; +} +#endif // endif DSP28_ECAP3 + + +#if DSP28_ECAP4 +void InitECap4Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4) + +/* Configure eCAP-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4 + + EDIS; +} +#endif // endif DSP28_ECAP4 + + +#if DSP28_ECAP5 +void InitECap5Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5) +// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5 +// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5 + + EDIS; +} +#endif // endif DSP28_ECAP5 + + +#if DSP28_ECAP6 +void InitECap6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6) +// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6 +// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6 + + EDIS; +} +#endif // endif DSP28_ECAP6 + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_EPwm.c b/v120/DSP2833x_common/source/DSP2833x_EPwm.c new file mode 100644 index 0000000..64f0e0f --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_EPwm.c @@ -0,0 +1,316 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:19 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.c +// +// TITLE: DSP2833x ePWM Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitEPwm: +//--------------------------------------------------------------------------- +// This function initializes the ePWM(s) to a known state. +// +void InitEPwm(void) +{ + // Initialize ePWM1/2/3/4/5/6 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitEPwmGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ePWM pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); +#if DSP28_EPWM4 + InitEPwm4Gpio(); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 + InitEPwm5Gpio(); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 + InitEPwm6Gpio(); +#endif // endif DSP28_EPWM6 +} + +void InitEPwm1Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B) + +/* Configure ePWM-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM1 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + + EDIS; +} + +void InitEPwm2Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B) + +/* Configure ePWM-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + + EDIS; +} + +void InitEPwm3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B) + +/* Configure ePWM-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + + EDIS; +} + + +#if DSP28_EPWM4 +void InitEPwm4Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B) + +/* Configure ePWM-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + + EDIS; +} +#endif // endif DSP28_EPWM4 + + +#if DSP28_EPWM5 +void InitEPwm5Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B) + +/* Configure ePWM-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + + EDIS; +} +#endif // endif DSP28_EPWM5 + + +#if DSP28_EPWM6 +void InitEPwm6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B) + +/* Configure ePWM-6 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + + EDIS; +} +#endif // endif DSP28_EPWM6 + +//--------------------------------------------------------------------------- +// Example: InitEPwmSyncGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ePWM Synch pins +// + +void InitEPwmSyncGpio(void) +{ + + EALLOW; + +/* Configure EPWMSYNCI */ + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO32 (EPWMSYNCI) + +/* Set qualification for selected pins to asynch only */ +// This will select synch to SYSCLKOUT for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI) + +/* Configure EPwmSync pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be EPwmSync functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; // Enable pull-up on GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2; // Enable pull-up on GPIO32 (EPWMSYNCI) + + + +/* Configure EPWMSYNC0 */ + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNC0) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO33 (EPWMSYNC0) + +// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Enable pull-up on GPIO6 (EPWMSYNC0) + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Enable pull-up on GPIO33 (EPWMSYNC0) + +} + + + +//--------------------------------------------------------------------------- +// Example: InitTzGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as Trip Zone (TZ) pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +void InitTzGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4) + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5) +// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5) + + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6) +// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6) + + +/* Configure TZ pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be TZ functional pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4 + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5 +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5 + + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6 +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6 + + EDIS; +} + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_EQep.c b/v120/DSP2833x_common/source/DSP2833x_EQep.c new file mode 100644 index 0000000..cb6ad92 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_EQep.c @@ -0,0 +1,154 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: July 27, 2007 11:55:20 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.c +// +// TITLE: DSP2833x eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitEQep: +//--------------------------------------------------------------------------- +// This function initializes the eQEP(s) to a known state. +// +void InitEQep(void) +{ + // Initialize eQEP1/2 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitEQepGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as eQEP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. + +void InitEQepGpio() +{ +#if DSP28_EQEP1 + InitEQep1Gpio(); +#endif // endif DSP28_EQEP1 +#if DSP28_EQEP2 + InitEQep2Gpio(); +#endif // endif DSP28_EQEP2 +} + +#if DSP28_EQEP1 +void InitEQep1Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I) + + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync to SYSCLKOUT GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync to SYSCLKOUT GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync to SYSCLKOUT GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync to SYSCLKOUT GPIO53 (EQEP1I) + +/* Configure eQEP-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eQEP1 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + +// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A +// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B +// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S +// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + + + EDIS; +} +#endif // if DSP28_EQEP1 + + + +#if DSP28_EQEP2 +void InitEQep2Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S) + +/* Configure eQEP-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eQEP2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S + + + EDIS; +} +#endif // endif DSP28_EQEP2 + + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Gpio.c b/v120/DSP2833x_common/source/DSP2833x_Gpio.c new file mode 100644 index 0000000..c615f0d --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Gpio.c @@ -0,0 +1,69 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:25 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.c +// +// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitGpio: +//--------------------------------------------------------------------------- +// This function initializes the Gpio to a known (default) state. +// +// For more details on configuring GPIO's as peripheral functions, +// refer to the individual peripheral examples and/or GPIO setup example. +void InitGpio(void) +{ + EALLOW; + + // Each GPIO pin can be: + // a) a GPIO input/output + // b) peripheral function 1 + // c) peripheral function 2 + // d) peripheral function 3 + // By default, all are GPIO Inputs + GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 + GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 + GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 + GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 + GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 + GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 + + GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs + GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs + GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs + + // Each input can have different qualification + // a) input synchronized to SYSCLKOUT + // b) input qualified by a sampling window + // c) input sent asynchronously (valid for peripheral inputs only) + GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT + + // Pull-ups can be enabled or disabled. + GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 + GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 + GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 + + //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 + //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 + //GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79 + + EDIS; + +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_I2C.c b/v120/DSP2833x_common/source/DSP2833x_I2C.c new file mode 100644 index 0000000..fda73d3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_I2C.c @@ -0,0 +1,76 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:27 $ +//########################################################################### +// +// FILE: DSP2833x_I2C.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitI2C: +//--------------------------------------------------------------------------- +// This function initializes the I2C to a known state. +// +void InitI2C(void) +{ + // Initialize I2C-A: + + //tbd... +} + +//--------------------------------------------------------------------------- +// Example: InitI2CGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SDAA operation. +// Only one GPIO pin shoudl be enabled for SCLA operation. +// Comment out other unwanted lines. + +void InitI2CGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + +/* Configure SCI pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be I2C functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation + + EDIS; +} + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c b/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c new file mode 100644 index 0000000..302c330 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c @@ -0,0 +1,349 @@ + // TI File $Revision: /main/16 $ +// Checkin $Date: October 3, 2007 14:50:19 $ +//########################################################################### +// +// FILE: DSP2833x_McBSP.c +// +// TITLE: DSP2833x Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY +// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT. +// +// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h +//--------------------------------------------------------------------------- + +#if CPU_FRQ_150MHZ // For 150 MHz SYSCLKOUT(default) + #define CPU_SPD 150E6 + #define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples +#endif +#if CPU_FRQ_100MHZ // For 100 MHz SYSCLKOUT + #define CPU_SPD 100E6 + #define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples +#endif + +#define CLKGDV_VAL 1 +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) // # of CPU cycles in 2 SRG cycles-init delay +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay +//--------------------------------------------------------------------------- +// InitMcbsp: +//--------------------------------------------------------------------------- +// This function initializes the McBSP to a known state. +// + +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +void InitMcbsp(void) +{ + InitMcbspa(); + #if DSP28_MCBSPB + InitMcbspb(); + #endif // end DSP28_MCBSPB +} + +void InitMcbspa(void) +{ +// McBSP-A register settings + + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode. + + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspaRegs.RCR1.all=0x0; + + McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + + McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1) + + delay_loop(); // Wait at least 2 SRG clock cycles + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset + +} + + +#if (DSP28_MCBSPB) +void InitMcbspb(void) +{ + +// McBSP-B register settings + + McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode. + + McbspbRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspbRegs.RCR1.all=0x0; + + McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspbRegs.XCR1.all=0x0; + + McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1) + + McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + delay_loop(); // Wait at least 2 SRG clock cycles + McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset + +} + + +#endif // end DSP28_MCBSPB + +// McBSP-A Data Lengths +void InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +void InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +void InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +void InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +void InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +void InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +// McBSP-B Data Lengths +#if (DSP28_MCBSPB) + +void InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +void InitMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +void InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +void InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +void InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +void InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +#endif //end DSP28_MCBSPB + + + +void InitMcbspGpio(void) +{ + InitMcbspaGpio(); + #if DSP28_MCBSPB + InitMcbspbGpio(); + #endif // end DSP28_MCBSPB +} + +void InitMcbspaGpio(void) +{ + EALLOW; + +/* Configure McBSP-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be McBSP functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed) + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed) + +/* Set qualification for selected input pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed) + + EDIS; +} + +#if DSP28_MCBSPB +void InitMcbspbGpio(void) +{ + EALLOW; +/* Configure McBSP-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be McBSP functional pins. +// Comment out other unwanted lines. + + //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin (Comment as needed) + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (MDXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (MDXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (MDRB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (MDRB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (MCLKXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (MCLKRB) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (MCLKRB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (MFSXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (MFSXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (MFSRB) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (MFSRB) (Comment as needed) + + +/* Set qualification for selected input pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed) + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed) + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed) + + + EDIS; +} +#endif // end DSP28_MCBSPB + +void delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles +} + +void clkg_delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles +} +//=========================================================================== +// No more. +//=========================================================================== + + + + + + + + + + + diff --git a/v120/DSP2833x_common/source/DSP2833x_MemCopy.c b/v120/DSP2833x_common/source/DSP2833x_MemCopy.c new file mode 100644 index 0000000..f7cba01 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_MemCopy.c @@ -0,0 +1,45 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:33 $ +//########################################################################### +// +// FILE: DSP2833x_MemCopy.c +// +// TITLE: Memory Copy Utility +// +// ASSUMPTIONS: +// +// +// +// DESCRIPTION: +// +// This function will copy the specified memory contents from +// one location to another. +// +// Uint16 *SourceAddr Pointer to the first word to be moved +// SourceAddr < SourceEndAddr +// Uint16* SourceEndAddr Pointer to the last word to be moved +// Uint16* DestAddr Pointer to the first destination word +// +// No checks are made for invalid memory locations or that the +// end address is > then the first start address. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) +{ + while(SourceAddr < SourceEndAddr) + { + *DestAddr++ = *SourceAddr++; + } + return; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..f1eafe3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:35 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitPieCtrl: +//--------------------------------------------------------------------------- +// This function initializes the PIE control registers to a known state. +// +void InitPieCtrl(void) +{ + // Disable Interrupts at the CPU level: + DINT; + + // Disable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // Clear all PIEIER registers: + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // Clear all PIEIFR registers: + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; + + +} + +//--------------------------------------------------------------------------- +// EnableInterrupts: +//--------------------------------------------------------------------------- +// This function enables the PIE module and CPU interrupts +// +void EnableInterrupts() +{ + + // Enable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enables PIE to drive a pulse into the CPU + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // Enable Interrupts at the CPU level + EINT; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_PieVect.c b/v120/DSP2833x_common/source/DSP2833x_PieVect.c new file mode 100644 index 0000000..d163c54 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_PieVect.c @@ -0,0 +1,204 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:38 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + +// Non-Peripheral Interrupts + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + +// Group 2 PIE Vectors + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + +// Group 3 PIE Vectors + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + +// Group 4 PIE Vectors + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + +// Group 5 PIE Vectors + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + +// Group 6 PIE Vectors + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + +// Group 7 PIE Vectors + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + +// Group 8 PIE Vectors + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + +// Group 9 PIE Vectors + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + +// Group 10 PIE Vectors + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + +// Group 11 PIE Vectors + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + +// Group 12 PIE Vectors + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + *Dest++ = *Source++; + EDIS; + + // Enable the PIE Vector Table + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..bf821e1 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c @@ -0,0 +1,1863 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 14, 2008 11:28:12 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines. +// +//########################################################################### +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +#if (INT13PL != 0) +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + IER |= MINT13; // Set "global" priority + EINT; + + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT14 of CPU (use MINT14 mask): +#if (INT14PL != 0) +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + IER |= MINT14; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT15 of CPU (use MINT15 mask): +#if (INT15PL != 0) +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + IER |= MINT15; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT16 of CPU (use MINT16 mask): +#if (INT16PL != 0) +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + IER |= MINT16; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to EMUINT of CPU (non-maskable): +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// Connected to NMI of CPU (non-maskable): +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// Connected to PIEIER1_1 (use MINT1 and MG11 masks): +#if (G11PL != 0) +interrupt void SEQ1INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_2 (use MINT1 and MG12 masks): +#if (G12PL != 0) +interrupt void SEQ2INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER1_4 (use MINT1 and MG14 masks): +#if (G14PL != 0) +interrupt void XINT1_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_5 (use MINT1 and MG15 masks): +#if (G15PL != 0) +interrupt void XINT2_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// Connected to PIEIER1_6 (use MINT1 and MG16 masks): +#if (G16PL != 0) +interrupt void ADCINT_ISR(void) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_7 (use MINT1 and MG17 masks): +#if (G17PL != 0) +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_8 (use MINT1 and MG18 masks): +#if (G18PL != 0) +interrupt void WAKEINT_ISR(void) // WD/LPM +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// Connected to PIEIER2_1 (use MINT2 and MG21 masks): +#if (G21PL != 0) +interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_2 (use MINT2 and MG22 masks): +#if (G22PL != 0) +interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_3 (use MINT2 and MG23 masks): +#if (G23PL != 0) +interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_4 (use MINT2 and MG24 masks): +#if (G24PL != 0) +interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_5 (use MINT2 and MG25 masks): +#if (G25PL != 0) +interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_6 (use MINT2 and MG26 masks): +#if (G26PL != 0) +interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + + +// Connected to PIEIER3_1 (use MINT3 and MG31 masks): +#if (G31PL != 0) +interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER3_2 (use MINT3 and MG32 masks): +#if (G32PL != 0) +interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_3 (use MINT3 and MG33 masks): +#if (G33PL != 0) +interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_4 (use MINT3 and MG34 masks): +#if (G34PL != 0) +interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_5 (use MINT3 and MG35 masks): +#if (G35PL != 0) +interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_6 (use MINT3 and MG36 masks): +#if (G36PL != 0) +interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + + +// Connected to PIEIER4_1 (use MINT4 and MG41 masks): +#if (G41PL != 0) +interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_2 (use MINT4 and MG42 masks): +#if (G42PL != 0) +interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_3 (use MINT4 and MG43 masks): +#if (G43PL != 0) +interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_4 (use MINT4 and MG44 masks): +#if (G44PL != 0) +interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_5 (use MINT4 and MG45 masks): +#if (G45PL != 0) +interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_6 (use MINT4 and MG46 masks): +#if (G46PL != 0) +interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// Connected to PIEIER5_1 (use MINT5 and MG51 masks): +#if (G51PL != 0) +interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER5_2 (use MINT5 and MG52 masks): +#if (G52PL != 0) +interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// Connected to PIEIER6_1 (use MINT6 and MG61 masks): +#if (G61PL != 0) +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_2 (use MINT6 and MG62 masks): +#if (G62PL != 0) +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER6_3 (use MINT6 and MG63 masks): +#if (G63PL != 0) +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_4 (use MINT6 and MG64 masks): +#if (G64PL != 0) +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER6_5 (use MINT6 and MG65 masks): +#if (G65PL != 0) +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_6 (use MINT6 and MG66 masks): +#if (G66PL != 0) +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// Connected to PIEIER7_1 (use MINT7 and MG71 masks): +#if (G71PL != 0) +interrupt void DINTCH1_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_2 (use MINT7 and MG72 masks): +#if (G72PL != 0) +interrupt void DINTCH2_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER7_3 (use MINT7 and MG73 masks): +#if (G73PL != 0) +interrupt void DINTCH3_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_4 (use MINT7 and MG74 masks): +#if (G74PL != 0) +interrupt void DINTCH4_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER7_5 (use MINT7 and MG75 masks): +#if (G75PL != 0) +interrupt void DINTCH5_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_6 (use MINT7 and MG76 masks): +#if (G76PL != 0) +interrupt void DINTCH6_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// Connected to PIEIER8_1 (use MINT8 and MG81 masks): +#if (G81PL != 0) +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_2 (use MINT8 and MG82 masks): +#if (G82PL != 0) +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_5 (use MINT8 and MG85 masks): +#if (G85PL != 0) +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_6 (use MINT8 and MG86 masks): +#if (G82PL != 0) +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT9 and MG91 masks): +#if (G91PL != 0) +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_2 (use MINT9 and MG92 masks): +#if (G92PL != 0) +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER9_3 (use MINT9 and MG93 masks): +#if (G93PL != 0) +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_4 (use MINT9 and MG94 masks): +#if (G94PL != 0) +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_5 (use MINT9 and MG95 masks): +#if (G95PL != 0) +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_6 (use MINT9 and MG96 masks): +#if (G96PL != 0) +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_7 (use MINT9 and MG97 masks): +#if (G97PL != 0) +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_8 (use MINT9 and MG98 masks): +#if (G98PL != 0) +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU INT10 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU INT11 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU INT12 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT12 and MG121 masks): +#if (G121PL != 0) +interrupt void XINT3_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_2 (use MINT12 and MG122 masks): +#if (G122PL != 0) +interrupt void XINT4_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER12_3 (use MINT12 and MG123 masks): +#if (G123PL != 0) +interrupt void XINT5_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_4 (use MINT12 and MG124 masks): +#if (G124PL != 0) +interrupt void XINT6_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_5 (use MINT12 and MG125 masks): +#if (G125PL != 0) +interrupt void XINT7_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_7 (use MINT12 and MG127 masks): +#if (G127PL != 0) +interrupt void LVF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_8 (use MINT12 and MG128 masks): +#if (G128PL != 0) +interrupt void LUF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c new file mode 100644 index 0000000..99379ea --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c @@ -0,0 +1,511 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:31 $ +//########################################################################### +// +// FILE: DSP2833x_SWPiroritizedPieVect.c +// +// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// +// Original Source by A.T. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // Reserved space + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + +// Non-Peripheral Interrupts: + #if (INT13PL != 0) + INT13_ISR, // XINT13 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + INT14_ISR, // CPU-Timer2 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOSINT_ISR, // RTOS interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, // reserved interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors: + #if (G11PL != 0) + SEQ1INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G12PL != 0) + SEQ2INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G14PL != 0) + XINT1_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G15PL != 0) + XINT2_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G16PL != 0) + ADCINT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G17PL != 0) + TINT0_ISR, // Timer 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G18PL != 0) + WAKEINT_ISR, // WD & Low Power + #else + INT_NOTUSED_ISR, + #endif + +// Group 2 PIE Vectors: + #if (G21PL != 0) + EPWM1_TZINT_ISR, // ePWM1 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G22PL != 0) + EPWM2_TZINT_ISR, // ePWM2 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G23PL != 0) + EPWM3_TZINT_ISR, // ePWM3 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G24PL != 0) + EPWM4_TZINT_ISR, // ePWM4 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G25PL != 0) + EPWM5_TZINT_ISR, // ePWM5 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G26PL != 0) + EPWM6_TZINT_ISR, // ePWM6 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 3 PIE Vectors: + #if (G31PL != 0) + EPWM1_INT_ISR, // ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G32PL != 0) + EPWM2_INT_ISR, // ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G33PL != 0) + EPWM3_INT_ISR, // ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G34PL != 0) + EPWM4_INT_ISR, // ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G35PL != 0) + EPWM5_INT_ISR, // ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G36PL != 0) + EPWM6_INT_ISR, // ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 4 PIE Vectors: + #if (G41PL != 0) + ECAP1_INT_ISR, // eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G42PL != 0) + ECAP2_INT_ISR, // eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G43PL != 0) + ECAP3_INT_ISR, // eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G44PL != 0) + ECAP4_INT_ISR, // eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G45PL != 0) + ECAP5_INT_ISR, // eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G46PL != 0) + ECAP6_INT_ISR, // eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 5 PIE Vectors: + #if (G51PL != 0) + EQEP1_INT_ISR, // eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G52PL != 0) + EQEP2_INT_ISR, // eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 6 PIE Vectors: + #if (G61PL != 0) + SPIRXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G62PL != 0) + SPITXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G63PL != 0) + MRINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G64PL != 0) + MXINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G65PL != 0) + MRINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G66PL != 0) + MXINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 7 PIE Vectors: + #if (G71PL != 0) + DINTCH1_ISR, // DMA-Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G72PL != 0) + DINTCH2_ISR, // DMA-Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G73PL != 0) + DINTCH3_ISR, // DMA-Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G74PL != 0) + DINTCH4_ISR, // DMA-Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G75PL != 0) + DINTCH5_ISR, // DMA-Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G76PL != 0) + DINTCH6_ISR, // DMA-Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 8 PIE Vectors: + #if (G81PL != 0) + I2CINT1A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G82PL != 0) + I2CINT2A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + #if (G85PL != 0) + SCIRXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + #if (G86PL != 0) + SCITXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 9 PIE Vectors: + #if (G91PL != 0) + SCIRXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G92PL != 0) + SCITXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G93PL != 0) + SCIRXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G94PL != 0) + SCITXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G95PL != 0) + ECAN0INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G96PL != 0) + ECAN1INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G97PL != 0) + ECAN0INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G98PL != 0) + ECAN1INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + +// Group 10 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 11 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 12 PIE Vectors + #if (G121PL != 0) + XINT3_ISR, // External interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G122PL != 0) + XINT4_ISR, // External interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G123PL != 0) + XINT5_ISR, // External interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G124PL != 0) + XINT6_ISR, // External interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G125PL != 0) + XINT7_ISR, // External interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G127PL != 0) + LVF_ISR, // Latched overflow flag + #else + INT_NOTUSED_ISR, + #endif + + #if (G128PL != 0) + LUF_ISR, // Latched underflow flag + #else + INT_NOTUSED_ISR, + #endif +}; + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) { + *Dest++ = *Source++; + } + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Sci.c b/v120/DSP2833x_common/source/DSP2833x_Sci.c new file mode 100644 index 0000000..d0a9e1c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Sci.c @@ -0,0 +1,168 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 16:06:07 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitSci: +//--------------------------------------------------------------------------- +// This function initializes the SCI(s) to a known state. +// +void InitSci(void) +{ + // Initialize SCI-A: + + //tbd... + + + // Initialize SCI-B: + + //tbd... + + // Initialize SCI-C: + + //tbd... +} + +//--------------------------------------------------------------------------- +// Example: InitSciGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as SCI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SCITXDA/B operation. +// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. +// Comment out other unwanted lines. + +void InitSciGpio() +{ + InitSciaGpio(); +#if DSP28_SCIB + InitScibGpio(); +#endif // if DSP28_SCIB +#if DSP28_SCIC + InitScicGpio(); +#endif // if DSP28_SCIC +} + +void InitSciaGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. + + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) + +/* Configure SCI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation + + EDIS; +} + +#if DSP28_SCIB +void InitScibGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB) + + +// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) + +/* Configure SCI-B pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation + +// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation + + EDIS; +} +#endif // if DSP28_SCIB + +#if DSP28_SCIC +void InitScicGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. + + GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) + GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) + +/* Configure SCI-C pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. + + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation + + EDIS; +} +#endif // if DSP28_SCIC + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Spi.c b/v120/DSP2833x_common/source/DSP2833x_Spi.c new file mode 100644 index 0000000..95a7b32 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Spi.c @@ -0,0 +1,107 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:44 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.c +// +// TITLE: DSP2833x SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitSPI: +//--------------------------------------------------------------------------- +// This function initializes the SPI(s) to a known state. +// +void InitSpi(void) +{ + // Initialize SPI-A/B/C/D + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitSpiGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as SPI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLKA operation. +// Only one GPIO pin should be enabled for SPISTEA operation. +// Comment out other unwanted lines. + +void InitSpiGpio() +{ + + InitSpiaGpio(); +} + +void InitSpiaGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) + + +// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) +// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) +// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) +// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) + + +/* Configure SPI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SPI functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + +// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA +// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA +// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA +// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA + + EDIS; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..f49a3bd --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c @@ -0,0 +1,389 @@ +// TI File $Revision: /main/7 $ +// Checkin $Date: September 20, 2007 13:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. + +#pragma CODE_SECTION(InitFlash, "ramfuncs"); + +//--------------------------------------------------------------------------- +// InitSysCtrl: +//--------------------------------------------------------------------------- +// This function initializes the System Control registers to a known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals + +long SYSCLKOUT, LSPCLK, HSPCLK; + +void InitSysCtrl(void) +{ + + // Disable the watchdog + DisableDog(); + + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // Initialize the peripheral clocks + InitPeripheralClocks(); +} + + +//--------------------------------------------------------------------------- +// Example: InitFlash: +//--------------------------------------------------------------------------- +// This function initializes the Flash Control registers + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results + +void InitFlash(void) +{ + EALLOW; + //Enable Flash Pipeline mode to improve performance + //of code executed from Flash. + FlashRegs.FOPT.bit.ENPIPE = 1; + + // CAUTION + //Minimum waitstates required for the flash operating + //at a given CPU rate must be characterized by TI. + //Refer to the datasheet for the latest information. +#if CPU_FRQ_150MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // CAUTION + //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + asm(" RPT #7 || NOP"); +} + + +//--------------------------------------------------------------------------- +// Example: ServiceDog: +//--------------------------------------------------------------------------- +// This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application + +void ServiceDog(void) +{ + if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR) + if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL) + { + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; + return; +} } + +//--------------------------------------------------------------------------- +// Example: DisableDog: +//--------------------------------------------------------------------------- +// This function disables the watchdog timer. + +void DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: InitPll: +//--------------------------------------------------------------------------- +// This function initializes the PLLCR register. + +void InitPll(Uint16 val, Uint16 divsel) +{ + long Val; + +val = 10; +divsel = 2; + + // Make sure the PLL is not running in limp mode + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + asm(" ESTOP0"); + } + + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // Change the PLLCR +// if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + + EALLOW; + // Before setting PLLCR turn off missing clock detect logic + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + Val = (val)?val:1; + Val = XCLKIN * (Val / 2); + SYSCLKOUT = Val; + + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + + // Wait for the PLL lock bit to be set. + + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + + // Uncomment to disable the watchdog + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // Uncomment to service the watchdog + // ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // If switching to 1/2 + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); +// pause_us(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +//-------------------------------------------------------------------------- +// Example: InitPeripheralClocks: +//--------------------------------------------------------------------------- +// This function initializes the clocks to the peripheral modules. +// First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. +// To reduce power, leave clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral + +void InitPeripheralClocks(void) +{ + long Val; + + EALLOW; + +// HISPCP/LOSPCP prescale register settings, normally it will be set to default values + SysCtrlRegs.HISPCP.all = 0x0003; + SysCtrlRegs.LOSPCP.all = 0x0000; + + Val = (SysCtrlRegs.HISPCP.all)? + SysCtrlRegs.HISPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + + HSPCLK = Val; + + Val = (SysCtrlRegs.LOSPCP.all)? + SysCtrlRegs.LOSPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + LSPCLK = Val; + +// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + // Enable XCLKOUT + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + +// Peripheral clock enables set for the selected peripherals. +// If you are not using a peripheral leave the clock off +// to save on power. +// +// Note: not all peripherals are available on all 2833x derivates. +// Refer to the datasheet for your particular device. +// +// This function is not written to be an example of efficient code. + + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + ADC_cal(); + + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: CsmUnlock: +//--------------------------------------------------------------------------- +// This function unlocks the CSM. User must replace 0xFFFF's with current +// password for the DSP. Returns 1 if unlock is successful. + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 + +Uint16 CsmUnlock() +{ + volatile Uint16 temp; + + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the DSP. + + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // Perform a dummy read of the password locations + // if they match the key values, the CSM will unlock + + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // If the CSM unlocked, return succes, otherwise return + // failure. + if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; + else return STATUS_FAIL; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Xintf.c b/v120/DSP2833x_common/source/DSP2833x_Xintf.c new file mode 100644 index 0000000..302ca91 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Xintf.c @@ -0,0 +1,242 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: August 16, 2007 11:06:26 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.c +// +// TITLE: DSP2833x Device External Interface Init & Support Functions. +// +// DESCRIPTION: +// +// Example initialization function for the external interface (XINTF). +// This example configures the XINTF to its default state. For an +// example of how this function being used refer to the +// examples/run_from_xintf project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitXINTF: +//--------------------------------------------------------------------------- +// This function initializes the External Interface the default reset state. +// +// Do not modify the timings of the XINTF while running from the XINTF. Doing +// so can yield unpredictable results + + +void InitXintf(void) +{ + // This shows how to write to the XINTF registers. The + // values used here are the default state after reset. + // Different hardware will require a different configuration. + + // For an example of an XINTF configuration used with the + // F28335 eZdsp, refer to the examples/run_from_xintf project. + + // Any changes to XINTF timing should only be made by code + // running outside of the XINTF. + + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // No write buffering + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + + // Zone 0------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING0.bit.XWRLEAD = 3; + XintfRegs.XTIMING0.bit.XWRACTIVE = 7; + XintfRegs.XTIMING0.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 7; + XintfRegs.XTIMING0.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING0.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING0.bit.USEREADY = 1; + XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING0.bit.XSIZE = 3; + + // Zone 6------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING6.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING6.bit.XSIZE = 3; + + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 7; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 1; + XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + + // Bank switching + // Assume Zone 7 is slow, so add additional BCYC cycles + // when ever switching from Zone 7 to another Zone. + // This will help avoid bus contention. + XintfRegs.XBANK.bit.BANK = 7; + XintfRegs.XBANK.bit.BCYC = 7; + EDIS; + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + InitXintf16Gpio(); +// InitXintf32Gpio(); + + asm(" RPT #7 || NOP"); + +} + +void InitXintf32Gpio() +{ + EALLOW; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 + GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 + GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 + GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 + + GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input + + + InitXintf16Gpio(); +} + +void InitXintf16Gpio() +{ + EALLOW; + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 + + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_usDelay.asm b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm new file mode 100644 index 0000000..d3878b4 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm @@ -0,0 +1,76 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + .def _DSP28x_usDelay + .sect ".text" + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c b/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c new file mode 100644 index 0000000..dab0e92 --- /dev/null +++ b/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: Example_2833xAdcToDMA.c +// +// TITLE: DSP2833x ADC To DMA +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect the signals to be converted to channel A0, A1, A2, and A3. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// DESCRIPTION: +// +// ADC is setup to convert 4 channels for each SOC received, with total of 10 SOCs. +// Each SOC initiates 4 conversions. +// DMA is set up to capture the data on each SEQ1_INT. DMA will re-sort +// the data by channel sequentially, i.e. all channel0 data will be together +// all channel1 data will be together. +// +// Code should stop in local_DINTCH1_ISR when complete +// +// Watch Variables: +// DMABuf1 +// +//########################################################################### +// +// Original source by: M.P. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// ADC start parameters +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz +#endif +#if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz +#endif +#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 40 // Sample buffer size + +// Global variable for this example +Uint16 j=0; + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +volatile Uint16 DMABuf1[40]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; +interrupt void local_DINTCH1_ISR(void); + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Specific clock setting for this example: + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Specific ADC setup for this example: + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x2; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x3; + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; // Set up ADC to perform 4 conversions for every SOC + +//Step 5. User specific code, enable interrupts: + // Initialize DMA + DMAInitialize(); + + // Clear Table + for (i=0; i>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)>>4); + +#endif //-- INLINE_SHIFT + +#if NO_SHIFT || POST_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)); + +#endif //-- NO_SHIFT || POST_SHIFT + + while (AdcRegs.ADCST.bit.INT_SEQ1== 0){} + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // Clear GPIO34 for monitoring -optional + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; + +#if INLINE_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)>>4); + +#endif //-- INLINE_SHIFT + +#if NO_SHIFT || POST_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)); +#endif // -- NO_SHIFT || POST_SHIFT + + } + + +#if POST_SHIFT + // For post shifting, shift the ADC results + // in the SampleTable buffer after the buffer is full. + for (i=0; i>4); + } +#endif // -- POST_SHIFT + + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // Clear GPIO34 for monitoring -optional + } +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel new file mode 100644 index 0000000..4bf2af1 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:35 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC Seq_ovd Test" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSeq_ovdTest.pjt"); + GEL_ProjectBuild("Example_2833xAdcSeq_ovdTest.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSeq_ovdTest.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("SampleTable,x"); + GEL_WatchAdd("AdcRegs,x",); +} + + diff --git a/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt new file mode 100644 index 0000000..414d901 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSeq_ovdTest.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeq_ovdTest.map" -o".\Debug\Example_2833xAdcSeq_ovdTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSeq_ovdTest.out" -x + diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c new file mode 100644 index 0000000..70299a6 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c @@ -0,0 +1,164 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:40:57 $ +//########################################################################### +// +// FILE: Example_2833xAdcSeqModeTest.c +// +// TITLE: DSP2833x ADC Seq Mode Test. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect the signal to be converted to channel A0. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Channel A0 is converted forever and logged in a buffer (SampleTable) +// +// Open a memory window to SampleTable to observe the buffer +// RUN for a while and stop and see the table contents. +// +// Watch Variables: +// SampleTable - Log of converted values. +// +//########################################################################### +// +// Original source by: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// ADC start parameters +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz +#endif +#if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz +#endif +#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 2048 // Sample buffer size + +// Global variable for this example +Uint16 SampleTable[BUF_SIZE]; + +main() +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Specific clock setting for this example: + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Specific ADC setup for this example: + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run + + +// Step 5. User specific code, enable interrupts: + + +// Clear SampleTable + for (i=0; i>4) ); + } + } +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel new file mode 100644 index 0000000..6ea6c86 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:47 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC Seq Test" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSeqModeTest.pjt"); + GEL_ProjectBuild("Example_2833xAdcSeqModeTest.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSeqModeTest.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("SampleTable,x"); + GEL_WatchAdd("AdcRegs,x"); +} diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt new file mode 100644 index 0000000..35d0116 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSeqModeTest.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeqModeTest.map" -o".\Debug\Example_2833xAdcSeqModeTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSeqModeTest.out" -x + diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c new file mode 100644 index 0000000..6a53322 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c @@ -0,0 +1,203 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: April 21, 2008 15:41:01 $ +//########################################################################### +// +// FILE: Example_2833xAdc.c +// +// TITLE: DSP2833x ADC Example Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect signals to be converted to A2 and A3. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example sets up the PLL in x10/2 mode. +// +// For 150 MHz devices (default) +// divides SYSCLKOUT by six to reach a 25.0Mhz HSPCLK +// (assuming a 30Mhz XCLKIN). +// +// For 100 MHz devices: +// divides SYSCLKOUT by four to reach a 25.0Mhz HSPCLK +// (assuming a 20Mhz XCLKIN). +// +// Interrupts are enabled and the ePWM1 is setup to generate a periodic +// ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2. +// +// Watch Variables: +// +// Voltage1[10] Last 10 ADCRESULT0 values +// Voltage2[10] Last 10 ADCRESULT1 values +// ConversionCount Current result number 0-9 +// LoopCount Idle loop counter +// +// +//########################################################################### +// +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +// Global variables used in this example: +Uint16 LoopCount; +Uint16 ConversionCount; +Uint16 Voltage1[10]; +Uint16 Voltage2[10]; + + +main() +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + + EALLOW; + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Step 5. User specific code, enable interrupts: + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + LoopCount = 0; + ConversionCount = 0; + +// Configure ADC + AdcRegs.ADCMAXCONV.all = 0x0001; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // Setup ADCINA3 as 1st SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1 + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start + +// Wait for ADC interrupt + for(;;) + { + LoopCount++; + } + +} + + +interrupt void adc_isr(void) +{ + + Voltage1[ConversionCount] = AdcRegs.ADCRESULT0 >>4; + Voltage2[ConversionCount] = AdcRegs.ADCRESULT1 >>4; + + // If 40 conversions have been logged, start over + if(ConversionCount == 9) + { + ConversionCount = 0; + } + else ConversionCount++; + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + + return; +} + + + diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel new file mode 100644 index 0000000..2d14fe1 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC SOC Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSoc.pjt"); + GEL_ProjectBuild("Example_2833xAdcSoc.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSoc.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("Voltage1,x"); + GEL_WatchAdd("Voltage2,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("ConversionCount,d"); + GEL_WatchAdd("AdcRegs,x"); + GEL_WatchAdd("EPwm1Regs,x"); +} diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt new file mode 100644 index 0000000..0c46c78 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP28" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" + +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSoc.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSoc.map" -o".\Debug\Example_2833xAdcSoc.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSoc.out" -x + diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c new file mode 100644 index 0000000..a4bfaff --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c @@ -0,0 +1,189 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: April 21, 2008 15:41:07 $ +//########################################################################### +// +// FILE: Example_2833xCpuTimer.c +// +// TITLE: DSP2833x Device Getting Started Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures CPU Timer0, 1, and 2 and increments +// a counter each time the timers assert an interrupt. +// +// Watch Variables: +// CpuTimer0.InterruptCount +// CpuTimer1.InterruptCount +// CpuTimer2.InterruptCount +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void cpu_timer0_isr(void); +interrupt void cpu_timer1_isr(void); +interrupt void cpu_timer2_isr(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize the Device Peripheral. This function can be +// found in DSP2833x_CpuTimers.c + InitCpuTimers(); // For this example, only initialize the Cpu Timers + +#if (CPU_FRQ_150MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 150MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); +#endif + +#if (CPU_FRQ_100MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 100MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); +#endif +// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any +// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the +// below settings must also be updated. + + CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + +// Step 5. User specific code, enable interrupts: + + +// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 +// which is connected to CPU-Timer 1, and CPU int 14, which is connected +// to CPU-Timer 2: + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + +// Enable TINT0 in the PIE: Group 1 interrupt 7 + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +interrupt void cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel new file mode 100644 index 0000000..cd7890d --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:12:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x CpuTimerExample" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xCpuTimer.pjt"); + GEL_ProjectBuild("Example_2833xCpuTimer.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xCpuTimer.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer0",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer0Regs,x"); + GEL_WatchAdd("CpuTimer1.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer1",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer1Regs,x"); + GEL_WatchAdd("CpuTimer2.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer2",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer2Regs,x"); +} diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt new file mode 100644 index 0000000..df3939c --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xCpuTimer.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xCpuTimer.map" -o".\Debug\Example_2833xCpuTimer.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c b/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c new file mode 100644 index 0000000..ebee46e --- /dev/null +++ b/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c @@ -0,0 +1,189 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: May 12, 2008 14:23:19 $ +//########################################################################### +// +// FILE: Example_2833xDMA_Ram_to_Ram.c +// +// TITLE: DSP2833x DMA Ram to Ram +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// DESCRIPTION: +// +// Code will perform a block copy from L5 SARAM to L4 SARAM of 1024 words. Transfer will be started +// by Timer0. Will use 32-bit datasize to decrease the transfer time. +// Code will end in local_DINTCH1_ISR once the transfer is complete +// +// Watch Variables: +// DMABuf1 +// DMABuf2 +// +//########################################################################### +// +// Original source by: M.P. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +#define BUF_SIZE 1024 // Sample buffer size + + + + +// DMA Defines +#define CH1_TOTAL DATA_POINTS_PER_CHANNEL +#define CH1_WORDS_PER_BURST ADC_CHANNELS_TO_CONVERT + + + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +#pragma DATA_SECTION(DMABuf2,"DMARAML5"); + +volatile Uint16 DMABuf1[1024]; +volatile Uint16 DMABuf2[1024]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; + +interrupt void local_DINTCH1_ISR(void); + + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + CpuTimer0Regs.TCR.bit.TSS = 1; //Stop Timer0 for now + + +//Step 5. User specific code, enable interrupts: + // Initialize DMA + DMAInitialize(); + + // Initialize Tables + for (i=0; iMDL.all; // = 0x9555AAAn (n is the MBX number) + TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant) + TestMbox3 = Mailbox->MSGID.all;// = 0x9555AAAn (n is the MBX number) + +} // MSGID of a rcv MBX is transmitted as the MDL data. + + +void mailbox_check(int32 T1, int32 T2, int32 T3) +{ + if((T1 != T3) || ( T2 != 0x89ABCDEF)) + { + ErrorCount++; + } + else + { + PassCount++; + } +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel new file mode 100644 index 0000000..90f787e --- /dev/null +++ b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:12:48 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ECanBack2Back" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECanBack2Back.pjt"); + GEL_ProjectBuild("Example_2833xECanBack2Back.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECanBack2Back.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("MessageReceivedCount,x"); + GEL_WatchAdd("ErrorCount,x"); + GEL_WatchAdd("PassCount,x"); + GEL_WatchAdd("ECanaRegs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt new file mode 100644 index 0000000..cbe5cf6 --- /dev/null +++ b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECan.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECanBack2Back.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECanBack2Back.map" -o".\Debug\Example_2833xECanBack2Back.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xECanBack2Back.out" -x + diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c new file mode 100644 index 0000000..1d1693a --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c @@ -0,0 +1,223 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:41:24 $ +//########################################################################### +// +// FILE: Example_2833xECap_apwm.c +// +// TITLE: DSP2833x ECAP APWM Example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor eCAP1 - eCAP4 pins on a oscilloscope as +// described below. +// +// eCAP1 on GPIO24 +// eCAP2 on GPIO7 +// eCAP3 on GPIO9 +// eCAP4 on GPIO11 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program sets up the eCAP pins in the APWM mode. +// This program runs at 150 MHz SYSCLKOUT assuming a 30 MHz +// XCLKIN or 100 MHz SYSCLKOUT assuming a 20 MHz XCLKIN. +// +// For 150 MHz devices: +// +// eCAP1 will come out on the GPIO24 pin +// This pin is configured to vary between 7.5 Hz and 15 Hz using +// the shadow registers to load the next period/compare values +// +// eCAP2 will come out on the GPIO7 pin +// this pin is configured as a 7.5 Hz output +// +// eCAP3 will come out on the GPIO9 pin +// this pin is configured as a 1.5 Hz output +// +// +// eCAP4 will come out on the GPIO11 pin +// this pin is configured as a 30 kHz output +// +// All frequencies assume a 30 Mhz input clock. The XCLKOUT pin +// should show 150Mhz. +// -------------------------------------------------------------- +// For 100 MHz devices: +// +// eCAP1 will come out on the GPIO24 pin +// This pin is configured to vary between 5 Hz and 10 Hz using +// the shadow registers to load the next period/compare values +// +// eCAP2 will come out on the GPIO7 pin +// this pin is configured as a 5 Hz output +// +// eCAP3 will come out on the GPIO9 pin +// this pin is configured as a 1 Hz output +// +// eCAP4 will come out on the GPIO11 pin +// this pin is configured as a 20kHz output +// +// All frequencies assume a 20 Mhz input clock. The XCLKOUT pin +// should show 100Mhz. +// +// +// Watch Variables: +// +// +// +//########################################################################### +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Global variables +Uint16 direction = 0; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Initialize the GPIO pins for eCAP. +// This function is found in the DSP2833x_ECap.c file + InitECapGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. +// No interrupts used for this example. + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code + + + // Setup APWM mode on CAP1, set period and compare registers + ECap1Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap1Regs.CAP1 = 0x01312D00; // Set Period value + ECap1Regs.CAP2 = 0x00989680; // Set Compare value + ECap1Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP2, set period and compare registers + ECap2Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap2Regs.CAP1 = 0x01312D00; // Set Period value + ECap2Regs.CAP2 = 0x00989680; // Set Compare value + ECap2Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP3, set period and compare registers + ECap3Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap3Regs.CAP1 = 0x05F5E100; // Set Period value + ECap3Regs.CAP2 = 0x02FAF080; // Set Compare value + ECap3Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP4, set period and compare registers + ECap4Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap4Regs.CAP1 = 0x00001388; // Set Period value + ECap4Regs.CAP2 = 0x000009C4; // Set Compare value + ECap4Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Start counters + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap4Regs.ECCTL2.bit.TSCTRSTOP = 1; + + for(;;) + { + // set next duty cycle to 50% + ECap1Regs.CAP4 = ECap1Regs.CAP1 >> 1; + + // vary freq between 7.5 Hz and 15 Hz (for 150MHz SYSCLKOUT) 5 Hz and 10 Hz (for 100 MHz SYSCLKOUT) + if(ECap1Regs.CAP1 >= 0x01312D00) + { + direction = 0; + } else if (ECap1Regs.CAP1 <= 0x00989680) + { + direction = 1; + } + + if(direction == 0) + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 - 500000; + } else + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 + 500000; + } + } + +} + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel new file mode 100644 index 0000000..15cb906 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:02 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eCAP Asym PWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECap_apwm.pjt"); + GEL_ProjectBuild("Example_2833xECap_apwm.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECap_apwm.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("ECap1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt new file mode 100644 index 0000000..d982655 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECap.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECap_apwm.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECap_apwm.map" -o".\Debug\Example_2833xECap_apwm.out" -stack0x380 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xECap_apwm.out" -x + diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c new file mode 100644 index 0000000..22ecde8 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c @@ -0,0 +1,288 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:29 $ +//########################################################################### +// +// FILE: Example_2833xECap_Capture_Pwm.c +// +// TITLE: Capture EPWM3. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make the following external connection: +// EPWM3 on GPIO4 should be connected to ECAP1 on GPIO24. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM3A for: +// - Up count +// - Period starts at 2 and goes up to 1000 +// - Toggle output on PRD +// +// eCAP1 is configured to capture the time between rising +// and falling edge of the PWM3A output. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +// Configure the start/end period for the timer +#define PWM3_TIMER_MIN 10 +#define PWM3_TIMER_MAX 8000 + +// Prototype statements for functions found within this file. +interrupt void ecap1_isr(void); +void InitECapture(void); +void InitEPwmTimer(void); +void Fail(void); + +// Global variables used in this example +Uint32 ECap1IntCount; +Uint32 ECap1PassCount; +Uint32 EPwm3TimerDirection; + +// To keep track of which way the timer value is moving +#define EPWM_TIMER_UP 1 +#define EPWM_TIMER_DOWN 0 + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + InitEPwm3Gpio(); + InitECap1Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.ECAP1_INT = &ecap1_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + InitECapture(); + + +// Step 5. User specific code, enable interrupts: + +// Initalize counters: + ECap1IntCount = 0; + ECap1PassCount = 0; + +// Enable CPU INT4 which is connected to ECAP1-4 INT: + IER |= M_INT4; + +// Enable eCAP INTn in the PIE: Group 3 interrupt 1-6 + PieCtrlRegs.PIEIER4.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = PWM3_TIMER_MIN; + EPwm3Regs.TBPHS.all = 0x00000000; + EPwm3Regs.AQCTLA.bit.PRD = AQ_TOGGLE; // Toggle on PRD + + // TBCLK = SYSCLKOUT + EPwm3Regs.TBCTL.bit.HSPCLKDIV = 1; + EPwm3Regs.TBCTL.bit.CLKDIV = 0; + + + EPwm3TimerDirection = EPWM_TIMER_UP; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +} + +void InitECapture() +{ + ECap1Regs.ECEINT.all = 0x0000; // Disable all capture interrupts + ECap1Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags + ECap1Regs.ECCTL1.bit.CAPLDEN = 0; // Disable CAP1-CAP4 register loads + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 0; // Make sure the counter is stopped + + // Configure peripheral registers + ECap1Regs.ECCTL2.bit.CONT_ONESHT = 1; // One-shot + ECap1Regs.ECCTL2.bit.STOP_WRAP = 3; // Stop at 4 events + ECap1Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP2POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CAP3POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP4POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CTRRST1 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation + ECap1Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable sync in + ECap1Regs.ECCTL2.bit.SYNCO_SEL = 0; // Pass through + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units + + + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter + ECap1Regs.ECCTL2.bit.REARM = 1; // arm one-shot + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable CAP1-CAP4 register loads + ECap1Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt + +} + + + +interrupt void ecap1_isr(void) +{ + + // Cap input is syc'ed to SYSCLKOUT so there may be + // a +/- 1 cycle variation + + if(ECap1Regs.CAP2 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP2 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP3 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP3 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP4 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP4 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + + ECap1IntCount++; + + if(EPwm3TimerDirection == EPWM_TIMER_UP) + { + if(EPwm3Regs.TBPRD < PWM3_TIMER_MAX) + { + EPwm3Regs.TBPRD++; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_DOWN; + EPwm3Regs.TBPRD--; + } + } + else + { + if(EPwm3Regs.TBPRD > PWM3_TIMER_MIN) + { + EPwm3Regs.TBPRD--; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_UP; + EPwm3Regs.TBPRD++; + } + } + + ECap1PassCount++; + + ECap1Regs.ECCLR.bit.CEVT4 = 1; + ECap1Regs.ECCLR.bit.INT = 1; + ECap1Regs.ECCTL2.bit.REARM = 1; + + // Acknowledge this interrupt to receive more interrupts from group 4 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; +} + + +void Fail() +{ + asm(" ESTOP0"); +} + + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel new file mode 100644 index 0000000..aefa65b --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel @@ -0,0 +1,46 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eCAP Capture PWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECap_Capture_Pwm.pjt"); + GEL_ProjectBuild("Example_2833xECap_Capture_Pwm.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECap_Capture_Pwm.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("ECap1IntCount,x"); + GEL_WatchAdd("ECap1PassCount,x"); + GEL_WatchAdd("EPwm3Regs.TBPRD,x"); + GEL_WatchAdd("ECap1Regs.CAP2,x"); + GEL_WatchAdd("ECap1Regs.CAP3,x"); + GEL_WatchAdd("ECap1Regs.CAP4,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("ECap1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt new file mode 100644 index 0000000..cae4269 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt @@ -0,0 +1,47 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECap.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECap_Capture_Pwm.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECap_Capture_Pwm.map" -o".\Debug\Example_2833xECap_Capture_Pwm.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c new file mode 100644 index 0000000..8e91544 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c @@ -0,0 +1,457 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:33 $ +//########################################################################### +// +// FILE: Example_2833xEpwmDeadBand.c +// +// TITLE: Check PWM deadband generation +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1 - ePWM3 on an Oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2 and ePWM3 for: +// - Count up/down +// - Deadband +// +// 3 Examples are included: +// * ePWM1: Active low PWMs +// * ePWM2: Active low complementary PWMs +// * ePWM3: Active high complementary PWMs +// +// Each ePWM is configured to interrupt on the 3rd zero event +// when this happens the deadband is modified such that +// 0 <= DB <= DB_MAX. That is, the deadband will move up and +// down between 0 and the maximum value. +// +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint16 EPwm1_DB_Direction; +Uint16 EPwm2_DB_Direction; +Uint16 EPwm3_DB_Direction; + +// Maximum Dead Band values +#define EPWM1_MAX_DB 0x03FF +#define EPWM2_MAX_DB 0x03FF +#define EPWM3_MAX_DB 0x03FF + +#define EPWM1_MIN_DB 0 +#define EPWM2_MIN_DB 0 +#define EPWM3_MIN_DB 0 + +// To keep track of which way the Dead Band is moving +#define DB_UP 1 +#define DB_DOWN 0 + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_isr(void) +{ + if(EPwm1_DB_Direction == DB_UP) + { + if(EPwm1Regs.DBFED < EPWM1_MAX_DB) + { + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1_DB_Direction = DB_DOWN; + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + else + { + if(EPwm1Regs.DBFED == EPWM1_MIN_DB) + { + EPwm1_DB_Direction = DB_UP; + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + +interrupt void epwm2_isr(void) +{ + + if(EPwm2_DB_Direction == DB_UP) + { + if(EPwm2Regs.DBFED < EPWM2_MAX_DB) + { + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2_DB_Direction = DB_DOWN; + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + else + { + if(EPwm2Regs.DBFED == EPWM2_MIN_DB) + { + EPwm2_DB_Direction = DB_UP; + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + + EPwm2TimerIntCount++; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + +interrupt void epwm3_isr(void) +{ + if(EPwm3_DB_Direction == DB_UP) + { + if(EPwm3Regs.DBFED < EPWM3_MAX_DB) + { + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3_DB_Direction = DB_DOWN; + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + else + { + if(EPwm3Regs.DBFED == EPWM3_MIN_DB) + { + EPwm3_DB_Direction = DB_UP; + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + + + EPwm3TimerIntCount++; + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + + + +void InitEPwm1Example() +{ + + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Setup compare + EPwm1Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active Low PWMs - Setup Deadband + EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO; + EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm1Regs.DBRED = EPWM1_MIN_DB; + EPwm1Regs.DBFED = EPWM1_MIN_DB; + EPwm1_DB_Direction = DB_UP; + + // Interrupt where we will change the Deadband + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + +} + + +void InitEPwm2Example() +{ + + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope + + // Setup compare + EPwm2Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active Low complementary PWMs - setup the deadband + EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; + EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm2Regs.DBRED = EPWM2_MIN_DB; + EPwm2Regs.DBFED = EPWM2_MIN_DB; + EPwm2_DB_Direction = DB_UP; + + // Interrupt where we will modify the deadband + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + +} + +void InitEPwm3Example() +{ + + EPwm3Regs.TBPRD = 6000; // Set timer period + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow so we can observe on the scope + + // Setup compare + EPwm3Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero + EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero + EPwm3Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active high complementary PWMs - Setup the deadband + EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; + EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm3Regs.DBRED = EPWM3_MIN_DB; + EPwm3Regs.DBFED = EPWM3_MIN_DB; + EPwm3_DB_Direction = DB_UP; + + // Interrupt where we will change the deadband + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt new file mode 100644 index 0000000..08ffef5 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmDeadBand.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmDeadBand.map" -o".\Debug\Example_2833xEPwmDeadBand.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwmDeadBand.map" -o".\Release\Example_2833xEPwmDeadBand.out" -x + diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel new file mode 100644 index 0000000..4466bd1 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:25 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM Deadband" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmDeadBand.pjt"); + GEL_ProjectBuild("Example_2833xEPwmDeadBand.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmDeadBand.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd new file mode 100644 index 0000000..2a2abf8 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:23:49 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ + +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd new file mode 100644 index 0000000..c107ade --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd @@ -0,0 +1,182 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:23:45 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ + +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 +} + + + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c new file mode 100644 index 0000000..9645539 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c @@ -0,0 +1,455 @@ +//########################################################################### +// +// FILE: Example_2833xEPwm_DMA.c +// +// TITLE: DSP2833x Device DMA interface with ePWM example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example demonstrates several cases where the DMA is triggered from +// SOC signals generated by ePWM modules. +// +// DMA CH1 setup: +// Trigger = ADCSOCA from ePWM1 +// Datasize = 16 bits +// Source = VarA +// Dest = EPwm1Regs.TBPRD +// Burst = One word / burst +// Transfer = One burst / transfer +// CPU int = every transfer +// +// DMA CH2 setup: +// Trigger = ADCSOCB from ePWM2 +// Datasize = 32 bits +// Source = VarB +// Dest = EPwm1Regs.CMPA.all +// Burst = One 32-bit word / burst +// Transfer = One burst / transfer +// CPU int = none +// +// DMA CH3 setup: +// Trigger = ADC SEQ1INT +// Datasize = 32 bits +// Source = AdcMirror.ADCRESULT[0-5] +// Dest = ADCbuffer +// Burst = Three 32-bit words / burst +// Transfer = One burst / transfer +// CPU int = none +// +// Watch Variables: +// +// EPwm1Regs.TBPRD +// EPwm1Regs.CMPA.all +// ADCbuffer +// InterruptCount +// +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +// Prototype statements for functions found within this file. +void delay_loop(void); +void DMAInitialize(void); +void DMACH1Config(void); +void DMACH2Config(void); +void DMACH3Config(void); +void ConfigAdc(void); +void config_ePWM1_to_generate_ADCSOCA(void); +void config_ePWM2_to_generate_ADCSOCB(void); +interrupt void local_DINTCH1_ISR(void); + + +// Global Variables +#pragma DATA_SECTION(ADCbuffer,"DMARAML4"); +volatile Uint32 ADCbuffer[3]; + +Uint16 VarA; +Uint32 VarB; + +volatile Uint16 *MAPCNF = (Uint16 *)0x00702E; + +Uint16 InterruptCount; + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this example use the following configuration: + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + EALLOW; + // Initialize PIE vector for CPU interrupt: + PieVectTable.DINTCH1 = &local_DINTCH1_ISR; // Point to DMA CH1 ISR + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + + InterruptCount = 0; + + EALLOW; + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + SysCtrlRegs.MAPCNF.bit.MAPEPWM = 1; // Remap ePWMs for DMA access + EDIS; + + GpioDataRegs.GPASET.all = 0xFFFFFFFF; + delay_loop(); + GpioDataRegs.GPACLEAR.all = 0x00000002; + + for(i=0; i<3; i++) + { + ADCbuffer[i] = ((Uint32)i*0x00011000) + 0x00044000; + } + + VarA = 75; + VarB = 0x652000; + + // Enable and configure clocks to peripherals: + EALLOW; + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // Enable SYSCLK to DMA + EDIS; + + DMAInitialize(); + DMACH1Config(); + DMACH2Config(); + DMACH3Config(); + + // Enable all interrupts: + IER = M_INT7; // Enable INT7 (7.1 DMA Ch1) + EINT; + + InitAdc(); + ConfigAdc(); + + config_ePWM1_to_generate_ADCSOCA(); + config_ePWM2_to_generate_ADCSOCB(); + + + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + asm(" NOP"); + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EDIS; + + for(;;) {} + +} + + +//=========================================================================== +// DMA Functions +//=========================================================================== + +void DMAInitialize(void) +{ + EALLOW; + + // Perform a hard reset on DMA + DmaRegs.DMACTRL.bit.HARDRESET = 1; + + // always perform one NOP after a HARDRESET + asm(" NOP"); + + // Stop DMA on emulation suspend + DmaRegs.DEBUGCTRL.bit.FREE = 0; + + EDIS; +} + + +void DMACH1Config(void) +{ + EALLOW; + // Configure CH1: + // + // Reset selected channel via CONTROL Register: +// DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters) + + // Set up MODE Register: + DmaRegs.CH1.MODE.bit.PERINTSEL = 18; // ePWM1 SOCA as peripheral interrupt source + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers + DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // Generate interrupt to CPU at the beg of transfer + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enabled + + // Set up BURST registers: + DmaRegs.CH1.BURST_SIZE.all = 0; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH1.SRC_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + DmaRegs.CH1.DST_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + + // Set up TRANSFER registers: + DmaRegs.CH1.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH1.SRC_WRAP_STEP = 0; + DmaRegs.CH1.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &VarA; // Point to variable in RAM + + // Set up DESTINATION address: + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.TBPRD; // Point to ePWM1 TBPRD register remapped for DMA + // need to make sure .cmd file has ePWMs remapped + // Clear any spurious flags: + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + +void DMACH2Config(void) +{ + EALLOW; + // Configure CH2: + // + // Reset selected channel via CONTROL Register: +// DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters) + + // Set up MODE Register: + DmaRegs.CH2.MODE.bit.PERINTSEL = 21; // ePWM2 SOCB as peripheral interrupt source + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH2.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH2.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH2.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH2.MODE.bit.CHINTMODE = 0; + DmaRegs.CH2.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // Set up BURST registers: + DmaRegs.CH2.BURST_SIZE.all = 1; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH2.SRC_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst + DmaRegs.CH2.DST_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst + + // Set up TRANSFER registers: + DmaRegs.CH2.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH2.SRC_WRAP_STEP = 0; + DmaRegs.CH2.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &VarB; // Point to variable in RAM + + // Set up DESTINATION address: + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.CMPA.all; // Point to ePWM1 CMPAHR/CMPA registers + + // Clear any spurious flags: + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + +void DMACH3Config(void) +{ + EALLOW; + // Configure CH3: + // + + // Set up MODE Register: + DmaRegs.CH3.MODE.bit.PERINTSEL = 1; // ADC SEQ1INT as peripheral interrupt source + DmaRegs.CH3.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH3.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH3.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH3.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH3.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH3.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH3.MODE.bit.CHINTMODE = 0; + DmaRegs.CH3.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // Set up BURST registers: + DmaRegs.CH3.BURST_SIZE.all = 5; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH3.SRC_BURST_STEP = 2; // Increment source burst address by 2 (32-bit) + DmaRegs.CH3.DST_BURST_STEP = 2; // Increment destination burst address by 2 (32-bit) + + // Set up TRANSFER registers: + DmaRegs.CH3.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH3.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH3.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH3.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH3.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH3.SRC_WRAP_STEP = 0; + DmaRegs.CH3.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32) &AdcMirror.ADCRESULT0; // Point to first RESULT reg + + // Set up DESTINATION address: + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32) &ADCbuffer[0]; // Point to beginning of ADCbuffer + + // Clear any spurious flags: + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + + + +interrupt void local_DINTCH1_ISR(void) // DMA INT7.1 +{ + GpioDataRegs.GPATOGGLE.all = 0x00000001; // Toggle GPIOA0 + + InterruptCount++; + + + if((DmaRegs.CH1.CONTROL.bit.OVRFLG == 1) || (DmaRegs.CH2.CONTROL.bit.OVRFLG == 1) || + (DmaRegs.CH3.CONTROL.bit.OVRFLG == 1)) + { + asm(" ESTOP0"); + } + + PieCtrlRegs.PIEACK.bit.ACK7 = 1; // Clear PIEIFR bit +} + + +void ConfigAdc(void) +{ + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 7; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // ADCINA0 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // ADCINA1 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // ADCINA2 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // ADCINA3 + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4; // ADCINA4 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5; // ADCINA5 + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable ADC to accept ePWM_SOCA trigger + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear interrupt flag + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt +} + + +void config_ePWM1_to_generate_ADCSOCA(void) +{ + // Configure ePWM1 Timer + // Interrupt triggers ADCSOCA + + EALLOW; + EPwm1Regs.TBPRD = 74; // Setup period (one off so DMA transfer will be obvious) + EPwm1Regs.CMPA.all = 0x501000; + EPwm1Regs.ETSEL.bit.SOCASEL = 2; // ADCSOCA on TBCTR=TBPRD + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate SOCA on 1st event + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA generation + EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + + +void config_ePWM2_to_generate_ADCSOCB(void) +{ + // Configure ePWM2 Timer + // Interrupt triggers ADCSOCB + + EALLOW; + EPwm2Regs.TBPRD = 150; // Setup periodSetup period + EPwm2Regs.CMPA.all = 0x200000; + EPwm2Regs.ETSEL.bit.SOCBSEL = 2; // ADCSOCB on TBCTR=TBPRD + EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate SOCB on 1st event + EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB generation + EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + + +void delay_loop() +{ + short i; + for (i = 0; i < 1000; i++) {} +} + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel new file mode 100644 index 0000000..f5ab59c --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:25:20 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM DMA" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwm_DMA.pjt"); + GEL_ProjectBuild("Example_2833xEPwm_DMA.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwm_DMA.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs.TBPRD,x"); + GEL_WatchAdd("EPwm1Regs.CMPA.all,x"); + GEL_WatchAdd("ADCbuffer,x"); + GEL_WatchAdd("InterruptCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt new file mode 100644 index 0000000..69ca432 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwm_DMA.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="DSP2833x_EPWMDM_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwm_DMA.map" -o".\Debug\Example_2833xEPwm_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwm_DMA.map" -o".\Release\Example_2833xEPwm_DMA.out" -x + diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c new file mode 100644 index 0000000..58927b6 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c @@ -0,0 +1,360 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:38 $ +//########################################################################### +// +// FILE: Example_2833xEPwmTimerInt.c +// +// TITLE: DSP2833x ePWM Timer Interrupt example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures the ePWM Timers and increments +// a counter each time an interrupt is taken. +// +// As supplied: +// +// All ePWM's are initalized. Note that not all devices in the 2833x +// family have all 6 ePWMs. +// +// All timers have the same period +// The timers are started sync'ed +// An interrupt is taken on a zero event for each ePWM timer +// +// ePWM1: takes an interrupt every event +// ePWM2: takes an interrupt every 2nd event +// ePWM3: takes an interrupt every 3rd event +// ePWM4-ePWM6: take an interrupt every event +// +// Thus the Interrupt count for ePWM1, ePWM4-ePWM6 should be equal +// The interrupt count for ePWM2 should be about half that of ePWM1 +// and the interrupt count for ePWM3 should be about 1/3 that of ePWM1 +// +// Watch Variables: +// EPwm1TimerIntCount +// EPwm2TimerIntCount +// EPwm3TimerIntCount +// EPwm4TimerIntCount +// EPwm5TimerIntCount +// EPwm6TimerIntCount +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Configure which ePWM timer interrupts are enabled at the PIE level: +// 1 = enabled, 0 = disabled +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 +#define PWM4_INT_ENABLE 1 +#define PWM5_INT_ENABLE 1 +#define PWM6_INT_ENABLE 1 + +// Configure the period for each timer +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF +#define PWM4_TIMER_TBPRD 0x1FFF +#define PWM5_TIMER_TBPRD 0x1FFF +#define PWM6_TIMER_TBPRD 0x1FFF + + +// Prototype statements for functions found within this file. +interrupt void epwm1_timer_isr(void); +interrupt void epwm2_timer_isr(void); +interrupt void epwm3_timer_isr(void); +interrupt void epwm4_timer_isr(void); +interrupt void epwm5_timer_isr(void); +interrupt void epwm6_timer_isr(void); +void InitEPwmTimer(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 EPwm4TimerIntCount; +Uint32 EPwm5TimerIntCount; +Uint32 EPwm6TimerIntCount; + + +void main(void) +{ + int i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + PieVectTable.EPWM4_INT = &epwm4_timer_isr; + PieVectTable.EPWM5_INT = &epwm5_timer_isr; + PieVectTable.EPWM6_INT = &epwm6_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + +// Step 5. User specific code, enable interrupts: + +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + EPwm4TimerIntCount = 0; + EPwm5TimerIntCount = 0; + EPwm6TimerIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-6 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-6 + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx4 = PWM4_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx5 = PWM5_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx6 = PWM6_INT_ENABLE; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + for(i=1;i<=10;i++) + {} + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // Setup Sync + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // Allow each timer to be sync'ed + + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + EPwm4Regs.TBPHS.half.TBPHS = 400; + EPwm5Regs.TBPHS.half.TBPHS = 500; + EPwm6Regs.TBPHS.half.TBPHS = 600; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EPwm4Regs.TBPRD = PWM4_TIMER_TBPRD; + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm4Regs.ETSEL.bit.INTEN = PWM4_INT_ENABLE; // Enable INT + EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm5Regs.TBPRD = PWM5_TIMER_TBPRD; + EPwm5Regs.TBCTL.bit.CTRMODE= TB_COUNT_UP; // Count up + EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm5Regs.ETSEL.bit.INTEN = PWM5_INT_ENABLE; // Enable INT + EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm6Regs.TBPRD = PWM6_TIMER_TBPRD; + EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm6Regs.ETSEL.bit.INTEN = PWM6_INT_ENABLE; // Enable INT + EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; + + +} + + +// Interrupt routines uses in this example: +interrupt void epwm1_timer_isr(void) +{ + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_timer_isr(void) +{ + EPwm3TimerIntCount++; + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm4_timer_isr(void) +{ + EPwm4TimerIntCount++; + + // Clear INT flag for this timer + EPwm4Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm5_timer_isr(void) +{ + EPwm5TimerIntCount++; + + // Clear INT flag for this timer + EPwm5Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm6_timer_isr(void) +{ + EPwm6TimerIntCount++; + + // Clear INT flag for this timer + EPwm6Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel new file mode 100644 index 0000000..43d8f17 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel @@ -0,0 +1,47 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:37 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM Interrupt Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmTimerInt.pjt"); + GEL_ProjectBuild("Example_2833xEPwmTimerInt.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmTimerInt.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount",,"PWM1 ISR Count"); + GEL_WatchAdd("EPwm2TimerIntCount",,"PWM2 ISR Count"); + GEL_WatchAdd("EPwm3TimerIntCount",,"PWM3 ISR Count"); + GEL_WatchAdd("EPwm4TimerIntCount",,"PWM4 ISR Count"); + GEL_WatchAdd("EPwm5TimerIntCount",,"PWM5 ISR Count"); + GEL_WatchAdd("EPwm6TimerIntCount",,"PWM6 ISR Count"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + GEL_WatchAdd("EPwm5Regs,x"); + GEL_WatchAdd("EPwm6Regs,x"); +} diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt new file mode 100644 index 0000000..6e0819d --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmTimerInt.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmTimerInt.map" -o".\Debug\Example_2833xEPwmTimerInt.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c new file mode 100644 index 0000000..1415e49 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c @@ -0,0 +1,305 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:42 $ +//########################################################################### +// +// FILE: Example_2833xEpwmTripZone.c +// +// TITLE: Check PWM Trip Zone Test +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Initially tie TZ1 (GPIO12) and TZ2 (GPIO13) high. +// +// During the test, monitor ePWM1 or ePWM2 outputs +// on a scope Pull TZ1 or TZ2 low to see the effect. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// ePWM1 will react as a 1 shot trip +// +// ePWM2 will react as a cycle by cycle trip and will be +// cleared if TZ1 and TZ2 are both pulled back high. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1 and ePWM2 +// +// 2 Examples are included: +// * ePWM1 has TZ1 and TZ2 as one shot trip sources +// * ePWM2 has TZ1 and TZ2 as cycle by cycle trip sources +// +// Each ePWM is configured to interrupt on the 3rd zero event +// when this happens the deadband is modified such that +// 0 <= DB <= DB_MAX. That is, the deadband will move up and +// down between 0 and the maximum value. +// +// +// View the EPWM1A/B, EPWM2A/B waveforms +// via an oscilloscope to see the effect of TZ1 and TZ2 +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +interrupt void epwm1_tzint_isr(void); +interrupt void epwm2_tzint_isr(void); + + +// Global variables used in this example +Uint32 EPwm1TZIntCount; +Uint32 EPwm2TZIntCount; + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, and TZ pins + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitTzGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_TZINT = &epwm1_tzint_isr; + PieVectTable.EPWM2_TZINT = &epwm2_tzint_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts +// Initalize counters: + EPwm1TZIntCount = 0; + EPwm2TZIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT2; + +// Enable EPWM INTn in the PIE: Group 2 interrupt 1-3 + PieCtrlRegs.PIEIER2.bit.INTx1 = 1; + PieCtrlRegs.PIEIER2.bit.INTx2 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_tzint_isr(void) +{ + EPwm1TZIntCount++; + +// Leave these flags set so we only take this +// interrupt once +// +// EALLOW; +// EPwm1Regs.TZCLR.bit.OST = 1; +// EPwm1Regs.TZCLR.bit.INT = 1; +// EDIS; + + // Acknowledge this interrupt to receive more interrupts from group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + +} + +interrupt void epwm2_tzint_isr(void) +{ + + EPwm2TZIntCount++; + +// Clear the flags - we will continue to take +// this interrupt until the TZ pin goes high +// + EALLOW; + EPwm2Regs.TZCLR.bit.CBC = 1; + EPwm2Regs.TZCLR.bit.INT = 1; + EDIS; + + // Acknowledge this interrupt to receive more interrupts from group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + +} + + +void InitEPwm1Example() +{ + // Enable TZ1 and TZ2 as one shot trip sources + EALLOW; + EPwm1Regs.TZSEL.bit.OSHT1 = 1; + EPwm1Regs.TZSEL.bit.OSHT2 = 1; + + // What do we want the TZ1 and TZ2 to do? + EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // Enable TZ interrupt + EPwm1Regs.TZEINT.bit.OST = 1; + EDIS; + + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Setup compare + EPwm1Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; + +} + + +void InitEPwm2Example() +{ + + // Enable TZ1 and TZ2 as one cycle-by-cycle trip sources + EALLOW; + EPwm2Regs.TZSEL.bit.CBC1 = 1; + EPwm2Regs.TZSEL.bit.CBC2 = 1; + + // What do we want the TZ1 and TZ2 to do? + EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // Enable TZ interrupt + EPwm2Regs.TZEINT.bit.CBC = 1; + EDIS; + + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope + + // Setup compare + EPwm2Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel new file mode 100644 index 0000000..a59442b --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:58 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM TripZone" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmTripZone.pjt"); + GEL_ProjectBuild("Example_2833xEPwmTripZone.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmTripZone.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt new file mode 100644 index 0000000..543de56 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmTripZone.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmTripZone.map" -o".\Debug\Example_2833xEPwmTripZone.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwmDeadBand.map" -o".\Release\Example_2833xEPwmTripZone.out" -x + diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c new file mode 100644 index 0000000..33b153a --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c @@ -0,0 +1,490 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:47 $ +//########################################################################### +// +// FILE: Example_2833xEPwm3UpAQ.c +// +// TITLE: Action Qualifier Module Upcount mode. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor the ePWM1 - ePWM3 pins on a oscilloscope as +// described below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2, ePWM3 to produce an +// waveform with independant modulation on EPWMxA and +// EPWMxB. +// +// The compare values CMPA and CMPB are modified within the ePWM's ISR +// +// The TB counter is in upmode for this example. +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +}EPWM_INFO; + + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// Global variables used in this example +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// Configure the period for each timer +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + + +// To keep track of which way the compare value is moving +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + + + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_isr(void) +{ + // Update the CMPA and CMPB values + update_compare(&epwm1_info); + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +interrupt void epwm2_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm2_info); + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm3_info); + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +void InitEPwm1Example() +{ + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // Setup shadow register load on ZERO + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value + + // Set actions + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count + + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count + + // Interrupt where we will change the Compare Values + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & CMPB + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; + +} + + +void InitEPwm2Example() +{ + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // Setup shadow register load on ZERO + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value + + // Set actions + EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + + EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on Period + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2B on event B, up count + + // Interrupt where we will change the Compare Values + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; // Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; + +} + + +void InitEPwm3Example(void) +{ + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadow register load on ZERO + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // Set Actions + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on event B, up count + EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Clear PWM3A on event B, up count + + EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE; // Toggle EPWM3B on Zero + + // Interrupt where we will change the Compare Values + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Start by increasing the compare A and decreasing compare B + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; + // Start the cout at 0 + epwm3_info.EPwmTimerIntCount = 0; + epwm3_info.EPwmRegHandle = &EPwm3Regs; + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; +} + + +void update_compare(EPWM_INFO *epwm_info) +{ + + + // Every 10'th interrupt, change the CMPA/CMPB values + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // If we were increasing CMPA, check to see if + // we reached the max value. If not, increase CMPA + // else, change directions and decrease CMPA + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were decreasing CMPA, check to see if + // we reached the min value. If not, decrease CMPA + // else, change directions and increase CMPA + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were increasing CMPB, check to see if + // we reached the max value. If not, increase CMPB + // else, change directions and decrease CMPB + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // If we were decreasing CMPB, check to see if + // we reached the min value. If not, decrease CMPB + // else, change directions and increase CMPB + + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel new file mode 100644 index 0000000..6ac8e2c --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel @@ -0,0 +1,41 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:14:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM UP AQ" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmUpAQ.pjt"); + GEL_ProjectBuild("Example_2833xEPwmUpAQ.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmUpAQ.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt new file mode 100644 index 0000000..45a227e --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmUpAQ.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\Debug" -fs"C:\tidcs\c28\DSP2833x\006\DSP2833x_examples\epwm_asymmetic_aq\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmUpAQ.map" -o".\Debug\Example_2833xEPwmUpAQ.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEPwmUpAQ.out" -x + diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c new file mode 100644 index 0000000..6ccdbb7 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c @@ -0,0 +1,499 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:53 $ +//########################################################################### +// +// FILE: Example_2833xEPwmUpDownAQ.c +// +// TITLE: Action Qualifier Module - Using up/down count +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM3 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2, ePWM3 to produce an +// waveform with independant modulation on EPWMxA and +// EPWMxB. +// +// The compare values CMPA and CMPB are modified within the ePWM's ISR +// +// The TB counter is in up/down count mode for this example. +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +}EPWM_INFO; + + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// Global variables used in this example +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// Configure the period for each timer +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + +// To keep track of which way the compare value is moving +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + + +interrupt void epwm1_isr(void) +{ + // Update the CMPA and CMPB values + update_compare(&epwm1_info); + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +interrupt void epwm2_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm2_info); + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm3_info); + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +void InitEPwm1Example() +{ + + // Setup TBCLK + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Set Compare values + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value + + // Setup counter mode + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadowing + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count + + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count + EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count + + // Interrupt where we will change the Compare Values + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; + +} + + +void InitEPwm2Example() +{ + + + // Setup TBCLK + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Set Compare values + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value + + // Setup counter mode + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadowing + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + EPwm2Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM2A on event B, down count + + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Clear PWM2B on zero + EPwm2Regs.AQCTLB.bit.PRD = AQ_SET ; // Set PWM2B on period + + // Interrupt where we will change the Compare Values + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_UP; // increasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; // Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; + +} + +void InitEPwm3Example(void) +{ + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up/down + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadow register load on ZERO + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // Set Actions + EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM3A on period + EPwm3Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM3A on event B, down count + + EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM3A on period + EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM3A on event A, up count + + // Interrupt where we will change the Compare Values + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + epwm3_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm3_info.EPwmRegHandle = &EPwm3Regs; // Set the pointer to the ePWM module + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; + +} + + + +void update_compare(EPWM_INFO *epwm_info) +{ + + + // Every 10'th interrupt, change the CMPA/CMPB values + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // If we were increasing CMPA, check to see if + // we reached the max value. If not, increase CMPA + // else, change directions and decrease CMPA + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were decreasing CMPA, check to see if + // we reached the min value. If not, decrease CMPA + // else, change directions and increase CMPA + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were increasing CMPB, check to see if + // we reached the max value. If not, increase CMPB + // else, change directions and decrease CMPB + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // If we were decreasing CMPB, check to see if + // we reached the min value. If not, decrease CMPB + // else, change directions and increase CMPB + + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel new file mode 100644 index 0000000..017de80 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:14:28 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM UpDown AQ" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmUpDownAQ.pjt"); + GEL_ProjectBuild("Example_2833xEPwmUpDownAQ.pjt"); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmUpDownAQ.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt new file mode 100644 index 0000000..56449fe --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmUpDownAQ.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\Debug" -fs"C:\tidcs\c28\DSP2833x\006\DSP2833x_examples\epwm_Symmetric_aq\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmUpDownAQ.map" -o".\Debug\Example_2833xEPwmUpDownAQ.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEPwmUpDownAQ.out" -x + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c new file mode 100644 index 0000000..443b1b7 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c @@ -0,0 +1,178 @@ +// TI File $Revision: /main/12 $ +// Checkin $Date: July 10, 2008 11:07:26 $ +//########################################################################### +// +// FILE: Example_2833xEqep_freqcal.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Test requires the following hardware connections +// +// GPIO20/EQEP1A <- External input - connect to GPIO0/EPWM1A +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This test will provide frequency measurement using capture unit (freqhz_pr) +// and unit time out (freqhz_fr). The EPWM1A frequency will be measured by the EQEP. +// +// By default, EPWM1A is configured to generate a frequency of 5 kHz - measured +// frequency found in freqhz_pr and freqhz_fr should be 5000. +// +// See DESCRIPTION in Example_freqcal.c for more details on the frequency calculation +// performed in this example. +// +// In addition to this file, the following files must be included in this project: +// Example_freqcal.c - includes all eQEP functions +// Example_EPwmSetup.c - sets up EPWM1A for use with this example +// Example_freqcalh - includes initialization values for frequency structure. +// +// * Maximum frequency is configured to 10Khz (BaseFreq) +// * Minimum frequency is assumed at 50Hz for capture pre-scalar selection +// +// SPEED_FR: High Frequency Measurement is obtained by counting the external input pulses +// for 10ms (unit timer set to 100Hz). +// +// SPEED_FR = { (Count Delta)/10ms } +// +// +// SPEED_PR: Low Frequency Measurement is obtained by measuring time period of input edges. +// Time measurement is averaged over 64edges for better results and +// capture unit performs the time measurement using pre-scaled SYSCLK +// +// Note that pre-scaler for capture unit clock is selected such that +// capture timer does not overflow at the required minimum frequency +// +// This example runs forever until the user stops it. +// +// +// Watch Variables: freq.freqhz_fr - Frequency measurement using position counter/unit time out +// freq.freqhz_pr - Frequency measurement using capture unit +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +void EPwmSetup(void); +interrupt void prdTick(void); + +FREQCAL freq=FREQCAL_DEFAULTS; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Only init the GPIO for EQep1 and EPwm1 in this case +// This function is found in DSP2833x_EQep.c + InitEQep1Gpio(); + InitEPwm1Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// Example specific ePWM setup. This function is found +// in Example_EPwmSetup.c + EPwmSetup(); + +// Step 5. User specific code, enable interrupts: +// Enable CPU INT1 which is connected to CPU-Timer 0: + IER |= M_INT3; + +// Enable TINT0 in the PIE: Group 3 interrupt 1 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + freq.init(&freq); // Initializes eQEP for frequency calculation in + // FREQCAL_Init(void)function in Example_EPwmSetup.c + for(;;) + { + } + +} + +interrupt void prdTick(void) // Interrupts once per ePWM period +{ + freq.calc(&freq); // Checks for event and calculates frequency in FREQCAL_Calc(FREQCAL *p) + // function in Example_EPwmSetup.c + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel new file mode 100644 index 0000000..e76a9e2 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:14:43 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// projectn. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eQEP Frequency Calc" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEqep_freqcal.pjt"); + GEL_ProjectBuild("Example_2833xEqep_freqcal.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEqep_freqcal.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("freq.freqhz_fr",,""); + GEL_WatchAdd("freq.freqhz_pr",,""); + GEL_WatchAdd("EQep1Regs,x"); +} diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt new file mode 100644 index 0000000..46676a4 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt @@ -0,0 +1,49 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EQep.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="..\..\DSP2833x_common\lib\IQmath_fpu32.lib" +Source="Example_2833xEqep_freqcal.c" +Source="Example_EPwmSetup.c" +Source="Example_freqcal.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Debug" -i".." -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -i"..\..\DSP2833x_common\lib" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEqep_freqcal.map" -o".\Debug\Example_2833xEqep_freqcal.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEqep_freqcal.out" -x \ No newline at end of file diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c b/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c new file mode 100644 index 0000000..9f5aa7f --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c @@ -0,0 +1,76 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:03 $ +//########################################################################### +// +// FILE: Example_EpwmSetup.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file contains source for the ePWM initialization for the +// freq calculation module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif +#define PWM_CLK 5e3 // If diff freq. desired, change freq here. +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // Up-down cnt, timebase = SYSCLKOUT + + +void EPwmSetup() +{ + InitEPwm1Gpio(); + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS=0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // Immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA =SP/2; + EPwm1Regs.CMPB=0; + + EPwm1Regs.AQCTLA.all=0x60; // EPWMxA = 1 when CTR=CMPA and counter inc + // EPWMxA = 0 when CTR=CMPA and counter dec + EPwm1Regs.AQCTLB.all=0; + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.DBCTL.all=0xb; // EPWMxB is inverted + EPwm1Regs.DBRED=0; + EPwm1Regs.DBFED=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=9; // Interrupt when TBCTR = 0x0000 + EPwm1Regs.ETPS.all=1; // Interrupt on first event + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; + +} + + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c new file mode 100644 index 0000000..500705e --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c @@ -0,0 +1,186 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:07 $ +//########################################################################### +// +// FILE: Example_freqcal.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file includes the EQEP initialization and frequency calcuation +// functions called by Example_2833xEqep_freqcal.c. The frequency calculation +// steps performed by FREQCAL_Calc()at SYSCLKOUT = 150 MHz and 100 MHz are +// described below: +// +// For 150 MHz Operation: +// ---------------------- +// +// 1. This program calculates: **freqhz_fr** +// freqhz_fr or v = (x2-x1)/T - Equation 1 +// +// If max/base freq = 10kHz: 10kHz = (x2-x1)/(2/100Hz) - Equation 2 +// max (x2-x1) = 200 counts = freqScaler_fr +// Note: T = 2/100Hz. 2 is from (x2-x1)/2 - because QPOSCNT counts 2 edges per cycle +// (rising and falling) +// +// If both sides of Equation 2 are divided by 10 kHz, then: +// 1 = (x2-x1)/[10kHz*(2/100Hz)] where [10kHz* (2/100Hz)] = 200 +// Because (x2-x1) must be <200 (max), +// (x2-x1)/200 < 1 for all frequencies less than max +// freq_fr = (x2-x1)/200 or (x2-x1)/[10kHz*(2/100Hz)] - Equation 3 +// +// To get back to original velocity equation, Equation 1, multiply Equation 3 by 10 kHz +// freqhz_fr (or velocity) = 10kHz*(x2-x1)/[10kHz*(2/100Hz)] +// = (x2-x1)/(2/100Hz) - Final equation +// +// 2. min freq = 1 count/(2/100Hz) = 50 Hz +// +// 3. **freqhz_pr** +// freqhz_pr or v = X/(t2-t1) - Equation 4 +// +// If max/base freq = 10kHz: 10kHz = (4/2)/T = 4/2T +// where 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) +// 2 = divide by 2 because QPOSCNT counts 2 edges per cycle (rising and falling) +// T = time in seconds +// = t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and +// 1 QCAPCLK cycle = 1/(150MHz/128) +// = QCPRDLAT +// +// So: 10 kHz = 4(150MHz/128)/2(t2-t1) +// t2-t1 = 4(150MHz/128)/(10kHz*2) = (150MHz/128)/(2*10kHz/4) - Equation 5 +// = 234 QCAPCLK cycles = maximum (t2-t1) = freqScaler_pr +// +// Divide both sides by (t2-t1), and: +// 1 = 234/(t2-t1) = [150MHz/128)/(2*10kHz/4)]/(t2-t1) +// Because (t2-t1) must be <234 (max). +// 234/(t2-t1) < 1 for all frequencies less than max +// freq_pr = 234/(t2-t1) or [150MHz/128)/(2*10kHz/4)]/(t2-t1) - Equation 6 +// Now within velocity limits, to get back to original velocity equation, Equation 1, +// multiply Equation 6 by 10 kHz: +// freqhz_fr (or velocity) = 10kHz*[150MHz/128)/(2*10kHz/4)]/(t2-t1) +// = (105MHz/128)*4/[2(t2-t1)] +// or 4/[2*(t2-t1)(QCPRDLAT)] - Final Equation +// +// +// For 100 MHz Operation: +// ---------------------- +// +// The same calculations as above are performed, but with 100 MHz +// instead of 150MHz when calculating freqhz_pr, and at UPPS of 8 instead of 4. +// The value for freqScaler_pr becomes: (100MHz/128)/(2*10kHz/8) = 313 +// More detailed calculation results can be found in the Example_freqcal.xls +// spreadsheet included in the example folder. +// +// +// This file contains source for the freq calculation module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +void FREQCAL_Init(void) +{ + #if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100MHz SYSCLKOUT + #endif + + EQep1Regs.QDECCTL.bit.QSRC=2; // Up count mode (freq. measurement) + EQep1Regs.QDECCTL.bit.XCR=0; // 2x resolution (cnt falling and rising edges) + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + EQep1Regs.QEPCTL.bit.PCRM=00; // QPOSCNT reset on index evnt + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timer Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + + #if (CPU_FRQ_150MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=2; // 1/4 for unit position at 150MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=3; // 1/8 for unit position at 100MHz SYSCLKOUT + #endif + + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable + +} + +void FREQCAL_Calc(FREQCAL *p) +{ + unsigned long tmp; + _iq newp,oldp; + + +//**** Freq Calcultation using QEP position counter ****// +// Check unit Time out-event for speed calculation: +// Unit Timer is configured for 100Hz in INIT function + +// For a more detailed explanation of the calculation, read +// the description at the top of this file + + if(EQep1Regs.QFLG.bit.UTO==1) // Unit Timeout event + { + /** Differentiator **/ + newp=EQep1Regs.QPOSLAT; // Latched POSCNT value + oldp=p->oldpos; + + if (newp>oldp) + tmp = newp - oldp; // x2-x1 in v=(x2-x1)/T equation + else + tmp = (0xFFFFFFFF-oldp)+newp; + + p->freq_fr = _IQdiv(tmp,p->freqScaler_fr); // p->freq_fr = (x2-x1)/(T*10KHz) + tmp=p->freq_fr; + + if (tmp>=_IQ(1)) // is freq greater than max freq (10KHz for this example)? + p->freq_fr = _IQ(1); + else + p->freq_fr = tmp; + + p->freqhz_fr = _IQmpy(p->BaseFreq,p->freq_fr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_fr = (p->freq_fr)*10kHz = (x2-x1)/T + + // Update position counter + p->oldpos = newp; + //======================================= + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + +//**** Freq Calcultation using QEP capture counter ****// + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit Position Event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + tmp=(unsigned long)EQep1Regs.QCPRDLAT; + else // Capture overflow, saturate the result + tmp=0xFFFF; + + p->freq_pr = _IQdiv(p->freqScaler_pr,tmp); // p->freq_pr = X/[(t2-t1)*10KHz] + tmp=p->freq_pr; + + if (tmp>_IQ(1)) + p->freq_pr = _IQ(1); + else + p->freq_pr = tmp; + + p->freqhz_pr = _IQmpy(p->BaseFreq,p->freq_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_pr =( p->freq_pr)*10kHz = X/(t2-t1) + EQep1Regs.QEPSTS.all=0x88; // Clear Unit position event flag + // Clear overflow error flag + } + + +} + + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h new file mode 100644 index 0000000..874e66f --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h @@ -0,0 +1,112 @@ +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:14:59 $ +//########################################################################### +// +// FILE: Example_freqcal.h +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef __FREQCAL__ +#define __FREQCAL__ + +#include "IQmathLib.h" // Include header for IQmath library +/*----------------------------------------------------------------------------- +Define the structure of the FREQCAL Object +-----------------------------------------------------------------------------*/ +typedef struct { + Uint32 freqScaler_pr; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) - independently with global Q + Uint32 freqScaler_fr; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) - independently with global Q + Uint32 BaseFreq; // Parameter : Maximum Freq + _iq freq_pr; // Output : Freq in per-unit using capture unit + int32 freqhz_pr; // Output: Freq in Hz, measured using Capture unit + Uint32 oldpos; + _iq freq_fr; // Output : Freq in per-unit using position counter + int32 freqhz_fr; // Output: Freq in Hz, measured using Capture unit + void (*init)(); // Pointer to the init funcion + void (*calc)(); // Pointer to the calc funtion + } FREQCAL; + +/*----------------------------------------------------------------------------- +Define a QEP_handle +-----------------------------------------------------------------------------*/ +typedef FREQCAL *FREQCAL_handle; + +/*----------------------------------------------------------------------------- +Default initializer for the FREQCAL Object. +-----------------------------------------------------------------------------*/ + + +#if (CPU_FRQ_150MHZ) + #define FREQCAL_DEFAULTS {\ + 234,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define FREQCAL_DEFAULTS {\ + 313,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif + +/*----------------------------------------------------------------------------- +Prototypes for the functions in Example_freqcal.c +-----------------------------------------------------------------------------*/ +void FREQCAL_Init(void); +void FREQCAL_Calc(FREQCAL_handle); + +#endif /* __FREQCAL__ */ + +/* Notes: + +For 150 MHz Operation: +---------------------- +1. freqScaler_fr + v = (x2-x1)/T - Equation 1 + + If max/base freq = 10kHz: 10kHz = (x2-x1)/(2/100Hz) - Equation 2 + max (x2-x1) = 200 counts = freqScaler_fr + Note: T = 2/100Hz. 2 is from (x2-x1)/2 - because QPOSCNT counts 2 edges per cycle + (rising and falling) + freqhz_fr = 200 default + +2. min freq = 1 count/(2/100Hz) = 50 Hz + +3. freqScaler_pr + v = X/(t2-t1) - Equation 4 + + If max/base freq = 10kHz: 10kHz = 8/(2T) + where 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) + T = time in seconds = t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and + 1 QCAPCLK cycle = 1/(150MHz/128) + = QCPRDLAT + So: 10 kHz = 4(150MHz/128)/2(t2-t1) + t2-t1 = 4(150MHz/128)/(10kHz*2) = (150MHz/128)/(2*10kHz/4) - Equation 5 + = 234 seconds = maximum (t2-t1) = freqScaler_pr + freqhz_pr = 234 default + + +For 100 MHz Operation: +---------------------- + +The same calculations as above are performed, but with 100 MHz +instead of 150MHz when calculation freqhr_pr, and at UPPS of 8 instead of 4. +The value for freqScaler_pr becomes: (100MHz/128)/(2*10kHz/8) = 313 +More detailed calculation results can be found in the Example_freqcal.xls +spreadsheet included in the example folder. + +*/ diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.xls b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.xls new file mode 100644 index 0000000..a7128d2 Binary files /dev/null and b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.xls differ diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c new file mode 100644 index 0000000..9475939 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c @@ -0,0 +1,201 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: July 10, 2008 11:06:28 $ +//########################################################################### +// +// FILE: Example_2833xEqep_pos_speed_.c +// +// TITLE: EQEP Speed and Position measurement +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Test requires the following hardware connections from EPWM1 and +// GPIO pins (simulating QEP sensor) to QEP peripheral +// +// GPIO20/EQEP1A <- GPIO0/EPWM1A (simulates EQEP Phase A signal) +// GPIO21/EQEP1B <- GPIO1/EPWM1B (simulates EQEP Phase B signal) +// GPIO23/EQEP1I <- GPIO4 (simulates EQEP Index Signal) +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This test will provide position measurement, speed measurement using the capture unit, and +// speed measurement using unit time out. This example uses the IQMath library. It is used +// merely to simplify high-precision calculations. +// +// See DESCRIPTION in Example_posspeed.c for more details on the calculations +// performed in this example. +// +// In addition to this file, the following files must be included in this project: +// Example_posspeed.c - includes all eQEP functions +// Example_EPwmSetup.c - sets up EPWM1A and EPWM1B as simulated QA and QB encoder signals +// Example_posspeed.h - includes initialization values for pos and speed structure +// +// Notes: +// * Maximum speed is configured to 6000rpm(BaseRpm) +// * Minimum speed is assumed at 10rpm for capture pre-scalar selection +// * Pole pair is configured to 2 (pole_pairs) +// * QEP Encoder resolution is configured to 4000counts/revolution (mech_scaler) +// which means: 4000/4 = 1000 line/revolution quadrature encoder (simulated by EPWM1) +// * EPWM1 (simulating QEP encoder signals) is configured for 5kHz frequency or 300 rpm +// (=4*5000 cnts/sec * 60 sec/min)/4000 cnts/rev) +// * 300 rpm EPWM1 speed will be measured by EQEP. +// +// SPEEDRPM_FR: High Speed Measurement is obtained by counting the QEP input pulses +// for 10ms (unit timer set to 100Hz). +// +// SPEEDRPM_FR = { (Position Delta)/10ms } * 60 rpm +// +// +// SPEEDRPM_PR: Low Speed Measurement is obtained by measuring time period of QEP edges. +// Time measurement is averaged over 64edges for better results and +// capture unit performs the time measurement using pre-scaled SYSCLK +// +// Note that pre-scaler for capture unit clock is selected such that +// capture timer does not overflow at the required minimum RPM speed +// +// Watch Variables: qep_posspeed.SpeedRpm_fr - Speed meas. in rpm using QEP position counter +// qep_posspeed.SpeedRpm_pr - Speed meas. in rpm using capture unit +// qep_posspeed.theta_mech - Motor mechanical angle (Q15) +// qep_posspeed.theta_elec - Motor electrical angle (Q15) +// +//########################################################################### +// Original Author S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +void initEpwm(); +interrupt void prdTick(void); + +POSSPEED qep_posspeed=POSSPEED_DEFAULTS; +Uint16 Interrupt_Count = 0; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case only init GPIO for eQEP1 and ePWM1 +// This function is found in DSP2833x_EQep.c + InitEQep1Gpio(); + InitEPwm1Gpio(); + EALLOW; + GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; // GPIO4 as output simulates Index signal + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; // Normally low + EDIS; +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: + initEpwm(); // This function exists in Example_EPwmSetup.c + +// Step 5. User specific code, enable interrupts: +// Enable CPU INT1 which is connected to CPU-Timer 0: + IER |= M_INT3; + +// Enable TINT0 in the PIE: Group 3 interrupt 1 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + qep_posspeed.init(&qep_posspeed); + + for(;;) + { + } + +} + + +interrupt void prdTick(void) // EPWM1 Interrupts once every 4 QCLK counts (one period) +{ Uint16 i; + // Position and Speed measurement + qep_posspeed.calc(&qep_posspeed); + + // Control loop code for position control & Speed contol + Interrupt_Count++; + if (Interrupt_Count==1000) // Every 1000 interrupts(4000 QCLK counts or 1 rev.) + { + EALLOW; + GpioDataRegs.GPASET.bit.GPIO4 = 1; // Pulse Index signal (1 pulse/rev.) + for (i=0; i<700; i++){ + } + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; + Interrupt_Count = 0; // Reset count + EDIS; + } + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel new file mode 100644 index 0000000..eb40b6a --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:15:15 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eQEP Posspeed" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEqep_pos_speed.pjt"); + GEL_ProjectBuild("Example_2833xEqep_pos_speed.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEqep_pos_speed.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("qep_posspeed.SpeedRpm_fr",,""); + GEL_WatchAdd("qep_posspeed.SpeedRpm_pr",,""); + GEL_WatchAdd("qep_posspeed.theta_mech",,""); + GEL_WatchAdd("qep_posspeed.theta_elec",,""); + GEL_WatchAdd("EQep1Regs,x"); +} diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt new file mode 100644 index 0000000..1463168 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt @@ -0,0 +1,56 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EQep.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="..\..\DSP2833x_common\lib\IQmath_fpu32.lib" +Source="Example_2833xEqep_pos_speed.c" +Source="Example_EPwmSetup.c" +Source="Example_posspeed.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Debug" -i".." -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -i"..\..\DSP2833x_common\lib" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEqep_pos_speed.map" -o".\Debug\Example_2833xEqep_pos_speed.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEqep_pos_speed.out" -x + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c new file mode 100644 index 0000000..9d4ef5a --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c @@ -0,0 +1,69 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:18 $ +//########################################################################### +// +// FILE: Example_EpwmSetup.c +// +// TITLE: Pos speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file contains source for the ePWM initialization for the +// pos/speed module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif + +#define PWM_CLK 5e3 // 5kHz (300rpm) EPWM1 frequency. Freq. can be changed here +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // up-down count, timebase=SYSCLKOUT + + +void initEpwm() +{ + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS =0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA=SP/2; + EPwm1Regs.CMPB=0; + + EPwm1Regs.AQCTLA.all=0x60; // CTR=CMPA when inc->EPWM1A=1, when dec->EPWM1A=0 + EPwm1Regs.AQCTLB.all=0x09; // CTR=PRD ->EPWM1B=1, CTR=0 ->EPWM1B=0 + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=0x0A; // Interrupt on PRD + EPwm1Regs.ETPS.all=1; + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; +} + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c new file mode 100644 index 0000000..7b25307 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c @@ -0,0 +1,245 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:23 $ +//########################################################################### +// +// FILE: Example_posspeed.c +// +// TITLE: Pos/speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file includes the EQEP initialization and position and speed calcuation +// functions called by Example_2833xEqep_posspeed.c. The position and +// speed calculation steps performed by POSSPEED_Calc() at SYSCLKOUT = 150 MHz +// and 100 MHz are described in detail below: +// +// For 150 MHz Operation: +// ---------------------- +// +// 1. This program calculates: **theta_mech** +// +// theta_mech = QPOSCNT/mech_Scaler = QPOSCNT/4000, where 4000 is the number of +// counts in 1 revolution.(4000/4 = 1000 line/rev. quadrature encoder) +// +// 2. This program calculates: **theta_elec** +// +// theta_elec = (# pole pairs) * theta_mech = 2*QPOSCNT/4000 for this example +// +// 3. This program calculates: **SpeedRpm_fr** +// +// SpeedRpm_fr = [(x2-x1)/4000]/T - Equation 1 +// Note (x2-x1) = difference in number of QPOSCNT counts. Dividing (x2-x1) by +// 4000 gives position relative to Index in one revolution. +// If base RPM = 6000 rpm: 6000 rpm = [(x2-x1)/4000]/10ms - Equation 2 +// = [(x2-x1)/4000]/(.01s*1 min/60 sec) +// = [(x2-x1)/4000]/(1/6000) min +// max (x2-x1) = 4000 counts, or 1 revolution in 10 ms +// +// +// If both sides of Equation 2 are divided by 6000 rpm, then: +// 1 = [(x2-x1)/4000] rev./[(1/6000) min * 6000rpm] +// Because (x2-x1) must be <4000 (max) for QPOSCNT increment, +// (x2-x1)/4000 < 1 for CW rotation +// And because (x2-x1) must be >-4000 for QPOSCNT decrement, +// (x2-x1)/4000>-1 for CCW rotation +// speed_fr = [(x2-x1)/4000]/[(1/6000) min * 6000rpm] +// = (x2-x1)/4000 - Equation 3 +// +// To convert speed_fr to RPM, multiply Equation 3 by 6000 rpm +// SpeedRpm_fr = 6000rpm *(x2-x1)/4000 - Final Equation +// +// +// 2. **min rpm ** = selected at 10 rpm based on CCPS prescaler options available (128 is greatest) +// +// 3. **SpeedRpm_pr** +// SpeedRpm_pr = X/(t2-t1) - Equation 4 +// where X = QCAPCTL [UPPS]/4000 rev. (position relative to Index in 1 revolution) +// If max/base speed = 6000 rpm: 6000 = (32/4000)/[(t2-t1)/(150MHz/128)] +// where 32 = QCAPCTL [UPPS] (Unit timeout - once every 32 edges) +// 32/4000 = position in 1 revolution (position as a fraction of 1 revolution) +// t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and +// 1 QCAPCLK cycle = 1/(150MHz/128) +// = QCPRDLAT +// +// So: 6000 rpm = [32(150MHz/128)*60s/min]/[4000(t2-t1)] +// t2-t1 = [32(150MHz/128)*60 s/min]/(4000*6000rpm) - Equation 5 +// = 94 CAPCLK cycles = maximum (t2-t1) = SpeedScaler +// +// Divide both sides by (t2-t1), and: +// 1 = 94/(t2-t1) = [32(150MHz/128)*60 s/min]/(4000*6000rpm)]/(t2-t1) +// Because (t2-t1) must be < 94 for QPOSCNT increment: +// 94/(t2-t1) < 1 for CW rotation +// And because (t2-t1) must be >-94 for QPOSCNT decrement: +// 94/(t2-t1)> -1 for CCW rotation +// +// speed_pr = 94/(t2-t1) +// or [32(150MHz/128)*60 s/min]/(4000*6000rpm)]/(t2-t1) - Equation 6 +// +// To convert speed_pr to RPM: +// Multiply Equation 6 by 6000rpm: +// SpeedRpm_fr = 6000rpm * [32(150MHz/128)*60 s/min]/[4000*6000rpm*(t2-t1)] +// = [32(150MHz/128)*60 s/min]/[4000*(t2-t1)] +// or [(32/4000)rev * 60 s/min]/[(t2-t1)(QCPRDLAT)]- Final Equation +// +// +// For 100 MHz Operation: +// ---------------------- +// +// The same calculations as above are performed, but with 100 MHz +// instead of 150MHz when calculating SpeedRpm_pr. +// The value for freqScaler_pr becomes: [32*(100MHz/128)*60s/min]/(4000*6000rpm) = 63 +// More detailed calculation results can be found in the Example_freqcal.xls +// spreadsheet included in the example folder. +// +// +// +// This file contains source for the posspeed module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +void POSSPEED_Init(void) +{ + + #if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150 MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100 MHz SYSCLKOUT + #endif + + EQep1Regs.QDECCTL.bit.QSRC=00; // QEP quadrature count mode + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + EQep1Regs.QEPCTL.bit.PCRM=00; // PCRM=00 mode - QPOSCNT reset on index event + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timeout Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + + EQep1Regs.QCAPCTL.bit.UPPS=5; // 1/32 for unit position + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable + + +} + +void POSSPEED_Calc(POSSPEED *p) +{ + long tmp; + unsigned int pos16bval,temp1; + _iq Tmp1,newp,oldp; + +//**** Position calculation - mechanical and electrical motor angle ****// + p->DirectionQep = EQep1Regs.QEPSTS.bit.QDF; // Motor direction: 0=CCW/reverse, 1=CW/forward + + pos16bval=(unsigned int)EQep1Regs.QPOSCNT; // capture position once per QA/QB period + p->theta_raw = pos16bval+ p->cal_angle; // raw theta = current pos. + ang. offset from QA + + // The following lines calculate p->theta_mech ~= QPOSCNT/mech_scaler [current cnt/(total cnt in 1 rev.)] + // where mech_scaler = 4000 cnts/revolution + tmp = (long)((long)p->theta_raw*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + p->theta_mech = (int)(tmp>>11); // Q26 -> Q15 + p->theta_mech &= 0x7FFF; + + // The following lines calculate p->elec_mech + p->theta_elec = p->pole_pairs*p->theta_mech; // Q0*Q15 = Q15 + p->theta_elec &= 0x7FFF; + +// Check an index occurrence + if (EQep1Regs.QFLG.bit.IEL == 1) + { + p->index_sync_flag = 0x00F0; + EQep1Regs.QCLR.bit.IEL=1; // Clear interrupt flag + } + + + +//**** High Speed Calcultation using QEP Position counter ****// +// Check unit Time out-event for speed calculation: +// Unit Timer is configured for 100Hz in INIT function + + if(EQep1Regs.QFLG.bit.UTO==1) // If unit timeout (one 100Hz period) + { + /** Differentiator **/ + // The following lines calculate position = (x2-x1)/4000 (position in 1 revolution) + pos16bval=(unsigned int)EQep1Regs.QPOSLAT; // Latched POSCNT value + tmp = (long)((long)pos16bval*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + tmp = (int)(tmp>>11); // Q26 -> Q15 + tmp &= 0x7FFF; + newp=_IQ15toIQ(tmp); + oldp=p->oldpos; + + if (p->DirectionQep==0) // POSCNT is counting down + { + if (newp>oldp) + Tmp1 = - (_IQ(1) - newp + oldp); // x2-x1 should be negative + else + Tmp1 = newp -oldp; + } + else if (p->DirectionQep==1) // POSCNT is counting up + { + if (newp_IQ(1)) + p->Speed_fr = _IQ(1); + else if (Tmp1<_IQ(-1)) + p->Speed_fr = _IQ(-1); + else + p->Speed_fr = Tmp1; + + // Update the electrical angle + p->oldpos = newp; + + // Change motor speed from pu value to rpm value (Q15 -> Q0) + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + p->SpeedRpm_fr = _IQmpy(p->BaseRpm,p->Speed_fr); + //======================================= + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + +//**** Low-speed computation using QEP capture counter ****// + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit position event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + temp1=(unsigned long)EQep1Regs.QCPRDLAT; // temp1 = t2-t1 + else // Capture overflow, saturate the result + temp1=0xFFFF; + + p->Speed_pr = _IQdiv(p->SpeedScaler,temp1); // p->Speed_pr = p->SpeedScaler/temp1 + Tmp1=p->Speed_pr; + + if (Tmp1>_IQ(1)) + p->Speed_pr = _IQ(1); + else + p->Speed_pr = Tmp1; + + // Convert p->Speed_pr to RPM + if (p->DirectionQep==0) // Reverse direction = negative + p->SpeedRpm_pr = -_IQmpy(p->BaseRpm,p->Speed_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + else // Forward direction = positive + p->SpeedRpm_pr = _IQmpy(p->BaseRpm,p->Speed_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + + + EQep1Regs.QEPSTS.all=0x88; // Clear Unit position event flag + // Clear overflow error flag + } + + +} + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h new file mode 100644 index 0000000..14d1761 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h @@ -0,0 +1,85 @@ +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:15:33 $ +//########################################################################### +// +// FILE: Example_posspeed.h +// +// TITLE: Pos/speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef __POSSPEED__ +#define __POSSPEED__ + +#include "IQmathLib.h" // Include header for IQmath library +/*----------------------------------------------------------------------------- +Define the structure of the POSSPEED Object +-----------------------------------------------------------------------------*/ +typedef struct {int theta_elec; // Output: Motor Electrical angle (Q15) + int theta_mech; // Output: Motor Mechanical Angle (Q15) + int DirectionQep; // Output: Motor rotation direction (Q0) + int QEP_cnt_idx; // Variable: Encoder counter index (Q0) + int theta_raw; // Variable: Raw angle from Timer 2 (Q0) + int mech_scaler; // Parameter: 0.9999/total count, total count = 4000 (Q26) + int pole_pairs; // Parameter: Number of pole pairs (Q0) + int cal_angle; // Parameter: Raw angular offset between encoder and phase a (Q0) + int index_sync_flag; // Output: Index sync status (Q0) + + Uint32 SpeedScaler; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q speed (Q0) - independently with global Q + _iq Speed_pr; // Output : speed in per-unit + Uint32 BaseRpm; // Parameter : Scaler converting GLOBAL_Q speed to rpm (Q0) speed - independently with global Q + int32 SpeedRpm_pr; // Output : speed in r.p.m. (Q0) - independently with global Q + + _iq oldpos; // Input: Electrical angle (pu) + _iq Speed_fr; // Output : speed in per-unit + int32 SpeedRpm_fr; // Output : Speed in rpm (Q0) - independently with global Q + void (*init)(); // Pointer to the init funcion + void (*calc)(); // Pointer to the calc funtion + } POSSPEED; + +/*----------------------------------------------------------------------------- +Define a POSSPEED_handle +-----------------------------------------------------------------------------*/ +typedef POSSPEED *POSSPEED_handle; + +/*----------------------------------------------------------------------------- +Default initializer for the POSSPEED Object. +-----------------------------------------------------------------------------*/ + +#if (CPU_FRQ_150MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 94,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 63,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif + + +/*----------------------------------------------------------------------------- +Prototypes for the functions in posspeed.c +-----------------------------------------------------------------------------*/ +void POSSPEED_Init(void); +void POSSPEED_Calc(POSSPEED_handle); + +#endif /* __POSSPEED__ */ + + + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.xls b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.xls new file mode 100644 index 0000000..367b4e9 Binary files /dev/null and b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.xls differ diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c new file mode 100644 index 0000000..903a088 --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c @@ -0,0 +1,260 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: May 5, 2008 15:25:49 $ +//########################################################################### +// +// FILE: Example_2833xExternalInterrupt.c +// +// TITLE: DSP2833x External Interrupt test program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Connect GPIO30 to GPIO0. GPIO0 will be assigned to Xint1 +// Connect GPIO31 to GPIO1. GPIO1 will be assigned to XINT2 +// +// Monitor GPIO34 with an oscilloscope. GPIO34 will be high outside of the +// ISRs and low within each ISR. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program sets up GPIO0 as Xint1 and GPIO1 as XINT2. Two other +// GPIO signals are used to trigger the interrupt (GPIO30 triggers +// Xint1 and GPIO31 triggers XINT2). The user is required to +// externally connect these signals for the program to work +// properly. +// +// Xint1 input is synched to SYSCLKOUT +// XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each. +// +// GPIO34 will go high outside of the interrupts and low within the +// interrupts. This signal can be monitored on a scope. +// +// Each interrupt is fired in sequence - Xint1 first and then XINT2 +// +// +// Watch Variables: +// Xint1Count for the number of times through Xint1 interrupt +// Xint2Count for the number of times through XINT2 interrupt +// LoopCount for the number of times through the idle loop +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void xint1_isr(void); +interrupt void xint2_isr(void); + +// Global variables for this example +volatile Uint32 Xint1Count; +volatile Uint32 Xint2Count; +Uint32 LoopCount; + +#define DELAY 35.700L + +void main(void) +{ + Uint32 TempX1Count; + Uint32 TempX2Count; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &xint1_isr; + PieVectTable.XINT2 = &xint2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + +// Clear the counters + Xint1Count = 0; // Count Xint1 interrupts + Xint2Count = 0; // Count XINT2 interrupts + LoopCount = 0; // Count times through idle loop + +// Enable Xint1 and XINT2 in the PIE: Group 1 interrupt 4 & 5 +// Enable int1 which is connected to WAKEINT: + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Gropu 1 INT4 + PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable PIE Gropu 1 INT5 + IER |= M_INT1; // Enable CPU int1 + EINT; // Enable Global Interrupts + +// GPIO30 & GPIO31 are outputs, start GPIO30 high and GPIO31 low + EALLOW; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO30 = 1; // output + + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; // output + EDIS; + +// GPIO0 and GPIO1 are inputs + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 0; // Xint1 Synch to SYSCLKOUT only + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 2; // XINT2 Qual using 6 samples + GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0xFF; // Each sampling window is 510*SYSCLKOUT + EDIS; + +// GPIO0 is XINT1, GPIO1 is XINT2 + EALLOW; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Xint1 is GPIO0 + GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 1; // XINT2 is GPIO1 + EDIS; + +// Configure XINT1 + XIntruptRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt + XIntruptRegs.XINT2CR.bit.POLARITY = 1; // Rising edge interrupt + +// Enable XINT1 and XINT2 + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable Xint1 + XIntruptRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2 + + +// GPIO34 will go low inside each interrupt. Monitor this on a scope + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // output + EDIS; + +// Step 6. IDLE loop: + for(;;) + { + + TempX1Count = Xint1Count; + TempX2Count = Xint2Count; + + // Trigger both XINT1 + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + GpioDataRegs.GPACLEAR.bit.GPIO30 = 1; // Lower GPIO30, trigger Xint1 + while(Xint1Count == TempX1Count) {} + + // Trigger both XINT2 + + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + DELAY_US(DELAY); // Wait for Qual period + GpioDataRegs.GPASET.bit.GPIO31 = 1; // Raise GPIO31, trigger XINT2 + while(Xint2Count == TempX2Count) {} + + // Check that the counts were incremented properly and get ready + // to start over. + if(Xint1Count == TempX1Count+1 && Xint2Count == TempX2Count+1) + { + LoopCount++; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // raise GPIO30 + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // lower GPIO31 + } + else + { + asm(" ESTOP0"); // stop here + } + + } + + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + // If local ISRs are used, reassign vector addresses in vector table as + // shown in Step 5 + +interrupt void xint1_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint1Count++; + + // Acknowledge this interrupt to get more from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void xint2_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint2Count++; + + // Acknowledge this interrupt to get more from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel new file mode 100644 index 0000000..f2542a3 --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel @@ -0,0 +1,41 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:15:49 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ExternalInterrupt" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xExternalInterrupt.pjt"); + GEL_ProjectBuild("Example_2833xExternalInterrupt.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xExternalInterrupt.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("Xint1Count,x"); + GEL_WatchAdd("Xint2Count,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("XIntruptRegs,x"); + GEL_WatchAdd("GpioCtrlRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt new file mode 100644 index 0000000..0e88e0e --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xExternalInterrupt.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x\DSP2833x_examples\external_interrupt\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xExternalInterrupt.map" -o".\Debug\Example_2833xExternalInterrupt.out" -stack0x200 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xExternalInterrupt.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28332_Flash.gel b/v120/DSP2833x_examples/flash/Example_28332_Flash.gel new file mode 100644 index 0000000..d254c08 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28332_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:15:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28332 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28332_Flash.pjt"); + GEL_ProjectBuild("Example_28332_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28332_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt new file mode 100644 index 0000000..1d116ed --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28332.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28332_Flash.map" -o".\Debug\Example_28332_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28334_Flash.gel b/v120/DSP2833x_examples/flash/Example_28334_Flash.gel new file mode 100644 index 0000000..df91989 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28334_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:06 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28334 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28334_Flash.pjt"); + GEL_ProjectBuild("Example_28334_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28334_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt new file mode 100644 index 0000000..74faf44 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28334.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28334_Flash.map" -o".\Debug\Example_28334_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28335_Flash.gel b/v120/DSP2833x_examples/flash/Example_28335_Flash.gel new file mode 100644 index 0000000..daf0d95 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28335_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:14 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28335 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28335_Flash.pjt"); + GEL_ProjectBuild("Example_28335_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28335_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt new file mode 100644 index 0000000..766eeb9 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28335.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28335_Flash.map" -o".\Debug\Example_28335_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_2833xFlash.c b/v120/DSP2833x_examples/flash/Example_2833xFlash.c new file mode 100644 index 0000000..7e7d4db --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_2833xFlash.c @@ -0,0 +1,342 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:33 $ +//########################################################################### +// +// FILE: Example_2833xFlash.c +// +// TITLE: DSP2833x ePWM Timer Interrupt From Flash Example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to FLASH" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash <- "boot to Flash" +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example runs the ePWM interrupt example from flash. +// +// 1) Build the project +// 2) Flash the .out file into the device. +// 3) Set the hardware jumpers to boot to Flash +// 4) Use the included GEL file to load the project, symbols +// defined within the project and the variables into the watch +// window. +// +// Steps that were taken to convert the ePWM example from RAM +// to Flash execution: +// +// - Change the linker cmd file to reflect the flash memory map. +// - Make sure any initialized sections are mapped to Flash. +// In SDFlash utility this can be checked by the View->Coff/Hex +// status utility. Any section marked as "load" should be +// allocated to Flash. +// - Make sure there is a branch instruction from the entry to Flash +// at 0x33FFF6 to the beginning of code execution. This example +// uses the DSP2833x_CodeStartBranch.asm file to accomplish this. +// - Set boot mode Jumpers to "boot to Flash" +// - For best performance from the flash, modify the waitstates +// and enable the flash pipeline as shown in this example. +// Note: any code that manipulates the flash waitstate and pipeline +// control must be run from RAM. Thus these functions are located +// in their own memory section called ramfuncs. +// +// +// ePwm1 Interrupt will run from RAM and puts the flash into sleep mode +// ePwm2 Interrupt will run from RAM and puts the flash into standby mode +// ePWM3 Interrupt will run from FLASH +// +// As supplied: +// +// All timers have the same period +// The timers are started sync'ed +// An interrupt is taken on a zero event for each ePWM timer +// +// ePWM1: takes an interrupt every event +// ePWM2: takes an interrupt every 2nd event +// ePWM3: takes an interrupt every 3rd event +// +// Thus the Interrupt count for ePWM1, ePWM4-ePWM6 should be equal +// The interrupt count for ePWM2 should be about half that of ePWM1 +// and the interrupt count for ePWM3 should be about 1/3 that of ePWM1 +// +// Watch Variables: +// EPwm1TimerIntCount +// EPwm2TimerIntCount +// EPwm3TimerIntCount +// +// Toggle GPIO32 while in the background loop. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Configure which ePWM timer interrupts are enabled at the PIE level: +// 1 = enabled, 0 = disabled +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 + +// Configure the period for each timer +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF + +// Make this long enough so that we can see an LED toggle +#define DELAY 1000000L + +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped using +// the linker cmd file. +#pragma CODE_SECTION(epwm1_timer_isr, "ramfuncs"); +#pragma CODE_SECTION(epwm2_timer_isr, "ramfuncs"); + +// Prototype statements for functions found within this file. +interrupt void epwm1_timer_isr(void); +interrupt void epwm2_timer_isr(void); +interrupt void epwm3_timer_isr(void); +void InitEPwmTimer(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 LoopCount; + +// These are defined by the linker (see F28335.cmd) +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + +// Step 5. User specific code, enable interrupts: + +// Copy time critical code and Flash setup code to RAM +// This includes the following ISR functions: epwm1_timer_isr(), epwm2_timer_isr() +// epwm3_timer_isr and and InitFlash(); +// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart +// symbols are created by the linker. Refer to the F28335.cmd file. + MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); + +// Call Flash Initialization to setup flash waitstates +// This function must reside in RAM + InitFlash(); + +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + LoopCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + EDIS; + + for(;;) + { + // This loop will be interrupted, so the overall + // delay between pin toggles will be longer. + DELAY_US(DELAY); + LoopCount++; + GpioDataRegs.GPBTOGGLE.bit.GPIO32 = 1; + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // Setup Sync + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // Allow each timer to be sync'ed + + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; + + +} + +// This ISR MUST be executed from RAM as it will put the Flash into Sleep +// Interrupt routines uses in this example: +interrupt void epwm1_timer_isr(void) +{ + + // Put the Flash to sleep + FlashRegs.FPWR.bit.PWR = FLASH_SLEEP; + + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// This ISR MUST be executed from RAM as it will put the Flash into Standby +interrupt void epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // Put the Flash into standby + FlashRegs.FPWR.bit.PWR = FLASH_STANDBY; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_timer_isr(void) +{ + Uint16 i; + + EPwm3TimerIntCount++; + + // Short Delay to simulate some ISR Code + for(i = 1; i < 0x01FF; i++) {} + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU.c b/v120/DSP2833x_examples/fpu/Example_2833xFPU.c new file mode 100644 index 0000000..66654f2 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU.c @@ -0,0 +1,167 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 21, 2008 15:44:31 $ +//########################################################################### +// +// FILE: Example_2833xFPU.c +// +// TITLE: DSP2833x Device Getting Started Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// The code calculates two y=mx+b equations. The variables are all +// 32-bit floating-point. +// +// Two projects are supplied: +// +// Example_fpu_hardware.pjt (floating-point): +// +// If the Example_2833xFPU_hardware.pjt file is used then the compiler +// will generate floating point instructions to do these calculations. +// To compile the project for floating point, the following Build Options were used: +// 1. Project->Build Options-> Compiler Tab-> Advanced category: +// a. in textbox: compiler options -v28 --float_support=fpu32 are set +// b. OR the following is equivalent to "a.": pull-down menu next to +// "Floating Point Support"-> "fpu32" selected. +// 2. Project->Build Options-> Linker Tab-> Libraries category: +// a. runtime support library used is rts2800_fpu32.lib. +// 3. Not included in this example: If the project includes any other libraries, +// they must also be compiled with floating point instructions. +// +// Example_fpu_software.pjt (fixed-point emulates floating-point with software): +// +// If the Example_2833xFPU_software.pjt file is used, then the compiler +// will only used fixed point instructions. This means the runtime +// support library will be used to emulate floating point. +// This will also run on C28x devices without the floating point unit. +// To compile the project for fixed point, the following Build Options were used: +// 1. Project->Build Options-> Compiler Tab-> Advanced category: +// a. in textbox: compiler option --float_support=fpu32 is REMOVED +// -v28 should not be removed +// b. OR the following is equivalent to "a.": pull-down menu next to +// "Floating Point Support"-> "None" selected. +// 2. Project->Build Options-> Linker Tab-> Libraries category: +// a. runtime support library used is rts2800.lib or rts2800_ml.lib. +// 3. Not included in this example: If the project includes any other libraries, +// they must also be compiled with fixed point instructions. +// +// Watch Variables: +// y1 +// y2 +// FPU registers (optional) +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +float y1, y2; +float m1, m2; +float x1, x2; +float b1, b2; + + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + + +// Step 5. User specific code, enable interrupts: + +// +// Calculate two y=mx+b equations. + + y1 = 0; + y2 = 0; + m1 = .5; + m2 = .6; + x1 = 3.4; + x2 = 7.3; + b1 = 4.2; + b2 = 8.9; + + y1 = m1*x1 + b1; + y2 = m2*x2 + b2; + + + ESTOP0; // This is a software breakpoint +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel b/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel new file mode 100644 index 0000000..b6531eb --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel @@ -0,0 +1,50 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: August 29, 2007 14:07:24 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x FPU Example" + +hotmenu Load_and_Build_Fixed_Point_Project() +{ + GEL_ProjectLoad("Example_2833xFPU_software.pjt"); + GEL_ProjectBuild("Example_2833xFPU_software.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_and_Build_Floating_Point_Project() +{ + GEL_ProjectLoad("Example_2833xFPU_hardware.pjt"); + GEL_ProjectBuild("Example_2833xFPU_hardware.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Fixed_Point_Code() +{ + GEL_Load(".\\debug\\Example_2833xFPU_software.out"); + Setup_WatchWindow(); +} + +hotmenu Load_Floating_Point_Code() +{ + GEL_Load(".\\debug\\Example_2833xFPU_hardware.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("y1,f"); + GEL_WatchAdd("y2,f"); + All_FPU_Single_Precision_Regs(); +} diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt b/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt new file mode 100644 index 0000000..863f8f7 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFPU.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -al -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xFPU_hardware.map" -o".\Debug\Example_2833xFPU_hardware.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFPU_hardware.out" -x + diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt b/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt new file mode 100644 index 0000000..c4cdc70 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFPU.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xFPU_software.map" -o".\Debug\Example_2833xFPU_software.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_ml.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFPU_software.out" -x + diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c new file mode 100644 index 0000000..ff9c488 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c @@ -0,0 +1,458 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:38 $ +//########################################################################### +// +// FILE: Example_2833xGpioSetup.c +// +// TITLE: DSP2833x Device GPIO Setup +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Two different examples are included. Select the example +// to execute before compiling using the #define statements +// found at the top of the code. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// Configures the 2833x GPIO into two different configurations +// This code is verbose to illustrate how the GPIO could be setup. +// In a real application, lines of code can be combined for improved +// code size and efficency. +// +// This example only sets-up the GPIO.. nothing is actually done with +// the pins after setup. +// +// In general: +// +// All pullup resistors are enabled. For ePWMs this may not be desired. +// Input qual for communication ports (eCAN, SPI, SCI, I2C) is asynchronous +// Input qual for Trip pins (TZ) is asynchronous +// Input qual for eCAP and eQEP signals is synch to SYSCLKOUT +// Input qual for some I/O's and interrupts may have a sampling window +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Select the example to compile in. Only one example should be set as 1 +// the rest should be set as 0. + +#define EXAMPLE1 1 // Basic pinout configuration example +#define EXAMPLE2 0 // Communication pinout example + +// Prototype statements for functions found within this file. +void Gpio_setup1(void); +void Gpio_setup2(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. + // InitGpio(); Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + +#if EXAMPLE1 + + // This example is a basic pinout + Gpio_setup1(); + +#endif // - EXAMPLE1 + +#if EXAMPLE2 + + // This example is a communications pinout + Gpio_setup2(); + +#endif + +} + + +void Gpio_setup1(void) +{ + // Example 1: + // Basic Pinout. + // This basic pinout includes: + // PWM1-3, ECAP1, ECAP2, TZ1-TZ4, SPI-A, EQEP1, SCI-A, I2C + // and a number of I/O pins + + // These can be combined into single statements for improved + // code efficiency. + + // Enable PWM1-3 on GPIO0-GPIO5 + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // Enable an GPIO output on GPIO6, set it high + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // Enable eCAP1 on GPIO7 + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // Enable GPIO outputs on GPIO8 - GPIO11, set it high + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // Enable Trip Zone inputs on GPIO12 - GPIO15 + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13 + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // GPIO12 = TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // GPIO13 = TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // GPIO14 = TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // GPIO15 = TZ4 + + // Enable SPI-A on GPIO16 - GPIO19 + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // Enable EQEP1 on GPIO20 - GPIO23 + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // Enable eCAP1 on GPIO24 + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // Set input qualifcation period for GPIO25 & GPIO26 + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=2; // 6 samples + + // Make GPIO25 the input source for Xint1 + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // Make GPIO26 the input source for XINT2 + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; // Qualify GPIO27 by 2 OSCCLK + // cycles before waking the device + // from STANDBY + + // Enable SCI-A on GPIO28 - GPIO29 + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // Enable CAN-A on GPIO30 - GPIO31 + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + + // Enable I2C-A on GPIO32 - GPIO33 + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // Make GPIO34 an input + GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + EDIS; +} + +void Gpio_setup2(void) +{ + // Example 1: + // Communications Pinout. + // This basic communications pinout includes: + // PWM1-3, CAP1, CAP2, SPI-A, SPI-B, CAN-A, SCI-A and I2C + // and a number of I/O pins + + // Enable PWM1-3 on GPIO0-GPIO5 + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // Enable an GPIO output on GPIO6 + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // Enable eCAP1 on GPIO7 + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // Enable GPIO outputs on GPIO8 - GPIO11 + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioDataRegs.GPASET.bit.GPIO11 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // Enable SPI-B on GPIO12 - GPIO15 + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 (SPISIMOB) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO13 (SPISOMIB) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 (SPICLKB) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 (SPISTEB) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 = SPISIMOB + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 = SPISOMIB + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 = SPICLKB + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 = SPISTEB + + // Enable SPI-A on GPIO16 - GPIO19 + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 (SPIS0MIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 (SPISTEA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // Enable EQEP1 on GPIO20 - GPIO23 + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 (EQEP1I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // Enable eCAP1 on GPIO24 + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 (ECAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // Set input qualifcation period for GPIO25 & GPIO26 inputs + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=1; // 3 samples + + // Make GPIO25 the input source for Xint1 + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // Make GPIO26 the input source for XINT2 + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; // Qualify GPIO27 by 2 OSCCLK + // cycles before waking the device + // from STANDBY + + // Enable SCI-A on GPIO28 - GPIO29 + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // Enable CAN-A on GPIO30 - GPIO31 + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + // Enable I2C-A on GPIO32 - GPIO33 + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // Make GPIO34 an input + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + + EDIS; +} + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel new file mode 100644 index 0000000..84616d3 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel @@ -0,0 +1,35 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:35 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x GPIO Setup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xGpioSetup.pjt"); + GEL_ProjectBuild("Example_2833xGpioSetup.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xGpioSetup.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd(" GpioCtrlRegs,x"); +} diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt new file mode 100644 index 0000000..246125c --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xGpioSetup.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xGpioSetup.map" -o".\Debug\Example_2833xGpioSetup.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xGpioToggle.out" -x + diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c new file mode 100644 index 0000000..017a1f7 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c @@ -0,0 +1,245 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:42:43 $ +//########################################################################### +// +// FILE: Example_2833xGpioToggle.c +// +// TITLE: DSP2833x Device GPIO toggle test program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// ALL OF THE I/O'S TOGGLE IN THIS PROGRAM. MAKE SURE +// THIS WILL NOT DAMAGE YOUR HARDWARE BEFORE RUNNING THIS +// EXAMPLE. +// +// Monitor desired pins on an oscilloscope. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Three different examples are included. Select the example +// (data, set/clear or toggle) to execute before compiling using +// the #define statements found at the top of the code. +// +// +// Toggle all of the GPIO PORT pins +// +// The pins can be observed using Oscilloscope. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Select the example to compile in. Only one example should be set as 1 +// the rest should be set as 0. +#define EXAMPLE1 1 // Use DATA registers to toggle I/O's +#define EXAMPLE2 0 // Use SET/CLEAR registers to toggle I/O's +#define EXAMPLE3 0 // Use TOGGLE registers to toggle I/O's + + +// Prototype statements for functions found within this file. +void delay_loop(void); +void Gpio_select(void); +void Gpio_example1(void); +void Gpio_example2(void); +void Gpio_example3(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this example use the following configuration: + Gpio_select(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + +#if EXAMPLE1 + + // This example uses DATA registers to toggle I/O's + Gpio_example1(); + +#endif // - EXAMPLE1 + +#if EXAMPLE2 + + // This example uses SET/CLEAR registers to toggle I/O's + Gpio_example2(); + +#endif + +#if EXAMPLE3 + + // This example uses TOGGLE registers to toggle I/O's + Gpio_example3(); + +#endif + +} + +void delay_loop() +{ + short i; + for (i = 0; i < 1000; i++) {} +} + + +void Gpio_example1(void) +{ + // Example 1: + // Toggle I/Os using DATA registers + + for(;;) + { + GpioDataRegs.GPADAT.all =0xAAAAAAAA; + GpioDataRegs.GPBDAT.all =0x0000000A; + + delay_loop(); + + GpioDataRegs.GPADAT.all =0x55555555; + GpioDataRegs.GPBDAT.all =0x00000005; + + delay_loop(); + } +} + +void Gpio_example2(void) +{ + // Example 2: + // Toggle I/Os using SET/CLEAR registers + for(;;) + { + + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + delay_loop(); + + GpioDataRegs.GPACLEAR.all =0xAAAAAAAA; + GpioDataRegs.GPASET.all =0x55555555; + + GpioDataRegs.GPBCLEAR.all =0x0000000A; + GpioDataRegs.GPBSET.all =0x00000005; + + delay_loop(); + + } +} + +void Gpio_example3(void) +{ + // Example 2: + // Toggle I/Os using TOGGLE registers + + // Set pins to a known state + + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + // Use TOGGLE registers to flip the state of + // the pins. + // Any bit set to a 1 will flip state (toggle) + // Any bit set to a 0 will not toggle. + + for(;;) + { + GpioDataRegs.GPATOGGLE.all =0xFFFFFFFF; + GpioDataRegs.GPBTOGGLE.all =0x0000000F; + delay_loop(); + } +} + + + +void Gpio_select(void) +{ + + + EALLOW; + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX2.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + GpioCtrlRegs.GPBDIR.all = 0x0000000F; // All outputs + EDIS; + +} +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel new file mode 100644 index 0000000..5e49d74 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel @@ -0,0 +1,36 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:50 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x GPIO Toggle Test" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xGpioToggle.pjt"); + GEL_ProjectBuild("Example_2833xGpioToggle.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xGpioToggle.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("GpioDataRegs,x"); + GEL_WatchAdd("GpioCtrlRegs,x"); +} diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt new file mode 100644 index 0000000..ae80e72 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xGpioToggle.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xGpioToggle.map" -o".\Debug\Example_2833xGpioToggle.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xGpioToggle.out" -x + diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c new file mode 100644 index 0000000..66c2b43 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c @@ -0,0 +1,376 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: May 5, 2008 15:25:53 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM.c +// +// TITLE: DSP2833x Device HRPWM example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module +// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine edge movement +// due to HRPWM logic +// +// 1. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1A toggle low/high with MEP control on rising edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1B toggle low/high with NO HRPWM control +// +// 2. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2A toggle low/high with MEP control on rising edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2B toggle low/high with NO HRPWM control +// +// 3. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3A toggle as high/low with MEP control on falling edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3B toggle low/high with NO HRPWM control +// +// 4. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4A toggle as high/low with MEP control on falling edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4B toggle low/high with NO HRPWM control +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + + +// Declare your function prototypes here +//--------------------------------------------------------------- + +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// General System nets - Useful for debug +Uint16 i,j, DutyFine, n,update; + +Uint32 temp; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(10); // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(20); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(10); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(20); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + + { + + for(DutyFine =1; DutyFine <256 ;DutyFine ++) + { + + // Example, write to the HRPWM extension of CMPA + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + + // Example, 32-bit write to CMPA:CMPAHR + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + + for (i=0;i<10000;i++){} // Dummy delay between MEP changes + } + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm2Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel new file mode 100644 index 0000000..5ccf383 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel @@ -0,0 +1,42 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:09 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("DutyFine,x"); + GEL_WatchAdd("update,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + +} diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt new file mode 100644 index 0000000..b92acda --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt @@ -0,0 +1,51 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -cr -ecode_start -m".\Debug\Example_2833xHRPWM.map" -o".\Debug\Example_2833xHRPWM.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c new file mode 100644 index 0000000..9e092f6 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c @@ -0,0 +1,546 @@ +// TI File $Revision: /main/15 $ +// Checkin $Date: May 5, 2008 15:25:56 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO.c +// +// TITLE: DSP2833x Device HRPWM example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files, which include the +// SFO_TI_Build_fpu.lib (or SFO_TI_Build.lib for fixed-point) and SFO.h +// files required by this example. +// +// !!NOTE!! +// By default, this example project is configured for floating-point math. All +// included libraries must be pre-compiled for floating-point math. +// +// Therefore, SFO_TI_Build_fpu.lib (compiled for floating-point) is included in the +// project instead of the SFO_TI_Build.lib (compiled for fixed-point). +// +// To convert the example for fixed-point math, follow the instructions in sfo_readme.txt +// in the /doc directory of the header files and peripheral examples package. +// +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM2A is on GPIO2 +// EPWM3A is on GPIO4 +// EPWM4A is on GPIO6 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module. +// +// This example calls the following TI's MEP Scale Factor Optimizer (SFO) +// software library functions: +// +// void SFO_MepEn(int i); +// initialize MEP_Scalefactor[i] dynamically when HRPWM is in use. +// +// void SFO_MepDis(int i); +// initialize MEP_Scalefactor[i] when HRPWM is not used +// +// Where MEP_ScaleFactor[5] is a global array variable used by the SFO library +// +// This example is intended to explain the HRPWM capabilities. The code can be +// optimized for code efficiency. Refer to TI's Digital power application +// examples and TI Digital Power Supply software libraries for details. +// +// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine +// edge movement due to the HRPWM logic +// +// 1. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz), ePWM1A toggle low/high with MEP control on falling edge +// +// 2. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM2A toggle low/high with MEP control on falling edge +// +// 3. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM3A toggle high/low with MEP control on falling edge +// +// 4. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM4A toggle high/low with MEP control on falling edge +// +// To load and run this example: +// 1. Run this example at 150MHz SYSCLKOUT (or 100 MHz SYSCLKOUT for 100 MHz devices) +// 2. Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch window +// 3. Activate Real time mode +// 4. Run the code +// 5. Watch ePWM1A-4A waveforms on a Oscillosope +// 6. In the watch window: +// Set the variable UpdateFine = 1 to observe the ePWMxA output +// with HRPWM capabilites (default) +// Observe the duty cycle of the waveform changes in fine MEP steps +// 7. In the watch window: +// Change the variable UpdateFine to 0, to observe the +// ePWMxA output without HRPWM capabilites +// Observe the duty cycle of the waveform changes in coarse steps of 10nsec. +// +// +// Watch Variables: +// UpdateFine +// MEP_ScaleFactor +// EPwm1Regs.CMPA.all +// EPwm2Regs.CMPA.all +// EPwm3Regs.CMPA.all +// EPwm4Regs.CMPA.all +// +// +// IMPORTANT NOTE!!!!! +// +// THE SFO.H FUNCTIONS INCLUDED WITH THIS EXAMPLE ONLY SUPPORTS EPWM1-EPWM4. FOR +// SUPPORT FOR MORE THAN 4 EPWMS, USE SFO_V5.H WITH THE SFO_TI_BUILD_V5.LIB LIBRARY. +// SEE THE HRPWM REFERENCE GUIDE (SPRU924) FOR USAGE INFORMATION AND DIFFERENCES +// BETWEEN VERSIONS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization +#include "SFO.h" // SFO library headerfile + +// Declare your function prototypes here +//--------------------------------------------------------------- +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + + +// General System nets - Useful for debug +Uint16 j,duty, DutyFine, n, UpdateFine; +volatile int i; +Uint32 temp; + +// Global array used by the SFO library +int16 MEP_ScaleFactor[5]; + + +volatile struct EPWM_REGS *ePWM[] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; + + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + UpdateFine = 1; + DutyFine = 0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// MEP_ScaleFactor variables iitialization for SFO library functions + MEP_ScaleFactor[0] = 0; //Common Variables for SFO functions + MEP_ScaleFactor[1] = 0; //SFO for HRPWM1 + MEP_ScaleFactor[2] = 0; //SFO for HRPWM2 + MEP_ScaleFactor[3] = 0; //SFO for HRPWM3 + MEP_ScaleFactor[4] = 0; //SFO for HRPWM4 + +// MEP_ScaleFactor variables initialized using function SFO_MepDis + while ( MEP_ScaleFactor[1] == 0 ) SFO_MepDis(1); //SFO for HRPWM1 + while ( MEP_ScaleFactor[2] == 0 ) SFO_MepDis(2); //SFO for HRPWM2 + while ( MEP_ScaleFactor[3] == 0 ) SFO_MepDis(3); //SFO for HRPWM3 + while ( MEP_ScaleFactor[4] == 0 ) SFO_MepDis(4); //SFO for HRPWM4 + +// Initialize a common seed variable MEP_ScaleFactor[0] required for all SFO functions + MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; //Common Variable for SFO library functions + +/// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 30 5.0 MHz 3.33 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(30); // ePWM1 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(30); // ePWM2 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(30); // ePWM3 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(30); // ePWM4 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + + EDIS; + + for(;;) + { + // Sweep DutyFine as a Q15 number from 0.2 - 0.999 + for(DutyFine = 0x2300; DutyFine < 0x7000; DutyFine++) + { + // Variables + int16 CMPA_reg_val, CMPAHR_reg_val; + int32 temp; + + if(UpdateFine) + { + /* + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // Add the offset and rounding + CMPAHR_reg_val += 0x0180; + + // Write the values to the registers as one 32-bit or two 16-bits + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + */ + + // All the above operations may be condensed into + // the following form: + // EPWM1 calculations + + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // Example for a 32 bit write to CMPA:CMPAHR + EPwm1Regs.CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val; + + + // EPWM2 calculations + CMPA_reg_val = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm2Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[2])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + // Example as a 16 bit write to CMPA and then a 16-bit write to CMPAHR + EPwm2Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm2Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // EPWM3 calculations + CMPA_reg_val = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm3Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[3])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm3Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm3Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // EPWM4 calculations + CMPA_reg_val = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm4Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[4])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm4Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm4Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + } + else + { + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + EPwm1Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm1Regs.TBPRD>>15); + EPwm2Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + EPwm3Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + EPwm4Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + + } + + + for (i=0;i<300;i++) + { + // Call the scale factor optimizer lib + SFO_MepEn(1); + SFO_MepEn(2); + SFO_MepEn(3); + SFO_MepEn(4); + + } + + + } + + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// No more diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel new file mode 100644 index 0000000..520f385 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel @@ -0,0 +1,54 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:23 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +//########################################################################### +// Test Description: Run this GEL on F28335 or F2801. +// The Watch window should give a Scale factor value of 67-70 for the HRPWM +// modules in the device. F28335/6 will have four entries. F2801 will have three +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM SFO" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_SFO.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_SFO.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_SFO.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("UpdateFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("MEP_ScaleFactor[1]"); + GEL_WatchAdd("MEP_ScaleFactor[2]"); + GEL_WatchAdd("MEP_ScaleFactor[3]"); + GEL_WatchAdd("MEP_ScaleFactor[4]"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); +} diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt new file mode 100644 index 0000000..ba907e6 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt @@ -0,0 +1,59 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\lib\SFO_TI_Build_fpu.lib" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_SFO.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -pdr -pdv -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHRPWM_SFO.map" -o".\Debug\Example_2833xHRPWM_SFO.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_SFO.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c new file mode 100644 index 0000000..6635f1c --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c @@ -0,0 +1,477 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: June 23, 2008 08:58:36 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO_V5.c +// +// TITLE: DSP2833x Device HRPWM SFO V5 example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files, which include +// the following files required for this example: +// SFO_V5.h and SFO_TI_Build_V5B_fpu.lib (or SFO_TI_Build_V5B.lib for fixed point) +// +// +// !!NOTE!! +// By default, this example project is configured for floating-point math. All included libraries +// must be pre-compiled for floating-point math. +// +// Therefore, SFO_TI_Build_V5B_fpu.lib (compiled for floating-point) is included in the +// project instead of the SFO_TI_Build_V5B.lib (compiled for fixed-point). +// +// To convert the example for fixed-point math, follow the instructions in sfo_readme.txt +// in the /doc directory of the header files and peripheral examples package. +// +// +// Monitor the following pins on an oscilloscope: +// ePWM1A (GPIO0) +// ePWM2A (GPIO2) +// ePWM3A (GPIO4) +// ePWM4A (GPIO6) +// ePWM5A (GPIO8) +// ePWM6A (GPIO10) +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module. +// +// This example calls the following TI's MEP Scale Factor Optimizer (SFO) +// software library V5 functions: +// +// +// int SFO_MepEn_V5(int i); +// updates MEP_ScaleFactor[i] dynamically when HRPWM is in use. +// - returns 1 when complete for the specified channel +// - returns 0 if not complete for the specified channel +// - returns 2 if there is a scale factor out-of-range error +// (MEP_ScaleFactor[n] differs from seed MEP_ScaleFactor[0] +// by more than +/-15). To remedy this: +// 1. Check your software to make sure MepEn completes for +// 1 channel before calling MepEn for another channel. +// 2. Re-run MepDis and re-seed MEP_ScaleFactor[0]. Then +// try again. +// 3. If reason is known and acceptable, treat return of "2" +// like a return of "1", indicating calibration complete. +// +// int SFO_MepDis_V5(int i); +// updates MEP_ScaleFactor[i] when HRPWM is not used +// - returns 1 when complete for the specified channel +// - returns 0 if not complete for the specified channel +// +// MEP_ScaleFactor[PWM_CH] is a global array variable used by the SFO library +// +// ======================================================================= +// NOTE: For more information on using the SFO software library, see the +// High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (spru924) +// ======================================================================= +// +// This example is intended to explain the HRPWM capabilities. The code can be +// optimized for code efficiency. Refer to TI's Digital power application +// examples and TI Digital Power Supply software libraries for details. +// +// All ePWM1A-6A channels will have fine +// edge movement due to the HRPWM logic +// +// 5MHz PWM (for 150 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP control on rising edge +// 3.33MHz PWM (for 100 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP control on rising edge +// +// To load and run this example: +// 1. **!!IMPORTANT!!** - in SFO_V5.h, set PWM_CH to the max number of +// HRPWM channels plus one. For example, for the F28335, the +// maximum number of HRPWM channels is 6. 6+1=7, so set +// #define PWM_CH 7 in SFO_V5.h. (Default is 7) +// 2. Run this example at 150/100MHz SYSCLKOUT +// 3. Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch window +// 4. Activate Real time mode +// 5. Run the code +// 6. Watch ePWM1-6 waveforms on a Oscillosope +// 7. In the watch window: +// Set the variable UpdateFine = 1 to observe the ePWMxA output +// with HRPWM capabilites (default) +// Observe the duty cycle of the waveform changes in fine MEP steps +// 8. In the watch window: +// Change the variable UpdateFine to 0, to observe the +// ePWMxA output without HRPWM capabilites +// Observe the duty cycle of the waveform changes in coarse steps of 10nsec. +// +// Watch Variables: +// UpdateFine +// MEP_ScaleFactor +// EPwm1Regs.CMPA.all +// EPwm2Regs.CMPA.all +// EPwm3Regs.CMPA.all +// EPwm4Regs.CMPA.all +// EPwm5Regs.CMPA.all +// EPwm6Regs.CMPA.all +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization +#include "SFO_V5.h" // SFO V5 library headerfile - required to use SFO library functions + +// **!!IMPORTANT!!** +// UPDATE NUMBER OF HRPWM CHANNELS + 1 USED IN SFO_V5.H +// i.e. #define PWM_CH // F28335 has a maximum of 6 HRPWM channels (7=6+1) + +// Declare your function prototypes here +//--------------------------------------------------------------- +void HRPWM_Config(int); +void error (void); + +// General System nets - Useful for debug +Uint16 UpdateFine, DutyFine, status, nMepChannel; + +//==================================================================== +// The following declarations are required in order to use the SFO +// library functions: +// +int MEP_ScaleFactor[PWM_CH]; // Global array used by the SFO library + // For n HRPWM channels + 1 for MEP_ScaleFactor[0] + +// Array of pointers to EPwm register structures: +// *ePWM[0] is defined as dummy value not used in the example +volatile struct EPWM_REGS *ePWM[PWM_CH] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; +//==================================================================== + +void main(void) +{ + // Local variables + int i; + Uint32 temp; + int16 CMPA_reg_val, CMPAHR_reg_val; + + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// For this case just init GPIO pins for ePWM1-ePWM6 +// This function is in the DSP2833x_EPwm.c file + InitEPwmGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + UpdateFine = 1; + DutyFine = 0; + nMepChannel=1; // HRPWM diagnostics start on ePWM channel 1 + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// MEP_ScaleFactor variables intialization for SFO library functions + for(i=0;i>15; + + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // Add the offset and rounding + CMPAHR_reg_val += 0x0180; + + // Write the values to the registers as one 32-bit or two 16-bits + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + */ + + // All the above operations may be condensed into + // the following form for each channel: + + // EPWM calculations where EPwm1Regs are accessed + // by (*ePWM[1]), EPwm2Regs are accessed by (*ePWM[2]), + // etc.: + + for(i=1;i>15; + temp = ((long)DutyFine * (*ePWM[i]).TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[i])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // Example for a 32 bit write to CMPA:CMPAHR + (*ePWM[i]).CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val; + } + + } + else + { + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + for(i=1;i>15); + } + } + + +// Call the scale factor optimizer lib function SFO_MepEn_V5() +// periodically to track for any changes due to temp/voltage. +// SFO_MepEn_V5 Calibration must be finished on one channel (return 1) before +// moving on to the next channel. +// +// *NOTE*: In this example, SFO_MepEn_V5 is called 700 times in a loop. For example +// purposes, this allows the CMPAHR and CMPA registers to change in such +// a way that when watching in "Continuous Refresh" mode, the user +// can see the CMPAHR register increment in fine steps to a certain point +// before the CMPA register increments in a coarse step. Normally, +// SFO_MepEn_V5 can be called once every so often in the background for +// a slow update with no for-loop. + + for (i=0; i<700; i++) // Call SFO_MepEn_V5 700 times. + { + status = SFO_MepEn_V5(nMepChannel); + if (status == SFO_COMPLETE) // Once SFO_MepEn_V5 complete (returns 1)- + nMepChannel++; // move on to next channel + else if (status == SFO_OUTRANGE_ERROR) // If MEP_ScaleFactor[nMepChannel] differs + { // from seed Mep_ScaleFactor[0] by more than + error(); // +/-15, status = 2 (out of range error) + } + if(nMepChannel==PWM_CH) + nMepChannel =1; // Once max channels reached, loop back to channel 1 + } + + } // end DutyFine for loop + + } // end infinite for loop + +} // end SFO_MepEn_V5 + +//============================================================= +// FUNCTION: HRPWM_Config +// DESCRIPTION: Configures all ePWM channels and sets up HRPWM +// on ePWMxA channels +// +// PARAMETERS: period - desired PWM period in TBCLK counts +// RETURN: N/A +//============================================================= + +void HRPWM_Config(period) +{ +Uint16 j; +// ePWM channel register configuration with HRPWM +// ePWMxA toggle low/high with MEP control on Rising edge + for (j=1;j +/- 15 +// from the Seed Value in MEP_ScaleFactor[0]. +// SFO_MepEn_V5 returned a "2" (SFO_OUTRANGE_ERROR). +// The user should: +// (1) Re-run SFO_MepDis_V5 to re-calibrate +// an appropriate seed value. +// (2) Ensure the code is not calling Mep_En_V5 +// on a different channel when it is currently +// still running on a channel. (Repetitively +// call Mep_En_V5 on current channel until an +// SFO_COMPLETE ( i.e. 1) is returned. +// (3) If the out-of-range condition is acceptable +// for the application, ignore the "2" and +// treat it as a "1" or SFO_COMPLETE. +// +// PARAMETERS: N/A +// RETURN: N/A +//============================================================= + +void error (void) +{ + ESTOP0; // Error - MEP_ScaleFactor out of range of Seed - rerun MepDis calibration. +} + + +// No more + diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel new file mode 100644 index 0000000..d76daae --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel @@ -0,0 +1,58 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:25:04 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +//########################################################################### +// Test Description: Run this GEL on F28334 +// The Watch window should give a Scale factor value of 67-70 for the HRPWM +// modules in the device. F28335 will have a maximum of 6 entries + 1 for +// MEP_ScaleFactor[0]. +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM SFO V5" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_SFO_V5.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_SFO_V5.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_SFO_V5.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("UpdateFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("EPwm5Regs.CMPA.all"); + GEL_WatchAdd("EPwm6Regs.CMPA.all"); + GEL_WatchAdd("MEP_ScaleFactor"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + GEL_WatchAdd("EPwm5Regs,x"); + GEL_WatchAdd("EPwm6Regs,x"); + + +} diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt new file mode 100644 index 0000000..45731df --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt @@ -0,0 +1,53 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\lib\SFO_TI_Build_V5B_fpu.lib" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_SFO_V5.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -pdv -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHRPWM_SFO_V5.map" -o".\Debug\Example_2833xHRPWM_SFO_V5.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_SFO_V5.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c new file mode 100644 index 0000000..ba2dd87 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c @@ -0,0 +1,381 @@ +// TI File $Revision: /main/13 $ +// Checkin $Date: May 5, 2008 15:26:01 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_slider.c +// +// TITLE: DSP2833x Device HRPWM with Slider example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// This example modifies the MEP control registers to show edge displacement +// due to HRPWM control blocks of the respective ePWM module, ePWM1A, 2A, 3A, +// and 4A channels (GPIO0, GPIO2, GPIO4, and GPIO6) will have fine edge movement +// due to HRPWM logic. Load the Example_2833xHRPWM_slider.gel file. +// Select the HRPWM FineDutySlider from the GEL menu. A FineDuty slider +// graphics will show up in CCS. +// Load the program and run. Use the Slider to and observe the epwm edge displacement +// for each slider step change. This explains the MEP control on the ePWMxA channels +// +// 1. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1A toggle low/high with MEP control on rising edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1B toggle low/high with NO HRPWM control +// +// 2. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2A toggle low/high with MEP control on rising edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2B toggle low/high with NO HRPWM control +// +// 3. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3A toggle as high/low with MEP control on falling edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3B toggle low/high with NO HRPWM control +// +// 4. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4A toggle as high/low with MEP control on falling edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4B toggle low/high with NO HRPWM control +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + + +// Declare your function prototypes here +//--------------------------------------------------------------- + +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// General System nets - Useful for debug +Uint16 i,j, duty, DutyFine, n,update; + +Uint32 temp; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(10); // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(20); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(10); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(20); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + + { + +// for(DutyFine =1; DutyFine <256 ;DutyFine ++) + { + + // Example, write to the HRPWM extension of CMPA + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + + // Example, 32-bit write to CMPA:CMPAHR + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + +// for (i=0;i<10000;i++){} // Dummy delay between MEP changes + } + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel new file mode 100644 index 0000000..0c5556a --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel @@ -0,0 +1,51 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:42 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM Slider" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_slider.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_slider.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_slider.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("DutyFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); +} + +menuitem "DSP2833x HRPWM FineDutySlider" +slider FineDutySlider(1, 255, 1, 1, finedutyvalue) +{ + + DutyFine = finedutyvalue; +} diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt new file mode 100644 index 0000000..dc610c8 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt @@ -0,0 +1,51 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_slider.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -cr -ecode_start -m".\Debug\Example_2833xHRPWM_slider.map" -o".\Debug\Example_2833xHRPWM_slider.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_slider" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c new file mode 100644 index 0000000..d602c08 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c @@ -0,0 +1,473 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:43:02 $ +//########################################################################### +// +// FILE: Example_2833xI2c_eeprom.c +// +// TITLE: DSP2833x I2C EEPROM Example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program requires an external I2C EEPROM connected to +// the I2C bus at address 0x50. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program will write 1-14 words to EEPROM and read them back. +// The data written and the EEPROM address written to are contained +// in the message structure, I2cMsgOut1. The data read back will be +// contained in the message structure I2cMsgIn1. +// +// This program will work with the on-board I2C EEPROM supplied on +// the F2833x eZdsp. +// +// +//########################################################################### +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Note: I2C Macros used in this example can be found in the +// DSP2833x_I2C_defines.h file + +// Prototype statements for functions found within this file. +void I2CA_Init(void); +Uint16 I2CA_WriteData(struct I2CMSG *msg); +Uint16 I2CA_ReadData(struct I2CMSG *msg); +interrupt void i2c_int1a_isr(void); +void pass(void); +void fail(void); + +#define I2C_SLAVE_ADDR 0x50 +#define I2C_NUMBYTES 4 +#define I2C_EEPROM_HIGH_ADDR 0x00 +#define I2C_EEPROM_LOW_ADDR 0x30 + +// Global variables +// Two bytes will be used for the outgoing address, +// thus only setup 14 bytes maximum +struct I2CMSG I2cMsgOut1={I2C_MSGSTAT_SEND_WITHSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR, + 0x12, // Msg Byte 1 + 0x34, // Msg Byte 2 + 0x56, // Msg Byte 3 + 0x78, // Msg Byte 4 + 0x9A, // Msg Byte 5 + 0xBC, // Msg Byte 6 + 0xDE, // Msg Byte 7 + 0xF0, // Msg Byte 8 + 0x11, // Msg Byte 9 + 0x10, // Msg Byte 10 + 0x11, // Msg Byte 11 + 0x12, // Msg Byte 12 + 0x13, // Msg Byte 13 + 0x12}; // Msg Byte 14 + + +struct I2CMSG I2cMsgIn1={ I2C_MSGSTAT_SEND_NOSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR}; + +struct I2CMSG *CurrentMsgPtr; // Used in interrupts +Uint16 PassCount; +Uint16 FailCount; + +void main(void) +{ + Uint16 Error; + Uint16 i; + + CurrentMsgPtr = &I2cMsgOut1; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); +// Setup only the GP I/O only for I2C functionality + InitI2CGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.I2CINT1A = &i2c_int1a_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + I2CA_Init(); + +// Step 5. User specific code + + // Clear Counters + PassCount = 0; + FailCount = 0; + + // Clear incoming message buffer + for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++) + { + I2cMsgIn1.MsgBuffer[i] = 0x0000; + } + +// Enable interrupts required for this example + +// Enable I2C interrupt 1 in the PIE: Group 8 interrupt 1 + PieCtrlRegs.PIEIER8.bit.INTx1 = 1; + +// Enable CPU INT8 which is connected to PIE group 8 + IER |= M_INT8; + EINT; + + // Application loop + for(;;) + { + ////////////////////////////////// + // Write data to EEPROM section // + ////////////////////////////////// + + // Check the outgoing message to see if it should be sent. + // In this example it is initialized to send with a stop bit. + if(I2cMsgOut1.MsgStatus == I2C_MSGSTAT_SEND_WITHSTOP) + { + Error = I2CA_WriteData(&I2cMsgOut1); + // If communication is correctly initiated, set msg status to busy + // and update CurrentMsgPtr for the interrupt service routine. + // Otherwise, do nothing and try again next loop. Once message is + // initiated, the I2C interrupts will handle the rest. Search for + // ICINTR1A_ISR in the i2c_eeprom_isr.c file. + if (Error == I2C_SUCCESS) + { + CurrentMsgPtr = &I2cMsgOut1; + I2cMsgOut1.MsgStatus = I2C_MSGSTAT_WRITE_BUSY; + } + } // end of write section + + /////////////////////////////////// + // Read data from EEPROM section // + /////////////////////////////////// + + // Check outgoing message status. Bypass read section if status is + // not inactive. + if (I2cMsgOut1.MsgStatus == I2C_MSGSTAT_INACTIVE) + { + // Check incoming message status. + if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // EEPROM address setup portion + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // Maybe setup an attempt counter to break an infinite while + // loop. The EEPROM will send back a NACK while it is performing + // a write operation. Even though the write communique is + // complete at this point, the EEPROM could still be busy + // programming the data. Therefore, multiple attempts are + // necessary. + } + // Update current message pointer and message status + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_SEND_NOSTOP_BUSY; + } + + // Once message has progressed past setting up the internal address + // of the EEPROM, send a restart to read the data bytes from the + // EEPROM. Complete the communique with a stop bit. MsgStatus is + // updated in the interrupt service routine. + else if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_RESTART) + { + // Read data portion + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // Maybe setup an attempt counter to break an infinite while + // loop. + } + // Update current message pointer and message status + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_READ_BUSY; + } + } // end of read section + + } // end of for(;;) +} // end of main + + +void I2CA_Init(void) +{ + // Initialize I2C + I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code + + #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) + #endif + #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) + #endif + + I2caRegs.I2CCLKL = 10; // NOTE: must be non zero + I2caRegs.I2CCLKH = 5; // NOTE: must be non zero + I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts + + I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset + // Stop I2C when suspended + + I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO + I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT, + + return; +} + + +Uint16 I2CA_WriteData(struct I2CMSG *msg) +{ + Uint16 i; + + // Wait until the STP bit is cleared from any previous master communication. + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + // Setup slave address + I2caRegs.I2CSAR = msg->SlaveAddress; + + // Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + + // Setup number of bytes to send + // MsgBuffer + Address + I2caRegs.I2CCNT = msg->NumOfBytes+2; + + // Setup data to send + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; +// for (i=0; iNumOfBytes-2; i++) + for (i=0; iNumOfBytes; i++) + + { + I2caRegs.I2CDXR = *(msg->MsgBuffer+i); + } + + // Send start as master transmitter + I2caRegs.I2CMDR.all = 0x6E20; + + return I2C_SUCCESS; +} + + +Uint16 I2CA_ReadData(struct I2CMSG *msg) +{ + // Wait until the STP bit is cleared from any previous master communication. + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + I2caRegs.I2CSAR = msg->SlaveAddress; + + if(msg->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + I2caRegs.I2CCNT = 2; + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; + I2caRegs.I2CMDR.all = 0x2620; // Send data to setup EEPROM address + } + else if(msg->MsgStatus == I2C_MSGSTAT_RESTART) + { + I2caRegs.I2CCNT = msg->NumOfBytes; // Setup how many bytes to expect + I2caRegs.I2CMDR.all = 0x2C20; // Send restart as master receiver + } + + return I2C_SUCCESS; +} + +interrupt void i2c_int1a_isr(void) // I2C-A +{ + Uint16 IntSource, i; + + // Read interrupt source + IntSource = I2caRegs.I2CISRC.all; + + // Interrupt source = stop condition detected + if(IntSource == I2C_SCD_ISRC) + { + // If completed message was writing data, reset msg to inactive state + if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_WRITE_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + } + else + { + // If a message receives a NACK during the address setup portion of the + // EEPROM read, the code further below included in the register access ready + // interrupt source code will generate a stop condition. After the stop + // condition is received (here), set the message status to try again. + // User may want to limit the number of retries before generating an error. + if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_SEND_NOSTOP; + } + // If completed message was reading EEPROM data, reset msg to inactive state + // and read data from FIFO. + else if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_READ_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + for(i=0; i < I2C_NUMBYTES; i++) + { + CurrentMsgPtr->MsgBuffer[i] = I2caRegs.I2CDRR; + } + { + // Check recieved data + for(i=0; i < I2C_NUMBYTES; i++) + { + if(I2cMsgIn1.MsgBuffer[i] == I2cMsgOut1.MsgBuffer[i]) + { + PassCount++; + } + else + { + FailCount++; + } + } + if(PassCount == I2C_NUMBYTES) + { + pass(); + } + else + { + fail(); + } + + + } + + } + } + } // end of stop condition detected + + // Interrupt source = Register Access Ready + // This interrupt is used to determine when the EEPROM address setup portion of the + // read data communication is complete. Since no stop bit is commanded, this flag + // tells us when the message has been sent instead of the SCD flag. If a NACK is + // received, clear the NACK bit and command a stop. Otherwise, move on to the read + // data portion of the communication. + else if(IntSource == I2C_ARDY_ISRC) + { + if(I2caRegs.I2CSTR.bit.NACK == 1) + { + I2caRegs.I2CMDR.bit.STP = 1; + I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT; + } + else if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_RESTART; + } + } // end of register access ready + + else + { + // Generate some error due to invalid interrupt source + asm(" ESTOP0"); + } + + // Enable future I2C (PIE Group 8) interrupts + PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; +} + +void pass() +{ + asm(" ESTOP0"); + for(;;); +} + +void fail() +{ + asm(" ESTOP0"); + for(;;); +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel new file mode 100644 index 0000000..3a11875 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:18:05 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x I2C EEPROM Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xI2C_eeprom.pjt"); + GEL_ProjectBuild("Example_2833xI2C_eeprom.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xI2C_eeprom.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("PassCount",,"Correct Bytes"); + GEL_WatchAdd("FailCount",,"Incorrect Bytes"); + GEL_WatchAdd("I2cMsgIn1.MsgBuffer",,"Input Buffer"); + GEL_WatchAdd("I2cMsgOut1.MsgBuffer",,"Output Buffer"); + GEL_WatchAdd("I2caRegs,x"); +} diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt new file mode 100644 index 0000000..06c13e7 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_I2C.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xI2C_eeprom.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xI2C_eeprom.map" -o".\Debug\Example_2833xI2C_eeprom.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xI2C_eeprom.out" -x + diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c new file mode 100644 index 0000000..dd70f78 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c @@ -0,0 +1,167 @@ +// TI File $Revision: /main/13 $ +// Checkin $Date: June 19, 2008 17:08:02 $ +//########################################################################### +// +// FILE: Example_2833xHaltWake.c +// +// TITLE: Device Halt Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as the LPM wakeup pin to trigger a +// WAKEINT interrupt upon detection of a low pulse. +// Initially, pull GPIO0 high externally. To wake device +// from halt mode, pull GPIO0 low for at least the crystal +// startup time + 2 OSCLKS, then pull it high again. +// +// To observe when device wakes from HALT mode, monitor +// GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into HALT mode. If the lowest +// possible current consumption in HALT mode is desired, the +// JTAG connector must be removed from the device board while +// the device is in HALT mode. +// +// The example then wakes up the device from HALT using GPIO0. +// GPIO0 wakes the device from HALT mode when a low pulse +// (signal goes high->low->high)is detected on the pin. +// This pin must be pulsed by an external agent for wakeup. +// +// As soon as GPIO0 goes high again after the pulse, the device +// should wake up, and GPIO1 can be observed to toggle. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void WAKE_ISR(void); // ISR for WAKEINT + +void main() + +{ + + asm(" EALLOW"); + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Enable all pull-ups + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; + GpioCtrlRegs.GPBPUD.all = 0; + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 set in the ISR to indicate device woken up. + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + +/// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable WAKEINT in the PIE: Group 1 interrupt 8 + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter low power mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0002; // LPM mode = Halt + } + EDIS; +// Force device into HALT + + asm(" IDLE"); // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from halt mode. + for(;;){} // Loop here after wake-up. + +} + +/* ----------------------------------------------- */ +/* ISR for WAKEINT - Will be executed when */ +/* low pulse triggered on GPIO0 pin */ +/* ------------------------------------------------*/ +interrupt void WAKE_ISR(void) +{ + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; // Toggle GPIO1 in the ISR - monitored with oscilloscope + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +} diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel new file mode 100644 index 0000000..584ec59 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel @@ -0,0 +1,29 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:32 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Halt Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHaltWake.pjt"); + GEL_ProjectBuild("Example_2833xHaltWake.pjt"); + +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHaltWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt new file mode 100644 index 0000000..266e087 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHaltWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHaltWake.map" -o".\Debug\Example_2833xHaltWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHaltWake.out" -x + diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c new file mode 100644 index 0000000..f9167ce --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c @@ -0,0 +1,175 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: May 12, 2008 14:23:32 $ +//########################################################################### +// +// FILE: Example_2833xIdleWake.c +// +// TITLE: Device Idle Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as an XINT1 pin to trigger a +// XINT1 interrupt upon detection of a falling edge. +// Initially, pull GPIO0 high externally. To wake device +// from idle mode by triggering an XINT1 interrupt, +// pull GPIO0 low (falling edge) +// +// To observe when device wakes from IDLE mode, monitor +// GPIO1 with an oscilloscope (set to 1 in XINT1 ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into IDLE mode. +// +// The example then wakes up the device from IDLE using XINT1 +// which triggers on a falling edge from GPIO0. +// This pin must be pulled from high to low by an external agent for +// wakeup. +// +// To observe the device wakeup from IDLE mode, monitor GPIO1 with +// an oscilloscope, which goes high in the XINT_1_ISR. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void XINT_1_ISR(void); // ISR + +void main() + +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Choose GPIO0 as the XINT1 pin. + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFE; // All pins are outputs except 0 + GpioDataRegs.GPADAT.all = 0x00000000; // All I/O pins are driven low + EDIS; + + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 pin + XIntruptRegs.XINT1CR.bit.POLARITY = 0; // Interrupt triggers on falling edge + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &XINT_1_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable XINT1 in the PIE: Group 1 interrupt 4 + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter Idle mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0000; // LPM mode = Idle + } + EDIS; + asm(" IDLE"); // Device waits in IDLE until XINT1 interrupts + for(;;){} +} + + +interrupt void XINT_1_ISR(void) +{ + GpioDataRegs.GPASET.bit.GPIO1 = 1; // GPIO1 is driven high upon exiting IDLE. + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + EINT; + return; +} + + + + + + + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel new file mode 100644 index 0000000..97129a8 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel @@ -0,0 +1,28 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:43 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Idle Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xIdleWake.pjt"); + GEL_ProjectBuild("Example_2833xIdleWake.pjt"); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xIdleWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt new file mode 100644 index 0000000..88e5a28 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xIdleWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xIdleWake.map" -o".\Debug\Example_2833xIdleWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xIdleWake.out" -x + diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c new file mode 100644 index 0000000..2a30112 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c @@ -0,0 +1,169 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 19, 2008 17:08:04 $ +//########################################################################### +// +// FILE: Example_2833xStandbyWake.c +// +// TITLE: Device Standby Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as the LPM wakeup pin to trigger a +// WAKEINT interrupt upon detection of a low pulse. +// Initially, pull GPIO0 high externally. To wake device +// from standby mode, pull GPIO0 low for at least (2+QUALSTDBY) +// OSCLKS, then pull it high again. +// +// To observe when device wakes from STANDBY mode, monitor +// GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into STANDBY mode. If the lowest +// possible current consumption in STANDBY mode is desired, the +// JTAG connector must be removed from the device board while +// the device is in STANDBY mode. +// +// The example then wakes up the device from STANDBY using GPIO0. +// GPIO0 wakes the device from STANDBY mode when a low pulse +// (signal goes high->low->high)is detected on the pin. +// This pin must be pulsed by an external agent for wakeup. +// +// As soon as GPIO0 goes high again after the pulse, the device +// should wake up, and GPIO1 can be observed to toggle. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void WAKE_ISR(void); // ISR for WAKEINT + +void main() + +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 set in the ISR to indicate device woken up. + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable WAKEINT in the PIE: Group 1 interrupt 8 + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Choose qualification cycles in LPMCR0 register + SysCtrlRegs.LPMCR0.bit.QUALSTDBY = 0; // The wakeup signal should be (2+QUALSTDBY) OSCCLKs wide. + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter Standby mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0001; // LPM mode = Standby + } + EDIS; +// Force device into STANDBY + + asm(" IDLE"); // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from Standby mode. + for(;;){} // Loop here after wake-up. + +} + +/* ----------------------------------------------- */ +/* ISR for WAKEINT - Will be executed when */ +/* low pulse triggered on GPIO0 pin */ +/* ------------------------------------------------*/ +interrupt void WAKE_ISR(void) +{ + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; // Toggle GPIO1 in the ISR - monitored with oscilloscope + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + +} diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel new file mode 100644 index 0000000..cfec4cc --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel @@ -0,0 +1,29 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:54 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Standby Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xStandbyWake.pjt"); + GEL_ProjectBuild("Example_2833xStandbyWake.pjt"); + +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xStandbyWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt new file mode 100644 index 0000000..7ed3469 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xStandbyWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xStandbyWake.map" -o".\Debug\Example_2833xStandbyWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xStandbyWake.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c new file mode 100644 index 0000000..84f748e --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c @@ -0,0 +1,244 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_FFDLB.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Digital loopback tests for the McBSP peripheral. +// +// Three different serial word sizes can be tested. +// +// Before compiling this project: +// * Select the serial word size (8/16/32) by using +// the #define statements at the beginning of the code. +// + +// +// This example does not use interrupts. Instead, a polling +// method is used to check the receive data. The incoming +// data is checked for accuracy. If an error is found the error() +// function is called and execution stops. +// +// This program will execute until terminated by the user. +// +// Watch Variables: +// sdata1 +// sdata2 +// rdata1 +// rdata2 +// rdata1_point +// rdata2_point +// +//########################################################################### +// +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Choose a word size. Uncomment one of the following lines +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + + +// Prototype statements for functions found within this file. +void mcbsp_xmit(int a, int b); +void error(void); + +// Global data for this example +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Recieved Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Recieved Data + +Uint16 rdata1_point; +Uint16 rdata2_point; + + +void main(void) +{ + Uint16 datasize; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this example, only enable the GPIO for McBSP-A + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + datasize = WORD_SIZE; + InitMcbspa(); // Initalize the Mcbsp-A in loopback test mode + +// Step 5. User specific code, enable interrupts: + + if(datasize == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + sdata2 = 0x0000; // value is a don't care for 8-bit mode + sdata1 = 0x0000; // 8-bit value to send + rdata2_point = 0x0000; // value is a don't care for 8-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata1 = sdata1 & 0x00FF; // Keep it to 8-bits + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + if(rdata1 != rdata1_point) error(); + rdata1_point++; + rdata1_point = rdata1_point & 0x00FF; // Keep it to 8-bits + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + } + } + + + else if(datasize == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + sdata2 = 0x0000; // value is a don't care for 16-bit mode + sdata1 = 0x0000; // 16-bit value to send + rdata2_point = 0x0000; // value is a don't care for 16-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + if(rdata1 != rdata1_point) error(); + rdata1_point++; + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + } + } + + + else if(datasize == 32) // Run a loopback test in 16-bit mode + { + InitMcbspa32bit(); + sdata1 = 0x0000; + sdata2 = 0xFFFF; + rdata1_point = sdata1; + rdata2_point = sdata2; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata2--; + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata2 = McbspaRegs.DRR2.all; + rdata1 = McbspaRegs.DRR1.all; + if(rdata1 != rdata1_point) error(); + if(rdata2 != rdata2_point) error(); + rdata1_point++; + rdata2_point--; + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + // rdata2 = sdata2 + 1 + } + } +} + + + +// Some Useful local functions + +void error(void) +{ + asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + +void mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel new file mode 100644 index 0000000..52976d1 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel @@ -0,0 +1,27 @@ +menuitem "DSP2833x McBSP loopback" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB.pjt"); + Setup_WatchWindow(); +} + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata1,x"); + GEL_WatchAdd("rdata1,x"); + GEL_WatchAdd("sdata2,x"); + GEL_WatchAdd("rdata2,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt new file mode 100644 index 0000000..aa6cf7a --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB.map" -o".\Debug\Example_2833xMcBSP_DLB.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c new file mode 100644 index 0000000..345e7d6 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c @@ -0,0 +1,403 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_DLB_DMA.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back with DMA program +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a McBSP example that uses the internal loopback of +// the peripheral and utilizes the DMA to transfer data from one buffer +// to the McBSP, and then from the McBSP to another buffer. +// +// Initially, sdata[] is filled with values from 0x0000- 0x007F. The DMA +// moves the values in sdata[] one by one to the DXRx registers of the McBSP. +// These values are transmitted and subsequently received by the McBSP. +// Then, the DMA moves each data value to rdata[] as it is received by the McBSP. +// +// Three different serial word sizes can be tested. +// +// Before compiling this project: +// * Select the serial word size (8/16/32) by using +// the #define statements at the beginning of the code. +// +// The program loops forever after all values have been transferred to sdata. +// It is up to the user to stop the program. +// +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata +// rdata +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Choose a word size. Uncomment one of the following lines +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + +// Prototype statements for functions found within this file. + +interrupt void local_D_INTCH1_ISR(void); +interrupt void local_D_INTCH2_ISR(void); +void mcbsp_init_dlb(void); +void init_dma(void); +void init_dma_32(void); +void start_dma(void); +void error(void); + + +// Place sdata and rdata buffers in DMA-accessible RAM (L4 for this example) +#pragma DATA_SECTION(sdata, "DMARAML4") +#pragma DATA_SECTION(rdata, "DMARAML4") +Uint16 sdata[128]; // Sent Data +Uint16 rdata[128]; // Recieved Data +Uint16 data_size; // Word Length variable + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for McBSP-A functionality + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_D_INTCH1_ISR; + PieVectTable.DINTCH2= &local_D_INTCH2_ISR; + EDIS; // Disable access to EALLOW protected registers + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + data_size = WORD_SIZE; + for (i=0; i<128; i++) + { + sdata[i] = i; // Fill sdata with values between 0 and 0x007F + rdata[i] = 0; // Initialize rdata to all 0x0000. + } + if (data_size == 32) + { + init_dma_32(); // DMA Initialization for 32-bit transfers + } else + { + init_dma(); // 1. When using DMA, initialize DMA with peripheral interrupts first. + } + start_dma(); + mcbsp_init_dlb(); // 2. Then initialize and release peripheral (McBSP) from Reset. + + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5 + PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6 + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable PIE Group 7, INT 1 (DMA CH1) + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable PIE Group 7, INT 2 (DMA CH2) + + IER=0x60; // Enable CPU INT groups 6 and 7 + EINT; // Enable Global Interrupts + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +void mcbsp_init_dlb() +{ + + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspaRegs.SPCR1.bit.DLB = 1; // Enable DLB mode. Comment out for non-DLB mode. + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspaRegs.RCR1.all=0x0; + + McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = 0; // CLKG frequency = LSPCLK/(CLKGDV+1) + + McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + + + + //*************** Initialize McBSP Data Length + if(data_size == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + } + if(data_size == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + } + if(data_size == 32) // Run a loopback test in 32-bit mode + { + InitMcbspa32bit(); + } + + //************* Enable Sample rate generator + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// DMA Initialization for data size <= 16-bit + +void init_dma() +{ + EALLOW; + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm(" NOP"); // Only 1 NOP needed per Design + DmaRegs.CH1.MODE.bit.CHINTE = 0; + // Channel 1, McBSPA transmit + DmaRegs.CH1.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH1.DST_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH1.TRANSFER_SIZE = 127; // Interrupt every frame (127 bursts/transfer) + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Don't move destination address + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Start address = McBSPA DXR + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Not needed unless using wrap function + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + + // Channel 2, McBSPA Receive + DmaRegs.CH2.MODE.bit.CHINTE = 0; + DmaRegs.CH2.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH2.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.DST_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.TRANSFER_SIZE = 127; // Interrupt every 127 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Don't move source address + DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Start address = McBSPA DRR + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Not needed unless using wrap function + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A) + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + EDIS; +} + +// DMA Initialization for data size > 16-bit and <= 32-bit. + +void init_dma_32() +{ + EALLOW; + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm(" NOP"); // Only 1 NOP needed per Design + + // Channel 1, McBSPA transmit + DmaRegs.CH1.BURST_SIZE.all = 1; // 2 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.DST_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH1.DST_TRANSFER_STEP = 0xFFFF; // Go back to DXR2 + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Start address = McBSPA DXR2 + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Not needed unless using wrap function + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + + // Channel 2, McBSPA Receive + DmaRegs.CH2.BURST_SIZE.all = 1; // 2 words/burst + DmaRegs.CH2.SRC_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.DST_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0xFFFF; // Decrement back to DRR2 + DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Start address = McBSPA DRR + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Not needed unless using wrap function + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A) + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + EDIS; +} +void start_dma (void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start DMA Transmit from McBSP-A + DmaRegs.CH2.CONTROL.bit.RUN = 1; // Start DMA Receive from McBSP-A + + EDIS; +} +// INT7.1 +interrupt void local_D_INTCH1_ISR(void) // DMA Ch1 +{ + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + DmaRegs.CH1.CONTROL.bit.RUN=0; // Re-enable DMA CH1. Should be done every transfer + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt + + EDIS; + return; +} + +// INT7.2 +interrupt void local_D_INTCH2_ISR(void) // DMA Ch2 +{ + Uint16 i; + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + DmaRegs.CH2.CONTROL.bit.RUN = 0; // Re-enable DMA CH2. Should be done every transfer + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt + for (i=0; i<128; i++) + { + if(data_size == 8) + { + if( (rdata[i]&0x00FF) !=(sdata[i]&0x00FF)) error( ); // Check for correct received data + } + else if (data_size == 16) + { + if (rdata[i] != sdata[i]) error(); // STOP if there is an error !! + } + else if (data_size == 32) + { + if ((rdata[i])!=(sdata[i])) error (); + } + } + EDIS; + return; + +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel new file mode 100644 index 0000000..1c54abc --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel @@ -0,0 +1,22 @@ +menuitem "DSP2833x McBSP DMA" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB_DMA.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB_DMA.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB_DMA.out"); + Setup_WatchWindow(); +} +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("sdata,x"); +} + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt new file mode 100644 index 0000000..4194aa8 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt @@ -0,0 +1,52 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB_DMA.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_DMA.map" -o".\Debug\Example_2833xMcBSP_DLB_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB_DMA.out" -x + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c new file mode 100644 index 0000000..9f0a646 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c @@ -0,0 +1,221 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_FFDLB_int.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back porgram +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a McBSP example that uses the internal loopback of +// the peripheral. Both Rx and Tx interrupts are enabled. +// +// Incrementing values from 0x0000 to 0x00FF are being sent and received. +// +// This pattern is repeated forever. +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata +// rdata +// rdata_point +// +//########################################################################### +// +// Original Source by S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void Mcbsp_TxINTA_ISR(void); +interrupt void Mcbsp_RxINTA_ISR(void); +void mcbsp_init_dlb(void); +void error(void); + +// Global data variables used for this example +Uint16 sdata; // Sent Data +Uint16 rdata; // Recieved Data +Uint16 rdata_point; // Keep track of where we + // are in the data stream + + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for McBSP-A functionality + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.MRINTA= &Mcbsp_RxINTA_ISR; + PieVectTable.MXINTA= &Mcbsp_TxINTA_ISR; + EDIS; // Disable access to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + mcbsp_init_dlb(); // For this example, only initialize the Mcbsp + + +// Step 5. User specific code, enable interrupts: + + sdata = 0; + rdata_point = sdata; + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5 + PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6 + IER=0x20; // Enable CPU INT6 + EINT; // Enable Global Interrupts + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +void mcbsp_init_dlb() +{ + +//*************** RESET MCBSP + McbspaRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset + McbspaRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset + McbspaRegs.SPCR2.bit.XRST=0; // Transmitter reset + McbspaRegs.SPCR1.bit.RRST=0; // Receiver reset + +//*************** Initialize McBSP Registers +// McBSP register settings for Digital loop back + McbspaRegs.SPCR2.all=0x0000; // XRST =0 + McbspaRegs.SPCR1.all=0x8000; // RRST =0, DLB enabled + McbspaRegs.RCR2.all=0x0001; // RDATDLY = 1 + McbspaRegs.RCR1.all=0x0; + McbspaRegs.XCR2.all=0x0001; // XDATDLY = 1 + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.SRGR2.all=0x3140; + McbspaRegs.SRGR1.all=0x010f; + McbspaRegs.MCR2.all=0x0; + McbspaRegs.MCR1.all=0x0; + McbspaRegs.PCR.all=0x0A00; + + McbspaRegs.MFFINT.bit.XINT = 1; // Enable Transmit Interrupts + McbspaRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts + +//************* Enable Sample rate generator + McbspaRegs.SPCR2.bit.GRST=1; + delay_loop(); // Wait at least 2 SRG clock cycles + +//************ Enable TX/RX unit + McbspaRegs.SPCR2.bit.XRST=1; + McbspaRegs.SPCR1.bit.RRST=1; + +//************ Frame Sync generator reset + McbspaRegs.SPCR2.bit.FRST=1; +} + +interrupt void Mcbsp_TxINTA_ISR(void) +{ + McbspaRegs.DXR1.all= sdata; + sdata = (sdata+1)& 0x00FF ; + // To receive more interrupts from this PIE group, acknowledge this interrupt + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +interrupt void Mcbsp_RxINTA_ISR(void) +{ + rdata=McbspaRegs.DRR1.all; + if (rdata != ( (rdata_point) & 0x00FF) ) error(); + rdata_point = (rdata_point+1) & 0x00FF; + // To receive more interrupts from this PIE group, acknowledge this interrupt + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel new file mode 100644 index 0000000..b3cd28b --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel @@ -0,0 +1,27 @@ +menuitem "DSP2833x McBSP Int" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB_int.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB_int.pjt"); + Setup_WatchWindow(); +} + + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB_int.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata,x"); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("rdata_point,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt new file mode 100644 index 0000000..1f8f3a6 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB_int.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_int.map" -o".\Debug\Example_2833xMcBSP_DLB_int.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c new file mode 100644 index 0000000..46f35d8 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_SPIX.c +// +// TITLE: DSP28133x Device McBSP using SPI mode +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// SPI master mode transfer of 32-bit word size with digital loopback enabled. +// +// McBSP Signals SPI equivalent +// ------------------------------------- +// MCLKX SPICLK (master) +// MFSX SPISTE (master) +// MDX SPISIMO +// MCLKR SPICLK (slave - not used for this example) +// MFSR SPISTE (slave - not used for this example) +// MDR SPISOMI (not used for this example) +// +// This program will execute and transmit words until terminated by the user. +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (CPU_SPD/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata1 +// sdata2 +// rdata1 +// rdata2 +// +// +//########################################################################### +// +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +void init_mcbsp_spi(void); +void mcbsp_xmit(int a, int b); +void error(void); + +// Global data for this example +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Recieved Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Recieved Data + + +void main(void) +{ + +// Uint16 i; + + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this example, only enable the GPIO for McBSP-A + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP281x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + +// Step 5. User specific code, + + init_mcbsp_spi(); + sdata1 = 0x55aa; + sdata2 = 0xaa55; +// Main loop to transfer 32-bit words through MCBSP in SPI mode periodically + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {} // Master waits until RX data is ready + rdata2 = McbspaRegs.DRR2.all; // Read DRR2 first. + rdata1 = McbspaRegs.DRR1.all; // Then read DRR1 to complete receiving of data + if((rdata2 != sdata2)&&(rdata1 != sdata1)) error( ); // Check that correct data is received. + delay_loop(); + sdata1^=0xFFFF; + sdata2^=0xFFFF; + asm(" nop"); // Good place for a breakpoint + + } +} + + + +// Some Useful local functions + +void error(void) +{ + asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + + + + +void init_mcbsp_spi() +{ + // McBSP-A register settings + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis. + McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1) + McbspaRegs.SPCR1.bit.DLB = 1; + McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme + McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay + McbspaRegs.PCR.bit.CLKRP = 0; + McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive) + McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit) + + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word + + McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods + McbspaRegs.SRGR1.all= 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16 + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +void mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel new file mode 100644 index 0000000..f0a701d --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel @@ -0,0 +1,28 @@ +menuitem "DSP2833x McBSP SPI DLB" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_SPI_DLB.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_SPI_DLB.pjt"); + Setup_WatchWindow(); +} + + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_SPI_DLB.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata1,x"); + GEL_WatchAdd("rdata1,x"); + GEL_WatchAdd("sdata2,x"); + GEL_WatchAdd("rdata2,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt new file mode 100644 index 0000000..2f8e650 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_SPI_DLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_int.map" -o".\Debug\Example_2833xMcBSP_SPI_DLB.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_SPI_DLB.out" -x + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c new file mode 100644 index 0000000..6d93eff --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c @@ -0,0 +1,390 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: April 21, 2008 15:43:14 $ +//########################################################################### +// +// FILE: Example_2833xSci_Autobaud_.c +// +// TITLE: DSP2833x SCI Autobaud detect example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Test requires the following hardware connections: +// +// GPIO29/SCITXDA <-> GPIO19/SCIRXDB +// GPIO28/SCIRXDA <-> GPIO18/SCITXDB +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// This test will perform autobaud lock at a variety of baud rates, including +// very high baud rates. +// +// For this test to properly run, connect the SCI-A pins to the +// SCI-B pins without going through a transciever. +// +// At higher baud rates, the slew rate of the incoming data bits can be +// affected by transceiver and connector performance. This slew rate may +// limit reliable autobaud detection at higher baud rates. +// +// SCIA: Slave, autobaud locks, receives characters and +// echos them back to the host. Uses the RX interrupt +// to receive characters. +// +// SCIB: Host, known baud rate, sends characters to the slave +// and checks that they are echoed back. +// +// DESCRIPTION: +// +// Internal Loopback test for ever through SCIA using interrupts, +// FIFOs are disabled. +// +// Watch Variables: BRRVal - current BRR value used for SCIB +// ReceivedAChar - character received by SCIA +// ReceivedBChar - character received by SCIB +// SendChar - character being sent by SCIB +// SciaRegs.SCILBAUD - SCIA baud registers - set +// SciaRegs.SCIHBAUD by autobaud lock +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +#define BAUDSTEP 100 // Amount BRR will be incremented between each + // autobaud lock + +// Prototype statements for functions found within this file. +void scia_init(void); +void scib_init(void); +void scia_xmit(int a); +void scib_xmit(int a); +void scia_AutobaudLock(void); +void error(); +interrupt void rxaint_isr(void); + + +// Global counts used in this example +Uint16 LoopCount; +//Uint16 xmitCount; +Uint16 ReceivedCount; +Uint16 ErrorCount; +Uint16 SendChar; +Uint16 ReceivedAChar; // scia received character +Uint16 ReceivedBChar; // scib received character +Uint16 BRRVal; +Uint16 Buff[10] = {0x55, 0xAA, 0xF0, 0x0F, 0x00, 0xFF, 0xF5, 0x5F, 0xA5, 0x5A}; + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + InitSciGpio(); + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SCIRXINTA = &rxaint_isr; + EDIS; // This is needed to disable write to EALLOW protected register + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + scia_init(); // Initalize SCIA + scib_init(); // Initalize SCIB + +// Step 5. User specific code, enable interrupts: + + LoopCount = 0; + ErrorCount = 0; + +// Enable interrupts + PieCtrlRegs.PIEIER9.all = 0x0001; // Enable all SCIA RXINT interrupt + IER |= 0x0100; // enable PIEIER9, and INT9 + EINT; + + // Start with BRR = 1, work through each baud rate setting + // incrementing BRR by BAUDSTEP + for (BRRVal = 0x0000; BRRVal < (Uint32)0xFFFF; BRRVal+=BAUDSTEP) + { + + // SCIB has a known baud rate. SCIA will autobaud to match + ScibRegs.SCIHBAUD = (BRRVal >> 8); + ScibRegs.SCILBAUD = (BRRVal); + + // Initiate an autobaud lock with scia. Check + // returned character against baud lock character 'A' + scia_AutobaudLock(); + while(ScibRegs.SCIRXST.bit.RXRDY != 1) { } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + if(ReceivedBChar != 'A') + { + error(0); + } + + // Send/echoback characters + // 55 AA F0 0F 00 FF F5 5F A5 5A + for(i= 0; i<=9; i++) + { + SendChar = Buff[i]; + scib_xmit(SendChar); // Initiate interrupts and xmit data in isr + // Wait to get the character back and check + // against the sent character. + while(ScibRegs.SCIRXST.bit.RXRDY != 1) + { + asm(" NOP"); + } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + if(ReceivedBChar != SendChar) error(1); + } + + } // Repeat for next BRR setting + + // Stop here, no more + for(;;) + { + asm(" NOP"); + } + + +} + + +/* --------------------------------------------------- */ +/* ISR for PIE INT9.1 */ +/* Connected to RXAINT SCI-A */ +/* ----------------------------------------------------*/ + +interrupt void rxaint_isr(void) // SCI-A +{ + // Insert ISR Code here + + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // If autobaud detected, we must clear CDC + if(SciaRegs.SCIFFCT.bit.ABD == 1) + { + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 0; + // Check received character - should be 'A' + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + if(ReceivedAChar != 'A') + { + error(2); + } + else scia_xmit(ReceivedAChar); + } + + // This was not autobaud detect + else + { + // Check received character against sendchar + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + if(ReceivedAChar != SendChar) + { + error(3); + } + else scia_xmit(ReceivedAChar); + } + + SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // clear Receive interrupt flag + ReceivedCount++; +} + + +void error() +{ + ErrorCount++; + asm(" ESTOP0"); // Uncomment to stop the test here + for (;;); + +} + +// SCIA 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity +void scia_init() +{ + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + + // Reset FIFO's + SciaRegs.SCIFFTX.all=0x8000; + + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + + +} + +// SCIB 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity + +void scib_init() +{ + // Reset FIFO's + ScibRegs.SCIFFTX.all=0x8000; + + // 1 stop bit, No parity, 8-bit character + // No loopback + ScibRegs.SCICCR.all = 0x0007; + + // Enable TX, RX, Use internal SCICLK + ScibRegs.SCICTL1.all = 0x0003; + + // Disable RxErr, Sleep, TX Wake, + // Diable Rx Interrupt, Tx Interrupt + ScibRegs.SCICTL2.all = 0x0000; + + // Relinquish SCI-A from reset + ScibRegs.SCICTL1.all = 0x0023; + + return; +} + + + + +// Transmit a character from the SCI-A' +void scia_xmit(int a) +{ + SciaRegs.SCITXBUF=a; +} + +// Transmit a character from the SCI-B' +void scib_xmit(int a) +{ + ScibRegs.SCITXBUF=a; +} + + +//------------------------------------------------ +// Perform autobaud lock with the host. +// Note that if autobaud never occurs +// the program will hang in this routine as there +// is no timeout mechanism included. +//------------------------------------------------ + +void scia_AutobaudLock() +{ + + SciaRegs.SCICTL1.bit.SWRESET = 0; + SciaRegs.SCICTL1.bit.SWRESET = 1; + + // Must prime baud register with >= 1 + SciaRegs.SCIHBAUD = 0; + SciaRegs.SCILBAUD = 1; + + // Prepare for autobaud detection + // Make sure the ABD bit is clear by writing a 1 to ABDCLR + // Set the CDC bit to enable autobaud detection + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 1; + + // Wait until we correctly read an + // 'A' or 'a' and lock + // + // As long as Autobaud calibration is enabled (CDC = 1), + // SCI-B (host) will continue transmitting 'A'. This will + // continue until interrupted by the SCI-A RX ISR, where + // SCI-A RXBUF receives 'A', autobaud-locks (ABDCLR=1 + // CDC=0),and returns an 'A' back to the host. Then control + // is returned to this loop and the loop is exited. + // + // NOTE: ABD will become set sometime between + // scib_xmit and the DELAY_US loop, and + // the SCI-A RX ISR will be triggered. + // Upon returning and reaching the if-statement, + // ABD will have been cleared again by the ISR. + + while(SciaRegs.SCIFFCT.bit.CDC== 1) + { + // Note the lower the baud rate the longer + // this delay has to be to allow the other end + // to echo back a character (about 4 characters long) + // Make this really long since we are going through all + // the baud rates. + DELAY_US(280000L); + + if(SciaRegs.SCIFFCT.bit.CDC == 1) + scib_xmit('A'); // host transmits 'A' + + } + + return; +} + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel new file mode 100644 index 0000000..20a2117 --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel @@ -0,0 +1,48 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 15, 2007 09:42:26 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI Autobaud" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSci_Autobaud.pjt"); + GEL_ProjectBuild("Example_2833xSci_Autobaud.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSci_Autobaud.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("BRRVal,x"); + GEL_WatchAdd("ReceivedAChar,x"); + GEL_WatchAdd("ReceivedBChar,x"); + GEL_WatchAdd("ReceivedCount,x"); + GEL_WatchAdd("SendChar,x"); + GEL_WatchAdd("SciaRegs.SCIHBAUD,x"); + GEL_WatchAdd("SciaRegs.SCILBAUD,x"); + GEL_WatchAdd("ScibRegs.SCIHBAUD,x"); + GEL_WatchAdd("ScibRegs.SCILBAUD,x"); + GEL_WatchAdd("SciaRegs,x"); + GEL_WatchAdd("ScibRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt new file mode 100644 index 0000000..d4ef177 --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSci_Autobaud.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSci_Autobaud.map" -o".\Debug\Example_2833xSci_Autobaud.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSci_Autobaud.out" -x + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c new file mode 100644 index 0000000..4fe5cf7 --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c @@ -0,0 +1,236 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:43:19 $ +//########################################################################### +// +// FILE: Example_2833xSci_Echoback.c +// +// TITLE: DSP2833x Device SCI Echoback. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Connect the SCI-A port to a PC via a transciever and cable. +// The PC application 'hypterterminal' can be used to view the data +// from the SCI and to send information to the SCI. Characters recieved +// by the SCI port are sent back to the host. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// This test recieves and echo-backs data through the SCI-A port. +// +// 1) Configure hyperterminal: +// Use the included hyperterminal configuration file SCI_96.ht. +// To load this configuration in hyperterminal: file->open +// and then select the SCI_96.ht file. +// 2) Check the COM port. +// The configuration file is currently setup for COM1. +// If this is not correct, disconnect Call->Disconnect +// Open the File-Properties dialog and select the correct COM port. +// 3) Connect hyperterminal Call->Call +// and then start the 2833x SCI echoback program execution. +// 4) The program will print out a greeting and then ask you to +// enter a character which it will echo back to hyperterminal. +// +// As is, the program configures SCI-A for 9600 baud with +// SYSCLKOUT = 150MHz and LSPCLK = 37.5 MHz +// SYSCLKOUT = 100MHz and LSPCLK = 25.0 Mhz +// +// +// Watch Variables: +// LoopCount for the number of characters sent +// ErrorCount +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void scia_echoback_init(void); +void scia_fifo_init(void); +void scia_xmit(int a); +void scia_msg(char *msg); + +// Global counts used in this example +Uint16 LoopCount; +Uint16 ErrorCount; + +void main(void) +{ + + Uint16 ReceivedChar; + char *msg; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. + // InitGpio(); Skipped for this example + +// For this example, only init the pins for the SCI-A port. +// This function is found in the DSP2833x_Sci.c file. + InitSciaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + + LoopCount = 0; + ErrorCount = 0; + + scia_fifo_init(); // Initialize the SCI FIFO + scia_echoback_init(); // Initalize SCI for echoback + + msg = "\r\n\n\nHello World!\0"; + scia_msg(msg); + + msg = "\r\nYou will enter a character, and the DSP will echo it back! \n\0"; + scia_msg(msg); + + for(;;) + { + msg = "\r\nEnter a character: \0"; + scia_msg(msg); + + // Wait for inc character + while(SciaRegs.SCIFFRX.bit.RXFFST !=1) { } // wait for XRDY =1 for empty state + + // Get character + ReceivedChar = SciaRegs.SCIRXBUF.all; + + // Echo character back + msg = " You sent: \0"; + scia_msg(msg); + scia_xmit(ReceivedChar); + + LoopCount++; + } + +} + + +// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity +void scia_echoback_init() +{ + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + #if (CPU_FRQ_150MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 37.5MHz. + SciaRegs.SCILBAUD =0x00E7; + #endif + #if (CPU_FRQ_100MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 20MHz. + SciaRegs.SCILBAUD =0x0044; + #endif + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// Transmit a character from the SCI +void scia_xmit(int a) +{ + while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {} + SciaRegs.SCITXBUF=a; + +} + +void scia_msg(char * msg) +{ + int i; + i = 0; + while(msg[i] != '\0') + { + scia_xmit(msg[i]); + i++; + } +} + +// Initalize the SCI FIFO +void scia_fifo_init() +{ + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x204f; + SciaRegs.SCIFFCT.all=0x0; + +} + + + + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel new file mode 100644 index 0000000..33e7cb5 --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:20:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI Echoback" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSci_Echoback.pjt"); + GEL_ProjectBuild("Example_2833xSci_Echoback.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSci_Echoback.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("ErrorCount,x"); + GEL_WatchAdd("SciaRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt new file mode 100644 index 0000000..89b00df --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSci_Echoback.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSci_echoback.map" -o".\Debug\Example_2833xSci_echoback.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSci_echoback.out" -x + diff --git a/v120/DSP2833x_examples/sci_echoback/SCI_96.ht b/v120/DSP2833x_examples/sci_echoback/SCI_96.ht new file mode 100644 index 0000000..9c7ebe3 Binary files /dev/null and b/v120/DSP2833x_examples/sci_echoback/SCI_96.ht differ diff --git a/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.c b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.c new file mode 100644 index 0000000..61f1fb9 --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.c @@ -0,0 +1,217 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:24:12 $ +//########################################################################### +// +// FILE: Example_2833xSci_FFDLB.c +// +// TITLE: DSP2833x Device SCI FIFO Digital Loop Back Test. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program uses the internal loop back test mode of the peripheral. +// Other then boot mode pin configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This test uses the loopback test mode of the SCI module to send +// characters starting with 0x00 through 0xFF. The test will send +// a character and then check the receive buffer for a correct match. +// +// Watch Variables: +// LoopCount Number of characters sent +// ErrorCount Number of errors detected +// SendChar Character sent +// ReceivedChar Character recieved +// +// +//########################################################################### +// +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void scia_loopback_init(void); +void scia_fifo_init(void); +void scia_xmit(int a); +void error(); +interrupt void scia_rx_isr(void); +interrupt void scia_tx_isr(void); + +// Global counts used in this example +Uint16 LoopCount; +Uint16 ErrorCount; + +void main(void) +{ + Uint16 SendChar; + Uint16 ReceivedChar; + +// Step 1. Initialize System Control registers, PLL, WatchDog, Clocks to default state: +// This function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Select GPIO for the device or for the specific application: +// This function is found in the DSP2833x_Gpio.c file. +// InitGpio(); skip this as this is example selects the I/O +// for SCI-A in this file itself + InitSciGpio(); + +// Step 3. Initialize PIE vector table: +// The PIE vector table is initialized with pointers to shell Interrupt +// Service Routines (ISR). The shell routines are found in DSP2833x_DefaultIsr.c. +// Insert user specific ISR code in the appropriate shell ISR routine in +// the DSP28_DefaultIsr.c file. + +// Disable and clear all CPU interrupts: + DINT; + IER = 0x0000; + IFR = 0x0000; + + // Initialize Pie Control Registers To Default State: + // This function is found in the DSP2833x_PieCtrl.c file. + // InitPieCtrl(); PIE is not used for this example + + // Initialize the PIE Vector Table To a Known State: + // This function is found in DSP2833x_PieVect.c. + // This function populates the PIE vector table with pointers + // to the shell ISR functions found in DSP2833x_DefaultIsr.c. + InitPieVectTable(); + + // Enable CPU and PIE interrupts + // This example function is found in the DSP2833x_PieCtrl.c file. + EnableInterrupts(); + +// Step 4. Initialize all the Device Peripherals to a known state: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); skip this for SCI tests + +// Step 5. User specific functions, Reassign vectors (optional), Enable Interrupts: + + LoopCount = 0; + ErrorCount = 0; + + scia_fifo_init(); // Initialize the SCI FIFO + scia_loopback_init(); // Initalize SCI for digital loop back + + // Note: Autobaud lock is not required for this example + + // Send a character starting with 0 + SendChar = 0; + +// Step 6. Send Characters forever starting with 0x00 and going through +// 0xFF. After sending each, check the recieve buffer for the correct value + + for(;;) + { + scia_xmit(SendChar); + while(SciaRegs.SCIFFRX.bit.RXFFST !=1) { } // wait for RRDY/RXFFST =1 for 1 data available in FIFO + + // Check received character + ReceivedChar = SciaRegs.SCIRXBUF.all; + if(ReceivedChar != SendChar) error(); + + // Move to the next character and repeat the test + SendChar++; + // Limit the character to 8-bits + SendChar &= 0x00FF; + LoopCount++; + } + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + +void error() +{ + + ErrorCount++; +// asm(" ESTOP0"); // Uncomment to stop the test here +// for (;;); + +} + +// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity +void scia_loopback_init() +{ + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCIHBAUD =0x0000; + SciaRegs.SCILBAUD =0x000F; + SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// Transmit a character from the SCI' +void scia_xmit(int a) +{ + SciaRegs.SCITXBUF=a; +} + +// Initalize the SCI FIFO +void scia_fifo_init() +{ + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x204f; + SciaRegs.SCIFFCT.all=0x0; + +} + + + + + + +//=========================================================================== +// No more. +//=========================================================================== + + + diff --git a/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.gel b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.gel new file mode 100644 index 0000000..541354f --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.gel @@ -0,0 +1,42 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:21:46 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI-A loopback" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xScia_FFDLB.pjt"); + GEL_ProjectBuild("Example_2833xScia_FFDLB.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xScia_FFDLB.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("ErrorCount,x"); + GEL_WatchAdd("SendChar,x"); + GEL_WatchAdd("ReceivedChar,x"); + GEL_WatchAdd("SciaRegs"); +} + + diff --git a/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.pjt b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.pjt new file mode 100644 index 0000000..1f2db50 --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback/Example_2833xScia_FFDLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xScia_FFDLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xScia_FFDLB.map" -o".\Debug\Example_2833xScia_FFDLB.out" -stack0X200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSci_FFDLB.out" -x + diff --git a/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c new file mode 100644 index 0000000..eb1680b --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c @@ -0,0 +1,329 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:43:28 $ +//########################################################################### +// +// FILE: Example_2833xSci_FFDLB_int.c +// +// TITLE: DSP2833x Device SCI Digital Loop Back porgram. +// +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program uses the internal loop back test mode of the peripheral. +// Other then boot mode pin configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a SCI example that uses the internal loopback of +// the peripheral. Both interrupts and the SCI FIFOs are used. +// +// A stream of data is sent and then compared to the recieved stream. +// +// The SCI-A sent data looks like this: +// 00 01 02 03 04 05 06 07 +// 01 02 03 04 05 06 07 08 +// 02 03 04 05 06 07 08 09 +// .... +// FE FF 00 01 02 03 04 05 +// FF 00 01 02 03 04 05 06 +// etc.. +// +// +// The SCI-B sent data looks like this: +// FF FE FD FC FB FA F9 F8 +// FE FD FC FB FA F9 F8 F7 +// FD FC FB FA F9 F8 F7 F6 +// .... +// 01 00 FF FE FD FC FB FA +// 00 FF FE FD FC FB FA F9 +// etc.. +// +// Both patterns are repeated forever. +// +// Watch Variables: +// +// SCI-A SCI-B +// ---------------------- +// sdataA sdataB Data being sent +// rdataA rdataB Data received +// rdata_pointA rdata_pointB Keep track of where we are in the datastream +// This is used to check the incoming data +//########################################################################### +// Original Source by S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +#define CPU_FREQ 150E6 +#define LSPCLK_FREQ CPU_FREQ/4 +#define SCI_FREQ 100E3 +#define SCI_PRD (LSPCLK_FREQ/(SCI_FREQ*8))-1 + +// Prototype statements for functions found within this file. +interrupt void sciaTxFifoIsr(void); +interrupt void sciaRxFifoIsr(void); +interrupt void scibTxFifoIsr(void); +interrupt void scibRxFifoIsr(void); +void scia_fifo_init(void); +void scib_fifo_init(void); +void error(void); + +// Global variables +Uint16 sdataA[8]; // Send data for SCI-A +Uint16 sdataB[8]; // Send data for SCI-B +Uint16 rdataA[8]; // Received data for SCI-A +Uint16 rdataB[8]; // Received data for SCI-A +Uint16 rdata_pointA; // Used for checking the received data +Uint16 rdata_pointB; + + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); +// Setup only the GP I/O only for SCI-A and SCI-B functionality +// This function is found in DSP2833x_Sci.c + InitSciGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SCIRXINTA = &sciaRxFifoIsr; + PieVectTable.SCITXINTA = &sciaTxFifoIsr; + PieVectTable.SCIRXINTB = &scibRxFifoIsr; + PieVectTable.SCITXINTB = &scibTxFifoIsr; + EDIS; // This is needed to disable write to EALLOW protected registers + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + scia_fifo_init(); // Init SCI-A + scib_fifo_init(); // Init SCI-B + +// Step 5. User specific code, enable interrupts: + +// Init send data. After each transmission this data +// will be updated for the next transmission + for(i = 0; i<8; i++) + { + sdataA[i] = i; + } + + for(i = 0; i<8; i++) + { + sdataB[i] = 0xFF - i; + } + + rdata_pointA = sdataA[0]; + rdata_pointB = sdataB[0]; + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER = 0x100; // Enable CPU INT + EINT; + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + + +interrupt void sciaTxFifoIsr(void) +{ + Uint16 i; + for(i=0; i< 8; i++) + { + SciaRegs.SCITXBUF=sdataA[i]; // Send data + } + + for(i=0; i< 8; i++) //Increment send data for next cycle + { + sdataA[i] = (sdataA[i]+1) & 0x00FF; + } + + SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK +} + +interrupt void sciaRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data + } + for(i=0;i<8;i++) // Check received data + { + if(rdataA[i] != ( (rdata_pointA+i) & 0x00FF) ) error(); + } + rdata_pointA = (rdata_pointA+1) & 0x00FF; + + SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag + SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack +} + +void scia_fifo_init() +{ + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCIHBAUD = 0x0000; + SciaRegs.SCILBAUD = SCI_PRD; + SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + SciaRegs.SCIFFTX.all=0xC028; + SciaRegs.SCIFFRX.all=0x0028; + SciaRegs.SCIFFCT.all=0x00; + + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; + SciaRegs.SCIFFRX.bit.RXFIFORESET=1; + + +} + +interrupt void scibTxFifoIsr(void) +{ + Uint16 i; + for(i=0; i< 8; i++) + { + ScibRegs.SCITXBUF=sdataB[i]; // Send data + } + + for(i=0; i< 8; i++) //Increment send data for next cycle + { + sdataB[i] = (sdataB[i]-1) & 0x00FF; + } + + ScibRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK +} + +interrupt void scibRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdataB[i]=ScibRegs.SCIRXBUF.all; // Read data + } + for(i=0;i<8;i++) // Check received data + { + if(rdataB[i] != ( (rdata_pointB-i) & 0x00FF) ) error(); + } + rdata_pointB = (rdata_pointB-1) & 0x00FF; + + ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag + ScibRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack +} + +void scib_fifo_init() +{ + ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + ScibRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + ScibRegs.SCICTL2.bit.TXINTENA =1; + ScibRegs.SCICTL2.bit.RXBKINTENA =1; + ScibRegs.SCIHBAUD =0x0000; + ScibRegs.SCILBAUD =SCI_PRD; + ScibRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + ScibRegs.SCIFFTX.all=0xC028; + ScibRegs.SCIFFRX.all=0x0028; + ScibRegs.SCIFFCT.all=0x00; + + ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1; + ScibRegs.SCIFFRX.bit.RXFIFORESET=1; + +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.gel b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.gel new file mode 100644 index 0000000..617b3e6 --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:21:58 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI Int" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSci_FFDLB_int.pjt"); + GEL_ProjectBuild("Example_2833xSci_FFDLB_int.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_WatchReset(); + GEL_Load(".\\debug\\Example_2833xSci_FFDLB_int.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdataA,x"); + GEL_WatchAdd("rdataA,x"); + GEL_WatchAdd("rdata_pointA,x"); + GEL_WatchAdd("sdataB,x"); + GEL_WatchAdd("rdataB,x"); + GEL_WatchAdd("rdata_pointB,x"); + GEL_WatchAdd("SciaRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.pjt b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.pjt new file mode 100644 index 0000000..9fce8bd --- /dev/null +++ b/v120/DSP2833x_examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSci_FFDLB_int.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\scia_loopback_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSci_FFDLB_int.map" -o".\Debug\Example_2833xSci_FFDLB_int.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSpi_FFDLB.out" -x + diff --git a/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.c b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.c new file mode 100644 index 0000000..8a28e12 --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.c @@ -0,0 +1,184 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:43:32 $ +//########################################################################### +// +// FILE: Example_2833xSpi_FFDLB.c +// +// TITLE: DSP2833x Device Spi Digital Loop Back program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program uses the internal loop back test mode of the peripheral. +// Other then boot mode pin configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a SPI example that uses the internal loopback of +// the peripheral. Interrupts are not used. +// +// A stream of data is sent and then compared to the recieved stream. +// +// The sent data looks like this: +// 0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF +// +// This pattern is repeated forever. +// +// Watch Variables: +// sdata - sent data +// rdata - received data +// +////########################################################################### +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +// interrupt void ISRTimer2(void); +void delay_loop(void); +void spi_xmit(Uint16 a); +void spi_fifo_init(void); +void spi_init(void); +void error(void); + +void main(void) +{ + Uint16 sdata; // send data + Uint16 rdata; // received data + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for SPI-A functionality +// This function is found in DSP2833x_Spi.c + InitSpiaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + spi_fifo_init(); // Initialize the Spi FIFO + spi_init(); // init SPI + +// Step 5. User specific code: +// Interrupts are not used in this example. + sdata = 0x0000; + for(;;) + { + // Transmit data + spi_xmit(sdata); + // Wait until data is received + while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) { } + // Check against sent data + rdata = SpiaRegs.SPIRXBUF; + if(rdata != sdata) error(); + sdata++; + } +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + +void delay_loop() +{ + long i; + for (i = 0; i < 1000000; i++) {} +} + + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +void spi_init() +{ + SpiaRegs.SPICCR.all =0x000F; // Reset on, rising edge, 16-bit char bits + SpiaRegs.SPICTL.all =0x0006; // Enable master mode, normal phase, + // enable talk, and SPI int disabled. + SpiaRegs.SPIBRR =0x007F; + SpiaRegs.SPICCR.all =0x009F; // Relinquish SPI from Reset + SpiaRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission +} + +void spi_xmit(Uint16 a) +{ + SpiaRegs.SPITXBUF=a; +} + +void spi_fifo_init() +{ +// Initialize SPI FIFO registers + SpiaRegs.SPIFFTX.all=0xE040; + SpiaRegs.SPIFFRX.all=0x204f; + SpiaRegs.SPIFFCT.all=0x0; +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.gel b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.gel new file mode 100644 index 0000000..3ba33a3 --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:22:51 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SPI loopback" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSpi_FFDLB.pjt"); + GEL_ProjectBuild("Example_2833xSpi_FFDLB.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSpi_FFDLB.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata,x"); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("SpiaRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.pjt b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.pjt new file mode 100644 index 0000000..e88dc66 --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback/Example_2833xSpi_FFDLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Spi.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSpi_FFDLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSpi_FFDLB.map" -o".\Debug\Example_2833xSpi_FFDLB.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSpi_FFDLB.out" -x + diff --git a/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c new file mode 100644 index 0000000..625b618 --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c @@ -0,0 +1,238 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:43:36 $ +//########################################################################### +// +// FILE: Example_2833xSpi_FFDLB_int.c +// +// TITLE: DSP2833x Device Spi Digital Loop Back with Interrupts Example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program uses the internal loop back test mode of the peripheral. +// Other then boot mode pin configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a SPI-A example that uses the internal loopback of +// the peripheral. Both interrupts and the SPI FIFOs are used. +// +// A stream of data is sent and then compared to the recieved stream. +// +// The sent data looks like this: +// 0000 0001 0002 0003 0004 0005 0006 0007 +// 0001 0002 0003 0004 0005 0006 0007 0008 +// 0002 0003 0004 0005 0006 0007 0008 0009 +// .... +// FFFE FFFF 0000 0001 0002 0003 0004 0005 +// FFFF 0000 0001 0002 0003 0004 0005 0006 +// etc.. +// +// This pattern is repeated forever. +// +// +// Watch Variables: +// sdata[8] - Data to send +// rdata[8] - Received data +// rdata_point - Used to keep track of the last position in +// the receive stream for error checking +//########################################################################### +// +// Original Source by S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +// interrupt void ISRTimer2(void); +interrupt void spiTxFifoIsr(void); +interrupt void spiRxFifoIsr(void); +void delay_loop(void); +void spi_fifo_init(void); +void error(); + +Uint16 sdata[8]; // Send data buffer +Uint16 rdata[8]; // Receive data buffer +Uint16 rdata_point; // Keep track of where we are + // in the data stream to check received data + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for SPI-A functionality + InitSpiaGpio(); + +// Step 3. Initialize PIE vector table: +// Disable and clear all CPU interrupts + DINT; + IER = 0x0000; + IFR = 0x0000; + +// Initialize PIE control registers to their default state: +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SPIRXINTA = &spiRxFifoIsr; + PieVectTable.SPITXINTA = &spiTxFifoIsr; + EDIS; // This is needed to disable write to EALLOW protected registers + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + spi_fifo_init(); // Initialize the SPI only + + +// Step 5. User specific code, enable interrupts: + +// Initalize the send data buffer + for(i=0; i<8; i++) + { + sdata[i] = i; + } + rdata_point = 0; + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx1=1; // Enable PIE Group 6, INT 1 + PieCtrlRegs.PIEIER6.bit.INTx2=1; // Enable PIE Group 6, INT 2 + IER=0x20; // Enable CPU INT6 + EINT; // Enable Global Interrupts + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +// Some Useful local functions +void delay_loop() +{ + long i; + for (i = 0; i < 1000000; i++) {} +} + + +void error(void) +{ + asm(" ESTOP0"); //Test failed!! Stop! + for (;;); +} + + +void spi_fifo_init() +{ +// Initialize SPI FIFO registers + SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI + + SpiaRegs.SPICCR.all=0x001F; //16-bit character, Loopback mode + SpiaRegs.SPICTL.all=0x0017; //Interrupt enabled, Master/Slave XMIT enabled + SpiaRegs.SPISTS.all=0x0000; + SpiaRegs.SPIBRR=0x0063; // Baud rate + SpiaRegs.SPIFFTX.all=0xC028; // Enable FIFO's, set TX FIFO level to 8 + SpiaRegs.SPIFFRX.all=0x0028; // Set RX FIFO level to 8 + SpiaRegs.SPIFFCT.all=0x00; + SpiaRegs.SPIPRI.all=0x0010; + + SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI + + SpiaRegs.SPIFFTX.bit.TXFIFO=1; + SpiaRegs.SPIFFRX.bit.RXFIFORESET=1; +} + +interrupt void spiTxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + SpiaRegs.SPITXBUF=sdata[i]; // Send data + } + + for(i=0;i<8;i++) // Increment data for next cycle + { + sdata[i]++; + } + + + SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ACK +} + +interrupt void spiRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdata[i]=SpiaRegs.SPIRXBUF; // Read data + } + for(i=0;i<8;i++) // Check received data + { + if(rdata[i] != rdata_point+i) error(); + } + rdata_point++; + SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1; // Clear Overflow flag + SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ack +} + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.gel b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.gel new file mode 100644 index 0000000..b0204c9 --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:23:39 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SPI Int" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSpi_FFDLB_int.pjt"); + GEL_ProjectBuild("Example_2833xSpi_FFDLB_int.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSpi_FFDLB_int.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata,x"); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("rdata_point,x"); + GEL_WatchAdd("SpiaRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.pjt b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.pjt new file mode 100644 index 0000000..10b6b8e --- /dev/null +++ b/v120/DSP2833x_examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Spi.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSpi_FFDLB_int.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\spi_loopback_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSpi_FFDLB_int.map" -o".\Debug\Example_2833xSpi_FFDLB_int.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSpi_FFDLB_int.out" -x + diff --git a/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..b039033 --- /dev/null +++ b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c @@ -0,0 +1,1879 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:43:40 $ +//########################################################################### +// +// FILE: Example_2833xSWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines. +// +// This file is based on the standard DSP2833x_SWPrioritizedDefaultIsr.c +// The ISR routines have been modified slightly to provide a trace +// mechanism used for this example +// +//########################################################################### +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +// Defined in the Example_28xSWPrioritizedInterrupts.c file +// for this example only +extern Uint16 ISRTrace[50]; +extern Uint16 ISRTraceIndex; + +// Used for ISR delays +Uint16 i; + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +#if (INT13PL != 0) +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + IER |= MINT13; // Set "global" priority + EINT; + + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT14 of CPU (use MINT14 mask): +#if (INT14PL != 0) +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + IER |= MINT14; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to int15 of CPU (use MINT15 mask): +#if (INT15PL != 0) +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + IER |= MINT15; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to int16 of CPU (use MINT16 mask): +#if (INT16PL != 0) +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + IER |= MINT16; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to EMUINT of CPU (non-maskable): +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// Connected to NMI of CPU (non-maskable): +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to ITRAP of CPU (non-maskable): +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER1 of CPU (non-maskable): +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER2 of CPU (non-maskable): +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER3 of CPU (non-maskable): +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER4 of CPU (non-maskable): +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER5 of CPU (non-maskable): +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER6 of CPU (non-maskable): +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER7 of CPU (non-maskable): +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER8 of CPU (non-maskable): +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER9 of CPU (non-maskable): +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER10 of CPU (non-maskable): +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER11 of CPU (non-maskable): +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Connected to USER12 of CPU (non-maskable): +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// Connected to PIEIER1_1 (use MINT1 and MG11 masks): +#if (G11PL != 0) +interrupt void SEQ1INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0011; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER1_2 (use MINT1 and MG12 masks): +#if (G12PL != 0) +interrupt void SEQ2INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0012; + ISRTraceIndex++; + +} +#endif + + +// Connected to PIEIER1_4 (use MINT1 and MG14 masks): +#if (G14PL != 0) +interrupt void XINT1_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + asm(" NOP"); + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0014; + ISRTraceIndex++; +} +#endif + +// Connected to PIEIER1_5 (use MINT1 and MG15 masks): +#if (G15PL != 0) +interrupt void XINT2_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0015; + ISRTraceIndex++; +} +#endif + + +// Connected to PIEIER1_6 (use MINT1 and MG16 masks): +#if (G16PL != 0) +interrupt void ADCINT_ISR(void) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0016; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER1_7 (use MINT1 and MG17 masks): +#if (G17PL != 0) +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0017; + ISRTraceIndex++; +} +#endif + +// Connected to PIEIER1_8 (use MINT1 and MG18 masks): +#if (G18PL != 0) +interrupt void WAKEINT_ISR(void) // WD/LPM +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0018; + ISRTraceIndex++; +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// Connected to PIEIER2_1 (use MINT2 and MG21 masks): +#if (G21PL != 0) +interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + //Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0021; + ISRTraceIndex++; +} +#endif + +// Connected to PIEIER2_2 (use MINT2 and MG22 masks): +#if (G22PL != 0) +interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0022; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER2_3 (use MINT2 and MG23 masks): +#if (G23PL != 0) +interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0023; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER2_4 (use MINT2 and MG24 masks): +#if (G24PL != 0) +interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0024; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER2_5 (use MINT2 and MG25 masks): +#if (G25PL != 0) +interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0025; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER2_6 (use MINT2 and MG26 masks): +#if (G26PL != 0) +interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0026; + ISRTraceIndex++; + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + + +// Connected to PIEIER3_1 (use MINT3 and MG31 masks): +#if (G31PL != 0) +interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0031; + ISRTraceIndex++; +} +#endif + +// Connected to PIEIER3_2 (use MINT3 and MG32 masks): +#if (G32PL != 0) +interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0032; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER3_3 (use MINT3 and MG33 masks): +#if (G33PL != 0) +interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0033; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER3_4 (use MINT3 and MG34 masks): +#if (G34PL != 0) +interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0034; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER3_5 (use MINT3 and MG35 masks): +#if (G35PL != 0) +interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0035; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER3_6 (use MINT3 and MG36 masks): +#if (G36PL != 0) +interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0036; + ISRTraceIndex++; + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + + +// Connected to PIEIER4_1 (use MINT4 and MG41 masks): +#if (G41PL != 0) +interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0041; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER4_2 (use MINT4 and MG42 masks): +#if (G42PL != 0) +interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0042; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER4_3 (use MINT4 and MG43 masks): +#if (G43PL != 0) +interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0043; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER4_4 (use MINT4 and MG44 masks): +#if (G44PL != 0) +interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0044; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER4_5 (use MINT4 and MG45 masks): +#if (G44PL != 0) +interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0045; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER4_6 (use MINT4 and MG46 masks): +#if (G44PL != 0) +interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0046; + ISRTraceIndex++; + +} +#endif +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// Connected to PIEIER5_1 (use MINT5 and MG51 masks): +#if (G51PL != 0) +interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0051; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER5_2 (use MINT5 and MG52 masks): +#if (G52PL != 0) +interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0052; + ISRTraceIndex++; + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// Connected to PIEIER6_1 (use MINT6 and MG61 masks): +#if (G61PL != 0) +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0061; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER6_2 (use MINT6 and MG62 masks): +#if (G62PL != 0) +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0062; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER6_3 (use MINT6 and MG63 masks): +#if (G63PL != 0) +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0063; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER6_4 (use MINT6 and MG64 masks): +#if (G64PL != 0) +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0064; + ISRTraceIndex++; + +} +#endif + + + +// Connected to PIEIER6_5 (use MINT6 and MG65 masks): +#if (G65PL != 0) +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0065; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER6_6 (use MINT6 and MG66 masks): +#if (G66PL != 0) +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0066; + ISRTraceIndex++; + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// Connected to PIEIER7_1 (use MINT7 and MG71 masks): +#if (G71PL != 0) +interrupt void DINTCH1_ISR(void) // DMA-Channel 1 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0071; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER7_2 (use MINT7 and MG72 masks): +#if (G72PL != 0) +interrupt void DINTCH2_ISR(void) // DMA-Channel 2 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0072; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER7_3 (use MINT7 and MG73 masks): +#if (G73PL != 0) +interrupt void DINTCH3_ISR(void) // DMA-Channel 3 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0073; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER7_4 (use MINT7 and MG74 masks): +#if (G74PL != 0) +interrupt void DINTCH4_ISR(void) // DMA-Channel 4 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0074; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER7_5 (use MINT7 and MG75 masks): +#if (G75PL != 0) +interrupt void DINTCH5_ISR(void) // DMA-Channel 5 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0075; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER7_6 (use MINT7 and MG76 masks): +#if (G76PL != 0) +interrupt void DINTCH6_ISR(void) // DMA-Channel 6 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0076; + ISRTraceIndex++; + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// Connected to PIEIER8_1 (use MINT8 and MG81 masks): +#if (G81PL != 0) +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0081; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER8_2 (use MINT8 and MG82 masks): +#if (G82PL != 0) +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0082; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER8_5 (use MINT8 and MG85 masks): +#if (G85PL != 0) +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0085; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER8_6 (use MINT8 and MG86 masks): +#if (G86PL != 0) +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0086; + ISRTraceIndex++; + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT9 and MG91 masks): +#if (G91PL != 0) +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0091; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_2 (use MINT9 and MG92 masks): +#if (G92PL != 0) +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0092; + ISRTraceIndex++; + +} +#endif + + +// Connected to PIEIER9_3 (use MINT9 and MG93 masks): +#if (G93PL != 0) +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0093; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_4 (use MINT9 and MG94 masks): +#if (G94PL != 0) +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0094; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_5 (use MINT9 and MG95 masks): +#if (G95PL != 0) +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0095; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_6 (use MINT9 and MG96 masks): +#if (G96PL != 0) +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0096; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_7 (use MINT9 and MG97 masks): +#if (G97PL != 0) +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0097; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER9_8 (use MINT9 and MG98 masks): +#if (G98PL != 0) +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0098; + ISRTraceIndex++; + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU int10 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU int11 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU int12 +// ----------------------------------------------------------- + +// Connected to PIEIER12_1 (use MINT12 and MG121 masks): +#if (G121PL != 0) +interrupt void XINT3_ISR(void) // External Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0121; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER12_2 (use MINT12 and MG122 masks): +#if (G122PL != 0) +interrupt void XINT4_ISR(void) // External Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0122; + ISRTraceIndex++; + +} +#endif + + +// Connected to PIEIER12_3 (use MINT12 and MG123 masks): +#if (G123PL != 0) +interrupt void XINT5_ISR(void) // External Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0123; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER12_4 (use MINT12 and MG124 masks): +#if (G124PL != 0) +interrupt void XINT6_ISR(void) // External Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0124; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER12_5 (use MINT12 and MG125 masks): +#if (G125PL != 0) +interrupt void XINT7_ISR(void) // External Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0125; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER12_7 (use MINT12 and MG127 masks): +#if (G127PL != 0) +interrupt void LVF_ISR(void) // FPA32 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0127; + ISRTraceIndex++; + +} +#endif + +// Connected to PIEIER12_8 (use MINT12 and MG128 masks): +#if (G128PL != 0) +interrupt void LUF_ISR(void) // FPA32 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + for(i = 1; i <= 10; i++) {} + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Add ISR to Trace + ISRTrace[ISRTraceIndex] = 0x0128; + ISRTraceIndex++; + +} +#endif + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c new file mode 100644 index 0000000..b78de16 --- /dev/null +++ b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c @@ -0,0 +1,597 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:43:45 $ +//########################################################################### +// +// FILE: Example_2833xSWPrioritizedInterrupts.c +// +// TITLE: DSP2833x Software Prioritized Interrupt Example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// For most applications, the hardware prioritization of the +// the PIE module is sufficient. For applications that need custom +// prioritization, this example illustrates an example of +// how this can be done through software. +// +// For more information on F2833x interrupt priorities, refer to the +// Example_2833xISRPriorities.pdf file included with the DSP2833x/doc directory. +// +// This program simulates interrupt conflicts by writing to the +// PIEIFR registers. This will simulate multiple interrupts coming into +// the PIE block at the same time. +// +// The interrupt service routine routines are software prioritized +// by the table found in the DSP2833x_SWPrioritizedIsrLevels.h file. +// +// 1) Before compiling you must set the Global and Group interrupt priorities +// in the DSP2833x_SWPrioritizedIsrLevels.h file. +// +// 2) Then select which test you want to run with the #define TEST directive +// at the top of this file (select a test between 1 and 10) +// +// 3) Compile the code, load, and run +// +// 4) At the end of each test there is a hard coded breakpoint (ESTOP0). When code +// stops at the breakpoint, examine the ISRTrace buffer to see the order +// in which the ISR's completed. All PIE interrupts will add to the +// ISRTrace. +// +// The ISRTrace will consist of a list of hex values as shown: +// +// 0x00wx <- PIE Group w interrup x finished first +// 0x00yz <- PIE Group y interrupt z finished next +// +// 5) If desired, set a new set of Global and Group interrupt priorites +// and repeat the test to see the change. +// +// +// Watch Variables: +// ISRTrace[50] Trace of ISR's in the order they complete +// After each test, examine this buffer +// to determine if the ISR's completed in +// the order desired. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#define TEST 1 // Select a test number: 1 through 10 + +// Define which interrupts are used in the PIE for each group. +#define ISRS_GROUP1 (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8) +#define ISRS_GROUP2 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP3 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP4 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP5 (M_INT1|M_INT2) +#define ISRS_GROUP6 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP7 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP8 (M_INT1|M_INT2|M_INT5|M_INT6) +#define ISRS_GROUP9 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8) +#define ISRS_GROUP12 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT7|M_INT8) + + +// This array will be used as a trace to check the order that the +// interrupts were serviced +Uint16 ISRTrace[50]; +Uint16 ISRTraceIndex; // used to update an element in the trace buffer + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + +#if (TEST==1) +// Force all group 1 interrupts at once by writing to the PIEIFR1 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 1 interrupt 1-8 + PieCtrlRegs.PIEIER1.all = 0x00FF; + + // Make sure PIEACK for group 1 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT1; + + // Enable CPU INT1 + IER |= M_INT1; + + // Force all valid interrupts for Group 1 + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + + // Enable global Interrupts CPU level: + EINT; // Enable Global interrupt INTM + + // Wait for all Group 1 interrupts to be serviced + while(PieCtrlRegs.PIEIFR1.all != 0x0000 ){} + + // Stop here and check the ISRTrace to determine which order the + // ISR Routines completed. The order is dependant on the priority + // assigned in the DSP2833x_SWPrioritizedIsrLevels.h file + // + // The ISRTrace will contain a list of values corresponding to the + // interrupts serviced in the order they were serviced. + // For example if the ISRTrace looks like this + // 0x0014 ISR Group 1 interrupt 4 + // 0x0017 ISR Group 1 interrupt 7 + // 0x0016 ISR Group 1 interrupt 6 + // 0x0015 ISR Group 1 interrupt 5 + // 0x0018 ISR Group 1 interrupt 8 + // 0x0012 ISR Group 1 interrupt 2 + // 0x0011 ISR Group 1 interrupt 1 + // 0x0000 end of trace + asm(" ESTOP0"); +#endif +#if (TEST == 2) +// CASE 2: +// Force all group 2 interrupts at once by writing to the PIEIFR2 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 2 interrupts 1-8 + PieCtrlRegs.PIEIER2.all = 0x00FF; + + // Enable CPU INT2 + IER |= (M_INT2); + + // Make sure PIEACK for group 2 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT2; + + // Force all valid interrupts for Group 2 + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + + // Enable Global interrupts + EINT; + + + // Wait for all group 2 interrupts to be serviced + while(PieCtrlRegs.PIEIFR2.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); + +#endif +#if (TEST == 3) +// CASE 3: +// Force all group 3 interrupts at once by writing to the PIEIFR3 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 3 interrupts 1-8 + PieCtrlRegs.PIEIER3.all = 0x00FF; + + // Make sure PIEACK for group 3 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT3; + + // Enable CPU INT3 + IER |= (M_INT3); + + // Force all valid interrupts for Group 3 + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + + // Enable Global interrupts + EINT; + + // Wait for all group 3 interrupts to be serviced + while(PieCtrlRegs.PIEIFR3.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); +#endif +#if (TEST == 4) +// CASE 4: +// Force all group 4 interrupts at once by writing to the PIEIFR4 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 4 interrupts 1-8 + PieCtrlRegs.PIEIER4.all = 0x00FF; + + // Make sure PIEACK for group 3 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT4; + + // Enable CPU INT4 + IER |= (M_INT4); + + // Force all valid interrupts for Group 4 + PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4; + + // Enable Global interrupts + EINT; + + // Wait for all group 4 interrupts to be serviced + while(PieCtrlRegs.PIEIFR4.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); +#endif +#if (TEST == 5) +// CASE 5: +// Force all group 5 interrupts at once by writing to the PIEIFR5 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 5 interrupts 1-8 + PieCtrlRegs.PIEIER5.all = 0x00FF; + + // Make sure PIEACK for group 5 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT5; + + // Enable CPU INT5 + IER |= (M_INT5); + + // Force all valid interrupts for Group 5 + PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5; + + // Enable Global interrupts + EINT; + + // Wait for all group 5 interrupts to be serviced + while(PieCtrlRegs.PIEIFR5.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); +#endif +#if (TEST == 6) + +// CASE 6: +// Force all group 6 interrupts at once by writing to the PIEIFR6 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 6 interrupts 1-8 + PieCtrlRegs.PIEIER6.all = 0x00FF; + + // Make sure PIEACK for group 6 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT6; + + // Enable CPU INT6 + IER |= (M_INT6); + + // Force all valid interrupts for Group 6 + PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6; + + // Enable Global interrupts + EINT; + + + // Wait for all group 6 interrupts to be serviced + while(PieCtrlRegs.PIEIFR6.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); + +#endif +#if (TEST == 7) +// CASE 7: +// Force all group 9 interrupts at once by writing to the PIEIFR4 register + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 9 interrupts 1-8 + PieCtrlRegs.PIEIER9.all = 0x00FF; + + // Make sure PIEACK for group 9 is clear (default after reset) + PieCtrlRegs.PIEACK.all = M_INT9; + + // Enable CPU INT9 + IER |= (M_INT9); + + // Force all valid interrupts for Group 9 + PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9; + + // Enable Global interrupts + EINT; + + // Wait for all group 9 interrupts to be serviced + while(PieCtrlRegs.PIEIFR9.all != 0x0000 ){} + + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + asm(" ESTOP0"); + +#endif +#if (TEST == 8) +// CASE 8: +// Force all group 1 and group 2 interrupts at once + + // Setup next test - fire interrupts from Group 1 and Group 2 + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 1 and group 2 interrupts 1-8 + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + + // Make sure PIEACK for group 1 & 2 are clear (default after reset) + PieCtrlRegs.PIEACK.all = (M_INT3 | M_INT2); + + // Enable CPU INT1 and INT2 + IER |= (M_INT1|M_INT2); + + // Force all valid interrupts for Group 1 and from Group 2 + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + + // Enable Global interrupts + EINT; + + // Wait for all group 1 and group 2 interrupts to be serviced + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000 ){} + + // Check the ISRTrace to determine which order the ISR Routines completed + asm(" ESTOP0"); + +#endif +#if (TEST == 9) +// CASE 9: +// Force all group 1 and group 2 and group 3 interrupts at once + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable PIE group 1, 2 and 3 interrupts 1-8 + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + PieCtrlRegs.PIEIER3.all = 0x00FF; + + // Make sure PIEACK for group 1, 2 & 3 are clear (default after reset) + PieCtrlRegs.PIEACK.all = (M_INT3|M_INT2|M_INT3); + + // Enable CPU INT1, INT2 & INT3 + IER |= (M_INT1|M_INT2|M_INT3); + + // Force all valid interrupts for Group1, 2 and 3 + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + + // Enable Global interrupts + EINT; + + // Wait for all group 1 and group 2 and group 3 interrupts to be serviced + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000 + || PieCtrlRegs.PIEIFR3.all != 0x0000 ) {} + + // Check the ISRTrace to determine which order the ISR Routines completed + asm(" ESTOP0"); + +#endif +#if (TEST == 10) +// CASE 10: +// Force all used PIE interrupts at once + + // Prepare for the test: + // Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + DINT; + for(i = 0; i < 50; i++) ISRTrace[i] = 0; + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // Enable the PIE block + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enable all PIE group interrupts 1-8 + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + PieCtrlRegs.PIEIER3.all = 0x00FF; + PieCtrlRegs.PIEIER4.all = 0x00FF; + PieCtrlRegs.PIEIER5.all = 0x00FF; + PieCtrlRegs.PIEIER6.all = 0x00FF; + PieCtrlRegs.PIEIER9.all = 0x00FF; + + // Make sure PIEACK for group 1, 2, 3, 4, 5, 6 and 9 are clear (default after reset) + PieCtrlRegs.PIEACK.all = (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9); + + // Enable CPU INT1, INT2, INT3, INT4, INT5, INT6 and INT9 + IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9); + + // Force all valid interrupts for all PIE groups + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4; + PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5; + PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6; + PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9; + + // Enable Global interrupts - CPU level + EINT; + + // Wait for all group interrupts to be serviced + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000 + || PieCtrlRegs.PIEIFR3.all != 0x0000 + || PieCtrlRegs.PIEIFR4.all != 0x0000 + || PieCtrlRegs.PIEIFR5.all != 0x0000 + || PieCtrlRegs.PIEIFR6.all != 0x0000 + || PieCtrlRegs.PIEIFR9.all != 0x0000 ) {} + + // Check the ISRTrace to determine which order the ISR Routines completed + asm(" ESTOP0"); +#endif +} +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.gel b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.gel new file mode 100644 index 0000000..b801e86 --- /dev/null +++ b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:23:56 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Software Prioritized Interrupts" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSWPrioritizedInterrupts.pjt"); + GEL_ProjectBuild("Example_2833xSWPrioritizedInterrupts.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSWPrioritizedInterrupts.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("ISRTrace,x"); + GEL_WatchAdd("TempPIEIER,x"); + GEL_WatchAdd("PieCtrlRegs,x"); +} diff --git a/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.pjt b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.pjt new file mode 100644 index 0000000..d20e72c --- /dev/null +++ b/v120/DSP2833x_examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSWPrioritizedDefaultIsr.c" +Source="Example_2833xSWPrioritizedInterrupts.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -o2 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xSWPrioritizedInterrupts.map" -o".\Debug\Example_2833xSWPrioritizedInterrupts.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSWPrioritizedInterrupts.out" -x + diff --git a/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.c b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.c new file mode 100644 index 0000000..8b80d5c --- /dev/null +++ b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.c @@ -0,0 +1,161 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 21, 2008 15:44:40 $ +//########################################################################### +// +// FILE: Example_2833xLedBlink.c +// +// TITLE: DSP2833x eZdsp LED Blink Getting Started Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures CPU Timer0 for a 500 msec period, and toggles the GPIO32 +// LED on the 2833x eZdsp once per interrupt. For testing purposes, this example +// also increments a counter each time the timer asserts an interrupt. +// +// Watch Variables: +// CpuTimer0.InterruptCount +// +// Monitor the GPIO32 LED blink on (for 500 msec) and off (for 500 msec) on the 2833x eZdsp. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void cpu_timer0_isr(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize the Device Peripheral. This function can be +// found in DSP2833x_CpuTimers.c + InitCpuTimers(); // For this example, only initialize the Cpu Timers +#if (CPU_FRQ_150MHZ) +// Configure CPU-Timer 0 to interrupt every 500 milliseconds: +// 150MHz CPU Freq, 50 millisecond Period (in uSeconds) + ConfigCpuTimer(&CpuTimer0, 150, 500000); +#endif +#if (CPU_FRQ_100MHZ) +// Configure CPU-Timer 0 to interrupt every 500 milliseconds: +// 100MHz CPU Freq, 50 millisecond Period (in uSeconds) + ConfigCpuTimer(&CpuTimer0, 100, 500000); +#endif + +// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any +// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the +// below settings must also be updated. + + CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + +// Step 5. User specific code, enable interrupts: + +// Configure GPIO32 as a GPIO output pin + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + EDIS; + +// Enable CPU INT1 which is connected to CPU-Timer 0: + IER |= M_INT1; + +// Enable TINT0 in the PIE: Group 1 interrupt 7 + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); +} + + +interrupt void cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + GpioDataRegs.GPBTOGGLE.bit.GPIO32 = 1; // Toggle GPIO32 once per 500 milliseconds + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.gel b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.gel new file mode 100644 index 0000000..96f17f2 --- /dev/null +++ b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.gel @@ -0,0 +1,38 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: September 21, 2007 09:00:23 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x CpuTimerExample" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xLEDBlink.pjt"); + GEL_ProjectBuild("Example_2833xLEDBlink.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xLEDBlink.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer0",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer0Regs,x"); + +} diff --git a/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.pjt b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.pjt new file mode 100644 index 0000000..8e75e9e --- /dev/null +++ b/v120/DSP2833x_examples/timed_led_blink/Example_2833xLEDBlink.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\timed_led_blink\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xLEDBlink.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\timed_led_blink\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\timed_led_blink\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\timed_led_blink\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xLEDBlink.map" -o".\Debug\Example_2833xLEDBlink.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xLEDBlink.out" -x + diff --git a/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.c b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.c new file mode 100644 index 0000000..d424eb5 --- /dev/null +++ b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.c @@ -0,0 +1,176 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:43:50 $ +//########################################################################### +// +// FILE: Example_2833xWatchdog.c +// +// TITLE: DSP2833x Watchdog interrupt test program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program exercises the watchdog. +// +// First the watchdog is connected to the WAKEINT interrupt of the +// PIE block. The code is then put into an infinite loop. +// +// The user can select to feed the watchdog key register or not +// by commenting one line of code in the infinite loop. +// +// If the watchdog key register is fed by the ServiceDog function +// then the WAKEINT interrupt is not taken. If the key register +// is not fed by the ServiceDog function then WAKEINT will be taken. +// +// Watch Variables: +// LoopCount for the number of times through the infinite loop +// WakeCount for the number of times through WAKEINT +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// Prototype statements for functions found within this file. +interrupt void wakeint_isr(void); + +// Global variables for this example +Uint32 WakeCount; +Uint32 LoopCount; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &wakeint_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + +// Clear the counters + WakeCount = 0; // Count interrupts + LoopCount = 0; // Count times through idle loop + +// Connect the watchdog to the WAKEINT interrupt of the PIE +// Write to the whole SCSR register to avoid clearing WDOVERRIDE bit + EALLOW; + SysCtrlRegs.SCSR = BIT1; + EDIS; + +// Enable WAKEINT in the PIE: Group 1 interrupt 8 +// Enable INT1 which is connected to WAKEINT: + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; // Enable PIE Gropu 1 INT8 + IER |= M_INT1; // Enable CPU int1 + EINT; // Enable Global Interrupts + +// Reset the watchdog counter + ServiceDog(); + +// Enable the watchdog + EALLOW; + SysCtrlRegs.WDCR = 0x0028; + EDIS; + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + LoopCount++; + + // Uncomment ServiceDog to just loop here + // Comment ServiceDog to take the WAKEINT instead + // ServiceDog(); + } + + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: +// If local ISRs are used, reassign vector addresses in vector table as +// shown in Step 5 + +interrupt void wakeint_isr(void) +{ + WakeCount++; + + // Acknowledge this interrupt to get more from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.gel b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.gel new file mode 100644 index 0000000..1f8e577 --- /dev/null +++ b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.gel @@ -0,0 +1,41 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:09 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Watchdog" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xWatchdog.pjt"); + GEL_ProjectBuild("Example_2833xWatchdog.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xWatchdog.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("WakeCount,x"); + GEL_WatchAdd("SysCtrlRegs.SCSR,x"); + GEL_WatchAdd("SysCtrlRegs.WDCR,x"); + GEL_WatchAdd("SysCtrlRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.pjt b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.pjt new file mode 100644 index 0000000..e72a9a3 --- /dev/null +++ b/v120/DSP2833x_examples/watchdog/Example_2833xWatchdog.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\watchdog\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xWatchdog.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\watchdog\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\watchdog\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\watchdog\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xWatchdog.map" -o".\Debug\Example_2833xWatchdog.out" -stack0x200 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xWatchdog.out" -x + diff --git a/v120/DSP2833x_examples/xintf_run_from/28335_RAM_xintf_lnk.cmd b/v120/DSP2833x_examples/xintf_run_from/28335_RAM_xintf_lnk.cmd new file mode 100644 index 0000000..8d7dc3c --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/28335_RAM_xintf_lnk.cmd @@ -0,0 +1,167 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: August 29, 2007 14:08:00 $ +//########################################################################### +// +// FILE: 28335_RAM_xintf_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + xintffuncs : LOAD = RAML1, + RUN = ZONE7A, + LOAD_START(_XintffuncsLoadStart), + LOAD_END(_XintffuncsLoadEnd), + RUN_START(_XintffuncsRunStart), + PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c new file mode 100644 index 0000000..2902cff --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c @@ -0,0 +1,256 @@ +//########################################################################### +// +// FILE: Example_2833xCodeRunFromXintf.c +// +// TITLE: Example Program That Executes From XINTF +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures CPU Timer0 and increments +// a counter each time the timer asserts an interrupt. +// +// The code is loaded into SARAM. The XINTF Zone 7 is +// configured for x16-bit data bus. A porition of the code +// is copied to XINTF for execution there. +// +// Watch Variables: +// CpuTimer0.InterruptCount +// CpuTimer1.InterruptCount +// CpuTimer2.InterruptCount +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// These two functions will be loaded into SARAM and copied to +// XINTF zone 7 for execution +#pragma CODE_SECTION(cpu_timer0_isr,"xintffuncs"); +#pragma CODE_SECTION(cpu_timer1_isr,"xintffuncs"); + +// Prototype statements for functions found within this file: +void init_zone7(void); +interrupt void cpu_timer0_isr(void); +interrupt void cpu_timer1_isr(void); +interrupt void cpu_timer2_isr(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize the Device Peripheral. This function can be +// found in DSP2833x_CpuTimers.c + InitCpuTimers(); // For this example, only initialize the Cpu Timers + +#if (CPU_FRQ_150MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 150MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); +#endif + +#if (CPU_FRQ_100MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 100MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); +#endif + +// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any +// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the +// below settings must also be updated. + + CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + +// Step 5. User specific code, enable interrupts: + +// Initalize XINTF Zone 7 + init_zone7(); + +// Copy non-time critical code to XINTF +// This includes the following ISR functions: cpu_timer0_isr(), cpu_timer1_isr() +// The XintffuncsLoadStart, XintffuncsLoadEnd, and XintffuncsRunStart +// symbols are created by the linker. Refer to the F28335_ram_xintf.cmd file. + MemCopy(&XintffuncsLoadStart, &XintffuncsLoadEnd, &XintffuncsRunStart); + +// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 +// which is connected to CPU-Timer 1, and CPU int 14, which is connected +// to CPU-Timer 2: + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + +// Enable TINT0 in the PIE: Group 1 interrupt 7 + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +interrupt void cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +// Configure the timing paramaters for Zone 7. +// Notes: +// This function should not be executed from XINTF +// Adjust the timing based on the data manual and +// external device requirements. +void init_zone7(void) +{ + + // Make sure the XINTF clock is enabled + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; + + // Configure the GPIO for XINTF with a 16-bit data bus + // This function is in DSP2833x_Xintf.c + InitXintf16Gpio(); + + EALLOW; + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = SYSCLKOUT + XintfRegs.XINTCNF2.bit.XTIMCLK = 0; + // Buffer up to 3 writes + XintfRegs.XINTCNF2.bit.WRBUFF = 3; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK + XintfRegs.XINTCNF2.bit.CLKMODE = 0; + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 1; + XintfRegs.XTIMING7.bit.XWRACTIVE = 2; + XintfRegs.XTIMING7.bit.XWRTRAIL = 1; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 1; + XintfRegs.XTIMING7.bit.XRDACTIVE = 3; + XintfRegs.XTIMING7.bit.XRDTRAIL = 0; + + // don't double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 0; + + // Zone will not sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 0; + XintfRegs.XTIMING7.bit.READYMODE = 0; + + // 1,1 = x16 data bus + // 0,1 = x32 data bus + // other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt new file mode 100644 index 0000000..e71b210 --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt @@ -0,0 +1,62 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DBGIER.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_Xintf.c" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xCodeRunFromXintf.c" +Source="Example_2833xRunFromXintf.gel" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" +Source="28335_RAM_xintf_lnk.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -mf -ml -mn -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -heap0x800 -m".\Debug\Example_2833xCodeRunFromXintf.map" -o".\Debug\Example_2833xCodeRunFromXintf.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCodeRunFromXintf.out" -x + +["Example_2833xRunFromXintf.gel" Settings: "Debug"] +ExcludeFromBuild=true + +["Example_2833xRunFromXintf.gel" Settings: "Release"] +ExcludeFromBuild=true + +["28335_RAM_xintf_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["28335_RAM_xintf_lnk.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel b/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel new file mode 100644 index 0000000..04e0f4f --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: August 29, 2007 14:08:07 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28335 XINTF Run Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xCodeRunFromXintf.pjt"); + GEL_ProjectBuild("Example_2833xCodeRunFromXintf.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xCodeRunFromXintf.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer1.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer2.InterruptCount",,"CPU ISR Count"); +} diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd new file mode 100644 index 0000000..fe2d6c5 --- /dev/null +++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: August 8, 2008 11:09:25 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ \ No newline at end of file diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..9da1026 --- /dev/null +++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: June 2, 2008 11:12:24 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel b/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel new file mode 100644 index 0000000..e08455b --- /dev/null +++ b/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel @@ -0,0 +1,237 @@ +/* +/* TI File $Revision: /main/1 $ */ +/* Checkin $Date: May 7, 2008 13:07:07 $ */ +/***********************************************************************/ +/* File: DSP2833x_DualMap_EPWM.gel +/* +/* Description: +/* Adds dual-mapped EPWM registers to the GEL menu in +/* Code Composer Studio and allows user to enable dual-mapping of +/* EPWM registers to Peripheral Frame 3 (DMA-accessible) register +/* space +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +/********************************************************************/ +/* Dual-Mapped Enhanced PWM Registers */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "___________________________________"; +hotmenu ___() {} + +menuitem "Dual-Mapped ePWM Registers"; +hotmenu Enable_ePWM_Dual_Mapping () +{ + *0x702E = (*0x702E) | 0x0001; /* MAPCNF[MAPEPWM] = 1 */ +} +hotmenu ePWM1_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x5801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x5802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x5803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x5804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x5805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x5807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x5808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x5809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x580A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x580B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x580C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x580D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x580E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x580F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x5810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x5811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x5812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x5813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x5814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x5815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x5816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x5817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x5818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x5819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x581A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x581B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x581C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x581D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x581E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x5820,x","ePWM1 HRCNFG"); +} + +hotmenu ePWM2_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x5841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x5842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x5843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x5844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x5845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x5847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x5848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x5849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x584A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x584B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x584C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x584D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x584E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x584F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x5850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x5851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x5852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x5853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x5854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x5855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x5856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x5857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x5858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x5859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x585A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x585B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x585C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x585D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x585E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x5860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM3_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x5881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x5882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x5883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x5884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x5885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x5887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x5888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x5889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x588A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x588B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x588C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x588D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x588E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x588F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x5890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x5891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x5892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x5893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x5894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x5895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x5896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x5897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x5898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x5899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x589A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x589B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x589C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x589D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x589E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x58A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM4_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x58C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x58C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x58C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x58C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x58C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x58C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x58C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x58C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x58C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x58CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x58CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x58CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x58CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x58CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x58CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x58D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x58D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x58D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x58D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x58D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x58D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x58D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x58D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x58D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x58D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x58DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x58DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x58DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x58DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x58DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x58E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM5_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x5901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x5902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x5903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x5904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x5905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x5907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x5908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x5909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x590A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x590B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x590C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x590D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x590E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x590F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x5910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x5911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x5912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x5913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x5914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x5915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x5916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x5917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x5918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x5919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x591A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x591B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x591C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x591D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x591E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x5920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM6_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x5941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x5942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x5943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x5944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x5945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x5947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x5948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x5949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x594A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x594B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x594C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x594D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x594E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x594F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x5950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x5951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x5952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x5953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x5954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x5955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x5956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x5957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x5958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x5959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x595A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x595B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x595C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x595D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x595E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x5960,x","ePWM6 HRCNFG"); + +} + diff --git a/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel b/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel new file mode 100644 index 0000000..c51afd1 --- /dev/null +++ b/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel @@ -0,0 +1,249 @@ +/* +/* TI File $Revision: /main/7 $ */ +/* Checkin $Date: June 2, 2008 11:12:27 $ */ +/******************************************************************* */ +/* File: DSP2833x_peripheral.gel */ +/* Description: Adds '2833x registers to the GEL menu in */ +/* Code Composer Studio using the structures defined in the DSP2833x */ +/* header files. The user must have the symbols (.out file) */ +/* loaded from a project using the DSP28 structures in order for */ +/* these menu items to work. If symbols are not loaded, the */ +/* watch window will report "Identifier not found." */ +/* +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +/* Add a space line to the GEL menu */ +menuitem "____________________________________"; +hotmenu _() {} + +menuitem "Watch DSP2833x Peripheral Structures"; + +hotmenu All_Peripherals_Regs() +{ + GEL_WatchAdd("AdcRegs"); + GEL_WatchAdd("AdcMirror"); + GEL_WatchAdd("CsmRegs"); + GEL_WatchAdd("CsmPwl"); + GEL_WatchAdd("CpuTimer0Regs"); + GEL_WatchAdd("CpuTimer1Regs"); + GEL_WatchAdd("CpuTimer2Regs"); + GEL_WatchAdd("DevEmuRegs"); + GEL_WatchAdd("DmaRegs"); + GEL_WatchAdd("ECanaRegs"); + GEL_WatchAdd("ECanaMboxes"); + GEL_WatchAdd("ECanaLAMRegs"); + GEL_WatchAdd("ECanaMOTSRegs"); + GEL_WatchAdd("ECanbRegs"); + GEL_WatchAdd("ECanbMboxes"); + GEL_WatchAdd("ECanbLAMRegs"); + GEL_WatchAdd("ECanbMOTSRegs"); + GEL_WatchAdd("EPwm1Regs"); + GEL_WatchAdd("EPwm2Regs"); + GEL_WatchAdd("EPwm3Regs"); + GEL_WatchAdd("EPwm4Regs"); + GEL_WatchAdd("EPwm5Regs"); + GEL_WatchAdd("EPwm6Regs"); + GEL_WatchAdd("ECap1Regs"); + GEL_WatchAdd("ECap2Regs"); + GEL_WatchAdd("ECap3Regs"); + GEL_WatchAdd("ECap4Regs"); + GEL_WatchAdd("ECap5Regs"); + GEL_WatchAdd("ECap6Regs"); + GEL_WatchAdd("EQep1Regs"); + GEL_WatchAdd("EQep2Regs"); + GEL_WatchAdd("FlashRegs"); + GEL_WatchAdd("XIntruptRegs"); + GEL_WatchAdd("FlashRegs"); + GEL_WatchAdd("GpioCtrlRegs"); + GEL_WatchAdd("GpioDataRegs"); + GEL_WatchAdd("GpioIntRegs"); + GEL_WatchAdd("I2caRegs"); + GEL_WatchAdd("McbspaRegs"); + GEL_WatchAdd("McbspbRegs"); + GEL_WatchAdd("PartIdRegs"); + GEL_WatchAdd("PieCtrlRegs"); + GEL_WatchAdd("PieVectTable"); + GEL_WatchAdd("SciaRegs"); + GEL_WatchAdd("ScibRegs"); + GEL_WatchAdd("ScicRegs"); + GEL_WatchAdd("SpiaRegs"); + GEL_WatchAdd("SysCtrlRegs"); + GEL_WatchAdd("XintfRegs"); +} +hotmenu _______________________() {} +hotmenu ADC_Regs() +{ + GEL_WatchAdd("AdcRegs"); + GEL_WatchAdd("AdcMirror"); +} +hotmenu Code_Security_Module_Regs() +{ + GEL_WatchAdd("CsmRegs"); + GEL_WatchAdd("CsmPwl"); +} +hotmenu CPU_Timer0_Regs() +{ + GEL_WatchAdd("CpuTimer0Regs"); +} +hotmenu CPU_Timer1_Regs() +{ + GEL_WatchAdd("CpuTimer1Regs"); +} +hotmenu CPU_Timer2_Regs() +{ + GEL_WatchAdd("CpuTimer2Regs"); +} +hotmenu Device_Emulation_Regs() +{ + GEL_WatchAdd("DevEmuRegs"); +} +hotmenu DMA_Regs() +{ + GEL_WatchAdd("DMARegs"); +} +hotmenu eCANA_Regs() +{ + GEL_WatchAdd("ECanaRegs"); + GEL_WatchAdd("ECanaMboxes"); + GEL_WatchAdd("ECanaLAMRegs"); + GEL_WatchAdd("ECanaMOTSRegs"); +} +hotmenu eCANB_Regs() +{ + GEL_WatchAdd("ECanbRegs"); + GEL_WatchAdd("ECanbMboxes"); + GEL_WatchAdd("ECanbLAMRegs"); + GEL_WatchAdd("ECanbMOTSRegs"); +} +hotmenu EPWM1_Regs() +{ + GEL_WatchAdd("EPwm1Regs"); +} +hotmenu EPWM2_Regs() +{ + GEL_WatchAdd("EPwm2Regs"); +} +hotmenu EPWM3_Regs() +{ + GEL_WatchAdd("EPwm3Regs"); +} +hotmenu EPWM4_Regs() +{ + GEL_WatchAdd("EPwm4Regs"); +} +hotmenu EPWM5_Regs() +{ + GEL_WatchAdd("EPwm5Regs"); +} +hotmenu EPWM6_Regs() +{ + GEL_WatchAdd("EPwm6Regs"); +} +hotmenu ECAP1_Regs() +{ + GEL_WatchAdd("ECap1Regs"); +} +hotmenu ECAP2_Regs() +{ + GEL_WatchAdd("ECap2Regs"); +} +hotmenu ECAP3_Regs() +{ + GEL_WatchAdd("ECap3Regs"); +} +hotmenu ECAP4_Regs() +{ + GEL_WatchAdd("ECap4Regs"); +} +hotmenu ECAP5_Regs() +{ + GEL_WatchAdd("ECap5Regs"); +} +hotmenu ECAP6_Regs() +{ + GEL_WatchAdd("ECap6Regs"); +} +hotmenu EQEP1_Regs() +{ + GEL_WatchAdd("EQep1Regs"); +} +hotmenu EQEP2_Regs() +{ + GEL_WatchAdd("EQep2Regs"); +} +hotmenu External_Interface_Regs() +{ + GEL_WatchAdd("XintfRegs"); +} +hotmenu External_Interrupt_Regs() +{ + GEL_WatchAdd("XIntruptRegs"); +} +hotmenu Flash_and_OTP_Regs() +{ + GEL_WatchAdd("FlashRegs"); +} +hotmenu GPIO_CTRL_Regs() +{ + GEL_WatchAdd("GpioCtrlRegs"); +} +hotmenu GPIO_DATA_Regs() +{ + GEL_WatchAdd("GpioDataRegs"); +} +hotmenu GPIO_INT_Regs() +{ + GEL_WatchAdd("GpioIntRegs"); +} +hotmenu I2CA_Regs() +{ + GEL_WatchAdd("I2caRegs"); +} +hotmenu McBSPA_Regs() +{ + GEL_WatchAdd("McbspaRegs"); +} +hotmenu McBSPB_Regs() +{ + GEL_WatchAdd("McbspbRegs"); +} +hotmenu PartId_Regs() +{ + GEL_WatchAdd("PartIdRegs"); +} +hotmenu PIE_Control_Regs() +{ + GEL_WatchAdd("PieCtrlRegs"); +} +hotmenu SCIA_Regs() +{ + GEL_WatchAdd("SciaRegs"); +} +hotmenu SCIB_Regs() +{ + GEL_WatchAdd("ScibRegs"); +} +hotmenu SPIA_Regs() +{ + GEL_WatchAdd("SpiaRegs"); +} +hotmenu System_and_Control_Regs() +{ + GEL_WatchAdd("SysCtrlRegs"); +} + + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + + + + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Adc.h b/v120/DSP2833x_headers/include/DSP2833x_Adc.h new file mode 100644 index 0000000..5c8467a --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Adc.h @@ -0,0 +1,264 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; // ADC Control 1 + union ADCTRL2_REG ADCTRL2; // ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; // Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; // Autosequence status register + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; // ADC Control 3 + union ADCST_REG ADCST; // ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; // Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register +}; + + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of DSP2833x_ADC_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..3475801 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h @@ -0,0 +1,190 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// CPU Timer Register Bit Definitions: +// +// +// TCR: Control register bit definitions: +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// TPR: Pre-scale low bit definitions: +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// TPRH: Pre-scale high bit definitions: +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// TIM, TIMH: Timer register definitions: +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// PRD, PRDH: Period register definitions: +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +//--------------------------------------------------------------------------- +// CPU Timer Register File: +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +//--------------------------------------------------------------------------- +// CPU Timer Support Variables: +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +//--------------------------------------------------------------------------- +// Function prototypes and external definitions: +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// Usefull Timer Operations: +// +// Start Timer: +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// Stop Timer: +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. + +// Start Timer: +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + + +// Stop Timer: +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DMA.h b/v120/DSP2833x_headers/include/DSP2833x_DMA.h new file mode 100644 index 0000000..e8b0d59 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DMA.h @@ -0,0 +1,295 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Channel MODE register bit definitions: +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single burst transfer + // 1 first interrupt triggers burst, continue until transfer count is zero + Uint16 CONTINUOUS:1; // 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap counter + // 1 sync signal controls destination wrap counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +//---------------------------------------------------- +// Channel CONTROL register bit definitions: +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +//---------------------------------------------------- +// DMACTRL register bit definitions: +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +//---------------------------------------------------- +// DEBUGCTRL register bit definitions: +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYCTRL1 register bit definitions: +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYSTAT register bit definitions: +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active and interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// Burst Size +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// Burst Count +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + + + +//---------------------------------------------------- +// DMA Channel Registers: +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +//---------------------------------------------------- +// DMA Registers: +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h new file mode 100644 index 0000000..3a765c6 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h @@ -0,0 +1,97 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: June 2, 2008 11:12:30 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// Device Emulation Register Bit Definitions: +// +// Device Configuration Register Bit Definitions +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 MONPRIV:1; // 20 MONPRIV enable bit + Uint16 rsvd5:1; // 21 reserved + Uint16 EMU0SEL:2; // 23,22 EMU0 Mux select + Uint16 EMU1SEL:2; // 25,24 EMU1 Mux select + Uint16 MCBSPCON:1; // 26 McBSP-B to EMU0/EMU1 pins control + Uint16 rsvd6:5; // 31:27 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// CLASSID +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// PARTID +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + + + +//--------------------------------------------------------------------------- +// Device Emulation Register References & Function Declarations: +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Device.h b/v120/DSP2833x_headers/include/DSP2833x_Device.h new file mode 100644 index 0000000..027aec2 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Device.h @@ -0,0 +1,366 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define TARGET 1 +//--------------------------------------------------------------------------- +// User To Select Target Device: + +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28332 0 // Selects '28332/'28232 + + +//--------------------------------------------------------------------------- +// Common CPU Definitions: +// + +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + + + +//--------------------------------------------------------------------------- +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// + +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + + } qua; + + unsigned short all; + +} BAITE; + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bitA: 1; + unsigned int bitB: 1; + unsigned int bitC: 1; + unsigned int bitD: 1; + unsigned int bitE: 1; + unsigned int bitF: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + + } byt; + + int all; + +} WORDE; + +typedef union +{ + struct + { + unsigned int bit00: 1; + unsigned int bit01: 1; + unsigned int bit02: 1; + unsigned int bit03: 1; + unsigned int bit04: 1; + unsigned int bit05: 1; + unsigned int bit06: 1; + unsigned int bit07: 1; + unsigned int bit08: 1; + unsigned int bit09: 1; + unsigned int bit0A: 1; + unsigned int bit0B: 1; + unsigned int bit0C: 1; + unsigned int bit0D: 1; + unsigned int bit0E: 1; + unsigned int bit0F: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + unsigned int bit16: 1; + unsigned int bit17: 1; + unsigned int bit18: 1; + unsigned int bit19: 1; + unsigned int bit1A: 1; + unsigned int bit1B: 1; + unsigned int bit1C: 1; + unsigned int bit1D: 1; + unsigned int bit1E: 1; + unsigned int bit1F: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + unsigned int quad_4 :4; + unsigned int quad_5 :4; + unsigned int quad_6 :4; + unsigned int quad_7 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + unsigned int byte_2 :8; + unsigned int byte_3 :8; + + } byt; + + struct + { + unsigned int word_0 :16; + unsigned int word_1 :16; + + } wrd; + + unsigned long all; + +} LONGE; + +#define XCLKIN 30000000 // external oscillator frequency +extern long SYSCLKOUT, LSPCLK, HSPCLK; + +#define LOWORD(l)((short int)( (long int)(l) &0xFFFF)) +#define HIWORD(l)((short int)(((long int)(l)>>16)&0xFFFF)) + +#define LOBYTE(w)((char)( (short int)(w) &0xFF)) +#define HIBYTE(w)((char)(((short int)(w)>>8)&0xFF)) + +#define BYTE3(l)((char)(((long int)(l)>>24)&0xFF)) +#define BYTE2(l)((char)(((long int)(l)>>16)&0xFF)) +#define BYTE1(l)((char)(((long int)(l)>> 8)&0xFF)) +#define BYTE0(l)((char)( (long int)(l) &0xFF)) + +//--------------------------------------------------------------------------- +// Include All Peripheral Header Files: +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_McBSP.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + +#if DSP28_28335 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECan.h b/v120/DSP2833x_headers/include/DSP2833x_ECan.h new file mode 100644 index 0000000..65988ca --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECan.h @@ -0,0 +1,1161 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* --------------------------------------------------- */ +/* eCAN Control & Status Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Mailbox enable register (CANME) bit definitions */ +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +/* eCAN Mailbox direction register (CANMD) bit definitions */ +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx + +}; + +/* Allow access to the bit fields or entire register */ +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +/* eCAN Transmit Request Set register (CANTRS) bit definitions */ +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +/* eCAN Transmit Request Reset register (CANTRR) bit definitions */ +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +/* eCAN Transmit Acknowledge register (CANTA) bit definitions */ +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */ +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +/* eCAN Received Message Pending register (CANRMP) bit definitions */ +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +/* eCAN Received Message Lost register (CANRML) bit definitions */ +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +/* eCAN Remote Frame Pending register (CANRFP) bit definitions */ +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */ +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +/* Allow access to the bit fields or entire register */ +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + + +/* eCAN Master Control register (CANMC) bit definitions */ +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +/* eCAN Bit -timing configuration register (CANBTC) bit definitions */ +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +/* eCAN Error & Status register (CANES) bit definitions */ +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + + +/* eCAN Transmit Error Counter register (CANTEC) bit definitions */ +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +/* eCAN Receive Error Counter register (CANREC) bit definitions */ +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */ +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */ +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + + +/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */ +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + + +/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */ +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */ +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + + +/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */ +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + + +/* eCAN TX I/O Control Register (CANTIOC) bit definitions */ +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +/* eCAN RX I/O Control Register (CANRIOC) bit definitions */ +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + + +/* eCAN Time-out Control register (CANTOC) bit definitions */ +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + + +/* eCAN Time-out Status register (CANTOS) bit definitions */ +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +/**************************************/ +/* eCAN Control & Status register file */ +/**************************************/ + +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status + +}; + +/* --------------------------------------------------- */ +/* eCAN Mailbox Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Message ID (MSGID) bit definitions */ +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +/* eCAN Message Control Register (MSGCTRL) bit definitions */ +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +/* eCAN Message Data Register low (MDR_L) word definitions */ +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_L) byte definitions */ +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + + +/* Allow access to the bit fields or entire register */ + +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + + + +/* eCAN Message Data Register high (MDR_H) word definitions */ +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_H) byte definitions */ +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +/* Allow access to the bit fields or entire register */ +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +/**************************************/ +/* eCAN Mailboxes */ +/**************************************/ + +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +/* eCAN Local Acceptance Mask (LAM) bit definitions */ +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +/* Allow access to the bit fields or entire register */ +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + + +/**************************************/ +/* eCAN Local Acceptance Masks */ +/**************************************/ + +/* eCAN LAM File */ +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +/* Mailbox MOTS File */ + +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +/* Mailbox MOTO File */ + +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + + +//--------------------------------------------------------------------------- +// eCAN External References & Function Declarations: +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECap.h b/v120/DSP2833x_headers/include/DSP2833x_ECap.h new file mode 100644 index 0000000..b82bd7f --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECap.h @@ -0,0 +1,151 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture control register 1 bit definitions */ +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + + +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +//---------------------------------------------------- +// Capture control register 2 bit definitions */ +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + + +//---------------------------------------------------- +// ECAP interrupt enable register bit definitions */ +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +//---------------------------------------------------- +// ECAP interrupt flag register bit definitions */ +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + + +//---------------------------------------------------- + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_EPwm.h b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h new file mode 100644 index 0000000..9195752 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h @@ -0,0 +1,423 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Time base control register bit definitions */ +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +//---------------------------------------------------- +// Time base status register bit definitions */ +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +//---------------------------------------------------- +// Compare control register bit definitions */ +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier register bit definitions */ +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier SW force register bit definitions */ +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier continuous SW force register bit definitions */ +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + + +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +//---------------------------------------------------- +// Dead-band generator control register bit definitions +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone select register bit definitions +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone flag register bit definitions */ +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag clear register bit definitions */ +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag force register bit definitions */ +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger select register bit definitions */ +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger pre-scale register bit definitions */ +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Flag register bit definitions */ +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger Clear register bit definitions */ +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Force register bit definitions */ +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; +//---------------------------------------------------- +// PWM chopper control register bit definitions */ +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + + +struct TBPHS_HRPWM_REG { // bits description + Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) + Uint16 TBPHS; // 31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_EQep.h b/v120/DSP2833x_headers/include/DSP2833x_EQep.h new file mode 100644 index 0000000..c330165 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_EQep.h @@ -0,0 +1,242 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture decoder control register bit definitions */ +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + + +//---------------------------------------------------- +// QEP control register bit definitions */ +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Quadrature capture control register bit definitions */ +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + + + +//---------------------------------------------------- +// Position compare control register bit definitions */ +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt control register bit definitions */ +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + + +//---------------------------------------------------- +// QEP interrupt status register bit definitions */ +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt force register bit definitions */ +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +//---------------------------------------------------- +// QEP status register bit definitions */ +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +//---------------------------------------------------- + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Gpio.h b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h new file mode 100644 index 0000000..5759c81 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h @@ -0,0 +1,391 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// GPIO A control register bit definitions */ +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO B control register bit definitions */ +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A Qual/MUX select register bit definitions */ +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */ +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + + + + +//---------------------------------------------------- +// GPIO Xint1/XINT2/XNMI select register bit definitions */ +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) + union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) + union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63) + union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63) + union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95) + union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95) + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select +}; + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_I2c.h b/v120/DSP2833x_headers/include/DSP2833x_I2c.h new file mode 100644 index 0000000..382c12d --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_I2c.h @@ -0,0 +1,193 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//---------------------------------------------------- +// I2C interrupt vector register bit definitions */ +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +//---------------------------------------------------- +// I2C interrupt mask register bit definitions */ +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +//---------------------------------------------------- +// I2C status register bit definitions */ +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + + +//---------------------------------------------------- +// I2C mode control register bit definitions */ +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +//---------------------------------------------------- +// I2C pre-scaler register bit definitions */ +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + + +//---------------------------------------------------- +// TX FIFO control register bit definitions */ +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved + +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +//---------------------------------------------------- +// RX FIFO control register bit definitions */ +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + + +//---------------------------------------------------- + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + Uint16 rsvd1; // reserved + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct I2C_REGS I2caRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h new file mode 100644 index 0000000..05e4af9 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h @@ -0,0 +1,715 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// McBSP Individual Register Bit Definitions: +// +// McBSP DRR2 register bit definitions: +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// McBSP DRR1 register bit definitions: +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// McBSP DXR2 register bit definitions: +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// McBSP DXR1 register bit definitions: +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// SPCR2 control register bit definitions: +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// SPCR1 control register bit definitions: +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 ABIS:1; // 6 ABIS mode select + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// RCR2 control register bit definitions: +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// RCR1 control register bit definitions: +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// XCR2 control register bit definitions: + +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// XCR1 control register bit definitions: +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// SRGR2 Sample rate generator control register bit definitions: +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// SRGR1 control register bit definitions: +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// MCR2 Multichannel control register bit definitions: +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// MCR1 Multichannel control register bit definitions: +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// RCERA control register bit definitions: +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// RCERB control register bit definitions: +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// XCERA control register bit definitions: +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// XCERB control register bit definitions: +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// PCR control register bit definitions: +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// RCERC control register bit definitions: +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// RCERD control register bit definitions: +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// XCERC control register bit definitions: +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// XCERD control register bit definitions: +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// RCERE control register bit definitions: +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// RCERF control register bit definitions: +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// XCERF control register bit definitions: +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// RCERG control register bit definitions: +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// XCERG control register bit definitions: +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// XCERH control register bit definitions: +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + + +// McBSP Interrupt enable register for RINT/XINT +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// McBSP Register File: +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT + Uint16 rsvd2; // reserved +}; + +//--------------------------------------------------------------------------- +// McBSP External References & Function Declarations: +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h new file mode 100644 index 0000000..1ab6e9d --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h @@ -0,0 +1,153 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Control Register Bit Definitions: +// +// PIECTRL: Register bit definitions: +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// PIEIER: Register bit definitions: +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// PIEIFR: Register bit definitions: +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// PIEACK: Register bit definitions: +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +//--------------------------------------------------------------------------- +// PIE Control Register File: +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +//--------------------------------------------------------------------------- +// PIE Control Registers External References & Function Declarations: +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieVect.h b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h new file mode 100644 index 0000000..acddab7 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h @@ -0,0 +1,208 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// +// Create a user type called PINT (pointer to interrupt): + +typedef interrupt void(*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + +// Reset is never fetched from this table. +// It will always be fetched from 0x3FFFC0 in +// boot ROM + + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + +// Non-Peripheral Interrupts: + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + +// Group 1 PIE Peripheral Vectors: + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + +// Group 2 PIE Peripheral Vectors: + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + +// Group 3 PIE Peripheral Vectors: + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + +// Group 4 PIE Peripheral Vectors: + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + +// Group 5 PIE Peripheral Vectors: + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + +// Group 6 PIE Peripheral Vectors: + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + +// Group 7 PIE Peripheral Vectors: + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + +// Group 8 PIE Peripheral Vectors: + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + +// Group 9 PIE Peripheral Vectors: + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + +// Group 10 PIE Peripheral Vectors: + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + +// Group 11 PIE Peripheral Vectors: + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + +// Group 12 PIE Peripheral Vectors: + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table External References & Function Declarations: +// +extern struct PIE_VECT_TABLE PieVectTable; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Sci.h b/v120/DSP2833x_headers/include/DSP2833x_Sci.h new file mode 100644 index 0000000..7c17822 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Sci.h @@ -0,0 +1,235 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions + +//---------------------------------------------------------- +// SCICCR communication control register bit definitions: +// + +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +//------------------------------------------- +// SCICTL1 control register 1 bit definitions: +// + +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved + +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +//--------------------------------------------- +// SCICTL2 control register 2 bit definitions: +// + +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved + +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +//--------------------------------------------------- +// SCIRXST Receiver status register bit definitions: +// + +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +//---------------------------------------------------- +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions: +// + +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +//-------------------------------------------------- +// SCIPRI Priority control register bit definitions: +// +// + +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +//------------------------------------------------- +// SCI FIFO Transmit register bit definitions: +// +// + +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels + +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +//------------------------------------------------ +// SCI FIFO recieve register bit definitions: +// +// + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// SCI FIFO control register bit definitions: +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SCI Register File: +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Spi.h b/v120/DSP2833x_headers/include/DSP2833x_Spi.h new file mode 100644 index 0000000..1325c59 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Spi.h @@ -0,0 +1,183 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: +// +// SPI FIFO Transmit register bit definitions: +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO recieve register bit definitions: +// +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO control register bit definitions: +// +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +//--------------------------------------------- +// SPI configuration register bit definitions: +// +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +//------------------------------------------------- +// SPI operation control register bit definitions: +// +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +//-------------------------------------- +// SPI status register bit definitions: +// +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +//------------------------------------------------ +// SPI priority control register bit definitions: +// +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SPI Register File: +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h new file mode 100644 index 0000000..f8bc343 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h @@ -0,0 +1,383 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// System Control Individual Register Bit Definitions: +// + + +// PLL Status Register +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// High speed peripheral clock register bit definitions: +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// Low speed peripheral clock register bit definitions: +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// Peripheral clock control register 0 bit definitions: +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// Peripheral clock control register 1 bit definitions: +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + + +// Peripheral clock control register 2 bit definitions: +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + + + +// PLL control register bit definitions: +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// Low Power Mode 0 control register bit definitions: +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// Dual-mapping configuration register bit definitions: +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +//--------------------------------------------------------------------------- +// System Control Register File: +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + Uint16 SCSR; // 18: System control and status register + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + Uint16 WDCR; // 25: WD timer control register + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + + +/* --------------------------------------------------- */ +/* CSM Registers */ +/* */ +/* ----------------------------------------------------*/ + +/* CSM Status & Control register bit definitions */ +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit + +}; + +/* Allow access to the bit fields or entire register */ +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +/* CSM Register File */ +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +/* Password locations */ +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + + + +/* Flash Registers */ + +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + + +/* Flash Option Register bit definitions */ +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +/* Flash Power Modes Register bit definitions */ +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + + +/* Flash Status Register bit definitions */ +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +/* Flash Sleep to Standby Wait Counter Register bit definitions */ +struct FSTDBYWAIT_BITS { // bit description + Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +/* Flash Standby to Active Wait Counter Register bit definitions */ +struct FACTIVEWAIT_BITS { // bit description + Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +/* Bank Read Access Wait State Register bit definitions */ +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +/* OTP Read Access Wait State Register bit definitions */ +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register + union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +//--------------------------------------------------------------------------- +// System Control External References & Function Declarations: +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h new file mode 100644 index 0000000..6f860f6 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + + + + +//--------------------------------------------------------------------------- +// External Interrupt Register File: +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +//--------------------------------------------------------------------------- +// External Interrupt References & Function Declarations: +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Xintf.h b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h new file mode 100644 index 0000000..cb68744 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h @@ -0,0 +1,120 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 20, 2007 16:34:08 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +// XINTF timing register bit definitions: +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// XINTF control register bit definitions: +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// XINTF bank switching register bit definitions: +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// XINTF Register File: +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +//--------------------------------------------------------------------------- +// XINTF External References & Function Declarations: +// +extern volatile struct XINTF_REGS XintfRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..d7cd332 --- /dev/null +++ b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,444 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: June 2, 2008 11:12:33 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + + + + + + + +