From b8a0477c5cfd116e7b667ec976daf2ce28247a95 Mon Sep 17 00:00:00 2001 From: nelolik Date: Mon, 15 Feb 2021 09:56:02 +0300 Subject: [PATCH] =?UTF-8?q?init=20commit.=20=D0=9F=D1=80=D0=BE=D0=B5=D0=BA?= =?UTF-8?q?=D1=82=20=D0=BA=D0=B0=D0=BA=D0=B8=D0=BC=20=D0=BE=D0=BD=20=D0=B4?= =?UTF-8?q?=D0=BE=D1=81=D1=82=D0=B0=D0=BB=D1=81=D1=8F=20=D0=BE=D1=82=20?= =?UTF-8?q?=D0=94=D0=B8=D0=BC=D1=8B.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 1 + ADC.c | 253 + ADC.h | 6 + F28335.cmd | 206 + GPIO_table.h | 194 + RS485.c | 553 ++ RS485.h | 138 + bin/HEX2BIN.EXE | Bin 0 -> 111104 bytes bin/create_rs.bat | 5 + bin/hex2000.exe | Bin 0 -> 770048 bytes bin/ice.bin | Bin 0 -> 31284 bytes bin/ice.hex | 981 +++ bin/ice.map | 33 + bin/ice.out | Bin 0 -> 228274 bytes bios.c | 450 ++ bios_dsp.h | 120 + cc_build_Debug.log | 3 + cntrl_adr.c | 43 + cntrl_adr.h | 44 + crc16.c | 221 + crc16.h | 10 + create_rs.bat | 5 + ecan.c | 355 + ecan.h | 3 + filter_bat2.c | 19 + filter_bat2.h | 49 + i2c.c | 142 + i2c.h | 4 + ice.CS_/FILE.CDX | Bin 0 -> 3072 bytes ice.CS_/FILE.DBF | Bin 0 -> 2898 bytes ice.CS_/FILE.FPT | Bin 0 -> 4178 bytes ice.CS_/SYMBOL.CDX | Bin 0 -> 542208 bytes ice.CS_/SYMBOL.DBF | Bin 0 -> 421019 bytes ice.CS_/SYMBOL.FPT | Bin 0 -> 687650 bytes ice.paf2 | Bin 0 -> 21979 bytes ice.pjt | 71 + ice.sbl | Bin 0 -> 13745 bytes isolatio.c | 148 + isolatio.h | 13 + kanal.c | 164 + kanal.h | 7 + log_to_mem.c | 34 + log_to_mem.h | 48 + main.c | 180 + measure.c | 656 ++ measure.h | 136 + message.c | 355 + message.h | 51 + package.h | 56 + peripher.c | 143 + peripher.h | 28 + spise2p.c | 471 ++ spise2p.h | 134 + test.c | 183 + test.h | 17 + tools.c | 84 + tools.h | 26 + v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd | 176 + v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd | 178 + v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd | 176 + v120/DSP2833x_common/cmd/F28332.cmd | 197 + v120/DSP2833x_common/cmd/F28334.cmd | 203 + v120/DSP2833x_common/cmd/F28335.cmd | 203 + v120/DSP2833x_common/gel/f28232.gel | 2822 ++++++++ v120/DSP2833x_common/gel/f28234.gel | 2930 +++++++++ v120/DSP2833x_common/gel/f28235.gel | 2939 +++++++++ v120/DSP2833x_common/gel/f28332.gel | 2845 ++++++++ v120/DSP2833x_common/gel/f28334.gel | 2951 +++++++++ v120/DSP2833x_common/gel/f28335.gel | 2960 +++++++++ .../include/DSP2833x_DefaultIsr.h | 147 + .../include/DSP2833x_Dma_defines.h | 81 + .../include/DSP2833x_EPwm_defines.h | 164 + .../include/DSP2833x_Examples.h | 141 + .../include/DSP2833x_GlobalPrototypes.h | 207 + .../include/DSP2833x_I2c_defines.h | 117 + .../include/DSP2833x_SWPrioritizedIsrLevels.h | 5850 +++++++++++++++++ v120/DSP2833x_common/include/DSP28x_Project.h | 22 + v120/DSP2833x_common/include/IQmathLib.h | 4493 +++++++++++++ v120/DSP2833x_common/include/SFO.h | 52 + v120/DSP2833x_common/include/SFO_V5.h | 70 + v120/DSP2833x_common/lib/IQmath.lib | Bin 0 -> 625984 bytes v120/DSP2833x_common/lib/IQmath_fpu32.lib | Bin 0 -> 861356 bytes v120/DSP2833x_common/lib/SFO_TI_Build.lib | Bin 0 -> 5822 bytes v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib | Bin 0 -> 26482 bytes v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib | Bin 0 -> 26264 bytes .../lib/SFO_TI_Build_V5B_fpu.lib | Bin 0 -> 25918 bytes .../lib/SFO_TI_Build_V5_fpu.lib | Bin 0 -> 26016 bytes v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib | Bin 0 -> 25944 bytes .../source/DSP2833x_ADC_cal.asm | 42 + v120/DSP2833x_common/source/DSP2833x_Adc.c | 65 + .../source/DSP2833x_CSMPasswords.asm | 67 + .../source/DSP2833x_CodeStartBranch.asm | 86 + .../source/DSP2833x_CpuTimers.c | 115 + .../source/DSP2833x_DBGIER.asm | 28 + v120/DSP2833x_common/source/DSP2833x_DMA.c | 590 ++ .../source/DSP2833x_DefaultIsr.c | 1187 ++++ .../source/DSP2833x_DisInt.asm | 65 + v120/DSP2833x_common/source/DSP2833x_ECan.c | 404 ++ v120/DSP2833x_common/source/DSP2833x_ECap.c | 255 + v120/DSP2833x_common/source/DSP2833x_EPwm.c | 316 + v120/DSP2833x_common/source/DSP2833x_EQep.c | 154 + v120/DSP2833x_common/source/DSP2833x_Gpio.c | 69 + v120/DSP2833x_common/source/DSP2833x_I2C.c | 76 + v120/DSP2833x_common/source/DSP2833x_Mcbsp.c | 349 + .../DSP2833x_common/source/DSP2833x_MemCopy.c | 45 + .../DSP2833x_common/source/DSP2833x_PieCtrl.c | 83 + .../DSP2833x_common/source/DSP2833x_PieVect.c | 204 + .../source/DSP2833x_SWPrioritizedDefaultIsr.c | 1863 ++++++ .../source/DSP2833x_SWPrioritizedPieVect.c | 511 ++ v120/DSP2833x_common/source/DSP2833x_Sci.c | 168 + v120/DSP2833x_common/source/DSP2833x_Spi.c | 107 + .../DSP2833x_common/source/DSP2833x_SysCtrl.c | 389 ++ v120/DSP2833x_common/source/DSP2833x_Xintf.c | 242 + .../source/DSP2833x_usDelay.asm | 76 + .../adc_dma/Example_2833xAdcToDMA.c | 212 + .../adc_dma/Example_2833xAdcToDMA.gel | 36 + .../adc_dma/Example_2833xAdcToDMA.pjt | 47 + .../Example_2833xAdcSeq_ovdTest.c | 266 + .../Example_2833xAdcSeq_ovdTest.gel | 39 + .../Example_2833xAdcSeq_ovdTest.pjt | 45 + .../Example_2833xAdcSeqModeTest.c | 164 + .../Example_2833xAdcSeqModeTest.gel | 37 + .../Example_2833xAdcSeqModeTest.pjt | 45 + .../adc_soc/Example_2833xAdcSoc.c | 203 + .../adc_soc/Example_2833xAdcSoc.gel | 40 + .../adc_soc/Example_2833xAdcSoc.pjt | 46 + .../cpu_timer/Example_2833xCpuTimer.c | 189 + .../cpu_timer/Example_2833xCpuTimer.gel | 43 + .../cpu_timer/Example_2833xCpuTimer.pjt | 46 + .../Example_2833xDMA_ram_to_ram.c | 189 + .../Example_2833xDMA_ram_to_ram.gel | 36 + .../Example_2833xDMA_ram_to_ram.pjt | 47 + .../Example_2833xDMA_xintf_to_ram.c | 242 + .../Example_2833xDMA_xintf_to_ram.gel | 36 + .../Example_2833xDMA_xintf_to_ram.pjt | 48 + .../Example_2833xEcanA_to_B_Xmit.c | 187 + .../Example_2833xEcanA_to_B_Xmit.gel | 37 + .../Example_2833xEcanA_to_B_Xmit.pjt | 45 + .../Example_2833xECanBack2Back.c | 309 + .../Example_2833xECanBack2Back.gel | 43 + .../Example_2833xECanBack2Back.pjt | 45 + .../ecap_apwm/Example_2833xECap_apwm.c | 223 + .../ecap_apwm/Example_2833xECap_apwm.gel | 39 + .../ecap_apwm/Example_2833xECap_apwm.pjt | 46 + .../Example_2833xECap_Capture_Pwm.c | 288 + .../Example_2833xECap_Capture_Pwm.gel | 46 + .../Example_2833xECap_Capture_Pwm.pjt | 47 + .../epwm_deadband/Example_2833xEPwmDeadBand.c | 457 ++ .../Example_2833xEPwmDeadBand.pjt | 46 + .../Example_2833xEPwmDeadband.gel | 39 + .../epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd | 183 + .../DSP2833x_EPWMDM_Headers_nonBIOS.cmd | 182 + .../epwm_dma/Example_2833xEPwm_DMA.c | 455 ++ .../epwm_dma/Example_2833xEPwm_DMA.gel | 43 + .../epwm_dma/Example_2833xEPwm_DMA.pjt | 46 + .../Example_2833xEPwmTimerInt.c | 360 + .../Example_2833xEPwmTimerInt.gel | 47 + .../Example_2833xEPwmTimerInt.pjt | 45 + .../Example_2833xEPwmTripZone.c | 305 + .../Example_2833xEPwmTripZone.gel | 40 + .../Example_2833xEPwmTripZone.pjt | 46 + .../epwm_up_aq/Example_2833xEPwmUpAQ.c | 490 ++ .../epwm_up_aq/Example_2833xEPwmUpAQ.gel | 41 + .../epwm_up_aq/Example_2833xEPwmUpAQ.pjt | 46 + .../Example_2833xEPwmUpDownAQ.c | 499 ++ .../Example_2833xEPwmUpDownAQ.gel | 40 + .../Example_2833xEPwmUpDownAQ.pjt | 46 + .../eqep_freqcal/Example_2833xEqep_freqcal.c | 178 + .../Example_2833xEqep_freqcal.gel | 37 + .../Example_2833xEqep_freqcal.pjt | 49 + .../eqep_freqcal/Example_EPwmSetup.c | 76 + .../eqep_freqcal/Example_freqcal.c | 186 + .../eqep_freqcal/Example_freqcal.h | 112 + .../eqep_freqcal/Example_freqcal.xls | Bin 0 -> 16896 bytes .../Example_2833xEqep_pos_speed.c | 201 + .../Example_2833xEqep_pos_speed.gel | 39 + .../Example_2833xEqep_pos_speed.pjt | 56 + .../eqep_pos_speed/Example_EPwmSetup.c | 69 + .../eqep_pos_speed/Example_posspeed.c | 245 + .../eqep_pos_speed/Example_posspeed.h | 85 + .../eqep_pos_speed/Example_posspeed.xls | Bin 0 -> 16896 bytes .../Example_2833xExternalInterrupt.c | 260 + .../Example_2833xExternalInterrupt.gel | 41 + .../Example_2833xExternalInterrupt.pjt | 44 + .../flash/Example_28332_Flash.gel | 45 + .../flash/Example_28332_Flash.pjt | 46 + .../flash/Example_28334_Flash.gel | 45 + .../flash/Example_28334_Flash.pjt | 46 + .../flash/Example_28335_Flash.gel | 45 + .../flash/Example_28335_Flash.pjt | 46 + .../flash/Example_2833xFlash.c | 342 + v120/DSP2833x_examples/fpu/Example_2833xFPU.c | 167 + .../fpu/Example_2833xFPU.gel | 50 + .../fpu/Example_2833xFPU_hardware.pjt | 46 + .../fpu/Example_2833xFPU_software.pjt | 46 + .../gpio_setup/Example_2833xGpioSetup.c | 458 ++ .../gpio_setup/Example_2833xGpioSetup.gel | 35 + .../gpio_setup/Example_2833xGpioSetup.pjt | 44 + .../gpio_toggle/Example_2833xGpioToggle.c | 245 + .../gpio_toggle/Example_2833xGpioToggle.gel | 36 + .../gpio_toggle/Example_2833xGpioToggle.pjt | 44 + .../hrpwm/Example_2833xHRPWM.c | 376 ++ .../hrpwm/Example_2833xHRPWM.gel | 42 + .../hrpwm/Example_2833xHRPWM.pjt | 51 + .../hrpwm_sfo/Example_2833xHRPWM_SFO.c | 546 ++ .../hrpwm_sfo/Example_2833xHRPWM_SFO.gel | 54 + .../hrpwm_sfo/Example_2833xHRPWM_SFO.pjt | 59 + .../hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c | 477 ++ .../Example_2833xHRPWM_SFO_V5.gel | 58 + .../Example_2833xHRPWM_SFO_V5.pjt | 53 + .../hrpwm_slider/Example_2833xHRPWM_slider.c | 381 ++ .../Example_2833xHRPWM_slider.gel | 51 + .../Example_2833xHRPWM_slider.pjt | 51 + .../i2c_eeprom/Example_2833xI2C_eeprom.c | 473 ++ .../i2c_eeprom/Example_2833xI2C_eeprom.gel | 39 + .../i2c_eeprom/Example_2833xI2C_eeprom.pjt | 46 + .../lpm_haltwake/Example_2833xHaltWake.c | 167 + .../lpm_haltwake/Example_2833xHaltWake.gel | 29 + .../lpm_haltwake/Example_2833xHaltWake.pjt | 46 + .../lpm_idlewake/Example_2833xIdleWake.c | 175 + .../lpm_idlewake/Example_2833xIdleWake.gel | 28 + .../lpm_idlewake/Example_2833xIdleWake.pjt | 46 + .../Example_2833xStandbyWake.c | 169 + .../Example_2833xStandbyWake.gel | 29 + .../Example_2833xStandbyWake.pjt | 45 + .../mcbsp_loopback/Example_2833xMcBSP_DLB.c | 244 + .../mcbsp_loopback/Example_2833xMcBSP_DLB.gel | 27 + .../mcbsp_loopback/Example_2833xMcBSP_DLB.pjt | 45 + .../Example_2833xMcBSP_DLB_DMA.c | 403 ++ .../Example_2833xMcBSP_DLB_DMA.gel | 22 + .../Example_2833xMcBSP_DLB_DMA.pjt | 52 + .../Example_2833xMcBSP_DLB_int.c | 221 + .../Example_2833xMcBSP_DLB_int.gel | 27 + .../Example_2833xMcBSP_DLB_int.pjt | 45 + .../Example_2833xMcBSP_SPI_DLB.c | 208 + .../Example_2833xMcBSP_SPI_DLB.gel | 28 + .../Example_2833xMcBSP_SPI_DLB.pjt | 45 + .../sci_autobaud/Example_2833xSci_Autobaud.c | 390 ++ .../Example_2833xSci_Autobaud.gel | 48 + .../Example_2833xSci_Autobaud.pjt | 45 + .../sci_echoback/Example_2833xSci_Echoback.c | 236 + .../Example_2833xSci_Echoback.gel | 40 + .../Example_2833xSci_Echoback.pjt | 45 + v120/DSP2833x_examples/sci_echoback/SCI_96.ht | Bin 0 -> 23333 bytes .../scia_loopback/Example_2833xScia_FFDLB.c | 217 + .../scia_loopback/Example_2833xScia_FFDLB.gel | 42 + .../scia_loopback/Example_2833xScia_FFDLB.pjt | 45 + .../Example_2833xSci_FFDLB_int.c | 329 + .../Example_2833xSci_FFDLB_int.gel | 45 + .../Example_2833xSci_FFDLB_int.pjt | 45 + .../spi_loopback/Example_2833xSpi_FFDLB.c | 184 + .../spi_loopback/Example_2833xSpi_FFDLB.gel | 40 + .../spi_loopback/Example_2833xSpi_FFDLB.pjt | 45 + .../Example_2833xSpi_FFDLB_int.c | 238 + .../Example_2833xSpi_FFDLB_int.gel | 40 + .../Example_2833xSpi_FFDLB_int.pjt | 45 + .../Example_2833xSWPrioritizedDefaultIsr.c | 1879 ++++++ .../Example_2833xSWPrioritizedInterrupts.c | 597 ++ .../Example_2833xSWPrioritizedInterrupts.gel | 37 + .../Example_2833xSWPrioritizedInterrupts.pjt | 44 + .../timed_led_blink/Example_2833xLEDBlink.c | 161 + .../timed_led_blink/Example_2833xLEDBlink.gel | 38 + .../timed_led_blink/Example_2833xLEDBlink.pjt | 46 + .../watchdog/Example_2833xWatchdog.c | 176 + .../watchdog/Example_2833xWatchdog.gel | 41 + .../watchdog/Example_2833xWatchdog.pjt | 44 + .../xintf_run_from/28335_RAM_xintf_lnk.cmd | 167 + .../Example_2833xCodeRunFromXintf.c | 256 + .../Example_2833xCodeRunFromXintf.pjt | 62 + .../Example_2833xRunFromXintf.gel | 37 + .../cmd/DSP2833x_Headers_BIOS.cmd | 183 + .../cmd/DSP2833x_Headers_nonBIOS.cmd | 183 + .../gel/DSP2833x_DualMap_EPWM.gel | 237 + .../gel/DSP2833x_Peripheral.gel | 249 + v120/DSP2833x_headers/include/DSP2833x_Adc.h | 264 + .../include/DSP2833x_CpuTimers.h | 190 + v120/DSP2833x_headers/include/DSP2833x_DMA.h | 295 + .../include/DSP2833x_DevEmu.h | 97 + .../include/DSP2833x_Device.h | 366 ++ v120/DSP2833x_headers/include/DSP2833x_ECan.h | 1161 ++++ v120/DSP2833x_headers/include/DSP2833x_ECap.h | 151 + v120/DSP2833x_headers/include/DSP2833x_EPwm.h | 423 ++ v120/DSP2833x_headers/include/DSP2833x_EQep.h | 242 + v120/DSP2833x_headers/include/DSP2833x_Gpio.h | 391 ++ v120/DSP2833x_headers/include/DSP2833x_I2c.h | 193 + .../DSP2833x_headers/include/DSP2833x_Mcbsp.h | 715 ++ .../include/DSP2833x_PieCtrl.h | 153 + .../include/DSP2833x_PieVect.h | 208 + v120/DSP2833x_headers/include/DSP2833x_Sci.h | 235 + v120/DSP2833x_headers/include/DSP2833x_Spi.h | 183 + .../include/DSP2833x_SysCtrl.h | 383 ++ .../include/DSP2833x_XIntrupt.h | 83 + .../DSP2833x_headers/include/DSP2833x_Xintf.h | 120 + .../source/DSP2833x_GlobalVariableDefs.c | 444 ++ 294 files changed, 72365 insertions(+) create mode 100644 .gitignore create mode 100644 ADC.c create mode 100644 ADC.h create mode 100644 F28335.cmd create mode 100644 GPIO_table.h create mode 100644 RS485.c create mode 100644 RS485.h create mode 100644 bin/HEX2BIN.EXE create mode 100644 bin/create_rs.bat create mode 100644 bin/hex2000.exe create mode 100644 bin/ice.bin create mode 100644 bin/ice.hex create mode 100644 bin/ice.map create mode 100644 bin/ice.out create mode 100644 bios.c create mode 100644 bios_dsp.h create mode 100644 cc_build_Debug.log create mode 100644 cntrl_adr.c create mode 100644 cntrl_adr.h create mode 100644 crc16.c create mode 100644 crc16.h create mode 100644 create_rs.bat create mode 100644 ecan.c create mode 100644 ecan.h create mode 100644 filter_bat2.c create mode 100644 filter_bat2.h create mode 100644 i2c.c create mode 100644 i2c.h create mode 100644 ice.CS_/FILE.CDX create mode 100644 ice.CS_/FILE.DBF create mode 100644 ice.CS_/FILE.FPT create mode 100644 ice.CS_/SYMBOL.CDX create mode 100644 ice.CS_/SYMBOL.DBF create mode 100644 ice.CS_/SYMBOL.FPT create mode 100644 ice.paf2 create mode 100644 ice.pjt create mode 100644 ice.sbl create mode 100644 isolatio.c create mode 100644 isolatio.h create mode 100644 kanal.c create mode 100644 kanal.h create mode 100644 log_to_mem.c create mode 100644 log_to_mem.h create mode 100644 main.c create mode 100644 measure.c create mode 100644 measure.h create mode 100644 message.c create mode 100644 message.h create mode 100644 package.h create mode 100644 peripher.c create mode 100644 peripher.h create mode 100644 spise2p.c create mode 100644 spise2p.h create mode 100644 test.c create mode 100644 test.h create mode 100644 tools.c create mode 100644 tools.h create mode 100644 v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd create mode 100644 v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd create mode 100644 v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd create mode 100644 v120/DSP2833x_common/cmd/F28332.cmd create mode 100644 v120/DSP2833x_common/cmd/F28334.cmd create mode 100644 v120/DSP2833x_common/cmd/F28335.cmd create mode 100644 v120/DSP2833x_common/gel/f28232.gel create mode 100644 v120/DSP2833x_common/gel/f28234.gel create mode 100644 v120/DSP2833x_common/gel/f28235.gel create mode 100644 v120/DSP2833x_common/gel/f28332.gel create mode 100644 v120/DSP2833x_common/gel/f28334.gel create mode 100644 v120/DSP2833x_common/gel/f28335.gel create mode 100644 v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_Dma_defines.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_Examples.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_I2c_defines.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h create mode 100644 v120/DSP2833x_common/include/DSP28x_Project.h create mode 100644 v120/DSP2833x_common/include/IQmathLib.h create mode 100644 v120/DSP2833x_common/include/SFO.h create mode 100644 v120/DSP2833x_common/include/SFO_V5.h create mode 100644 v120/DSP2833x_common/lib/IQmath.lib create mode 100644 v120/DSP2833x_common/lib/IQmath_fpu32.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build_V5.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build_V5B.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib create mode 100644 v120/DSP2833x_common/lib/SFO_TI_Build_fpu.lib create mode 100644 v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm create mode 100644 v120/DSP2833x_common/source/DSP2833x_Adc.c create mode 100644 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// DSP281x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP281x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "ADC.h" + +#include "log_to_mem.h" +#include "RS485.h" +#include "filter_bat2.h" + +#include "measure.h" +#include "message.h" +#include "package.h" + +#include "peripher.h" + +#define SIZE_ADC_BUF 1000 +Uint16 ADC_table[24]; +Uint16 raw_table[24]; +Uint16 ConversionCount; + +int MAY=0; + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +void setup_adc() +{ + long CLKdiv,HSPCLKdiv,Rate; + + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + +// Specific clock setting for this example: +// EALLOW; +// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK +// EDIS; + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitAdc(); // For this example, init the ADC + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 +// EINT; // Enable Global interrupt INTM +// ERTM; // Enable Global realtime interrupt DBGM + +// Configure ADC + + if(Desk==dsk_COMM) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1 + + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0B; // Äàëüøå òåìïåðàòóðû + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0A; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x09; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x08; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x00; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x01; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x04; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x03; + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x05; + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x02; + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x06; + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x07; + + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0F; // Òîêè-íàïðÿæåíèÿ + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D; + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E; + AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0C; + + } + + if(Desk==dsk_SHKF) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000E; // Setup 2 conv's on SEQ1 + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x6; // 380 Ô1 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x7; // 380 Ô2 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // 220 Ô1 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // 220 Ô2 ? + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x5; // 31 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x4; // 31 UC + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0xF; // 24 ÏÌ + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0xD; // +24 Äò + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0xB; // -24 Äò + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x8; // 24 ÏÊ + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // 24 ÏÌÓ + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xA; // 24 ÏÓ + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x9; // 15 Äð + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x1; // ÄÒ° 1 + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0; // ÄÒ° 2 + } + + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + +//AdcRegs.ADCTRL1.bit.ACQ_PS=15; +//AdcRegs.ADCTRL1.bit.CPS=1; + + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + + EPwm1Regs.TBCTL.bit.HSPCLKDIV=4; + EPwm1Regs.TBCTL.bit.CLKDIV=1; + + CLKdiv = 1<>4; + + if((sens_type[i]==POWER_380)||(sens_type[i]==POWER_220)) + { + if(Numb>200/*150*/) + { + if(prenumb[i]==0) zero_cownt[i]=0; + zero_cownt[i]+=2; + filtar[i] += ((float)Numb-filtar[i])/100.0; + Numb = filtar[i]; + prenumb[i]=1; + } + else + { + prenumb[i]=0; + if(zero_cownt[i]) + { + zero_cownt[i]--; + continue; + } + } + } + + raw_table[i] = Numb; Temper = Numb; + ADC_table[i] = filterbat(&filter[i],Temper); + + if(sens_type[i]==TERMO_AD) Temper_count(i); + else Power_count(i); + } + sig.all = chk.all; + chk.all = 0; + + if(/*Modbus[127].bit.bitE*/0) + { + Test_mem_limit(16); + for(i=0;i<8;i++) + { + Log_to_mem(raw_table[i]); + Log_to_mem(ADC_table[i]); + } } } +/* + if(Mode==adr_SHKF) + { + for(i=0;i<15;i++) + { + Temper= *((&AdcRegs.ADCRESULT0)+i) >>4; + adc_table_lem[i]=filterbat(&filter[i],Temper); + adc_table_tpl[i]=adc_table_lem[i]; + } + adc_table_lem[15] = ExtraCanal1; + adc_table_lem[16] = ExtraCanal2; + + measure_all(); + } +*/ + if(Desk==dsk_COMM) + { + for(i=0;i<24;i++) + if(sens_type[i]) + { + Temper = *((&AdcRegs.ADCRESULT0)+i) >>4; + + if(sens_type[i] != VOLTAGE) + Temper = filterbat(&filter[i],Temper); + + ADC_table[i]=(int)Temper; + + if(sens_type[i]==VOLTAGE) Current_count(i); + else Temper_count(i); + } + + sig.all = chk.all; + chk.all = 0; + } } + +// Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + return; +} diff --git a/ADC.h b/ADC.h new file mode 100644 index 0000000..7d2de8f --- /dev/null +++ b/ADC.h @@ -0,0 +1,6 @@ +extern int MAY; + +extern Uint16 ADC_table[]; + + +void setup_adc(void); diff --git a/F28335.cmd b/F28335.cmd new file mode 100644 index 0000000..fffa02b --- /dev/null +++ b/F28335.cmd @@ -0,0 +1,206 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */ +/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ +// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */ +/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > RAML0 PAGE = 0 + .pinit : > RAML0 PAGE = 0 + .text : > RAML0 PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = RAML4, + RUN = RAML4, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML5 PAGE = 1 + .esysmem : > RAML0 PAGE = 0 + + .logg : > ZONE7A PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > RAML4 PAGE = 0 + .switch : > RAML4 PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: * / + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 +/* DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 +*/ + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/GPIO_table.h b/GPIO_table.h new file mode 100644 index 0000000..c6cfa83 --- /dev/null +++ b/GPIO_table.h @@ -0,0 +1,194 @@ +#define COMM_gpio00_dir 0UL +#define COMM_gpio01_dir 0UL +#define COMM_gpio02_dir 0UL +#define COMM_gpio03_dir 0UL +#define COMM_gpio04_dir 0UL +#define COMM_gpio05_dir 0UL +#define COMM_gpio06_dir 0UL +#define COMM_gpio07_dir 0UL +#define COMM_gpio08_dir 0UL +#define COMM_gpio09_dir 0UL +#define COMM_gpio10_dir 0UL +#define COMM_gpio11_dir 0UL + +#define COMM_gpio19_dir 1UL // 63 — SPI +#define COMM_gpio20_dir 0UL // 64 2:9B mode 2 +#define COMM_gpio21_dir 0UL // 65 2:9A mode 4 +#define COMM_gpio22_dir 0UL // 66 2:12C mode 1 +#define COMM_gpio23_dir 0UL // 67 2:12B control -24V +#define COMM_gpio24_dir 0UL +#define COMM_gpio25_dir 0UL +#define COMM_gpio26_dir 0UL // 72 2:11B control +24V +#define COMM_gpio27_dir 0UL + +#define COMM_gpio32_dir 1UL // 74 2:10B SDA +#define COMM_gpio33_dir 1UL // 75 2:10C SCL +#define COMM_gpio34_dir 1UL // 142 — SCI + +#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red +#define COMM_gpio49_dir 1UL // 89 2:14B ts2 red +#define COMM_gpio50_dir 0UL +#define COMM_gpio51_dir 0UL // 91 2:13C mode !8 +#define COMM_gpio52_dir 1UL // 94 2:13B ts1 green +#define COMM_gpio53_dir 0UL + +#define COMM_gpio58_dir 1UL // 100 1:13C led term +#define COMM_gpio59_dir 1UL // 110 1:13B gotov +#define COMM_gpio60_dir 1UL // 111 1:13A led job +#define COMM_gpio61_dir 0UL +#define COMM_gpio62_dir 1UL // 113 1:14B alarm +#define COMM_gpio63_dir 1UL // 114 1:14A rez out + +//=========================================================================== + +#define VEPP_gpio00_dir 0UL // 5 2:7A input +#define VEPP_gpio01_dir 0UL // 6 2:4A input +#define VEPP_gpio02_dir 0UL // 7 2:7B input +#define VEPP_gpio03_dir 0UL // 10 2:4B input +#define VEPP_gpio04_dir 0UL // 11 2:7C input +#define VEPP_gpio05_dir 0UL // 12 2:4C input +#define VEPP_gpio06_dir 0UL // 13 2:6A input +#define VEPP_gpio07_dir 0UL // 16 2:3A input +#define VEPP_gpio08_dir 0UL // 17 2:6B input +#define VEPP_gpio09_dir 0UL // 18 2:3B input +#define VEPP_gpio10_dir 0UL // 19 2:6C input +#define VEPP_gpio11_dir 0UL // 20 2:3C input + +#define VEPP_gpio19_dir 1UL // 63 — SPI +#define VEPP_gpio20_dir 0UL // 64 2:9B mode 2 +#define VEPP_gpio21_dir 0UL // 65 2:9A mode 4 +#define VEPP_gpio22_dir 0UL // 66 2:12C mode 1 +#define VEPP_gpio23_dir 0UL // 67 2:12B input +#define VEPP_gpio24_dir 0UL // 68 2:12A input +#define VEPP_gpio25_dir 0UL // 69 2:11C input +#define VEPP_gpio26_dir 0UL // 72 2:11B input +#define VEPP_gpio27_dir 0UL // 73 2:11A input + +#define VEPP_gpio32_dir 0UL // 74 2:10B input +#define VEPP_gpio33_dir 0UL // 75 2:10C input +#define VEPP_gpio34_dir 1UL // 142 — SCI + +#define VEPP_gpio48_dir 1UL // 88 2:14C DIOD red +#define VEPP_gpio49_dir 0UL // 89 2:14B input +#define VEPP_gpio50_dir 0UL // 90 2:14A input +#define VEPP_gpio51_dir 0UL // 91 2:13C mode !8 +#define VEPP_gpio52_dir 0UL // 94 2:13B input +#define VEPP_gpio53_dir 0UL // 95 2:13A input + +#define VEPP_gpio58_dir 0UL // 100 1:13C input +#define VEPP_gpio59_dir 0UL +#define VEPP_gpio60_dir 1UL // 111 1:13A gotov +#define VEPP_gpio61_dir 0UL // 112 1:14C input +#define VEPP_gpio62_dir 1UL // 113 1:14C rezout +#define VEPP_gpio63_dir 1UL // 114 1:14A ledjob + +//=========================================================================== + +#define ISOL_gpio00_dir 0UL // 5 2:7A +#define ISOL_gpio01_dir 0UL // 6 2:4A +#define ISOL_gpio02_dir 0UL // 7 2:7B +#define ISOL_gpio03_dir 0UL // 10 2:4B +#define ISOL_gpio04_dir 0UL // 11 2:7C +#define ISOL_gpio05_dir 0UL // 12 2:4C +#define ISOL_gpio06_dir 0UL // 13 2:6A +#define ISOL_gpio07_dir 0UL // 16 2:3A +#define ISOL_gpio08_dir 0UL // 17 2:6B +#define ISOL_gpio09_dir 0UL // 18 2:3B +#define ISOL_gpio10_dir 0UL // 19 2:6C +#define ISOL_gpio11_dir 0UL // 20 2:3C + +#define ISOL_gpio19_dir 1UL // 63 — SPI +#define ISOL_gpio20_dir 0UL // 64 2:9B mode 2 +#define ISOL_gpio21_dir 0UL // 65 2:9A mode 4 +#define ISOL_gpio22_dir 0UL // 66 2:12C mode 1 +#define ISOL_gpio23_dir 0UL // 67 2:12B opt input 1 +#define ISOL_gpio24_dir 1UL // 68 2:12A led 2 +#define ISOL_gpio25_dir 0UL // 69 2:11C +#define ISOL_gpio26_dir 1UL // 72 2:11B opt out 2 +#define ISOL_gpio27_dir 1UL // 73 2:11A led 1 + +#define ISOL_gpio32_dir 1UL // 74 2:10B opt out 1 +#define ISOL_gpio33_dir 0UL // 75 2:10C +#define ISOL_gpio34_dir 1UL // 142 — SCI + +#define ISOL_gpio48_dir 1UL // 88 2:14C DIOD red +#define ISOL_gpio49_dir 0UL // 89 2:14B +#define ISOL_gpio50_dir 0UL // 90 2:14A +#define ISOL_gpio51_dir 0UL // 91 2:13C mode !8 +#define ISOL_gpio52_dir 0UL // 94 2:13B opt input 2 +#define ISOL_gpio53_dir 1UL // 95 2:13A led 3 + +#define ISOL_gpio58_dir 0UL // 100 1:13C +#define ISOL_gpio59_dir 1UL // 110 1:13B gotov +#define ISOL_gpio60_dir 0UL // 111 1:13A +#define ISOL_gpio61_dir 0UL // 112 1:14C +#define ISOL_gpio62_dir 0UL // 113 1:14C input +#define ISOL_gpio63_dir 0UL // 114 1:14A + +//=========================================================================== + +//=========================================================================== + +#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \ + (COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \ + (COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \ + (COMM_gpio19_dir<<19)+ \ + (COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \ + (COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27); +#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \ + (COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \ + (COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \ + (COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \ + (COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31); + +#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \ + (BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \ + (BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \ + (BKSD_gpio19_dir<<19)+ \ + (BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \ + (BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27); +#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \ + (BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \ + (BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \ + (BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \ + (BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31); + +#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \ + (PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \ + (PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \ + (PULT_gpio19_dir<<19)+ \ + (PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \ + (PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27); +#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \ + (PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \ + (PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \ + (PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \ + (PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31); + +#define VEPP_GPADIR (VEPP_gpio00_dir ) + (VEPP_gpio01_dir<<1) + (VEPP_gpio02_dir<<2) + (VEPP_gpio03_dir<<3) + \ + (VEPP_gpio04_dir<<4) + (VEPP_gpio05_dir<<5) + (VEPP_gpio06_dir<<6) + (VEPP_gpio07_dir<<7) + \ + (VEPP_gpio08_dir<<8) + (VEPP_gpio09_dir<<9) + (VEPP_gpio10_dir<<10)+ (VEPP_gpio11_dir<<11)+ \ + (VEPP_gpio19_dir<<19)+ \ + (VEPP_gpio20_dir<<20)+ (VEPP_gpio21_dir<<21)+ (VEPP_gpio22_dir<<22)+ (VEPP_gpio23_dir<<23)+ \ + (VEPP_gpio24_dir<<24)+ (VEPP_gpio25_dir<<25)+ (VEPP_gpio26_dir<<26)+ (VEPP_gpio27_dir<<27); +#define VEPP_GPBDIR (VEPP_gpio32_dir )+ (VEPP_gpio33_dir<<1) + (VEPP_gpio34_dir<<2 )+ \ + (VEPP_gpio48_dir<<16)+ (VEPP_gpio49_dir<<17)+ (VEPP_gpio50_dir<<18)+ (VEPP_gpio51_dir<<19)+ \ + (VEPP_gpio52_dir<<20)+ (VEPP_gpio53_dir<<21)+ \ + (VEPP_gpio58_dir<<26)+ (VEPP_gpio59_dir<<27)+ \ + (VEPP_gpio60_dir<<28)+ (VEPP_gpio61_dir<<29)+ (VEPP_gpio62_dir<<30)+ (VEPP_gpio63_dir<<31); + +#define ISOL_GPADIR (ISOL_gpio00_dir ) + (ISOL_gpio01_dir<<1) + (ISOL_gpio02_dir<<2) + (ISOL_gpio03_dir<<3) + \ + (ISOL_gpio04_dir<<4) + (ISOL_gpio05_dir<<5) + (ISOL_gpio06_dir<<6) + (ISOL_gpio07_dir<<7) + \ + (ISOL_gpio08_dir<<8) + (ISOL_gpio09_dir<<9) + (ISOL_gpio10_dir<<10)+ (ISOL_gpio11_dir<<11)+ \ + (ISOL_gpio19_dir<<19)+ \ + (ISOL_gpio20_dir<<20)+ (ISOL_gpio21_dir<<21)+ (ISOL_gpio22_dir<<22)+ (ISOL_gpio23_dir<<23)+ \ + (ISOL_gpio24_dir<<24)+ (ISOL_gpio25_dir<<25)+ (ISOL_gpio26_dir<<26)+ (ISOL_gpio27_dir<<27); +#define ISOL_GPBDIR (ISOL_gpio32_dir )+ (ISOL_gpio33_dir<<1) + (ISOL_gpio34_dir<<2 )+ \ + (ISOL_gpio48_dir<<16)+ (ISOL_gpio49_dir<<17)+ (ISOL_gpio50_dir<<18)+ (ISOL_gpio51_dir<<19)+ \ + (ISOL_gpio52_dir<<20)+ (ISOL_gpio53_dir<<21)+ \ + (ISOL_gpio58_dir<<26)+ (ISOL_gpio59_dir<<27)+ \ + (ISOL_gpio60_dir<<28)+ (ISOL_gpio61_dir<<29)+ (ISOL_gpio62_dir<<30)+ (ISOL_gpio63_dir<<31); + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/RS485.c b/RS485.c new file mode 100644 index 0000000..4e57f4a --- /dev/null +++ b/RS485.c @@ -0,0 +1,553 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + RS485.ñ + **************************************************************** + * Ïðîöåäóðû ðàáîòû ñ UART * + ****************************************************************/ + +//#include "big_dsp_module.h" + + +#include "DSP2833x_Device.h" +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "bios_dsp.h" +#include "cntrl_adr.h" + +#include "tools.h" + +//#include "flash_tools.h" + + +RS_DATA rs_a,rs_b; + +unsigned int RS_Len[70]={0}; + +static char size_cmd15=1; + +void RS_RX_Handler(RS_DATA *rs_arr); +void RS_TX_Handler(RS_DATA *rs_arr); + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */ +interrupt void RSA_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_RX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_RX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSA_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_TX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_TX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */ +void RS_RX_Handler(RS_DATA *rs_arr) +{ + char Rc; + char RS_BytePtr; + +// led1_on(); + + for(;;) // 'goto' ýòî íå îïåðàòîð àçûêà Ñ + { + if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag + { + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + return; // êñòàòè ýòî åäèíñòâåííûé âûõîä èç ïðåðûâàíèà + } + + Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // ×èòàåì ñèìâîë â ëþáîì ñëó÷àå + + if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag + { + rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI + rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + + continue; + } + + if(rs_arr->RS_DataReady) continue; // Íå çàáðàëè äàííûå + + if (rs_arr->RS_Flag9bit==1) // äëà RS485???????? + { + // Èíèöèàëèçèðóåì ïåðåìåííûå è ôëàãè + rs_arr->RS_FlagBegin = true; // Æäåì çàãîëîâîê + rs_arr->RS_RecvLen = 0; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_HeaderCnt = 0; + rs_arr->RS_Cmd = 0; + } + + if(rs_arr->RS_FlagSkiping) continue; // Íå íàì + + if (rs_arr->RS_FlagBegin) // Çàãîëîâîê + { + if (rs_arr->RS_HeaderCnt==0) // Àäðåñ êîíòðîëëåðà èëè ñòàíäàðòíàà êîìàíäà + { + if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING) + || ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING)) + + { + rs_arr->addr_recive=Rc; // çàïîìíèëè àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Ïåðâûé áàéò + RS_SetBitMode(rs_arr,8); // ïåðåñòðîèëèñü â 8-áèò ðåæèì + } + else + { + rs_arr->RS_FlagSkiping = true; // Íå íàøåìó êîíòðîëëåðó + rs_arr->RS_FlagBegin = false; // îñòàëèñü â 9-áèò ðåæèìå +// led1_off(); + } + } + else + { + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Âòîðîé áàéò è ò.ä. + + if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING) + { + RS_Len[CMD_MODBUS_16] = (10+Rc); + } + + // åñëè âòîðîé áàéò - ýòî êîìàíäà + if (rs_arr->RS_HeaderCnt == 2) + { + rs_arr->RS_Cmd = Rc; + // Ïðîâåðêà äëèíû ïîñûëêè + // CMD_LOAD - ìëàäøàà íà äàííûé ìîìåíò + // CMD_STD_ANS - ñòàðøàà íà äàííûé ìîìåíò + if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3) + || ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD)) + ) + { + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_HeaderCnt = 0; // Ïîòîìó ÷òî êîìàíäà íå òà + rs_arr->RS_FlagBegin = true; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_Cmd=0; +// led1_off(); + continue; + } + if (rs_arr->RS_Cmd == CMD_LOAD) // Äëà ýòîé êîìàíäû çàãîëîâîê î÷åíü êîðîòêèé + rs_arr->RS_FlagBegin = false;// äàëüøå èäóò äàííûå + } + + if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) || + (rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header))) + { // Ïîëó÷èëè çàãîëîâîê + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_FlagBegin = false; + rs_arr->RS_FlagSkiping = true; + rs_arr->RS_DataReady = true; + rs_arr->RS_Cmd=0; +// led1_off(); + } } } + else // Ïîòîê äàííûõ + { + if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End) + { + rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé + rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé + } + if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // Ìû çäåñü îêàçàëèñü ïî êàêîé-òî ÷óäîâèùíîé îøèáêå + + if(rs_arr->RS_DataReady) // Åñëè äàííûå â îñíîâíîì öèêëå íå çàáðàíû, + { // òî ïðîïóñêàåì ñëåäóþùóþ ïîñûëêó + rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà +// led1_off(); + continue; + } + RS_BytePtr = rs_arr->RS_RecvLen++ % 2; + if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // Ïîëó÷èëè ñëîâî + else *rs_arr->pRS_RecvPtr = Rc<<8; + + if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // Êîíåö ïîñûëêè + { + rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD; + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå äàííûå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà + rs_arr->RS_DataReady = true; // Ôëàã â îñíîâíîé öèêë - äàííûå ïîëó÷åíû +// led1_off(); +} } } } + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïîñëàíî */ +void RS_TX_Handler(RS_DATA *rs_arr) +{ + char RS_BytePtr; +// unsigned int i; + + if(rs_arr->RS_SendBlockMode == BM_CHAR32) + { + if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + } + SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++)); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ + + RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/ + RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */ + + rs_arr->flag_TIMEOUT_to_Send=false; /* ñáðîñèëè ôëàã îæèäàíèà òàéìàóòà */ + } + } + else /* BM_PACKED */ + { + + RS_BytePtr = (rs_arr->RS_SendLen++) % 2; + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + } + if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) )); + else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr )); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ +// RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/ +// RS_Line_to_receive(); /* ðåæèì ïðèåìà RS485 */ + + } + } + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; +// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag +} + +/** Èíèöèàëèçàöèà ìàññèâà äëèí êîìàíä */ +void setup_arr_cmd_length() +{ + int i; + + for (i=0;i<70;i++) RS_Len[i]=i; + + RS_Len[CMD_LOAD] = 12; + RS_Len[CMD_UPLOAD] = 12; + RS_Len[CMD_RUN] = 8; + RS_Len[CMD_XFLASH] = 9; + RS_Len[CMD_TFLASH] = 16; + RS_Len[CMD_PEEK] = 8; + RS_Len[CMD_POKE] = 12; + RS_Len[CMD_INITLOAD] = 12; + RS_Len[CMD_INIT] = 5; + RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2; + RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1; + RS_Len[CMD_IMPULSE] = 8; + RS_Len[CMD_MODBUS_3] = 8; + RS_Len[CMD_MODBUS_6] = 8; + RS_Len[CMD_MODBUS_16] = 13; + RS_Len[CMD_MODBUS_15] = 27; + RS_Len[CMD_EXTEND] = 18; +} + +/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */ +void RS_SetBitMode(RS_DATA *rs_arr,int n) +{ + if(n == 8) + { + RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */ + rs_arr->RS_Flag9bit=0; + } + if(n == 9) + { + RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */ + rs_arr->RS_Flag9bit=1; +} } + +/** Ïîñûëêà áëîêà áàéòîâ. + Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî áàéò + @see RS_BSend, RS_TRANSMIT_INTR */ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len) +{ + unsigned int i; + for (i=0; i <= 30000; i++){} /* Ïàóçà äëà PC */ + + RS_Line_to_send(rs_arr); /* ðåæèì ïåðåäà÷è RS485 */ + + for (i=0; i <= 10000; i++){} /* Ïàóçà äëà PC */ + + rs_arr->RS_SLength = len; /* Íàñòðàèâàåì ïåðåìåííûå */ + rs_arr->pRS_SendPtr = pBuf + 1; + + rs_arr->RS_SendBlockMode = BM_CHAR32; + + RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà */ + RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */ + + rs_arr->RS_SendLen = 1; /* Äâà áàéòà óæå ïåðåäàëè */ + if(len > 1) + { + enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ + } + else + { + SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ + RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà áåç ïðåðûâàíèà */ + for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ + RS_SetBitMode(rs_arr,9); /* Îáðàòíî â 9-áèò ðåæèì */ + RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */ + } + return 0; +} + +// Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len) +{ + + RS_Line_to_send(rs_arr); // ðåæèì ïåðåäà÷è RS485 + + rs_arr->RS_SLength = len; // Íàñòðàèâàåì ïåðåìåííûå + rs_arr->pRS_SendPtr = pBuf; + rs_arr->RS_SendBlockMode = BM_PACKED; + + RS_Wait4OK(rs_arr); // Îæèäàåì î÷èñòêè è óõîäà ïîñëåäíåãî áàéòà + RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */ + + rs_arr->RS_SendLen = 1; // Îäèí áàéò óæå ïåðåäàëè + + enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + + SCI_send(rs_arr,HIBYTE(*pBuf));// Ïåðåäàåì ïåðâûé áàéò + + return 0; +} + +/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà. + @param speed ñêîðîñòü RS â áîä */ +/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà. + @param speed ñêîðîñòü RS â áîä */ +void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed) +{ + long SciBaud; + + SciBaud = LSPCLK/(speed*8.0); + +// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++; + + rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud); + rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud); +} + + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ +void create_uart_vars(char size_cmd15_set) +{ + size_cmd15=size_cmd15_set; + rs_a.commnumber=COM_1; + rs_b.commnumber=COM_2; +} + + + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ + +void setup_uart(char commnumber, unsigned long speed_baud) +{ + volatile struct SCI_REGS *SciRegs; + RS_DATA *rs_arr; + + if(commnumber==COM_1) + { + rs_a.SciRegs = &SciaRegs; + rs_arr = &rs_a; + + EALLOW; + + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O) + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I) + + PieVectTable.SCIRXINTA = &RSA_RX_Handler; + PieVectTable.SCITXINTA = &RSA_TX_Handler; + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + if(commnumber==COM_2) + { + rs_b.SciRegs = &ScibRegs; + rs_arr = &rs_b; + + EALLOW; + + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O) + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I) + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default) + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output + + PieVectTable.SCIRXINTB = &RSB_RX_Handler; + PieVectTable.SCITXINTB = &RSB_TX_Handler; + + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + rs_arr->commnumber = commnumber; + SciRegs = rs_arr->SciRegs; + RS_SetLineMode(rs_arr,8,'N',1); + +// enable TX, RX, internal SCICLK, +// Disable RX ERR, SLEEP, TXWAKE + + SciRegs->SCIFFCT.bit.ABDCLR=1; + SciRegs->SCIFFCT.bit.CDC=0; + + SciRegs->SCICTL1.bit.RXERRINTENA=0; + SciRegs->SCICTL1.bit.SWRESET=0; + SciRegs->SCICTL1.bit.TXWAKE=0; + SciRegs->SCICTL1.bit.SLEEP=0; + SciRegs->SCICTL1.bit.TXENA=1; + SciRegs->SCICTL1.bit.RXENA=1; + + SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off + SciRegs->SCIFFRX.bit.RXFFIL=1; // Äëèíà íàèìåíüøåé êîìàíäû + + setup_arr_cmd_length(); + RS_SetLineSpeed(rs_arr,speed_baud); // ñêîðîñòü ëèíèè + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + enableUARTInt(rs_arr); // ðàçðåøåíèå ïðåðûâàíèé UART + RS_SetBitMode(rs_arr,9); + rs_arr->RS_PrevCmd = 0; // íå áûëî íèêàêèõ êîìàíä + rs_arr->flag_TIMEOUT_to_Send = 0; + rs_arr->flag_LEADING = 0; + + SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset +} + +/** Íàñòðîéêà ðåæèìà ëèíèè. + @param bit êîëè÷åñòâî áèò äàííûõ + @param parity ðåæèì ÷åòíîñòè (N,O,E,M,S) + @param stop êîëè÷åñòâî ñòîïîâûõ áèò */ +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop) +{ + volatile struct SCI_REGS *SciRegs; +/* +SCICCR - SCI Communication Control Register +Bit Bit Name Designation Functions +2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits). +3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications. +4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin. +5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0. +6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. +7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1. +*/ + + SciRegs = rs_arr->SciRegs; + + if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1; + + switch(parity) + { + case 'N': SciRegs->SCICCR.bit.PARITYENA = 0; + break; + case 'O': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 0; + break; + case 'E': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 1; + break; + } + + if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0; + if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1; + + SciRegs->SCICCR.bit.LOOPBKENA = 0; //0 + SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0; +} + +void clear_timer_rs_live(RS_DATA *rs_arr) +{ + rs_arr->time_wait_rs_out=0; +} + +/* ïðîâåðêà íà æèâó÷åñòü RS */ +void test_rs_live(RS_DATA *rs_arr) +{ +/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT) + rs_arr->time_wait_rs_out++; + else + { + rs_arr->time_wait_rs_out=0; + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); +}*/ } diff --git a/RS485.h b/RS485.h new file mode 100644 index 0000000..3e4ca38 --- /dev/null +++ b/RS485.h @@ -0,0 +1,138 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + RS485.h + **************************************************************** + * Ïðîöåäóðû ðàáîòû ñ UART * + ****************************************************************/ +#ifndef _RS485 +#define _RS485 + +#ifdef __cplusplus + extern "C" { +#endif + +//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +//#include "DSP2833x_Sci.h" +//#include "cntrl_adr.h" +//#include "params.h" + +#define COM_1 1 +#define COM_2 2 + +#define MAX_RECEIVE_LENGTH 400 // 80 //150 +#define MAX_SEND_LENGTH 400 //150 + +#define TIME_WAIT_RS_BYTE_OUT 1000 +#define TIME_WAIT_RS_LOST_BYTE 100 +#define RS_TIME_OUT (SECOND*10) + +#define Rec_Bloc_Begin 0x200000 +#define Rec_Bloc_End 0x2F0000 +#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin) + +/* Message RS declaration */ +typedef struct +{ + volatile struct SCI_REGS *SciRegs; + + unsigned int commnumber; // Íîìåð ïîðòà + unsigned long RS_Length; // Äëèíà ïàêåòà + + unsigned int *pRS_RecvPtr; // Áóôåð ïðèåìà + unsigned int *pRS_SendPtr; // Áóôåð ïîñûëêè + unsigned int *pRecvPtr; + + unsigned int RS_PrevCmd; // Ïðåäûäóùàà êîììàíäà + unsigned int RS_Cmd; // Òåêóùàà êîììàíäà + unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Çàãîëîâîê + unsigned int flag_TIMEOUT_to_Send; // Ôëàã îæèäàíèà òàéìàóòà íà îòñûëêó + unsigned int flag_TIMEOUT_to_Receive; // Ôëàã îæèäàíèà òàéìàóòà íà ïðèåì + unsigned int RS_DataReady; // Ôëàã ãîòîâíîñòè RS äàííûõ + unsigned int buffer[MAX_SEND_LENGTH]; // Áóôåð äëà îòñûëêè ïî RS + + unsigned int addr_answer; // àäðåñ êóäà îòâå÷àòü â ðåæèìå âåäóùåãî + unsigned int addr_recive; // àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè + unsigned int flag_LEADING; // Ôëàã ðåæèìà êîíòðîëëåðà (ïî óìîë÷àíèþ âåäîìûé) + unsigned long RS_RecvLen; + unsigned long RS_SLength; // Äëèíà ïàêåòà äëà ïîñûëêè + unsigned long RS_SendLen; // Êîëè÷åñòâî áàéò óæå ïåðåäàëè + char RS_SendBlockMode; // Ðåæèì ïåðåäà÷è + char RS_Flag9bit; // äëà RS485???????? + int BS_LoadOK; // Ôëàã óñïåøíîñòè ïðèåìà áëîêà + int RS_FlagBegin; + int RS_HeaderCnt; + int RS_FlagSkiping; + unsigned long curr_baud; + unsigned long time_wait_rs_out; + +} RS_DATA; + +extern RS_DATA rs_a,rs_b; + +extern unsigned int + RS_Len[70]; /* Äåéñòâèòåëüíàà äëèíà êîìàíäû (îòëàäî÷íîé) + 1 */ + +interrupt void RSA_RX_Handler(void); +interrupt void RSA_TX_Handler(void); +interrupt void RSB_RX_Handler(void); +interrupt void RSB_TX_Handler(void); + +/* èíèöèëèçàöèà ïåðåìåííûõ rs_a,rs_b*/ +void create_uart_vars(char size_cmd15); + +/** Ïîâòîðíàà èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà, èñïîëüçóåòñà ïîñëå ïîäâèñà */ +/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */ +void RS_SetBitMode(RS_DATA *rs_arr, int n); + +/** Ïîñûëêà áëîêà áàéòîâ. + Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî áàéò + @see RS_BSend, RS_TRANSMIT_INTR +*/ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî 8-áèòíûõ áàéò + @see RS_Send, RS_TRANSMIT_INTR + */ +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ +void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - ñêîðîñòü ëèíèè â áîäàõ */ + +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop); +void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed); + +// Transmit a character from the SCI' +#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y) + +// Îæèäàíèå çàâåðøåíèà ïåðåäà÷è UART +// wait for TRDY =1 for empty state +#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY)) + +/** Ïåðåêëþ÷åíèå ëèíèè íà ïðèåì */ +#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1; + +/** Ïåðåêëþ÷åíèå ëèíèè íà ïåðåäà÷ó */ +#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0; + +/** Ðàçðåøåíèå ïðåðûâàíèé ïî ïîëó÷åíèþ ñèìâîëà è îøèáêàì îò UART */ +#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2 +#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1 + +void clear_timer_rs_live(RS_DATA *rs_arr); +void test_rs_live(RS_DATA *rs_arr); + +#ifdef __cplusplus + } +#endif + +#endif /* _RS485 */ + diff --git a/bin/HEX2BIN.EXE b/bin/HEX2BIN.EXE new file mode 100644 index 0000000000000000000000000000000000000000..0a3799ad30a59ddfc1706fd5d4cd44664fd2f68d GIT binary patch literal 111104 zcmc${3t&@4_CJ2}XquL^2@s$HLXm>hBDR7+c$Suwf)qkaTSSYZGy?LnO?W7M8M5|r z3HGbvYkjf0yL{bM*vsvn71r;=AuRO z=HwSrBQ_vU1ovkZ7A&;IF35l4iTuLCnFVuDl0Gk)y>K3D8Mw_K5E&I2H-6Tz5H8v0 z%(KNN4!!UG!S|U0%o!BmUThqyB=_qbfBRKXp({G*f9cQ(Ah6>7GYg*DWu$~AMe+ZJgB zO)O`sE>!Z>e2-Y}ntO}d_l0M}ghRawBft3O+UJz%sqMR3)1OQ7C073Tg^&7{jkJuh z8$U)mHQlcJxNqsmk@m20{HWilKeE?ItDy(6?Dq_FAWsLZ-s-S7}^PLaf z7g1?HU;2&0Ci0^=%_@yj!w*(#9t{^SDEU$MaQxuM!%Ii?=QvyMEn03@e{N;iIBlgZ ztUNsROtaM;P9&98tGV)UzQ^O?o4Ju&XN4c?rGM^-lGkW7eDxL$w{>IqhS7(5B^^oH zFK9M~mw6{DY~9Pe8PoO7zbS>zTf(c(La}GZw{;f-Qs!O9*)?UOc7;z==$%WHRzdSkxRuu!G*%&cTR2`-TB~9oaDciQJG*l-#9UT`3w= zsN(CvY4p!^Rj$(X%@ZC2fx2R_!nQTE$g; z9X6$G|L*~9vz8O0dvN2o`h0ky3Z2_lc&KduOTQ||DYkL?LrI10%e-1n?<`bo<`jg( zTwvB+!*}kXsrp6@IRcV{iC3epf_u@vaB)0`9Aen0-e6et-CA)7x0(?%iZ~bz4klGv zs~VI~UbOyY!zihTHY*eYKpsl!pK;8bK>Ls3 zJ*_Hyvj3&J)H}?kE%n}KQObv}C|f6*pZZ%q&L zXt(Bsc~n~;3(FKB?|Z}Jw#^Fn^bni4t%YHp4qI1+d7`$yO~uwzvBI#-ZNtMvBloaq z;I_?Fi;>)B-^4?`Qa30M^;+4b^h%t)xf&YLG9@>ua@ReYEq8Di|MKWV)2cUfs%^cv zr2ST8a*&;Bj!Qf%KI-F73mDO!m<_|lOkdfxS>d*hD_8h@;t-!ry;uE6nyBImzNto! zZ5zw23@=xwrfDnfEt=dO;o=*1OW1L%kjiFNoZbai~|B$f+*X zdhRJ5HAfp(aMxyT+M!j;ug$7y+aT<{s^64~cC}<7Yh{nw z+C(3|D)9Iudwh7>Th$XWk;Ud06f7(l78^G#_KBGbXogt0D1QOo=n=|8eoCF3mKL{Q zVJxXhmQK!!ou5B{VZpMv1^Jk;#^QZo93b3ni!EF-$M(eRSWHg&{wlGB`SbFhuq`Yo z4CKhQEB@1e6BVj9n!P)xSG0pjPvh|?2A|S7Zk<8;k9$MG4Y1`ewISP|N9ERO+kk*A z!Epm-&9u#=Y}8@@5v&*S9P%$2&jTJWEM!@K$2a;9?Op$`6d8Z+o0ZdZd&IqeSh%+T zOXDB3z0So)_BbG%UDHncQclCOhQ!#TugBznba2nCuFq9|^S9$8Uwv=NrBCzhW2YBS zobY_%TXP!3=Ux_S=4=1a^@(ZIM!$M|<9J8pMy{s)$gVMedf0o{ko)gi@!^Fs=d4$L zG|t{P=(E&q`wCCLHnrmI+@BmTCD(4PY=8CpM>@E+_xt=k(Q-%sl(X*->=`@mo~$`D zraWzVP^FIKH25Dkbj%$E&$XnyqQjJOAIBl#re;r_oSBrAI>0g}Yi8uL;hJumZMp|l z5#jA3+C_wS4%ceJG~t@C!Qq{|w2RbeBin^(I;k~X!XmYJ&_wppXv1S7!y~or!rQ6) z;D3=Cb(k?MVoCoHw zZObc{dc`EXQmMG3dF9H~rjjz%k;W5mZ2In6_2w_18eKeT#t%JDe|xI2@`aYn&F4SJ zdF9dCe%_bF!-d5IPfk9y>7wcTl12S5EgsQMESdC=e;ndIdsp$Nb(=Sw|JV8Wzxu9)`*}vm{hrgizx{Okd%sM3wRQB#kF=LQ`Odds;EEsiDu1fp{KL}Uy|cXM z!0Mi_PDuAX^VyEA-*xHa^L=^WzwWzO_h8Y|oE_H+XZ-x+mNoD6d88rdnU}Uc{LAU$ z6MD_PeE7M9OZ{Fwzo7Bqx6c0Z)!Bwa-_9<{`^2*@ZG!%RnEh|+@<$(9TleYd^yJ}V z%Rl@4Z;w1U^!36&9qiK(k-JlW;nbFHL#}+(?c;BEl=M7YJZtqK+XKrUUgGU@qU4kF z5nbYk+;`vI0|y@6b?n-@3(22dTKn^`7f$?q^u3rzpI!0Y>8FP~?>)P?tohW5x1ad% z)WhT6>v;ab2QKfb$~yJk@9e&-SF`S0)iiIHtGVve#iPGf{wcwJYP09!;+Jfj9&Rv9 zcZ}P)`brP|;P0RQy^DM6c;9Q^DqkO?U;Wg7z4qn8H5V6+{^7Ca-jCGXKl<*Yk4;&+ z``j;S>(_1R%s)SG_=vCtD6>)C%Xg;Cy z(yA|l|7pIKAsQK#K4xe`V>;ASV{K2y&ji2r+ANAL(osQHUxaZqr!_S|bocH5n^G|=Zz54utD=ST_vUgVZUU;m) z)6+YA`Tp?3o#xIzZQ})^m zQ^hwfzh85~xNFm}Udz^>Umw+>GXImcQH$@`RCTb&(XE!Jbr00vk`EEA9#M&$^EN{6P=rmdo$d zyA!=H>3)B|wRgMWmq!ntHtdtUIsE8t1$#0dX>6I%?Ns>cp8u@B+TZm`Q~JVwnfvDd zqv!8uo%3~n?(?R9w6l!cF{9%zDJKpucRu}$;^_FqeNTPWZf$bd`9p7iRycLxO9M~Z zU-Z2itar2bX;|wZ{h)#%GTFYufTNN8bDXqdCi;e=LzVPE3hi*v6sXx>tch}_2KK)A0lAiZ=j+(IjjXpCz+c0~OW9FX9phdVMrY$Ze4$L)AD0G!jCL_ za(%Jmof)xb&eVVNS=O$WqstyTxP8s%OAn9QHFDYy1#AD&GF@@`Z!@Fww*2$i*HZg@ zYrnWBI%&b6mdn%jwLJaSV|9OSKO*b-6@9f2oF7=)Reb;5Ppg~m`|82`a}Dcfly)8F zZu#@J-#M>{DN(1FKK)(s)j>aZkJ$RwyH6$O9{Jn3$}Ps_FSg5i`?V_vW_J2z)lUWQ zY%N~#O?mU07mhx&zw5AJRRj0;dFruet`>YeDQ{o+f3J-hz2f7SV%~iIy9YZOPq*8; zWW>3JFYn*H^P7t$|M;?Q(*@PhRrQZ|49m6a_bjdn%ldBQw^`p`jsEe(z<1g;%``n! zxnyzYrm~tXjs+{;{q!O~xlc@5_jQdEzZstJg*Vyoy<@@BuU~q*e9P&`$j`?1)<*uRcl_@UR6kYp#<`IvKFtq1 z{nX63!!vt?w}iR8SlHP6Y$n@dB!@rC@33wT51S=CK*mK<9o8uvx3w4+$Dt(asygfD zNIVp(H^3ydzUMv1aaavu1!7&b-|@8yD-f%+vSVE(r z%F(OpQf=X-eW-AWgpAhq>`on;({Gxgt@5a?Y!M6n&MKO(a z_3kb6fFmsSBwy>rKZf&PSU0!hc9G$8D5q2LvKO z=P$p@)`XmqTI45Hn!;`2e7M7{_WaCH*8m{jX*Nn&`KY-_X07dxmfzC>DE}#c*jiS_ z86015_Yxm1;xMpo)>>lYd-GUfHfPUt*~zxB%|Gt^@HC{p_2OUnPV{{(q3_YNgwe1WEb=}4 z=#1)W*J3VlDc5HX$G2qj-#Qu%bCrTwYjK%dE#kH>FeLWqW?MROoXgy75x-*@TKdS| zule7bEVHxxh3+`YY6<2hkD_9KwG3AWsL2-bHMHy4qvk7lvllsz%5aN_<+4Ao*-_NY z*}~msFS>?vn_DRn%&jJ~w?yr^hi?(GTlpHrZdXbKzgv~9%@oJ^D+}2=Rd#E+(r0e< z9I5~ug`MEwvrjO4Jxac1e|4n2aORWwv9t4+-v9WV1+gRMEEp9#VxiqODv~RBoQvcl z?F(i;4&NyJsI(@IowHz(-4<(|gDh?d3IsntQIHP@b1doxOH6(+k^>LR8Vy)n=H_IH zS;U?qt;*JG_OQ+zH~S!jTby<$u}8~SvOZ`KAmQkP+1V%{n01aywP45;^CZTCO-}D6 zaAybo8Nbwzlg8qYcYjUA@bGod0uGVyvF_2#38d*;7XTv;B4xo%Kg*hC0MW;>AWXPWCLdBWXn~88A1fJfqggh;( z`v&@I_*x;a)n5kvF8JZMl~yfDYn&vlT_LUAt`k!TD2XJbHHM_sC`oH~Nm^s+6O+~n zkT)i+^gz-&iKWeJGg<0go5RvJ(&`OJD;1KZRURv{&=O7P4)%-qFZBay~xDA2@Md+-v8w5>DvQA;s=7_7X zE9VJg!!$U;SbwXohuudS*%21;X$g{`lAvUXX+bDVJp5Wg0@2Qo9w?IVGX`;UR@$Ku zdIDllS4fnHVi7HYU=yY%U53)74HQs#9O6!@UWE@9waKDg5@`{)4~6LL_Gt8^h z(`1PW$Z+M0@@#NDMr?v3jDBl^3&E&0fRQx8{RT#FY`qSn*O3v5QDSiB9`8!g@hMtf zDWqt@FQyS8H+z#ia&A&{oI6=9C2SVAx|0o1h{-yp5R;AQ8@xfRLloj~@;YSdzLheR zFd{a|ysDRtfwQtPAj-x-BTBmR>R}D=H3=!O*mZ480g_H!?fw87)8T|9EC9YT}nNJIc!+i+A&0t1wa$e7BV^@(M~Q)xe`s`82&rmQs&+|qmbh~ulT|3d@CyAW245;^KwFgl zlie+9v+y>#rjE#pkY>f;;FeUkR?@p3i=?-IrE#BxG4m^pI{|IB(YUsD<(=KBY8t?v zD5iW>cqO6cYlE{6)4YO)S&~{w(@(jXrvI^n)UHN|5mL3LRCPhSEb)URWWs+F0rEks zM^l0Ac`PBA%GXFLUv7?QCGjXCP39iQa1p}W(wu)2nhWK&!-W_}5higX)_D*211;m! zo+Ke0?WjEQla}_CI{}E9?q}H29K=x%0LNp#acYy8NSh~$3kLxYbbgafFY(zEegjT34XzTj7!h|0W774zEYlPRGKJ(vd^MPk zVa0pevD#|Z3;tPBsx?<3wUnLAm@QAH>JYn-%26q@Zv+*P%DG`tSytyN@IOqLC^rD* z_}#%78VfFe+c%TT=>ePM6bwqn31*Y%vc$hjtbr6T!vd4Zy&;A{JB#=pW@dR@_$`A7 znQ5wu^3DO#Bw4}SPU2$M@%C0BLn|l*3)DFqpZqaF(ZmgAlb^Dpyrx`} zHrcb;WN)=c_#0C0)xgJ~b>%nt^@XExC{YFtiDg{k%1Iqo?6>Jk_bbaMb!a$+Ik`fZ zq=uYCOc9^eOB{v*?$D9~^HEPrj0Zs!3KvWyIN~-p z<1gTuTZMGBDP6lH$|ClZNvrZi=s$^oYsZ(Oc3fr(>TruXTT)PmkfUEQ7C_x>+uw0H z!9JudoMQtd7F`c#vi_40IG*GR$K`wN!`v!TMQtIhxd{ZQ$`A+)ldY&NkvC1}_-2vb z`A0x=Tu#(GKfwct5GJTi6F^_4IJzxVb1RvkmwooG@Kw3V;=$sFDIX@I4GRF-ae1jN z%yD^|eGnK2=AtP-!=f$X5BK^Bjf6fAa!kJ>4s|_4^*aw|`s}UZi}19fK1t{n$T{Rk z>*-eExSDK_kimL%j;pcEK}LnJylZ2Rz+v_}Z*JtXn;6M?(4(%0Y8+Q1mW1(Nd3sj3 zrtETD30tCZE!*#DkGFSrokQPHmdds4zfDEnk}iH!!hs5N>Md#LO#0Z|4B`bPZ{8=Q zsCn~2!Q6N$e;=aiz7(<>^&e*+RD3Cz_vt@2H!1e=gvCidyB<~eS`{9Zd{akrJ)fcu z^0|Gcc&xw7mWB+pz&OKr-7pHTWCV2Jvrm>z=%DnF7gB(Ma+36PQl%?@dvGM^{A$LP z-JI#l_GV^@C*Yrg>bQdu5P2!j>&R~9F6Fff*lm{e!~ z4bq+^jx#~?O7587guE-_I>;~I3i5ecGE0#A+z#F|uZKSP#?a?Nd1Z+&1fc`(fEDI9 zzhrMg!}Fw-m@g5FKp%7zaVDHip~hVCsMMq z*Kd7&D&!bVIWbGx_rabNXUP%U^`$~uPh`20W%<&KwC>)*fGdAxquI49$@{_<`BMW( zPM48{JF_m}%``~f%nwKjqJgLi@@PtJq_8&NNq{Os%%tQT%@MnSc>%uymzZ?_z(EfT z9x~K4CM9*OIW2KoNY>29pO}?z#qNzX@{`$2t`qDASJ5@Mx%PX^K5jF7;*``-LUurV ztf^pTomu3#5^En>F}eIi>6!5I8g*iMxc;vfRaHNzup()2w%EUArAwdDae5cl+}wyn z{fd7eoxC?ZvEc(eR5-3A+Y8+0%4=w-Wsj1!Z7Mx@p3I+coY4yzl`D;r zZvm&cq$8JpDm{=`-UX)Xc}J0vEAGHrXi14u6GAmK*Yn@UUvccd#%CXtIiQu@=0f&C zRdx+kD^jGWvX3UUn0A+_`MvR9N(H+L6LgNRqxp<|D>Dt{*?XKV#l0MtmA3AV%UWBP z9R1GhJ(wk48%((AOilV#|BcoN+;XUa8qRj_-xC;c<=^ks?>r);8cnJ2aHGoWy{U@U zqb-Mo?DnM^ot4WMIf{;Qw$4IUy3c;pXRpl?G6(sN05E2tsg9z3T6-6?-_hUdUH(>= z4`EdfVnbH0U@{-HLqF|Pwyn|hfQ;wzFp%eAW?_3wi)x`g*ag@86!EQa@?~rYtVozh zX@!o=7dAr3B=;g*Z41H(l9~-VwntH<7dpZ!e9Rtx={Q?9SoqJdmwkc1JO$L|VJnAp zb8w{t&vS6-cVW=`1)v)w=yN&#r=&VQ!^`Kj!l?1ty}4pXf`l~_)T+Ega}x{?!mj!^ zFx-YI^54L4fdu_V7(Pvq+F(d42d(T*46-nxErKw?opnV8Y?RD_3JXHWQkv6$_vgDGSkCJcj=uptONS%4XG~l zXEGE-*%^wYExSUY7Iy7UD@uCqslYq5oV~-&e7w_;@3PZOUknvHpOkaLc8q^=|tr_fL+sKn8bkXlhF<3C9uvPs}HMXe}kZYNeMXo4m8_SX-g!>W&vjGMlHi4>{ z`y$R+S)^gA7=I--nJYGfeL=t(ZnC*g{`t^4f<4@9z0!cf;nuF2<{P36f=AWnz_=c-Aq)Y-ZT z^5>%2paJ49JVe4iVggbu_4c%AG#MCtG5B&)+qq=MF3@!6FecT zNw(HwTgbs)q-`Rj$r7`q-CTr!g=3c-Rw6bce96WeaZ)N9H5Z#ob=?Rdtw*z08Hv)j z!)S>z+B$)EkB!%az<7;C01~m3ZCs_(Ahif7&>QgMNjq8ize-yBde(!K?$m|Et@*Dyyuws-z5KR#)gJpp@$^=`YC zF^X97y1j?_$z!a53r>HXt5$M`?M;QE4%x?qNbC5+j;|Fo!`U>Y2NWK4Md_JqJhJx% zc2LZ^m0Y=!m-qKc(O;Ki*0Qoe{f_mH83u|i#`O%8yO7w5qlX-K@sDithi%ve!b|FI zWA{zz%4p)#>$sjE z*%T%8+hntS!M0IC64?|b1hR#^lYU8pVh`>dGtSaJt<*%5%-Lp{vtF6At-=lWX{9FE zJ}uiZo(@j`Ch0eX^f>FI-`Me8_a>Wvf_u<^Mn>q4uYa#GkJ(f%+GP|n3_{Y4M+w_C zC#m|aUGoqb_458vB5fYBQ9^BuQNtM;94?Y4ATVAGObuYr5=H}Wj?RCMN-E*Oq~{*6 zl-bu~*3u&ln*l66yY_yTifae6w9T*y5=e!9HEd+M+Kik3#VDiOpg%BfZn>#WT9Bw_ zd*Q!Leqi_nflB0u4j+m3wviXC4H`dE8%;8cn`IVzWfr#?Kf%Zgsg2sY<3dxlQX~&wn~*Anf^-T|p@E>F{||+! z+pE_JQ&(ij!c@^p4qg1Cbp1#UVZqWnrA^5k*DSwN+MLq%`{JHbJ%4>|EL@y4_Grt< zA0I}~*uFwooduC~a-51;tKXGukgO{+4&+-5R;zwzhR({T8}z$&2TH-Q5_~2oI@v4> zv|eS_9Is|I0%+_fwc$IK# z`^J1PFIO^Gcc4Ua2S>f4&6}pp8-nm8So%+r18|d$tW55(PGb*a;T%M^+#W#-)JKhu z(idjUmZ!*XwB5(@v&j8|AlN&2MdA@SiRfRzZGTS7N1SF_zQPHCRUCk}Tg^-r$!4DJR0;IukaM zwB8Cy(gOVnDPf3(DJ(!tVL@jGB}-vJQ?d+0&N2+V#mHL>e7Z~_8TgWQSY&8PC6;B0 zy>!r?g*yIOwO}^#&^#gjV_@Z|92aZ>M~mR}3cTNpL;n2hIqlCUUP^r>S1_r6 zgk*x?FGKy{e-7q5md0`VHElNXAf&pC~eC1 ziWQai_R_-hF%}~35AuRP4?a#=zC#r``|E6JLYWzn~9LFAe4?M$?p-C30PYEH~!9PB(A2&1?W*D4D?3(L59~jxU5y2RcNC}P{Aq#N7iirGo z;Q3XFJCz083aN4^@z<-bvmEM?5fTwd@k~!+qrxwXTJfzmZ}(wuEcne4c%!~dhfG7D zrx=)5)<^=4zG8jHo(T5O5DBS%Xg-Yu`l?`p*;d{+1@cHg+O^oH;I9ffY9UPJp0N4Zn6 z>p%(ilCWVUEB17-)tw63D1qjngxpCi9yGW|NPa1%E9P>Nwn%2$Vr+=Eka_10oLp(6 zKYu`!K!E$726#!_ZZByH^bs4=2!BdVPt3$_RF>F`f+7B2iScsn(ON*gy$L7*+_te7d8}H6^s!br{JOx7#2AdPv1IBuRi#_R z!%``^i9qRWoi)YETgJ*-S&WO8A&ZarpWI=ay*O424hQk`%Yr}s^%vp{7@Q>@0Gu0e zBu5+qkPr}=75^m!SOH4qt{K5pHhb5KsR8{R)af%r^0eZqz#EM!oG+>pm4n*Oag?WO zlb3Wv;NbLbCvc8>ox`iMDN<;#w;v zL5w92t*lf-;e-6^{Jp=*355ei2lmJSz|&iOL+kr#!!_{l?fKH9WucTlCa3EsO7EjG zq%?Ywl-?z$%jI%sffm-Vh+|Tk_SvHJQx6JirL8)O+9P?8+(>b2OY+iuH)sIirdD;u9 z-I20b8Ev5oc0V2w)Xt~I@bq9P>+Qn{-K0upl+hSx8eG+~M`7z-diENx60%UGKPvKB z{e>(*iUT}8D^9@QRJE@#PJ9pkTX$+4^?^IJzm)W&Bmk4RW}!J9J8}NmT;2`Ap@AjZ zge5v5H^|Q>@N=)kPvKFWFism^8{Y)&B24bjXEX`9as0mc8k4zIzq*3jG<#=JW9C*z z2ti64fDIPfLTDf9_D%yNu!088)@Bafnp%-YweQ`VKm`cN6NJJT@ zl5Uez5#SUKxOi+8es1kW)Y5;>t>)K$i(7F)Znd>#yOUkeqEgTz^+SN+3%m2r#!^fk zqU?KL^QcPODMI}UQfE+)57J>!hRqcLRb7h6nu-a-{l zkvgs#i#uoK;H)dqKwOXFG-eaULq<XteA(7Z|A{7zY>X-CmMKj4A<%&k*7`EM4bRYG*lb8J2Ljw^?viyS ztz@7sNBHe?`P5920Zoy;McAu_N3{(5ai+Xh!oF3)9??_Rm}8f)FVZR=ReSF8V}A!< zB_SVKu~Jd48Iv|)*(H?WC#&O8ouaMLvR3>6fo^gqz07cI4T+cXTe-4y6j79{)U}A9 zk!um39Zc`y>P|S;`yuS{fRgXnw#RofS(^EZUzR*^6+%b;aOu~-@a+`W{Bj|c8cwC2 z?amj*LN4S*(Df@Lw(toogLG&=WEm97UA77We*^0uqQ$OdfnB2OWmH2@7lql%I`i%d zgzXwIhSMZb)iA`@twF&V-TC5JN8fAAgXtH4xvgwn*#VCG@G5VBF!?~h_Hs(|pSW~sIrc$rBrh1b# z<@fOf$1GV^@RXA4NLQ#I3Tq%T9h;o`PpV*fVf8QtE9Cz2N}tNIf(6m|GS}z-RN+eZ z@e@!dS@y8e{=juBHh88f^2TLsXF9OBBVSW7p>$ZJT@zoE4x7((U`Z1Om?GfKCqK4T z7=tBZrS1McbgPmu#ej%K?6prZ#_x9Nl%}f1?JCBXnj&qHrm7_^E_GMLTPbSd_oZL& zh04iFY7y=vQxU#{eu$c9(=Z~hf@YdD4TtRnhkU}rgCJhVL!-5_0@b@=ic;d*fi`ue z8sGYP8!U}JR1n@04-7A^dLwNZeU*TX6krdVYqQO{^1T z=%f-t3{=~o|B2Nh*U3^RWFbOKpj5}_KlbUw}iULAq(AGXnvKQ<*kk7Sy<```WC}WvlAS_?2l)$`UPf+^OJOt za8*VtKM9DdfdPDnt_ePV5(Pl}Y`G+bW~H;haK`$nO;ZCl=k$SE zI?SVNScO-_ol4aDBWf4jETXp8QHfSW)cR>1C)1h+zaj4isc^gAD+G2ac3nUXvdJVP zQnnz;JjHEFz(D0u@x|~G`)MJKEfGNLF5FLsjUUMpTA6JqU(<>;4Yj-**K*+tuG4}W z01M516q@VwvK5b?*-=^IoQn)!elMM9PlN?a^H&7#qNNf4xoQVhz#PX9Lm${u^*fye zAN(Hbnyla>u~-$CU^4NCpyvr|sG{P8)U0nKRmbY}N0_|)PvyFvxYdTdVYoYP-LuG& zj2v5EYE-dT9Rq7grAS~{y4Dcl5`;|H`vjpD7kUApKlZMyF-D?&Wrm^L#V{qFwUx`M zHO-(13R{eF$nz^(@|YS*yptp`xp*>781>tT+!KySST$TjWB;r`fZ$y@O=MRign3pAwF-(Pt@>-9TmF;<2T^QIj(w&aNNBie( zZ9=L#elPUH`5+i0)k%gG?Kgb=zKH8@T^NOZFi?i`hb1*qb?L?<=$omBSw_go%=WHq z1a@0+`kD>~3^OwB`0vVMw(WIyI*bfJ?{z)&7AYeHI)Rp5=857d_^bWy_=?!;{v}@b zkIin3P|0)ZFIEgcaEX!4c9B z=M#--_6Uc!b-CJ9yF3Nw4>fzu+Y@l6!My$6OSQg?J?wnt>z6L`+3QzkuP@!5C}iv@ zZ}0F%l$;rllbMR~E3>zkw;#`E>{*#zS>B#+NXXcOpf$9okZE)j)w0VxaaAiAQ`AHV z*!2QX%x+4mbDK{RS&pK5oNJd4s(L0=05PjQhR-_+luhQE;yyw~4Vkg==A)iF@U@o1 zXlI{Fu<7YhCE!A#yrXn>vIv|a%MBop;?Nq}F=aPV=1FSbQ3U&pydmxIlwj|$ErDe= za<(qp?!}|WxGmP76UK6|D1sNJR>(f;8XKvARc$`1GSf8#Dsv5Q-XI``J!3t!a=18> z9K0&?2531)(R!{VQZR2wPB5>h9eVQyxA`C-b0%|4F_x4upeEy>qv#-4e7B?MtkTvC zf3>!5D*Hhn{l8zXn8y5OI-KLwJ1+ovV3H{0Ldw>ga$}Z6LEBGjAPuC&$-8oB;r0GQ z#p7_0RKIE$s-zK6J3ynEP|zOcCXqnDigH3;le130dOhKnSF^l5{4Y2Y=CkjUPK9~y zQ`u{fmVy^gt47*nE9D#3+qLZ9{#W6sJ+sZU9W=ZF{ z19HW;MTR-y*#(8@%ndidH_n(Qb*g^#pQu7!O?)*_$xY8vnfF<8*?Aah7ofk!_lB}i zsAxJp2(=2I7}P|9N=VppWCS`90(STGMp0po6<%e3O5j z?#h2ZM2C`-%VZ(9iGRkz(pfZp?ek&tnsy~24_RUtl#pi!=zd!D(Pk%=)L&QfJhq~+ zWB+&5Y;(RSWKK0wy<_!lTi7Vodj|D#F)3wDi&&a+t2hgj9pY zSBTOdF-&ncP?e||q*#ZGWH7sD38gF07t9yOto-NDXuuB;Tw!2NDjA9c=|7-wOSKli z5%ehnARP57hgW5f*h&gGsl{`5OSRG##jO9GWN&ynSI{1HMADI+T6zt~gN{Kc1%v~1 zIUk@I>|GM~^R;Yu8E9z$M8BpA7vcmj?^Bh2rln>hNUja}WBHdnnj?J3TkHVwjq^hwabm3mw8>Kgf6l!op}{E22goQslT?AeJAx3tt`0AF4PRv$t5H$Ct;W$_wI z&#rxwrQ+ImS=uN7C_9`4pz8uasgQii0{!Befxf#01_>Je#0}%G+WLKOaZw>zezo$A zIIvC}l@u?D9>cSctPQf7^3e5C5sNq#MiY~~U-5q`@qdxTe=GR^B-jdBB<_ZG1Nc9S z`2U#1|Jf4%=LPtGTjA{?{BI4gN(yk7PTWvWt^n&87M!RoXemqF^B}8=IYtC5xr#J*VKKrE z^Etceq8!D$41{{h+9$D)0>#eP@ZA@jWmf$g`TkS2!_;-AE^nSxQYO zV}~nDae>cD4&q0i(rkn%+PXQeC~VQ2X^L=Mfv1|U@kC0ks49|h$1Bv((-XzzB_a9@ z@Wrbj%AGoq$x)m2TnM3c6Bwaz&9!e)Y3&`UULls#SUt)y4$6>tg#f2>#OIjV5W3Ud z5w~>t?CpGuCyGgc;89hynVZ=GC~yuZzm%*`F;PWM$;uShAA=)72X0LvZr#5mgj?VM zi};1VWS!F1BkmU-G24jmwRc2hFLf$z0JN~^UU=dCV~~sh)=4luySbj3ddm}Sw>7px z&f>HN4!eYoEjl~J#ulB8`>nARa^mu@0cas(3+Ghfj&$r*w{9__?=Jo^cm$IqP>$t* zn#WdPU{L!44L8Yyx>+97UU^Wrk~VFkGds|xHyYGl*9^5gZ6X^AIYuEZhT`|K#4YJe zLgvETc(R4rzpT~UVq8dzH&jZO*i~}4JeTNTXL0?P=l=KvwW_}4rolwfia#L3AA-TS z@avO;)Bf*H3ev2zq%r3P zA|Iup0cYQ>A|Itfhk-e+=MG8U8gny+{83xSUc9Ad_}>=Mar~x?cu&Q&tEwvDLmZ?Rg;ggVAV2%SC6cgNR-Y)?@d(G(tjuoJ=5%15Os2VAW&kWFe4F^Mn&+UmO;x|Gv30|1+; zHw2Y_6K-3~(5W&ERiXj+F6#Ktt9~>nyjZJzkFtiUdV_w`{)m0N%2BPR>l=$&O-0Si z_d1X0S6l@IQ?XY6!dU_ZQqvU(oJhqLStVgxV9{~R)%C?UF7;bRyjc*?BA!7nAx;bj z1o&w?d$H%IYYFc7on4fFvPk4l#Zt zI<5TjSBxnLEi6+9I0oPh@%{7C>wTK*X1iA*WX+z^Pp(utgHoDUcG!<ZA{q!KBR$PoICj@$ z%4K_olr@&rQ*S51VlHY7?yQOrfYzu*18*hu{i&9BH6C zUiF)LDBw}uBP*Ld_;D;Kqb8vTe#lF4TyYo(@CTS4+GFMM>vX&ZCY`BBT(X1jEaU67h8sRBRUfZliIZh=aZNN~M+DGt1>*|( zohTMUr!|?Ii?u0=N~9$S+JlHD^ItlyK}YTks9gT1pwbl=EkHLfx|zCto%*9lYs!`7 zlgIn5;l&2v-Bdae>z51Z94AR<4oN2@j4wJnVJYnco|Tm?pK%uYc0xcliy)gNB%8US zj~ZdJSp|tkLCia@?pvU@T!REhzOJV&b5|@-rHQzx$x+>kD7+f}@)shn!4w^bi3;}= zQ}%GaNJLj)tMZF8Jeb?`g$PGmXY7`k^3E2V3ViD9>0UuyhAJvvL*ITv{1tMfol2Aa zY{3PDPmgDzhf-g{&+(|V%9ih_u^WUm11%|X4e`5eVYs>2lLCXwvDe7k>#ORO`~}5s zOd+mEhGL&!H)|_WP?@T12Ij0ZRTUoG3K8>p{%OjtFE}M{kI@c^-gy+nvfdsrcaZoN z92;;AP=Dhha&l_kVBTYws8+z2Mf z)bM+&t^x2_=sGCe_)j60CrJ5W9GShi+_1`ro&ZfiBS+S`kY8w6Q&CgFUj%!z$?h#2 z4L*8tr{kvGDxmF$_`N}Kfq}vuUN-~Nj0?gGc00`Vh#06R?Wy-6yn$Ye>K&sw+fM?~ ztmT(TqfELuNwQ*NNMpj2n5}cALn*Z4SUiT6>k)0MFpzI@n?<7f(q8N&AX*czWL?65 z{cj{VZ{jeE+Nydjy*05nbydBZ-VjrTZ%Tl|KB&=W7AZ5CAT-9}3A;%`k;oS{ZlSk? zj7C1vQPdb&l8hfh#k;wYzr zF#C4YO$iXCXe->0>GjxA?Gm=M+iIzs4It64W->%8KPH-=0yQII^thHlb2d(ZJ(JNG zm@^usIm3w`3J6RWHNX%A@^06oMp)_yjMc-;^_Jyh1@0?>$X5LTNTN-PE;7&;wtL%3 zzgOS}+Sq$s7j7E_Z<-E$jtq_kalv1PRgnVW^T=g7>EQ~TNR-~mlZewZNkH zcYISjd{R-j&iCS1SJ?|zl&NYqSzwk6V;f#r%J4M}F9RFwHG4ru638IfCjIh zhFpmTdS^6@`%h`mfS;g&mb)tVIHu*9XBBcB>nIX&sz9(eLNB{kBprhL7|U5+v-1I9 zmq6Jue3EAY3Y6{rj6UKg>XL-1j@G2QOS{=P)^200J!7DE3}X#`akc755~ovNZqDAxdK(eOH-+R9u`sgwj8}+;u+E#?)bzD`YE zwQ=d4A9osS`SHw`XS+T)_Qii?Xg+T$9qX^xWkJ}+jhkOe`}y+d2G!)D8Ta3rcsYH^ zbJIucDl9oQxs!c6U;FCckGwfz;Gft1t9Q$I)5t$JkNrje$NS%Ub=BwEtq=D}UHI2o z{WSX`fhYY-W`DV+T~b;XKSqc7-#;G>tx?uERLSB9t+;F)zj0}< zVdjYWs1}vw;0}B`0jH7uAiuE`@o84Ka}mZP3Oi>bW#ygo@WiS(ZFr)FQLKPHx^~P$ z%I{b%)g6Hssyhg&RCg$zq`Jv?lIxCQkFJf0NcoLRrMgzm5_RuN)UA`soBu@Ay~b}`B(-uB3AJ(%sf1w-o}^Z4@g%qM zC3|%3*oTzgF%N$c4&!`TF5q@n$WOKpvguD8M0|2f4Jwxzf>zSd00a(69JsN2q-UncqUV}ay!RE)aCl864>@*Fwzecj*hqC;#umi|*H}Xh&p^-$ zgcZ=2bP{$Dc$d+qxFQvxSD%xrhf=TKsR8toKM1TIzvE3nb$AEpoupN-E9ms;o#%lj zMe%j6NR_|JVge)+Z6259bH^2}{`n&)CehAsBw`hB5n)Mn6{&E$=vTak&r%lq6(7^_ zqOldi8VNW03m7FGg&h)!KE*MfJ$kxI)EP?J3mYZsS`=UM>~W0g`0^dsgXkOtaRrxF ztRZ+5g~(_%poIVwtdsaP1Tv}aII7z%%w)0)~{QMf$ULw50 zlGKJWyisEKlG$J@&#)6*B--@rJCK)nVFzIxA_eq%T|3nOM}#$0E&c#FUmPjXS@Ozj zpp2nyyYtdpRMXQb$O7Ew?;k3D`r{DURRzu!Dplo}nf% zxDF zr>i9F^d-d()*^fx!vL;$iuBsKq=Uqyle%9f0!qW3__#%n_7Yr#i)%_}(;A|^WK_J1 z(v!MFR8H6^z5L87iKqa%qO9+icM@2IOD9ea`WO3pfWAt?8NXZc1;xLeMg#nD$JcsW zxD2rL8w!kDF&|P>c6AW`7I!&SE8V1lX^%S5K`&IUz3-;X73=PdT*^POT(4gUmA6`_q-RQ^U9Xf=b=lzP{@c(_#O zr*jZvoJ^+^pFoI2f)p=BH1rRp;dmvwmU2!WIR3+_Z@#K8Jv+9vIoY0es_uBz>D{OI zpJ)i=b@nJv)gJ#L$gqZ~(ZIs(d<=M_Eoj+C@C2@Lr`VH6bE=m9=VO}G#{|#E1kcA* zmXFQkbvtSx1fmNue7tih00ZBI1==(&+&SDZGAia_Sz!VCs8I$f?FX6el$z8G==b! z4Z>UWotz5{DMzJD^Z2Dvf`RYosH9zt@$kkl#md?4l7_M5Yv`0C)BP6c2CWiFGHgZ@ zdhWQuxGgs>k!t00qgms`2-Z09AB~SEFHmT^t~HhTlIdErhZ0G+earxqn=b!}x~~*p zg^grmNpnVM-;JC*NG|*LhafA-p{}kQcaYpQ)#wY@N(7ayMRkIcp4oBsiU82O+XTup zohKpLrYD$Mq@G~YBlQGp@#Z~2J;r*19GF1sNs?2%|D<`dj&Ac8> zJhK2KCC+bLhZ=&DdQ@QD>zb(am0eaMQn^SQHV|Q!@Ly~m3_$TU3WkwF;+>1IGcnzb zpYdR+$wk2EjZ)|S;tuhwR6P3{FXcihze;FHjJ>KUj+@KPj=-g!7FjU*e1k6DgN=zR zQrA1KYUm^a3}#lvgYv#XZ^hwstG~v@GbDDbqxR^eN|IRmm=yY$6)!{I@hu45K_bfU zAmd&VSF|TL#xyin+}Fo!mNwEI%ajvUg@*SRXACd4N+VWyi(Y|nai5CosG1BMZ$cG~ zyBkn-C!>lD${=>ER|z|M@G%`J6ZYIWB1S46z>fNX5kn6WH{{}3thmH8xwr(*&$)T1 zA(y?#2&WAFu0_$399rGU(EFfB8j}LX%tk5!cWL|qi8(ekf7mloVCx`qU&@v;RtT7r zFDnj9!_W1|{n%DzK68c8(NtqINVaNCVSD!5EuKgd6QY6>N&Df}as3^&Wd*2r9@pSS zo@B9c?c9&|OI73~(mQwH8Bt^mE18fP-w}@pP4u9QI5v#a4e^I%l*9M~p79kDDdgT~ zQUK2b{}b?K+Q;?Cu$$n!N5XeU0N*3dBPF(m2Y?4|`qw+JVa)qg_jo_n{DCs`vmQUm zLx1f>{(SmbjYag*J?`Nd2qY%+!BtL9uB0OY1K>nhkbH@3`v`6$-5qF1F$r-eqC1 zCgLyk>M18Zd7j`8TspxYuDWb=T<%yByA#Vu?u%>u#&lMAY@jebc?MTFsv6zSWI5My zxkpKdT|EIT{&W5^^N4+M#uLUK_%$O?>XeiIo~~**3FYKx*Nt!+iehjo$be6=r<>xI z$O`ul6s9LXZvEukTjLgoQm35s_jCiyC}uL5OIwrmD?UYNSi=Bd>sqrNpEKLYWGe=j zYt3dUpT=X|4mvm|o<+XkqVfqY`WhHs(y&R$F;txibEzW{NM83L)sQ3@*9YEle7|1+ zs_Ko3D!;gRx*b0d@*zI(;rM~$`%hmu6*d(nVC@Mq^}_7){E`}R>iBW-c%`Q#ARUk} ztt4%>yG|YV_W;5$?fC6s{fbjR`+Ud6Q(=z)8phIbQ3Cn@*n9iF3}KQ< zAV9zXqXr}*FF`~G6AcNIfEXNz2`I#hk};$RG&v{0mB6HvXig3Xr&exhl@^NL($==L zR}f!-ywD7&S0nfmUW>}rGo4gJp-F(0`F+>kXC@P*);{<7{eI6M4}3D`oc+4?+H0@9 z_gZVO?T`kZK7QJ?j6w%``O6tpjG~8!zw}LnAPqzWMV^I>UVmk<_g_ud0xz_RKD*Ic zH;P7=&IkHstixrQ(;dh?F~g?Ue( z=<9gGK*UbrDq88SVY_?mU82_%g?r`dJ0Q_Y$LSNi589iK?|%g)Dk}Z%vB>IfJdgi| zesNsmWNO+&$A3dn3r^BT$EZ_@6m|UU*IT86?J!0$Tvi3-@v&2@9N~0+HL%S44>$## z;PtWdsXR5Ea}8mfPQX&=H)Fg5sZQ6?@0qvHG;_o-jK5p+Iopac&TeO$5^LROP$z)Q zc+nRl*c8=4>t#uC~5ca_!1h!0}#U*>;I*}m@^|@^C{XjuzneSl>e6|i< z58$s^hbsM(ib%mqrI%|;eWZWVwR%!6ZDl&m@IK>?{z+GaN~M=;N{#EEbTvylTH(@F zR_dV8?&VMO1VLY0(N#ACxpWJvQu$8LelN=iT2o(o6Fu9f=SpMxLkrY~P`f}7V$Vyg zCci(!v89Lh#Dd+7?9iZ&gbK3h^C)ON4X{Cg?E&dk4OgLyQiN>S{3}D{He5X^L9gA3 z^DedfKxc64M&uU0=~~j1p|CT7)(JXNvNVAqh@pjySw6D^J!BK}s&p#-yaDGyc#uoJA9~qgP_!!2IlH7)J*zl6JktdU zrilcprx7-Y9rm885fnJY%k--qu-ogXf&pj;bgm+_HSEAP>=mGTpA8#B(qN~*C1pdu z%FuAC>60iKM@O0sZ$TBUF3E_nS-8u7DP*&7sWO4vEX3N2PF0-7Y4D@gO|3vg&;f;P zBuY4JVJyQkAreDj?3`)(@_!p%UI^9Ms~VpMN(dbj{zdFSQ`*KTXwFL4@|DZQb;7)* z^MuKQmwFp_2;8$YchzIRc>3r)|9SWkWn4q+Jy+KK%sF`0v3q!YS~h>C>d$2Td6w%? zp2Kv+h%)t`t5INQroK$0#`kSh610?uCdG`I;M*%c)L!J0nP9C?MCz-1fd&-*DMPZ! zTM$lDC?ga90AG_284sWV5S>9^Sz&hh$a0Wu(+VtgN2;gzNE$1gc9>5yapvi5G@=!i z_(=^;BL+9hDh<`sOptoI1fFY185=4gG#}&ENi1rmGN|r+20BAb1+t<%Y-=V+>AXsP zX?ugOZYxS%`yv=$wM`JyaMs#qaN{#DoJZA!q6R3E%@+MDdgE#hadlsk;SWSxrizu^5~%lH^2?DJ+t;ajxx%1)Ef|Ra6rkXEm{7! z=8Iq~4D;_{?V&YFC{|zUzlC<+BX6lk%xR`jsPP%F-}cq*MhM}_|6}}km2Fga^fszm zePfCda0YD~?qp~ugzw8ns`MUR)WS5&9DOw{gOFI+LW$6We;&{bIdvGhOdXAEJi6)F zrx{1)FVMxjY`?*UnTc0J>&6-%X?Hnvtlv%bz|R@~X_J?pnCG_Av+1;HJDv+qSZH=U zgM~yV>W9Y){L*aNf#>nx(C^7DAFy|dIsT+EO zQ`pcoYX|%4G(0IvWOKw`BA&jwMm>Rt)hDbU?W;Sd2k~mBR(dOCglM3yes6la0&KlBhxrET{6myY`U5f#cXI9_}B5KQ+K3cQ3uY)^Ah|4 z8>g_YCW9CsWJN+1Lb`+|CLuB8d)QNuK0XDD9Wc#BUWJW_?sl<&uJ*P9x>FWbF`}Db z(Z#SYPS$CcN*>HhW+_?Wl=7PL-^ZdI%@V}C>+SYP5s*}Y%tDzlEJo{1QnY7 zOzrVOiTWE@_qm%UD~vYk6QE}%B56MsVkg$xyD?}{a(kftRA1m=ASd6> zNXfeSEI>Q{cKZ?f16uqdMxnxR2Bi}L$p#Atp5yO-AEX=x$%$=xb9=LnPq0C2Z3VE0 zjs2&6TMjAbbUT+9p=jVD;=5}}p+!;aRwu&$1%3xzilQNGXm zS)AUtSg_XRK-?J~!PeT_@rhZLW5dp{Ax;Uzg|GyD7ssuRY`gd&NAp#~Oqs>_&&PwC z2iXW$7<+1snH)F)$w=S$ideC5NfO;CknisXN>MY-Q?hypzseq(ZDc0u43C%pMvE}* z7&eaa?B9)O0bU$g*VOo!Sbz0FlIoA&e-Uwk$50*(syUp4+1d299{PVOIQ?B-G(68L zEFzsDmP@1zd>T9-n(?RuP%e}kR9+pl2lo89Z0zFW9!D?9!eEtY8-9Sf6?&U zg#f+-2(2ffpeNYIvmWKh7dI$uvDpXA@UV_SI}g!rKWN0sfoY-iR1yInk-q8L^rT%O zF#19NJW};R#5NC{Jm9@}GVDOVg4X8SsPO#1A$nj+EHYW&0Nve-sEeNnLpi_rmgV5e z1_lHjtWZ~@1YRcBqcSBXS&6c;vC|E*Bx?sp=rDQEx-a$q6^HTx?eeUnrN?~j(Yw+2 z@ZZ+MXI7oqIGyWfoMhgN{coarVZ%ILo3f2QufcK2;cNPYa7^v)hvPeuiU(8w(QwVt z_gP1!iTcK8Y-k%q`z0|Y$QG|bwnFvQ?LUm*Z<5_-og=$C;fN@0Ad$tp!~geeb9 zNz7;@J4%>So0-u^Q-m32V?Q&@#(rj)jk+0TLbh&(X=2+6t~&HI+tQl@vHT-P{@C-y zXmP-6Hq@JbNq)~0G;WCT_W4s4()GZWL>aE7B9HogiQkxb7+Y>V_f z-G+}j($pn!INQSXQn5@gHHfW1?QNB&H&AO(J^{@XTUk}KlW?SZF5j)-21`J%q)6M-ju)A&ZS-l;`V9Jrn0SObUzu0Dh$JLjOw`@y>TEnxbrsxhkOeN zR}mXAV5rx_n+whiA~qOSJB=7h!;e{Af1AO1g`$$BDrZYBWy{_8V747R`#e|_P&s7! zUN;MII&&J-XI~NGO)!7QUWiUh4OpnX4+v;4#O7OBeE~)24coxXM-&$1lIJJL>re&7 zGYbwzQjIt;7-_+A|GEpL4`r110AuZ(^2|6*z)R%@VSJ^<$xEl?AN?5xH%^x8&QcA~ zopMlSCh`$P62@k607q?L6;=r}m(ckx2Dq9`t1H3qeu!%moJ{XqM_inZG0xAq26*T- zBaNXh09#B#p`A&M*Bs)VN9BfQR2l>NygHLn)5{3Jz{1WlL6Fu#IIMGk`TP`DTcA9W z1Gteo1SyD{%`Z$W$2dVBq&z0(x;&vhFicUYAUkW%n#1JYiP_BKEWw=^$byu?nK@Lf z(pb-a!l&I@Yi27DY95v&C#X#f)BgAHiqXR&){nN<9m6-30!=sG!X;VjUdJZ{)|-Ed zCv`I6Ut8rP*1)=gx{UAx?ibl*xX&*z@A|zZzXwjpcq{9vZ{mdQ5uC8Gu5n|$G(u6S zWwax;@}}^n&Jb^G*g`S-c5A4geAarQw4AErLK+fcB=*ok`As0Fft7c)DYQ-V!!lj) z>SZy`Q=g=#*H`ql?-MHenDM)feaHZ>-3}n^%nVJsfl|Q(4og7cGLwsfasm^00YtBw z%Hrvj2U1FHZ8($XP)fev2Qi-aI^$;{tS!Rh=ekg1P;tOFq(%TeJQC>qz^}dGzWpI% z`=P#N{X}OJ`4qw-52RnSKPAiWe!Hshj@7fD#=1ZYI(i8&=zcJj@lV~V3egNv zTs?-9>=mJC>PtaJ*SMPi{g9TT+dE7WHE90?;l_Q|cF zL;QyytDjIwPyk@H-|t>O-}P<-EYyrtbF?MxH&^ufeYp%W87eg?iq7ct^C(F0tiL7F z!PH~K4G&qmqO;*uGy){dgoWC!ZF+;~T30xEFiF2tiN4>gBer*x$qOH{fbW za$ko1xcl;>Qj&X}VLYyK0?QI=K7%QaP_`GK4(KG$9NL5ELO_j^hKJ?+=}PPvasfD? zU5@SYCF0h<{MowuKjx&EyZ;k^x=>4e4h$y}C&bmEvHUkQXPBHbU5QG&V9A!Fd^sG6 zbORo_Xh-X*H@WvcczHu7L5zwUOL5JXex(+B$3l*{IX4>-#lQl> z#b6thur%)~x$HWNp%j6WdxC)54nKPV11Q@i=g#^%bS#AK0_%>B0*-ONa&9VlTFteg zNg0iHsaNEe>V({$0|$(xyP}Pf#NEbQpRPdz*iAq1Gi}&PD*&Tjo=LkA#8aqc{SYKH zceYZPilUiwA7$nWK-~;`t#~QMJuop4<8=?T;Q~U2JG!^5G8IQ4D&d*E551)AXAbnq z2X<~YVZww%xP%Mta6jZr&C_AwLr;m`WwzE01kH3EGD`)XC$S#5p-@}=BN}=rxL;q< zx{vNhBZP1iz*9VW63P1TgUFPcfppO@x&G(t0Ni>3k0wthr+2eEhUU=>+rLN0cyXDU z{jVaf-#~Z5hu!<~HCdsI5BiMNh1F1{lG%LfhwzebgBda zSZgN|zs*gin-|Q%++<~NS2H}ab+txWYnzBLt1WTXx>rN(>+7ZG5#;S^O~eV$(6IYw zeS|?o!>+H7aMxV8eGz@M`p2R6{qx3M+ea58+qM8x4(?BYMgXm7SY z^$MCIw^G+xYj@$jKkdPCnbF>j|A_XiwR95a+O|b9l!(524g>su(sv<_f|=6osMb)2%niGE1A;ffu^ z4F|S_pWNg%F+hk}Oe)m&Y-ZdE>-M_ANWqxat%cfs#GZ&9@R3gp=j$B@?f{qg;(!fv zpdu4Tz#l~}_lnOsk+pU*N;I?vs5NR)8=B+Z1R#iKo2kMiM0YvkncTr8CIIk=g2VD#hUT>s>~G=36XRFWg{in4oAD*i8v8(om!}J; z5I6T2t#v!`rWD%7BY7LV$HMmJu-u*Qvwyt7Buj^>YIrP!BWgaa$c}eF$#sp@`mKqi z`SIe&x-sKu;I`{BZX~x~hM$S6FqRXe(m!Gd4@}m9#8q9mY<_MkHlUcu`eQb_=pFc# z^xXUv+%xADYEv;*01O*bnBWK!u=Qxflk1+j7;o3I>1)bU9Pg;5Z-y+Bs2r?MKnf*^ z-ooPGn(5jf2BW7T>H}d7;Di+~{eL~9z@>F6$XS5MboMrt6 z5K5zuMXVnf?a5c_f*U5H){5zH`lJ=`is9;q>P`sNJ-{7j3*hoLLu=j1jYre}q~v5{ z31foaiJa_y9*O(>V8IcJ0~Sm;JkQL4Fm^CI`+ovD^1@$wkGjZ!7<>tVsmi=$<>8d{ zx0RSNLYyFE(T_ArdDxczHhe&>fg6oP!zKHr(9Kqj_DgHJ;Pxjg;u^WCq(a<;ldSDY zXNWWWDKH$R;_5hdynemK+YnoC$e$T3=venR!^61ot`{ayxChf(8wD83gT-3(CK_kt zj?-HEB~ju$+xU5@o=Y36(2!o(d!2_@gaGv67ZFMBNXM64#H@3~50#?OmB-dXd2Fl) zZu2U1=?+@o0rxJWlswFz@C1PsQL#cRBDsnB7B><-F3-zGY$2TU@d>mO5iVsOy90Vi z;X;1*^M@Gf#J=)oAr_tnaq$rQ#U(FzM@9Hemh%$3W7vYoq|Bokbe>I~my&S=&c;L& zvpJ^Ne4pU~F5op8;-;<1sBl3NP3566ImH-ks@ zt&wiS-c>aYb}m?`O<;Tv3r=wmjR;{p$u7j08moY%3R|J8rH8^ZOijlo1T&^;k+*Gy z-Jh>+6Mm_$e0BBVx7zUAbKy6y{)W>sl+n8PP8 zdOn3Z_C?h5u>Srm;*R5eHJ+g|QuX(qi1bu{AGKi}@RiKg0XX;Eo-x|?66QtGl0 z>VC`MUl%GMWwh^3axR< zTip1N)%Ez*{(T^rP94Q6EZF^)jTtdwkSQ#M{})v9TegfY|2DkUyhVrauL~T8rVv=~ z?P|t$tqI0&UCl;u1kALIn8)G&$EEBiRJ-Kq{+)=055rIlk3hIW;c#DoWc1H}6ce8} zl6yqq7J+`K>BAk8hJ3>18!K*I*sqm8d5RGWZz69Oo7nC{E>2aT9~LqLAzjVbPI*vX zm}jkn&m+3A6|=Pb9V4fiY`VW{Z2x+uT(=%^5YHW^QAoF76OwIXn;`rFe=+c4aO*Ka_|->bVI`T^`7fYed<08o#+8*Pac7>) z3b(&keY@dm`X#JSa*c(0&p%bial(3;RyT)=oUaDr4DT8aqb%ex>|vuMfYTKm z6SL>*-50Fv#f=`Byi6wC;OMmV$(0k+o<8#0V4*d=D zukMIwuDMhK?p0-ajUF{`HG)B^+qNS;2bfM`J%TWOv||;c=6&etDX>0$FG6weRs}}f zhz|u}5B@?=djHi2g7EG){QVhm^has`(O(?muJ`wk(*G;rem$??E5nw4Aby(pV3smV7`4sO$@o5TOJfg}V|Kms!o? z*q0}0wr>6{N(vl@#*gCTxH>Oz1oKd~wf0%6<x&u3BPn>J${}Sf23Ot$Xu>PHlt)y&B7R9)${puoVR8XZbS`%}4v;daM zG-)$Pz*?nMeN1ByVWu2Srz-XNU)e^xfZ#E<`3mJqlt$33o!B=wyJR!$w4rzv<5?gW zWPUH^uf7yAELxvKQTo8s_-wAe8A~Hc=Ir4QIEiLxT_^6@vr`ZVp6 zG5-FF+3wuOnDN^A^RN2*89cwuALaYDf5v|y?YAxSUr9&xyFa}LcTzG+-l|jbt&EZz z@Ky8aK^hpty>i#2k;fp}pB&Zb`V zg=j|Od>($c6T^w^Na1A(H41Q<$uiNrOd?I36RJ*jTcg;!)w7@Ny`iruNp=r3KtqW< z>Puz#4e#P%6VA8r*1ZGa;1j;&AC}+|mWhebez-%;B?(LquqV7udwU4HO!RCh=&3i) zzIR=>r@9vx{;IjbKsj3>j)$}Pf*vp8>5N--Z@uMC>)ye+aHA$BZH$E+$~S_ z(n#ijzhBtR*9jXI5oXqsBEHzISKG&i{rID?Shk8uW2nVUn^;)GZnt6*XYPv_l%au- zGS~mQ^pB(_PVMC(JWw!1MMdMEQU7PU=3mS|`4{^?{Ad3E`5*ej(=m?8wcutnnWzFz z;T>mTo11O-RaxXt`1|hehR=B~Nt5|Sa_qckH!MpXXCVmehHGcJ6OWH%38x${0^NfD z9DeL2XDe*h{m0yY9nHj!(nN%;G1{+I#G%mitHV!FP6__^&%(7g+>VkfQrs-y==J{| z*}bpZ@H@V!gIuh`@#kl9Njt1e--o-{7W)1I)zcT9NyRBtgx~~fJN#rLOetz7x3Dbq zbBZlG*L{I%bF_DVLB~uTxGD0i{jD`IQnJ0X3g@md?pO|C{J;TnGst$lP-UJ5_uRd1M%iQj%j((K>p0 z;vW!&c)j*NRhctjP)T3b{U0+@I|TviVEdIdaE*KpysP3*T(j}W0UJ_{m(aPVj(tJS zK}aQJ>-y#D+e`9YdVj5Z{a2`-(1t%#RV_pW|fIYCo|iR*Hd^z0z=h zMi<(|P_*l(YHr!a4oO_)9zZ?9UFO zal*o-6)Tsoe0+v2ch%~ORgaZcR<5eBtz0GAR#%i(maY_SOII$l&2kpZu~n9e(rTM) z>GBn&%Wg!@@O8{{T(+gFSFc$9*iv!%s+G2-qFDOGYO&JhTCoZtD<8M5T3uSf;wo*G z>nagzdt&K2TiMc;k5f60f+7O1^a%-%iObfO3hFfQt(p!amIJ_~WGa=o$WRAnPQ)D7iHWlkP2i3jLO#bIS6TrayDD_TvM2nI-EGqp-6kJf$wuy{9)Dz}$C z%CmPOuspx)1^)FZz5;8@&f!ao>1%~Fi(lj35L3_Yq0dvd8ECoHC?;o45{;QlU>S4* zk0}_ICTp4VQ@}a_OC_xh^QrpM zMYifV(!%f>yyKNG1YrlICxH&pUwj!I_s|}{g-x0}C_XsZsYRoqXe0UpXf4MFQj;Vp z!R0gkimg&mWR>9BNgw4wX8+*SN|BI-BcDqdLUFHMfRi29=0BIZ6oV_v{dXzFXWGgN zh{GYt=kzy%@3lGD=TOQ9LuRZrJQO()$yf&WKwh>UfzMD$EQ06;t18ve(PE&w+5@;1vWIg@&RY7ko6kU0i55v?-8WG(JPCP&cJ6rP%1dJB8Y-_t_NtW&$$@_ zFDavI@=4^Ux$fio_Fg7w`s;7Iq1?VWUmHad4s04Z~`WO21**e8$}X0D@RtT@fvxk-O{LuBqd7NM+?_c}Tqu-BBr4JArYcPQ!J7 zC8#a(?xDh=X6c6n4FvphO5z1$d>T5bwVE{_S^RvsG|S8j$EvjG8Hd0Zg1d>~G_SOUrA z@qxthgn*^o8Zeh928`uN0ikfzM0b`K<4zEhw9oLEXx%%KzU3upX4k~cBVWKfsF_m0 z(ZCz~@bXOVt6&Cd=Q2iJJgzzFcT=ZOXmPwdt{mu1(*a%!ad^n~9-8 zYrov7G*Rc;6h|_QWyUEEW=sd8LdZD4P>^@)Gf+HlNS0To$a#YNuu-08mWwS9J(Fi!1QqhQXY$fy zSE_4M9?;kczhKSaExPbh@KdZs z2=)Kp{quUA8I7NJ?zVlt{d3!HNh1sRMOWSf9L`Y_yG%a^z6{bWgpKWZ?J^AmsT#$h z{KYKApL-;8q7=J(owfrRM=zQfobV#jMdS_i<(+{&RHAsI%QOiuX7T;N;fbECtw=72 zgBZel@E(k(kkNqw&fROZ`v@8x45Ji_(qE?10j+Hj!Pxtov2y;czj5K$<{InCpBS_I z20eL{6r;r>`+H-9rst69z1`98c~KvuZ7HL0{(^8HbLy~0zb(fTebh7h&p6_GJ!s`* zGWwwh7q{TrH(EEbl>)#2G)+E_Yn&RQ>kYXxF>?;OR~&>itp;J{z0xJvF?zlCN}ojD z?8>et!c|#sH$>G(WB!fHnTa<8@^2`I!4I_~AiVj(dh6UG{n#4E0en zbH0||(~%0(RkZ-S`ipd)0sAEEcJv!d0w#4@&~dIIishr#s-ts0%tBSiIj1%_i_OKX zT|0>1*-f?h702zQN5;v0M##)22>5C0iL$p;lX;_Y8+`}ca_tw^|24d%B-}7DgPDB% z9suU~ElaQ9O>1-js8-Spy@XE~9Tiv_W*Rcbi*dlhK=-<+@e=oHKoJI*5#O}Y3^QU& zV4XS*cEo9c@2S&XH=t!WqBG`oGA;>>!pSd~UaMVPZEW2P}M)$1;jOw&LLru0f01quOAE4DP z?N*tfjo(WNGtFP7U?_=Gx(*qn30Nbc(GdJrCTmA{eK1Wlv7A6F774*hvqrW*AYG7? zS%g`63RYc1oZ2suK3JKe4M40fHwEPgK5VP#gN?xOc?vd+eYrG75tmF*g?V=7Gy~Bv z6Kp|qp9q2Y=U?G=7|+>3@Y*iTQr4JZN|mL2$C!Qrchyam*TCI(SAJrQ6s_c2?7<4$;+~dh= z!{R}ZmiSEU1%P8o`SY6rcJml)fP~k2@sm!x0S=>LqT?wQ)Fuh@wQ3|HmH~O^6B#F& zfyxew_4JslVhu-g?QLr=$s<2N2n$wc_uAiGV`b?wPQHc%R>8m^uiUJ#B!O6Un&GIJ zma7_*?5%4qD#_buRRgKXkV0)d8q*hm)&vGAQL>SxXpQ=+{vm^!W7Ovk&L=pI)%&9l zpmD;n&+EE2g=d} zta)ekL~U>`*VqeGRtf5?s9w8dSu@b?uvEq1z9+jnZJ~BAkd7{+y02i@p$jIY7+`d` zI?etkF$t?}$R4BQPUpfx4ZA3Tt~cimX6u!Oqy~fBtRPXVno#~rcmt!EMvT_n;+tA^!(+itaN-(LE zBxW4JKr%?7qVxHD!Yx|J1@K$I3|&jmil#wDxjfl{$@;dk@OB;XU7o zJ6Oqju_sI}-mW`hxYx={0mD-rJqCqXT^Vq!xY@Qr)hHl%#L5ZIBO-1r&( ze#jW^5W2W+)(B#_=;IsU{0Y<~2IT*Sc3uB&i!lM})ZMiTJ$6{(_G{W;F z?lLXh6(!wYsMX~V*CkE?uL#lrL$~fdi_X7FlhB2Oq;y!PU&6!yU5(r}9>x|;8;8n0 z>7DlI^$Bzm$7mP`68$dPfx5a5MTw@gZk(opCTAgW^YK`B%B`FsGaGhe&0~o{oZ1T9 z_DedKDvl}CFtFL3wIF_;sVfs;f_Ej7J?Ox|&uCu3tMs*#Ntj-U-Z9LFgJiLOwjPMe zvA0WRH75xDxz{^K`b+32me=1sGeqCIoi%(%@f8a4MPs#`Yu(${Wh`Qbr*QR%>rAXj zK;xLl2jD%TbG#I5Junzov*r?(#2EZ0N;e~7vNW<`p!*V3?(R#Aq$KNsTm#C)ty(}T zO*#yzxI8)$(g}PZJ(g^2`AA*0k#ujOiPqC@xs!UCF4dJ=VeA@Ir$HFh=~9v%4OpzZ zAk!h!E!?};*%lb*bwLS&o5~gu@&`ib;%Pnt=y0bADsTKHKwwG-2yhbZj!q1Q;Q9pn z`89D^*Wn(#qRtJm2T^@6U}0i!Tp^nnUC^oHBk(l(75-&XNrt0C_!>djcQ-}A%m9z- zKF-$#v`(H2T9rp&Q9KR3LPCN>8q?f3TBlQX-!rTOs0)}v5^dyIweD>WoBnh_(?=*+c{axRjr)&qqGpa7^pNQehdPdpe#y6GS-3mAI? zmZ6Oz4N}Gt{n9tIm*d*VaJ|bcni-l$tJ8qv2RM!iu}3fkf#yRv#`TWXfUZMWZ?zZn zR>Vn3?5@X7(u8&}{Kn&jk<#zpV+dv>6nK`})FD(4Vp6gQw8Dc2E#$*^rBtGME*QK# zDgZuD7dgsPBJt|KAM6t_`M=Vizk_E3`d))Eh$ma4Pc3xqAQ7r-XFKLWl2`0Jg_j*9 zjD*0|io2wz?i_d2AhbIC3slED&hi_zud*=!UUhs4NvBIGI_1L6eAZWws;N;BE4O8<#Tg$fW9aQnbFe?LjqS!cKZX zuu6bI^yJB6FVYC@JUBa!R3y1}P#)J#%I_yneRU_-uSdEzs;FvgA69fYJ&jXz&{(su zPo5Vrd9DoJnD0{VpoSo1E5zE!N*PtFsI-th1cfS6iLhG3aHi2YrFX z>NLPfC`59?TwoI1=Ng*SnZ^(}_LlX#TdFo!0W*x@!W@!xR)&7Xp6=aQv05m8Rtbq@@7^L$r z#jm$~GM$sMXaZo?=Lgl%3yT4>_JeF{Mlzjbqt8)D!KY8mQ;E?3q1-p&kQk4Bn45!| zpAxhX2V68x)A$F5?L!t{PAUPWFnxi1Z<-FFwQe=Gm@ZHCA^3JH#jEwzkwmkeD^a4w zb0u0V^wR{PPV+flp%rg~DFCXtdbr;4PNNoE@7U^d>_#qt{W2{OeU5q@NWxZzl zj2G19pzpzn_qptC*19|JVV4@Mb+_R~#Z95re^#WIYg+$|jBlWHq1;$5%-5!5vmvQC zUUu)JD4UdszMt#45)@;aI8S+fC-Z$2| z2he7B^{tyQdTkk+?fS8+`;y#ZJ$MqDu0yh8lbZazT=bl3c~&*5hzG4~!Xmn86OjHI ztqy*SqIPmtT(H~y8o_9jNXBzNY^246V8Qla!HbIHMfY?Yyoi@< z&&6WwhQMH2C%xD(NGaG}pM(T+&=$%d`Q3B_Y*K6V#9YF9p|-xB*VTfP zxMlnC&c=_4w}FkPf{yvxk2!e6BNMUJg$^A5%UY3K+t3F&wMuUvTIQR{#<>6cy&=^cNu&HLmC3H3RK*MAfPJ$KShR;>RTv;hhdV#qx zG#|f~5B3Zh#7Mc*bJp5))mYz56q)4d8L+|RZoZ{HY0g~fvwf5*{jgJ=X>h`<<2eY% zLehPd#q8t~*ObD3b}9t$>a;ERb>q*gKk0j|{#~!Xhra0<`A2yu{l1%lbqFK&P1K)c zO@MDtk0izJqcMG?#nZDE@00ZRby(Z?+#tp6yM+ay?fY(GZ@EiXtgyK%mOfEx6DyWJ zR{H4D$G&TG%yCxEh>x?`Ca)F355UgWyhezepo$o>0{F!?mTBvhMJeUBvKD{_3_J^j zmYcbq!fKoLYjiAza3BM6my+J9OyzcnET$=ojpZ?A=Xj1sSdK!?jimC0e5CdSYVcHRhTtXHi?_!SblG0M9Z3Swg4SXRcWO_{t~98YZ`_^s(;>k+w39ii%Ygf^+HP zrLc{WR)|7==}MTptgtyNR*{(vnZ)F=h(eK?uD_Q)&dQqyOB*M*v=Qd4tXjHa`7+xB zg@yfUSXEV8Q6a4qX04JQT~VqR5D5aA>nyE;Va`&-hl{y?^<%4+l?pklq?OAmb-?dO zQ83F{Bji++F8%K6Rm)e3!n}ex!mQFqrN@O?%d3`G61FXNB6&K*)TNnOr`g>?xjlFH&Rd2eQ27v1MK!_H!x$T(nnf#DFZ+PO#~@++4Pm z$A6#YNh^mf%+HVjW%hNW3vo(G&ykkAkTsH%TFuO-R#WEy)hoq{RVyYil(5dIEL|23 z%?*b*U~t89*aX-(*-DqM&Ju33p=(xEWPylFm#zg~N*`svkFnon?6-0`g)hS|5LV1qW-L~l3XZ5ex8hqr&j8w}L4 z%Hzs5;T4^ACpO#VQH9z<*gycmKjNV`A{1R0G3M?>Jn$U2Tb(w!QU0s^amb`YKHS|l z+gXgFI{(Ev=gK;1SYKzoMu~#jZ%1S3P4iqCv}Tg~jb&(oAdY1@ zt*YJ?9Bf8vFwwuQ-KwM;Vj9M9w-^=5t zMC4s<*5>laH+kd`mKl~EdRr{ocpl%(GpA_pQ>3ZvLmv73HJMYj-&6d6vXeaiNyJ0&hQ$oCq=9N$Bt2)gI}_5uOU~dO zWb1;C**FOhhWVTWxpd@ak8_s&H_Fn|*(kDwf^T(}X%svN!J)9*oMizDy9z=Gg-vvp zeMw<|jtHCVEIUtOA2EUn7dgdQc9DV)BDfEh*I<937v>!2IRwj-!&~jml1V#94Gn5r zM)JKRiK(E^$_ZxO1L6SpzB~?3DTz!&2lrv}lr8LWq-AE#f(P=P4%?jj z?z0s-@{1pEEGU?H--3eKMNZqCc@Nm;BEmVx>6l+M=YgWa1sV98GVlI8=K~97It9nt z<;9SBdm^&_8QCe}EP3M_x4FF||x#ns%fZbr> zvV`9OZmchjdkAhO=zbm{*ukz=e|nZCx+@85#*_~)QwOlVd>UJ`a-(Y8=EOIx4yq6U zzk7iZ-tv^PU+_eavP8w&_i;`RSnb0%aSR0>G*hdk?g(lVu;=tk|FnOCRWr7LM7dJODz`AVS3Rk7-cJ~j(Zd0q4|UdK5d zdGZ(!5XoD@Ni>yF0+@_v?ewIo0c4T*JT8sUP>gPE zA4VQm7wNJzGnN%64>&)@(nu}pfnC9WFq1GdcI(oBE|ZFOMu~C7h1%;p9P(DBpjRF$ z&og>j&ADKyRX()@ws?|u2r0@ml!W(lc-NB-p&&WF1HXmk1GJw~sADd$CeYoFq+)x?qnGQE*$Izws7dXTVepN18b9wdpO0yE`E|-TvR48NpXsQHN5{DJTDtFfUvF_y8Ur zM~5-n)00&7DfY#ksDe<22jRqLA}scz&WL$0!Dk|@C8Lpn@sLTdFDJfyCPEl^7(^Bw zpCdpm>R3>Ivo>!UQ30gY9p^%UX__5@Wn>414l&?eJ4eDL-AFZTdYV)}gr-y-SBNHK zD>&(C^PDw!s-caEcYk^nz)~>Q#5l4Z{=oWm2f=AKQ7uxkYX`N+WjF1jPm?C1KH6Qp zXbc9Cmg`oTl_W-ZOdu;8ee8if=Ty1XtHj7xNN?)CoFxv*&TTN)9ueaj2G<@Hjnm&3 z{qE^mFrI-O(%ZOs3)fsp@AWB{NZwXhyb#iQ*FHnSe`Qq0yLP?_@@6cCv{2u9c(L43 z(&8<4%AcS7%;k%D=%LehyHUv0<9EX^%{>sqdwTAX#^Rd8FV9>$-gx}%nd7JLw!Rwk zQ*qGA&yL^yysKvH<>2v&C>|QXjK+r_ZlO9o9huZ5+{}VDjsrdD4o}1z)B^K-)p6Ka zZVVm;$HBG>K^{A4hsT3qD?y%r_OTrx+ow2>XQn;Bh>2k_7j?gX zV-vQNHy4=)ytUx?ZD|iN^m3e#4KUlKYTHmK2_Rvd!0uxEcU0>wPgEV9@J+LXH?gL= zbJik9hL~Ke-HOr7;Twj8*itTsDX_NbPkrjHcc!=mKd z@WAQPad;#v`Du7SiHZ{QZ*y&4I7PnrjESsAM}OyGvL6I3!5qK^vGBFT8*P2HF^pR> zS8)ODkhUdoi@>i@I;V3s9#EX|+Tw;mGgCjdJ`Y3q;i&p~#`-E#eKC~y`uL!HY!tT%$LQ*G7I#XHX)4uF{VSTW(c$j(}FB~2Ss`^zb{B%vDckmd~+*m zT~9*=i`Jd=U0(%dVv zqIsYBhoLa=t<0Y=9u^X2FdAcgnz7fK&q<9aUuX&#<&r~eep?ONBLjZ%@rHau<_zhM z;_~Q)+V%|eWotBA>)sf(1ZMwvLD%L9q?{~m6_&`Id3|3(U;@osOQf+l#Bx)AT7J9x zSTR_-S#zR1RlMDR0__YE=^mOPv~g2O;KvS*$mbgzhmF}dYygeepG)fvtd>8cz8T>+ zUNeP}B1zl+Jr`yVObwm*I!h&0GLd{7}6)s{1)kL1~kwRLa7FGyqv&! zFV5<~OeiG(y8%6uafBC#qI|KWXyL`dd5$mI$v#nB4EP0(GLx2=&ouYt&C_i)*>-_1 zQjMY+N{RExf72ujdAX~mq-@si`a~lfjNMQ zgfCjl6i_r=(l%xTw>+sBm2nb;ICck}n!o~vXnD9k?q8q}%Z}}MK=vZIrPVBACxx^0 zJ1KdY0Ov(o8rx;ixuP-T>P0`LHN0jFxGTm`fX?(21s;Ko`bMTY5-uO>;m-BQ3T@ zk=?^Ub$*-Y@_-G|>ii?PgA9sdLt8FlrE?Mcjl%L|O~L?_TgsEkNO|d4Ft_$T`!y~D zh8;1fSbI63uqMX$tr;hYF{hxfh?$+`ak+@}fRRaoV3kpOJCs4!(ar_#(38d59}v;c z9t-u9n9I$YpG2Rn@+dWR8#ZtNh+VCbXT;LPsT~>v;9&a9Hgc#J_+#*8oV1VHFa-P2 zJR^bPKzmS2u6@+TzYr7-R939r(^us!HwlaHxmB1rabie@h05hKIKuf8)JgJLi}k7P zc*WcWvkzGK!cSr_H?RhE!XD%n*n`|8#aIvYuXzH0$BK z8pQ9j?Jbq2+`x3$cm>5ND9Ty(pOosMP%0@I$NOGIP@z`A!m#L+24HCWqKMKOqU&RF z^PtjW^8$_shKyLOwF}Y8@no=(2!oA&HhW=zk8*c(wME6|umF1>?OI(jh6&7`!^SiluK zwGTgLvx_nqQLS*rjSFqT3zKog`gth(v{9@}$u_;$UUYFo66+_-C^^bv3j#Ktr!Lja zcvzqE{YJ*gj4u1=4OzfB%-9s;Zd^ME%fZ2r9YJIio6S}Lmkcd|p2#1AuI!KFQ_iS+hawUhHWCle~)44Cs>JB=K1Q!B##@@1zL*3-O^>aWD;q+Hbc$ zQ$=a9V&`sX!!YVPUjHT}rS?ORlw-sKSuxgo)5U1v!y4>1$4!iw}w|*>lf2e zgN53_p$KAb;1_B^I2lm$qSN4qHw7!}&x#8dYCjrJ@e8$8x6#>E?J)27h+1$pBh_fE z4??n73Lrg)QsHp{C(E%mu_sxdS&py}*tAaU8;3Jk|6=*XF*0z0b{c5|H=rF1_94N^ z+TaPOzZt_7$z-QdAFLq@O)9UZ<1E?^N(kK{gFQywbQDCRqRX_Y$ABY1gLjau(7o0$ zLxLS_)K2>1XXWG*#0E#uc#X=OA(}InV9ZXEqSc2C>@bX9KC^>PF1puF6~t(D^;G%9 zcqWd7n7BJ~L2GDpf(t(lJjr$0sGbWgF~IG|Fmw}(gL^1cyXhS^1Ohk10|ogd*MkQl zxG&N7PzpK$zHsLON9@`ecV?Ub8#~sXC<(VfP-zHUA{kqaag%t2K^n;;tb2`d`k0Lp z2Q;|pWO2PQE{8P*CRX-VX_wqS-b8q?H?QBtvm3=ZSljHUk|SHji&P&l1l|AEJ5d_b zkn{J2)>pG}?(`?{ zv(w;kd(LhI3#oBx<=8RE?CzYhwJKU)m7=ZJq+@Y3zt9y7zNkFCna_~pcFrXT z8=U47r34-6yU^?4FP{C=kqp**dhi?&C4%*@r-@M5WmT+aVOU6u57+vEHdYhoU%-S6@m-AQ#0{3A66acRGb7lV%7r?wYhD z^KMPD=&g8vIJxRU;fF~;G652wm)k5teMCHLflrp%75)^8iQFx(NhD9G3JZ^kO zprTTgdwo(cPKp5&5&}b%Efl1v6y0h}iff$($+p6ZXk|VD7Gs8zxAah=ZS+e@ow2kA z#d_yfYF9a{fvp17xdvIKL~Jd3ihC1KSZ2zWPV*g$$4S14;t1wgM`v}>xG0F{vfvq2RlEP4VK891b!qrmeMy zA&<|Dlg{$G-FCrRy9YsZ9FtetFtmQlo2UsJ&L6rj-z;u+UtTO_z?~_UH;{{U0+Z+@ z-Z?~wKz-fgz;s`C`4{2Sv!8korO(BOqIVnE0C>Pl9f*-H$X~ekQ$<oOT$)Lhj{ig8i3u?6?g>sPh9EBD1p8w;d@E_=zLx!2D$Wo+!@C52BZjxs`v$jBgmv#RoRp#CC}!z%=1+FA1Zupp0(f$C018+95~>E<3c@xxDxws|M!tP$Y=^>K#Ujs7%e7~zY$&TmqGFd=@a@QKXy(?2r1ee zj3?mzGL?5tt{7gHy&Yc65sj=kgW~9ckRo*-pa=$rfS$u;@q!Q^-q3Sfxz$+UK(P22 z%+0GUl?1M3u{0qlr3EEhP)ZF-DZJU(fs^LagiWTBv_R{?1neiTq^QH^VB%$;gO1GM z>qY)}nH~^~d77X1TsBlu$&b?ssF#VnV1rI3xCmQCbn=QB9|0?9qS^wZKm=grB&a2g za>+iJe&ZcEcF}{{q~kC}DM$^zuj4Qw5{FU@Z!Vqax-sb3rIhSzjh=wh?)%UlmP;?A zAQ85!o}Teia?tK=IHU?s^=?60!C=HW zhnEErWA#NrdKIv(>*&jit|I!Ru-X3RIGrf!m#Fb=Q_hD+Tg zUQf|;LU+k?G^mE5bDc_wEqF{RNb^y}wCKT^xso(rG<|Y{QHvVwMf*hD5QrkIYEcuu zn68I}(hs*sI)EXVeaa+!1gs&|C^5I zIQ-G`+y1qo5c)fZKg!dCCjeZawZMuAVo_!A@ezSy;!Ozq9fi@@JdJyc^srxt(w&?U zn27Z?MMJsab>XZY3Wfdr7)(HbKJz96#*E(K(Id#qC+%bW#Q+JFRBw@ewL$k)f*faG=WpwGYO z29`n&eMIb_boVq2cEhjg^oHE4)7vUD*fvX@ZNNE6dsDSt{Q*N9)fE@T>$>UhIWr-E zwl}TU=x7%tXGBX9k-0 zh4NG_ky15dMJJ;``6CQ+Ks&S?_p=sj?s$wH#B}0JO6aU}2u{!+$(|jSF#;x?Ec%f^ z3TEwNSYA*m@Oj5A9cWr%^PiuLBQVW+zOaC2X6;57(W~ho!Ge;~F32##FG*|)#JVpS zJf9hyRNh^X$ubKIIs`Pl%Mou76PUK~r>H0tA^sE*IOITk_hN0mI^d8Wg|v%(OFzEPu3;|Twsay8?!rkC^^#Zgu?Yc*3XJ#{O0j<+ZHn! zROGRP;xjM`eo1D8);coCmwh!~(4lR4L!xH`xZWfjAJ0%mZil=Dcd6}1M4p*pT}nU! zmZ-GLD2mw{%}cb&4_mtO5~IWzwHgJ$Jn_(WDF1HjGQEJO5zYcP;i+wSlWhySO#AfE zT@+fzLmB&_Lf~#A&*BVLnd!EwC($%H2B?Nh0CI>EatWY2#0j|s5GOKcIOCk)J?9>?9$R;-uZ^Ag?MYY<;=k-r@X&bd3EFw4;Q6jMRIx-RrEC{Y}~lO8y*h+i}d zZ*6#c1%EWntY5E;q!@T+wmZxfkJMbbiZp8$@$|IsFQXr==?yf%CudRK1C+U!EMSET zFYTb*>Fv&PIQ+nyq1~z7h>-#MdYna(`IAmm2IOFg8bE>t=K5qPNgKb;_i;g4K0`pP zB{A()IUlAtiMtXpAJSUWe+9KNpD9u?NM%8YRBj~rT4k&yXrSZNS3W0}{KUXSFI=YB z|s?8`)hQ6tx$XuTY?+eT~3y>8D57ghW zY>Y=K+}BEAp*pSmq&zy{VrRJ18XV?&N03c3sua}IV4mr7*^=#Lg`ouI+y#0o?%$>S zxK277j_FQazF+}SSY!b+7d)RO zjya3Igf4?JCL$OjWU$}?=&KoQUyYZU&`~BfIQ-xZ`1&5q589Zu!dY}3*(CHgTbl&# z7-AFTPXzXkoHyK!RkhqAcaHg@ug0H}LW&(ZVm;Zv@5}Ckj~Xo&KtX2?9!yhTq1J+w z=pE0K$x$0(a4rL%A-#34=aO~9=s?tqbGqR(3U>GAZZ-u-U)CRP@<*jbUwEm$>B5Wr zrrjbl778KJZ8s^owbi35}o-6sRLU@S3z5tx^Wzyk19xhoN8Zto=@F9SehCgmYx z`rG9OptB-bdj+y&FyJTySCA8|o(^~_G?Ph(Fe`%G2Z6M3W>9mD@d&Og4+I)?^DkpK zyp1}a_sNalwS-eM=@=nbsI=BRj~_9>*dw6?(=j~j<$`HM4c zU^37)E!1ux)y4@#1xB+$)@6(}i+4aReyo~g8}7{8M~Lvxb8P+J>W*$0xu94(K@$+l zg3eNk=f#t(5_b&CZ6Pw#=Z$Qd5@|68{qG@C$|^%nad1<~5N08rLkoc$N7j-9!P-gR z&F-)zj^br7VbpgS4e(|434-7)^w4~5H5ovi!Y5$lv=arZ_&$3^eEglkDzdPh;KX! zBJyYpwp398Uo9;dmGhYz)Euo)u!r3Ln%O%|i=K1t`F`Jbzx%s)w>x|G?0K$PGqYyR znziJ05W(q^#9gJDq!cmo>W^6)#zRIAQk(jJF0~nrB8cd(E}070Q3bF}-ZUF-K>mjM z(S>l)=I&bo<6P$4kldZ5s1O<*f##(4g2;y(!O?Ztjhsxsa&u(v&XcG}t^l=!J1e+r zbneb7?uzzw&#g&~q^_9??XmbpSs*p2=qNP^k-r;VD8O?bhOiO1U<}Y5cgoRAVx;=~e=+_`aikq}@xp5Ua(h~LQ4<@f% zBbz!kd&R>mR<2z!bt<(n?_)qgv+7+J@J^iGw(iFC)^!&>a3G&FD*y&N>6wde1Ibl& z@mu6Y9Wz>-g9$MVGYvxiu?kZs z+X>iSSIW#kgQTR?cQqmq+0P0lhaO}N=*vXPD`Xsgfze`)oslD>qlV(lt z`h#nGm+2bgl=+(6N*8J5J(nxTikR@3SAcvK!Bj#fx64c_w($)|vZcY&kvKSP{xrwE zA0rJ|Za_7kP-k-ul2-`2PldWlcd*Sh6&mKr*%|(ripi;AP8T_Q;xOklkbae(zP1zT z!a_IfZDQw>sg7s5nJ~727*;`4fq`*u!1y+nctM;-H1*|OHx)B~Ti50F@e_}ipa>t5 z8*Mr^B%OsSNpy?a^R`{v@TdvijbBnAno7miQji8ev}^^wVq?b?Wi7p&Q$4PomZ`(J)k~2DNzV<<5yk@J<518;WXhVNmUHSpkqOD zT?-QsXx@MwNTgzik&6BfDgYM}iG{{KzzGyK4W1RmCkfZiP=VgnYqT@MO`S;nB5{$w z!0g%?%8Mi!4#-)phpi83>4N#dW9I9Yjv@!??sN*6L}C%h0UE4|-^7qo;n6|X=9iZ- z4Pq#UIb6L)m=VsZ1y*9ADHWNVSHO!HOV3)rQvCeVeLzOUW^&h}wPrr`$`c7S zQ8E|n@t1(a3r}Y*z13}Jo4>4VrhXhvcVKnXhNewVp`y@rRN%tEPb;ERfvHekgAysB z#DIiEe4pDcA&(yAYOB55FQkV8AVGf2s6t_go z>Us#h5~LBEj|1K4LriK8qYX5P--9hys5cDdlnj)R67kRiU1%@}v9P&q{9rP*1w^u( zV$eE?mc9bY?{*R#`ZIXsC>^aw!XUl52_1>XB|w)!irlCb;0+vP)8x%C?;TLVUc7=M zk*e7GODqyo|+NPX1O1}PEd-(VFXCFBKAP@X`_6zOmbaLcB`eJMy9 zhfyCKpwYQeHE3rEGIc#h<0XyECP?agL90v?%OKT@w-~h?-fP*U`wYMVYViJOrM$V(tCax)zHg z`x;_er;awmh8}1|a%1BXPxZmjGA8I-8bn_bN%6b8I>=I;h;=7UspVB+Aa<`EB8{h6 znR)xjXR+TWmTO{Anzh(a%W=nI=3&#~BEGG`>Y{D1U}F!|ez?d1_yeOEAL1$@blKeoVa{+G9PpThas`^cLh-ff`yGTB0k-Q z#ME3{(z8g!WOgAP0CV35MZkit%#fz1JNFV)^LX}*xjIj@(!fJmmN_IR3;z_n& zwu?OIoQUsED!qFdh=*O|0$CBth$PQo;k>;Ii}yZ6{`nD(MD6>Q=A9Hyh}++GT#wB^ z5cK&MOLWen()Og3i`d$ir3aB(aUMfo##~6De5JUi@I3bY!cbaSliNLX3g8ISt4&X1R1h$v_&5_Ji8I%C1p ziHF;K1?xP}H8g%pH*k%2HKy~^GYHEu^}!?`Q-sA5;JQbdI0MqeWE%jL__;c$?Tm#~CgLrMLoy)@I9+Cu+!iY{ z7?qI_em)&Ox>}<|lVCYi7aqy@i$dLyFKv^F(S?)A#SH}ykY*>^mr21(HsPV1CCfIV zfQ=H#b?OIy$|jLszJL`+8_vj^$&qG_}4!R zEu^jg3^q>ALN?0wO*lb`v!FSQFd0LR0Gi7puO@0#K`3W$`*bM520t*7NiJ$D&E4qi z0oP*ex!oBrBr1JD5R`WqeZp$!>y7u}z%DeCX=EDEQi;maKK`cg=b`vLUB|~DI^@^M z|8MF#egtXUr0baTg6{(=0f$fy{_eR$dWT399UJkMA{ z2h!6R0uig<8GmU|3LJlf+}--O8-E|A0BrpIRNP)`8-Kw>38G=w)m<8V$>sujPaJt- z>XnA7_B`olnfR=@7L~@`uK|<5arZeaP}Ci_9Vf(=sP?1W6h0{I!%siY`ahR0Eb z28wfv;zYlD5)bvk;?8wg8{wE*u!dr%L*8B$%pxnxDKcVG_@d9m(Kl;;a#{xDs_A#k zBP&-dUa}&0rEK&VcBacZxe-xhW@BFdEKokQZ@eoGv1yuz3~hQIeRjX_Cv+FRGtWX{ zy0;HAPz+;3n7l_3fJfOzQThQFc5Z?n^xPtyvf#~dmj+*i`w)55o*1*(^x&9fD<8an znQ6)L#j-InKl;Y8gy7*%h9BgQ-cA{CC zAfOowRMx3uOl#dFUoVuXexY3mn8rddEYZs8Jz$mg0W29ZJ0M^B&r?9z5!A!`CMyv` zz0rtY-vNr{*xmwq0dvMPsN!JcpXojdCvZE{{T3X;LTst^fieUjy9@hDObnegI8I+W zhWw`8jUYCp*lVU$-D!lWU|(MvY+>=OM;M_<7j{6b}SAhZhdDFJbvDj zyXV-GXl>8vyhf`~8(VA&IY-R3a_gjVSeFIA)K4<0+tf7SRqR zeW(s4vCJn9KA74BxuYbGc|?&1PQ<1v9VPM1r!PfHRXIwM*=rcRp1|H9&Z^m_j$M0? zeJ*MEhE}_^=^Kiat5MFiskUFou1(aIQ%>LmAEl=Zo7DPn``t=M+_Uxsl>^Evvos^+ z*M%<>>%;Ax9Lf(-P?@|%s8O)+*ohGLFW)0rIHn;D!9noHQH_fQLof!i)^M+HJoV?h?sZCH7K9z!iMPDFF zLAZ9UsxbfXOsp-i?vj7PGZM-*2=5LoRE4^C2^7%v5-vY4Hl}GHhp75ksE`;g!jd?lU7AwSIh-|#Buyc+o$%MJ67=7m zR*+eYqc8{`F|Wz!Ik3a?_xvC+^)H8C4xCwm8)F8>1W$l`=jnMr|%V$0K^jCUxlSh>nsxc*YO zVJsX827?{0a>91BdyZ`&6~IY5z{!^^^~5ONA*`|*h+D;!Wkb4a4~T9jEG(~y(l zj-w>2unkIk*w8HxKm}bLNV}j+Du~8vmLx271;tH=hECdWmL=v7 z9ZvLBY=_KJI_BUc6x889>QI8EA2b~89qNedLpu}@o<>01wMpvDcf+xv#ySVvFqk{h zClNOvN8b)Ql#e--)fCaoBQ}ku@4}ZcwN!%n;WM=L1$RM>h(ifkKn%2AXi*SO;M||n^n_sw;XVQ6m?LMe3~B|Fg01} zP(BM(bR;Wo9K(c7p`i-Ou|R|HUa;F0FqVmf0rC^VDVWPqI1<=foxB!iDTkk8nx92D zB4}kO%U?PCeb@(BA7ZNt#gmytr`q4ELdC|gu9D3vMjgd&Zm}2dZ$Y)lXLk* z5i}lOLY!f3an!}chrt>@Zlt=TGn}LVInx~+7@`^dik&&}z=83!CY6?lvYJ$7DIVBu zyIL}|*SIN-x8T6hPq*baMyV*#w7 z-Hdm-BR<`>4F%hNLDAKl69LSoE!1~$GOc7ks4eW>mh8imY0}4J-+*dT5n`_R%d&&W zhxID;<~LZ;T7-hPu6`*L?5CYg{VM>Zejm1xA#ZskmOw2t-35+@`7Om;u>^k%-YV@+ z{A`e&B83Y_RP+JrRZ`)k_Fz+jC*GdD&0g>dLMV6$p;1Cw~+Ux2P1qx{|*w+@n zrkKU0!lLj52OL-R=}_7oL}ScWsUIi#89FUeLv4YS)Wt{PqB`zCaG(JXsZ?*a;uSaw zwM#p&>QRfU9>*3rD{1mO#Hb0eJpy}ZAy66)nH;&7#}<+w#{fucf*sn~%AzA=aEA1S0Mw7Lx0jxRN9Q?@QOWE*sYW0eI-@6OyL^h5{E<+FF_~7{ zGE=;rt-oW=IYEL$c$zxMSk~(1A3V2#vKhpX7LwM)3((GdOtUr^qT`ldfPm3o1Y_W( z3DmJ|AmIzl5{_f)ca8v9WTa_sq&-O$ObCFkq7d8YqBYtT7EKqiyDk#a8gM0~^IGOQ+P2yq-h^TB2K z0fUbyTuykBXY%LyH04RJQl7TUq}NU)c|=JMnryqKt$PUTYWq~7z$>oU9L5&G+#Jl7 z9r;)JPf<&5{94f9CJ)aYoEw* zPBPNWKuJ0g4|EQnCwL+SNaQFbB0sUNYD47~Y=u)*WVwhq8dmByRzc<8Tt) z21}>pquoj`MWj~<;UN?q)&Eh)Iyr>IwF@3q7J8B>m3v_$HIhPOoDvG}kn{j%npfyo zuE;Vkp1XKaR-QR!^^(l{P1EmRk+S#!{r#&GjH~tcub*ySG2Of@!TeC>V&m)wO%R4l zUi{$D(c{)c($COwiz0_ck6kp;{}VZMQ5YYOXl0QY5xfjwP4|uUtycP0t9+}&AyMim zj(^So&9?T$K5z=;%&Wq0-fp0xI}O5?hsY(;;)K{|F*l^UUjVvFyhm{_A7d?qV(gQ& zA6qm+3#MXuh+RQOBzkyYWUFA5ud98M{9|F#`rGUwAi-#mr%)gpvDeVcKJMy8!Arrv z7=BIY?BDig>p{L(fht5LM3{%5*ii`@bANkccvM0-Af2d+N>D)=V4^ZAL1|XngQDb8 z+1AneP8U%_5QoK+Pr>MEWlWx*_t*+Pot)o&X`Dm%Db#&H0(=Y`7sJV?F5R)PG1EN& zK1=&#I&`jdcQ$}$sJVzQu*@4k zoX{J`IU-ep*_@73xrA;CoeR4MV6wjfo~hmJ-cU^q_AjU6P%flO%Ik>u&c0+XX1FQn zO6?0>+7pGayD2PmITB%n?NTDleAupcE`)uYOBBb4y}eC#{ilL{TaE5h@}b#(H+3n; z1c;pOCfU4AFfU^MiH*iW{U<2uZijxKpx^2<<6q;@?M}x8>^n=~gqK@~34m6T5g7Vo zh58w=MY!qjNRVs{!>EVn6a;!T{?vx+c6$ywCivgwc;Ab4S$1>DIrS#uOKG!Dsf$m- zag0XX4F%zG3n397%;p$a)4>OsJx8U@E>%0|WQ%y*lKP?^nxD34H$~H|VqO~K(|%E~ zD5e2z)~qcaN1mpcsG_2H98DoOBp6j3LoPwLL#o=2_En?vq+-=*(b=rkor2~o-41}n zGt>!&ORBa|RrI_~w*{0|saUE_CSVL(mv{y{?fPwU{cd!pK*%vXWy2UiyT^jyi~?cn zA6VRlEVIg16e-7mof^rShFM|4Zd>?Vx0+2rOqfnx@;&O0kTUhAZ{Ye(c(vdIhgXZ* zLHtSa@H4?HH4-4x7RL~1)FlL2+B(Cf&2|@9&?Lal)JO?-3+)_mQN?2kYVuH)^Og#5 zMZS^?vm-^xa4ID<7rS$b$ULbbyL?zyn|1AD5APTozyxwa+Dbc1RU}|)!fOkIXp4GN zh6GW^;zkB4zDJZtm_b7o?J0|NN*=)vvW^81!-O&=^H%K0j1*<<27SWzGhMV=mi~#; zLuXa8zY?-R>*^tSv>R`K6|(ms<_MDVa-XAUdKajB?1p}Y&c7dWHJ66^0EJ+hGz8sS z;*!Qu*vJp}$baUz6j#$l(0nJNaJ^zlym2!49Ik5k|&O3H)hqhOL|p8jY? zs7V=P4uK5q7*p6{XoQ4uCV63JALvk+Ifu+_qhtCF5G#scl1V9Qhh}7ePW#_MDGBa!)WDpW0|<)+xcH z)Yu15Agq2OVWS*J1XPf>_MPEWwzW2aN_VyuYN{w%K_Rf@eZkRqL)|-Px(@<23<46|MvNXI?g_iV`IRq2fU*Zm@Ad7Rx&);SS*mfAG~xp!hFGA13>aAT zs7t0HBS-mlnvcp);TJHp9;MgO>f)aGcBO>uA8ORav@mtDY0Qw~B5#}#5*YN~%-0ni3uVZUC z7KHf9f@h-6usn|isxLSmZZxO}%Ud`sGc(*}0G|lUu}!ZdFW7t_myo0Zg?Kj&Q?YwQS2byzW@vxD*Ine3PV^^p{giV$;w zih#y4k0tS!bOrROnu4v@$Cw9~_9Te3kFHF2Z$#yqW@Gv1n1K4A+Y1NYf|szJl%@!E z(*(x0fo>)8E$ao{ttK3&SzzjfMAaovplJ3I7L#X32eJWLpWBaksBBDQ?-K))q|JdYswqCp72=pU8(dEf!j z3k;Ce{%Q||6mE$fvBjR4b&(27cv!p*9bZIM)10MuI+&UtsmCtE@Q+GeDftkU(wJg6 z0E90}>m=sw)w6OH!)HR6?Qc)Y?(osYqBnbH!W4 zl+5%oeDfWk7x$b;Fx@g|wQ`)yUQV9vP&%gK=e?#d^}!TSFSC8aPw|d-r_{xK3?=Oh z?`Q~@CuX?&5(^3ALrDXG$Vcx_;6mN+q|sOGO3`T112hKbh%NCaqM`vlEvT;F9Cr`X zjKhZZ;KM|eK+Pp3D}w9_I~2p_imwQ7#c$M8-BZ?6#;SnkxF@>Sew6j%QymeLBaQ>Q z`bvAHU}ED#IEQQw@51rv?hgP>0*l6W9YgM`02m)~A(t*rMW$4#mrN0}I`i9ERV%y7 zcnImc@cz|v;!vNA{Q*81)`FfCr-CWeY57d)P6UAch`$^kXml?|ttI-B*4;X2gY=Dc zzyF0ulWe$r2F=RGdL{#&4R%t5<7f;Kypw6j+C@{5&@&dlHEaq4NZ}$fg1d;kpbIQU z>uxkyF!dw%VocbjRi!Z z>8Su3Q}0ao*(+kbO}#kQlAe-7v;)%gEq)vmc2dxo2AHx|U>9qj+%y8#8A24Su#zrC zQp9|@5VeDTXhvPVr5Naeu2_U@7tWnoKAO=*)S-khaxe%Mo{cb&+H?pShqWo?higYrJS;z)=GU)N*&e-rpH);#RsVyy zdm3|2WDt6SoY+y1i!@z}>ty-`t|(LIxKU;@8V?lqC6#q9J*7Mo*JPc@<)^KptXS77Sp-ul7t4DoDk3OlYhHFS_s= z#HwJAk+2#cHN5st@tePBl)-s@E6zS$=s)D%`vhorENH#}V=AHwX~d>$M^L;BI&CJ5 zpPl*IM-LAb+a{cMxR@){EG?9i$Qh>AX{LAD!0ZvAXWJCQ)Kq>S*iNk8Z9pE`Flv)Y zY$w}C|EQV14p^BX%uTG(=BME zK4>J!sX$<@tJB{emDC<0j^#IzMzMn6s|%a2o{!3I-EduoO^Jf84WqWAMi*;0RLQ{J z21_~k>Uo5L32&@q3xf~S1ATK;y&L@^Uv{NRZc;Vui^k&ZVr}Jhxvc_om6@eo7<#dm zox!2F$V85Y`MYK)o&}l&1g}a}|^aKqsP-K87E%<1kfCy_^<3p4)UxqYkEgGGa!o*_K z2YZ!0NqP)po%CyR0SD9vnVTCcAYYQ^mgGWU^I+Uqz#ZvsxC~&4>o$zWKRpMIhW|_g z$vB&P@r69m@`tEBn%+PJzNg-1J_TBjiHfgbqSRPvs*58KiX@|Ft-?7ph?nX`@lt+T ztnxc0BvHLMV0apWsd#4pfWT+aq4?p)%}gZ;6NXin#88Iin=m_NVu=PV2-gVXfETvQ z)5Hm$=_S|zHW5si=nt_PuL7o=+Qz0M2w_3(-yy7I+lg#K3gMH}96tM2*>#6RQD$|t&~$`yU9dZ{HKposu8SeX3<#4a>v3W!2HamFiLPJSP2A3cUM8O-db=( zW||?KXX8htsXJL4Ae|Dnme3+H+humsfH(rMuuh6J^Re(3^6CvPgNJm{VBCo`b)t9_ z{BI!FJi~>HSiutfp#L?+eGWh?RnUBeigtlo90=O9bT0gwR-C$U$KqEcI*Ioq#$iOC z5zq2apJ{rGu$OE&yUU*yL8dMafhU1-HhM=+2tzE4I@nYsVRlHS@~NZ=QYRFb041S4 z?>X&zi{Th0%tgmn2KE&3Sj(30|2MnIj1?5&A7isPc5^%n0b#@B(uqQ8xm{i2L>+Q# zQbKq&d5?MLXj?HCHTA<-!t3U0UpH?+k9Z7GcqQ@%0~R^%0toHn`)uk5OIUjS8L~v6 zABeTx3u$$90_aQTWm}3U0W$M@idjbx$5jl*G-UU7mT72V$2bm3`o>1@@Ax@#)*rsV&WJj&+h_Ee@hqa_4F>?1>2uL*(4PjS zT7R8tiY@9|++Z4Pg*Mb#O^cA8_1AmU#h)Nu=*d+VcZW|C1R_wkDKd3Ar_q}>!=r2< z4#ud93t1EbD%9w{e5EqTw6|#~g-J!b@5&B1U486CI!oR2cN72y!dUt+a6-C|n;u6v$Al}D za`Pk@b;5Wt9%`b~^R8Ji*`P$X0S##xNhLD%1&EQg;>`uK%R*9OPpFIOtej_dKz+M| z#my~0s8X7i;wz=CGWQU}&!g~z920=)1EI*6(E!x)DI8M(Qv_fHsl?HDOh}oPl#r=o z{94%Qo0LrIi08K1KGeeSsD&!ni+JYh0CgC%vd&uf{%=yhbQ!)ecwykD_J758s&%Cvn78!VT9MO z5d)AcEmRm4Vhc*8{RqUD1j2)i#m>|H2&*`TtJ($Lh>fhlRwa{`eC zb9mI9^a1CpA%iwIFlte}f)!a?(7N^;&p7bS&8>mo3;Xdj9T8fHS|XH5kBSZd2pw($ zPZZh@SJ%>qI7s`#x(wmm`5<{PBJ8d-tFFqc4TPw_EG7{TNIBCG)e|=52vaY2Natwmv%F?hz?e*0^B3aJ@I#+c$iUn%la&CrR@)~Wy zWz#sj{<33%%BTHc^&L(u37|FPyl@eE5rGLo!cSsL-B{x-)3=m{&Co8qoL_G*xGVy^ z;Ig)$dF@td-9$VDz&4d8h@$ zK_4`8Pvz@a&0`BFM{}hb#!am6Yph?tE##0c0cba2 zRXqwGNr?$Af;`4A`%(I+KGqu?vtl2X0`Rk4A8Hy3=6QyD0y6cLPzWE3M2NvsQy=RE z0^)Ou^gbfhlq?dHtSMRMcNzSy1%6jDTy#~J%p*UZxW5p#>+94THy}Z%Y>l?jdUpo~ z_j`WkNFqSZl|rE2;FuQpvcguKJ;`K`hM!YItej(6b?IUe@T!)lsd z@Fx@1^eo(gNLB`B_XsG87L&TS)pIvwUy9FJW`eiO`a&7Zm{kU9VIGTJNkFyJp;r^!9kycA_&_F+p#)z^h7CYN+jHG3c;(t zZjnt_!Oev z10ase%xx_#C*PWqY51iS#Gc*M#P-T~K63j3mIZdek%bzO*;$*pE%w>1o>b|hm_IcQ zOPO>GO5bR0gR=2&>f>`;agJPS#GF>9Fdl~rx?VkRJ1e_d&&x217m6eRn!=EPR8Lk2 zN(&q5;SDRAu{fI`7U@E2i|r`2)3CzHygg}~064aB{%Fp<^&P*RqIxmA?RR1W2$R=#iZv z4vGhRXE@3!Fm@0KhA^drUz~k!h#TTQjC2JCdDv;P9;ILqP_|80VTO>ILnSZ-vv(9B zum!D0S$67@c!0)nbOYiFN2zI>#t^Im8|-!w?)KDH`vICfgsYXlLBdaxLaQ@@RmB2KY9VR?Z;mKwY1B;Xl z|Au%)tsIEZlZ2)xaE7BTI5x;E*}U~2>B2gZ`|wgUC2d2ShDEW!yfHauX}#*rucO-u z2dHZ`?WP`xF^ZaBILf@9Ag_En*~%I&a7SjkP|kv^KoALDflb<>4<<|P{jc}Iw>$Jf z2_~$&k%A;ACpr3p7`Swd}l2y?#_UZn;@lx~n-hJh7E%BYJ&Q7|c0s)4%r&-fL}mk9~r@JLaa??osK402=ULj}m!S7BSJzFr&2B??%ai5E?}( zVcC~cVz9S`Uzzzy+fjOznFSB=p}>Ki!1ISRH7nswxq#PrK>|Mm*gzXYEtR<^FNk$Y zv?**BAM>k2qT8rQ;m0V3bQ~4!YzS0vFdWE3A?yr#0z+5r)q)U#ja%YWPX^csk0q$a z1D>W(8}kdg!idRe^H|%_1ymc;a66kw?d( zqdrznWJQL173fJuxU$iyn&kyCA2nz1wT{`1W#!$=KXU)|9tnJe_NHMSpwt^{QG(HGfBpnb@MjHMV04F?}s$jbib`ADKBPL@@Is^Cj!oJvL zoQ$6q?DdJ)j-YtB^7?)~ulL(${|0}?=Sl|Ow_!QRfrv7FWU0OmmQLy``1ICLP~lFe z9b;W15WZn~1qoUBFy)CN!%TfB=GBUZf@Ys?h#i933-6dw|HFkQKFwNNG&eCH36#nih6g$sG0lavbqK-pxm6>FlrvWE`Ct|K9W1U8>2RaD4mGrY*^mhFhZKU zZ=6Q5Yx>*ur{(%ayZ%VSi~AAuVl5&yjJWu|2l_uQ)KwOomfNbDZMq}PKK+^X$1eU2 zpP5cb+CjWf2kw}z5$0W?r$Z4vBOWhBS3E%%>PVjrR{8eqmUNg%Z%%jL$wX8%p4IfF zVN@fi_lvb{(CLNGRDD;&C^vnoY#7zdg4E+kfzJC@I9LJo%P)iD*3f^*{QBiy4oBN{ zRbkj6E$W8jZu!`rDpDParng`xWJRJ&6*GLgM%3C5%4BPEyt-r^hOi5D5IwE4RlI9! z8LZxzi|H5!$r_zls^!b_o&-PeX}Qd`g+Iyt-+5F1c~9{CZ3T@oQ?DfL!aMRK%3v8d zg`8`D;rhEnqG2Z({2+ZFu(+VlCzw{$2;;A>j-d`6xPy4?5|YN304ow++aZzAu-x?z z!2Hi(4C@&twLe1wu=$VvSIXZM33ER$Knq^{^T1KfiDu+onqDRgQ%&XJ&_nY6ga) zp@8@Pk}+6^UZ_KD`%_xm_>H!s@nmVm@{ z{&7G3=QuPn5QnG*MJ#GUYw_j-%}aG@!zVN3k%RHD&n_<7IQQJ~<8wiXE?LcC>wPBR(aWt*87V0+J zs;j$!A)R71C1YuPQ{SDlp~~oqoRoZBuXx%?*M# z%AbZ~@qTe{6-m=&z0q-=75(M$0rDJtp0zWxT4mXh?aRKTVN^N>Y;p2ron)d=N3t>s zSiLBd#YLMmabr#4apQ4Dd;%Y zV|^^evrdXOYY;XB->Si_@_d8#Ax%$w!%CD_Sit$Ow0)otFVksgJgqHIfyWRs%A-Wz ziAoVXwriaVmpgGn5Ofk9Jfx1>=`fpMA>&Hp$6+?VDxKD<=ozIw+CpOc;aaDn_iWcx zg(@DQyR)QL3LoMueV@nBde%hKC=FZfp4C@8LkMpuQmB~AO>rO(h`Q|ADp6;%?w=(~ zTaim+H0UmSHmvhVTmfv5Ypj=wawq$WOrdNGGGBHTQh1;iafTD8D@;9iuHOpYd=QUA z9hLYNI}4a66Lb^zHxK23h7x5@XhR=R!vT#OVdg}bh)D`C5t9^gMX6Dl{3c=s+ez75 zw`tJum!yQ*0oWa4y11|n?^dymY!wU9n}-mt3fEzDBnby*s+bKz7_I*5PasGaH*;E) z(UwX=cwIz&!41ev+^~K`dMaD%m$!lf#N!4ir`U^4wI@)W|F&yvx=eNlZj)CogG~~4 zktjRAHr0*ZJTOGIOC#IVD-5z5w};C%_X?5a9-$zI6u}?HtR5n~FVx!y2FVVE%07&- z4^(nTNT_;;dZ&7y`bFUb;p}FLZKv3z2ZNo~ZRFxtH#{P76B8@&I)iX$5N+`6}%w{im-Tb70lr-$-jF%E@cqRs>4xv4112tw_s{24ZrQ zR@uLi)+MCX@!Gv!COf%9{%@6y+O1=Xlpa|K`giI|xYe<)lpYzJB76cGIzb!B`r@XO z&#MslP7sluCU>lrOy)hx{XVbY&#~fj|2+Oa%fO%8YWQ>a-TYZ~l0Uzj&!3}@^XFg0 z(IBsuzn`h*&naSjrT82zKKtPr2IvII6f&hO7&saVIlxZv>nsbGb&++IsX_Ph{x>9T z(Zon*+&psGk_R4)e89Y9nJE$nt0Tw7M8;^f6Yw)JX57RWZR7*%BOiM3!N{?r?;1UJ zbWG$BS^OQh4gYuJQrkt|YFxc?-FlP`D>hs*l=h}SIgHNmznj0^7ZaQefKK0b5y+$W!Y_W2ie_2(NJFI@c6_0`wkT>9&OeCuxd&U5+u zAAa=y?Wdocf4OqC<=XXMTmOE8&g3RMuyVEO)-GW*z7l+>O{9w;NNzl=xZ7VM7~6aP zKCW~O_kZ&{F~wCXm9pb_L9n8;Y-Hn)hYxX?#1(C zyyxOsgXc4N9>? zw^ z&BA{Y?iAc9zGT4w6zS!SkKW}hJ%Pndx_-Gbui(~>QE zgr04gojBc+jt}XmPka+tSxvL+(839XkC9*X=#`dWVfz;~IA3gmHLSwrlvsJ;o8=-Q|ipw$V89lPtri z=av{pzd6A$rf`Na`l&vKn1>$nj$M7-FfKLCJ3gb)aObcn?}V|(40nZg@y6bA-WB^F zKYF#l9&t^qKI@&-@SH2|^&gCr-?h4?JbuPF_1Onp@hksgOeiigB+lMqOj>lmA$d%` zQJ0)#NKwx-rVbfuNNq8B)0Clxw7MMc^lzFBGY-XiXMPy$(r@kOo%PDMuGwo_z3H23 zU32d5Ys^^ovMV$GS7X*phbuesf-z_0O4nT3apSz6n+)?@JB@e$vcfRG!e+eZvvk9P z7oYboJTTU9udu;;UwMSVu;fAS{e{u42hw!j2k-6fS~Pr^ck$$AS8n%Y<3j^JcRlpe z?Z&*nA95`@r!p?R@F&;9Z+vH5R{geN`4gv&EA~EPSh?yoqw%pn7*@@H-@7_@p<&I$ zSG=Z_sRnbu&EEVm_qg(}8@=n)lU?i1XL#5DILP(L;ql%-d@OfacFi#sy!MT&&^FFk zwD~=k^}(LT4QszPJeqjbXq$V|P&~NaSaR21!(*L)@owy0YS`%c!drTEsX_SQ9dFqe zGY$5apY?94$a6WMk81Od>8{5gzR&Blj&wbdWidW!=<0fE{Jq94Q@yV8hX)pFQ=aVcYf~@AiG=hUYAoyw8`eHSAbW?cKTRDc7Il z_IY>BF}rs6FZ1q+nd{mc{DSd?Zd%t1e-(`T{&tJ&#rGaIzH~m;@bVtL@s-2<46l}q zF~0UptKs#<-HiL!Uo^ZiYn1mdcUKtR9If`grTw$vK$pLH4-P)&I{5u3-a|nxo-@8%wa9hk>9>qW|D57FmjATz_@j5YDst8tD<9SwswT`go|rMraI#mN z@x7={hWC8)yftASL(P{Hy{EqW&`^84zxVx5np__|cf))7%@1537P`D2J@u;V^N_K=alGODew(-9 zNH0U9bFufrvn_^;##HZ@B@r%H`f%@8i>|o7j_&OJCb`aaN&UU|uR{*I{(3FU_^ooA z>)X1^M)##cSJR=7jNg6utiiK&zwz>`1%~g}J!$;Gai8JG`(N{VmnRthmf-aMq`%GZ z^R27B&7*=1zsR$^S9;y*y7JWo@6{^`S4(9d@3qhV>bkz;y7$)uHLljO-p0R|zv#NL zbL9+=sVlb*~P5?tzY#J-O_I5a7y;uUCJ>VNLGhOs}SIp=GkL#tx$`8|*B{qupb?a$_3 xeEy?zr<51=*3nJ_zpU}`l2c|qhV%)*i@=9pjGLancNdA5KlcB3{Fg)Ee*s+4;i~`u literal 0 HcmV?d00001 diff --git a/bin/create_rs.bat b/bin/create_rs.bat new file mode 100644 index 0000000..98959b3 --- /dev/null +++ b/bin/create_rs.bat @@ -0,0 +1,5 @@ +set iname=BalzamUMPLeonardTMS320F28335 +set oname=BalzamUMPLeonardTMS320F28335 + +hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +hex2bin %oname%.hex %oname%.bin diff --git a/bin/hex2000.exe b/bin/hex2000.exe new file mode 100644 index 0000000000000000000000000000000000000000..7072690af6cbef7f2ac602d523378f4920d6fd89 GIT binary patch literal 770048 zcmeFaeS8yD+BZIFrfn#J1PBnNO2nwuR;;$JV2TDPZAFB%r7a4ys4N>RtF=r36`?qd z5{9mgp})qU)}#i*9{`ltRl(p@_OxaTVXz=?1lmLh*$>-|L*2WRkY1d*9FV z`{$R>=VY!q@8>#i*ZH37oVn_n^@3Rt1Q8}06@+Fy>E~ttC;#h#^U$#`3>7vH+IvQ` zX~y0&X8Uhg;;O5^`DgXl{@iu_wKv^#v*fz&r>^?IO|Bbmauv=hcm4e4g+CoXWJrcv zi~8cP|Iu>Ge>LB$n=gL#(Y^KT{rP*(!t=Ucy>f3Ip3!xGzqgbp3-kV*6h3P zJq_;b-3|#Cm1=95QOUn zgSLY>geP%>=oHQ;P>f&n6uj2h3-OV8B)=4ZJ!22D6dG>K5VDBKwF>Kp5YhiH_q}u> zvwtUM>-}<2VjUr$S*C#ljF*18T!QoQy;`}bth}hPKrTU8Fus1_wbHdH>b)o|mHj?E z4-gOHKQBr>o_iCvKZZmbGKi^yun14X5B|dA>zCAD4?9*?lvx;xmuChWd@=6A>;M1z z|AGVEw|1ln9r0he(xUh*l~r5o-Y*uEFP=|Brt%IRd0aX}`C_XdcF$8Q&pQAc+a^=q zuEubU?Y@@kwJmd76~Vo#z-zlVoM0P|no(8Caiv(4mpe=WZ>7>xYf|>9J8u+)hDEij z8dkWif|R8!6Xlf-lQi7#{-{`}HCL*~dd-5o-I{lldH*eWpIO^bU9(LTl*u{4aA1sb zMZPlG4r-Wkg*CWKO6``%nuTTuB4|y>figLl`=5~HzkC4yg>Flw^0_j@ZSj@*KWv{a zAj5xuLlBhNZhL#$LL?BX%v9Q{w^k5Xm&7KYBEXK7_stxGws)^AM{ zlpcAz7?RwUys)PyROog{qpA?)YwrjGk4`Dh3>6_pBx$XwUKnD7guLC(%P~OwwK>Y? z>Ig(nkr%qfV7R@|&4wSzS*h$)DI3*@Q8dIyWy%XDrBGR=pcbkS+Z2`~2?f-0G|Ls5 z=~AlPp-Q(>oE0j{s-a?w#@5r(p(OAte<$PD-T&bHf};beI*DVm-6*E3J*|;AI1`a( zQEbk{*g85+R^BtW{BM@G?4MKvl${?_-U0GgRhxzSzVqe&>U$j3_lIv&YWMY@+5mM= z4H@^44j`0 zZxX*Kx|8Q;!1|#6`97w%zT+|LpM@;`FXQnWN57M_f|I6KKX7`lby0c5f5po41JmOZ z4LYtBDO;W?j?Fpp;jD6Hp1Y)~TshuU==S+gGc%fIxP7JQ;WNtc=u~UWW}z``Ya9jH zjhusFDOD-4MpE*2RVotRkK(~) zw}Ub;a>XbxQjMg(OpH|0%9VXlpVKcR5NBu!XQ)f*Qs3LhSn9YBKEcA=0%GkvcRtuU z0nBs2ZZX1vtq;Hlv32XWjIGRtvGpB9q0|%x(MF!7e2qeKWe!iP?XJh^wU}hJ(}^i1 zb_i){Ayi2ulh^tX)OzPgvjFME9@*E?&TF6|;wK591SJY^k)2|>lo`0Ibkhv12 zM?HfQM>vEnpos>}Vh&=Phx{*qmjcQ^u|GO;qn7{ZH!T0mh2{TrieiR)VNLb?c%?5e z&Y!XRUXW1V^WybgSE8gLzjj4MeX|OdKQSHq=a^59y{_yz^V8^X)({l0;|10hzR=r( zXPYg!7gowNQ7LhFc1z+#2P5Z9^f{!_njq{`KmCLY!eJIR))>}yQ5%6z@uF~KP|W($ zE?eXI6k`#O@kOf9z(t5U9^-@k$GE1@Jp%m7ETj-3T0thVg%kp#W3g*qoG~v>r5Lg` zY88@1B!>zgt7V6=mb*u=T6VBncCcEm$q63h?RSnHl%f5;1kXxWB=tq|S9?0IbQiDm z9CdsLt8ypmjD(j=WZ5NA)z5PmARAsZu)@%6cL}QB1vgp%qxzR?)h~R_s-L;A>K}{f zun1WpNW~BVR=W`SUUZD*AUv&0ZOUHt=OBG>yLcq4s28aUC(ennC4F2gu|=|=rK-b@ zM5Dw7uY-+|Ti}&NZfpD-NO-6lO9`y)Qhx^G(pFpJf036}ULkM^k}88`fr!y?uUbrG zDj2j+EzoWEsTXqF!L_NdFT_iv8pIe7w&%jsJ?+SV55XYB6K9 zZvz8NfmC|1!q^%iT?&l{1JX&x``3pV#{1fNyqamXg-qtC#k<+aI5`_ z>hx>Xd0}#%eF#SElq$gl^XbIH`YVz3VpPKjA>c(hU;doTv%<$&(Wy?epgc3&ixUPCKNd^yEDGfn%3?^` zZ%P-)w>$0i=LSDfrixWfw~I?1$g1*6OLvOWbL0=oZuvd)kqy;8^~*3@>C}X7bhJ-( z+K{id!fa8PKX;oYX~9G>(}H#4O^&K1sjB<0kZ_6|SkpPOcX--uQ+k8ZrPGv|PWiaK zys28O7nKo_6y;UCf*cHTPj3pU8m4AC)Su(Ww1UQ}D;^|#xZpxh4bfu}ZecHDux}cu73EA3DOWg`fBpdOD zrm1q+gb00Y)4oknGvFSYW`T$1k6d1%Rhh3Ufx}9LMY#&#z*09Ar9M?zDn`t5o2ax9 zzrO~*cQSsH*Q;1@>xU~d#Zq-CE!$aO#3+AbZz>WY@PzE4YG-IBF=Sg!n`jY~tG?71 z({q)Nh&70bC1q7A#WM8*zC5oL+KX5fwih|5G_^t-Fh}*-R))jKx4Nk&Cfi$^U^+TV zl~PfeA~q}^DbUK?9>8+`l8JTJC8>(n5)qaCia>7C;c8{F=-H3K&Mr9>n`gSUei+0) zJKA!g+ZwXhT#fu-NEBfyCRirQGnmI9`8g;p$HZk0WUMmP;iC{; z@E81K>5a_hodEBefvX zoyzSF^Ks9KrKiD~;-N{VG`pv=97T8?ZL_ADx*v5or(W2v{;U^vj8g6>qryhMWrg*# zo_>LHJ1^*GhJwzoK|!mDYZhTX(l@+fNI=1;ea2d+UNAc{PbHgQqXk9Cgm+%Ar5Fp; zs&_CNp&2Mk-55HprA@QlmNI1@P1Ndtp)%kmdWyvAKw4h-Y68`~c6v|@fUY3MF0)`} z8OCF=^H}T@iRX0zu^D%tx`c$H`5VdeAMCiuW8iE&5IC0I?yFSaL6Dk+5E#ri_8H8nQDGhy)k`s?<%OGOTHDinkQ9-R$&U8P zY;^OXbvf5ero6a(>L0#AUVt|uKe5G>opMIa)2Rx=QQ(FqX;7s)2y1=}vwFrM)rs(< zY^zEfHEGO58P>10Q2uwZ{G&0dnN$KjFt~*L@9dL*`EX(FaQ{N&7~O%^8ZMer@yw)( zgydos)K`(?CeiKFWDOs=sGp+S`+I)E#1dC20=VZP67@KyNv%c(;1{*wOy%<`aLuaD z2X2`cu8qd{=9Am48r#6YDsavP&Z%`@Gp1RoJc(S3RX^daVxqmX2D;g z_dI`?FBx*NPCUMq)wTOek|r0sy~uJQ?QEcKXrbW7`)uR@l4UP^@T|R#tm$s7cYcXT zXo%9d@H#k%v7&N4;1ka*tF7@-M4&9OU}cWHywQcsVeFmlc9dcM1%SB^iDbIqM;+4( z{()&Ua*BE3h#94mcbF=C;O))3NuUn=2}0vSK`ND3SxxmL_{30&rEN++ zUaX-KtGp_U#F}Nqv}FzeDq5ZIYr5LBc9`74`}v;I%BB*#dW6!Q2fiYct0`RM=#|XM(cxm2N#i*Ail8in*mf|4W85+b|L;van2;+s$Efn8qxZ+VKZW;xk1s zCllgTYjz7V*_0DR0zyS;86+&1dK6-{yxoopb(NWSfE{RWDJckL$=-u(n|GOam6rR| zP9}Ye5S~$sv4ZU+AIH&J2Km%6&+^fZBsHvG=g)1jHk(m7Hi0{r6q{Rp73J!gZvZ1NvMBqrU!@_d6h5=RW;wfpa)uUW zg6mQXb0jH7J!3YdZJj@tCTJ@JneVcDE2`AD{$Ua-s>(w}7PV#u3rP((rwqxItDlrp z7^fbF#ur|-ReGgzexg#Xp7teK$$SQf5ShI!ySJ(oOnZk(jF1k32c$g8{Z3Zxp5sf- zYI3~b*)N?A8{$_}0pVOim9I>_4Z=OLZEi;nF=!<%fG9sR#o#U)aIH;Mrg*lf8a>;V zWYh{YPZXkI0T*c!n-k}|%BEYaJOas18A2?q0eE`r(`&F>M$!?*f0C%X(H(fy3S^(e z={GL#^pLzmokQCrln8oumFwuj;k&B3d?zr-9xEfr99C&~0CG+5-AX&3+K*hc!9_^fTR%eg7yv%n-bm_J27;lr z<@$j@X~OokccKiZ={f;*Ze+qwnhqrgX z$X{onJCNrz{uef6LmIgzeW3NH3VEZ*`J6o;6EiPHw7f7P z8&Lnk*+>5(t)@CJOllX$_SeXVOx4zuxvd=}FDp|3v}hU}J$&>a4UTh^9zz|3VZ&Bx zc?W{f;kbWWb;z`K8?8Z=6cpQWY(L_(rsN&KG8You{oBYnd9+1&udphUtX5@xxp&aAs;E1- zInOIJJG+Yo_-?jqPmA{a78OtSJ=#;%o^NZ<{n~S<_6%#!&HOnJaW8~f3?sp;fN6wT z2Xi0HgD@Lls69fSAN;qz^1OwnnX5!yCCZDN^&}<>LK2xp~v$q9z z1yY}ief0UV~d~mPke4nxliyNB#<__8?n{8)$tEf2$8T0 zrsU$HR3xW=5T-`|rpKoVelPy8nKWfdsz5uJp=k~c&~?!W6)l^Mstz7iR82gV+f23Y zO7+My6fY11Nz87GjKD$(MZo$vw!Yk^bTv&iF+BZ&G@)GSt*la4l7NTpNaYHLG7N3K zstN_5*#3anXlEHqufW3$?7hl?9k0vLJ+l;3S=8r6LKmWIHG_9Rxsq8Am;P!5{+w{i z3(rreD5_}fhxTZpF`%8;BCNj6LfCv|;9}(>x$Rr|MCP*WsQcO6pLm6K(q{#Cy<9|`=h(tz0U0hV(;&yzw`-obV%zHsF6z|flN_7sW5LAd4Cm$)xN z1W56XyZhtrPxa?MC+3bp_HFoheiVhrAj`v-#N2DDFA7sSdVQhhS09I8hSTywNoO+~ zmo$Ps8v45Kn>I>v*swLG&OiX#u!-^Ew^HHY7(C_hn4$;LfDzZ^4HP8Tf7kwu&0cipiCDk z^NwN#bpfPU#MMkT$}CAag<`NH2Bod#kf^LD`{04526_hGslf=7ygH%$V1gdf5G@w+ zj>^ZQEJ7)#nJgGysEj7fk!Tsu*ipqABq#W65*ZbE2h%&>@(hghtAk3gF;J!cdW49j z&?Xbjoq&M?r}|wJuE2)I9(4s={5ywnZ#Nsf>HVV=xIw@S*+`kpmzIh01e14CDwR4* z=py_ztQ;vob)!;L>cvoN`Y%zLzBgj&k~v1^B6(EaQURXMl|PxwU| zi?NMvD36$!IPI|~4mBTi=)(fCZ&I!%ncLGv0$rO0n-=QdFsNci#%vj9HaLl0vgcW9 zC5UjXcU9{}Bz4Ds$Ue3^NC7z|;AQH@=b;#FMXR8_LTbw?$VQK0#G9vOgR3T=xJ<<6 zJBHwvL(V}(EBdVdH9VHZdjNjd!t2qlQ^WEh@0y|-KIz8uLKNkfM1+YY4vBifT5qj< zXu%>#4{3`gxr9JkGnJ-w(Ijklq&3sj-I}*+(WC`}F50FkEye=U{0VvcbLbU7Qh=f{ z&Fh4A4TI=159?I`9zZ@|VPcD{sBd{_xs_{>$j4IxmwR>@YN>jURtXKuSEbhHvUo6s zG=?QNi=sA-ZHQy<1d%YXMm}x|SV+P02$U0;O=5ZZ);Kaq3-VR#Qw9G9>Q}wBLREzt z{bj14oGx#-Lq05b0CkI&JAM8~;DIS(l*7y0+s+SQ5wq;fF)Z_SRLL8^A zEvXH6i{th%9j!H(bfolVQof0}u<1Opno_B(4gXsl_v#wVKFv&pCbgNw`*e@N0A}JRggyqEL4!nBl zH4N1d+jFlT>pF9r?YUiOrJkL01NnXY>@V}XA{evQV*pdPJV9d?st*Z~1! zSzO_mGke`^c%_*+VTF$M&rkYU|3Jh2c*82Y0Axe71%WPM!W7FZ+KTO1_oGzu< zlJ|*c2egTt(n#94te#IEt)xj)4l;6eZI=4bJ;WZiAc5D#ZnukA}Xa2%{zd+CODk+2nSLU#-PSYA@`s!YS;TItbNYFlTZrk}UK z1D!t!SXqF-nY!7&t-)Jo9@|eTF=%T z^1}dHlJ$KT9o$Mwsam^wR})r%S6OI+>rtjSLTO+;nhC0AIBL4Ip{pn%Fv0lS!C7H3b?(xuJUCkpsw6gGrvU$Hl2(fec7c zngz*K8j1PKMCvJlDZl_5ZUd32q%ezN`u^a4ZXq2F4Qo}rOwk2Pj$t03B``Q-(rlzp zLnc0pHB5Q}LlD74=(o><)pD=P7Nos>IhCX?lblLYm#JaWM)D`6s@EKiMjzdP7tEO% z*g^~qp_kUxlSov<&sABqWU(@dLYbp-)U_m)p-9THmVc#Is#}#b!E`ZsZK{f*{^YMs zk5Txgr#0;8+A`-Ic^ismCi4O$F~3J3g*2Dm?4-d;|;7V z=2n`n?QFvZYbW(K`0KNPq42KKxpRlj4SDMn2x2xUDG#)}Fjx{A>BKv7Q z1?3{PjMCMq)`u`M6g#rp;NtYO*{1Z!JEPfC9iFyjq%ieYI0ui~?s^zCQK8)EFn_9R z7yX6;YN}LMI!Z~qsHqEE7N0DY460PC`l?dJHH@r@8b(mlYG(7)!u^d1a=(9wMW~rxpMy1MBm`?M0acsDz4~Ylx@bQ{Ws56bKx*-$*Xrj7nR5B(ko*eKt=tvz zVVAN!w9xGjS@NP#BPoII=xq0FU4!ISM;XMLlD5gvDm)+U15!gFX+)UPM5tFt*%(p0 z_WB{{(K$Z#cfV#ew27b*Y(=ueh6Hj$;Ml`W2PrZn??lePoTm(yTfUZ$pJKcF zGQ36IO^$LedS{01?(ytBxB~Bx{d&GG7P`m43N%6D-8N1WEZ%MAG(qFt$5NReg2%ff zoF<68`&~{GOy2z}rwJ{GcZZL|?Oj-bcO68(%IT+wZs+tmqF>~+ zpXjGS8#DWR?ly|osH}SKVKaGH#OZZJ zU&CoX(KGuCIFWlOArI$sI)~^pIPD-B2VCMQrcm>M)K2I-iu&zQc)%t((H|16a(X|} zZ-X{gX$NnO{iC&oGZ#H)m$*qLb zhrR+`0Gd@r9tc#$0$vr{$<4+6JxH{J(+i2VaN0}swUAgGgLNlNuUv_Xy~ zi1;~(=FdPZ1mP!QE(jM9Wgxmf1#tzUTULmup3%oWEQFuI!?THtj#?ouHgRd~ zicMTvyJ8cU)~?vZMePdy*~GPy(`@3Z=QNwR7IB(QT-R`#OAtiGSA~!nnNljiHD(Un%JYuJkiqWUg0B{oGZP;Y?vmPH(^XOyu!IKt6^GT zOjmh@OJSD4JO%R_%(pP^nO|qA zVIG2c0_Itm7MQ&-Z^C>FV?iEVFbmTj0JOc85R<8K#Vs40DETiT zFqgqhhpB|Q4(2A9+hFd3xfkYZm^9>NILzrV=fT_zvm9nE%xV~xS3?#3M`YhR)|amA z8C!3x`CELw0sVN|2U)$!f?hbben#zxyrceJbWTm}EX#)8O+aNEAqMKk4yejwbxpeR z1a;0)+dAWV@>!%OpTqRzU-<A8R%fCp?t790=?O}9kGaZTtUp`oz#g9+oILp4 z79^yxLa`_}h=AWby94Do$3@P#F~+jyYR8&uNH=7<*f!ZAfT$O{??nL5EtWur@_8jP z_Q_$apNhmaa~!mvQ7X1gfk(i1CAe^-Q(g5zG#a^{;*&OcF4V)^0Neh;cxfY18HSBU zWf;T4%mC0xhZ`rnszlEeF^~!r6GsU@8w=)=5-W#rQIz+No;@1 z)_4`>MOdLxIvIv*VhVwI2ctfT)Y+w6rN)Ye>@1~a_G?&X=a-?X-Nf}(7ER5`-53tg zxe*=%c`o;7@pK2XbRP!Lk3^7a%-1kK=^-MWGL{aGNzo=-ZHBf(w(um0|B-OIlO~?Y z6aU3q#Gf3?=!Wyywt&a3OkFz3hjxx$qZpHa^G<}-oT;)8}a|nfe#lm^I0_U*< zYgW%to4i-|?W;woPIXO^Z)N<%8?8&r(cIk_2i)p%3_ethiGJ&nOSO$NmYULuZD_=y z7A3_%*-$S`vP7gyDq@i?`4Ig8k$Q?nDb>SbzLF_2#bSmyR;eDwri!s7K8pE`B+E)P zBnNe_p>)KQIu}kZ)r2e>*R-z09<(1rN5B5F^FcT9^Qb@Se9$#3STh;md=NiQk5)h< z4iz0I>Z_E?CNA%LqP_;IV^X@3=9yw$a-KqCH#Wti95W|{gV?Y;_f*v?9i zQ>jyQiWtDe8LKkiT?xgJr$57ak3gmYOQ%ia3-hA#ByVWC5S7l}LeENU?99f<8_Jd2 zq5Zc?E(kK`rhN7cyi0K;fF(SRjca)v^rSfKiE%Jz#6i!%yO^~}5!EPr@%-YhLIJW@ z-l^E1tM<{xK{Eu}rj_hM8|+OsmD8arI;1zt!p>%ScJo73ovMxGhhiM6dLWb~7x_#$ zn!aOxqW%>+A2f{6bgn-_BEPy0d8C6gv?Ulmg=vZTA*s~07m>77r>^@4No&}5w5z{_ zv%dFt|C}-sc z_FCx2?^8G3!;Y_xQkLdG=Ae;psOBs14pa}YT_@7jm}qRzJ%o-ybIMA(pg_M`ppyh4 z_3M|AGFF!uxB}2vptF{DBN{rii00z8lf}}Q1+Q;*O%3+Cn2bG)E3%cXAeEOfXjP~T z+^_^~He2vJ@HIiBZQTYNmAaYuGmNV^HBdnx&o{>a_gV!*1#*t`ay0zlUWDs{`LI*GTj?? z2*_I_w?0Srww%9@*1cgbjl3=9)`D(L*Yd)80k`hn8;u_AsvZNa!;Ds@kEiUb?*0{a zKCxe)w0({9NDy$_Cfl)5%Jf5R!EQvRjDW^56qK;e(}Z6V*(<7)sA9&*qe;D7s}%~9 zy)lK!QZ@TA&fw_kRkNvw2kMonZfM=y>~C7)YO2u37Dy&^?o%II_CcSMH9)!GNvIk> z85q=F>_?J9B#*UZ3eLhBIzs%g=Q0Y5O1Exo5;uls`DwyeMvxp#MSzYKlY=KyBbv|D z^F={>^cf=25=CWaOZRa3y~}OS{c^$?&|Jo=6|ZYXJ_X$YgJqh0=<>A<e1PQW(ctZ zwVCLRQtmJoYWd|9E9jbuHk0sql}Me$}nMr3Hn3jAXUk*O_nH~> zg;0n{eYpevYX$YA)oDV7zZoy;43Onb;^jX7Q}j9suYMotytjaow`b0;!kP2$iZIYK z9+y^C;(R&YSVffi)c?N1ESOS>{gvv@1{4%yvp$ah}tsJ_(`Z(RHxJvW5--j#GxbO@7|93?6cbQmaiVRfF&Z_boI^ zN1zKi$kw<5B=&@)WjH4oI5+PoKhLH(p8XPmaP31%nL3L?wV5d56Xq2k$|o#$oLRNi zf`Hj4wE3Jof=_4h_~p+`flq2|e^0$vi^Hc5hKn*}z4l(Jegi>7-tMe!ee^?ScNX2s zPvv-@B$Od4vt0ciw=GpWU~BvP$WOKKW$KHtc=T{$&_6OyL%z^Fm8!p{xJLHyxZdY+ zm9hJq(^9l@jx*tq@QkiR^3Xwo`>}X0Np=mFknA(2jVde7cQyw+`TqkU)BH zM=Fl{Ep*4v`=R+cvvKGZgQb1#*tKbpno!k^2iHI*kuJiNKHj!vf0?=&jayM|TUveU z6Re$EJUaq585oEuuoE&iPUv3Ux)x!u17#PaPi$Luma41Z)3)W+GF(O?@jx}%xJ(T` zJLJPY%8~zcsD=O_bNKD<5Ei$POmh18Hh^(v ze=lDA0{M6d7GNIgbg2JJ=4CsxvA|bP%-1qzN0(d-^&e)w9*+4^W4=lazCL8WmdAV@ ziuuYm_TFlqZn6KvzzP2-8hnNkO zF&y*tD}%3>n6DRNzM5mces1u!nfbae=4(^TSFyp@Q_R;*F<%>FzRocC+Q593#C$yx z^YzX0co`pLzQ%E1evvBB$=a8Q5p89v9KHk>-i34Z+CI*M`qv|v`Wc2?jH8e~0whv| zC+ogmg)jd)7V}P!%?%*s?T+OBlD$pom7@?!*!YL@Xwj8r*dw!Txr+k$)CCNJ5(_4; zuoO&RC5oR#PA#|+^fjQ5MuryTf}RNaj7Z9+v#6J7O>#D6l8v#RV=MluW#n>}b4%XQ z^|mdu^X+A7iWYl37F)sifVgRLB)#B#oL&{D*tUfA5}9IA$|q7+ysX6;Sw;*%oVG2$ zSb;2;s()rPp=iij-$-#%;#rzm)AE_hLk^w+R$_A`!Iz%eCi0B)5oaOt4!7o_?U zN!R8J^!bHNTPTFDc^>|uhl|ckqo!JlqqwLcwB|AXIV{Zyh#lk9Vr08X8XE2XBVqzL zv9PSUgauVkHv}nUK~gCQF2ZF&(xTmT=_e$Gg{9429wY+HQctCT1v#)3L1t?~Mn$_P zQxIg+*PPFTG{=Hu_;X>^eH}(>o{t>v$60`C!SqxDP4jBi&CvB6ss7GP!d_ z%sIpFqzIxI|9KJ)?jz6O!%jX3{oqMhxQ}55A0qiU13qk9(tYZ71{sM3*I?x(z@T;j;~G_*6qf8Cp;yWfYt*r4@{q65Deli-nF)dXCuE z4M8#dy)610dGxfKB5(KUQa|ML!JCu!??^tU`^(48N6qw+&)NOuB)+t#xz0ih;@^|_ zf%l0Im>zw<;+c8j)xxu9CvgJ?B`rXL52B4-8 zyM1Mj;6a9V49D~~6jyAp1ApD7GxsPhp5j7&vtNJLOk0f?5c^+D5iqS=*#*Q_cJ~U! zUqRvnZkNWX8ttC!+A4nmO61ornRa2merX94;AvaWphp+#PW(>*0umE#CukKOyI*=v0)KG-Aueo~mXCw3C43K(?n#)Y-7o!_ z`PjQ-qQ~CA{n97c{nBv2t;2Etu>&`)??LGA+lm4ZAU!u^XMI(Y@WcJ(}+A<~KT1ARr&3UtkP1-sqfOj#I*PXSdRY z;Rf5Y#MxR`0zY$*vRkdKXB=fmT)-n2<0`J}M$%qnrVxGD1^eYjuI^O}A7NZ&E{vIu8}b;hjJ(k;j?7=v~|EyG1U6%GZ+ zX+o(n)}k%B;Yv48%=~>)seew4fhZbF>oj(o3vtvGS#+{)pXlh1G5lQ8c{dZh$XA8U@C&D+6f@%2!I) zc}*j|THI%a`3@Ydqd_#*wH6yeZj5j1`;4dZVYjAYzrtO(`f?FWM=X8_+LVI=ssmf_ zW&C@(wTtan=Hwmpe1jdNBD&QH6y56NX=UFo81#4SLg}|U)!x9_@gT2!mwNlnY>Dom zp%M(BO-@G}5=n`U%xAT{PxU{%E`DDQ9;_&GFlrtU?L$GYh5? zWofyj4uQzVHDBClfw}0Vt9u5XbVget`Q8 z*vH^5#&6<@AW4rh`8`>;@_!nhsnZ%FH5+Im|JU8MMwqz&btc=g()Yh)=u8hIo#~$t zh&F+-v$_=9v@qO<}-c!CWz3+4XzV!OIYy8&76ICWa61*jKeaWIvOU)hH(6OCA`T1824}43} z#p{Ozj%e8msvpvKXZ0hUNA;mqPT)vl#blyl)YYtF-o`_#$>jRk0jCa_S7Cl^`F|{b zllk*M4WAs}kIld72iDKqTK&AH)lY1Fx+h`%g%7&C*>F2u67MGA@Jg|=ZK@SlMO4Ku z#G7i*i+b9z;bNCE=z8S5F__NI$Ndm@T*byyNY1zs7ZP8llu?B>)2nWNKLiBKOcHTJ zQ|)xw9Xw!56@aVlu17K2Rbc3}D{0uuk6-t|FM9}FAHV29s#55p1ntU(tt!fbd(O-V z&n`;1n9Vh&+a0);;4>WD1l$cRKz0`azUV=k(NI(@v+|n=aM>x{fZ=mti;*;okt?=% zqulkf{6UeHF66uOTI6~@^Um)bfT|L0I670TH?GPNeWK7dzwyPHc!3DRRnN34CQhW5c058c=z zW9M_rb=mm`oX>4~5DON`T}WT3xfU1HU|%8eeD2rRF!l^^J~!mSjm}A`KvPg@E=4$> zm?oW#trKYk?Vn_$Hr&uiRsW6skjNM;ouD4MS1rJbDMHH!x2~}244Gw*@yrZe{;byX zd{A>tlF{j$u-4h|VCUVfO0^q&45L8GQlqL;OxwJ27XdD$$cv zmEzm*e7u#s$cP0BF%z)H{Rt@rr9zzp-*Le0LW6Pdh<+`S=3Lys2eA@i9r_%b5!Olg9NRUI_X}bjK{hm4M()t%#ZRHQu$G323Y4FoI2KBc=-_pj`ZMzYfiLGLJ8GK3Sz}5L)vRK z*aXEGH3uUWtQIGrI`lCuw76J%OYFb7dV4c=;22)2cVytD$AFjiBJFvkMn4akbJF)Q z=gFUmOv@AHn|JJ8-q_w5{T`dnc_+n7^cre4bSWT3Tfn9EQ$#@y2REQdb8Qu$!=JV832Z9)ge zBBQg_FDfuPBTLAJoqtIJ#qqJPNuV4dTnq{*GJ)jQ*l-cYQ`!abLbm$m_WJ*#<_8k+ z6Xembeuu0)t{W*7^BM2LyNb=s%eIv@nDE@~VQYok{2u*51F;(abn#FD?m?*ur#($FiXnf#} z^O~-HReEqgQBWZV5{)n&_i#t(8;igQN7b6C4NZV@F~6u3N}b9H=zwzY&ZnNE<&JJG zLsQ&|yFNg*73ZX=Pl4v`a5SPWo0Aa7K0_QIEaxTM1?{Roet}CLcTjcXT)2s@9W>EV zjoK8-hFD!QA9ID0Mx6_qsoLu(n%rWpF^w6(o3>1j|rqy{liS&hcQZ@RG0@>jPiUB z3NU~?AAXF>^YkQn{(h()8;&n9XUOyPOqAz=FWv}FbGGaI!TSF86x=H`!2b3IOm6LI z8!kro|55wfU=DpA6CAVnO8pD4D+4*>;|ero+Ebd%rY)Q{aJ8pxM%(!D8ZdvffB!{6fB9qk_p@34 zD7uq>PaTXC>GRkYwv3|tw!lz~lhS99e8ylD9!YDkRHX$@G=7=r9@-WYd#6qo>tAaO z{YyUF|NejafcyU>0z0v9D=MuKJ49h=F#5dy32mkcz*bcKd~iBpMOFP@{j8{TO@M?i zPFG+`^6v+GjLHB{m$P>BgI83YYSZeZ71dLSVnAg8@GBQoz5lwt#3K zfeL^|jq|9IUH*n`?@?;VITf#oEs=BSsJF{ZoF5@{hdLtA?JA!{y1 ze(E42&w%|3gpMt}_Na~q#(3t!q~kn_1|>$3Y>kfq696YJ7>oz!M3y=ZFMKP#Tk-;C zC}3oHZ`2-1HLv2yOvAcjJ7?qrrCF&y(mw`AO5qZsYAL+8uL z9W-Zfrx^{Jz{;a5lejaIqUlsmSnvR*pne5{FHF199>DpSHbrK{1%+@@mB`ezDO6}v zEOuu?zaW#}%*hJR3Qqb3MtCDZzu=YMu!1M+7fi?L6|LZxgYBI}}N-DU^SmRy4W(9Y#8h6DMD^{Z`Y6V{k(tjjYaBUGzHJ+=UHwy_BV#?=wGBY$y zl0N-`U@u+6Vvi~&7yL|$rc-^27ra+}41|wv=+A)K9JOdgm1bf6m}Lr-5S%p?POEV4 z%Ez`fSxZDCoSXtX!S}xll8y9%|u6e$=wJqf^;SdKnq4k z1->qT`Is;OI?|0sRYst|KTz?Agz#SYk`h*>bsPww$pydIc$qlAd=DO=jf*G41JVb; z1IA!rAv|ChdKB`@@qiKn0CoWo#@Flt0+iDtcuvHM!q1`dqHJ?8fw50Go0X{+OsJ?z zA7-;R@$sUs2_}3iat;pmrRN>&CJwPf4oX(f2+cnUsWwki`Ia2sv>)gs4P3 z#620~#GWek@uvsEL)O8?KSA@h%HU0F59|O4j*;fE`&`)9rpl{=VP&6mDv*f@zUaN{ zQN$|1kB27nMNDhtkdlTED%H#-%mQ5tO-TZ-Q3OaBCoyib;1XzDuv^`V9_OOhfPNSg z7B<4Mt|(Bv1)i4rH<$ej%W?WV$j)VZ$Aph{;h+lSX|O}XvRa+e*hfHb}oQ5 zJO$gwVV;5czP-`pz1aWl_y5=F>wCM5f9P-Ji#R0~%hI^WOvJXaC9blXg

|Nxc3uY|hcf$0|PbS~5rLkAj zXUL#2a2oz1x%$>^tf?Q?%miEGiM20=P?(Igy`8nS58dI5Pc3kV$st#Q``-FvP{89t&h(t7Dm8U=?Ye4Fs`qmkIzmtAeseY{&oG1 z{_tiO_uNO>1KEs)f3<)8kbEs@mX;pIo59Z|;~_FGEm1yiSUHF;UBkWiMKtpjSu3hY z<)E!-5DMT^w?R&03J2En*}zB>vQgpSIx$J%pa?gr$I(>&DGBV|(Dpv5AM6D0%hzN0 za_Bq5__!Z^mO}s7gbWXgnSF=?u-0;X_X*>4>{|_mC=gpdv3We5edYlYv#z9o&!l-{ zK4@DwpD8IoL*c3%fD|KSs08d$dici@SRy1$KwW{pmH@ny-DpHQ3QTO&b7&`BhF;um zgiF9REd>t-9?pp`ei2ou*z<4Owg=0*KY?SMPh#MalXKSLh$ZyaB7|-BhtA=qzYzC79TQ2MLAUOS~Qp5S9%naS)a! z!#D`b9QUccw1JQa!s1h#kQ_fX;HQsW&xL|dl&c7XEyUL@LA6Z-2Af4+zQpq0qG^T< z48m4xkq`(w?w_dw`>ZEEnY}|A4P(jP5g1)-j#z=c5)|tbBlzwl+h1UxGNEtn(y4UX z>GHFY2@rsWF5k@xOb{@k%gk|~I+hBS#?WOSZf3CHt~p*XBe=Z#I$kgWmn+o8uOo(Mr1jpML>nR>TMv)RGust2g;KL#zOZ5s~T)}%_sazFPr{83g0G; zJIC;@Ec9v}-~7+<@y>}5 zAAS_R{XOfci_v(J*Hcd{Pgqa=PJ7kXQwm-U3#eFo_8Z#sK=^Iy|84yCVJ!AA&lyj0 zrNvHiCE&Lw(4hUVft^PD_OnT><^Kr$cJGaBbsRs;br@0nApG``1b!{l^%D~C+t_)o z)c*BhV*F(A?P(moy%fjwF){C>(>*Gtes-pdfwn-~H2BsT8HZy(1e7zR&Z)z<_?{Ht zTcA}8zNG_SG5D70i}VNIp4Z6n$&Xgi(#g5d-ZU5JC9a zFGs@JFFFl{`Imuq)1ZbGgK3RwGYK&5nKEZX5=>j5gLYl&g#_9W_{-a!hE{Se1U$%U z9HwxLvQ+(glIs#SWyXC@W=2OoO-5d}Z*&VCEN1b87s zE4x%bNPjq1a1E{G1z&L~a?D{`!l&H~t%RZp0J4OFbC^~?_g3joDtLgR=~REA7d)6$ z@I-u?*SL;P^V5DBKK&%JiIa|6jT203tnmbx_CoC4pnj5J+82;CD|oN^G)R9(tl%>= zd>UXya3YdHSQL2%4eF?44#}^GZ&=V`CpxkNt_0p)|1(zP_=d%uh$04=Az~Y z6Y#G^x+10K1%))=U-Uh6e!k|uO<0pQdpP*DL3^&(o@=zHrb@9GekGU{FpV(r)H^yf zxQtG|*n)ISmFvs|_h9MnLNoGbj;GmRb4tNKJt&STw&wG_08Hd!(iSB3Og@5h0h}*}@xYu5 zGa2Ul&d(&De@T8%Ixf@ayiBrt^85FtpX~p~rf)X1_wu!XpXgpghtj$FgC1~5-7zLr zShV_^9;hz_PVvtxD8Uc`P4vr7V_1|9HB~4P`J+1dJA1(GFVy{<3O{}?z2OX*YGol@ zxGo@av;3XQ=<)MRcr4I8et%WSc4n+w#FV2X%M{%!#SDx}nAI+UUV zVMyx{=Gj5FSbUc&UFdh}vE0pLX*}3W;{Ec}W|Hm=0e{8=&ezLj=&*_F1P?V7e1zOu@?B0tkq#7~wH9wdFb zXi}~qJ#bb7(vjBEr*a$UQ@PbmGX|yLOS$VG+6=4><{p?|!zAYaG@gI`ybgW3h_+`? zhW#i*a(0bin<2Z!l-(<2H7#(Z25@QF4Gdjt$SOz1Y<~~CSD{bJy}o61>Zb?kAh|<* zSq5nkoSOlM7h$%+tkh_F()%tL!JPO@em5mLo0Hv>oXshQx+W6(WbqHE_F%Cr_`5K= z(~{VVNj6=pV62)2e=m3NSxIq2K4hkQq4fDfZ6&pCFe(Y3({MS~0u%7Lat&Ym&+xfP zKPcakk^Sep9~`j}eFyn#uH(-bmlE64_uxe}--j3Bpm;xcQICcf5%W1DL`r+O+ujyj zk4B>1l&|z^V3NA?ZA_j3Y6xwafN$PHRfD4Z#?d$a%4Ivw=A!MU9gv>@>Pp+)l>pmIMWz^5~fdK>HS395O_!T_~zxrxJ0)EAu zfnU)x5x+wIAkW(xgVYlFnX5aX40Ss$6q6+R_#o+K^nB@BDE&#*XvWfXI)_zE3W0ef zIOpP%hSIt6aSx0f+!q$P` z4?5v06jxCq;&ewg*oci8tOMiM2c6^$R;N1mYPJrHBTly=ih&WQnEp#5KfXu*MPtm# z^k32j(tnxH^N#V%2m@jT4vvV`+6wSLA|rp1y| zfdQcJVVJY#Fs{Y5SPIW$*&FCE%tzzUb$;|=7|iMe@|&F>98f4i2>jwC z$K87AxSK1X(YlfH&Md||YP3!U*Dc1OK|1WV!d-w$U`$3f2&lrPK&0*Ucx4j%ckn12 zP$2RN*sTOY@eJ*C?NL4aa98q4BV7UKKftr;zIB6s(C%wFyshEcFXGjJXB+U386_n` zyBFA%@v|n);JOj;Sk(Mm<16lWS(osxjP$;YAr?3L9gr>n5`+EJX0lOcNy;g{vS_&- z%PXa=<&dbXC;Q-mrUrTj-l>_Jcym1$8M%JWf-95sbI4)<{Ty=Q`Z+`;>gOz<1yLOO zIce(#($6`pKtE?rDfjj+Uig|$uMXS?j&rf>!U$XNX|M+CUJgH)UqBB+>mq1^gh4Sc z8u=LsHt8HknM;C4I!9P$VU!2$Lios3x|273>mx*8g0UX-0;03&+THZ6B(O%tVzvQY zNAw8NDi=wsyxX+;y)dkBZ(N_NPRg!?bG=V9%6NPB8HRwm+bYo-v-9L?n8SpYKw1|7me zi%i@c1x0#nZ&%ZvB3(3J#lBaC24uzkF|<+7?~m~<58*@=J}re)I{|j0>ISTQVkfE) z3+8J?7+`B{4OY_D8QQuV!|O08V}Oy%9Vxc^xPCs?TGh#mtt_p)nfys?i^reMm%Hq0 zd@X)$U5xmL>hYTpKW6oQA}`b;&y7c(5ILgU$mp8;tuh_?ZOHqw8;d8M1JFxp)vCETh2!o>j?X6 z2LYJEMeATY{sL#Tn_l9ftwOtLL!4Z%lZZ1x;--5QF$U!w%?rPPxayQybCgq>8hRj? z&}c;WP&SFrnZwF`!k4f!<1+bZ;H~(HdmSGv*YUwgVMMd65KzR%HU>pB;L#5_$Z%sm zdU74gW*S*r`Mo{O*cxG)Z0m~LGdms?V#(-oj;ub~QSQ!z2# zKx(_Hc?ykScBaz^xjO`#d05XPS?>eY@vC*JwB~faq!| zT74(npV12mE#dx*kJA$G&-j@o;r@&{c$L5J{)}FOylznl6rwem4yueTw}nl*^Pfx=qkfUg|hBLok3ALpFXF8(T2@ew#H73 z>9T5;sxVX8fJu3Hy8jPp?*iX+bw2(lP1*(sBw&E3RqG5}wN)$aHZXM-DFx(W($W+M zw0`$h*H!0`CIuXnY6@%mSvGff(`~w|-+gzVb9k9+X=y>^B5sPJ(>Zkqiwbj=3QB+P z=X^d%(-tq^{~umWKKY#cInQ~X=RD`RoF}zu-NOPZMI-Jv*aT2_QtH-N)Xw|pe9;UH zyNxT{THjErxr=Ikk#6T#WvOZN_1m(NPS%=c@N3`Ejos#4_uTKL^3>i z=<98~Hslh*dnL>H<9sjlN5-xGk%n!Mu4bow{rH4E_BzkyV z{nOJuIy2QHUBDW?m1`Kb-U^QCw@EKT>KUEn?Vm1+k&uW++E0;)n{LwRk@b&nx2q#x z!ceUtlp!m=CRw1`i5jIe>j-fn1DaqzDD08&Uo4PhLX4lmUOX zNLe7%eTT#%vjYBL7imSlOhx>;9LW!612a3tK-~H=f23!GodrJ~o8I7Dj$g`0Udx8T zJHRJLaEuCw`k>C$1SUQ>6f4rqd~C)&N8F2r4>VIk4XT!+ab5KLx~N-t0Q4wACjo?RBfHk*CKm@dKU00`$q2!4K+R{CqtG`LG#7m>T7A7ZA-&y5Evi&;12Y zye#oTxTJi;HSU6Vzdd$P&hx4HH0z>MKAEk&nFn=*o0l@^z166AJs1?(KsB7_R-@?@AHR{f_UdyO{lPIpct9iP370zh;j;TEEKZ zUV*Pa<~K7mik_g<+>{LcS!U%yY22KXx0sVsT`?W;8+)GUmuZnIUGZ1#?aPN^Pi4$Y z3ZOIU6MkGHom16!y|L%|u{Hi}OpO4n^LoS19R9WA$n}ZIBNmrNr9IF63+#rs>qXau zM?Lq4vLy13JUH}2Vyyj?9Cs$mN6uFNr*ZbX)vZ6@VN1v)Ic1X|gPyESK02ngdl@)x zlHQWZlXot$9~zhwz!L=F9<}XUXMeUa$5ps3*xPivF~=JUM;eN$RK0dc06zCs0eGJ< z(;EL-`^?zh?34QZ#$KxxWDc?a)Fqu4<5I#rW@&yK3=tg{QcEYAsG!B4f)e-^CYfJu z`HDJQuMeC|aoXmJpzrVh(^!4~ipD7o*S?}7AB*#xe2>(^O_5a7i^8K#m0U%517|>D zu8UStNK({N1f>l}KB4V_Gvae!JvkkpoBnoG1_Ca(9k6Y$41gsu5@_)zTKtKYyhKZW zqQxg;xy`M|!gOmlexNCI@AC=6D5Xy(TAYa%(ZnaW+gYE0!HeWkTgnST3fi=O{D*39 zirHSe;(BW*q~h^*z=|-RENT(6shgGGM!#z=mg;Ht`+&` z*CE1Ecz3uaq<%^|MG#qytoLmbvi>tZwHkS{604GK?~0^v78CDIM35Re35MtJ3#>@>=`c0MgOm_DF5w25;g9f8vI`#0~k0 z8}ydCc$~S2Xkc?Muq$zcGjW3}af4eaKvNe(2)GDn5?GRpF2w$Vd>-#Ql%;)?<-Pe+ z<564zz4?=lMS=R(f4o~~Hqp8>dll|O+ZP3h!#>J@O%H|88W8)>7?pm&$v;pT$RZdX z3~(eb3?S@P|B`d+MZCwI7GeYOJ!b3^Sa0@=M?1;a+YI6yop-xZ(VJbf#`VG z{D9Gi^btwdX9LHq$BYFRSJ5DVdpQwYq)!C2njd_WSzD83JcBOoIJbR;V2-Q1&6daM zmV@1EiC`+ey?3$j5+$c!w&YU31V?>=#~Q+psvoWpdE3=u$PAC&k{9oBab1z%ExTxH z!vbU_RrWnv~g;~0!jGyKPAC!B@jidHl(7bYxpr*oSTPO41lvw4pc0L zw7_}eLTRzlUR|r^nyo@Ml;3RdEVIGy>3Z+ulLlLt2JH2#RxrBFuWdZbY5w+egb6K(L2%vMrBX>{^n^K_Qf zn%F*>SkVw&!zR@Wm$6!MpVcsH3_S{$h(uXz&pr63X@MFfDt(Dc{N?099H15c zP%l8Fz9gtkFmvy)WtDZ#Q2nH3+~I~z0i|EUDbNHgRcu^+okUF&Irtv+uv8WCC7qWB zE4|GVIqMY;5|#~&!Ipq_b!%c^V&R%((WSvd%^w+oLJQxvBmdN|h#qIOxF~;|`2)D_nB0|5G@?$Zfb+ z82EqIU{V@VKV}&H0i{Gf(v= z4TUbpf%xn8*y}Kd@Iv)iBcEx`%82z6`UuTnhkM$7LT&oK%qPwVBTS~(v*ox9vD@R> zEJsx~(w26ACt{~q?TeE?iD&c_xt=+4I6X?7fA(h)IILt%0QkT z`E5C1D@Goj*04_J8K27I;%)3znFCO9(>3WLIG)x1eMSc6IzSOqYX^+!#$Y7?r zJTCItnRtD-hPvG z-7Vai*jxOPplTN?lvDdbY9(kivBH3^)E~M7d2b@e5!xfO8>t7@AsQQ z*Z-w|i|F6=!yU{@b&!Yabq`0NJF(Y0I#X|ySho7%F>@xbutOZyE;V~PKh@Jur9pA6 zJIM5%8B#>sPos@=gE{F2 z)1+i946$L2q0D{g9kX9sXNmKQ(ff5ozLER2nflfM^yY^B?0an3W6#KjoqTZQh7D_u zMv(u<%vs7eXX$inmiDn9*^M9;r?E|M(9}_>-rTtEky};InAo`u%nP8(&U(G^7VEIY zC)+exdU`PCU3;BT1HT=u!vPG3^Bqkv#=F%lKtjr}9e1mTbQ$T@>5{1nTZ|gPeG|-H zB}>JL_JEuLk+*ljD#Il2&`h#@m2_8JI#{W~NSAcJ`M)L;{fpuB3=kt8tgr^+6=klk zmTS|Y&94cDiI!>@9dtG4HYmtR|1=n!Jjd>&Z#(qV7JRh%oQB(ZukL(W=Jt<#g2HIO zq_bo{%nYY9P@Q8(aFKWIg`y%;BE*I&)Gs)kbAxhR-=X3}c(+=|n>eZn`-jdua^7)$ z^se?9Pu0Ut5hHfg{VtQ~V%GY(_lx+tUdyf3^%%RO6E!~p@N^x@jSV`s$(i%lOlBHL z|LZ@gU6BUT7GH2MO;rY&*db$k>pwR^+jm7x{-kwhYrCgo2Xdy?e{AYfxv|&VIYZmi zmAc1PIu`O_ZnFvp?JYj&jIebMI7z)!PWTr#IInBtoz9RtNo}XX)Q2>tz8frQZtK%c zfSqCjYzj2;1T;)sA-wU;ACSFFyJKg%eKl3pDvr}z-OoOIrSud0IjXA`e5d(x-CmLmIj8g>(&8J-|mt!waIlR)13EV z%8gp@dcEN0VcNP+>@$u^K-q=E@s|s?RdY`VAF|kC7xT6^X(-*>pFwrsZzkPY{W&E& zlM>H4w_OWGyXhmIUFmv0I!Ltba4xV;yK}u7H)Y@+c?8QiXV39A zITCZc;2r0o6EvEUhjj4;BB!g6`r%?uqs+~p=%wflkuN^m7W3SbKY?)Po%SEgcY-h_ z!%_~p-ya-m${{r|$Js6Zhq(D9W`ce<#5>*yYCX2^ye^6vCe^?1v2#gt|5alwY29-TOuTv zuP!7-AukVNbC(GD+86jo;#%oXpIsMQC?1}2b#$xHh=^{jmlaT;q#jTIKF7L0 zF|#j~>|yo$RB}uSagtRAdbm|Zr*G{g=uLd{Rdj=XA`7(j4*hw%{%qHut@?AF{=89t ziY6Cvr9MNc2L5j1FUsF7{I&A8g}-}xhzL)=1H%o$@3$+Gh62eK_}VHF(7U&;mQQ17 zKW`53C;#krJN{I0f3|rGD)6S{;0T23_%!R^8Ub&l4^)=h zqbRs}4Oduw+DeXi&D$#j*TK3mV`;Iez6DK6B?VGRrDjt6`tp-~l~}Ti<(5F#V~-`n z{zN!G8O}?D1Ialqus||gkO&ti=eQGde93T8B3x?KGAC6XZ}iO>7aLYmI6w8K*nE@T zfP!BPSL^zzw%8=WkL(BiD>`6iG3>4DrrK~`M&JT_x8ZHQg`9rl3YWZ&xoinLBBuUm>l%RCV*ny4;hn4!-V!GfvJt87VehgHwZ$lP5?#Ngu%1ie=}afqJ4s~b?*<0MO7 z;tIFA^8=FXN0BG*(aPvRG8!bUe@%_?=lyLz=d+5$hJt$_pFjGWnt zkjwaTKr~SW%B|>>xAuIK7h@2F=YA$Q-sR#@TVRS7N8&SmYbZilcks>VnYGFFF3^6$ z@tI7tDQQMRI6|LLm(P$fpQ5~fRC#ZvenHw^Be-?gACAn2k4w9m@lV-e7dHCU!WZ>2 zKmb`MIb<=_wy38OD_XRMcBuOi)rklwkpm%gYMVl9S?b`^GGR{kvs|2}_w)Z89lf75 zFqmK^9H}>?7QUnN^yLWcs_OqrklHRWOKvzUL)80r~sPZti+fvVr8orOI`6zZd>$YjXqWJg6=s$ zz_mr{s7bu(T6Yy7ApY1i2;jzSzKEiYt9*&2a#@KLoL_co21E=)yhT4`fnqag*&-4F68!S4)3K#s$B2fhgdQYrX7YI%vcC3Ke{Q{aODa43#rBvGua^gB5SR>JCdneP+;FKeQBuQ7 z!EPnj+9T>7LAjt`edigDgnlgPiH}PO6`_WBkDn$8V{WlbxRToFvTc$xf34hNd|dLk ze#+))lZ&J3BI?^Bs-Oq1;K|rE_XzkFX3O*!X3G?YA}ThVp?MrNW>X`1 zOEr^}=8>@TMC#B5TP3`cJ};-!3Xw4zUC9l_LyhAj>TmxMSVZM3T8JR@V}GzG*A1ms z`FvvuOtW6)(>?d!{?eNQM&EjtubBt?pUDIzV{hS}2(rd-gO4p0QtMzI&Y#ECthenT za~5@g|2uNf1-#Vr$i6C7oh1@uxU}e0Q>BI@%qxPRS7@Dz;0ClHk66l{JhND zaQc7Ig$DjCn9(rue)yL?5j~%cx9izcZM^XjcHKm|DHOyDvSO#vk5RiUV%$7y^FW_H zp8-bmjY<0S@EuN?nWu+{I!~(@IqSO7gc{zQ^l(@+$^_|j-~bE4M`Y%m;3K@hdPV=r zIiZuSvPZcXu;+f0r84Fe$8AH#!hFNd5|7nS32Pf2Ur8rdLQeyau9kJOg?y0|yv@xw ziXlyx8jFezJ50kRgg#u{cRsopc7fg<=Jo8m>4P5m&bJ$j@>z#GhqBx8e6QUX`siVF zTAVWW_IWnc@#1fYtUqt_(55@tcSw!v$KKw`{jw&G^l!lG-z~a-wdwu^j9IWW^sm(F z-x1H^-qHPgE2Dp<(!YR^Cf&b$&;9eztwbh;$*y$rG~G$*;p=u7vAoR#o4zYOtY3xf z*gR!gi@}#M@s53H&B9f1o|{@O=S>b%6D#BaRnDpJ$fgf@Q|^~PbpCvcX<&W(a+U*3 z>NaF6eK`VGMl&FWKrRQEngP$Zc_#XT^K*=w^X)m*;Ay)KWduZPo^hByWBP1~lYME=`|`)xSgl&%pHoc-<>{=Wreo+{=FCdI5}MZbeYMN2B=r zUK@$xYgM^fj(Xg>o?`R29BeX>IQ1z%x6bM2#*Jw1vG`#xyxL{9U5jiF6bMp*t5(x# zOjrwaY!AR>5RNKV!|aSVj!EtD9&a}aO~}W-3f*DT3vD>7;mcqS_!zIM=4jOL*D|dn z2U}l;@*l_$r=E$AOEcD^*VHu94CXqV3x;eW_ ziu~)#xl1tF@3b#G=owx{(e zGbL^l{f&pl^iTXv>i9o@mDyrODC8bC=m@XN@cobAt#r09# zs0j$-szpO#NvSd0c+zn^_>|{134A#)uRJU2uCD`aTbY4VSIK@Z(A@n~Bzuk57*{yn zv4?TEjmM2gA3qd-J6}vdnzA3rXOgPXEz~giB}R*0;VO!iPI0=CJS2QmAv_q zSllO;rndgiOEawh6NQtF6ZV=iEH0J=81kcq$L*h@a>p)YHcu2j?vVa7!DbUvQ&m~= zvzp?>8T}uTk`&K3#u+hh;iSabMl9d43q6NP#*$(Y9m@i&h}(yZ&j*YpsG5iEi5gp7 zyWN_5YrW0u_}O*d=-HxX~oue;MT~8 zV(jO%_Kq`nV(rUX|EOMGE;C;y>RgFBC)dbUV0$Btscqea43UYMS5}W!m*}bSiCXpG^SbiZ7Sc~f zUo?$!hnMHQ$)dPEVErKpHhPTEz3`Hl~k_s)CA9$mHhU`sWl2|GI~W)>&i zGmV7>FuL(eZ3Owex)k>KOvf|9Cz{SM!lm&nPIsV&i(n3!4m#E>|hxoI9~w z)%5?;_>#lU_{PJw*jeTf7GF{zHuf=Wn(~5u(U0}bJFMxF+2Ou&5gOVKeUA@JOc>gs z27xG4QCptX6?9ZwQta3>+_8YMUOINU;C}=P86CUDo|tX+YTSq}NfhfVz`2K+AgjIp z3u&zXP81!uBU|Wn?0`19G4;1-BR4s(fbO?G=$OOZhWKYcoT8)qt!XvM>9%wc$mt&_ zLaOXtH5v2*s4O*BydD#`Fv>pt@fWxrRLvW+(YU2`Db zPSN-gK6>`bnJx|L&tAGKvFaU9+g|{ofIN?uma=ipCYRnH0Hg;0E6A_ ztKJ#LtHE6#fLABU<(FVX3k2I&?K4)ns@rQ`kaeA2?dS~|^Y(>9$tC;3#$KAs!o;-X z;H*{qqL*mytN%h{-eGvMD^CStaR}1ZvvM?u9WFU&Y*ZGI1y3-b=xLf?n|*bGuxr)O zKC-94>-PWy;B}hby8{(7!9${X@h`2zGa5!T4H&JTKL%gIJsC#}Q3yexf|bD9Y;`;S z)v)*2@^dD(#<N82wGQ|`P1YF{&Wgp6D81+*Jj@sC@^mhd}5UxJ-sitv==%3{Kaxf z$t$t+@d|52%m-Lor$;U^aksX{={Uwz(lWdlGd8iJOYlM6Lp6-&D|ESWP^H?u4p#It9J^WyH-%yhuMV7{5Bk{QYEO7`OXmTd`3_d}5k+0`9`;BKhaz%g- zeg$rZ$FD11BZCQq)Qyl28O-9q z%25b^n?HSjZYt(nfp{y9`r-xL7-vBajVX?OXfT|KctZy;|38NU1n73=4Kd?QcgQ|V?4TcT}{() z+>H1aJ2#gc2)yk`=)3zT7&)H%ccE2ewUo^Q`$Zrd`(wQpo-h~Q#A;{4JDPn$f5k41 zyCVRQ$eC@(p6O&-YvmN_zRYy!;XN*>ROEqxP{WFVQ!RYf++`v4*FK9HR?~!&)8Zo5 z%^6m;dMQTILANr{;xy?X2g)iHMXJEUIBO9>Oq3=F_&Z6e-m9LY-m#=mQ^E9oz_||$ z-^U`)s4;#S_%h9Iel5Btz7clq#t5wX?|P(zK!6Ak5c3aw~M zOpZAZ??5lo*kirTQg2c@qjU2@#3Od~cRDFsA`!FIF^&!Tn6t`4I;JoL;?OZ?#Pu$} zCypQ)!VizQ?|lH0Bp_=65}0ZhBOQJIF~v4!S6Nw8h>%ae=!wg^@lE5uwD5o#6dr*S zhdRogiM}OP@(}S=sps`AihC3Unfyj*Oc&yZ{emoyn*4?8M!kU@I;c;S-b5Ye@psha z+o}30S7P2v$$2k@s>6vIrDTobJ#M5(DxYLtC2L-)s%|*UoRd-Am`e95o21WsHaYLv zP<6vgl3w$ITAWJvsTX8%Jsp$V5l8)1p65F|TdvfjhJ91klRu2I@49@2j;ggCxj(z zyaf{yx4xc##XK>WboNySG-9vJZ|DA(<5UgEc4T?hd)+A}JKqSGBV8HTmW8R_N{o(z zpsU$_E){G>xGcC2hMd`&8dC{b35_jp6lObE)41?Maatd<_$$PDF&DREVuEnrC`{$2qMh z7Dt`!r}uk$?F)I|YyX7)EH(ap>npZNbfn9E>q#5OwwSyA_g|=MpWHjgZd=jKJ5Y0U zVn?mLKK(Llzx*HA-}+*Hee0vk)9*)ui^v=AJ_Wo8#a+fdIH)0{W<3Su4~1BX1*#|| zBoX-;medFiSlEhD9LnDJXXvRmU-USCBdpHiz_lIrvcd-iHjwaDM9(X`FnUf|acpYG z9DCWisIzQ&Y`jn(S>^um^upEeB%@60toU)SXc!gL7~L=e#9L{dwaL>KmsL3K9e!tP zY2r6I0Ok%y*(Pp0R~v6d7jeVG`n7eo%rTxUga&#Z>4avN79KIS7xp3uNR~~4KbmB( z4XZcdwLv_+xkcO*wtmrWYZ1dCsVw%8RKh}EYpnKf9%z{qe5-kU;amM;oV>dKUobu8 z!l^7v9r-=*NwD`6wEk z-DnSm;lW*$D!@6&_eF2Q&j4k1=J~WOfqkC;{CRnY)&SG6r}cFSFPE&TL;flF9rs9n z=M?zFIgC#ZBjg&!C)I!Z0DQ7aO9V3U31~BZxLo6`r5a%( z!s>Oo1!0#7(pn8v*YZK_ zwZBh$aal9QrqGd{d^m)Q17?W%7 z(FCd6n<7XZY@S~GMVk0rz$bmr)@;kI|C9+fo-ikOMQq&fuQ!QMH*a7fJ>S}vTsGx8 z>z$Aq=*x~%(3fi&Wg9(aJ%z~Rhtw1MATqCo62AlundL%f=Cg~8X{Pb9#0}d3+7om~jmtDcbz>mZ%js2AX78f)j@+_Bes9Q%y2>s@ z41r-OrF`lvq|pW@8ya1Lc9{It4+-xa+(q`u*YPpMW^B`xXr-n^i$L{9On^_qh>=JshU4n_34r+G(+ z?bYCimHKqOl3&X}9_4yq=xjJ+87%(N9|Y2U=RBX(>wfLQBtSEGood zu37UYYHr=6NoSv(N!}FOr>ll)=!VK^L?Ga9`pMT%%rEJ6qD_ySF-RIyBWX$JWJjAh zsBZ>DJK4C>&kLEN;O-Vra7Xh5oJ)LJFKK@+70TLzFPMFSyXxWRm^Aj}7-~-|Q6-cgp*30JN4iEXhOggm52f_9Wx%R7nyaCh+DdLTgreErw z+52;;Tyj%LIwV_Ke?zh%-=J?7>Ig=GNwPU|N}~MhpJd#nyI~zwsYZsX0RTL%zNYOP zp_iUEJx~aIVP9AbU!((_L!sL0nxx>6h}wdfjN%Vd91*Tz3pW<)ps1CE+%ej5@ z8x0V~Qmzyl?d>K+F=&~sP)#*stRVXe$!;PgM08ac%oK-(eOSyuE|)YJ2vblI?3Udz{uz$-Fjms-Z%Kb3P=$T;x{5WIrcynx2rQt=$Aq2va-c_YX7+qJUD@}# z?#d1+)KfZeh1bdK3G~Rn2mX4V1jBw{7HGL+9J1hYVIl*}O@S;|fto3$ElP4DY!qDO zaDV9(Y0~E^J&o)g8r1T_Z!wfpnXi3PRq9(G9i~v= z5kV&Lp2f4Hfn}PBLZGI)H50|F)oFaS(!y8dfu+MHz|6ys=qTCc>S0z(bN+(+#eVYW z>^fglw))Q>*u=mxQfFk&!R>2BtbERW2%KN@Yn8i*Voeib$VZOlfgF(q~Pg(5^=OocYt(O};hR z#yrF##&%>1ARvF?6IG5~j_$CdFQiugMMH`fZD-@Ak8FPviFKZ_H(7RumRf7yG2N!P zdW5tZ2*h)TZ;iwFyiG*ZCY>Cq>n{@o|B-M9fUtH3Z_I%Of&ZBEe*DM6H2={xW0?K8 z%$9#@?&A^a{q1P(I_xomc9=aSl%qyT3$K-^Py3XWl+Fdnl zrF=Ph6ye<1j@FOdP<%P?TbWFgo`o_P8c2$uR@oO}a>=*wrsW(ds?;`pq!_`_us#}@ z3jZ6zf)a6BLmB%ytj0?_@VI~s6kiVK@U14F%dZ9yH+-&F`!2AU>2gzoo0bPExRjKB zK>Tn84EEc%ZgO#Hb)ZR!rdpLui%aVUUOS+4HS z9`;LC5T-=YN<=!UOQcNj-lB&e4P0B@2sVj`{Qs5bK^8lBt$7rCy$e+(j%6`9dGHqX zfLbhlT>T%xf8n*9^icwt?+g~lrX*bblM)1m=GST$${c7Agq^Lo_-sjT%#M0CA7Dyr zKtrE%vR{Ia#;Q5`NOJ5<6gsc=wSU^DZ^e4&_;B{gwaOupf(LJQ#l{;)BO*!t2py|* zwl5baJXGC#1sTy0S>WWNO?`pOrvCqy`l7!LUXm(vHE&N$_W*;q3{s7fc=@xUHSy?T{4Hqc$;6um;L zP%KUh?&3Wmt%Dmj7Ggh&0Nd!Q?W^?5!u3^Zs}xqn#V=bg4i2&Iwf0ko7ie$WA3Fw* zC1$t}6Czr0MM~gJect~+_1!qOKJ9bw|7-v9M%6bGo(1b&o0uWPM9?KRYM}l@(Z!8t z0?_5`93WQYH$@ge7XZ+Ho9Y`nDFE#jfGz@{SE`o*@rK3aT8FSm0J?Zkgxp8EaD;6f z5POLm;gG%R-Fz0uAq_>djW4?T{YEwL#xJKa$TbAn;D*<`VmD|7mL?}4yVhyUbIx8a ztG~|KKVkOSEd8fgdK|T_avF{x;*i)>$xa=;{o`uY`8(tY?Myf%9bR@dBp<~p$z?x^;4%<;8{eeH9Ft@HlDK5IEaNsckU#u8_6J>aQ$o>kAw=jCNia4>cq z0`t~&?71myBm6z|0)MLQ9N8qMm0{HI&ib^EYr+MtSy%g_|7Cuo-{NI|;#a%3oC1z% zx~wwY7<7k#>)m8fv#F{-s#}m>pn2DeBLC<11*wU5DQNTFN9-I_qg0mo8A{ZtL`Hep{AJ>Z@tE zmJKq5Z0Uymj81XRfhlSej9MLO5HBb|y(oYX!Et711gl zIC*mDUkJN(WAs$JYi|Ciu37gLgS)u0hZ`>_o_lECI1|`01*(b zfRV($_0z_XR=nF2yF9hG&qRn}Zo(o{|I+#y9q1QTOT9h4Lc1rBv0VR-9x;x{QP3}( zfympjkG)s7lqkkVc7%EA@ct-}{h>|6(g;6a*!)V@hAFsUWtQ@XZ$D7|bfwI>@GhBY z6==I)j#!otoV=~h&4asIFM9~X0j%P*zKi(36xY?axU)MZK0?BV38>KJ z#uw$F8bGB5Hkew)Hx1L%VE53J8rY)xW~(s;7i%al2ZXdbo@SV;b+sS_QsB>aDG3 zol>m0p_NL)%5UaIE9>lMB)jAVmqn)lL`4m&$rDolc~VzRDX$!Ni`99uX7_2H+q#Xj z*dy~sj%(^pI+`WdY6k{Rie5;8u)Y#b#-@*^zK~k-M}0J zys??SPLz67;s1iAOvwdEBy}TqYmXcez&9Ku1ewG)xojX1Ioq+%xMT{25hAf47NfT> z{1{WhPGBpNm?wwYyr91(_Az5xu-ffOo}e;8T=~^zscDqLJ8QZeJNyE$5Z>p5lRQa@ zv8i(-mX$UXvd7Ha#znJlaJPuSBLEx()Q-O}brpfY><0J7OQDv+;OO%B?Vc)isGp6h zLAs&7HtHpnZj|$qS!wrlv(n&vXEZygYhI*16{KtCxDZi`M^%Dz&WQTtsFx9tA=j#V zRh`_{2{O!MJPDUIYbn^5Z{S}j>qz*IAI`s9+%+yu?TaQyoTQP2U^+Y zrL1gE6T^W~s0XHcJ{JJ3mpv#LB$nHotv!g~o_Y3VV$IreX2ZjPY($+4q8GVYkISKg zI%&hpt(QHZON|5FwBF*ip`VYlf~7dPZn#euIt*chq&bukaf=uVC_NoWrxKx?q6SsU zYTI;-uIM?lfof*Qrv;n7P{S{E9rx-w+z!=x*;d`!x%&L!6~_>J)cA)XomS2kGiU#m z8kJAB#U{6|Bin@dI(N<5HXkhc%s#qU`5gE|(5Ei7{BzdR&_yWz{a)tS03 zzqD%3%=nJQ0Z;oxnH}k8J-ZHiU!|V!(5e+>&G~wiIVMMO<@IeyfJ^R z@u}JC+#9ojc<%o88FUA3`fz

;!%11g~&!yuip2_J|2{hN|@0nVHhZB-JR00vUi; zLl0-AD^gDaKZhQ|7*`&wf8zgE2#QNfGf{5aqrNK?c`0f=XPX_znpS&N#oOy+j}2t! zp}J#FA6t?cY#u(;md7XR^as4;qDx2|xE#p6JInTCA8*i#x8EZVkZAMUX8m+E6hAlL z)|c%kQJ1OSsb@{<5Tem~nOjm~mkQVw_g!g=p8tq^MRZH*j~x6H#Xw)u`ImUvW=XLT zA4a}o&-P|ZSv!;E51HAwke&5#8MYMn#AIp39n-%W9LDzA(flX}&5-ey`rQBMjxqgy zxzC)`?h>yU971=-{%veeQ4oGXL8OS9MFFf|w#R!2WKuFTG6&Uoqnm(fzvmHmZdg4D zi6tYuR-nh<;hf&?JevmSt-rO*Qxq$!?scARQ!hZ*L+U2R!B!#nd1N4ZDc)Qq!0FW1 zbpW?V1NS%q?kHy>qRr6>rf7tRp5Wk`Tg@tyy2>;EPgP1EtJF8Qa;#Ke;gimYqcnjO z^PhmUD=AJZ*4zzcSvn=GJ|_>Nfz&Dwm8fZ~)k%3_b(2oYuTt0PBsBU~>ZF3OD$z+7 z-~vS_6@}EfI_V!M;>}gQP$DzN7PiwQVEObmWQP{#&O64I7c1- zp(N44qw;`+R4I9gFs|o$i1+42)RXeilRsSFcF7|3JuDAW-yh^b>idOGqP}}{67}7o zlc?{jItjDDEjlSbtTyrx?+rv$R33T?MynU4`u}lV5)W=gx+I(PJb8%ZRH-v`5=_V? zIth<61w6!iy%BYeJoMycRtlInWlr3Ur4cpsYc>|%5wstwD!uSJB7JJ{_#V!mA5nWV z^Z)1r@)tzZ4>R*``+)rP_Y3L#%*bbcU`_GW@*qcSK#B zE`Mf3eI!->bY0AaJW&^OOR@9_hs*mS>WyDz%*SmfrIGiZ4=VgiI{y?bxW6yGb4Jwv z$ODd-bu+{DGrq5;^IypL$d;^RNw1a%!MCgBA>yi1pOqSV8Bm=(^kDs;?(vBFF3+rQ zrj!VT3;7+C!OrT zOQ9#sLt`nd4^l+#uhrV$arfKF2J43Z%cp#iE?-ppfE>9-mA}O*pPwpUq&{ht&zJHA zlrPogOKTq(Kel{_RlXoqzEmCit=WEol=o6TPc(Dw)H}uUHKYYg7uQ=4M6O!@riE`sYCtw(%-yPe~0G>O{dfpX+pF>x3=SZ zx;1diBl0AIMRlJ%Ee?Rbe_^JA&N|IhlmYHHQwzfCmpp-T026Tntwj2eUFek#sfZFn%6dQva4lXNCxUQ(bVH|3E4Y&Vno~@yk56-CHyU8hf z&$v`sE>Suq>k$9&-0gt>vEp^E+b}j>=LX(6%y^w5*V19n9ulR%*~@*=;m~0Z?#*KK z?vkBm5Hb>V1hU}_-?cJy;xoutumDrK-^%$tg6Z6HaWOMfy7l0Zp`kBW{W(9`x^zv>tV~p{ivBDfYm6Fa5g6=T*a9w~5#JmwzowG*EaxM z&&Zg_uNQmvh@AUVIa}9nutle11G|rF3jl244Lquy=nYlNI(Z_E8L9cd5zc1iIU$8b{@ANage!E8NEF zGTowkWM4mO_4S~!3$fRZ%Ly}`Xlh`Ry0sF#dIjD9H)H0soC2m_c`OCf&2D2o5%whO zNU-m=vJ4oNK(%`|7YQkl538S9i8|b1I=El0jE_q>ELbH!w!#@jn$ksf9Qs(EJ*5)} z4#Bw9PQVmGxZVp`HD;@OPo6}We1$Fm6V*-M(hQNAKg-Oo%>3(g{wb%-FL=ec%1=~? z9}!+s7)$Xj^N2n)&j(4b|0Rc?Uib%29V6^@t;5locL|Jh%1zzpjW|ywY8mD5#!;bz)a13X!6x5Ie0pS#PgaH$xEd2)_msdGCs}E8a7q4V-4N_&o<1FaEhReXG}F z6n9=%onxB>*pnY3{}|C8>kTlyt$GLmX}XWT;XzhV2d7= zmXOyGPWm6YY@4NC@?zuTVd%lf1$Qqk2tEz&t}Br2GeM#qyMAxq|Dwy=JAW~%;1Z9S z`4szvqrqdQUokFCu>%M`QG-_>T=A*GSG(R7mp>9(L@fJnxku06Dv*M<#c*q>85J?+ z;4a*z9qe}zcd78{t`k|o{IXWGkp{lUj`+XK?J}N_K^KgBIbs@)7_f|wt zTv6*=9b*&mNFBrVMbz^1*Ltcf_f^TAPZyncg{A!0k+JRviVCpqv?rc^QfE^>TqFMiD5| zY~IO2`Kpt3UXe9p-zEN*WghyPFWI~^St}9drT3}V+nR`LgYly3I0rDPCT`?|D8xPJ z+5AsInM>U@>T5*~34B9@pno~Zf^+F*p5OFgDml-metH~)x1iV%b`89j{316-rL*A! zJ>TjK)z+x%kSH1+=2q^&2aoaN^7xQld^krv@u5l4@$sRv@YFx#iOnU$Cr^;!h%whh z4QCtPDhoBxJ%g5rN3=uc1mwW&4;XnGvy2>H92ZQ09cP=wb=E#BaX=-iB;RT^JPBu444xKTu} zMD*(pd_xasWb$CMOH}D@{5nLZKRT{P9l29ut~!yQ7u655Q^jf8DjYiSr%nNX<(fl3 zBoK&ppNf1EYO`BCFY~xWZw{_yt9Bi7&V-xlw|5WMJLoQVFa)u3Bz*_nkqm zO-`fiPvB&%g?Go0fgD6y+<#6;#lb+cm%H#YG#@;%TQ%_;&clJmNWF03!B~h0OS{z< z850zBw_5WF#<&r)hTZCz=&!8u3QB@AHWA8BaHj;D>v}tjaE2D{Tq-?4v!irtd>+~Y zI^@{}QV&n)3F!-8_4dEXWQO!U`SIac!&%&lr6<$GG;4fOpPox&n*_)%?oQ37NeEVt zK8bj&3>I4k_dLjc2mqV;szg8yHCl1Gib|Qx>S{Uy`@dAjbVUkl?;jT*a>PCrUx%s7 zEWiYJpT^(Q2*GRe2@^f{FAgk*QE;}e3@n!VLrUVc{NCQNOLzs5HlIAV`3HFOakM`!K>IH(;Wy)GzYqF;!B3Uk4U}$W zMAGEj??0UlcKn1Ju5mcK1k#)jcwT5>Upm1L~rd0h|X~#I>&|R9QUw`gkYl0 ztNB82SQuHZf&A6Pqi!r^43%Dio$FCX74{Zj4p|YhZyC8n$*z%0L;!6GSDoUVu>iL+ zbi#gd-=7&kJFJtu+~WfrEpGLX5{HfWY_h{&dGq9u<_y3f-gFOUk80feL5;uBY4*;9 z4_ppHq%~?hB4oNIOnhcpBq3<=!E-%deM!)?fWeWj*BzYsgGX7)ye2Q|{xFOdAanr; zz*Wbxzyb_8Ib{muh}z<;*wx7vJ5Em)NYuS47PieXu{P-I642K~fgd&ft29fYQCS9? zCy6Flf%>_?4iCf|D_!FRoJ(=&vw+C*y7bduNtKSCVOCCz8*KST2l(RpD^J*2Q1>hi zDtbl-_UGfL%ogu_J3i?4e5nwUimTzjE)lJT&0G1R%2EmOz*2}PY;kUrn7c2|O%0fV zO5cz>%woE1u|+ak@!LAy8fkaah3S!AINaCaAv9>eE`JCc#^X>{mOoG{E$aK%`<*2S!_eYE@V^m?5?T>b+F^6sI# zD4QC{yNABQFAO|N*Xk9}#J)gvfW=z#PvQx4^boVmA!eCC^ckJ+ME_!)ubTz!8#xo^ zDg<@5cl&2p)e+jm5t}fJ6*p^hn6>$Iwqs-xv7Xn_9h?(lbND>BT>yh5o){MMzO-Z@ zS@9@AXjuxMXG@7JL?%j|fTC#d?U*b0jEPM}3!^}7MX$KSrWve`T~EB&w$Ib{93z)@ zOc@l|=adA(g8*bCGdc?Uy#8=qtV`J*BQ{C&Et z$d%l)ZysiY!|Ge<#MSQ9oP?AIM~CzptLEJx(mC|bm>#OGYAA?v&UZvqJ*7bYMFd<;8%1rW8y)KVg zV(jEsGjDa;8h*meiL*I>g!{DHcyYIW0o0)6rp}Q!cgf`1;X7xc^gdDE++n@}Wn!(W zj#E#(r@Y~Ic`M3Deysgomde}BH@LHDB$mm3UO}+ARt)xPOzGJ&9r&e-ZsZv!g9l*G z2Kr}L!$^D*fQ3EdSQ$&PXBJDHTqNw7#l{y;CR?)@?|6;UVxuxI)X*kPisEBFCehbO zi}=NbSqEzi7W8-8I^ z|I&&JE}&-EejudPAmE;&jUtcBkU)w&rUB6zU4;eS{ZBjB?$_KQtiD{lxKxl9=?*;a z9(r*tlWJ3+eV2vUtL~P}WOA!s;7oFp;~L%1Khp7fI=T#qPIq)A9Yx+6|6&L+Lk(!X zCZc}%>dB!7G3-&F0Z2IW_~hDv1*=i_tU-D+H&n8d?F|NG8a!KIKy0=Bh87I%?E<8Zv4D`@HxqF5*0kMNhh|_ZZWR_iNB)jp(Bh?QN<=3la&hi+I+3z*3*k{s1 z89QzD_rK4|Twx|Q{9T&K9zBW*vnAb38UV(&@a`Yqr-c{HM04$b3=Pq1PZ0NieSsZ?495KBA@x7sqU$35vSivB`s!NQXVGS9=Dp?F%SXwxO?hv8 zXq<6$V{Uu{28C;L>rFBzw+8m1+uP`ovG@_M;jNdu+B(iopK+$T|5)n-TS-UP2dpob z&DcNS@!iFJ`ps_RD_e!LFavPE8CxP(rQF&Xtlt#*#$FRtJzV=O2rTu=nh z>&E5pcS~DvM5CWzh##xngvc$Ir8RS$yg$5wdH@&Vag619zpXY&Hk}bE$G| zgE+?{s+Vkp3H8SARV(TaeIJGM^s?{!tsY&yEPEYJspXPR!$0yQmRD==pC#8F2Q2VE&Df>Ufo3)=bZ{aK z)ge`ARWpR^PIGm4p38iEp~0w5qdBLMS>o+qTR^Kf!JXvpo3C*}yahd>xn+sUyyz0+ zhO$#^vQw<^C|J8|MCG3{yAp572X;qPncigiV}WK=l?z8y*`KdRhx@YktTOO{RSx_r za|-TARf(ffy7|S7k*B*^aLPK5q!%Kreq_}-z_jjB6;fwQgLzqR(wcf>7dy=Oa|U4D zWR|Jd8|-FM#Q$BqrN9&t(?JW6rW<=TAVIMRt|Xh@X*{3qe@MOfOLI;R0!Ze@YCXr?ShXoYS~aT3Z&F3{ zt_qVqwX5a>MFl#n(umsx3x9wdQ~M>8ex3q3X6%Ip2JE_h;*8`ZaCYV1I;tM2XVbORY*_6m6S+LgAmuEG;&#m zLmS9z{h`mo?WM77qglF6Nb6D((x^p0XnYIiKh=Dl0`q6g*A%N)dcI;*{6X`z%$%M}{09pp|O)EM5eN7mrt3sQ1dfK+g;~cM+AIp`%8N-*; z>c~O4n(p`?nIgpa-1tt8O-cPT+|GO^rGFO5uzQy_etW@>g2r z&!K#7?DW2Q3(TIaOn@6|33lQ&<_9FCCgN;(;e0d7gB7n7xwEHjJAI6|IO+I9`bo3` zey5-0C@XHC)gPZ_(I<((QvE_6nTeJ?1$(HR0g%YnQ}ZT(;p^kN?cXJFgi_^F)%Q0c@WiAViRzsA+h=vTy&? zDys|KNuj=ZCjWzCIGd>~QSk$j(9IIb7e-M?M3MGwFwe<12FmGS#VO}Y%(uIlf*@1x zX?uVt(HnXcP0!&2Aw$`bCc0tud8;owmE(TqjvYOiK2MtWHREWX;v5r9G{4C)eu~&pZRY`xA5QV&RO;6TeHkyia{|I&;TF%HR@LEla`8IumYg z2BJP6ym3ou^s};R$KH^=scwG~!4Ue8C~Qd2CmVy7e&Y^x-D4+VNO!1TafCAzdKY_# zLZwnSZQ#3nOR4dBr_}T-v!+U^X;3<&CeV?@7na3OjH}-uN9>Pi*w(!0blr;8#^N8G z;>4Fh{!X(-3i(q%$C8$YiwL-v7G4&y8$lu958271?Gy8m$8)&|^)(j%sgwY(6#?xU zm+ySmRd9&cmTX{ur2Tnp$0AMSy{|qDq@R@iQ7k#J>HCiC4;{KZ!(TxE+3}Ovv5y+x z=}aY#ikI0ds0nkt3trSa$J`lu=g9t0r!jLKUuAl2NHlV^@9p9Y$%go{7?v62{McOf zP6V=LiH2*m%s9ma?#amb+>gwRJ6Wsp#GGr5P41Am{r_o>1CN1w)y8{C$I#JhG?(eE zLBOw{uQ#^_mky#DH!R355DQu~$H9puJA+-2SSTn|E0!};--}$v{<>WIeEQjulS8%1 zvdxUfR;%v(T(-?YG*TzG-li#E{cr7-kSk1us7oEiK6CSa!&S@X$BBm40I76qWkI3x zIE!lgg&@NHq={z6Qdi-lXl7JDBuy4R9eln?uF?PUHVO};vN-kzyJ|df7z>-Rahkya1c~fuP~16)*4F5B0bicumqjT zR|8R*LNNu%uX1eHhroYAwWZs;=(c00V`rGq5PQjnlp6*W{m1mcMCHW6onjRA$}`uQ zYr!P3!?DUm3DU8zo``5N^_5Qi%&;amx#*1F_*>xcTug@ZNt zU;8c>1GUw#R;u2El!u+fIE$)irdqu=P0ILFWh6c)UGvJ7mJ6-RqwFHnB(tYq>!!Gb zSn4sb?u<}ukG-{~R^=t{aPj+y>R zTt9$_;22E>qt}%cq4VCV!ogZmM7v4kzan-d$XSWZ)(#D3!MB@cBz+GC_eIa}rZ@=|QrSw!^!(zAMWd^ra$C>VbIBVO}%ShY~M8$Xk4+X*+FKDgP2LIF&Tl&y%|(aeG~ps@e8C#;nji9NxqcOut)5R2 z+?Y0IF|L2eEfrzB{A%s1y050zzIBv+I|GYN|3Qk%Spu*7y%3eP4Z=Ti9g%q?P4jaN zBlx)j9VWJXGeKfKZ7<8ra}T-BmBoUhmu~8r)1^uKgu}o0`_i1Ld|D~DY~^9mJe^FS zDY2XQ8O3?&Qk{)-8#&Hopn4WBaWzpSmy5Zr&?Z-ZcI&l)BGDiyCsS=B?!K5?;04@G zaksKJY3m+X1U0Z`Xvl${v+h%}?9ZY|HmYk)d!=g=t*#BA7u)Qv#p47WyMv7)H74eY zZ>BO~b5svb3gm(h46G=_o#&@hKBe~R6OEU&%Hvzdof?Fcc#X$ zOZliFF+XZV@)%2>DSrcTjym07KLEwXFOXh=Z>J|+Z~>G41=$BXlq<-jo2;W_$eQc} zgfX!I))h_x>~6IR{fUq|_B|6|Ujr&W@2;(B#OH^)4V_AaHX~OZvY`!d%lc~q|6Dvoju_&d- zXIig>R6-}EbkjY5qC>$Qp7<`t#by`vy+*=gqb^s)q!cmaYh=i3$`84yWuT^`bqL~u zP&#b@Uk=GiT;xNfJo5*yr=FSDqm*`?0~N25gYsBw-lq$n-{{iral_n6rE9nk6iF$+ z)-aML7F4CvcIev0@5odsw*UmsiZwO%v2MP@ghE-YIqup}V=lPq9i(-MxkZ)+zcwBUyEE5A z>mGeV7Zn&>Hy$e~rZd%ZX1+%mpCz zkf$vSXbKKkCvZBKA2OZg>gctM8f|Agijy?ET2^f=p!!Au>cO2d_SkoZ$F2d@56RfA z{{Er~rjMCm>epcE{cte)5nW~4^57IOYO`{j0!Cl{_HcjZx&=nP!5s|F6YpYFjWA>u ze2QM42VBLbA4`G3T{3wTt;`S`z^EU>_07L6D+ z)~KmQi54Zb!Ni&%gn)pXdr(NQMY>W{gbknq2A5!#V=UfUZ?#ypUTRzK;sp$H38;Yg zqS#hjzx_@Owon!Dn&0Q0Gw1BtB&hv8zyI^+VKQgWnR#dCo!dL_ycZcu_V}za<8x9- zpr?%PEP>1{5ugQPWW_V`A4-J`ykavpkDdD%eYA*-awVKCLOBf1p`B}GaQYdQS?)fx zP!CI^2Nz^$x+{q)-Ynho*3C(D=%E>;b1uN^T4L;o)S)@*JXhdXkIXxCP8pe#dXLOG zdSp)7#Ff3UhNd?r&q_1Q(6rajrMucev6ivlqdF;<^|?~`vfI>^?-RW;@}rUMPajJf zl-J8KL_0cy($z-J65{AAkC0EuA!HM>GL}m(Vw;8UMLXsdRaq~p8(#trTbOljX1pU@ zwAIkRMtRAW(;8SKV)ThFk^cx-`M0zMZgDOiQtusNW3bM5CX9zmn_xUa@0Fa%-fsWM z?;3d~l$-q{r|bAL=@0uycGux@1hju-b%n&j-~MB+3M6JPE0>XFl|<;`7i6&%2$my4sTasC05WjA6cK04QCG|g z@IEA0BzOhkeF^W2<$XWie`2T46JQG^jZKT@YhZ_QZX{C{FSE5m*OQO{vS+!s(LJvI z`q)P2-6%s$ivy?yce7TBdT3?7!+42VWjRF~V;7IQBsUhtZnB&{Q6o!A8%$2QII9dH z{GGxos#HTw30u^C0zU>qQTfFu+WvVN)&SImx+93x`-?uFyGPhaxHJ^{*z0VP6N0;+ z|Gw9LzI4~idXU;0xBl8XGrvS+G*h>@=+6uX=3!U1x$US>i*88sv4m(wte_7RSmzX= z`-5T+?PtSi*_*Mfg+*2*6VArTo)#{>TpG72l?Qk#pfm=xpoS;iw$yY3O}Z`WQn_VS z$(d8g%t5^bDt&$xc4Y*|=o@TR3$Ors0Qp6)(AgXjj6!}fuoepi@y}%Bj=8o_1Ohw! zfP2DOzSv~1&1F0C$$~bL_2>&(g5XgDR;^ivJGE^6@m*wlQ>-F-5`oW3!Z2mC6U%ZxpuFd$&^2-(w+L-Zq}rZa(y!A+knusMw>b($alq@@6axfhf83&R8yv zyZfHDBGW2Jm7DC0VIW+uC1r zsp$Re>?*8b=lQpo;?(;SGN3h%hN{`39JNjC>3zUF#Ef6|18so^`re>2mW_}lN(sKB#ZKV3kI`g>m@kcRhH6W?ybA?`2?N5_k!Fb;T&jFM#g?M$_Gb9>#nBp zDi#%)eQj^R-W7VO1Wjo(>zW)SQN!<*pwLa=o;BVWkKA;>h&oDt3U}5AU>RK*Qh(?M z)_#OY$MFL4`VY^4-Q8Klv)-RGTEruQgNL&Cl6>ESVJ;qohw1<@7V7$cJzl!hwUdA;8NP!+u;Zm&!^ks9Y&${j=kSB7= z3kAeK8DE~-X7;RYl_WwTD;1MTftqA(Pn499>R{3fMb~zSe7n*>afMSdJ0F3l@|2#{ zv-CI1$tOpblpaV5=p{@4y`(%`m+pn4OaFy@`>N-Pmen~jwe;+srPoQmjXm=vX{2Q7 zCrirP_3G(`qDvnt-|+5|+J@}TC!j7pZD*BC9m8)UUfDUWXTIdRnJoQJlJY2Bx)+Kr z{YLrb?**mvN2#T=zNVIbzU14&NJ+tba>Y%SeyXJW4Jq|1?LyI|A1dGCy`XeH4Vi5% zXIo@Xd`bPg4Bgi0)^&IATL$Le<2NkNWZ%ZG!k>mD}=+cvV)Zo@;J`uGhLiCMm{E`@I-+vWO|A1*HSeMPu( zNvZEM!h)+xee;+pal)rO-$?ur;cmingpGtZ3I8CVW0M{@h=2Y1^G81&G~l4%z(Irg z85-j9$YF$OO>J#<;u~~9a}|iu3IQyW54S;KeH&!z zvs>!ZZr4X{zRpe6N#3poNqx=@v=uzkcBP+k6Q`(g$&#C{n`U)@o1S<%j^ZH-UV>H{ zzJ0}j*1#wzDqNF)VxJ-ZJCt1WPpVKSD0#FeN`%jXqIwZ(q8HmzJffHX4ISO}E+cX> z<|&@;ZVELtcCb$Se1c`P*owX(-(!*wv7XRsG50XIq0#Oc?t@?Hb<&CNs<+SLqVFC< z24?1dI24}4m_myft~AH(?#dhyt1ZvOtR+X5t)5$nrJQQyyt0KG{zyIQoFhb~Q?yU* z+_=OVxwpGAkJE^-*G3rqeKBiLU|$+8@pC7YQ6+L11?oRY2T8I-!6TYhv-WjI@=%iB zz}I3`U8&W(XJCh)nr(tT<)@@94L)P}ZS3fV{{n}R>}cfSyBW5KK1PY)0PW1{edb!T z%+Myy3m0KN=|@5txLJB9zs^Y>Ul{QE*!aS!zNYN>!s))IVey5t zeNC{d=lGfi#TUkW8O#1E8#3GqJOkV&Hw+N`k^D2(XS8T40=7l-^YU6t%V#Xx!&7%< znDGfCn`Y*8M`on2#{k9{%^C=|HHHyS5oQO@BRDpc#lISeaKYZLqg&b`hxfALA&2N3 z-Uqv)p1W;Z*I~$FZ54Y)dIxH(Idl6X=9D{sFw03*8+}qi{76&YP&~) z%k_4m$?m-eB)bn#P{!48_I*-V#xD)q+s3MnOO0 zPwSaSncOkLwvb$ctN8k`Y5(~gGQ&0ojx!iIl2Mi^1m^*0<}C89Na;~-vW2GHBf(G3fbt?nDL`JmYIGAgv|MCId+W_zN))_lccpO}P@;i9E+MCC^wQ>Af4-^U353;!q7 zlP|i=z~eB!*iW~}nLdlP2?i7kC(o=*MY}Vuo-LfTu}0%q>(zOe&>tHpETOPc^6_k6 zO=4Tk%bRXkG961T#URkT)wBK$W^9=CPe#Yb|Lxcia|YjiY?Pb6KhW6NG4Y$m#vnKM zw~mcG85?4ZhsmF14Dw)&XCMebEw{Teo0T4pszC+21&q}%ggq{M1Ur}P9I{m)5Beu2 zj~-k?+KFVzx*D4>nwVSfUJ%b%|1ugoSR4E2ivUr=OWO&%V)$+)Hwco|RLkogNaeBJ!=b&!<3 zl@SM8m3 zN=e*SH>XlE6bSUEzDtH{npps0BX3te$rG1DnYknTzULz1u|EkXZ_;9!hT)N062Fks zW@nA09v?El#--#<-mfjtd50$R$^k(i>U3WHYj8^5Z9BYo%excUO6^( zifFaYtAE|?=Jm&p^$3T*{s+O;#mT&K#Ohk8GwR2S^$7m*BP#Zbm3&LsS8F zD)s&FT5KT@{y?~!->(qPVFFGgTuSKV{RM5MxSlWd{hHwC_fp=!&GVtes|miL{-Nd{ zhrE9M_49zCa<~f(IcR7`*gf6hFGmC(LbcZ0btrv5FGe)um`ojrh|){yJu%U=DG>iR z-pOTIl5^dxZd-yUx;sUFXN=J6Q0rEwdS(~2`c`%JCYGSxB9QxlyqFwPul|L2vwCn0 zH%m)$n2)P?YHiHJLV#_na9cz#c{nUdG-M?jvJ(vvYivDsU;3@qwlQ`;FVWKsEEGmR z{#{ILD80LpVm7OOud$Nt7Bf$NHAs9X9wah_+25y zUUsi)Vc}cn==;XD!1am3cp28Ou)672`2tm*I>u>NFY1f?DDm7Zlu#AMW=(~+tAJf$ z7IdoH)-)Y+lFoLqV=fMdWJMqG5aVIJzwV+RVjvb?cv{g#jz`k+#4i+9OGnd0+aES!FUqfsHwlBJbSEOz&B?+T_~44So9Hj@f>|glOx0R z&Id&!#BpAhtN!|nue&jMv!)qPhThT$i+S)G?TOb>GSa>SUQ6HViC5%#l6(sXwI4oi zqqgPSP-{V%fif>Mp>+T~z>fURldQ9?hlCRblton8vX&1$Sr1>ITjP!NiQEn2n_qLIC zvi=m7!-%$#wgxu5Q>%4YUE~60tE!i4q|K^SYPD6J(eC2xH>9>2ku%<|av!D%h?rq& z#wJiT?<~tXO%0aQ6jmD-Be_JPM8PddEKLz8V5vV?>MvNzyW7Rm$)5V0N_`}qU!5R1 z%EIRUCx}Nzj~%(5R@^4c`xf+^XcBnP<6H+Fq(9jvqcav8SsJD3g zod?usbG`*VJ4^x(dYl2ZMt@2jP~$ySnnac2i}Se99wRH1NXMBg-%0NEsO)dY^HtBy zknCrh)xFYyt?JI_TvVpZ8yl6aLKuDf+e@YI#fu5QTp=R;LA~^Lovwye)&%LmhfwzvYI$g_Lo|@O#w+aWv7h@F! zRibh<`|%`Vl=vr&(F&XqInZ$En@A)IoW;IA0K{JoWn0z6cj*Pswui1FVvS;TN?()NBwt_Bj6c1|#;BH7ThXE~y@nxsCmyhI z(v3NLEF>mnA-_(Qas0l?-EB>?bzC;=OcUEiDVK9S^6ZJ)B?^(eUEN5A4r2#qQ7-M8 zT%4GcBM1<8tkp=ysDBeAGsy|{@(bygZJ)0c6IBK?YVp7?T6??^ihvf z%4SuDjyqkZmys*p(etVfhw*CiuiW`m#cO9i)!hbRD8kv7e4p>Ee~)P>J`a=v8%h;U zFH|rIWrzpLP@qU>a|`DT6OT0G**`Pm!z!Q3C0*qVId6Xrx#bN0>EuNcAXZQQRE?dW zH!F9~GhpCo)iFQ130{HFvu+ih20ic} zKvqO_Jcs|%MbQX8IVdUsG(E|UxO#dmDQx;)K%XI?>CpK0Zqcu}TIT&$b(3Av8l?A~ zlJ@M-9Wm=LR=2~Lo~r$3x2TPLbBfw>3(CX*ejmONkS5rW=6N99XCS2k3DU`@<|iRt z>49_=kg(umR4LYb?((0w(9;`&QfbK?p&+-axA7Lo7)tXLc)BStlL9lPz<$XB2YCuS zND7=(zO+;1fA_sD<8)Ab-2f3_KSY4nj47%qkNt!~Vs;_FUc=j_@}>XM8UA|YUb^<& ztoT0%&GN@L4ODCY49d>Us!c2isvB;iS~jEYSG=~dwO!r*D@^nLdB;}7uYs|Q{=+lrp^Mk^hDjUhFoqhHz(`)P=B8KEK0v?2b&193gMq>e*? zC|&~94M~W<@<6=ZKz!^NspBdKVx|r8Ob^7%48+5Mc(_0;NkSa!fjHhkyg);gi;LJf z;PHh&=~j0=n{4&b2I7%GJW?S3>jt;gAHSJw^}d^B@_@*LpcqH3k^2nY>`QHsw|GFl zOg3ru5r8~GK;E7Nxyl3b9zaUhJeMQQmRk;8$)jwDWgduE7>L#K`T?FAKq@hi1_4PNMXHP>q)ZQ_ET>XGkV-*3jK``~P4^AW!9^z#_q8i2-Jaaf@XeXrYj32v!U7v>!}u|!+P`(X*ft$lT1llGUvXxcO9+i7ykEJ4ag0Fx_D9b3@EG@cID(?JsFvqRZBc+u zwU0d-Aux=Ud4==12SPsY?KpT-YFevGPRL@P-mft9o_gMVQg@W?Gu5HLrT%oUTW0!-sc`)Cz8O4Oa3`aRFS z>uVd=z3&xk^S)QL%U$c$Y54Oxsk};BRecY;Bl6Gtm$w%<3qcEyX1o<|Gkm!|MAJ%S+mHP4tKO&4KTu5UiOyaqo@KeGi zgv$xb2)`iQM!1*oFySS_TZH!sy9iGHeLSZDX9yvSa2(+j!YINR!nuU=2;K?8U+6IYvf zqKU_txX{G;CeAf+mWe|q_L+G1&31b}F!2r(zhdGICSGmghfRFHiC3BUCKI=sc#(rinjkv-52>@l7UPX5twpt~T))6Bn2`&%{|K z4w!iNwKm)jOx$kb`%TQk?|DQ^I0|`S3hZBw=oJcs8Fp5x07*D7mOd(uAxQK8W z;c~)KLV|ET;a0+3ga-(Z5S}KiBWxkON_d;_KB1GahwvG}|1jkfh7t}Z978yfa4KOG zp_DM5P(heNxPWjG;WEPIgr$T8;d;WYgu4h25FQ~sO;|_RLU@(%HsO6jCt(laGlKsS z$|npZ98Nffa3bMU!YD#1VLYLNFokdd;UdCigv$v_2?@gWgj)%B5gs5sLU@{>^{e{L z=|3Pia1Q?l%@NVNjIcbr|AroXNamr#4$C_Hh$FL)`rgqw#~gcH?)Q&BA@9VKhUcGr z$`3}IdfLc>AD;fB!ck`w6`%Rzvr0-wpFL)5*|_rY6V919Y4W*|ipnbd7}eEJIq!TI zW?v6er!_QAzu+f7opIsJpG7a4_4C;mUvlX?)ba0x4+;Mvd`?JvwA43tJK3c?M9+X%lUJVtJK3c?M9+X%lUJVKtoeV>_$g|iO~Vh7iYHw}fqC0XIQxR?!Kp0q3=?1JpJf;?fS zG{*WJ*&g44^^B&>qSxmQY?y{$7O~Gfvc2ea_%I@&8%{Y4Q5V}k%kk^DY$_|@C`42! zQnZ>GA>YO1>HyQVyRBw&6yrF+2&sv2FO_# z2(W|(YHe!@S^cB${sSISBn$PhVVvaYy5htyq|81qv7Vn~*kO(0v&8=^vDXhbagVBP zXS88&|6kf5_BK_<@9)+=;X^QJVdTVy+ZBNQ*VA>(xRi3oPea z6vK!aEfA=Ew&1IY-WGIE?P)$;?BNEV>unErD)Q7KlZ{0+_1U5LhFg8BcGNZ|Hy3jp z9m{fsQzQS>?+?My_>*T(~I#`M;Si^DL7roZWky{f{|KN*t&Z3Iw zGI^{0=K*;uZ?)&__=a56|F|>EY&m;TY=(u2m7y?+vKSAMs_x3^h9#6mim({l&JAmk zaSWMwgvMV(X#B+JLJAOzMpEjm>aZ49AG^h zEbC!7xf~8{8pH}{UdXy=9$EkN`qebriUjr2m2IWzrD&+5&-{x0BDUAFd>zd46$yIR zuYWl!m$2313$w72m&qzr!YYKhb1~|N1H0192&=pJ*BrS8j^-WfR;+`5Oa6lRfZ3Xhb2?Z<`lJ7QgU2%ZrKk9-Z) zikn|(d2Mk&>*8S708tjTF7`>CV%O0|c?3!w zx@g(;h7qj|IeLu_p#@!`j<6G;v(QnNB`I1P0xmNX)Y$MM8eVZkbsg=()8Y|{hKa2W z#iqc?ITh+fJ3(K?)dnin@9obAEKb&w(|fHa6*Q`jd;efZ|Cbs34AV@R>*}gM$)=q< zvb(55RL&+F;7f87OY#y+@VyDL!(jnzJGREk{czYOoeB)$%as99v`(G{XiwR^SwWBb;ot)ia`(mZ<@--5&tv$22 z3^S#7lxc>x)F5+HS-_`8Q$)NYyN*iGL0R;VPo2VIB3KtY-|jV!Damd!J*z}M3++}U z*ap_B#8LLe&?ft)r|mjIq9Et zjL>mQuL_?0j7pn3an>Ot_eS@BuHA8nXN5eybj5OWH_`7twR#$;X1r)yq;z<_dTV+T z&w1j9BVYUBc%OOChJ|;B02|}xZ8O-EY6)+sYu&zr%#pAgtoI>X1q+(73IWGK2U*fhx6gM~fy zYcU;I7HF-X!BPR}O`}PO)roTUuP>9@bF3 zx2CfpTaiGbB0%$sMhBYuB_;&ez#@SnY)>Qxb*0m0_Gxf1InaDLjVj|7!pz}0)5wGe z2&o#H=;wo@iMbO!t7t?M@61YVYXASvKKdUY!>aUuX&?Q=LuI&y4qzWWzAKac94$e6 zL$9@VJnWZ4Nk09Z2}y_vhE;R{YqzzTm0hfiXKDYkSw{b8S`G^AZ0Sv6G*Z_4v9f88 z)#mbxUd$N%DuJzWFLp-1SD_GRr- zlNejQ4_(WPgR;$MEL$LpC&nqjbLO&k>tjZGeyor|QFKI8Ze5l3X;bOdB}Q;tTN3b@0-4{;?BDlVd@A&LaUEL8<#J5!@X0Qo zh;ZwenJCXnlxHW(a}(uxiSqnJITw@#t>uNS<+4o$dTkoO-`od$)&-$dWcd%Ng&=O^ z&bG-V?0%UY{R?h`WGE}nqZif1Lud~hQfosr(J-6KhPtRUkpt2|qcdMsR6sMIz&z|d43j7UQ)APL6 ztAAF3GTlGiyiQG&bE_Opl+R9-#}egSHZMxF%JD7HD%b0YR=F&Xzu28lRX;@Zv5_>%FaB^eS80i+l^`adKXD+>uZ6iO-p zV^$&2keg`8OEl!SO&&pKW%*U-AWh~y+-sFepge7@VkTRE5Z zW+iAXAJZ1eJwR{uHovdsg;M6%_(OWqkBjOjCcK zEkC5sGX3gJeptzq#s>%6nCf-Xc**_%P7ZL=koB>T`b1^E&;_rg_0fe0kkC3MDS7qF^ewoPk;2=GVj-552Ry})$ z<{&NGxv8H{6FbECFY`>g_0i3O{@49ZX6dbpk749Id}jA)23{|>DIs`}$6 zsnwBMs#|-!tdo*}^gb*v*i6&iqMCUjMHO8Vh=toGg({?)&)TWZu&Oje#w`!xxlaAK z2k06p@5CN2>*U-k1vbkzB$Nq$g&Gq;(*F(LRLrLI&-+R~ z?~tBv+lmLZWonO4m1@M-bd8)2gB4g$D+|#S=RDS%Pg7HGvi66dk8!HNjRh{=jwz6}`VN%~e=w{Cx$e=Hb? z4XjX?46&E?nowKl*|xxqxCUeIWe4UgYPKKPV&b-enLTM&g*wyDpiiQ24&^M^5X7Ab zF10!UTeNQ8Wo?-)^eWucZ0&BTEl|WXzI7leIpblL@73Xd#-IYHi{URA1|P=uhRE4? zC@gAe%)kA>oF5$ianaYYtK|M>Y&bC>-VrGJ8dHb8tJN0J1tmCRe>{9QHQ7W>wCk_h zs>IlkI*PK>DR|PZ;rrl|Vw>D8J zx4GBk5>HTBdTzl05)1rLWnpz0#bV;6?Yd?jSZlL7`p*{XqhVod!=l!P#VRMD>lLyk zKYNf^hDmf<4+&qpzRQ2dc|aI@WhFfXlzA)s9dvB!Ms~wFXqycG5yC!nho%=3OTy}H zAE<}gN-QZ!EE$tnQl3~cF;P}5+?8JJY2BY?;fM`DePI(j0Bz_zZH8RVNO_6UiSB~e zQ96;Q@-hf#W+5c&2(N!j{Xpbg3-D{26CiU9=&II#_1 zeOeE96vKPqg*(w$cOn!xw-#nLN-Za!xjr=t*p3GUAv->R;3CmC19ONs^Wti!#3`?Hl}4 z4xzW7?CkEgT~H>uwx8||9MDT;vV)|5mamk~ZEqT^PJy&a=${TsvN=w97(tkz*8pDN) zM~Ll0?TxSEkqPa9ZNaZbGgmbkD{am0~mW64GfF1sJ$3D1KZQCJ3A}XTPGWw z>r!zrX>k`O0w!bNsvT}xE<+BmVbuya;Q^LeE!R>S{WFC6{T=!(p8M`lhcV)Re7iVVZOCn{%~z|iuSew% zjV`J$_o-vw3-}_cn7^E@x+b>lTzqJ>Ts{ocAC5C0M$Yo#nbfkGw(A~J2a7; zAKQCbB$_Xo-uRn9`xk%d3@R|aW#{}OgudFYPNZ15$PH)7ybZ>?{7s$UCZtw=##kF> zEg7L{jbd0ai{ zIcG|bEk2$_q`>rOKs`BC_o$qp^IS$q0X<+XcYAo7^6i${EH7ZG+Jl37i|1brY0+wR z32=as@8zcm7|;5k9IlZsF`~x9?$!j<1#J?~92G zZ2T$9x6P_n;Psa`W`u86XUi*Z?MJ&skZ!X&j_(@8ieKC4>#57LscfoWGq&7d2&fn%xLK-8J@oRl*YTKz{S z`i(acTU)L)n*_318oeit_o7xyM{zu0|Z zyt%a80l|t_fqTfr@|N+`+GZY{I_k=$c`8?@s>OY`Z6?}=-fK;{`b0D6@I|X`K1(O} z_Q#_iIT&ePtru4K9p3LZxZef93@9(kOAhls6~GQMWp1fchm7o1Vu=fp#bdKNhBh;3 zM7Pdv!e(`lyz*9Jh?~XId}3=@VseZOHzbi>U`Ax3Y+>vmhU5|AENioR{T73osPf!XTUe3dTVB*vB9 z)jjEt%CiXk=LBaFD97PlVg>!Xl&aF*m^jgXg5mgRQ^r@grjfOax2N5VB~cDap{@Xz zOd)%0V6$DO??3TK>K)z1y@nmD^zt%R>6)$~TG_v=zqz0CjL#mGK)Fw0^^d;fSFA>Hw-s?#%CEI>3bUhHeC zZoZ1YldW-B7cizTt!ht~{o*k17x*U9OJkpBJ659P`h zP+M1n4d#P)GS9Hu#&s|EAO`qwN~X80&C?wkKwt1Fp)4xFjP^)-}=NIxvR;ge)w0!?Zhc$Rwefy%W|LNrC*&Z zyv`A%i>RBZ>X2Vlcm4JKHLVsKsAs?gFp!wcc=6g_>o*vaZd&pTv!AWqC;vwWS+m z`Q=EF+%A*!PpbzX@m^8=WV97mMA_ zE9XF7I5l@_?B@<1glU^Yo5g{(EGfl2=Mw}UW8tUrs#^VwF^AlapvBrP#ut~d7-}smR6lr!N^PPB<=zn_m2g{Fp#?3i^g7Py!mxfD z42m@U%5LTT3gVK`jTcksl$~cKY*k5ZC2Rf9Fl^^V560IoR6$ z{A}Jm9gsAL3L|Pu?eQ4Wc^dNwup)>!Wj%kjC0!mJ1TcTp{+rl!I9sDHo@1>O+0ldf z)07FKr|ox?#`)0>Kf0#|xl144pE5qOg)cpF=cvYsO^4#lO-4bsI|}j`Vhof5>xEjT zdaj-kW)wIM>dttnY2WZo+E{BQ{+6Lj7ffWRh4j)T3@N;Ls8w&%Hat@zRMrqXDBhlj z8Q}qi^@Xvt$NVVF=Y+K(olvD}+OOvUmB?*eu|Bz$NJSh(m{{W&?eE0je|iro|9|4|pGn!@ zz~BF#RPDdx?`y`sh^Nl2PV+@?k(G6uI-X-4Y`vpXD2Sz)tZ*m@js)G6x~l5G=vTT(v1{4)1g>_AbWhOwP~=W(pW=!I}MN2mC!)L-7B zK~D(v5f%DSEhd48ywCE_O0QDS^A)CGRB}zqSHUG$2X=+kyKjQXUHoxugFrz|DsYA)(R-&HN8BaFVN9FECeSWOB3dQ!fDbefX z+h0?@<=EfOqbgC3Pd@d0%4fg*`TVGyzSP|*-~Q)KDRL}Y4TU|l8rI$~dJKoGy+fkV z+LaRZTiZ+&6-f_uz5^#982Ysh2T||ro^al^;k;tQ*-a>r$)nRYKV#~ zyV`e*7X_pEwqh(Q5`~=Sw?@>cHQn9z{myQ+)k&#qlVL-d9=%zhJmP%QefjYlwD_s9 zQEBo1z=D%73USY#Qs3G+hqyUkbA zi%;)*LzwQ3e7Gae%u?~qR&d~!$AAf2f|-wnuduC8V5qS$#@;nE5nnKHU- zk_sJ}Btbm@Iw9LAbl4=4O(2Qj|IyK3OBp|v;!)7hwbRYN>vgGJHWWfwt8s*zZnmpa z=vF7KN?l2+jHjMx21fKw0dxdklT&P}{rPJ7ET$yX7e{+PpJ{(y#upjot0cwSDJhP$ zQwX~xdY62DCgt;&uj%52SrYxNe7-&9^Iz=GvOEZ)@0Jvor=)n66!x6GfcG|*Y1Tcw zM$x9xUeUIyYG^mTqIp@Se}ZVYS*GR$KGDmi?UTcipJmpuD&=2Houy{#f4}D``6OL( zR>L#|5nwN}2)_5PQs4g){zdqd@Fl?^yL!=ETmB^#cki#@SA5coSkOef)@TTK^cPt> ztE^sbCFnV7bG%K6wKdEU8HOu))uy>gBAs!u{JLa1k}B#aJj&^9Z_y@EeyFg^O)Lmt zye+XHgv$l{L!tRFFOZlQOw7Y;y7_RlsVS$D#su=eO~C{n@jMDYq8Fhh|3f49+6MM> zJ$CpJN@J(L-Zk(o?pibp@!i@#TlkDhzY2B4aG0qp|Vv9;|5q0XB zSJ)zOZU=Ab=fxs9fNiGi=x37lT+$-vq8I%-b-g6)FEawYwQM}(wzOM2n)*E}^D6qe zq(7SU$f-nTF@NgR1(JT4ogRp~^sm^)%owXvB_yCgIa|0#Dywv&aB)gQ=7gbdkta{& z1;%j2uwR|a5{jt59qMd~mq#rUX)nE!$dl$-H_epUEjyd~H;VX^G0TKUQ}*E-WcFEM zy(McFQZIeJ1qOx~!@TnQl325Pf}9H7gOC}J;JXeM@n`DeYrr$Q8JuQ6f+`;_6pwwY z2w!NO$28#)F7T45RbOmf65_1V=N;tkOuM;zHQ)CJ3cx&*b*`t~O^5Jlk6OT|#>6GF z1+mQTg$i5g_y~JAC4Xf~B4<7^Uj{$l^S;TW|C4oRIp%p7ks)sM%5jIyw;<#TSA zJ@Ys`bFFSG`nd8CaiirU^A*lw^1k_Slgpfs`YxX}IFtV8f2!1{)W(Q>hHa_Owk6qI zk-!&GY43CDgByfgXQH9Jv4=Q;b8w@)yx#4VUSyKw+G2{CO7uTQe$>%FLU~9Bbd*H` zjG4qG)z&zv)U&c~jH=H>LOt6v^hyq~`>T7@rLpmox^7t~3jKX^rjhl>^LbW#YHuAN7^CK8HE83VSE6-RiteLik zkQ|PM4d2iwhVx3n?c8-zTg19R~*$YxB`9p4xzqMld(RG160{LwkybWps&W60&}He(C%6)bscQDrJA@@JpX|_CvT+PXXB) zWCHI|r%{G9Uave(4|_W9CqwOKZm~RzPio(u@tkM4m+sCKIt)JX5j{hVfG#FBd3XDHm}dvm!$v1JH~Q2UhEj@AEkd3FFvumX{gxU zlZ9Q|0GtATT_G>WVa|Fd?*z$vm3UPQTbVzw{MPrWcYnxj^^$Vm{OTH}#>kJf{XG0@%4A5L3ixaV zjdkedo;6cX1HhzjlwI~*8&ti3>hQOns|WJr^107Ub9Vw~w?zRS_n!MPC5<4EYq~MS@k2Q=J|)a8ey2shImtD*qS+dXhptnOaCg(oYU>XuEN#U_4;<6nD%- z)Qbl>NMmsZ}ED4;pC4F52Cn%Ex z>hosG(=M^(a;tKBQkF!seq&YjkY?RC2tLiN@bh|kUznVj5p|(cjAbg#@-BTbDkarfZYopfX?>+S+)c%4 zCV_DW2U3r*z9(eH`lgb4L8WTGDi!mop0n*4s@F4Ej`*`G4Xx1)iFzAyhXKm=GgWq2 zY*Am7{9d6JIfcqnKh(Nx1ULEs!}X^YFbMdSyl0&do%4;4frd(U=uSCPBA|>^-pb(qMxn zt7NK8N%l^2UouT7k zxBSQh!5${=U%8ht6X4Xv%vcel?`hs5Y6@tVk-9J}D;tJgZEwaU8GqU#*Dj5j3cm*! zYwbZHo6S}HRXRK2i5M)qefhW)-0)3q|d1~@h z!Bug8rV{naON@)LfV-4+Er8@`gh(Pya6SuCS^w0IEBR{Qj~t}$N3{FE|4>-Z+Yqhq zRNjjojqi#8M=n0G*ZvxJntFw>BAM~e(>mnplYgEev>7Am(kvO3&kLbCYGHNLdC@n1 z!w#!2NX2l+V=(J%IB_h0q@J0saRF3J9d$)@6L*r?qWuwxE{X%g&rJ$uJR<5+V8l0M zLX||Nav`;r7g9@6mc9Cwbgg&sV2w6zAuJgCR`&2$om*M=MrW!!vd$+2U_)b72Mv9cA7jVjXw6yGHG-l^|5B0G$7eK z?9YLwa=RN+NymVj$}9u@tohOhd!w7A)laZzI83HGwXa=QOCwI*#wU%ksyg*o{ecs< zt<=GIWE_eYL5TiZB;VT#T7V|hdAJrGfTQ0LIH7dTVvgBhA%~;wk_Ouc>c_xFVI9<%nDTt ziXAZ;Sr5un&cCMMN{cFSXuUH0bynP* z3Q`XLT-R)h)QpsVsP*|l{SgJKDs}4RdUm4=rc0@@z8b#2rcQmxT~$q8mG}a=6cr6} z=F-mmN{XpcUoDh8Sxz3Cp07oP>;KNaz+X9LJ33q=aS&^5*46RSf z4%LU44BJ_ZLMn_C5(Ij-sd0?*j{e1~gqbwex(a*lOwBB5Fm~OAojR*uRP?9o)KSb- zXb{@3MKr%e(Gg7?SVb(g>GA}jGDEmO)1}Uh!Vfx-CcTX@nVMyqFz!VSUGHZ#ZAS`LRPL=O!xdvL%i$@FT5*!4~Mp7kx?v%l$kKhCW=y%MCr53NTmJY{)* z83H}!h2@8e$E@CuyCX=oZ|knhOqGxn{PuU6gabF5tdJEDSyoLFR5>((my>;Hw}^ZT z$u@qfb-9>^vQGvcs_s8uJ4raH!Ah7AO63*3X1=#u@R1M0H;mqdg+G^??m;)*X7$H| znDE1pOFdc>J(8&^*m%CD$8GgcyNfcGJwyLGZOT~oko?j|BezYpo(h+`6{by>IS00s zqssT(Bz?E(>#yuK>oyG&d<$V=+SK3`5r4x?xmoQPLcJK4qe`(+1|AJIqKynbJ^nQe z;k3k&cg(cUIGXb!njE^TjOG#a()d1DEI%`a>0=+&>7^}H<|aV;GkBLMhE%9i?UyOT z>E-4#BTNlhbuo1IGzg9F&&g;JDZzNZiK5dT?^iBS^O<8L9eyqz*me2&Xio~-SO_6dHtTx;kC7I-9OPz`S<#O&;LV7+E#}cejxt2 z|8B`Y|EQ-WRs4nSwnhGFxKml0o=gVtzMSI3zCyZP+1bYUD~*5x$X1vjjRt6Adf z`VE^?pmQbQouygFcgf7xjK0{1$O;URlC49fWfj&CsbghDBs!H((K*lI9bo28z278p zB>kl)LysfM2VW#-gXVH^!O}-ht#OmtWVGG8>^#m8KM?$7Zbrl4=^OquH(3h&zN&JX zn-msL#Z*&)1C<|eQ-5RmfBD=&!?%|IsGGE6Y8$LO-#P^rDBr^$A3Q6kR*jNzutBs# znJ*pwVuo+BKagt+umtX5`{KPA46A=ty3Dz7m4VE_Jj0CZrjrn)3+6N(XAc~-@8TzW z$Fm-Lu~6rm5C#!71W-xQLOp&ge|%R+mRwnH_0baYU7da+2ld?;Idi+gdaKbt!BV=Y9Avr4$~?a;IiXZ;0XCnI*N5bY!pM)78qSW|70(4=d}U8P5o3Vf_zu;tv=v4&9e@x(F*(- ze_C&y8%~sFT8D{ZKJHe$2Q%efL{_Nl_uFIXBdZQ>2>ve-if3))qCq#wL(LYwXg3M} zUSiHc)Ru2aZou2v9AHW z$g8Ru8J8Np$VRsBMz?EqLEi+weV@B~d;@&W7~cS2=4YAhV(2)=gfOV`puL6}zLI7a z=)-Fs?4l1-X#uGqSEpDM4q<8(wMDd`A@nqrq!Dp%$GZ0d)=GKLG-#H%>95*JrHI?Cmfot*r^ zcDi+F`>qMx4vR&u)$%C%Vtqi9PXbM1prLL%UOK<~29aWE6j|Tk0Tn=@to0T5O}J~~ zBpDWVU1G^>@hb!)!P-Ihz=2Hv8(yL`uYmr;N|S2BwWF~?<*fWRei=W_R~7ouL12{n zYr9uU9qenGd4wBu(mgLzSzKJyE`atecQc1qjvN(BjupB^6r++ zO#@Jxm-W<|FFJlbHnYP%wFl~6t2PvU__snXRAR40zf8SOfgfGt4ta-=^w3;eKd~V} zndl)un|t%2TJX6Bslpf%JcFrMsL|$f+cOi!Q;&&xje&BYi5WX|DYKGkGo+z$+UhUw z)^2`io1W;s!4>udmpaV_nx5nu+OBVd_Tk4pW_539dP-|(@4C>g3bD?n^4L}xNL-b= zn%LBZv&|g4WiLCq<6j+|am@#ejPBe&6dX1hlP1$vw>ux@$HU$q_jrHY;{9>0_eZn$ zN6h;p>isd*`=i?Xqul$W*!v^j`y<=?Bk29{B|}YLBS;gJ^P?vEE|1Y_h%@zq7RCz6 zcloUouRML&Xy4g{2w@sw7GVKl8R2@uorK>LRueW74gq5lUgP<1gk6Ns2>p2{_FZKM z?0w6S_Mg;#X7SWRIT)#BC@*9vYad?1%wX~Rx@18^tfH+9|87TTTq9DJc!PO3YqWTS zxrL~4^)2^s{FJnftFKKyE=oSmNj}a{~E0cKp(>n}HuYgg5Z8noew7 zUF;-kT%DhM%yAw`2pc~3z1nCduc9*qvr$bpg&J4OFH^6Olfmj%;O1k(*Mx!8Ka+4V z!RPOn)-U-lJ^84g0teVHX3c;O`uM57b_s3V>W3(oepmZb2ilLShsF-(n9K6*H7(_8 z)925sSC{o!18rey9tk07#oP#tvOye1_Zn~y#0b@SD=*X`=xD7aW&{dCR8h(POPEIXZ1&b9;f z9aaxLD>rp$IBi1!ti&dU>XVmjqJJ5`0s*{CeK%%l1acu_0%O_Z^SY6Eg{rF8Mi51XgXIW!rAEI z(({X526>~R)lCECCVf;S8iW2c*OWqcu9XX(X~>bskp;>a#8z1Gd=X?VcpG5B&#eqA+yBYC9%2gy2L<%JL)f zS~BvZqKzmui%EG9!=Y9xPlBOUV$dB;cxwk%;jcss5B<|&)(dS5{VOmg=U=v^X&-%; zJ-kCK7Tm%G0V5MG#wk4$4eu!0I6upJL5gpS_^oa?`|uYmMQ>$V6JnOXiXkjTHQmho zNA4-3MMU1IXSUTrHgBd^RzJipfF7HzU!453spyrtGkYc9Z6}ZTjlNhi{R_i)r^j-$ zpBHdX51=?PbKjIp1@Kr73ZmI?n7b=WIIU+`K1}s922&~hAJS0L#o z*%p;R%UdR_XcIHtcFesUqqpOt{_}66-r(y4yql#{=D%4G#W{@>6SxoE1MuUufh6szqG0e70^+J?m{F<<4aYDXy1vO(J zbsaCePy5&L{ow^i;U@Bf9HBc}-X&srK^odurOuYLJ6xDeN5~9@dEe5$AftK7B45+M zjh!)l=T@`RSDR8=fie3vYRR+oP6Cae6$B z(UqKUC;S@zo@u`%=(GL*blM;KA89|DTs`V@5?MX z?=;_$EUgY;n3LU9Hmn<@9Ja>abc$9N1d1)Z+_lIWW`C19=rv4B71@%_eOBNKZw0vO zA1!N|rvm4BDlm`=3`HV>3h0JP1-i0nqfs(oWM#CBVFoVS`K(;MeWUXft=(*m% zz-6?@Bm!HL$TKC^_l~wPVShxO@dUG8kuom#agM!*s_5e^`!y0~{;|wXdBL^OInKoP;A4V; zv(u_APE^fKGCU~HyAK>|($TS6wp=q_ddZr7`46}IqgF+6O`+6R)u2r%zUA1CK|70U3WT4a>FO%fJSRcsnZj<+n_tE?h_(676lO+792Sso_(ryb zjBBRAQpk96Wq7!33pamq(r9!tD7MBfR^w{)3kPSlJW#F7WTdI+J zfNJRWlTFPPK=ryA)dHweP3H|6!Ph^rXKypn@*>fRq?wgI%imcdH80jVu+sz%f8dn( z%?&pg_e+5zbj?kH|GwWT@PEY0zP4488;LH98zHrPT+OQ&NfgaCrAmXVV=Ym7iEq3E7rIc^) zRnxd!DSSV3whrM7!KT|Sg9Ogmv)yK4twS2|@qNBWqR`*<5wx^R3-*keLgDW7UfNiPkaE~uKX z3onnp>wuOTT_9<{y}^10ji~54BV`chn#|uah-IdZh^W24OZTmTr2+;rt*uMnXMQzb z-fw(-%a^515P@;1Air>jqc7_U+Vf-`nQFCrFlZ>5d(!lWc*&UM4c-wrV|IzBk}Q4w z`}%t=o8YKt$2k1Gq{TASWXvf!#x+EDwAR}AeY@=P_~tK5l4Wxoh(6~ar?x_kr5H%9 ze3_s4=-cR5>437A6sbx+hW3upRml_rkBY?C`QxAENR=|KzKCA69?xy2!QwRhcpO)UgzrVk)zx)gIa|k;VbJoIMXTKhdjvvhmtDEoDt1`!lV`Rq}k4Q+U zqeME%hntoT-~FJ&VT3qr9%Lef{`C4YgI&?vzvF-5&rINX{YCZ(FZ6%yFH-0mjM$=U ze{cknN*g7V15i^{vCoaUt2l%wz2*lvf}Y0 znEbJ+B;UWOmQQ^En%1m0!Y^e^ z{8#d+gYP=9eCh$}Ursqwg^^kXnTYymFg9`4kqBFtOoJE08cfylwVk0@Zr&!5)l-lC zhxTxlCY;H92+FDI)lX^6#1h?@d}+*x{Zp}|`R?NZpJtxUwv;+kEN+eUNlCaHS{&@k z(hjQlCCtjfjF8zyTQP3m^t0xxPWD+%0Tx3%8J!&%6%}_;3jbWdED2iY z2SyEVI#iO9e^b}MI`tf8$~Xxm(uEUX)dxoXJlHf(Cm3LDN}L_+npvk7nl${X7iUv7 zzQoX?NkJz0o~|QwxtH1HCVq@_S!Fm@$oDm6w$|s@ zZYs;i|F1B75DsO!Xx{dGD_nS9J_;a_AaU%cc8pp}xb?jJ2y@h@`pLP~&a$F5zcrHI z+K`W+S}icut$^#Augf^ZE#nO-qrY3kAqM96?4k}6pfC-suc@^)AJHrk*~AK-uE;PF zyCoO7fRY9Kbh(%DrL{31D=Ol>aZ$UiU>>QP+a; zwzPD6dV8d@LUlhtx^YInS>)!Xp$Z;ajdKZ<+ifUU1&8mK4|q;U{qlc^dl&eqs%w9I zCYgjFqcg}TQKRP8(WWJ8G|>hVYY<4HgfK}+f<+Q+X*wcBgb5D?3`{~9j$^5?UcHOCHfRK_yV5xc z-g;D%E}GsX+TD=!pR-n?R-8`Tuv%t~tElATqdRejElz_~vu-Mm$I+I%UfBh28b=$? z2UhV0_&!;%%W?nR4rz3)`j+mtX*o9OvCw`^8`%uSjj(?Q|0jA)Cat?1NlGq-d^Mnc z!A4445oCrdadnoYarq;JXrw5OhLj_@Y3sSjI6VqJMpTnN>0xK%RkBOK%bbOSBUN@q zHlhSVeq#O%9qBm>aF;h;=EfU=H%0P0bQnSJK&sNI!}u3AO2NmC>!l~84`WYp)2BUi z%>eoie+r@*EPu7O1fEB^`{8>8vgfwX;(!Xgu8$`gA6R*rp22-eA{P6!TSatvrna?K z-+bU0wnrAus?~L6;DR7gBtXCk!MwSkomAGj&>QdJj#LBz?pUr`Y#St`v-}^8f9-1n z$KN{S_#eDqkDswi)18utHJ}c)YkD{25dSCeJ-m0|_+A}yd`W|i@9ej}czi?ZcT)SKMPjmK9pPgSQ3J%j@%FodD|zw5;M zzjNJ?AaFoX^hF>TqW{@hkn-jZ+VuZ0KiCA}uizJ0?(R(8M{Fu~bruV0Qs-hnV#B#R zi!<=e5h>5?EcWvo$)?saf{uIve?}$vLO3V&kH`P*pA5~V#VFEH@W=-|&O-}0Ec;>G z{|p}Juje@Q50dX)@FD@2)PvohOO``7%;{WU#?%c23|Lr_s7PI=nRu=^JHnjLdHpGZ zsic+r4g|M!4m#ywnNKIO`Qkrw5ju-jabEh-&Wp zybmPb4GH$h`p%RPj8yoa_T9j73R~1#%g}XzE$XoIVI&~QYz(dcjjgBEzTa+tLCzO7 zx6v=n5w20!#z=w}5a9>&-F&`ekX6PY1B~3@nBe+T=y|-Y3WDA8JcM~Is=!$jshOjK zpz~V6hSSH7nJmu)>%f?fwP|Da(B*13?OSZfVaaDw=M!`KlyFTPsA~qlU<8#`|Kn1Vmy* zwghA*T*d1c-o;;y#Q?A|8|84vL^1PhSq4ty2-VwP$8EJ5wg4-6y_flrHQUH2 zZ{S+D4>qRZRZPS7%$G1E6h&-G#JP1uR6)*(ylZr!^J8cplcx;0SLH6(6Sn&a9h5=MP@M)7*si(25v5E|Ps@)CXfG z=mU1)vR_y^)e&_qr3S z_szs^hnt}2L6+ViF>W(a1Ti6k<{0K22dt+LXlo9^%C_dPt%YV=b10Ms;y^)Y?0}w0 zl=!`#m5*YTMV4sN8IM?yN&JFph$N1SWp8y^SVp~_8NWRnlxWXBG^!P9xZ20NU_WA3 zK`_ypzRCdN$B%6EFr3^utkR_x!TDTMjaVQKK0JMxTLS^*h5W+0rOt9#595K~{{n0eLJj{m~v<|4?P89g^C z$(e+I@Lz&`0?y<62Asz$4iYy&IgM_}VxgxgRLy7>o0Q?ev+&7A;PdxU248*nq~ntz zGwNuT=bTnc>r3d%0hjf77+1K*&QHuAumplZ+(L6($4;9X8ik!0{0Gke*~0>=UcW)Z zkjP4lp~f$0EIY0-c>Y5xQ?MNtN)Ru}tr&rH7I@)XPoa`(JsTK^5>=5i*e{enLor&= zZY(N{*63hU!_jNDxah(O#8Xu%10BtQqNE;pMkM12<>N>Zwg4Y}Ty`tzWAhqT*@TUMTFB~<{&m}m5kt@AHJ_(q7}s312r^yPl5ka4)+ zGhA@GZ7Hfx!R=h!8lB4;O^|d7fsH zeSFLJG>hFAETimw*^#(F?yV-WiFMR)z-}Yz_S`^G{7`lFZHd)!!Xx)MMIVbRnuf-y z$8U6DHo+P-?%U>cXug2SfG$Bk-DeI#t^CcgK4Ca$5-Q9{e!yH>bz}~zE-Hi_0F4J}Y&fv;ogTtt>*4~KkiQ^0|d(gpQWDE4j zg6i6#Mm9&ieAB-Hwx`bc_rP`+4bBFD%^I0rdiB_PG&%=-^$gSgguuJQ1fJe@>WqJ9 zlqEn< z)H(V-54`rbv_eVCJK#y?vpf7e;>-X!E4KUrKSYIv9Kmo{S_~7#N62~&!y%Y^NRFO` zHwnLxVCX3O71seA1n~xakF=VnfK~!gxe^)?Pq8T#5aqY3@A# zr#&gsux)Q?vBoEJNC^WN*!LK_ZyM}tvw2So16&xzbB^b?{t>9G9K+G|O)Nc;=1y8( zJtJ+*KFF)Z1t4aK-!t0wJ)jKYJqmq=uZj`Uc%a;6wtvK!%-gN)#yQb+z%)HAcc^=o z0z;}@vTa=VMsiG8P;XD;Qv!oF;U9x3r=jX%=k)rRQ!DSQqJgCaR=hdnD6{)*3Ofi{ z0h=+$6&;)@1l?ZhHgFr)w6RyRG@C;E<6gx72E+8ki#X%eKt)~<@Xk-kZH3%F0`tmi zyvqOMV}1Cg5XZpho%Iq@I0+d`!`s@c;x7<~s{`w;klQ2K63sU^L7;w=) z_{B{F_(i#7!<53?>AVlDTkat&Q%3Zb^xXY&a--FP9ieM6Ux6>;IwHSyfjkvrg9Ong z4sc_VVG?Lp52Mo;93@_wDj8oR>47a;_9>>V>7`wSp4;5q>A)e>DB6HIs za|eWYjtNIJ{Nntvhu5f2ekilG6cw1?VDfpSgRH3~@^wyhP~@JwAM92J*)3>j8j)BC zw_)5Ot$Fk=ID^x8=QONO8s4ND&e;gWf${geZcLsgPe$U&snN+yu9KmvY4~F4kQ&S( z$*e3rQoNCg9W6=6KVxJQ_>HGI=`Q}2e|tU@!JpWCrl6w%^RcFI*TJ|c{PHdh)i0ca z;4|ofsM!XSCx~x1@}INoLGm~M_w%F7M~g5cNQ0|vXy|~OE9RR-xq?q% zio^K6aiP9yDr!~!ot!+vd_f;vhttO$$w!KIEtt~z(svKoLjU{u(w}$#W3v0bBvFbetP%)qZ@zXV04KD%~V@s8`SAm7V$q##k@* zbrieDMd~uNzM+0~T~=gnc4ul4k59(b=8>N8AK)>#eob>FI;LctPIsx@{WZ3a^l&p< z^>NjK<7VfmmCIxU^i$A?I?x5ap1Lrj3kQ`KKTO_Co%IZa^O{W?EDiu5RU2LIq85fc zg35jiOM;UMXV!P7E=3!75Yq4h zu|@mTh51x&7DOpHv}iBzlgpAMaup!iebYrr@gTL!C$l_4nT}}c$MgIKbPgxO5S$ZN zzBrQsPT`7JZZS>|FGnNT(iLRCC_w!7aT|$SVYH_23*m}g-G06SSv_GK; zPe+bZZ=G&NjdMas99ixM);_AS_92b637g!w#t#-BH=`8E)Cd0`;}Zmuq06P3c|Kfs z_@x$K5EMq$F9XzJB~1gxK? zLfqG!DlLrgG}8`W&onUxctLy%YuUnZ-NH$*qfYiTZ$-Ue6P{z9kG~0=>QV}_Q_P$N zQasHMu|StDaHlTN87nZ-(;Q}jeY(JRb%BRKF{`ymj=&s+m50pc@>my+Ukkx05_ZgGCfeO@&*7zz_GS6`x zR|WaTlNwW-%Jb8DTulx6N1EgY|X`-)Wt zQ%jc+n{JLD@*`RbKyq{y(1_C%db1y5Tu$>bnU!sc;8{hzk9N5}o#DrzY!Jnd<#OE_ zH>wSf+Soi5f(gm+T&_*|w14)lxWa49!rRo^7dQnb1OVvbXYd`Xh&=-x2g`KOHXT+l z1JX5hhB*V$sd!t8g(o=rPkw8T9x9O(SW@aJL*g(VKkmI|F$(R|D^=AF48BWc+^9RX zG@0|iPsoy5sud6w6S4-!MFiR}2()ndi>Y{GO4 z+lh2XTpyFoCd@^+NKbMDd~ii9LC;u;93nzeD41YNBB(ACKKwmB;r*N$U}8^L@9Qmi zyq3JakqU_^KJX}7tHs5v%vA@3*vM$7Imok&M=!W=ljxs3DW%)`o81O zm*=^1nDdR8^R*Cgsca0(A4Fmc+W4pUYdreBwLZ2zMq+yi{tevLPn*TIanA-+9?o@a zk3YVzO`&Y`lkFjF$~RZ()%Yz(7c+tKthyHu^ayA9u})t^e6ENaUoz6t53zkmS>sdN z5Ievq%^XN}4nyTZ1ePfX;mnNRI-Zp`1DoLOhVT`3Bt0>&Vm5(q;o_{hN%M9RRSeA^nz*z2Y?j#7Vl7G4*NOPQqNbo%d93Il8DQRhF& zVIp4zxTWlOFgZd~_qlNLfS%&GkiLh_r8NRm!=I*xh8Mg6;{EA}#^IDVt4vObv;+ED zoE*LLpN?;Ninb5eQn#HJJMk?=8X4D}BSxx}$#JG_TG5yWlf&bR@4?lF`)8As2 z-KK73P@E|+j%-YMPFxhd!e{v+B>{rNIv71GaT3W<1k{umm*t{Qv=Xsc@QFjunbvrS zKayiChCj`t2jGwFfvhVTAZY%$fzV?EI%O8JtIVR)s+C`*LLK=f$rSd!Y@ABF0Qh?> z0^(objx2Y&WXXWIQ?-1IxpalweBIQe*=A8A7`Z}id>U7W?^5{)PRP}$ALc%ThttBn z013C3`gk{fmxg;s%C8hwxk6p^Thc@Xd0>f(J$QD3x;6gUi+pyfI(Qdbczyj=4A0aOW!#S7FioZee{<03&Uz~es1#QdX^2a2B z*lBaz_$vp>*HV1d{M}=HxqV|_qJc+b`7Felk1StoGRw&40RMcr{@IEvbpOkz5D&@?VUFf-Y>|V-NZ7a=P!By| zoh1-GJjBy@{_R||#?#>JQ}TEDdJ>Xw!)DD5Au3XAKYl4MtXhGpAOR$51znQE2Hf>l_R47!2-8AurXJxU=n^F0aW_J0HAbexVY z8Hu8a`|s}$gSpE&aZmFtAdNwU!E>lGG-eO|`)q6cwD6X6*a$#0N0qASDi8ehwY1@3 zW@w_Z8$;3#^Jo7KsBu^)TW*EJ{8vy8UhCVH3on8j^nex4irB=yicT;qGJ3WTym$UO zJ)9R&R1YVqS~*ZMxRIlL7>|vr>#f|;)#}gJ;T6NFD}%2l&5S|#6})1u<>&eKyHash ztm31rxQVYSrD8Bv@dteM0$+ViYR!q&S}1K!4bqH3ogo$H#VSr?#h3W%7>)&_Dio`D zrBuup4p!sJeiV@z)>f-?@zz?q^u)D$|L1XQw~_e!6wDGpSgH}s3=YPmG1mgl_rac$ zqO*lp;>Y*#!2T^;&*QD}Wa|%yvc_VbTqph$mwRfyW@wln1~<&wXyHuUwdayAylUpI2i`|9bllk7{x?W{;1(=;fZ|1M5cv0FmC zdaxkouYUXsM75$1LquD>og>~=oH(*xXHV43X3yg>sLIN>;1&6#r zf*AA#{H)~JFd#;FeE+x|gUv}@bQR+Fh2|lKan|}$2N-~jndV=g`8Un{>oEWR;}Ko% zp#B>O?!%YhVut!%wuJC?Z{!a&wKfy&X5o{APd+|H_>|%kz({J5@N;`!lDuoQ~90Aau25}Mswx7hGv zzZ2$0rP&2<&L3_B@{{)zyfq&Y(M%kW#d-}v{NZ=39pDDG$4m@%dt;~h!EK+WL#j!C z^WWFm>=5h}Vbv-T*VAfBCV>3}jgt&8!yI6t*n`f2eW%DPG$qV)^+$XS zK7{yG4EmFf*iqSacyPZwfTcgfD4oeC>##hq`G=`_btTet;7MLZ|8I z^oMq1F4RP00oBAuK^973JgLG8HP>z|1=Y}4rJ8OwHk0L2%~=+++-ip9N<~F9R-tnF zXc`L*GpG3YU| z11)ACGTN@|QN0-3KD@;z*1Rq|h#Rcq5dGtotzk~<-y__!>7S-tC4m11B#MAJW zEKp0@l8(Z>FkLDHM&qgnBjtGv{^V2JPz>!LFx^gdHUNZ&3_Kh}p+5BjA%^f}#M(j9 zYvO(++4)kTtw%}~fo3x-7aY|=>KWAxoN_pTGWFSj6p#0n;|RhukaH7#WT1?_2>*#o z0?f@2kIE9r2I=R3e4C@uirvCD*ur=}mk|*NFeg{=VHWFEhjCH~yD1l%OIhx=tl%Sf zsot<&$xUjsyvh!)=d0%vUj1t_YvqKuObz~;Z|_TZ`!?PNf5Yd^cy3I}i!tTxd_~!& zx{S3iTG;b3T|)*sXMKs9*~iXqc` zR%I;`^?@~`DM_Z__7l+lGu9Lm)4@T7T18mQ)I+m)jh~vu8~jHlU}i_L&(Sy*y(RbW z4G8N9or&K5Qg;jiK)n59)zhSyP){2&{m84vxI#%3dt~34t^SFw3m<$4XDnhd?fIbT zJ?D|P&fMGd-nC7eFI;`vukd`$xI({EN=`z_hw-E% zF8i1+R#@_TyY3(qnOV?9<6SdZ|*Y}kR|SQNJ?L`UYnZyZJT3!P=# zbRxf<9yeaqIYTR@;6qiUN$$dN)s{X&_%9b0$qeNV+_6Ks`=}ef<^@|fOvaBitapCr z44p~^^#UMXzJU7DkFlCy$S7_U7Oym3-q^Gli+C>BiBu?wOS72p?i+3<>Na2ngWaY6 zbT_I`fTK5>06w{6UA-C!r>&r!W&V7YMcmxDxe7pI@UPj^8_g5XUZ%qJeM^8J zp9)vX_ly6<)Y_o%RSm|O4U7Pm#0X#?Ap+PUGXhwZ7Et~f&W)Z89PaM$fnm||X$ZtR z&fE4uGF;6^)<$o27WCFPj_^D?4$hVflUHAtRjKB;AM0DQoms8YydA5cL321I0++@E z>)-#?e5<#Y{$J!P1__RqI^Gm61nDLiz()lIT3{x|Zi zwnH68kBEW!R=X+woB)e4yp7Md+LkORWaUn^@~z&AhRl4ceY7W?5T9=~Ds|%Wty=5b zfFSmgcNIsDPN+K!v~|qpJ-uYbnNJt{0oKcKSlHGxjDUJ&&nJ>j_jWs-?)}B~@>(U# zY`WWlT~;<-mhYcUH@^6Sk!CVo3;@Y=L57e^H$cgsx~r<+%3@1pJFFzSZS?~d^>;Ah zkwx9}iO!(=Gn7eKQR%r0uRqa-bsv0_jU+7S;^QUI-Sa8)=Uyc=B7H%z&Ye4q-Nvou zo=?rxx##f3AWO-3w!pIfOZhU^&s@q`pY~tMr=(8YQkwKbr$*NKb1e{J4c+i!`*J_X z0yJPgy_I8nYw3e?7^Khg2)K~rNA}!3pCEZ|X4H2plINbm} zVESe*y6p<_q-er~_47sxZ*7QN+z?(x?T?eZu;nBq{Uq+X;r9Sfj?}*^qr})OD*~2C-Blsp-EA zXR`2kS2Q~aAhfi`)(bQ#ZoPJ@4`uVa8sIHWTR4oQAtF34!dP#0(wRvv@VNhE@%{s@ z2$^X+R@{ZbI?Y5C9joM*mA3-$YFgrh3>$f*Z%J=C5*jVg_;0(L5=ZJZST191v@GsR6;fU+^zVK~+r>A8FUNqeXUidb6VqK%Z&NCKpbT{hJebd4_ z2vcfc0*wT58V|8MDKyWPVu^?to#HHLW5^lOg~biAVTSXa2pNN*j=04aTw53#1B~oh zBe#i(j&KLVP5_Yvu!lV>%K=#I4%1))-yi_AO(!(H68-80p8)T6s+X~14a8br!kh2L z%&;mFY6tOYh{T=^t%$e->Jzz>$P8vLx;&>g@?&}ws}Bt{BCht8rbXZs;oHCCKbqUu zF!m)ju<+`tYV38fR`hK6yJfIAOw1%>NW5J=LwXA=a|IhB`Iuuvfz+SB6*QVMMoVA= ze)zWo_+c)h%&WW?L&C|`(n_V?Cf*OAhL$_a>U9s{SNBiwPeFSlya6e0wZjBxIj>k% z43hAuq{Wm{ub#GyI_0FsDg+w{eU&Yjx`X#qMuCLDnYtLL6S+{EGxb6=CU645bddvY z9FB^s*HLrA=T3z6b*-K@0hc6X4hM4YQqTUrudi0^6wRV5ygc2py3W^_g`mt1xwe5P zpocGFeIiyTl6BK=mbZD{s^}Q8FnxBKdSjAMDjc&XV>tdu5WzhSg`$Tn{Od!6q~&R2 zK0$297`2EwN7@8NeG6-Yh%DH#h^~WphFNj42+mG0OaC+Y`Y>khC+dkKPDj)2K8L4y zELO%SNhj7xkV^*a^)#Qyr$yK+WXdxbQ}VDUe6kcJoRQ_H+KlQ@4-cDN2*3I^8Lq?O zuR9wVbPBt;f^j>BTE?cZxr`k}%N*gaCpBg_fErLR18J8NHXCm*@E}o8!AHC~RAd#rB{zqF%HLq!9A->UlS^(| zeH?aKqFz}5$b%rm`GjFq;5VqQMAFIpdY`BH8vx_j`V3EV1-?|jh<`xW7BP+rKVDGh z3~gUT8t-WqsFT3AeUcQN*jLcz34e+z95F9EakrgOa@lDdY2I~)lYPZ~2iiS+sZ>j! z#n>Hdwm;7vUwaR$)V#Z~(T?qDQARV|)=stb2CV3ES4&@vK6U~Vc)2KOCxL`{nyO_X zLCEx|YYj-F*YI7z{-|JX=V`-;@vexM%r&N$(S1I^K6IzU*d9)QR6>9(RU?X0m(@(S zA|ry9GmC&is47jdjW z>AZEw=xd}xNPyr#kmz4bJg%StR1=m3w(2f&aRs=?dsdx}mE!r0Cq4kPI{?t>2sEAz zKVb3X4>%dVx(u)Ay3ukBk98TFqGCIG#W2aGliQny)A1hqhi}*W@rY(Csp3AF*Z;oC zS?D~YC(YVO9J8lI%qmlL&Y%Et1}(Udvna`CQa5ce>kR};e+^okT%~@5wv8!BDFlhF zSeGJ?jB&G0Hw5fO^JD%9HIzHK9kcf8`RifKl1ILU)=-k$2?64OpI22h@YqvLDXXgzgU<(W>I$3bx~}r$sZy93|5O$Vp%Qx;*vZFZq127IVs05 zm+4MC!)Q_)zs3x>0$@MXW_r3zuiJF{1c`_i8e?oXUW-i0i`3?WdBE;TgJ#p)Zq()@ z6ardQe}oYaa+wfYup=0Hz-JeiqQZ}h#%}Xr%%Ql*r~$vjvo=tP(wUX&q;vZa1=oip zHvnFGWNwzH8Eb`&!iS_q`s!;ePvusBIS{P*FtHe8wKqnx43S{PKGK-}W3x;g?|?wRgJF8S z)nV!~jp=>t$k>JW&BKhj*+yL!b6x!r>y(b02gz{BO!oE>5Gr!>Ok=e6#W)S6k+X1C zY&d&R0O`Z*;kB6@LjO z%Yh%6NY9A1+oe+fjl;A3HejUmL)WtvJYP@H80OoRq)f3WN~r3e9pJRMa5g!6g=Mbzh4L%pFjI@Et)&~X}_qN;%U0}2ESQBkyF z6i2=yRgkk~DfLg(=FCEX>1S9j+w34jUDJb74qK|!EXp8UMO0O-X4wqg=2T{1sZ@

FDy)Ul*jS}pU3W+zpsGAWoRt%~A^O1+}lNtNnSmUZY>C!p1&fI3$S=bM_O zWb{9aZKSbeF9=l?>V{?~SE?i900xk%QtHAj<&qvRh{Ha-4IU(6OG1SJD{N(j;vzGN zj2*ki*?FnCk-v}nbP~>_W?zXp_1RLi$WWI`C%X8@DDkk}S3bqL0*vnpYI(Df) zdjXZ8>E;F`wobtMOuvdK#Vj@~vid$hS>O35V>#iJlRZW57&<=>78nbu(<)#Qv5@KA z_v7fPN2(iY`l#*9S2v+ObdyJI=fzliJk0BC_TP^Jps{^wJDwSL_}AfgOy#*^3xAX3 z%z6M{n6=_#P#r73?TUl<%u)xZQW!Y@dux?m975_ovkgMhBuTSJ+odreVM zcuN|sBX^-Pk45@xXniyT7*=b3*z^~|Fuk~NEW_wL8zw_BeZ4e^k+-5Y|5NW`XaN;M z>kutsqk1ci9qJFb*FqzXtCM=*GMEieC+$-Y^J_AQ7r08*U5FX)QV+7ayzTlL>BE;~ z$ahGi=Srh#c&W8X!LwH!Cwe zA?zG3-A0}XL&%)ZNPl_By9>axEJ}LPiC_5$#ZrtdP&#&=zwt_Z$wuMy`Dw|U@i$}P z#m(D7S7FbU8ne|0*>g#2D)WX+5;X7{9{sEFgHddFP_=? zoB@}o5*$}618<%I@RCOy3IE2sC?e6W4C3kdC;lY=XeNxYq!MQC)lErwkCgYYp^MMn z^Xrg#t%cdX10`TD;8BI7Qb03r>6rorw&|d}6@1iu^EG zllg>=uO}TGOX8dK`KJ>m#yKSU1hy1?361Ov)>d^n7)&TV}kxva151Ux-`gOOTPkIu{bkb-Wn$ zoNi3?<6Ne3QHDgNoS+^(6{E+XjbsWhw_D@KhF&>NqXs-%Bq-kv2~#;$A$!(gr12cFY!s3#>(7ru-$X z1~d@zeJp@_3E3_YRqqHmX;}VQwC*}kDv|G3!{2i>Bw1K5>c>H)AfP!1Z*vdzq-uQS zb5Aoh0>(U%67=w^mJ%G`S8MH*C%hZK6V^|e+!>3<1AD)_2yjEp&Eq!n zsBXsaJsEX98L8E&&CL2diEvQe_@0v%=8ROEp)zQZ4Z;g15cor|+QRQAv1zE$!>Jxy z6L1Py*tvQeTl_-!U?H4JutuP3>P$4>w268L02&wq-w@jUWvU+(LcD{+0lN(=NK~B~ zy^Xm>?H%_oE`VH4Hyp7*HB1=bm}q;Kdh<^hatZY_KqOBy4^X2j7@aiD=rG=tv>A?dm@y?m1+z=d)m?cuxaPrI zO5}9l^4q$T5dhB{t#B6XZamrZEan8O1Q!^zQu4lj^$kn$N5 zVXx8%f4p{HeHT?~q34+I+2Dvk9~xI(@O`^l@=hGSXMce5q?e;&^pX}hpqIpV9t62Z z%rkN#?-SM_{q88!^$-*ZapB#M3@X5!A&x#k^V*U(Q>6nAHDe9NN_rQm@~v^$LUgM1 zn|DJM>uI5hW`F7)(+$7)Wh^#OU3lGS-gD41%0a+*yM>Yq43~5`5RncPs_(Njih^-s zm&l|*$)|Pag$Z)YUdpN(BEd|nAsVn}(`qEvPPY2%+tLoQTx8#hgMe$)(=hZP)Ab;k z2!a8ah8YZ1SxMm{Iy`Pi%gv5B+=fmU98u)_vBMIWHtn93NaaT{X+99#i>c;SL??OG z+Pj2=fo@%przQEOkuF$uqqptv$?J!OlEKZ4UG80g^n6s#jbBsa*T`U>sVQ;<)7nFj zVW)cYYe0tnuX`7!fl*Q4z5E!n3?dfscJ<*q)V|6#G~^<%U6p@=6Z23q~qF&&%TEaIMw|Bshq?SJ8Ec7gyK<%m~w!E<;X-w`RFAaYCN#+>MFF%!h{oB(XEANj#Cn(I*YbH|5(P;2Am zfM3NMXs8ykP~FlgvdXEt?}Bjwkq*NTHY zq^ZXN*A8lsuKxKZR5^!m_G@Z{An>{SBhUD^pcv>H8FMlQ{+g(kTtHscg;&C!tLIWQ z`##Tnnxq~vpOl(UlGWXK0#xuBPCR0(kYt-weVjZWN#6*g)DL^aK*$&FP6^TSzO?6L zv&SB~C(Kimhgt3L9)znCYz|&V5elNz+A?y_kg4N`kwx(rr7CK;2NA4~cs4A{H1@^s zwwy5?@!L8_dG`b000GdDn=_+jZ$rej+_RzAszs`j*^jDZscp}FSA=GwwQCSNeu55JZ$SI+d`Smmn!h+Ab&I+F3c ztTE@Cd!zwk8SldJxrbf`5kkOp`xMF?BapL0zGtf8Y>AL_jcJI?%LID@Tn=w_H9+I# zoxcUs@L?g-5#1gBFn0ifKou!edf+Y8+o?`Md<1}!Stz)XlGPbrxydmJ1s^1-G(NC% zQ1F>k{ezoeKcl!$yTYQi*)du>-h6n6pOnEChEWoiNO9?J3uC#hZ-5Yqv0NdA5;|7M zT3Rc_3pFmm{m+zVz!G}g0lwBTJ7B}mrM&RSNEB)8vHjvK5(fINO4*tA=bK{s^Ie5& zcO!x_#7j`LJTu;(?{RaKFZvvxTG{&h2U#aqdHJXw>-ygIjKfH&bk;zDTa|(Q0kq(V!Di3 z6~~u~pcIBVaITzo1+vECywTAYYhazRh6)6n^hd`qnY^nm^jqf*vmt5`u3v8JyzRKH|I3!*Ihs5{S!y)m$$4VXT8`sLe&GPSJ z`FD=|J5&ChCjXZ4U%>E5RNH{hi}WDr&TCt9QuDUPw_*`AjB!Dl z0$t;#J%R1~TcIARH-(_Ndm#o*^89G?n$6sqLzNFDlpkT2C%*&+0;wi+JgoST{zYb; zZN`!y3{+BxG3}JE4mO}sRtI9aq)+cb#(l8P9Cy9ZRoDGD9Eila*njXhp!;j%9!*au zFrOADF+K!=vAuxb{only4g~L8ByCaCKqh zH#F56*iIbCFR_LWQneKW$3zE)?QxrhkeVu5?1SE_OtMp*ZIlO*m#d(nu<=wrhnQ#n zchN+bngk7o5IqXbt*KIQj`OsyeulBLZhCj;Kb)4#O_a>c7&whB!p(Lc0*DDb5Hiai zY(O>7&~QdBTf{F4U2HmS#Qf)qh>>a%~bag-=_7Pfs?EVmloK> zKvs%Zuj^NVG@}=|HxsXEZ;RKb7^CcZ>4?a%Q>E#8ry9w2t#qjcgT)}!hBiIJcmu&Q z?Bm(PD%3Y+JTPFU`DnYbFi6)dnXpk`XhSEUt}w@~Q%?P1rxWq3fi|LLKoGwX#x7n^ zx?f`ilf|k8dai&<)pgkRw&~p)@yfz*?Jvybv$G-Xv*XWIs2$TakoMaPz({;?qj}UU zur0h~>IhHE&q;HNL*S}f#9)=16MomViIMN>Lrd(1>DS)%R(rCdFtBo~H^;y{f*H+E z;jiuTE60HwJAS>0Uv*sUEsvRtT}X?Zn|Z%`7YGgQS8*sb!os$?>Fsrdt~Gm!7eGfY z4FHX|5}q+02wgDV!}SM&{szaw_2zpM2BJ7CUi?K^KHscmVtLhSVEItsns0-vAO2fC z3$!u`k>7q*Lrd?5pW&C@4PgK%2*kV@kolSknZV*_*9y;O!z#FG5y={ImPNZ1|Q=qgb(mXsKqk;(sTYH z;RA^t;WK)U#+;=I@Ofa31)nd+;3MZ%8nkXz+i^l5n1ICNT5xhhr1Iuiw9v-Ci==15+6t2g9f2MWtX@c0YNwgYA6SXSI9{ ze|}{Dydt-i{i3^`iy;-kmJY5Xb%AZPYnrSP=o7NQU+u04E|nJn)l>_{_xTW_;}NeG7#-K4Ex67m}-?t_gv-iqk6CbFbO+8r=b>`9xAr>J!eM zq)S`Z&@DBs={-;D0aw!Q)irr4+3q|6EEavr6Xh!`$6@5329geiY8(~1K>A=L!)xRa z0@+M>pK84)m1?|TuqOUgBLK?Xrn+%WAc+=AQQKfF_rnbhs7D>{C}U@>>f${D_XXSn z5iP-rsuoc9TTRreU+E&}m_-uT7t|&X7{CZV;9q1qRhDi!Zc-Iib3;t(66-xD6-r?? zT(h;r$q%>6sf%%9VcWf7&tGO2*X7&QCJ<^>GRk6-8B;LH=`sEiiQ?b6MV4Y8TA{lG#>PdPcWlecrYqzWQU6t3$IQ?ZEk`unS2hh zBVeLz#^V}gD`YTUzB2kgfBI^N6J4a>GaR3j@fnGaJ)YM(oo3p`ovP#j##Ww2_v5Sx z5=Iy2tS-)5U3?ighq@O9*>xKCUtQnKX|c&+nGo+JNYN2^z6Wp=QJiUBlxo$1Q!tV` zcW@itt1#YLx1?IN6|aJ?@cB)wRi0%z#@DLfuoj&v11+t_zQ&YI5`l~!g6b-(4P2sX z)e06wXaJZt_njJim4n!)GOQx-L9bPHERw2=1hRuWbeUe90! z<6Q2`QT%7vrXt)EdPZ%^;~)2?EdEK^lz~6NogC3)R#P&fzn|=KVD*~b^;D>K=;woC zsk2XgFQL>nmMXq1yrnRFAepr4JfOq+4Ocrh9bofkZraU1qc&~fANQtb_$Ou4di)7e zW2(j`w00X>)A-5JCo&sXAxR7mn%Fk)SKu70fb8>Y%ytqR`Lxn(L^%)`72DxU4Mv?m zxQ9de9nK5ShV8M%JLKk_D??)`jFm!@G}ZP7_iETLMU5EjUqW$f2`j;ofz^uzoqLTv zl%c$i&DK-q*|6|(194~ILx16iybrpuMvdpc6u<`Palcf`KPfL2;*a#Eys^5ve{~F0 zU0M_DDAI!!{8fL#D>JM?t-3(or0Ym8F6N7MKYO)f6h3F-^B?$F6pHy0a0BCswqgq~ zSx%9DcfF19Vc;^f626PQFbb-3BjPKpgd!y{I!eRs5Wei!<G?sdx1PU zckj`o^kLl@&A2-abs}{>_4);rwKkrH?+iA)GoU^ibBw-O%GD@6;}Kw*xjFQTJB7ctDZy^fTa2Z#D7q? zB3~XZG3U`9$IDxB-#6Vc5=on4dQ3vLEobBmfU~ML*vX}uhl2)!L-=U~kaEdcr5+!y zw*!KmK%8EQ8VgIzj=`J|N~Tvre7vo1OfmOomAd&;jDZ5W5sLb#UcLAH80mAm$747m zOeC*TB`Q=#tn2Mdr;b;k8F;rEKgdIk&*rzOo24j&= zWiZ|SE)2`3M&c`^wmvF0Jgas=v5IkJ6FqzA<&&x9iL{Hve#6aM?uz~5yPbTzVIH0= zvkkt%VLm;Tq{Jz~lwf+T7w~VxFjN>*hqw4Ks1l!Ab{>X@3$Uko2js}0BVYj$b06Xr zb3rMAAXGErpt@T3gVBpy7A2L0><~l#hAurgWUn-bOj|4Ez>saIj^|LV^#W`YFG?w9 zql`^Q?h&$y*m9{d4Tt|?qrb%wB0+ROQmfRVRNbnK6$e3LtB>o7JdXypdY66)@MReD zTu_9Vu}Al@mx<^_9|P>=d+Y^)L+phd(9^`@^^|3fUx3ns<4u54U8OE&yTBQ=ogbZ= zpOm~ec`rZ{sqm?1n0cNH*>VNV7=U6Z2ubab%hEncZ_7au{$c%6W73UrBX}$Ydvbz* z0`e|7(KCH!1f5qFP$7K$9xIO5W1iWgY_X#_kgPcuut!h|Ej3tD@@Yy^2#cKr$b#N&+l99R+rZkAe1TwxI zN_HlAquStU5i7&aii2G3|s40;^H-53cSUYr{DTQ zpWHS;pUn74Wvbn`ljU{bw^MC~_daYAb0r{hKxo?ae6@~)&3jx3k=8|S)LwQo)KA|85aj9E>|b#ptD9WK!N z1$$_;Q=V1uCX9CKMDsU#spTMx&^jfv5FoM%X*mfEnL%24!QvyAs`0sk5a{T#y#*$9)6#WBA~N*{23) z{iTF%5A-t4^kBUBEBpbrquZf=SqE1gm!DesOuPwjM(U*-KJN=2zWiF&%dEg-|Mh4@ zZOgPpXtuq0FM5sHn`Q{xTC2spMuji@X;MFp%%3J`A_gGM!L4mqXf*a61f$@mVUA`S z_++(H`>LbvFR&thCA_AHzi{@cRH@Y0YB}N@$Px7>9;CTMl>q1KRyCOC?9||+4~ZWY z-Fot5{^x{0?}KGIj6wk;aTl_vLpqOco1czXHJxNntR`4xe4|ht41e`3wtq=sq&|q| zU}{!8XF7a}&^5f>1b1nl=%=Z5+{{T}u%3i$e|z2xUK=sYfeVR;*)sN|LqHblPQEHL zKzEo!K;5Xjs~18!0M?`mF%PSG&b8uS1(hV!zv5qo`^xp=@6`&z4%m6srz>C>&DaL< zzFG5}raj`o`meA&hGMy4Woozv)RS|G5iYo0Wg3Sq=sb@t%ey9^Qx6)}4>~$OTYG=_ ztT^}(K%nm-7~?FkKoitcBj}WgO?sdBNU0>+4wL^97rOf}SvT%7jzZ z7BpvhD19)8ZcoepgQSEa2bf<&OlsbbgE>!#8`D-PG>wIL^Kh%ze+2|k#tyJ8{>TiU zdWby2Vf+rk$onVwA@Np&YL3H)2;S$HX3KJVs}3=~0?ABmS8d`6r2(5)Y8Z$tWg&c;(jC@uIHm?OtD4Ocy@ z!utM`P8JE!Cpq+0h<9RDCAtj-)Fr5hH`$TNFgNhQNoe=!m{adY(iT8-Cfd0kHrHkN zUWD(3_?}(x8LU!XK!GGr^Bp)n)`Anx)Hi8dGdZ4_79cMx^=)H(Nuy_-FYCjp+Uigu=TmnT{x7Y?!0N^9R zi+5Z4=qf#AF!WSP!k1Asro1S=jIiFpYx$2qoBs-AcveckvuT9Yz3s$qQKHzFRbZ1h!*#&v1EwrOhS>V7nzx z_0L1_*omn?5?Cc|@v#Q1)Ohax z$fxfhwz1L^DAJEx1wS~!@50%{fHIMCSEL-db={4r$ohzqSE9YE77hbH_AHp{+Gt@5 zT5!~=+i=B6?#0L>%aMTB6)8?*u1MW9&pC-}XE9L-DW{nz21J8BZ@=e>5z*!%$(|Jv zEtlK^BBFs`K}fXoqrT@6673v@L}N^n!l;Y|anY_ANhrGe#YMB&Qk)A2jAndTaMTPn zQ|qeA-CyupwKy>wYRm_1pC>^LfcReR*R=lyVo zsY@I4X4_{;1wD(dk=Y4vR#~AQ_kzBanDGmdQPed9K3DFI)9V3Ovz6P^#`N+9V(uiq ziJ3>cwQIFnbY<+BcDIJ(Kt(iTB}mt=nt>6}q?M#$>acvp8hwOl95beKF?3h3q#jEc`eJ}C@Pqv|9lhKBi zCt|;FY(Hhg96|IZE4QZQ0%Zr0S)@Bp-jDy=!}$(G(4uYaF!-YP1z=}v+3^c|O?N1m z@}v1`G+)T7@MUwIll(E`y7b>L;6G{xoUgn@_^2ra&>}bladg5wxX#s?%Ih9t(DL%< zj?|@_nY|&Sj3BdjU3R1{C%Qb(*wsPyS7oMwbmC}PU5|G&SJ%xV_+$PS5^0I>x9quj z-GHhG`9}%N>gZfQ@{dk5J@eZo|7ev3BkQpl)M_(mkoSUUSJougm;eAUodxmwE zWb&zP2hmUc@{6&0bfV}-O4yz1XMdE&&&Aif@D*)Mm&VW14evz54UrP|{q%mko|0vT z@<7(oU8;#H0ZRL|GY!#ka#})I!yU>^VR|+EdG3wm*Uy;VUmWmiP4t!wyPF#He-lb|OC<9Egu#^|(R(G|Tx=ICEe4lO!Oaw=vb| zgm>ZS_~SE}ufcXm%RG^%dY8((&*>1dG6EZ-Gj%H1fXMP-WbT~E+vSL`)RR2Ki?YvvLf<3bT>o&{mg zKMPuxXPeLm1SDG{#WNRP5v}t{G_y&uu#TpeV)SOGwWGJIYZ3lNBFk-zU{v zk;JdSP3G>$L4#ArkKwo@^U@;I5YEjVndV(R&DZI8h7g~Y*$_d-gu@IT22uzO%p4@B z)OovissnAnPn_5mDOp{Yx4I5W=DN$(Whh1^v!#_GA(1()!TeT_^V#!TGtOrXO^^zc zOZW{u0=+hl_62aG37xT4^QP&>;ew+uYZ6llyl7MeCo2+uk#Vtr;>Nh_g!USYahErs zLh_}p?G0Cg1SCJ<#1}`O=dM<%KQ1SsJn0?m6{z|gwh=&c)U|sy6kkrI7`;> zOc^$c@UDF$d^k~TBM2J)#I}ljLzptrOr!o8tau9lNzQH6wc4c%T~*gyGcGTDz(XU0 z^PyF4ejNt8Y}YEtuG*#F_Khk0j+WLoq0~3=3F0#spAbH`;==*R{4sC17&Rsv<1+h? zFE(E?O4^`eWEJ!q(?tCQLM9@$U42z9F^gb%L5!+LfD90F5h04RRUUrEBY;Ji?DFTu zm(NkIA<8#hd4NtxTvksDwQS+ud{4_u{F3qqym5w8_VG{Cm9Mj0C`B<3*8{up1Nd^1 zQJNk(nLpZBT=^;sI2@TZwVv=od@-(M&E&ptU*>|8moxDsn)f;Wb&NThe1!kksF9x~ zJDiuXVzd^zTUYo~=P%jX!n2=)Ws4)cxi7lZnIBo|OqU+RZTaC3oQ*x56H*VbAw#-` z5V0-4UJs+L{pD-!@;iF&#wE8*SC~G-ozX8x!nCm3MjkNs6^YqjsrRm`d2G$<8A2io*1c~DxUZbu_?6UhT_`I59KY-b~CT%B6c%x=x)wpg&G{_&l`@&#CgWD&txAe}A!V3h@(oYmhKL z%UM%Y3Q+HY#fLYW&HfHxs`5BwqTfA`^4^1xY_8dkp38YNIf2SYTck28;!d)QaoVPW z1@~Fw_Cj?x(E)jgo))dwVdrUCf7GZFFqWn%2>7?v1NgV_!OW^^cdNHv1BZE7 z;tzP$q1T~wI#lpaLjvqHrWNe)G{1vmu~y`0ro%K|k9XrienV#yRI&+zV-~`Muq;oK*xy4fnR7CVZyh?uIB^7L^u~JlJQi};=duh?L$=0kW1BRoMvWUX1k*APJ* zoT4&j%c%tDP(Ph90AZT}5?Ypv8w1278J<;N#{+2hT;OT*Fs1Y%<`EyRWbAxBk8JKe zq33nS|E3M2ed*GmA6K!sZ31VD=CJ z9%3vU-hiqBw>1b>3b>s@V4MKlegI*+hFh3WiMXD`FE2RE2IC1nKw6|48)R_kFLkN% zUtn9{>gAL^0px}Vx&xrP{U#6rJjksIdIfqbU!m?DuJo{{p>>RB)e5vL?7MWu$i$Xi z#dWk0ijUrTX|~>i@EnDO>Qqe0_SM#SAh5H&%d=G5O3Vl48Vuj_4Url@mdk6T;?iw} z6oQeBANbe|EW%*wDUR8mq{SBytHyKdF`g3pr*)A1vs7+CZ{{AV#vaO0m;W4I3ObAc zqaNl*9u<#Re9gqik586_)M=K-beuJfsuoT}@E-BV;FY+-J$Ak?q=n+fD~#KD;TR2s zR@^N2Y@;wmhxD0;1D+ucPS)>DMLV56#rgKQZNB-{SewhF&CoO``>E?sGv-mckW;W# zZ@F!-#DOf_2S+mSBo;V_#2W2*^|-`9OI@;Gtk1+uot-yOOvI5S0Q_^mTZWq{{G! z7>x%%!h>WRvnfuXy^saS!@P~#J|{a9r(E+Dy#(+UatSj?u`~kg8GSMLzfQ1_zQ(h~ z^KZ0x{*BD9$ZK@xS6tROO#J?knn-No3IPR*+JhlFX&0&W+b~81?f}sPrjf)U;5&U* zXQ@M{9P6|64z@ouMV;CoI;gJSgSsHSiZFs?!VCqIfCeVz%~Mk#vu8PO=7{?V{K+&a zJa?#HQ)lAtg`1+q*m|Nb7ENDFPzhD%THiVTY37>%iFJR z0>7F#8<`0G&(pha#$+o-}1xIBxFP3X1>@56J*F2U~ZYf`PmYr3ia~&x`Wn+vBAqB zPs8q_>oQJ_-uWFpDeQ*{+Sh|<0>|!d*O81)!=rE0x4KK!MKI$o^)+N(Y2J@Cl!!Nu zvUoC4zc>dkWKi0^)U%32#W6EOS_d)tpYWC&KoW=R}vKLj(I{D3OvZXyQvU zDaU^89qIVh)iR3P$LXx{0V&#N^$H8)e--IPF*;g5Eg&_^)vwuLidRmafWLbwTgpB@| z#5LSti9x&{?)x#uJis1`k*5c>hZka*ep912{^>txL4hlP`i#51D|(Al(-(;sEAHbvC0?vgy@HaMn%C0* z`$hkcrFc?oXQ}^(1Q0qySj<(b=ReWg9gH=k0QEEa8vuYG+BXP46rf%GC!j5E^?Xkf z93Q}+AV&a*kgtjf`9i>Rhq}2N)Ma#diiRA%U@~#LM6o@->WMnuSQr zMR>BN1dbQ}aLnPHa?Rc?KJ6>$mju#uX8q8ca&KEpXVU;qaO zLExdjgW(|dFKG2+t&o!h?}xmHn(u5(dJ^7+w`9FUStR7-e-K&|DheNSHKt(4Nyh!)u+~?sUh^K*sq@r*sm2evvWXaNBu?ml4LJmkIZv*Iwm{~ zr9f$Bq|}c{?pU|-=$ylF2iksEd^oH{2VdQ^0Q6+Ft6sv!IiY!;zF z<;k`Gn}DRLt->+w#+`Y*zH-iQGm|g79Q5tQs4V#*nUNo^#i25{3`eb!d>g$uMQ1zI zQaoAae_@Cwh7tgWx$)-vN$&&o$B z*T5p=?gs^g4d)cE8c#(n1N%)Wi!K6l+ffp5sEhvcxg_T?O3DTc_y$>Ne84v|#QlJP zZ>pPou{IBB?J-}Q0pFIY&-)5`7{kr+k?dx8d*dLfkCEF%eOI+{F#LY6_8O`+y0HUp zjRN;~s0CoJjLB~G)8+Wt1*Az=^Ztx}Czj>zhcFD1M$ak)O=b{nduILz2`=>dMvL4a9sIpRef<=(gwYE+WWN^-95fAEJYa5E z0#=xsfO`#aMc8$Hl`wNacigdw;K6Ldt$oJ!Fgd%p`CNme9U|piDCXQEj&*xh zy@ZNY)#4xKqd0c0oE(y=Xi)ib{K@ga^_Z=Mkp?I-)T!@6xWmZ#G{0WVwN~~2ndFeX z@j5{7O#Gbf5dn~2h5ranrkJiqO9R12Im!wd<@-3WgZJY%%0avUBOZ6@!9Nmd*D zoTy2@fJ)#qD}oLb3o0o2)V;#CxHs}gk9*_cr|1g1@c{nVhJc`KIPp{g8VjyN#agg@ z5KvXBuSoO72(9uXcFQ3DWh^<8C0FZ_O!Z&Sv?Ir4&@h=rjuM;M&Y~6S`*;&vEX~4s ziYBakrEF%jE+f1JS3V#h4N}b0Ok1K#HWXBceHg1V#fZ#0zcv8+n5VvvrkOA!^xMpzoy!IZH)GfO`%_4u=wc=f@ZPSvJYr@<9HLh_O zmK}!|qv(5sL5`DFu!yKVhQr(;O7hnZ;3@&y?Ag$zqcm7>&O!NLFX4Qtuv6}h`~f&; z;sxOB#UCsr(m9dyuB{OJezoThnptKrIA{2C*hNm^{+Q!mik&{INE=0Fsx`n0ZJWG9 zmGh~3_aCIZ%$|^;-1{x8g0GS1b^PFMCR6$F6*d;yhso3YOG3bkd41Ru{vm$X1gBzL z0?@45fVvvPfyWcrcZs=e7dD9teWA2;j`nfZThpj#yK*&xxJ&|Zc@iolnWij97M7zM zLu9K*8cz$Bvd1JIV(4+VypWuv9nNl1i|jx?4Qt{*cq2CPYCcs8{IfZ6?4b~#)u(Ra z`jDo8?ig2>(JRcPE2X%e(B!YoKQo?H3~ENryZ}Icgo|YO_A&=BD$UcJ!wp{({1f1# z4xb4+1p94qg`4fHQ5Wwd|BeF+Dsnla(mkvGL>>tc0Y8LuJa$k`@r65M`X?)iOpG4y zQY)rmwV~&byiGys3Dt7+X!q8(BN^C@TO_u1`rzBTT>#?Vq__1Zy{$KKTL=Hl_AWwu z;!Q76<>sNm2BY2`RD5?T-o^Rm*Qg4-hA=03Gd5(tY)IOM&PW@x54NE}CbUp*<219p z^J`QlE7W^~AMjOs!mAX#LMsj7+fQ-?|AO~gO{ac_QuYK7yvjo9qO$Uu`YO+c61`tv zd#`18Xu7%Yj>GpNhpz9?-OR!^Uhx* zLsSlXaEP@xUJtJ4Ox2AeP80+jxU}+Rd6xli1DYK2yk3v4Y*R&?*Oapbd)WVPQQMyJ z-?pQB7%2jM{vU7e0v=^`Eq+guNf>a#j4;tuV^7p+8zt6MLQR~Y0YZofI7vtX1rlm0 zjw!WVW)v%z;3RD(FR>hJd!+T8it)6zwbk}m#Ty2q35X)%4eO;=d)XMYc;h1Ke808# zJCjKW+S>o~@sOE!-hE$t?X}lldtD@sYC?(8FgNGuy6lbEPD%;%^@O@*8Eb4N2(yu! z+R%QfeI~VQ>ssBfA5gt%bwaXLhO&~^I1H2>cqU86pxW5f9QD#KZdzDGg=P`aMZJ#l zJlCDh#=F3*h*wTd42Eh?*VX1W;wYtwRcV%$jz9YXlz?6d6Q``GUPSo%kH|4S_f?^V z?4;I|{Af>}Ml*@qc`bUx=nxO6^lKT_HiT6{b?8;;ztd9C^N!K&F0p;pLacXa2db1* zH9UqYUAYvm1qp4r0%C{3u~)0AyI6S0GpI8**=vqRiKw#2=!<;r@1}8EMTPUzykqzc z9VAXLsV_}Vv^dsXf^2*l2=cJrdSD!%2v;TeH50zMRM^Smg>Sy+JIpkC4nE?j)u;&v zbQko2!P);i;aeXS$@m&`o@P+Krex&i)N4gl-xB;c{_|eo799o^p;TS{7O0j3FA1sc z0KeiftXy|=rJEb}i|M*mYjd@Oy)TTgbK(R~;@2Rey~HgcY`PK9dex5Q%=m%m8n46l zIpO)9s6pBM?N0T=0S$ii5`5O-n$Bsip!g)tSIe{yaob>evGpA{eAp0a*Y%_AE-nt- zF2~{J=O)J_Ii*nYBpp->6S>)6iDE4UAV{MfSJhiE_Z+l{i&KfMmT$#WVCc23^vTYg zS5vP}qARq{ZQ|nqO0XtXk2Y71F5G@_KjF@J)Y?rAfqL)q2duTZxYRZ^AI83ajV~~Z zU40~LZh*gS&WFPt`K+E%Di}xQguKnu;*j_5#+bG|mwq~iNR4&C(O<93MZZeQ zsuSMQ^(OVJ=Kp07@``*y7~_Ol{{tEe26=WW%(nUY=rtjSr%fhKt3nGN4AyK-Pvq3T zz=~{f#!ydEFS+d*<5FVb%O4x(awmTc^w!?^z{k?Lsg6DFu=9gj4T&q3gttH(K)N6p zWg-DAUJH_mj<(yHKBS5(l2s(b^%%c_lqdA0+ge$s&jLfnbDmx7ptTFV)Mq%Bq98oj zxeD+Tv9pon{9X>OoGykXSrsoC!0#SRuQ*2zHXjiGNK~k`9XJ~|N}ZQNq9*T$AVWT_ z9*9)J%4vWkTJNgYUL3ZCTAEOo{~Dic5VvWVDG$;3r@6P)Awl2-5)4^l<4&*<0H>fy z01t6kGa{KM31Mx{ZhN1U+)a(ig;=egAC*Lceb(0o>D%EyKx+s}NO0{G0v(!R(DFx# z8VqfEMWZDpoaRu96m2jXebde_Xk_0aq3J{R>27^Eg;2RwKH@8upS!xV-bK)@O*nQH zqMOnaoRy7+4h%;8k%_)64s6y$s2EZ{&=tJ`q+k*NLG|278vxMo#W7uqlejhAsg{Uj zXO?$>yzCO`3-rRa*=N7G_SpT#$WwcEYZOS4r+x?#5S{BPFZKW^OA6((MXGrzB2_U9 zO^xUM3G!6hzv-CvhsX9v{$2NGu)Of&r~Y5a3pYP|e0kxFXA<(l-7jlw{SJ#C#58P| z_IbYd0?SB8s9CSQ5|2Ko7H{l>nkBgQ#Ffrj63KbWhSVy&2edV%X&gH zTyr?+iYPUB1r>-W)u+C&J5`j5AnRVZxdtsu_5KU8)K@On!!johBKg5=U+o$qDtrQ2 z>gUyMMEYRoLWn+CPXIF~kQhcMXONr~%O~Qw!CTbLK*K%o#|VPg0)9LCjdjuBHsJPg zs*SdRFl|E9g3-P_WT$uHvjp-yo^z^weB7Yt)6@DpsXH-;oX0ltd(gZlj$AVRgBwdZ za_v$daj7bly6h(+Hhn@pgyHD$!!&BPgR9bq3?oOS=eb6f>Wy8BenOuM0myeu|K(s- z0ctQZuON#p!hm(0X^TdYJK6U)ay}`zO7B~)z}D3%{#%YKAKg3*{a&bd-K2ap!sYZ3 z`KZ|7t*i@%O8&rkZKrzX91*}={u*ovBGNa3Is%X-Vn|Mu1u#qWZ*w`HY5m*d%SThg zR;`=HkVQWFTP?AAXQwU6@^egFCAgq2+G@+Q{Hj78jcl|)UA~v6<)D;OU`+blnhD<&-z;ir$vLPfv^Y1V9i znaD}gc!gJ+sFr3X`~`@>4>2anQPPE1=&P23Y9TMKBdXO-={`OLda-=P>551rQ`ubB^9KD|tGPGdfbIW!EJ z4}m39HcLu5q?8ELnUA0f@CvEh=xQVF7MZe+sC}kn)e>kCUoMoaUXzt`YLzX4mgwDj zlHRA|Ow#y+nwK5_W>SJo)$X>fp4O-ksOQ#!Zz6-99)0Y?$&t+Q2O$Mo`YZ|+1t_Wf zhI*1^Mf%)(9O-kepzqy(GUzKm21}n4Y8po8qrvn}nRpiQN-B-3$AA)qPzz@t zO$$hjcc16FC%C@Ez7&$TC{;MS#7L2B;VfU#{rFx=kV3L&2z9lWb;!McDkOrSlYfPu6C&$WXH9a{K zU_nnFF!W@QeD)tw-}TftAfMfRuXNwt*#s#-xPbUfTsOT*=fC9|r?Be}9gsqEDO4w8 z#-m=n`l%FJ3zp|e2#1HYGu*c&+j(Rg5DkXOMjlNM^0nB^)B2c5coH%*=)wK`*7P9x z4tnrr|2aClO_c1U6cve`YVQ^Rb&1o`1_&WBf>D3SNCDL0d+6e7SLj_y`6(&7Te|lz zlf(jD99`{pgx(_^zf_Vdl3ISV&Xmg)De*P#o$8i;vL|T?al>Z$@${?1ONjNV_#b^1 zcRy@a#luEI{IHe~zb|c#O!P?0P%qJq<*^W>N4?88=uWA>r6-1i-196M4w?{%NRbZj zBx$g8c%-Rev9)@1=%6%kJ6SyUKAG@>Td)592WptA=d9a0oS3ykl6Mt(2WD*x84W-e zrS{+#ycU5j_qJ&ucK$w`s>VYaL(5Y0t(A7<1OinWEY^j$ctfs7LV6*MNG&v7SDp~- zx`!-CZHFK(6OdNi^=;N)C5%94qcDXjVq8(r7$g3P6#In89QDzDh@@fb2VzHv+uH&A zk6E0K+vQAcVPC@Ocor=zjuEIptGsAAZ^|WMA_m(|RsSGuiOS37rdWZvD^0q@6<2ks zeQ414t)(jmWKKaH?Rwvk*ci^V?nxa~K1Hd1OOkry~q6Fj% zYR3Y=au|lsZ8iCVowM?)8`S&a4iNLKN8IYWVnQ=3KlQ}_3qZ9vy5{qatIoIT{hiKJ z0@J*B2VHSi-3IGBxYSkO6Dh%7w)`ig@H`)po!l8OTRpKRA6b|Gk!!9-WB4fip$HI@ zBEY#uNRTkGKu=wo%H= zp4Pl z25O1n#BosWPYi?4{2V=Yey~Z+$I0Lx)De)ZBiSSR^7w8de{voQpCqfT_?3@vYY@7J zxto?3tIQ)7FX))!Zp=PFX!+m0r+|&PZOIFU!j!02i~oclv`5g9&N!^TCSIO!RA%}E z8oOi(A*BvhhaT*kE}THabDS=@C?`=L$71z){G{3ZzN{81jLq`L>P4S-TW(U((%#aK zGrs0R@b=w@^!&>#wROWk$N|w2&aFpu`~{wdNUeILPpQ0v9wFnyC4~q%&v;oNBHghe za%p~yW!FI0@FP(Wt1LLy8;rL1PZ{rSGv3QZz;T@MZusou&G>&h-t%6P@k)38mGNqP z_(iTzC%;vnFIXX(^Lf>ve+@#-Ah#h^K$6W)V@H`U6+4E)%e`IW$N30-jt8$>K0Cag ze&GKlex$!B@RIKQEAToF{x&ohus+YDgU7DVGh}_<_(y5&uHjod&RUfv^NH!yhf$`m%$GlJ2u6KXlL@ci6j4#aBwGCe%CewsTNz~VN(Avu;L*PLw^HSN%Qq^VUrh;lAiyW@J zczv7gch#tCf6MWNz1kMB0Pj;D9jYHIOavqs|3|w4Xo4~+!k@=GXF27!KIydl4^=^w zQq+=rgnqIV@JSX%$#YrR_=ADo*reiEbxCYlVQg7ZI6LrMc%&kRY`k%s+YwvF`(k;r z$2)v~s42|BBELI|>7F5uf6%VU+ru~{Xt`ZD98DV!hJ85Zxi zcL`U4BNeiz-Uhh!rAVx?B-U6g$tgRJ`dTUZK8}n={RAsGjX*4%T-u>>+ zna3G|)#0jy>%6e`Y_||;j~Qg?-P#Cq`2y=ke+xNl)X`o&`t!PhVTBDSV_j6ft-=uv zI0sjT;2@~_OqoPwUTeLstXlo{6Dy;IIe-w^;r{&CBL7P3k(jGF-dP3X-OzcXK8SA- z=){)g#;)}o2Y@FJABy%cYzc&lF&SWL;FE_tJr zwA~gM%jU|$KwlUojQ-QD%3>?z4g4b_UYB@z0vq(*IZU?d&wR-DS189SAPnw>E|>}BzsrS>mU;0zIje4Xs{W(KD6tNayV(PCEiPa)EF-#_5Ww7dds^?Hc?x@5t|@m!P8ZXT<#{RS3yo$PX3FvX zRD|uP>JiJr#yM&>MPcEKV8#%HEyi+hjsrg<5}o(@N162u%2}9NV2xew>@6=wLkXV* zZcI2)XrAhbc6*~MbG^&YAk{h{sHWpVi|WtoKDK)6glM-js0zqI^~EOFpbiMUw+#dD zC9*z&lxF!XWBeSnzpZ_pCbDz2Wxm1o8yQj!t5EhCl#G$gkB2C=0;o$x$Z3M%w(Zbc z)%{Xw__WgMg5@Z`_+rMAx_@lv!1IXMgStvuTu){ocv@*tvIl)J<6gD@l+J-?$u9Zm zfX==noM~O`>dz3HdP5>0H9oyXj(_pppL<$GVxjwDy_0+!nO<_U?tgd^)ABj`EW4pP z+C#l8bFQJ8k@mU8G-5`(T|GHc12$m?3w*)mmD{`y`Ym~^cQ$n7cI>?1^N~E_k@`C3 zr17IMEiyXVogVE?M}Oc|F0(RE?T+rn3`TUDk+)pWrMXIs zt)O@v&PJZV6j)L)1a;zU!1;d?&g?~Y7jHVgtQPsbAJK_i^@aZfg`bpN$D2lDt&|9l zB&ArLKnk|6^Q`rWDbbMNWJ1(5XH7Mzv69G=L2-(27BIy^s^Wb*fm?opo=asCv5&Lc z%ml>=+Ks3?b{LQY>j45HAh!vKT$A|3=Ey6?hj~E;mIrL|YM8^^U|o&+DS}R%ea&J) za68rjrd;D@#R~+`A?0UKe(q`8QP1--L87Iuzz0|5F(%R@C(?hlm8k_Cmb!W;6=OQ$ z#!hmc-GxtW|J2Xa{)*K0L;p_uKV`NVfBnBQezd6kj6WX_CCkue|(RCW*Lww7eR}ICm!I9Zk^I4^l`k^WStW=kJMjTKAC70WJd=%Q zPupTyX8hJ3S;wN)$UsJ@IWF{KGB*pI4~Bk3@dWMms*lu%8Yv;ug)$*S>9+_c3N`(H zy_;yeOa$xSJ`facbLqy?YU{-91|5KnDGQI)ovW>j*DT~*x9VPcv{w&>YbpF^$;->- zrG%dFm#{t9hZ9D7qFrbjOreQtb_0FV;`O^PU|op!i##b3UX6TUljKr}X`WEMtStgF zUEcO0N5FDNcqY18xA|p2)+HFxupFlNj4kBh6=xGAN@YrQRnBN>S|kUQtKc#}h^aND zgK26dvUbtD5`QV2mQDn($q+OSvFC|)rM`If56Ec*6hr3I)tfq>bF`dvtz2oXDVFFt zXUZ{SR*Bet@PjjaQhDBzHzmnj^6n@%aB@vn zsMnd^=K-wj^I)Q!tiP5;hQvPKJk6Xz+jrMJNgw$j9brE01)lMql`UnsCAjg~}ax4;IOl66+5))DI(HDI};y5h|s(F8+JF`j} z2=f@^QFO7Z{sy%am+c;TXr7-y&jPhYln!T=Ra@KXOBm#Ks8fZZ*72~0a2oV_shUV{ z>;-|&9T;UD#&bvDaQJIMweA-phIUGe&;6B#8q{|N-rOi}ny*MSJzI@ehFl8}i`HqN3M^r1FT(CORnp|Lgto1|)yRqtzBrM

!eFI+Q<$3Exxq`T2=V&4-;TeYXD5$_MZlkx@}R$G&D;Rd5+*EwM3v4Z}hwM_h5 z$0p@&JoGWq7&2njx#R&?zbK>H9bE;%jJ#|u%k8W*xvmkXIFe1Se-@a|4+Qw+ev$3# z1uLVzv$#z&~iV41gdU%K_tyZ>u#kN!F1-P>@~#<_po z_D&kLo+530_q)Hg9+R|Rp=c3Q-+EAlRj#MbWMJPS9s$pTb`#NeaUt9dbN-j$CaL~< zw&}~hQ7soPhsycV!r~sv=NM{zKqhyXOkXGU1e56mlgakill1>1_35lvlXaBII_jAE za5?mUmtB=v(uhIv(6*w7)30)uG^R&JP{YVH?XYU(ur-YPgc?Rl4Neor9D+T{5zhL3 zTF172R|is%);;0RbO;t;-PS-Gl5jXBA=!o`yqA*jVmO<|N49ovKEPWv z(4^~)c6|vNz}_TB5-&kKWZJ!fcf}qA<}WrP*5r&ex$qkrYa)a~eyqtKBalKvVXUbr zT&m|n?BQfSFW5=^CSxnN^Or^(zuVqF2kcMC^iGVR7+mcRuut5th)IpnjuTYupg--C z@`0}DA)L)5c0$AEB={R`w9ya}Px*aW4hRlZM~=2?CavQbMp!8pO;Anbw>6sU0Ey71 zR|MfCB$R}gIKsq_Xm89*T_TuKtZ^r^CR3VA-u;z&?q@PEw;*kxhjUSGIHxuw5DgVD zeR4DHY1Ki(X|HO_cMi%ZHYeJtSGq zZI`>yF2`lE#pQRoQ;0V=seO3GmM1R3*@uPD^i6gODNngfF$-V(hN&;f&Z2OS8u>gN z!CVob9frrajwbm%GLag7%_a?aj+w=Eytlh#nDTiKS6pL=V8vdB@`CrUEn|!RtVCq5ALt)+-|B z^lPO8eQx2paJv$_)-K7&9HrcU;qrdCw`MsUr#<2JE4_iNhEDbYv(fd6cGGq4u znR($aH=k>2di-~Z!JMl7t=jK<9rM-i5=oIa2Es^){Mc3B{N-A8Sr5ZIAj3Ntp3^+P zUad>!zqt9_dbK?H^8y>@Cw92l;7))&Y&r7fNCq1bo%A`vVL-XmdT!iqy+5_P(@9}} zeh*gBE?J{X&Y)NWKtGD3qmE0{04cc+F1E6ZA+L*L9(1r${S`)g;?~iDd=_C=)03=M z;#|Hd|7jhm0rTiH?-o$#n|GJlE*JUDen~Tl{qj1k7wfc+-7m@Xjy1tA)g6rGNVR>L z@=LGW!iL28^kdF$t5;UZWiBQ}M0zX|L7C zq_Sg*8?lslkD6bw4yhKct_lP+z6|gSdirD_a1{93hz*1xtLI{G8XbNx%Se$thR_A;^EX8;Qsv z^33(l>xmx5>+wH4ZQ?Ph<)U*UBT-{-S?xF{e2DPSSkt-!y{j&ZTxyMIDLE%13=-er z!`AzPkN^DrnB44`9=cTkR;em zG1X#Yp4(Grog)a?_GW!U#ATf$*wgP^oqp(Ls^#j%)B1gg5$6C;E7r-5=rvx4r&Z4K zdZ`6NH*Lo7{2vf0YogSw>7(_0_yXJBf3g$5qXSse+c~2kJ$mGeE8KmPF}S9_o;2cM zP1f78RpSMwk6S$($8CG+a3^Blry-TyX>HxsA(^i zUrUv&+;_F*gBq*Tol)-i(jq@Mqr|BM0rdiBx1CIuSHFcp?QuW?D zg$iJFF4aA|53w1_W=_i!tgWrCs|ziWJa?0azM-7I?-~x&9OkVogjsc=`I7o$NoBB) z`1V~(YAVdHl_X7|4AGts!se}ey@f{55B>@ccDLc;djRx(fk&@8m5x?xb@e*>SS2kK zn?ClRG^FJ`{oZH#{#z?sC}6eP_1i?FFxrHBI?yHWHM)hr$ojHAM!Izsj$Qv(GEQT! zznO;y^@9Kvye(i_U!Im^w-!)G-ql*6%eY*DhhiLD8 zf+n3ItH*6GkM@=i+n!h2dj|8mzO0+1y-#d|HIt%0I)9JWhy2p7kutGH<)EjPWN)V) zQJO_{DS4CpDg6_8?788%@F>>(lX?efGk#)UrA6Rz(=qVpu5^=oSOwGnWok&@V)t8%RmKVZp@J8x#>zjuBRl^rWt?bC$P$>ub*DGzkxS zrJL|?@f#LpUE`^nKE6W_= z%7*dr(v`()Cf08$0RXIr&RMR~(c#lg({hi{S$Q}pjXP7?q#03$?_C*KS-k3r#-MwfO>G?iN?vDBf!h&s>G{tD{xvE3&0Z&z?xg-gC zFEiR%?=7u&g)!f2cGNdJ)n-7$5DfTmI#5rsS1DGb&Xn^%x=Pzv`p_cH57If!fA#6O z>n>BJT-NkPl{b30VpXzU9A-+rOjqeFSHymuuCPg#*DR)7y{Kk!zO7bIbEJ@n>y;Q! zxqBV?(MlIbM%~{{d+CfEif|B<{SwcMW7D0tyuw5K|vygPN-u8CPtL9wiIa zN)Lv*$)heZDO5)PuPLA6*udZG{FMWytN1f3*L@8*G>(VMwkj`**sf5?132kZFZ=>X&eFcX1d_?H4KfGg`ZBgN4`8!e zJ*Y-Rp_Q(6uZbi2noyyx=Rc*Mff-5R2bqr;38pVdM`QKwp>uQbz})y!=Y~6@96f}| zx#KI{ztsItPS+buj7%4+RE|9Kh@h;>&(V*Gk{KJ^qP{%L#WhyPg0bTsjjGRSULe@H z`oxf*5j3bLf1crJUoe)!(4^I_71KOh2uu=zaCo+y58+@jW=7wVrSMjfXUnCS*v=(Q zCwR6@L(UmhlBkNd{>_ z11`VMMYv&4dIDe2_SJRHa&D8eY%Gao0bPbx+#Q7{K|2OMBQ5>9RcBxi)a;lB433Cx-D15rg zvZry0-;b)=n<(SJ2#B8D2IyUWM_ziz&XzxWy8E36x23hS&?6V5!sX<|M)9zSeGqja zxGxZ7nHmr5CSxSC*Ku}#Mz3SC5bc(u>|8zUT-~xvyNi$>w~x>XM@I7Oxo7J@8aG8I zE%2=F)B11I(Ii2UF+s%U_RvPJ<9w+DDB(}r>cMBuwiO=h1MsPU1(fkbpl|tmhh9iP zaHWReH*W=kdOsQV{A+d_d)um7ou|(m%vo=m-h2j@N!6--R`wFAq%xWEr93j_Y(`<8 z7BlH!W375#Gu$p*%e%BWpOqC1g~*_`*a`YAd(czh=;@VH94q;oI&F&MD1QkWV+8e9 zws1P|cHQuH38{T_e-+2R($jn=aI@GT9!xXB1Rm8CF)e&jUuM~BmpBg7U|(hlPl~7h zv(4L=l5ZcEw?6Z>JNfo*o?^OU@L_&}pI8sxYkp$>B~yf-2w5-&w~%#Th!mDksI$Ra z+TaS0t*vc%`{mbIvuL0`AN9LJT)7g7h9WWK5oT$=k6~I-K2B+ zQ*xH8v+bO)n3xgLpw3++Kk08=b^HweQp1}jBd&FSlSSB{CEsz!CV?q|8|vXuPPzqj zGVVOxoQa3h@7|22 z{D^*;uHMl*tQWX1rIsb2qj+P!!zcoRyNQ)=sQQqGgyUSIH({S_!ebJf@ECg&p3e11 z`vN>D+MDpD{aI!_nm(&v4Zj&rLtykcY5&A#JkxdP>D0{_Cu08t`07wqmd*IrS^};& z<6)qrQO(K`EM~}SZE3l1?=uE?_t`x=Ajf~?Z}jvjj;r}AHfWmUhY9a!@b~T+8h^cl zzrF`qk%fsW4L`ibTe>ENt+V;z^nOcQw@)0fwgH$oE=O=Q`4p|jBss-UyJRbvyRRg^R#tA19_F$A>U)t;Vq zrHgX{)eNGa`n{%(`DDoWD1b5fs`ZAyp&z6y?sKqN+C1_E-RU7bvQq$Zs!1_Catt`$ z!rx!{y9UtxgueuRVmunY`(66T5lMi!eU=7su7EgSYTTjm1n6)?6e#BoWoLfRh#74H zjS;_uaw%A&w*6Ey4NZy7Oe(N*`H5yw$|lx1d!$5mm!OhtWN6?Bd!APdZKZ$yj=TbU z?!N1{9^H5-p4i<0c^(3)pmn8d+*_Sf4{SUH8xY7Wxf?O8pOOWEzRn6q+A3|GbpIl% zjXru{-0r{|E3)){YR^`>I>>@$whHM#3(Ys|jA>oAv^B?>HY}`!JJ7q2?uK=m=D@e< zmAdiJwS+H>WU&=dL&iS>O97G_gM$2ZB&xfZ?{P#pB7O?;!#i98!p^x9J7k*FTb#^Eyum50P zYdv;-#9cEuUR!^q?8O2&BZab6eynA{A`C5Y@ANUSOIA|f;=d&b=$-#Ch)zzr!KVcnbp@MYA z?J}w%>sacl}_0+iMI(qz`!~!nDcb9L~sfHWP3U*%Uty9l%I_qG? z%M7q!g%jF2aE52~wj1ZjX)x=vTxBG84=_XRY4TcFoqQfLK9I%iSuaw<<1Xk$v}eyY zCz{!;cn-Zw1YpxmiX3#}YXQ#{mril~hQH}Ne~Z7wdgjK*nGrb+G!QdKuP9hoVCF}B zBQcrZu4erBqd`}Ea#K25^c`9MY2h#Mj2D&V)-e*K6F9vR|#j#oEiR#i~sh!~J zj`qrNSAEI)s&!IGn0p<>OtircqevJGt)$z{S@o)!U(ATD^JJt??(n<@RgGD{o=PL5 zDX-rmLaI%gQxZuAF28;+3?>TD3IKU4Kc5KBFpzDZ@WTbZuJzMHEniJ>@X4)&7@fY?*B;BaDpa zPV8rM%}+udE-P5`)rSSd_W8!qDS0=26B zf$9RtO@-$Ne`E}8Z+fo(u8d{Azq~)oZX{lMO#w=qll&TAOasIplj<{4t0zYW*TeW| zTA8soa81FgXQYX7R}`czvv;YWHx~5S!_-hh%eu*{5^^E#yd~ug6BAcQ$;#p>5-sT@=UCX&_U4+~Qb%Pi z^9SBqoo>BvU5ulKjfaj{hdp;b8Q2wR&^h5A3yzs4ul zKj!%Lhjsnlf3N=Ee|I?e=>Ge3{rR6-KdxY8_Z2CJFRAQ$5^f=Op;6_H*DSL3X8Z|D zr|%#aBc%BTeJO`3c(~Cz-x?i2D7Jhux*|`hP9MfNSAVr-VvAnX9=wMX(z<$7Pre(Q zf3D2xUHDOhx}*FORA0GV6K+)RPJz#FpmyUQKorey1)c9o1(Q3>cn$C82D?r!W^?764%TG4`FzHbFJr7jX3Xdl6co+H=8d9c#&R=SOt(3sOol>&3X`H7o|Cv9_VEUcLTJ#9tkI)oI*maRoW3TVJAE^r*OLK}XL3ktmj} zs}AEe6l+&HZF(B`C|rn!g9|vCxjw)>X^wyZy=bU7pl_)6 z8iG2CM~N{AN&BZG71D0HLi0he&|yO~bJg#Dpoyki7A?qIV1uC85Kb3w6L0ifZ6iD0 z!Rb-k)x2oZ=FJ0&+jfZV8kq)P2YVg%XHNx>z`dw{3W6PZvv z5le*i@@R(|fxWtFZOg=RS$&a_EfaI}GW@nR62DbdVpHL?-tJE^GkEt|V11xJbBman zgoHIVeats~ELN9YufbU$G=x4@(8mJlqs&JVj-KAH_R(j4#YJp+Z5*zk#>p$nf@YRG~WdN#RgWj1o%_a}>sq!v4Qz;jd z*`UtT@)T$3IqP{B9@(J2GD}vcGeP0jSXVo(wXVP+$X6B%=EQ{idcx7w6lADque1L( zD_h1TM9IwrJ@7b4044`qLLcYoUc4{du}-TUN6kbUyj zTZdIM3=^H#-i;b}LIaY%uVjCb(+me2w8-A3(^zbZmGI^F$7w8|3i>MbwX%VEZ`jhlCb36M1rM-#c28Z(fdC|jJp6_pjq;OkuVBr);bCr5|ncm~j>M7K!vwn~o z4WzAP65&^~oHFZKp-fL+5}OKoDA_f%q>w73&Xg=E`}DCTuNYbqc{L?xrnb3!*f!4{ zT2k)fJgs9>ONNFiIYYg_bjUcJx}^9(PxiKPn37fMfuSWcb;+NlmITR%8Rxp8C9^0K zz9QM)mya#gGO6iMg4*IazJV8-49_KB zZ>H2D`pFmoq|Dlec;ggDX%qJwO#TYKf5YEAp8w9btjA4Nl!M#&yp>(flTgyUp!&I? z&28OXk{n4B0;An7;i|a?{J82KMsEse)5_C~Y2}IPqg|39g<_M6tgSuT$TIZ>>wd65 z#gS|EG|2)G8;N~8|1cOB); zj;A(Z&U7z=@!FzIRbJ7jjLUtVT6L4|f0w*VY%s_ha)so_CJ0QmDQGy5NQ~ED!3q-y zuV)*{86(ik@J$2#ADhTWB?|%dQP?^23cs0=Q%l$QA}4w7ZEP00yY_Qwj&-je04o-c zY;4vlyJGF)5i3_Kt(m!WM%OwW;Uf4MZP8p}3A>rExxWpo#UP-APn`--<25=x@@k64 zOp?BwDfA^lTg3N+wGSWp;!nWSTFh!xXN*el(zjm)*DL{U%hl3vCl;YA(9;VKnid{a z%cvf$NOy>BNo=aq@`hfura*PtDIivbGu?uPi$KaVY=+V>|68B?7|9!$SeQick{(X7 z5}+?vJ^kH};)~n57k32#x$(kcWy^E3x6?P06{zF*Eso{LJCzB$k6Kbede;oees89{ z4XT$TT(sP)vmhsV%z8oFoLL{g`)k?kcVc)}^X{)Ce0H81yM{r!)en{ol*pF4a83~v z*CG~y#ZIIY(^#-?4tOh!6pPq+e|Y~{F@0t%#VJyS61X_*)wD=YdoCw_-mjTlIn3C6 zsbO@|J#7+jP=tN8HdnM)conM0v>6%^EFdcL*U>f;H94;}HV6*^WR*453s{YH(!=k) zrhU>0QPDo>#5oa%#Go)Pxmubt79p^;Q^ZOPB5+{&?{Q0ykTn)^%W<}8f#_<^!>D$b zh`;v{`y#I8;6hgt|786!pjejdcg}V$Y%AUBWLd^$!NZ>fz$}Ai3H%cNMC1qOeQP-W zM4!KJhM*H`iC-+@t`QcN_Mutx+ zBam0wsPO2r?C_|LN_6AWpqj76bb)b)MA-jv+M2q+g#A>o=JO$KgqA5ke> z1J2weU!Ak!)eXU}+eX3AUk(koa^!7q#d&c@+5~w7xM%6=+731m%FH&A!2h@gF{04% zdm7M#jJK2&SqH#e-zWelS_k~)MrPt{spaU($d@~+(p!!ctpaY4zLq0jm#4*RMztK7 zv}#Ptk;=8%QdD%|fqj2Y%h4iUA3fi^mc;;^tpgpSk5|XJQpeendRoho^HCdSy@=(6 zICAez>+hx6wHX7y@8MYB!;y7(kyKd~u4_3G3I|(`EDMipIa2LuTT6?qYA?Qfucc$! zIu2^=@oXugBPdsQ&VFupL|9(}S7mHp5X+Vsi{%IyHw#mQIitHLS@O;Bv)20^F7z9v zA0s_mc681jwYy&i&hy$Ve(mUY^7%`t{jIdf)BU$e^U|I2!kmOFhnBpR>Z z9eJyNU1D+atwqu=K6EBc8+{Aip-$&G?!BzTPsKZ(Ypvq811B-zVjbYB!)vtSr4D>1I9ab#;y` zqF~4m%}_sB2gd55uG=TCfja7-JJ#fDMRv7Rl5=EgK!SB|m>kZ)JF8v|Ckp? z8u%qvUD+9tvl2_oEUfU{4XnA@ti52_8Q~d;#K;@{<(@6uTkZ?dfFoR7c0nZDv!y<* z<$nF5-&1z3yr@iT*=%x*F(n7eL>}+>d~cRRiM^y4I;KS~W5th~C_TJRTt24N_j0uzl^E&(Q_fPM=yws@ocG1fHcCJGa@-^7VsKcLuYVr^n<#qzvQ{+hC7x_ z;h^-R+xP+oW^E45u3gZF3c-RmL3*N zd-vCyrOK|Gc<#EH4{LiY`)JC?J9?^yP4F1aET-aUzX^L1Y_u(|789e|)o(;v^4?u^IUH%MOaj zRG;1;8Gwyf!f)I!xE9mPciip{*MPwsm#Z#}Acs(taOOT3*0}oJ;dq=2;KBH*`VVQz z<0w@_9=7DSkawqK0cWp0F8{Lpvg7hE&#V*vWyYib#Qn$c^~?Rum|^SJ@|&=(f4q3$Ph>6H>{4Ha~M zc!ty|F>h3ha7{qH zhm-Yon|kxr(TMJ=Pf(G1i>TLU*DL&HJm)r3uP;&WDC)&owe{7&yPmc`vtgE;<^wWY z1lPishFtW{T>BMCss&>4JD_A zxGJL4rwy)ny}yOBDrV{q1A-0w-fpUwpE8*u5lmJeP5}K!l(CGLUEzIgeqh}rQbEdY zgZ$jS@W389y*V@VA(h92GthjdXV{{O3`@1&GEm5xbl3{QjEp+$?X99JYtnoC?ws_V ztoTvyvL`yvifv_sygIaXfzt^^>ui`6-p;elpxrn`x7@E!}S!8IeAJ@RG zWFjnJVz`gf|JleEzbSo3uJ{o1luVNc((hn=vl-YVGrpgY1z?!*jceAx7#JV%!x^G? z$54@ngn$*nPZmRH82=(#Li4}k>U4f3_RRya$o|-B6^ra8Zclk3I@u!-ptZI!V3~)~ z`RBPjH*Rg8`O*bDV+%g?v_1^Vbk6)swe?uWF132uNAY0q)DP3tH@K{Wx=#HIa}(%k zU+^J!P{>7h<6%0m^QuwNBk>hjyv5O{cS&5uLrRox z6kOUD?6wxTYTN5xwHCZ;om`vIizC$C)xpl0yQ{4yX)Ya?ZR1}oS+G0&m4{`m67y>6 ze$Z>WGXv9em)jY=1~-H0ZfpjFDuZ2a^M7AG1?&CD{_!tbt3?f<%9*h%aFhWd5S`>Y zp|5mqf#fHI+cWH1eN#UK*l~3p43L)oj%IofR-A{EV{sC4c`IX``JO=CUP<$;zl!e_ zyl;xBhV)Hy`Sq8(n}q?9({|Qe;#YxD9>F0z z3t4yqn(id{dY{v!*N@j)jyaS@(L5ov?6SCql?}bZ??<||D^^)R`~WrY`$EPG+AE8g z-bz4&0zgpxqY=kHxRmio9Au%`&XZ-SYG*^q!-8*{OKcLpKiqim^IwV{h^3!VvmX+sMm)fGP?d#?^hkfI-V54}#v`_}Ehje0SrIGE{1i6N~% za&|OZKZVL)o(A*p;;r`edzzD{_S4?uNTAl4n*#~k#->)N-e#}bbj#=E)PlI9ns-HP z%4jb-y5y}|2hLd8PADW+K!fZBE_fPyuijwweFvo89k+iNZ%zwUFlzInYS)KxJbk)k zPcBfWfOyUE+MrJBZS{B4K$>zs@nO=Je!dQK;I3BZEY_>Pbb|EXnjpOfD*1XO*p|10 zY%4Oi$ZKj|$p&#Zb!o(Y{{t;BUP<|fvZkWY$MdK321zSa7CWN z#Ugn)fE~|(ahrC4p?(79nxZj?hOxe=amt3U>sa}M-NwbvP13ThzL|^YUF*YC*a}mA zq0u0ljrhoz-N_**2YMi7pwazvS|(O8(T;F=bG6}CmKts)PrZRl9vS0&voDKR$AyfY zO?gqu8$AngveI^_zBf~9OS94%j5+|p1gU|rxbQc%b^W7Q)44`ICSjC&EBs@Sg!;!i zPzotvXMOV%x5+wia^un%Ux!B?#PGXS^3t-YWqp#(dvVMm5Txd zpq|#J7=pE|e4s3S@>z4dh0v^u^{8NZ@%R+KLG+(EsDnc4%Y)xq`p!wK>%dCnMc`ok zc@p7~0m^?{kLO6L9?v-JB9iVxtp#3Oc4a=G%Y2&)6SuWgTv4Rx{T%(BER2NSkI*%P ze^t0HV3k*?=4OzJc4@opK`@R>pDkx0Q@MytWuz??Qj4cigOmD=#>sClZ+}32b=q5#`S~C;shJsZ57(l9I zibks6*huxJMyhWok?PUdq&zyYQdXoWd25wNy*~D)u6y15ibEphZ~FLMsJSX{@LtzfGjnKAfFzT1tZ~ zg4y-fQfF*}oDQNTj&McuMAOiG(@>Fm>2ggC{WA}(hl7ufzvk2R-!cH7RB6vANF0wl9+{8H!?vgA z<2Ko~v+f#b?>KE7w|;@wYcqx$kDiYTU4QpyhnLiU-SO-H%eSQeyZ^oV&p3Ylt-AhK zKYRV+4`&tR%|IF)8#`Dhf zbrY%l5-zY?2ma|=7l}Uo!j3oENIfM4Y zlIX+=a>Ku!$tR7PB$=vlo;0`l!Y9jLSPrV+qf?B zD*xAkXNBJ>E0#SAu~5Qc(e{)#de15)t7&mmV+$-i0AAbTIXNMX6ig4Qftcv?YhHLLbH+LxywUxQ zk+q3Ewj{a7Rt(Hi623PLf^WXfZ{R&rJCMTstAC#T7_JGO%c;Tu&=%Ud)$2_R)ae(g zE`7->2D*l!D47|YI)m>VjNRekB0Zu67dOP`(HNxBw>cDA|p17eiELqfLDVF`StF7!kmc8 zQWLCr86A%vc11?^O)Zw5_16;wOMUY?2K-8L)U$VL=9`nH>TlE&>=sf6>n&<(h2sx0 zC2oF+mb;k_5nmWB_YWu#ixe}qqQ<_dCBphA1++wg8<-lse#qvGZv8NNWX$HKA)hLC!alPaq>A` zeU0Y?q{I*k@1YIMw!ZI85g#-ci2C@v`I6ZM?|OR6s`KM#MNR>v-q=_8^ie2wBF4bI z73aqtVoD3o2V(g8(q&efVnw`yCSWW;DALkVAm*$1N*!b`Yw!_k1*j3cLQ4u(T9al( z_m_wuFwoPW)wsgTYMaNXx!*`b`BdGCHyAn===HSy6+9ati<^Wt4jNC2|8PrK8clm) zd%MJ5#o8@878$!To+Gf)dwrSO?1Uv|`h=tv3GXO;n37fGXQgvjg|lK4g1fi0#33AV2t&`h@Ku_I6U_DfHH=ib_keSkr8<4{iIFIMr<}W_%_9Ihjxr{T- zf%_y~R+H&Kq#|~X)W7csyk@)bwB^w`Gg{d&wE4*<8HmK>m_}Mq{YB52Gp0>;_KoMA zw6PnURe33G5ShkqLwvMS16{%;isXG<@*ep5aQ(4iA=fh2I>qMzeB>_0TKAVh?}S`f z>+aC+Jgv9z-F&wC8-h#gFtK8fdanOIuO4b)mD~DGf(iBHSx)PSmmm0(o@UO^KkB}q zC!C{49@P7v`T=f)na2J==<9UH5LAbu@OkQnuR$l4VDv8NO0>y%PP-u`B4G*wleoH* zEGW+e4y|g}vt*!Ax^X{U3V%*3M;XAJz>6-K)h?Of(v9mSgAE8b&!rn5mp5Z;o6l4C zFJx>QpSwi1Svq%Rc!YfvEZx{H+4#AXtu?K5qXd7{lc7d1m%JJd#@DT&Ai$bkQc=-&xO4Ma@HM|OeSD`>i zh{% ztULip*Agl-bqiA7Dkv7q*2_`Q_o;Uku_Qd-DaC2s{GVmY!Y=-oo&RM(C2^CtPYSw3!&kK5$q zcKH~XFQFTKneDukj>ocFCHXG-xLZCp^U;_2AfLH9V>eH-Tl8f+|8%d)tC7UPjU2H`!e_PbZzswlzYRnux)$ zphpg31EFp-&y?hMhw$eqqZH+j`UE|Vu61!JlBH~Amq2z9OU~O=#)A&eB}S(+=xK;+ z7kj@68CKS(&X}zkS(luVVOP@9d+>*$|@4>B27oflfC~t)>q_W&zP$Yf@{T3 zlW>KVN#V-4N(*AH!FA*`ms|vUA#~`QCxfY-Fi?;?Q2bxEi^jX?kBYx{4X|7~AVNcb zQ}RS(TPF@ZA8Zm3*hVH6F+Jr@{43V1D(oc35SZg=M)+!6F|WXiM;wReU_=SLMyl`s zBt=FqfwK;-16(&JVYX_3{ojuoA24yt$)B@b0g#g&NVEF}a=8X_0|$U36ln?-(=+wk zoisE-IvMSiJFUP3nJTO$Fi@>lK~huSM-+oDOd&WN7Kp5;HvibJwA z)i&&y>(vKlE3vY3shGiKX*(XTX1HVt1l85Gdb8QoDvL(H`KJ9w$c=gPxBr$+*||wJ zB=csHo#&?Hn{&+@YoZLtI!y+``3qMBr&{N8sp18UcQT-Qb-C%1n4|yM+#9y-fQ)j} zF4_S#&Os-j;pK151!{4r?sjZY*pL&nwc%#3F$S{FurfV@vRwj#@Oc_1#9)3{yj_1& z5^sa5>5%3(q7%12hOA+YTV2mBWpkPe)Mq%HT zu)7i&yGhc5Ce2F-G@X{H=QDt;6MCF-E`Dop9++Wc2BP zMjY|;)r|82AJ#eCh+Dg@9!>Z<3)^JCb=5UkgXF8LrU>$QiSC(Slkq4)hj*!O+{lF= z-QG#JCB#uRyy&H5Lu$rh8VZ#h*mlWr#4LlKR%$F1AaO>_TQINFy;=KBcH;yT10}Q+ z+z#B4(V1N9*>O*A{UAN?e5X?!$-&vt-P{$^GJ1k_wW( zPR(CfLo>DN+qz6{qKx?GSmxxy(K&t(vsR7cSlVT^o=yz8alOoLVE2j~&WUmWw#LM8 zX6uYia*1x0ely8cBjUm5#Zt@YTP63a|JXTjf3eBxNO2kjfZ+p?xD%)Iaf>0@IN-@VN<4xgPB}Rzzeo}~| ze}^+4K0rm-si|Krg?6u^eRIBAY0eAzh;E8zYTE6)g);(ly9oMSEUpOvv8XhLC?o&k zIk%fbMB*h_99QEhY-M0Gx)ZC&eI4X&_V!IFTN;}}h?rtSo4^Xx;!I6anXy$Y-2sU~ zJ&tC))%VFhK$az>OTD0kPhAcjxGQbn`MlF1wCdGV$dX7i9^?3rt=J>(z{j3eIZ>BR z5Nj{%$?(PMsUPCS=YOP(7HzH{80fSaW}tW315FvAFuU=b&GrEI{hptyorDCm+Y?XM81l7x#^OR;?%JadQ_$z$rJvY`I%3*%WP;0mzne>pLnU~ z<);)ruiIMh=QxQ>Cn;K6_sD!+^gur^0W*iv&oUO+3`}p{4uv^_bcsMZHbKN=>f`eg zb2(d79R0AWOr)@mC&F*aJa)$ z$ioZN4coOmJSjaFsSoA?g4uE`A#wyS`p?*;MdX>%BTwhACBca8ir2vwbxET5Xt{xe zmJ82`EHuZ%X0bD>S54c~*sdd1=q8d4R>%z}a4f>OOBGGmXyIRK(4w68DR;Fi4NmxF zNNOrs_muu;1ve+)uV)+EVF+!cM3mi6|LS6Kagv zLBZX7@DZ!6ulq8W@LT?A{eYZ~U~|iB2M+%6)IEp(7~OViEJuZgy>;#ACm-9dFObeE}6&+DNJXHji9i^}^Y!G*kOgnA%)}Q_%^L3q$*NlH)HoNRF$?v8jdk zR<;~@$wtU_Q_o(>wMFNuCKtQ?zHX*H^oYFwxqe@&-@}_p7ts&`S9_CA3Js#)g9O4)QM zvMA;4m&Gnp0_bD+m*BM@a`POXUaCdMk^k5v;()}6g1Z>eUpDCZpDHt(7*Vk#?9>U3 zI>FVKscWMyd(f{wL6+NfmH=6_lRsSiS;2yg9bgZP-yT>$t16H0JvA0S-pgG!M%4sE zw@K+{UHYR6!A(8&rck^9&S zqC1{k5Mk-ZZ+;-nmFv#Sa${M97D>X5I^j#YgE;k-(6{cylAJ9WR_F{_gEQFkQy^N! z8sBO{WsX9rnVeSK(9cKNN?}ViHCzK0R1q&$&!Mf6J@_LO^J$^`20z zpsxG%$&7l5Kc6XlSWr4Zr8rMD`TipL3Us~)$VVPMX?mH2FSlmpS~+^@Jhs-mYK}F_ zr`O32lFmhQAqLQ!!VnU#lOl`nx|HKAK1<8+Oi$|_0up0C9 z^a%KR(lE4UTe*g9#dN3CSkN@b~`26zhRZ)m7{**HdiIyjT&FAfz;rb~6E*W`3-uSK6J{Z*Z?BPGEV%9j$S>4du^0Y?zl3MXO6 z>2=^hID!?B6MrkCt&xGlh)E+~0LwmS{32zmzqT>l&@FFFqqolZNjI>pF4CM>m6^ z4`s`pqciqT92mAc^pYf8q!ae&1i8SV2*eq>WA~&c^q^$R)!BYcwoP&=LU%gdk4i3k z@lo%;^ixIOahspc9;2VC^&R~c@ZVY6 zcmIF9y$gJl#nt$~n{2`Yi@U%AQC3ZLt7}PZG}tCCv;mS3kjo|^2?`{%jdYu$#jp#g z2+<8T%VR3F^)0sgR^QrItF5&4t=MW!2qq|UQLDvT>!r3G3{Jn0&4svcs-ZbKmY4mX*x%kTOCUTjJcP3Y zaYAY@EFd^VLCV%n5To_Yj$yj1?QaW2>&&#j4Ggxyy#)-!cKWpq?v2+bwa`w2Pu;)O zXa8UJ?|)`W|I~ldze&1(0gQ^Je+3v8=U17Vp(A9>bX4JT@jGqsYr{?EL+Bj+bdj5anr2X;h z`t#EDf5iE(=ht_yv*wq^zs#=;+wO}Q*Cgi8zdDV1bJ^-RG@>l#l-P;+kBWey=$R>R z7IhX+5K%$o{7o;esg1qoG4`y^>zH;Su>snBh2p`4OQ?4}EpJlP6Wfs$e75C}L>lZS z_qjz+Y)Y&-t)t*V_|?t6^HTYP`&y2qv%etOpVIB)lxtI`h(nPhh4b|RX!Kn|(^$G5 zL%DygL7}Lx=n0FmAbq+QFO&q-RhTHbHA+&aC9-r8_S3gb|6O#pwdh~hh@jt~CX z=w9vF?BwdT-P2xa&+ZNOv>Y)vYNv=z$mhbH7R^4hp;Y_AMje*mEU_I44Ugrf)z}dg zFXt~k+ZXF{#@@|u_Z6?t0-5-w0wb6Mt$&{3z~4?vUcCz{9@3+ea!R+f=C@q=+1eHd z+?zhdL|HL%alkqj5HAX59D!lPzpg%VR2fn~bGMCy{|w{f&lWCZ@`wF<&C3_{!_Tt78BH8H_Ptp}%3;|dPID`KzV zOi#`Tev&cjS|`e?o)w#(c~rFFqS<(!Hm-IUmpa4oRD&vMv;X=7i7;sW66}K zqXfwWpT=|*`J(O;4bu24F6ldC?UmS9zk7#iOmb?lTWv*%)}S zfeYeWDg=_RI>SFsK~ijXJ)|xJ5}+s(+Ct0A=|mGK2-8*>P(>0G@=aux^;KH^`9Z3d z*OMOoy=E<5*`YK0lI#N|=)-=i4>C}4=2WLsjM>VfS)SGl31`Ur^bErwPPFYzuaMr~Z1?G?N_OnD@_16 zDgZ$7Pyp^L`bYrmB-?NRB!wRn1VNUtq0=6p;W_vKBVL}Aj3@EN`1Vher-$Y&;vwFA9IM#{@5gqc;ILs_$E+;l-OZu*+qng^ z$KJF@-{umo08=%gKe`+YCX$PFp0%H%HR#PzqcjleaGg=5E<(-3sv3m{C)WZavR4Iy z`_?>PqmCA7wnpM)Spp?baE5EGgURse*wsX>9j%@hg#=TQGF^^HlGbu4nP!ZQ>w}w& zM{N2${eFb{pKDGe`c6sGiX7GQzb8x(SY~2@8B(2GGg)v;V|~d>>YRgrdo*Ebxw5}I zpBj2!Vv^pa5|dn3JV+I-Z!N)d-}o|%1Hu?KAr{Byh+A}6lo_7j4un=s?r&sC%IUI} zjhZ~;Y9GSFv)wmMCN+3ut!r|pyWPz*?pHq<{6lmk6uYUTBC$r)wwppao|=V@osNU` zQq@%fObQ=Ac68G-?zSBe7-O&g{T3mZcEsMzg8byAMt`=jJs&>$-+DJ=^u2oY(GMCt z{{6{O(CuAC+(c8PBi%$z5Z{B@&sD463nxS;j6HhF8U1hnhzYmT!JLyl|Lwc`rqi{& z?8igu-l18^lFw_eo};0+?^fLxP#w25G{%Lz$LKP#LB8b{7zhk6?l9w%HEs6hky&PK zyZ1bCMA&a9XVZES2sO#jnWa-DqfgeTFVccZg-nsqH34I>!&t@Plmjt~$Rr~tO!8l# z{>oK^bbuQ3g{6j!OoMEe(oPvfxDp~f5Aq_K2aBb}#DpUz>C`Ej#Jna|m{ViF>d)8usTUs6&RbQhT*P`OFlhCNDoEsLtuH+ilzTTgN=_*h5 z%MgbtZ(0TE@$$&XDw$@C zjBB*?T~(*%<2@|BWFza$?NBovzG$!-1jlGA_GHPXbz?y%mL<;Y&KeilDgLt(@j`gxfuATF}A+L zmn$kInmB-&JUukn0UykkpEYlwFooJ z+fGjjR@U*0D!J&2e|nz$9TVbj;qwZrDi2@`Gs@6EZCF##IxMyesM>H)Eh=w#! z^h}TA0^Dtwb!iJH$%h)t&-HMM1oJi~gf&BP_q-00$m;QJ9KZflBjjO^$q)W}ZSLe} zV0^X65w{5rQhgf4wE^H;BKON$5;r0Svv2R4HXM|5PY$KPn1W3ttI~U^I(m=3R0v@_ z)~B(k3Ae->FfM8XIf!hG{((zR92Z1g!MC}$=oRyBeF*mzk17EtpmPy%8WXc$ zqHSgqx#+5<9*?s~JlDS|wQovn{5EPegZVRk)D+@W<+`vlb`3V^CB`L5Gjy>@=SMQa z+G*)G+9o}A12Y0g2c6m`eb%+fy`5Dmmjoya1iLm)Tz{&T@3SJ!+X8*7mZN^y!gg=o zxoY)bciS7RhAkzFT@kk&NpxcL2(fR7#i!3E5f4INdvuhl{24{{SmDFKBO0|t$Z#5; z)=B-=e2tDq`<0;9V5skWV}8B?JF|B^ThVRD-UpWaDf`?HboGtZv8$LzGCcWHdXK%8 zUGCY;&ef*fOhhITr=oS8sH}=uu&0y=z`B{(^mY2Uv`H_D8Zqc^djf^M=moGour zJF5C-!^J?A#-oez+$u)M1W?|5n)g~PTGe+J1suiz-PC)?Y{^B#;@q|3Iag@!-ohXvwJLW@)ilu@tAIgN%ZyJ=$*kl1zkS#0@v*G&Q) zzAAMC(iRl$GrJ6pGx23uFva9VDQa*&Ljs3z4jOOlmH;8< z;&DH)$LO8XMdAF=l>YkaI^%71SSx3EtQuG!J3OhYc)es&{CWVcF0DUUfU*Ie-e*rW z7FX)VJW$7fWF7nSf&;QbVWG#_x^+JzV5vv(U^!P#Z* zwjT)%n_a-tKSL_hn!&lSC@%V-2Wt$275KW=b8_ihUzfzQ(e>A&yh#&z61GW4Ey`=I z4u_xNki2x4c}PY#XgzBYeCl)N-IUaaTU^`0WSDweFdV=DgK-aUL%7kptagyE^sA{t zPH4rMy8GfQUH&yEObmq=55Ui2L=7*XcLtW$Rq7iS5M<0MHo}$SlOl;JW6#;g&@Aqc zy_t3F<;jU-e=zo*{hqpqQ;)IFQ0fOfY&sl~N$U(MciYbdTeH9x_8Ab8z5-fE3)G9KKBW zHq_+OXxpvMUZl~c-)R19rc|?6eJ$CUFX_(Ef;ZhEedhXT9XfkRhuEpr>B7s)YS8$S zBS7={W|xXh#U-;#Yd$%!OZlIKK^j{e+BA*uztXi)G*&^}^IqTpNLxzM>8SrnZ*6`~$dPp9iIQbhq`CcF~ftiLKav=Kz~-&eAU! zWA1sbQq&ONO^EEx6Dim(38wwqB(8(^Nfe?Udxztw;o2mx$l2l0PtiXcvm8dLR}9A| zgzx+V^5xz2>euKFHlic71i-||{Iqa>@f!6FEVxi{ zMWicfp%QLMB@9LyT{=E3)GbGN7%%KYWP<#0ZhuhC7OZaf|GrXx=bPV8LBySeF?x%r z24EVc+y)RW+R0<<6V*%GI>Da{-FOo0T6Z!LS{Gl(t*%2yoO6o%v{M=DMkyx!r4~m< zvt?Fu#nyL$)vRRI{|4n>Y2{mPeJ>i4A8i&q=R~rxz298g{K+HCmdIGaohOOAEQ!M+ zD@&${sD=yhW>Au`x@Trbs@H?3^HHDHrmrQdywNj{aT+&bG&lKY*^Wp!eY2 zbb4t0B}us>&; z?Kx8IMaD{DKYyaKtd5tyW(LH{1C+iJ!5Zeu-?DoHt1jQv3h9 zjQvfnA_%`C5z1iAYGQ}-jh*o(e>m4^kTmDOP*|LTq6Nh>miBS@(Smvsb$3aM)*Y36C0gc3qDIfe?fRxayoN5B>jqS5|X z7#{3l$gWnLiq529zG3^c9Nr@5;1M7)o5_?oKK%ns6ksBlrJw$7MA5L1QVVy~Y|}27Fi? zM=vNs&GX1b#NmmY^E>&jgG~MPzfL6Lg&ZJ>ZxEZdNx$wO&H=BZFE^sDnxr8T=BAb) z<+_>37ix?h^&RUn?4x?QQS9khoRQKU>~CDsGJ)8W*>b-$z@NTRPH?4Pp9xFa1BZ&C z74}kyc}#x?JcQH|_E0&m@3-PbZa$@*D}TG0>7NbpT3>IuUk1f=XQ}rCqf)G62&!hx zb)tRHwZ;+KmFS+_dF%lGUL`pTFHp|-h5TvVP{PeX94(d>g4Bpp&tR3KA?m_cAMU#1 zGab-G{8$F7oRUT;8!IhtPd%n_FHb_RXutJp>OF=2vVWPsBLC9MNWV|M7Wr0}p?^h= znybvPx2`L(Vdhloj1y+c(|QdRYC z3q`5$(r$p@dLy@y-dx(PLQN;w*wV3L_4v#Dnu$xU!g!0*C_Ksh8ZGn7lb&8k6=S$TuzKrw_Hs!M=UkkM4 z7_+=Az*%0A)Wji8X5wl|T$bm3oc2l{mMnNmN&gE5x5lx!vj$(l+FGqilK0_~YKRMc0Uu67meEs5+o# zrylmAD-McImmbf;VPNV_<0O3>MnDRNUZVp9CX3A+@X}?}$heDtc4LlLT~3|QX*JL7Qhq{4c{xYJ61Q%gV1qL~#xa=4xFGX&_!;A~^{UyUfot8s`}ZTS4P-9qg5DQm z8}eWYz4gqx3I`L6^#z+)6*6XfLvq$r=e+SA#wOQ|Xf!u?W1%m&z}M)$T{9FWBCNm2 zV;SWdg!ir2mdF{&VUD7{y3P}Y(+aN`^?5D&^&43UC7fYsdxNx%657{r=@{JOo_Ub7 zYapnMJ;=&;mDKpjvf3l_AE%&bJm*Y)CiX|{``AEz(J?{QG9F){%6;pOP0y@%8a07n zo$tCFV~Mjb7ZIArm@EKAZk9DC2Nz^(!e*QH5L<@1a&pz+Bf9n43BpZ-7O{1>-*W2XO?(`g8slrsUl}t9cvT+wISK{0i#zsv$CwO7kGaiMnG-&*-grT65i#kJ z;A*)<&Wn5@wt-PzkS~*1W=Vx7V*+3PcbUNJC+nFTSU(;!u{=Yz32qeP&Lx-1A*see zs;iNUG<=B5G)cb6052Keu0kAkag2v>l{(o%jnV--kt?|q35j<>;$VFBQ!~KLwvIZF#Q^ut&{rDOngMn#fB_z~|E+=K)+MU_w8gF` z)utg%@!tpbnD_PG)O|gn;3kMl$-&6H=E+4z!==ki1qpgqpr;X6^F83nrqeea@dFPdCF2oI z!!HLC$A(Isa@9r4fiWyiUNSmrRY zgA5Ge>Y#Vj(bG4wUcCTOj-iH_E$`v_OD=InTXcpIMo)Z}v+weH_1DYgX3ZhL>Jd&D zHFUw@f4faPbheWro^V*{0+828{$n;cr zZEEV3GOp%|i5Q;Z%e*LhS2~Mvx$;HxJL)w&?U%8g?dd6{z^`CtD6n~fx4qKa-r$8n zq%Jb3gI917AJHw0&1m5UDUhp|Fp z%^B?))NbUao5fgLw|X|!w>N4mgw#7DIUR%O(a&{W zL)t)XktJ+k+H(JY&oIQ;M>%B1c-MccCM@bf%rM-g3L(VmIo=>w%O>qx>i4&EW1_k* z!3#Rt6rOm4tA^ubay7*-YT=GN4(zIQ#w@(WHNa* z;b1#hFEtheYjTEAGhtsv(vYLR&B<4|qgvsP%J>sqk2-#Qwo7jWIoL%&^Xk0Zo#p&S z5M=DYM?CrisqtOGp8*7#PD3AOJ9=k3gzCnF&); z&Km>L(k&*>FBlGLiV8dMFncTeWtI9}uC9JR{V#gr zl!7<3gB3wIf5n%8V7eTRa4%sK1pFjN;+0$3;X+Ip^AD+dmcQmb_K(WsJ){>Rx@mTy z%UgFe3k!5^NWPlL68j@xt#KfH59_f;O-BY0KVQN>%=X20dg+R>&|jx6xRIF`FJ#p$ zOG+m+{`*hXxpxu!xQy9;!`ZPGrCS-&q8I53%QryKKnrW_IT~v;2N{TM)Vxl;qgt&p z(-{tLywTe`TQfZEjl^b5FIunIXBV?Gn%iXZehPhh7+|0ARx@bmt8OeJD&*luP(Rl zsU7GYl{0%gYD6k6o-*b;r-(y|;FGIIH4_zMj~dlRKM3~gxXqZ@;kzw_2$It@k}*+NL92j7#A@!099UjP%DBZ4 zS~ilk=$rDmxbom4E!ef%LsV|)xle730SYZ9Yv8>EG@WXXJI;%BIYjkH;4+vA?1Q`2 z%XmiJba+W*WUaa(ThD?q%^9=noFUH`>{dFF|jU48;GW15#>PbTfz=C*5jA1~QkDz z6nav9{|5RfIbkmx_ZpKr3hoU_c~Fi5#NodG)+lE^@tyx$!7>j8e8ef=RB2xn++HC) z2}8#viQq1GOfIzbTa9GgrC1Pl%Rq}$p-)K56^`u3@uco<(*c;JvXf>1C-FwC?1@PD z18eS;tQ_1xefE1+jpitK$tcs?;0_t(YCX!gNp7+VNj4^#`On%c`*4x(KL%saM5b^-e25a)@EJcQ_u7dqkW9--wb(&y0Y+H!|nc ze@;JU&ZGs?762YsNphcB#4 zsAn>*MLJrbvs-<(UUkg3vj*ul_h{;hzk%!7jt<8?1}7Vz@%G2?PZn{a>v!;LjGS&I zGA-Ts>OzoRn?!aJCJWj7)Um(nRvR01yX+25k=Y}RN%Mut6|DCk8;8VMctAEPd<<=a zI0%xVz1A99ljaDM=`|EG`X200)!U-qHcLpM9&{mvmkcC@yVchP4vvA2-!#Sp4aVac z`&6oZ*>ss0Os=l)2?UOg23HT-8@ld6fLMeO&g4THzHtL{VHOQBU;-lp|g5BO>3eJ|q0rB_bK^nF&OSkt8Ppj!n|PaA1G; zsW<1y6r|a0R)2eDO|_-lmOe}S2gUz`xuEu-AH!Po@-sdktaq%EyF+H$7gO}6e|4>% zc}e=y&&+!f4Vj^|rek4h=HU-XU_q|$`wi%4Tgql0)j){v!WKo_Z6PQM__aSa&JgVe^GN9;wdRl-PC8dHILDB?pv?(n57^8 zOCGZ|HLoEdUp+@Qlb_YQdh|N>aaqUOs<^^$ZR76PSJ?pMPPSZTFDD2#jVe#cWz1`% zd|EUMA4}o37=m>h#L|zPrsEKOy#keQFPm+SHl(NxE8)s$)?Z(xR!WBZ{WsAGGG!k> zc&)5guoH6NL5z$CwG_7^Ul1X}D`P<>BHoY`0hw*_&w_~kCL$hRD2Q0>kWJV`1a>b; zM6~}Ug@_J$#EX$e!hW)tl|`F$|0CBKslKniO8WgX@pqz#uu?s+pFaYB#uZqS4(_L} zS~?n&9I1}V4Ej#8n=1uoWLR?${d$^ns?=<5q+&ZU!BX!nFjY1}>g>M?aGqEX+B5Kc z1WURQ?FfoxOpAO{!Vj7l=%!>y)oC_FW1#4;+ITR9gSOXFIEc$*ww@XJ>M645r9t33 z#yYi%py3bjd%#LkCtpcv8qWQ_Fs8DSe%j&qsYyDj%)43}=U_jclD;B{Hzo3^OBA^- z0G(W;cr%4p-ae6tz{-7&+qcJ7$<3*FX4L}NNs=_+GF5AjjWle>_QzhayF?w0%Wu5k zZ>NZyTbudg-n3UH(JYrWb!9I2Ypc{VU;+SQ*K!j5gt5e1W5S$e!Tc-hHCxP6@Yk{K z!5MBzXSh!o@F5LcWoCd*ehyOxx-^H!0vx`t1RFm^4AKRH%bU1n6h^9yhr;yua3{9H# z3wcbgTjuRu{1)A+Z~cW+Bzn4P`?(nv9{(eKsGrt6hJ(a3bqB9N$h0)TFUtFkP_U_Z z$js3fUCpPcDEZQzeTY2GF10*WZx;USNTZOjAd7{hu>iO((wCh2ep6_h+;1+)*K3`A zej>AYlP=Ef1k9qltwgYrCVb%OT#Y$L>|zL?oWPph>eX{Hy5%>^<6%KlM`7OGn|_-{ z(*8k6>eR3FCFWf2Sk16(`i6CcXponQ&M!Ale9PIw$w|9kt;%fhS1*94ue+MZs!K^m zm(d#V?@RhdC}Rfx#;J?Qlg8g#@-%x?eyTq3_hl)!(!a>U;YHTA0ME;|gN-q_ieVv~ zLN6zsY2whWUixGb2UL+y70i_kstMv6glg6~lT$9w-6l@9@W1^(siMs6zaB8BS%OU& zv6tp)$4JQ(7vaWUbPzoh&f@Tga~30KKo40p1>51Tn!W10%!XIeurXf@4Vxz@H*eBd zs*+boMa|p4Dx!Z@3L^xSoH~?BUd$^<%FLlua{Le~iGF~H1oJH_iN=__?KtxR6ANDQ`KcA-)1J8CkR-&0Zb$3wROYr zi-mIj=j0Ey_R17guM<$Pb>mbye3z2wiJXDZLmbj2)V+AQ({hHwl#Fj$cTHV*|C6|4 zJV7~;6u8p#5_!Q_QuFx0>LvW$RJ;DaqZSQ-E`5)W^&z^BG?YKl( z<&m{=eOU5&J)b)qTMa^<%0BZstK=;LzfV=70mnn0+Gu|-p_xuj0sM~4HHt&(-`y6+ zA;;~3tproDg6F2|HnJa&7ej+Qh#2Av3m6Emc|Py^dC%;rb}&+@G4frmx}oBw4NEc( z|cI|RuRHLbY^hG@Cx%Sa-T}C zQI8f7$`KKC-Lj(*Br!#Yb zz5A&|!_~?Lz&lrf;=Il2_%SA-9$d54hGeV31FNeCaB2ryTt!c)BQFV`V()u;7;wx1 z)u(Ra{bKV(o(@ECPW2nB)b|B8q)KzqaPUrfE?!?KCm2w{WqG{HD=3^@XsTF*R8)Y> zNNLP|9BY;tUbu{b_kpH7`L1D>fD3tY{PH6xG+g@%6z7OYzN3dMc`-NNn~sXtJ}gKe zKJ#5httXyqlzZa~9H9;_66&1l7jGmIo9E}XFDUM*D1oRBiC-+2Ooyt~AKsKD&r|@p zUwumpO3GmzlEMV5T5$CE|Tg#(DzNt1>X(Gzjw|3mEpash5z2@dC(rd8ZP3xLyP^ zzHp(OEO)D4&y>T!9PSUy%@Dqp&Eb@c(}O2^dN|L_9M_qBWM-(u(V-l3Ia*7IC%6zf zT^~&Kw}16Z1Nz(FGN$N>8uc#$lrzr$;ig*VG218ijPOP-IcC?WN3C*Oh4++yOoHYd zcu&U}w9P$QY8#sMG(1DDI&`|gM0v62BZvreCv03| ze56j)%N=C86T6Zk0%Bau1Ble-a`S$@xg>F_`zNZWFCevMesLG2k3r}og}oi~HJz#P z>4OpUVBFg$5{$xX3;Oh8?;o_-`}JZUkL|VqKkQ=99D(nx1bA8O53|@`LeeLtzAvp} zYC6|DWltOlPRJW?ChQV2Dp5}gsauaws77v`p#Y5y+0QM51Ta(N{$l$uiHjR{Sp3r1$PVA5)M?A^h9?7nESfG_d%-Zv2y<1d{C2CnH!r(;lfDpH z8`sLeY>0VsCA~~*BL_n2&>Nc6(NY;Gk-OFu%TQ*@HdFUM2N=cl{ZE+;-}M`vOCwL` zw9IQBk9tP`zpY#En#g=N>p z>Z1mUe28#k`_$jW$Z{9SdQY`C;t-6zcV*Ngx)NO1I@y2YbDe!>VP4Q=i;Rh%LMm6i zrRUDLL(q|l)ztX|mn?@rX<|SCK4I_K4*fd&Z*S_KXW?`XiCs#d{HpTNJBC{TnhM#cpd{B5Jis z!1eBd{;NrML@vLUE|`~6DVdqm-6m(^n&xcv!%1`wEA7+<^V*YH^lhVy_(I>{o!&|G ziQ@@gaOQ#*i~hCl+XqRT^;UAxNA27CJ@hTTmAq$lZYvPlfg-h)lxZOHmS|Ptj6PfA z`@c8XY@5Y9BD8uAHUhHk<)z{Mu+3wI1@4D#9($fj4}~hUN_}5|vUI*;hrFVHS!;wH zt=E;HyLe!mT`sc=gqLoIP`WpLSEki$udxfd=_5Ih`0xC+_>E=xztbw2QNPGA5PX%3 zGF`b2HxPW%J@aV{zdsdx)_4-7%-tnx^T@GQ^fpo3>MueW8MVyL*a5_A(kN<~&$a+v z@L8gfp?|kX^zY^e*3UDpa9-Fc;0TbBRwhC|FnHTKaWq9llgKRAdhoR9XXCGvqH)+^ZM{%YT&ixfOI>}xWa}zWU)@hmDv=87JL+83YSMFNC{Q`d z)Yr(Fskn-_ezid=^&~6xWL7E-p)azGG%*5~hGdElq}P-jpifuw(e&xgJ$JA^UHPYm z)u#&`%o?aqcX%HFqfZCYGW6;AHB_Gt7X0Jr)9E_2KHWaxf7J{=j-`gD))HS-Lw zPe;@LsXkrt<{8E9RmJU?x-wXzPggvgJ{^gJ^y%1B(5EZb`gFxM<(Eky`gB-fXnne3 zOP{XT(x)pn_34VWJ{<+Vy+;?=yr8(fvbepW7-m3gwiT-vz=!D5(E|E(sTRH@1yD_* z0aKr@*wm*h7JWK)sp0kMq*>9YOSOBgj41ka$!1M`x?+`0_3e$KYUV*_ME(9xWCJ51 zwe>YN@&8D-PV>LeXXG2L8yO?f7yl$kO6!ZWr!L|6S+9y{ggGGQ5U7p6Xexd#ESH5`=3i=8w;`o5 z3d!Z;cgUu0dx76nXNb-ndxF+AqJpJbb`|^sZxN|ft1rBqWY#MiJ1Pn?^iwO-b69g; zC)0QQ0mgyCE(88Y*LP%vCG{O4C6>M;Pnr6T(B7oJBX0)iJMt=1-*G8p`XTy``HZAF ztQqGGk!uvaSkmBU`*pfEeTH>~NOXhG=mk@SS{;0;zn~o%M@QH+7S!=09}mfJI7uale7EsB&c!j@ZHB}T> z_ciIlx}3sI9{0%cEB#_j8Tz~!Q-11q@(qnwThYqTFs9V6F{YI7=*w^tav{OByU73T zb%{_hXT5o1a4Kws8fgNm1;X<(&UYb`A+z{lab?Bg-C*7kdWw`!E53_^yGv*@tC+co~FZ+GAR@iIJ1{&V2nE|J)6 z{*BX0-M4f?5OZSt65LnFk!H90$}YK2jgD$;*iHu%DeEgOL)G?Pb1F@Hud=qz=qyTH zL(YIZo?=}U|X?@$+A&*uaVOtb2^c*k3X>mEHb$_*x`rm(`dG5pxm=a?3 zq#zpOgnjXfLUo7Ky-{Kr=2bDm`S_J!zUHgHP9_t(U2wKTOHHz6JQtu9Mbqv!BIhB- zz}q&BBJrK+ZOq;SlUwP<4i?_igKR>?lOqvNx;M45oXk5pq(s?!O6Gc3i#XJTRxK6i z6oyla^;Kra2GM(avCnBVI;R}yI-bQOLKRDEgUa>75LK)bsF}-QzuCEn`!8Zd@wkK-b;`@tzpa_86L?sYk13#%Wa7A!>xRG5J?WA7td7> z{J?HYzqei%uo`^KL7UpbYvBVyc1o<}vCc`!@uL4&RI~aqMRkbv>$IZ>PU~zq+u=9u za3R$gf7ey>?Wz`+Lr3tRmq!Q3?}S1ijvvSK2>tAc`qax*|Vg!lOEK{JKo z>5bX~VBq`khrD0;A@5fWc`y3hTkp50E-{2PaK<)FwMA#h>Pb0~ZDNNo0{x|${w7ZW|>$}+ePGZ~2-zk_| zdnR##7L6*iZEvzNOVD&Wuw4S1%lAApeM=FUf_!FK-|5;0)ORlR-7ob`yUi?LV14IV z-!ALBf2)4KB}Qh0&$sz}pO4fl{i&-rH=83VRU)>I?dv}|$0mn`$Ce()dgaK&4yKr> z8Ogg<$#*NovSr}AaPr-OqpXa9?-nKB{eI}X{N%g+L*IFm?{=B*ax-ADCEx8FTJ8uK z)qUt3`tDE3cQRFhGdrWsoym8P3@x`U`EI#cE)$mZ$#J@%-LIR zn+Gg!|40>2M=8F%5YPjm+W4}mz2(JX@f2S+t$kT(d|6q1*}UHJ5R@?yzrv}S$t@Ra z@$yPjrPrU?Ap1${h5}n}uGHOIF_k9y()GzLJvL#NovTG1MDgA9L~lizWN1jnjtz9D z&PQJ!a6SqkzK?Az!_S;3Sk=@$y!9Ox|C_I}xe9?h$G}~gw`7(Bvn3rq#aEIYnQ7&^ z^lnH5xuSn;4yiYHaN5^*vA7A@bQIb+(vt23XA68Vkx*=S^#8QB(PnQ^pPn~m2W{e zA?aaB(u2Ekup|%BmyCt*#hRT>Y!SUuV|H1{?C%f0uN4u*a$%Ypce9<)8NgPM4x>D^ zTl6l}L&6r%E`zghbyOA@_S!^f8uz86IGoOKG>WGXc^fLI;Vp))i<(b?zqkk{1k&W1Y@NQGnaezmF|s(q-(LDMR2F~Y z+@c^Iuj+7>R(H5MI%Rqn{+#xD>_$)5D~{`R#;-GzI$EVjba&A+I;jChm5pwqVe4?s zu}XG0O5?6gyQqV>+s2b!uR5-OSPJRl*X!a>^yCO2b{4&3x}>+{ZkI;8Da%aMj{@@w z$*^MjcWu#J(`VF*>09Mlc9ZTE({Gb!p`bk9F3&`YN0`rd$g@!A?xH7FOurM? zKH_pv`;EdM4b@}KDslHd1<8D5Y?*Dv_U}@~_O0^gHu-bA{JBg1+#!GN8MP^N3C({js$9Kk46wmxKJ<@HXY&27Y(zP<~fbYKb^;$ZwoT?kbgd#NNY!ZmNp2K8s#NZ;QDa zU5pona@#vB-S{0s%;I-!(SN@qe{bEYpGEgIe#f2sZNKAg{r5-wT@k{2{_mp2Yucv%TMNj!sdrx_TJwAWsir!7F6rE~| zxMC_N>iVrT-C3F!TqkBp zJ;!5Yi1WFb&#ipi56x*78F3&oI;NVUE_3mjRdif$!|9ee&yy`0Ggb{qsKYnjTdM9W z;1JnJykgZL2FCsC8R9A?a!RTf9A|(|!$_rO`H5C}$)xog^TPKBAnQ4GJr&DrYPKkl z2x)iN_?=~a1fQJIGBuo?R|FHZCyUv?qtL1oi=iRi|EfTV8lLqKQ^fY-fOGxQttg!rq26kluAiCxjhB#ce+k z(tjF%Wlty!sRC1AA$0$f7TrIrw>s#)s;9)>A4>_vU%EpB#zZ~mfgqHe_r*PkPVG$o z2sVg&6Sv$Cx^V3Rd^;`pN``?CNVO`Nz?vK?{VnUCFx&oz#O39?Y789^c16N3AfcNGxh%R1v$UvvEJHm zFdoo9V}%x^q8W<@7o|8H4j>&IUY`(n3k9F5M0>b>>7gjBRW zt}A|fQkm^IpKKZ%&1XEHv-wQs^WpsQ#q?N)FM~f$vByVQv)YTxUwUOq;;=);KXU@< z^LeKKEy(*&|85`M|CX*V(_h@M_2C=tKlK-fzc==q41aGlVETLGA?5FlEGd6)q!0A> z#!LLYkvxpQH<54UF=0}eySHZm=7!(jC@+|Xpc==7uFR2lsv6gGL#|^L`P3gD!hFiXqZr(;(;YqcXO?kQzAE4`oc}2(tu~26e?wjUzbv*{ zo|s5nxT?Jb?wl~y<0o)n$}wXZnnq)AvuZwh!+B9MhQQtZMZbNz!ycns!-DpH0(EG_A!jeWz^~DNNt^?IMJs z1(Ctff{0)+2%&C&b5@mFBNdGY1IF%0g^Y<~?M~U3BE{h&W|L*wo@qWArBIbpf03=E zpOc2v13=h~eTKI{^QbV>_2Ji(1p^pDdDAWE6X|YsAqtUFlv6tI-}x22`@JrKi4IK^ zWAgPfi2|0Owi@T14-hiOEK)#`E-A7zqsTOh+;0`}OA$XNWb{`zA|-CNUV4q)G@@;X z64k}XT7(gLUD&~RXQ!R z(y8HX8I_L8taRF-$`1cBU73~*O3Sz`w4yPbq=AvrGNMxk_8w^|e7nYq1>kMeDOmLK z8|TktEHlKx6>+C1{Z<0Y88+MnU;b!(=((;JoX1t27M;t>|_fs*9FZXm+?FF3(D36s>6%!u?8*# zj-MwrwzHUQv1|Rd#>kX#rP&};kwOpYLjH_G#T2?r7xKf%tQX3Vua1zwgHMbk9;9)3 zhDJp6mRlpkf=(kWS4uV_;$D1M+&sC=_FsJNu)at6%4}o#COUjTo7=VkD?&0*#HIOUrte|biED7{>2Si)uC#lMsJ9*IaIEzifH*^O!lcuDje8J$XuNf_!jC@227JGGqdDp)4^PJLfH>B*Fcsfpt)*^B10w|-wp-7ooT@!31~X|!hY*_+HH zi_c!6OSI||!e_@e_)wgV<0(cP2O6iS2ghYfcRs80hpZMZYR-~<=^?G1uBA9<8)HO_ zQ>D&GHlxKjiSG$ur<%=BX=Acd4fd=0?Q#AJ*cXJoMLRqi&ywmPO@e#jQWPoc9&K2yiJLuFzQPEqTPCdFbb`jBf8ZA!l=c`Ms+Vr zbfFqu2n|WRyENxji7Svibq3LR;Gpx1p3sWNZE}WUB}c`8-lbN_=<-u27+QxDg@#Sp z5jh2CDx+lPoV_Evt1k=T9yPQUZ;aN6!huH-gEP@uTplgcCe|MHRsDNjbZT?9et)U{ zT@m#+=g4nv4CTnE2;-S3dZIW_#64a1_yW(t9VE9l`3sK;G)$;`e%sVFkDN%f&hrUzPB^&er;{BWM-g=` z8Ql+c%84G^?j~L0LVc?5n__hLoy+m{97LzW`e|FOQ&UaMpd|LUDZq@nJOigV)vDbs z>dW`+k(uhU8k?pU?>8sBFEd~&PJmNHd+GoN)U;=^?;EPplC) z%T8d;6ntA-Gktc5HIw*^6LY4Tr2Fwpy&>@x_w5tMP3xvWd&7ArH*Wg(Z}fUAda=(_MdG5|0ARJQ>4 zhJ2b?DW?TnWZ?keRvG8}UFry^?kf(zBc*;axRkI&kyD2$_2kcSO~I;?s$~$21L7jj z7CB?ni;?r;Gctu}($4P0Edm#BJ$E%Bk&Vw$|FO^ZMc!){M<8O@W2QAnUR|a zEk>mzVoaP^2TR)T2Btt61b7%}`P zw`mzdj&YqhL=}S=Bm!v#?mglV^((C#&$Ag(%ONVRN5d(HsOP60qAqciOc7_Ox_pl~ zL%m6vbU&L8dGNwq@-=64wa#EEZ?C9Vl~x{Y4J*4{36iZ|3+ z?F}^vh4zMukJdoi8)~`shFTlgJR{Iv6=*LHpt-$_Fvj9iLZ|?2XK)>wPKWqi+{lZ+ z$P4j?DyGq`>zILFCKck?fK4e5VWN6OIV~nxBmPhW=x>YH(m>?P<~L!i@P`@*;e5%a za{iGjvbiqM9)d^*(EF{UPIVjA^{vruj8C=kduby#)r6_R9YBLyH-!c_3jkL6eW2DJ zQD;L5@rbJ5P6U8d%fVDd>4t5(-K%)h-WZ5or`h%So+|aygPL^rmTP9cw>%#t*lK&q zJvOz2S3raDhUGPNndvnZ31fiL1=iMyS1}ik+X<=VsJ~)#u)gG`C)T*=)IW z1K9@Xa|<~~009%_@Ux{j_~h~NwX+S;asZoPCX(nVs;<)+GBhhGLfSMe085iX)Wb;;H95aD^d2+wIm@ z*;b)$>p?NpA>>E{0`yd4a^A_be>o5FtC7- zX?vKiNE~Dj)1>WTnzTJklTAgw z38IA3a6#%%x(G_76tUo^NSz%O`Khpa+Eohsp;gb!JQ~6%Q=gc-LK_ANexzx z-BqOiyil};(%Lqe=b>maFQ+227Hobc{ubV1)xYioBGC~WCBObo<%FUWz2K!-eoHu7 zbR_nwg+C*`Utdo~Ugso@KL>FHTTH9E@L0-zU-BH0I-4niMBa$R;$k=Cy+xoBBvCSRgh$4;4S1|YQOu@fb*gMXwDW1f{ z4)arh6BbYXnhAuf#Mw4=Q@6)chc_pfpg%G$3xiVyf&Qy4%;1DU$ph4gip_4EQu zP_L&m%wjUIDgWe**Vg?*&r_wQ|4k+d@qak;=t*+6Yk6adh`IGYa~M^rd?{=Plo_KUjQ65r%O%(^aDTo z&^djRnWZ-To#9~aq++JDwN+@cF=hbFKadQWFrT7M+&cv3+x|8b=1r0|%Yh{P7kko=_f;gzUK9zm|h`i!(jSP|MQ_hKWt`c9ur^}8Pp z0eXo5IEdoSJ_*o|-ua=yd37x78%KT>6^GRkh>{kmm~`V9j}H) z*htsV6Hi}BE>9~g&=0lsVrnt{W1M38#~6XAnJ_4bSu=GTENHLZ+UdPk>JWw}l%j^<2br2K=eZePfgk)W&*5-^C|=>C5G`=P|U2$MLQ=vtxf5 zL0A~KxZK|r9qs;gT_E_!HQ6F1ukeEC{LK~qdmN}=M62+jhWYT!&HGzlvtywuY8%>Q znXr1OZr}y&T&~|nfa<4j#Ng$V@2{&1Ur9 zNQ&(&EorQD-#Ce>CG!ohf?8ptb_)(ytCFtyzb1Nu;$MCQMT`-#o!WP`4|(#g#4T;I zwCWt2o&mF7hEM`<;12LfiAA(qg5!t?V#8!`$a|(0sPq`FQ3e7Sbju{bBHEidT7fh} zr%rsZ-$qA?BcofZ&TLKQrq$Xrw1yMvr@Q{0g+$(J&68{m|6eS2!#mcpesg2rT8Y7>wLm0Nx-4?{xG_LfC$Z+^$($O z&+CoY6~4(#JYOevk%%S0PVUE1{DeA=G|7=4eZoa=&`fyic8t3Asl;Ka;}$DB7v+g+ zbPQ18)zr&{z87QQ(qll;HrfbyxiCH;r6^RpWZ( zR8{tbUZF|%a`h^<-b4bnQ||^GeG zW_Y^Z$VLg#-O*wX9+5q9Mj&{AJ@L{&wfYhMlsE5YugLqQ{h8OC9%FtQOmMGbMOn_W z_o!VHX_edag^q068{8c#@h2T??^Cx+ULiKP;GCGeHC5RXXF9uJ%e?cM=&iFJ9>z zP$p#6uqQ`<6w$&ydIr;O$tEIaK)Lbk4+86Mk(8Fq*%`c?fj zgaynC*0GkfBHOvYaV;|g4fgf(%52T~%5$UM6@{*`#)UEpy;tWzD-D-FwM)9XVGCd1 zr1J_z*KDCvsE50)M#`~SK)Kb1tA~`!Q}+)pM*+%B&S>v>k(v)|AV%ZY}byG?5@ zSnd6zbVxaunl`wcC<40M?&EK=f1j0DtOMKgD97M(4oXDUCj0i!(2z1NwZCl;PQ;!S z?}-*3_eO@4ajM(RG7$F3Qg^Ry={ZDEWjh%F5Wk8#GX?-X>8IwF+4}huUV=?OpF8=u z7{>#AC#R71x5Dl{!!)*-V;Woh_%H7#jV)LXM1I+JKAYBV_07M_hVzNrp*h^RlzPQ# ztsiD_`#rqxbE8D4O(r7dzK_Gx+s$%yy4=CVJ4LgD3R z4LkoPJ*lS#3hR)nCPs98b@AKwQpc9VkkG5(bkiw)!*VzpNmTT9+j41JHKB1abc9gb-zPgs7Yu>7gK=w_9%br zwqOH){|$6&5+2(2#>dKSBx)`7&N$&`i5-hZjIrXZMP5zE ze9YD&cJ4lWIAMjr#2JCJ*B=36)h^kpU(N>0p}8jky}kZ<6UhAvQJH6n+;J- zD7;I$=OAA5Z$x!NBKmr$G#`Fj0LNxLw%+MTbWFqjSOx39p>f%T+IxNGb(FThUSX6r zub7@?i;P||J)4n${y6o4tH*BNW*?9pdgX|%^V*|srn)1XUpxnWQ*lz2q*-!a8(?o$ z@-4lhl9p=l<6$V7N!F75Sn~d>H&-aGbPlwOLaj|5lK9*U>qXG%!ZSx=zI2o#y_Agl}~J`dfbrl|fB! z?c|GG&e%a)7>oUN z#wuTZh66J^(?)S29Gl)bO`N}-_dEH9rimN0t?mK--*gWAzsYy><;DhPVR{P{KHMY) za?e|!$ptsO%{J|Uh%IQzH|3%?GOpRdkG*%YcNr8x6}dBuOg4B@CpqMO#G9DaNE zg`EQrfcSWP*BFrq<-=)@xUjQP{3{!it+h($P8s)Cd zrKMu*^bgs4Yl)!8x{+NDgEV^PzR^dn8sm2VBP0>uQv3x7uT)NK$~_!-xUn&%4-@gwjxW zKgl)fm)~JO;H={nbV8^Sp{30uc+OKVueR(c^VI7+iX0(NowkOJOAd53Y8@pxMoKvg z_xeoRe;wlyVVr8U`;R?v-Au6j;1Tx?(;>ASb^9tPvsj(Efs8m9O-&Pjbh-RQ(unmgFMKHhIlIb&IrelV5bri#n6e53b)S@6*du{oYOn`D_x>7qWAMDoH9;kZHjLDLR$SiHZePAS4`^I2R=wr;r0hG)G6e#6c=69sc) zZ&AWrmD6i#^?bDg9!nl38auzCbR@5GW_uz8+4qMMH7+TM6LrB-f6MM=OL{6Uw)tn~zf^Zq;{$re*&7f307;M|#F=URsFunC(x)quJ2b zwET3}knxTk5_t&|$f54%yb<GS*d`gX0YjpysMppB zlb6TBX%e}SQ(ZtwfmwKme_77}yHwBq?_2}0NI=q)!<2t8--qo#eE18Zbna3=rKFY? z3U3(JJwJv69W62Rs1x#tIT~5L>I-Z24>6PSste`Esk)?BJ&T zNu*I-Nc~Kbwj#sSwp>(KrM_oXXSm1#qeHB}^~nJwmgK=5@Zk~4k%BX1{UyiLs|ksHd( zekf?VsO(1Wwygk=oKEhx&GIWXrSg+Yj>%&JA(KXG`Z+ZT2pQYZV4Bc(UaBJO&V?qx ztmz&}e7XTN!Rmt`NGh)~EAN{S-X`OvX90m!FV@K(F+nyd7N`=b=Pu?nlXs;|UgD*Z z3(RYm*u@}2rXKUnyfpcPUDRjD1QL zdRAx07a|wfr~X^wBnwB-6?=6A$DoCtE|pDSG zoiT!spJpD?mzgSnSlZ!k4UIXNG>MFZTR$1@KiJ zz8jF^U;Zx?-f&|&8*2jGlZkBom)wjkTY^rW1u&f*Xna@WnZt`8ohp?NP6CFuz=C4Ou zHWm~cy&ZJ{<7H->T%^f_3)_PSWx~xhCme<-#*^yGSD0|N&AYYG^V!!hcIEPFZ3?p$ zK0S2YuyKusCzjd{9KBwK@&*|@d=E3TlhQ-EugW*?s}Rv35oJ#j)+k?1k?e97ACDx( z8~5JEU4V4S5nt>=nuwg&BO+37-$ftX>|YpKX;#8eF%?GWBWm?x86)F8Vfg#qH%JU_ zuD^UVj5}js-Ft!rt~OYkI5w_ZBqIUqVpoqxPb7L~2P`7S5O?*lgjv7c_L4?fzl|OY z1ZQoo_nWthsp*Dog4`;0Teph))U{W$#0S4Vum-8eKK2)mQ-@i|+^E&6n^{c=Fz|N| zUNQpjWSWCOU*y2%XG!no7;c`tH8qrzR6TZC8@!L|F-|opi^g1GR=}ry>LC;;nEVnW z3K}}n@Ssx5rIbdN_$=slfUu7F31UY*)L8W5GUm5QEe^Gsyk4`8-X%4?k_)%vJ5k7~!Pb#Q?)BDN9| z)OYXyN8Pu_RaK?$p92RWLk}qyDH#?PB^D(X3Y8|}4GmDhMpK)tPAA84^q^Lz)Bysw zG)~#wm@K=Fm6ev7nOD%vOE<^TF4I_T!^*N0)8h9$@7jBxy$|4}`Tp~(&yjQX-fQi5 zy|?wQXT57Jv@{+x$7LRw(vunNdKU~t#}`I zX-m;#a9|_(A6ZZCkI0lG+`RWx%2<^;8K&Y zpcGG4d!E-)g16O<&{9sBV1b281d~D}1#BM!97qeg^m9B&p^=d=%ISPYHY+ zr&R%!x0+#1WUdq2zop0xg1C z!>RVcI(y<`2`0WK5lf%Ub2ZZQA#Zc`2Fur;Mfw z8tdb=Gl&g>@wR*k?ZE7~+3)l|y(F=0Qy_kJo*O@k+$C*;t0RK75oMc7zQ9q#*0EjN zFy9|7pkE3=zn9g{e+1aiC`7&ZIm+%6Ne|Eh&O{`TnuaOYKx7!9FeowQPgw3kOH)K8 z;^06`s6;M|k6f2oKiPvf&exBd(fAM~dzhmAHpC1VB8%efs zU<4D4)z7~bLuo-T5mGAfAutY?n6wkG-^Q8a1J&j0m+`?;bqRYwad3VvFYQwUMI6w^m&WnZ7jj8jlbf&q2GUsFPG0qJXwLV3 zLxQcrIjYOkKjfv6d;=SZ>hkq9yj01teiRCVx&r+rqq^;^t`*0veDA~7gX9OQ%h$_s zi9_xrZ7cRz;8;I}`0^#_NrxBXygQhXao%04>Y*6-%K*7h%!o+*>A%BmMue3=8$S1(P_)kJlUVBt(I!_O1GGG!qvER1$>hC$>8`d7SOs zBzt0$5k(o@Y58gBP6uH1<}I@@BnFQW$kSg}O+yIA(R3|F^u$wVV{+3C7j>xHT6$ak z$V7>#we5z#o87iD27R4+=%=b;RXh~3VN=@B4}5FEUh_CkP>&o>yY!21L=#QK&=e#yfJF^Y!(Cr03({^+Z~H6qCPQzx z*bA5fS8qV$UuJ=Q&s%SRqR+P%fD)7`Y>XtKz)Tj%yOQXq5S5y*-)b+A4#k)Y91Dsu zM-st8pq4)(Prr)AvshfU2s;U;+KZ3K^QG~wz*8*H*0>9htj8_{3HOzPZ5U`_#)AEU zZL_$fNcdkB6wKvA@btTUS&HjWHGd@R{{|bkCmEKZcoCVWKZU!#eXoAen0mYD32&?Kw88?qrQIVv#1Au@)?pzEo5J@R~ z9do-{KHxeZDZ)z8pC98ScO192bSNOh#aN@yWPiDHicdm$tFN3yoWvOMH86O`Ji5GW zKNU+|_ zI&3t8Ti8ycPi(L0@qu=}={oRRDAM3ZDXG{Vn-l`lr-jGPH6Qaw>c!buOpDr1!(jw~ z@v^av(7LfzW3q7!(3o|Mf6u{PJm=-9XdCs6&ddn_Sgrq#GtY40j2t+Y?)a-1X5K`CsXu(Q4s7cf&%nv@)q7D8w&xCBNM z4`d8u7b3Om$AO+%p2**-&aTbLK)8>vk-2MvZvcHm&r$uixE{OSX17Z0bPLX7Vp2G= z8mq4Xk}~BgxoWi6xRY5o-9Vd29-PV7x7n=13GS@VBuX5|XnRF_%bupu5I<;Ap&U`aS?_Puh(v#> zQawmiIZdI;@GQV)fxBYTlJop&dOH@0h83q0xv2s!e0p_%o{0uuQ8hgaH=2UefUyBg z7ovQUz7~s``4D2?xT>tyM6~MDk6UVvSqj!!=ZRq?i3kfnJO~bqSQMveGa8jsVz3zd zI)tFf1=Yji^q1cP$&C3`8p8;_ni8ujO2?LRnV-Y+xRf{n7!TLS+-f?4gv>g6hN0>L z0c0%7u#z3^I}9=($4|k==TxYA0R$!heeO%cEjFRsL6+e%X%7)4b}(QGeCH{OthqXCMVJG% zXlZX$?uE4DBG&=qMXX_f*&F}}%P)dBU}&`idZ}z5^iRh0&Uz%8n$9jk-i3W+OfTIq zr4UmJOdeD~dc$Nnlzlt4LpdR5_sunsYslF>Y?N!_?BMSZ&kt`h{=RG9BJfr)5=ai< zJOx(P51B?thl0#x5vzX5Bu;L5%P=@+i1;pw_-0&%-f^pba3!-jtNzC6IwVPA+nhe| zAd*r9F7?=D8%}D`n3+(yNr~9tEo&6Q$NsQkq^_(-jr>pBUlO&7K}y&_GI|+Dk@cro zzAq2SG0YN~0CKjYV4iP+qUR=|=kO%ZgB%-#mB4qIu6ZA)ktKO2Nk1o#$bp#R`S^-f zq_LD-C_*ZWq6}5AWTl<7Rz-)HOl> z6CYu|&;<1JD7z6PuoG|0Blx=VP4&)6`j`0N6zx7&_y(U(cWb3a?RQv~R0GE2~ z0$vH9VX*cJT$FqogT3aoJYr#QS!v7Ef@s_<0G95wtB9VHYFPCiI zqBpLf*zZF;!2Bq#e>r}jf2w)`$*Idp!3)5M<5IQb??M#{jp5Mn_ywL;1%`vjKaogI z#=UYqf=O@;Xx%!3y<{FEeed0MM8LsjE+W?l|3$I6uVS-8uuV3n@?tbFSK=SKq~xhV zTaR6Wgd}(?4v=ZEg6TL-;&xGOW5^@gZ0>{3gZf58eLH(Dw4Zx;P1EU5>*@;6=DL zUK)fGGK-3lz{n1!$3gK}Q?ZFk^dfJT&wBF;#bX49c1?VYy<$a>az@iV4ffgz6j|dFC{>jjB&BxWBEtpW zB6O+nlIe1>4i|Y+0jh$N)rQ33P+04o8ou6ujbm z?H66+J2$|*2%rvf;HM2)Q%7e0GJ8x`ZB7WyWJb#7Mn7zJx5uOVyN;>=$d1tK4n)nQSnQC%`bBdkeb{@XQftWB?T z>oX`0gCB|DhxhK^*i%hNo(_rK{TllQJ;svTIh}sgFa}HLxZp$ z24Qib=JS-^+1&-~-s3Ij+6X)zr{yPr^}~y>uCAC&X6`|KTii*kk1^omxht6d+Y2`* zd$eBl5lFtj4yTc1ZuVaNF_4jD#6O!SM`#;+6((aVt&%vz_$6_i1qeiSdO!F{WBL0f zZGf$v+T(rnyAP}_fB#Nw>KRiX&1K@)-IFv0?uDEHOOLt^dT8_#Ap_?5@H04{_oIFZ z+KLUzI1?GTEI1t%3{1jH`{1R))p76$1L8RgyG?&MgS&UmXa~)U#{?^DuZqJwF6QWl zF_|w04Q0Nr?S}P2T;$T~SXv$qi^tp@(bh(s{aigWwyITCQHG%B;{Y?MF*)WQ#0f}QPho#o$bVnyJ=DM};ax;!R8#p&OI4t$B>`RW-M26|99 zorUzpP$sNANs1dQOHX3*^aK|r&qPc$|~xCrAjGe9$JPpXvej8 z)&BCYG~)uz{pHj2Aw!|o`(dEiUB0gWQPP4P=F1Pt4)dL~{t4R9c&!k575%X;XlP6U zA{OM!Q1gfW%nUl?jia=$$V#nnUxEJGXdxW1y-Oc*y=@zLi@zHk{LO|axj#87jXv)F zW}4sy2r$!iy2+mNRFlfO3(4Qp|fj+_I!f-7x!ikNz3~ecf(3&#NWr>zxcr(E$m;6 z46>8kzZm@oToX>ja21zyfnXBhLg|q6^05*VW;%xz0&S%4Mj8oJ2{0fhaS}5VfT@;T zR6RVlpjcmexf*1p!5-+)lZLC}Ls1+<2CIV1oh6qeDF{0>qF*dE3LSwBiIT=h(R{2A z#hbBo%u%$uUu<5no-1Vnqu>E~^klMr1Y6?3mnRoj7fSMVH}yboY>CU5PHIH1T!%u` zs;|OUj&^cLrT%=_#bUk*1pMbRwka^qdR5weFfP0*bD}4JJy&9ZjcwK6R8RHRhGQRl z+xxIlLa{z9tm;C(uUFW`V)kQvq07{aL}V6M#TY!dx-R+RZ&V)8r#t*#l594RQ3N>k zu&z^u_QS^@>vMnLT%MPt4P#e|b5tU$bJ&&kk4H}Q7Jb+yqDMoq#UepW?w*q_=P2PI zn#$1tH6MTY2y^pNaWgKz2tCfg0vTy%>+3+QEOXS<#*tX)_UG85iYK8Jy~f0P%O9b7oQ`QgOnD)G#lMJZ7(E4N@y>1W z`WeNXRs!*ktx&6PVgJeVGJ1c2`SUILD!O_BO%jfy>qOH=>d(WOS8*@YR8HoPV8kW+ zTqa<)*JzRX%J5fAz6-iOTB{4c&Tw&IGN@DWV(-nIzt7|RdZK9z8CE}`WwbOU6zeQ z5gfuef`8gCV{>o_Z#41{Fr|o-J#|I?%L_^V)qEqy7C{_9x+%~@w#EocGCK|ECzC)ioL{es2Bc`T zv>;AF_nY;xa`7iPAnHpDbPA;~KbI#{0F(5yv6fAwKS@vK*GO5!70_?K3KVbFlUN+h zn55_QhOWpaO`G-BQt9KYRCp}Sj$>=J20M1&j*6n@Cye;v} z$V!rJNJIbet6|hvi`jK!7RsQeLjAexs3QtJ6sOx&0I#~ zOx9<3$;f5InaVV*`+3R8WyCs3!Y`$`#N@-dD&LN)3Nc6K=Yx_~$P_#r@rrFbcqus^ zro%;Vs4id6wyKLnXNBqt^h=ED=)cg^Y*v@2cjAL9X?7lIPe#5T!%IteiHVD-u0a2V z&61~>poi+P{u7r-ovfGSBqplM*WcxX(u`Ip3+f8=<+udKGnsJ<3^AVF5B|!!WkX{J z;F^Ia;RfU=fI8D~RO$`XEkR>chrh;dZBzuLgNOqHKsw1q zd3skNKCb@!P$vZ(!E{L+nx_`%F4i5u31;i#B^}6IV=KvIMfv&{Fg*f&lKN4_>;x@R2$5NkxXMvE-KKw;1+CJWjdX- z-)5R?3Yf4f%fl@5^@W$LA0}zvB~if3~Y0pP%qKjE@VAi^iudKEy4s`VTP2 z6~F5Q$pv4@F0~BTA!_Au9osaRay2#>OaOi!(xz%70K6S zC&wV!=}cy@VX@?(*v!GPC8uhAvaoF${pyJ3=O-eI#O$W}uzYMva*yxcX7p;tOPqEO zI_e3@svH~_ZSC{1iF%53;)W10PI;|fju$izhf3UQ+ z$Li`S=}2?vmr~U)wW?p5o^vIZ-(mJ~Ol`mMuDX8XK#yyb%=_5lyIT>%LEebiW09sm zS{s%UtW8FafFu+!smz?NHx{65)xC-`WE=@;t%&fKoJ*QN!iskLy1`stT#burpBfRE zFx-|O^^dQ>ae&1qlOHt{I{}?g%0Tue1nHrafeuEwCMg4IeH|0*B1n!*B6I!cPDzRE zQ#~`8T{HCXn2YKT_CWJxQC*yoaTmFP>+#g;Itbdf6tB9Ul_s@Ke|#gzoaL!XyjUwj zI@CC~Hdqd5*4&Z5VM;I^8VRV_$UP$it@vrWEq=oKRxGpa@m(RBk+~<-j2X%4$d^Rk z9+fv9^&sp>u*OEoFrwkI>~#VlT#Vx-DHmUmEQ9zSoyFE}pF=^aM@KehevYAGytiUG z6sg+tIG~6|gEiRn={scqWo|Ll*<38S4w-q#gwS_g3fBBpHp2r3Ze=JLk5vz`a@w}( zi}~m^veRdEc59C|)CC3tf*DPB1y=7^DL_}c7TL` z95p4$SSu34lO<0_m2{>JhW3EvUm#a1TR@D)f?UP^5g-z)oN2XRBi$3|FepxzaiK#Z z$}L&{TJnCvA@B4;$!FWE=YEO9ZSNcpxa}!~UYy&;sZ7|H3=ZAON5glXT#b?igQ!YMRpMf>fJF=9y46PRglZ@BXso{&6@zG@IJ7@7)>?auRr&qvQ6A6K zd0ye*$9%nXqg%B7>^qSbfOHJr!W)xim!e#}3&|{7Xg~(1F<@|2m!xAaVQQvIl7Pt_ zfvZUZCShAz+rswDiPrYa*JB4~z1B2BT&0L&sn3=IfGknOD?qzC|=F}|U9AOXi z!UI#8Glo4Cw(2W-tF4-&nLSrk6xy!&$4sN>akgtt4BxIfa3!<>Ya7wn>N}H70b7Z} zq5VByzDOJZR`@&m65^-el0+#;X^{wJEw~I8r{`A>P1d6?{=E_W1o1;JR~?_IIJm7f zfSI!Jyw2TgCKsO1#5uB9cwS^IJP%_95{k|3tRu|kib5EyY?um6cB}qiFR+3!G%cyB zKimn;JEMH{nA-m1U888^?taS1AyQ@a`?2MfvihvCW{iY*-;s^M^9p0II98-iG97-LTeFD?85&im}nTSil{`x z#N#9yCUQLU(Hb$0#1lv~e1VUmXJ(>dyd)a3gFS-_C*efTK)1uxCFIQlQ1ag05r&4< zk647O=1TJc8Ebp>!cWD>Y#W9t-qeFP3^Cx>nj8P@SH4)r`H$jJ<+0-=dtKXk49)yy zHHf~(6U=&~k=nVn1Tg|upsKa4FdV3-7<*!U4zlF2xVW((qdt=-8J|Gq539=2XP{~f z)fj0)o#AooIe$ z9%D%|AJ_$Qup+}sgW~tiu*nCwxmHB7^4Bl zOuc@1^_X}`b`C|Vq3#7SH2atSZ$n;OD!m-teTIHIUT0s2Z0ue&(&)w+?a1PJxR%Ka z9T+C?#W$Pai(CYrgo%YeUyPB7O!Q(6I1cpO4+kC}U_79&$7YXpt+M_J*lIvxRZgN- z3;!BxODZ-_zJ{DR;e?wwU(Ofv-e4wbo-u%hb6FU>z&LgsXpx>o(DVL9&C!DmnYZfc zLXWDlc}i5s(PI6{sDE;^^(V6a4>7Za9VY{x4Hoq(58gpZ~wre|O9E z?-@e+7yWPbpVM;vWm5mj8fw<8{v|(CViuELvq`S^f!5tn0JxB z7+-_yQ@Jt|`UJ>n4ggfdY8X(Q>5D@ZzDX;Gxb!M{j9}3UjNnw@M*V|-@Z{y|0ht^H zfaEAN!YWkGLP8%_HlHG=CJ;|5)VhzX9^&Fsi{GM(tK`Sz7%YjCZ-R2!KrUkymiCYM zR=FHRbP5?V#P|!i7Bj0z{ccg-j3xL}n`-T%DI!<#~}s^|hCn4;odXy;V|) zwnKY`mC5>**%6hkf@|FX39;z(C#{M%s`K5m-Izwkl|$X$(GGhn?`7Df*1KSp7$5QU znjKSmxNAvNt*d*zuk>(te(PF4#=Gjh0)0iU!QQ~Y1#G((Th2nW6TRM52a5Dx)c82q z(04}rBK;fl*U(u}rR&<%N0zQTpjxQK%eyKQ&!}%@wD||Ow+ef{H;&S<@C;Rsy)F#0 zgG=xPf4%x9@9T3~$6^>ZBdP~?tG|gL9rj4}zP$;1SZ|t{QdFH@AjbwA?DkW2`clu0 zLli%PS7Kiv@I6?IjOiIaj;W3+QA5Ci2cZG&syzkVLA`k_7|u{!lC zR*tVM#s37|!<=6xDjkE5%k6gKBb_|$DOh$F=g8f`Uar8od0+>dl&Aj)6iI6%4a)cB zvO$~VEsjGCqvhKm+`6UxnvF3k5tWGf{|n8oHPo*s&&=u82-h^a$cx-aIGg;N9oMiY0hIKetwhh ztzIrX!r|iT{DNt{y|0&U{}-8Az7c=4X-9+KyQjCuuqOVM0{zJ=g106h3y|u}$}!JF4_>ubJ_shp*?i zn`Yu#-x(cC59iG4fL8MX*y`o8B8f1sb=PlZp@D&<(!;($r_#fJ3!qSb$(fnImvk5_ zuc(c1(X8Y>_#Q%cjrF`T{PN5)^tw(_0(%Qw z0+Ym%MxD>(6bxLjH~V+Wv#~MonKt4#4_?jOkg7P@IS{*e#k+9NTgH8*TeuI#C*{|7 zQ3RzT-Nx5TIUcU<( z&PnDs@nUI%lm0OY&Cs6<`jLlC`dd5bFWG~3al=@ol5W+{F<$=YVZMBZ_3{sTN4R<% z#JqQ}5?7$RhFOKujBX{TgJC%CzCrZd%)I`k9+~^ezn|Z-?s`%3|f$Q zO*U>@lJ<8XQ1f}>b|%gN7Q z(04kX@7&h${I>)=twiYfDCkSEp^y{8g))(%vX@DIUKF zgd$4#F7iN;Ol218YchnH68seEugNb-0lF3`jX>i*s_&S&U)wq*9`u%Go!L5oQwA_+ zG5G-U;n#qwLsODwdpg5F&-AWZo##7x?m$miakc+-NI1%q5SRblnp7QGM8KOt!tcpjTG8ca*%t|MjUur+Zg;$N$yA$qkAir_Ptxww#NpBs_icT)5MoWuzY-mCKYj=%$Mdw0_2ma}0#~FT zCzD?s{GBT(SLLC1HRqdKabxr{29TvQe*YS6NaM+e&9Px=N-5XV$v{f6;OdIh{q247dyRn+%wNN4UAgLNVb zQ@n(3D!%+XtY=4%UP@~!JAiN625=+fkA|bmqxY=LO>V!c4;4<BB=eU*JtR1g&T_ z^k0liSnsM<+OVTgM=YHgwz{A?XFa}b(|Vy7wN`Ej^7s8uy{sLTuUNygU!Z_CAbnI8SxV`s#`61D7CNLTa+c1*_ZiKA;11 zC1I@J)ubiR8}VRpM$LMJOf~CE-UBZasoX`Y%is5we}=IJBA_Jf>gz4L8#Q}h&rUvd ztgQTsad}sruH_unhQX+cR_Emlr&8@rSPnUxO)&j&C_V@_#7}J}ZShsI!J5(v${`T# zTZvw|K1wz9Z*oVPiaTtkd8b(2QI8Gg>vFI|xTiD&t6MNhMChl=<7qC6{|PG_k06&kOnq(*bSTTCE>Qu#eW)} z#6N7hUJ1NkIi|BwPE0M&w-dK@FMg{#QKU*NE#Ehnw|*wj(t&nX;2X#b|HTFM?8ovA zo=V@wZ_n}D27F^0U?qPnvmSkk-!gb@A-^T^+oRUqx%h?*H^}BFh90sga2*s06H(jr z75ox`FR$PWRw*0GXE+RovoXOVS7Q#sTm2zTcHNpUq9WH7R>$_|__P>P%kkKiexk>) zckvH0cLu}ouJW9LXw+MF7fLcyc_98NnZ>ct{S*QIp86gBBAG_N+qm%SKFVe%IV-4I z4}kn|h%ECt9)U|A4L#(~Jfp-$mS7cE85iD=Di&H*><7+{DzvS|`g}aXVJzZ;#;d(^ zhC)Gs0fqKNlDWZH+|z!%Ge;H?yK`50+;dhDAON_dWv}uCx&owlOF#;|bTD3K!4$Cz z!S{30EQ;TPM%jnIPJ9RJ0A0bA0?W8cS{3QDK#k^6kc^yyIK0q%j~5RCMELowY(O}I z{gY1!BG>+$-eNY+W0O{UoE^z z*!vSDmgWs-kMS4OVu5OtDBS*{j`6`P5t9eoGb^T9wA^*H zI(};8`~1J#4$bobp^fTv`O~AZS4QBX9-DfNj`83;2M>KUwg6 z9n0NgTqPeWPq0mK4(psa-{)HmQhn(tr%WUc^8)DkjJtD@IP6-B&pzYtmN&Cq-SM3t zr2k-tS*^Ah>+$m(>t$7b%rDk`gCOFw_Q&SpQ4Erkq-(~878uH9ZUaIBu&-5}>;zM+-!BdDaB*vu6tVUU zJ|4ZDj!W++u+MOMcaq*aFuMe=VA8v7;EB`wUrbDZOU=-mPlqX|No0Nw7z??Rh?}5k z0EBQ9GroWo@xg|O!m2CC8XRp#Eo^A*E&B>zkQ5e|H(W1<*U;MVey=Nmm8EFh20uBF z$bI&sm9Hr%#B^}_Gib&V;axn!2qatbPx3i|Hkp6*%!ObkqLHm*T3V-~xsccWBuxNb!B`Os! z39I8UhLa+18$~XcB9&H=Nm2wmjOq)ZBS_1M1Dm$$No-~ZM>CNrjbio{qgo+(Ax;+HvxiEZ>zBte+;s8OVy6bXTVL!<~n zz!@lV9YT8IXR1FcZ`6JSNY;SO>1-g@F9H|G&W_F+9`IyMDM|Dbq4kY`M2q#OJZ3Z; zl`$YP(8hw&UO;fqeHv>k2ywgg+tKP^j>jFWU>E0RAD837%t9OK;F$5{W9F+lvmiZO zp9{!LB+lXPCs;j+u)&x|anPFyJlaNYe~aE>pm(B4??|EdKx7N_{)!nZX3W%9v=MsW z0sn$IF`##ZMQ;r0-2-PNLRrQXR|mawMFGKE(0gIa^yZ%Gp!Wd*>B-*_pf><|3G4VW z5NQ_c{p|GO08NX(gGn#)glj9>3B4VKUSytDV7qIBzlo%`!K62)3B6w!x`1l*+Yz3& zz~607dcV4YQX#zqK<~|jyaz3m4Af~gRzbUZ}{`NHJZ3U<>F>9=irdFJ}s z|6P0WvNj3_&ey*KK5h@1RmCkZwUj$3ZzJe*qGJ@KQE~L`EY7t{eOg?ti+N6Up ze+OFbOaHM^CR1n?UBz?`8kU6#UaWwNcric{O2#iDStQFpnSA@)pI80 zqe(eSk@D3nE&b9k%9RL=`F5qBpF8P)K+Smo2(revfq0yHq9-?EYQo4G6tAApUNa zUO%kT-x0Bu|i{Ad=?~UNE z^!L++-q)~?j76`#zh40>^yB=I+KO&M?`&8}u%eVsBUtgSNwQoZ)uT5YUF{tD(f@K&KTP_gs2?+g{sY+6!lFOQrXRn;D*Q>LKUL^| z2U;7fC{y%rx9H~u(m&3m|5awRI_RIBr07Rwda|Pbtz*)ErIY@0L7S;BX8a=kYnjmB z!%n}wf9*~ByO93wLVs(apI|%q|Di=cFOdH6CjCDlC)G*+J7+8UQ5p7kwrfqu!#Maq z)k*&b0gFk0HuPsa^oOHO-yETT%C9#5x3cm7c38Fl9MaG84zWKZv>AP&qJO7FKQEAe zpGp6vP3UiJ(2vUWg&0MKw7v!UZ)oq(pD2s|5rNaP0yY|Vz%u-zO!K5M&m1-y<1Od@ z(v=mLg3e&Yet1rVa8bQlv74L@O8w{2q1^L{jn&dkjsPf(pz(xX7ZjTGoAE&m^>eY%e*jq}7X2|c z+5ZaQ-QS(`_Y(Twf!+lxxON!ydo22Sf%MNa>3?-cIQ_FbD*Z%ddUA+vOU*A9=Aar5v^f&kLmg36uVFn$Z7if}$Ul>GLp3J}&)hob>-9P;A)vVl#|n zxNI|5S%W<$T<)4QfThOBXc>s{Uq+WO??W3m#U)Ho)VOPQvne$|3?yW(;LlO?2rNvG za4m~EJi;YLLoUPJ%@{u08sgBOolg3DD*B;6gP=dRKz{^ZSTFqlF93PV9_;wSx3D7r zCFDQ$69E5LK+h3-lIUPXyv2WBApaMd{D1NTTZ_e>Z^sb_L~&4=9`7XEa!U^S|9-kt z{{`?3P#G?EmEb zaQ45dO8U9LFBhYA8~dH(t(zO*-FX%t? zIw)EK{!?pY$RZcWf6*GY_#D#hh(~|zp!iRKv^20$)KtIAYMx3#5OgsXu>yFP#3~ z2K}f^{}7naap}LpNqvlj2OIr%{(lRr@n?{J>@7t7hb9Fp_9*%x z8-spcApNUN`k&k$PXFz&7V1AL)8kKs{)e6Pmk1rMK<+!jv%iuQ_rRHlyr26bHizv-lZsi3%|U*VhK zAX6#q+c4!ElImX7CuGVSL6^Tb6?>4KFfrvWiZJ)8eNqZxtTJW(q$#s3P1(zm4o~_` zJJqD#xO*1{)=iq^u!m2a?fFVjUbe^V&%_=YL>~8lXVWLUJv<7X_h(WbT;T4~{m^p^ z6-aro0%Ltc9=t$#ylcv%U~9NME;NWoW%_!IvhC>tI*3q70>9pWgh^SzhUP*4OglIK zI@;GI!C~)FR{Kmm6M5oppXXWP{jY(!R)68K#ZN0>W&SL-Z=keqHtZl+f!>|%1J-G@ zj~Cd!?PmKXZwYVT;M0_FP?^35qu3_GK_eXWXFKWdFDP+Xf6)o#nf)~b3U^IHNXZyH z_|vFld)~ECBTBXsu?DQyjno>JV&p-HtAanJzm~`YMW1I;hnC%?iZY7PJ2@NTpnso} z{&GQeL4Q*`wh*qsFqOf|RPsWt*vVF0$yRi3(u#wa-e)UT9c3$44K!Q9pEMPgrK#-M z9NvhPs-*u)+%3X@vN>sl$)hz6GPd;}O9j^rlZOVUV6R z#U7s8YqJM?{Q3f{$lsUtFqG}nZ-<@-D`H4Arj#su;04;l9+J%#|M?wTizR;QZP1O% z^bav=w$t6LJqMih_f+(o+8;|2YDOx)1(FwV{tY{Zq4IAw*@Q35e!GoQn=u}DjhUH} z$%MM;asXUpY&+`ervsEFPwUhPU*k%^XG)z+EuY=z_fZV1p<$?}}`U}T= zSPyhqmjAKGtG!|Mq4_Yk-WoO#%sJM4Si{C}PH&G@8p8Q7KX9cGrycaZ=A`!{L0L(! zitjqB@mZYcM-b;RDS83oMP%3!yGqzOrwnQy zIZY_;Y*379^ksyI3|>3v%}sRhx2vMJIsfttOx4sAPWZTM78!ctnD1FtXXBhG%7dpG ziZaq&6PoW4|7cG5RI!l5KVGj2$%M}l47Wq;nKsJFPIt}X5anc` zn(y&6p?r61gYwbt8uDG{FGdUH!gnxsTWvVy&#FQ);nUYixl(h-e9v7@`kxkjI9AQ> zL>zN=XDNba^x*G9%45ga4agzikDc}RSM@vR!#cqUn3ClLkGp1Nh(FonkIe7v*$^(- zm8Tf|@wsb4^E<*H7Ng&InS~sZy+;+237#$(xZ5Oa@W(#Cv-m8BewGV<8?q>svr?D?IB^|rQ(=h_~l?4R>He&A9evK{=^o%DVrKrHEP2ConP z*G8}1`e(xmLwLPg{}VJbSW(ID`Ivb9)lI1GXi!bOehEhDA*w?fuf?5*L0+nQsA2B$lDr1uoA%WCj*8uLyPyW4cFo| zs-z&WqcHpi0vlI=gCIi)>;n**fxyP)$#X#nV3Z*N1;Gx_*K1&rcJ74nr)!c!9_0f3 zhWWQqsKT^g0+jBW*igJgFw)hEmeLIHTG0E0x-f=YGrM?mE9(rFI+!Vr0h zOyb5$J_6QN7Qr(R7Ot!z#;l(YQ-D(fIqn*l*)INMr)dGqr?FioOT^6gf(aau6JQQv zSdZgX&mzLC4t0_iIPCpxC;49qzANN6#nbNp+(x=RK6w;Y7Q)lqx*v*qB6wQC>TvQe zG|0aMnCPVra!qe8jZKFoaYks7mUmuDb zpr%T{_*3-D1k|cn)X_^^uZjwwb_By=TSFZDAL*q3M!}^Bs3+FMa-L)z#s$HUr5>nBJ5u%&cJU0x)SSl95WG83sZpnC}~3zRO$In+jq}=6{vomOYst zx%|I_iOA(&{QdEB`PaQ^<v2CwP^0z1WPq^?Xv$!|U zo$ao~R?us(;K7Y#r62d!LV96o{!Nw<48*IM+izs>UmNzkk*aSl3n3Dvl<9TDbhA=F0Qyz8(31`txxCUfw zx92*Y;rd|W)&_gr%`RP-CrdA&YaIFqzjYT3=aQ^f@m9+$6VQF@v%xQ9ZabDPaODW- zmbDL~=N>hv5~8qgwJcqbKVeH3;$y(R0=0CZhg93*(uH`r?J<`w^!LCAhn6lB{wish z#$B!PjeXg!^S;Y=4Zvp_K9AIAyW(*z8y^}WQYLU-#MQDbOAO?87ts$_QDC~ZME3hA zKZu2zNVv${fnze#WlNA?ZDa8FR@1I(OkV2yA=@>kE;~5}Ww35$jkG>~E)IM1?ER8> zu5rmTm&+`)IqCt=KV;Fx-${8c7^xOrJa$+p=gfDEYi>K#d=Wlb#$WR{uUXCmU(|XA zI1ue)Z}mXY^w*>ba3J`ll^vicU?648){;}#a2Q9-bz>L!^7gD!_=!iBBeT(U=x}w`TTftVdsPSC(&iZjUcliNLHgJw zs!8ZUxg_f3YFH!z;^eRz?D~`?iiE}ZIB((i#zriI@p{XO8^QH|_qy5>;K4J&tZlC9 z_-!RW?7fQDJ=;JC$R{nnugU&^#s0(wVLu*FoH71<3w|HL=L&FS7Cz>0ey1G9FQDkL z>(m#H{c>><5b{{_jIj7gXWn|Xz{QL!3y_yG*@mr;0fMh4ZQqsVU-S`ti6lAh1~Ok+ zfmNU`Y*rF&ZB~Na63xv@8n9wI3b9^Ens5H;*!w>cz0S-x)N+D@OYzsXLCD32*jTO& z7`^>cRS5S!+oJa>(CDMtL^5QWY!LqXw*mHwWy;HV+uz-%F1{?7eyIwE}3wOa;-qN6lGtC@_L&n@5khgJzw>P z4-8Ry%NK$SjA$z>;y@7AIJ2p-pk-Ezq9s4_i+vtME;#0at0aiuL*NB|oKvqyL(IXP zc*t&?CA)Y=x%(+QM!CPd78d1hH8g<5eSp1+rJ{+4RB(lk7n}@b7S&>=M)AWDZ=K^@ zFR)bbU@{{-pRNMsRdVTe(d(l3ZF(J9S#cW3Zn5zpy_S>z_@%{`l2!y?*7Os)pr<0P`xAn(_}iB2UE+%lW} z&1ox6AqFYqv5`kYJ^_k@W72&4*FbTiMREQG6u%r>5$%8y`lHdncfd>cm?U@21XfNg zI*F=t)Kr}nuY{@2{l6&guyA*b%!{R(9>3VEKDsW-hjBKdQ>+?pz>S>;*F~3ju`kA{ zYmP)#oyD8=#ad7P^*w;6A`gni;!lI}2T73!_0pfjBgAu8K5WsOhW%*M(V%!Vx(~|0 zGkCC}g?UA+xf(_25d@jB%sInSW?(eG!eo`~_^$&mJ3SVjBedS*D*=CFXSc$9{ApP? z+l>2ln!Q?2ax12LLe)9(>^f(C4;b||_4_xWK4l-fMdX)lbK1ul5X}kL$3pbF{!<~A z3d#(Be~0t4+sEZUn)cy?ip!&$q5Z*}G}y-syhQo^G}=cj2bP4ImeYeeaFu@?P}T5N z-2g-tOHG#?z;hML5N;rKb~SuHZ;ysY$Mw*}t+v|u<*BSlI0=5mg36-BieFn_a`G#Bzsau*D7~MLJ_gnXbJD@D zQj1^d(|=;YVGF?v+~HwK>A z&qr?sYlAr%;8&T&uMF}l-sIP{sKm*yOAIw-`OR;WU;Osoe)4N0`GuV*!7pAs`ZM{p zqvr|ntJuk}sA!JQ$*=Ivdj~94<$v!Nem%3<#;>T#ijF72uePA_Ao+y96Bjx8^(;n} zieEdSB7Q!a3DyR4vcRuOi(gsfSAxl}3s8xZUv5K9S^hB$_KKyZ1wW8q+sQAF@Qb(K zg^}jz&!o4=FZ=qsFP!}PNMPbvY`_s*{bsP?;%OIPPr?yLWlzF^_+xm)<%k4jBG~x- z2>VxS#oZk+YV3QIi04!Bxf~y38#lF?TSSE0{9^tMzi;{u{tb`M208a}J4cZW5f6t+ zOtG270T_#l&(!*yb(;(kd&`NKOMG?~ByckEnH=VB4rC{rOqnu1D|`WBvCpkvWLOf5Zv?VbEER42j;u67>(lhBer#-fN=F<_#~L29 zwL=5L<{$2LGABy#<>um$9k2|w*t0?D|3;hsM^{#KJ~925aY#F~;2@iazZ0Ji)BkTR z{r>^_&qp(%-NBq(@akcUSGm;x6ife6Ntpf{X2kN30X!;}nilM9CSG&&H_M#-_(iZ* z@}nP=l&W#u(PP4E@d7C&mwnU)zJougM4e9rK)%9}n#{`LPl5 z_w&(i{~|x~z>oPBKk~?rRFfZPq7o-Reyms3u)GH3saR_IM}0H=Xd!-0R`WW2a2D(l znc4Z$$*Ok*ktM4JfmOHISoIhzPT5tgu=wpNjes*GLIn6>tpPw#;r7-f+_N3 z+-#optG05`d%?poPE~tB=-6mVf)jrujuT3jWqO^>*G)HE-KDF39u6fOda8*q22K;qQ`XD5=n{1>Z@zc#NPsL-|6_#~RO< z$@8Jr_;1Pc9C3e-H84_jK9pcNxZ!dS8{xk934D|2dj#hy(0X;-h}X}9pTH0s-XRqccHoMxjg2l>9*#d8Vh)Uxlr^^66lhZVN;T+oDfp+ z^Qjm?*n5jiOqbcxh#d8Aan|48sy`1(ILTK3>7n{>Mg6u8!_xPWj`3Qu_=PNEy!MiF z9qp&TOFPONYb(y9yucj+{O~tc245{9GT442Ca+kX|JYHwh3;_W9DRL;YOqKH10+V= zTs<}r68Cpxygg{4&7NfvsEaQ49L$*jH?RyOs4#s3HHGD6w9s9Z?9$^TB| z|E4Fy`M=<6ga4Dj|CJX1Cz1awNB-Z>QV#y#s!I7g;cgUAh+_G6Dp+lG;hppuG+aCX zcUt_PXYzmge-;0EIsts4jsNRySA_r7c(khL(f^VEF6TPoPmc)yn+c*`f(0tPGESWR z%+-do_m*?WDwt&ozMOOrg+qS8wMO_iO6zrKn?Dg3Iz!2WIRQvvwIziB1F1Ypfq_)) z0{CfrAobNAk)0Hu1-PhKzLoE>Ng+``NTaYzfjLvk3MQCR_~}1N3iE9|S5~mlc15HR z{UxRFb4yYP1;Z2JS!~V;UmgB#ty2!h+=j&8D}xOeO}hy3_s;14MC{+iAH$=bg3#0M zQJ0&)L+?EZi_#kBqs$_FR^sD~v73b85n=Z&qEE=4A91c5t`^vs!9%#;9s{~m@DMNh zbkQnHpE5+B5I|h~NA&4j(WjT;1*uQ}raqkuZP^NK30BO-PpH&xQ>EkrwQ7Q?Rj=2C zY1QAqR9eMKE&w7>EY)57rA@2O)t~qZuUkFi>|n#JSslkd^#$}n0oKWmj?{OzrEDV& zWvh$g!?Qq_e#hrZ?dI5&OsU;G+Z9o}xp=f$w;K}tZ!l#`cKl+=&xv0;`@?#t{I&>o z+?@Ps=qc*lwH0aL<%u9xJVw@!gU9s`$zlA>eVlPtC~hkMOflN6zy4o*tI%yOdlFqX z4!zr|pN>*i2rOOZ_g_dkjJT9=@l*Aha)FMUrTNBB=2K|Ku>cZcy{gIzUAY*J7t6N- ztiZ4wcd{O&2ifmSeuD>kJa~bzkLpu%5O0-?R=ZFY=-a*`6&@d^aSV5os3aV(HRuaI z70Jeoh8zKHCS!B26u5WJ1{mGzcqL)EA`*THMVghcB~weDE=PQmC-IHXh;KSO*LnXY zfG*`Z6misFY;n|9Sn6@-H9#ngGb_~4)jk}&VIX+PLdwATVxZzo3a7)Oqn1kF~R2X_zL)WkCIP3BsX4f zhaw@AyB;VvUsj)|_2ggw%n-!AN4+H*5clJ|f3y?c9&LxWJ2f~g+|q{xhd!i;KJ+p4VY5>oz7u$t`Vfx0u7c&Oad4ve z=X(K_$T-+rPWc7vFcwb7my_x56FAgL5nb@YlTsJfqvie-2=XG>X0U?uW$@1cxeOEL z1!_a7sST$;5~dA5z?lK^M!nzwfqbLyGRAMei>^Sk*IQ$q?79d>?1bl_I1W zj#xkXv2wo?D4;-csu6!>fC307poGJSEJF;m%_n#~iq)Yi#=vQg7&zUM6wimB1PtCX zT;q!apSU0%^n~Uk3I#@{T*Bwq&Lf&HcsLzuv3?K{lgOn6^Tv?LWuWE+<`2XhUkH}v zke~Rw>LI5$KD1M@)vc$%-28l0dz2ztgw{et&^<#$yg-zqk|Lsuo`R|@7cFjf$SzeG zYxxRe;bN(;{u2jE5svQ-ce3PaL5j(eT)3_YHrLgjfW54rOcquB?@~)u5mZ1`G3|Ic z$UPZV6@0IosOort{J{4n_`8And%&(>#bU*SqZSW%foeL(RMWpc7^bEJKT#}TC0_zL zD3$s6_A{y!`8|9QJ4B_!#;eWdzXH9+gAk}dP=;%vAx9mEAhvO z_n&{u8Sh`a%J>}$`&!|pTH_p)nUBvRe4O#TfwbGg{^sw8;mL7f>)!>2ZO%Vcz)byK zE-p!B#v zmx}5XtU!XU;h%Vc{^>c>KYegtxPSWB4pkXz>Hjn}iroZb$L3Z#sC^M}zAjvX zXsP8-j)j*!<81Vc0zXp^!tuvwZ?sC z^miS_Cl+O!^&hsmy_W7f;-BaQhd(To*%9a!jG=3j*z_EFpE@@;a*xJJ5J5o9M0I9< zxoenSZJ@2&A$flmbmJUYgD@#4{6Z@k~EX8_0U(Tydf8U$jg|#WR3L2K^D! zxk5~59$bXPGgpB0H((A3=GgpTMYd%&yg;-0&@`KWR)?9*^!Jp@WF_sMpxN+S!h1He zxk9gk6+N}Tg?MH(e1~0u9sT3SPGnpdiil2NO}dveDsK6Q*)rd%s{YvJef7JW^TXWkXxYa08Ph>-FML)@vo%fOf(q zIk2Q&?+Q1D>$gHpB~^7R6xclmdp?ZD8)Wv)new`7w#_-npyk1>ila=KO#|wrQeH3H zYU606els|lhm_ZU-XgG2=DOxGUK8{uHjC?z%~g(`$$YsmF}VH_#+CXW%y^BJj8{o` zt-sij-kPSTmf_8qzyo-Yt5RE2SdH`-rKlhMMYb~^C_~NOW@xp z2-j@N%u}dJ`6snM>y+m#F+PnpA)lgF@?G60GvKl%ydHo%fvi=+>*`VxlRLkq!M25d{;T?@Z^b)VE4ipM}KsalNlQX1g2hxkH;TGaeKb&P0t$4V7wby zEBUVO6A5_FL1f1))TL|={&uf)s`O2plsdZghoG49=&#V(V<)`o_k?Tp>dmSezUogH z(5r;kahsd=V3z$m@nUDb>vv8*J^mk4X~Ow55uTw*zH6^%EY0BnJ&1hQnm?ZJ`X<~S zW5OL!LP=Ep1gtz(zUw;`VVd*QJBm5XcfA55eUK-7?phxd2abaI4PKYebBstEDNR9pP94wkP}dZhGs z_XC78`n%;~-%xAjOP!Q`+Y+YQ!|J{^SC_(65DaQmMYGx=ws2;-L^Eb%zp^2{f@;noSw%~b5>PdqV z94|pA5!E=yAU_)_!UUmvfdHrkp?Mo@h7hkuZ92gOq1ag{cZ>v~#B~bsYAHd;5x@6J zbU2%G0f3u}-;3ymjPn|n8}YjF`&9F{@@ZCo6oyY2`D?}m#|6%fJYv<0%Nu24tFq=i z=p3S^SoksijYIS_tEG4oIX$t?oStg|Sh9z~f?^C8nbXrGrDtlX%>reRIcz<(F3vq> zg1crJdpRz=a3u6x%`%SBWk*#;(s-5tu2Km-E08c{%}aLFyTOPZsSHgLdXn_>*QkzW zkqR@3UuLlFjb=iRT#*X*}uwApe=#(|fIr|DE)I(a`Lv zBux@}lJsZaR{UStg#YVpSA_p7@u-#1a}xZQxYf*OyTi%;HUgEi9}7>4{tSj;&*yn* zzTup`WhgmC$n$z*vgvbts$U;S7b6A3LEZ^G^6ndqPkA8j+k7e+dI) zmC&0EslOveVG{;>p^Kdn?^oMRK3a%N2uWd4drj{~6Y zhHcmdXvxnx-f`x~+~kzsivk`~e&P8|Gf}(3I|yqqNv5T4CIo9(DKf8+$6)6Lx8tuZ zMdr`w#n6=u*XONvqXS}wjNt%72{OOj2F9CfxTFKx@|JRdHS@qMcMVcrqz`J69`hzk zI^5v>s-z^vbjLtkrN{KZER@v^CF|n>yIJWm(^@s39kQMj2IEa|ynj?EI+8k2wMtN0aP|8YHEqBh=vd`7xg9VFvlB(h{j+8Xy9d zA9LrMHmTY3WA?1Vjh6FczFMYwu-z2SiRH)qgd!)MA9JUA&xz*8+>6Jd0LRLYIRfLf z8MtNN3CGBfi8|ZipSNtM=};fS^J8jI`Eb8S!b$*|DoN%REO2GCgH1}#7Jcwk)})`D zKGH%3&9|$r_QcG(XDE49$D`tueBS}e_AvA1d$oyOqrVm>%vM@7bZpLt1Wyt&m z(Y0m8Df(wCX~kBC%+RJ8GD-R;uPaqBGGxN0$c+q{&=h$+9 z9s{FqF`;A^uyLDxIPlM?B!?Yr*dlh|T@@W%{c^A&S>_M*beTWgjX%b0++j#S=Bxto6G6BR8G%jO#$hSjw@a@vHAVrkk`qw>?R{v($R5!^15P9 zD((g_wpN?LjWRa)(i&4ia~3|i_;7yGmJVSqMYR6PeS3d$EdMdl$+v2OqN!xp0A%~C z4P+Yw&tk(vlVzu>3;tng8V9O^hyL+=n|}fRr2p6erIi$!cc4SZ&$n6fw=hksUaFYM zESvLzfv9|&?n`Z&X6D;GybKq^5YZO$ZK_{Y&Lqp|SB{f!Q-jBk<3>(}ld$Qt;Bh-hIbZ=2;*j`=*%{(YLd|KIUa@h znywQHWftVZ$JoTzWWDd(PElPd^C1*f`22Y!DzeX?e^70SO8IYKkAwb@sMG}daClqs z-<9{DR_l_{=DCuFnM@t zW&Zr+`%^W6z79S~#-H$H|)h+E>h`5lYWxdqyTf)gZfu4+ghTX}^xd3VGIcRM#ndRmZZUPfgT+cKvm`ip4uAX++z`DjMB>s1 zzzq0X--;I+IWtD^Fn@`uekypF02gHsCMF=Xk>4SgaVC7g+(CH7E%@AqPZd6o;N$ZA zpZ@2L@OUDRQKQ^<*q;Xovn`*yT<~1lU-*6A+w{j#-y&yyJym_?{tTB+ z8wQpqT`4S&#UG=_Yf+rFc!ZKv(_3{UeVw6ElL`2f|p?%zazy!s7kgoQuv2Wr{@QtGya*xKOQsQ|)^<)V@;yGTG@r1<+s^{Rd%b zSpSAHi||>APbeR)`KZr!zh!!tIoBsYE%1h-cS*1zby_myG2<$c$0YnQY( zfUSn{^BGt=^8Y~NQG8-imb5g_NfkoNebDHj?|SDtvm4jYjam7Lm#X|{Mc>L0eb*w* z$4=iZoW^9@U5JydguXc_GasKt_}F=+C~{KU%zfdggWeCE^ezSdW~29_X;(ttbNUKD zXW);)&nnDG+vy#IOajMmvppgDb70w8V;1Vj#b-1=6Yz0GMn<~vQU67lU#!1j_nXrH znseRHFM`=x`g(!TpL?~?pM^gL{m*Z9(t8_5u6Fu+Aps(c{}r%Yt??*mjzv9*_@v@P z`lJO-NtZjJ`-U=y>r1LLU%scJ-;&E0Mg7OKvve@C44eYGki&$ogNmx%ri z?5FsFKL$Vcn$?=W-)q`_Sen)ti!zD$q~g;=zntn9w%(S;q=z;~U^d}j} zkG&dW%Rk%3mJzge#fbBfpJtcX&2ufrIO_kKGhg^40e;zEh3D}+LrYb4Yadv3kzz-E z^PKsc<*GjEufX4Pg}={b3xDV1k5S{M51rKR{mA$ovXArdeywo=%FMuL4nE*-7)Ok*2%{&A35{7HVC9_`R9~r zz2NVr=O`B8k10R1iN^1}KC8c*xT{I)N5P1(KU6BpXW=sdpJIGWU)F-Fh_vo2GqL`4 z=-(`7k_y+gLcY-Fk%5_6(*w8H-qV>w1fGKtI0aiNwgJV~UW$N015r3T!`xrB9adO$ z{xhOy{C#j7{@SKwwk=@IOy+Psi(w8Qz2OGv2)}%bA$*a1b1g*c4Q)}zGt=Zp^Yq6% z=W+Y5F!ZxkaJAKc>jQ-UyYa{1_s5@^DyLpD=!+&y{~DI4H7-J#mH51i5B<}z3`p*S zN(X;GaMJg*K+H-%-Uv3FC-z-AQ0SY1KL&kONY}A@qfK8np)W`1%SD;d_)Nfu?>`oW z#(if#SAXZcPLxSsbZ|A+KPdci;~=4LCH|QB<$q23l*umt%J^-rF1VCRQ?oxb?>3!d zGdT(T&M^q+9Pnk~lcE~#8ceNowhm6m35U z{CntQ=%8pG7`_`wgrQ?|_knLm@rgy-{*ZhpJHhe|g2d8(!oijYX<16!GWC|nFFz+a z;?WYTzUKO`t3!2OzR#41ddH#p#_uqFe4&e@{tl{sXMdA0MC2WdKL*8*eCMov`S-@} zP=E6}EKh6PJs9I2e2(G+e*Qn+-UdFZ;_4sY&E6ynEbIacEV|;Vi$)VQB~cSM)&NNe z0&$a&4N6E*DP7k*intrFhBdkbb2BVOt9`V!ebj1yw)#}tTE%KHA&`I|C~AcQ^}W4u z)q*b}2(th0nYs7wOA>9L_Vb6&&E7kA=FFKh=bSm`%**{IaiQ^Cj5o>W>wT7bE^LU$ zr-`2FV|N8fx@hYYM@FXSpHk23o36vV3bw$lNw&ZMael8cG{wIswa8~Ys>}DQjY~AQ zPh_X#_77^|AXP)9$p86i{*M5L_M``YTJ-uaPc5=iFLGsY0z%_SNX$wgaTfw$Tw|p5 z_XDZGrfa~U&Rs+1>OR|~)AW+hlHIQTcrm>G{h!qHShhU_2z>lVp9lQ0fDQWoHnqq- zq6nF&Nlp8H0+kb*b3Pn>&rS6=$^|ga&$@n976|>1AC+Tn#R{5a{VJoi{5jFVe}iN| z|D(){xOU-E^(WV|!~Id;r|SPF?J4s17>_v%{g3k^XK;Vw!77g5di<#PO}#S}zhd~q z$@q@?VhFw$bA0CmMgy*9T&=i-zo7aQ+=EE97KVABivRVg_VkB57)$b)&cDx+WC?k^ zLBmdTSc*I>O|_rz6Yx^~lN%DC+EPJrfGO}MrLLbW9}&OF0x0phYd z(WW_?(V8Y-OVjlKZ#Di;pU3)f0@e%1M%GvFrRjeiUOK%iQsJqxPXtP#Ph)EQak>sK z9lrsR9IpRXq!#&%$9t*E7efC8lZAAPC__pxJEn4ETK#frJnk_aSo-yQRWGDTl|zS7$=gr1?)c+s0YG)%-vpB(?CfCqlN zE49cYdXagc=MBm9T$#Y3UK?>i&t!k>{#1XwP5|Tahr$isn3IVq&`2cDX@e>B~jn_ zvzl_lpK!f`>kzI_aD9zyEKofSmm&M#{b$U`HYH$4;x;ooOG_K+J!hSv{4+gOUw!z$ zT)wq<@_F39TeOgqyAnSt2VJiWoiu|ugjW0|W_=8{5?b8903@-n7rWX0^N#5jPpEE-Jrc`A=T?aNq{z;OA{QngCc_e*$I2GQT zPiVv$BL4y&}tKyK-pH->jO`Q%beSA1O0c+kjj5ohd9d9xP zJk1|CpZljd^_;(*_)#ge|A(5m3yKwM6iYDmFMmV!)5kve0=O(FE9@iHavH`nNPVAR z>6G@bOZ8vsey!0zouAJ}{eqwGPc3q$UStSAeMZtDTGXdmglYQs)YQT8&0q2Qh5qI9 zdFvN(Vy(tc;6j?u^T3@oDywRsd-1HCgg=_9d-DPsF@^3e8BBeCQG1^t?pz?caVn}P z#x)n$Rk*Il^&g9e8F|EvCac81^jWpb2U4A>#~#=ED_ve%NHV$pc_OvQO1;QT zjF;CWkC(GV8E$_h^;fb#IVW}Soi2cJ{@xxLEaLXJ^J?B@7W}Ba|NMVxT_CvO*wNJI z9Z#swi7t5-lEdP=uEN|Ou8(n@z?HDClcpu0yNA)}iD?UZpCD(dKEEy1d8$J!P54{s z>;29qN#^v7rWQF}Tff!j zOIJ5=e4Fv3#=M8Fn3y0=>fN#Up((1gQ&r1()wfvB1gndnB zd>9htD7IB$rt=o55XH3uR3;^^HA|GC^#zBP;H$dog1n8pK$nBKK2D*}u;fXiPYQWb z`Dsh)c$WECqCa){C|SbklZPL*|89l-BFsa^T#MwE33Ac=R_&I@ZGg#*?^S#I*}olD<;0#IT*zgyG){KGOcC$j_;%{NDaQ ziT3P{49?{1m0rD;^V5s?QSslQaj5o;+1BLtT)#Z^`FYKLNwhDEx33v6TXC(&^&qY% zaeadg$yYC>Enm_sMEX_VYb_l{e*QaE9`E}(Z!Z=@&IlG^FOeH(?YaWf$ZkH5RHSk_ z7@MAzUIZ^x?WIc2Gqf^}7PY9)l17x&>QmzJ)mOcM2T`~CV=*CTe)u#6MC3_k%g z;bG@^JO`GiXXU%VBh`Ml+?|TYi%qG|&cExz{vD0)68#W{24V62*OeQN;TnZ%r{Z$s zD#T^T{5Ss@Gcq$xfFX?lM}MCnS_*&udQ?jM`ojkk{E7L&V(VR3fjl7F*5#aR&G=Dy z^05Yu3_=F~pjnja`|q7heLrb`>T^hwNj3lUv>C2RL{F-kWUm8q({)ralR`UmF z%|z;Qt$HX1#E5L)D>t}s<>M;F<;ArW*9u&>;bORcit7nnFW}mV>j178uH(4Ipnp!q zm5a-RYaXt}xD3Wg873(+D|^x;^Qh5dEMv!6ZIi}Nm^jHkiT@k<{jObg?Bi-*eV|NU za6UBn*}J}ooVZ^M@e#dmyPzk^cEnERLTUgdp*SFSAm1)Z*_?B-e==S>9jxqZgG zrCymIyr>x0qCmNY!wj0)*g@o%%>`XejqJlE_-1WnjTzs>IR_>Y3!R8!?=NoZ%x#w< z5nmfcQ8Qa$W}8=J@^pC}-B>qgM7my&3@(s4IO|aT|xBt3fKs|a0 zFRmB{)V#mq#dn4QwekhLa0~DnE8!I)r%;pO`%z z!eg&tI};iM29bIHTif4*`b}rBhd6Ialr3mMeQiYsYx{$wr!fO*FsN*nj)-FwMkDk! z|ArgB2QK;@Cs_Z27*zSyPZ6Ja|AumBi97`M3Hyo_d@66OU<`o zr{}VV(OiRfnLM3-Nur(Xn3Ay^@^={GhyBJ7JI`Tk*|i64bfo06cI;}&YW~$+1M9_> z6-!g%W5Kqb#Bj1}MEEYif8=|^!Jka>U2C1boq+dbjLze^aYQtdHn7YuNfY{T{uO=yx!^z7bmW zPttGiwZpZK)31=%_i>`W5o#K-Jw(5i!@}qEd*cpj&xr*5f0uqFpBcl}$J?`v*Jt_l zza^iKTr(oQBo5#Ct?+&I?1*yLpRjMPN@CR#8)OwuZ;ekOdc!wlyG?^i&hvPU*azvQ z5$Q|qoiH*!!8W3A-nZg2B7EY<-z^=ky__HI9DYdx{=X~Fq`zkkTOZfokKRu0nNRhN zz=?wAzp*{2TlELSC+V>H3`3aNTkU^n&lLtJ zqbaMvFc|9CLbnZX9CC%LFRK->WuH^7f<9{8Vpo?$jYuEDcT3}N^x^orIlcr_9pC<4 zd8PiY8MZ#&-_NWe`mCq={_p+$*^=Sf!})h1hyP%Dd%m$Q;;<3v$H%{s>-(UU+VkXp zu0HCo3B%UM`zy%ndojJfZ{;tppZ-qAaA0)yIY~dcy{tm2W|dM+wNF_Oy5ZnGuBY0b zN$4pdecwW#Ya2%FkFB>6eRiee`>p-K@x6rO>tsHzPhDO%ORDzzly^V_grYgFZ~T5J zuHV|9zgs*azIKl9!G9Uw5&4JfzhUbW`tJuspO2}&Z=}hH@QFX)yL!a-lyUec{j^+e?MKzWIszM&P;;`HlK#<*@KY|6|DN%WC-6{z)D0cHz4& z81K$m0b#~ihXE7-Fv!seXW=8V<7y=5F90{6}Sn{Yf)%l#?m4LN|YI#{`tH4_h@X&f8B&;m${{87``|ggB;Zye1=MW!ke5p z{weE_4FkDLzQ_VN30F0zr`8uJQ%<3F;G-qKptr0S4sXoj&`Ab5nh%cVV`&mQI(9il*Fdt9Dr7G>mF z7Lmv%QOo3Nrv}ueWx%|$s3u2ExjIjPTa>T9xvEfmQ>4Br5pNp%W|m@V!LYa|ao*l0 zqA$;;I{A^0U5L3Yj;waYgH=AZLJBMu#9gWp*LI^IZY#(M!n%mSAZZ?j2=FtWcmu( zIa=VjhNJizcsw4wuAZ%y{5y2m2H2sXcA@wVv2vHFA&1;MbO3#Uf@-S75peU7jZV0S zW}r@yFyLq@ytegPZB2cpd6b7&Ew9L@PO8*UApAydqT>Rb8SE5XnlX;zI&jZKLkG3vzrc1AZ(VFyPCRG>Sw^DCEtb1nxQb0Hsr4?`$CKTir$Aj1u7L1oq%4!hV^+o~LjT zI~PTo8kYd&A|2zh9?$OD@FqXsp$|HVGH&?T$ zxdb(rf_thgX0@Fiu>+N+qxI*W&u@s zlWLU0>y7wq*AL;HBjnP59~E5aUW${UZPfD()d53|()0VTQ8b5&_IAG`v9_gI^9<32 zZZ|xN+*doz9Tv>X7@<|Zh@2b~ycl*$116GADK0mJCe;JVDSn%~(twXd`gtued%YK> zr}^8^lQqiKJe8dFMFAr!c6h6m?q^WrLie&7GsfZpGFAM`YfK%`(*!M+^~C&2QOuPQ2T;DY4+3$T6yzu z)8s~r+~|-SopPglx!jl|SJ>nVI|4JHY%{*q(+FFK{^|5v#K#MIr7H8O7nMVcBPCSozKP4?PHKvu_>jitP>+Bubz2)x6(b{z=(F!3qG zcal7o?$W^3)*;HUkKJHy|HQiXB*@8bHn$I0*ZzZUZZREs=i0qNd*@7g zm}3l$i*)0AUm0unhTbXI5z9PvM`VAzeTTK3PjzmKKFayM)7JU&rIS%|2TFR4c<@ol zu8c@;29(P?1zjlF71@Vv!PfR|R3UE)n~7=bmpY(Jf*FX>5I&*I&GhX5wN7G(AhA<9 zdMzih?I4jDAHl^yLC1X3(QYMzJ3bI3<|&*zr0e(~K?7Sdf3$xRnj5**YzWO}H%n}` zwDDiT|K6^(XoQELeic7Hn1GSiY{?M1k`-qApO7@Q_^9YBhcfRP-d7fK zy;Uiu1CmuKUWiom98cl>)PU?9G7k8P^jSQ-vXu`uH4-(4cr&|pRoB)Pd{TTqq2#NF zxnr}gGlIJ8G{O%4APeS7d`vELJITKKSNga8XT+a{xvUr3Q{!*apThQry2U^jU2W9u zaW+5KoZA=aHv}(=^c#a`<4>r;v!!)W?iLfW*7&@N1^z1rX=uXl2^?b{WVnPN#ongB z{{n)+Gf}`s9JI~i$s`hBe%NNc(+oAutyec`y&7r~y-EQOwf|IqYgtkX@6k?VCF3mF+40r$&sLzMy}C}> zWIRcRf+KKVjgm(p^o4F0ICcx-vdPrV?L&s>>bSD+CeE{-!`Ai+v<=-mjSi)}l={8Q zZOJ_xngF6~hTh<3T*oFA48+EJj#}GE!ExE^m5K}x6Tv*0Z{Y9BsR4_hZv4bGN(a`P z@V7L9HHkBlr8Jt?3825=R1TS`9?%NoZGs>0+N<0E(?!M-7HA_1N~HT?=%1Hb-kSq~ zKqi;O$y=8aYYr2ZHnK zNSUpE4NiEufWwuZZT6T2&T*H(<$;=20D_jK*RQK^hPA?jt3X8 z7AbJMFiShM=*Z5+ybq-ZQ==nZVwU)%M-$NzFYm*H$Sy$B$&d|nK>C^Nb)_7u#?gQ& z-N#`Ox)+m~Ri^i`w+9vb$%_?rKPc)hRIU_t=R8Su!9`lpv;Q;7JI42G#259|6N9$>gB%7{29tRo}OOswy$)dcE z#6-iFMULBA8mRmudikxQyj@w1tSD>VC7MOHeh!8E$P@uwGoBmph~~W^n#WUk^VaCK zXq1g%bugza+1fdrvh#JyF5;AZLPuerK%qqW@+yu({y~Ald{nJF`GT?^h^o2U&#TTr z)kIlug0hQ};**2iUMK%hAM{IW>&R1lyaApfjr$~rzIto>xu~J&Gz#&+6RO06==K$_ zsA^-8K+fKXQ}a8Hfbq6R_E~C@}fKqXrYo1-REBqt);A^%6N=O zzS=A@u22KQeKVazKv9?1lIu0YJfdZMUYAH4%d4w&tCjQGX60zLAfRpdXs8ootw zg?ZIDPlaXGC{~ptk6lZy31SLlaMWNb@=F>)-GU3^kDxP}Ytit)C0fp2g8maM-Q8k5g$3kT5;NXa5F`_Kig<^ifI!@9Du0JQo zqevf+i$wbIJwT6yUGe&0JxI-3%>HXpq2Sqrn#1|1PssF>MD3v44J0TcnIy~42=o%N z{96@{9x+8{zW&2A_9SePwevYiE8pa0U@{s8hLfW87#>CAxtl{Sor66=pmVWni< zj$zxCF0ABaN-XnF_77q4_@wr|WS|GHVO8ebm%EQ;cy_kb0fyag*4>6yVS2dP*UE%C z-Xo4Y2rQ^j2x=4oHwP%;N9CYIp)f#r3a7;BC<1hCjK^v4turGD_IRk%e~#X$jiOPN zuxYD$v-gux05KR^eb*Iy~J7B9CJgHg=`W(~Tf<*R2^adjNWT zyk@rmB`maZtYVGm$ z6Mk@>Fk=$&;?~-NuAENPt+%eVfEf|zW~FAz;c4YU zX}7NZf>5s9XKo+e9+ znfLcwv0~N&oodk}p*uE7NWv&c!m|&29gk&h;&On{AA+NH3=SArlsp{f1sQO#I@-FS zwxK2mzRjI8iM9yfMf#-vlL#uPK^>qBBGiMssK3E6b~e)$8H_{e`$0c>ri;i0GCoMO zsgy8p&|Bu7Xpm8{ywIHop~x$S;~V)IH55D5{d_{0un^nx|UP~ z1|V261P&vW=t@}V0QKD9kIl}*G4#@Tjm*I=%xU@t|vjt;Qx@&a4r zvK(Zy1ZlL+Ar#~Vb~YQrX^GrwM@1A%r@K%VQIU(P-;Gf!VDc(+Z=$b*S)fs>ywq`K zgyn)BdH`qPAp?^!`WsVd;&S%vod8D?V12Gvp6Q5{(tW{z`ZQy?_1Tu&l3t&|CXtEN zn@LI!yBBQS;*!hlY-}6SjBR+u$UBCDxCn)+SaFYQO zudE`+lSy<5Ugm#W?-{@7nMKO>1(;eAQ`Ph3Cpq87C%HwB%$FbJ3CjD(#P#~`*m^h3 zp(c$(cWfoL=Vq7gkEYI#xYel<3N2gP-ym`X-DOx4+`c0uA?9nwru*FP?!gSN@{<_U zT7?;=7+hUyAT&F91Tc*iDwoajxu%9Sp`c@`NH>g9g7+rd5~PTQ?x#~wmy!$=9N@~T zrIt;`#(h%wq@CDcD3e<*b@j??s2D028s{`T{pfG}sqHfA1Vb=WnT368%FnR5jG!U< zNLpmy%HPt|J857acvj0i+m8c)RDF>rsO(m*oiFT_kA;0kR*4#n{vs)bbN(u1CHnZ3 zL)iTe&X|vth&9;KgWFQDUJ~geTl166U0ScnhK#4xzCa$9VZUC$!v~-#f(@vid{RSj zI<3r}Tn*69nre(imm(M0q>^q>+h~U{Y+W4vnvzC?cx@-X4>8b_fi=3pTvlYlxYi$hJhYqa8$kW^n4LG!8&jH9s^c2-Hp>K_)DMi#Vql%H|1Lm1V3O< zWSr`vx3TS3m!Z%2B$zWe)yHmjpnI|4QOTS^Go1e`z%=T)Y5!X@77$|*IzlmFyL_WL z>_m*3tWvupYH`$o5h%*ilj8~7TNRpb1aefd`VY!cl4n}b(as_fO?xX%)`w*j4~ zZ$wkWb^NfaAM!_fYjS@ohjrMSD0R$c$QWUim!L0PgYb?Z*&;j;h z(;hrZ7_=jOIi4Hst$%Kk8*MZhf&N5MN5LnQ)qbuCHe4z7RQuocNQmFPpn*wG_8=Lm*M$0tL>r;YIWF2~3G|06!s-$bBF znEIe}8R1QvTQ&ZF_zMbUc7;~LVIIWoYoA6=y6SJq-0VWbqa`gwl6vL7B5Z*5L3>J( zuZ+K-A}y!aK5s#m$d-7t!HA_gMu~%pbX%|^FBDtcSC&19_lSW~cGis-MqWcxqs)_f zV4JFU8Z!8$?_?jtvcpyO@R^X~IHJQslH>P~ThQKh`*_&NB+sktt?%*gKf^_mqSCX> z-rW?nbT=-JKSHCG3bWS7_On~;kxz~FtIv*>Jgau{Y?U2#s5az?{3EA*V9om~(0OS< zX-rhl-vEl-U-HE_ZsbUX=CX^~m39n0)iv>Y3)a{I$E{}IxF#>^eAaY;{tJI(NP8wG zwFgr+V(YQiA~Yy|4>d=mgFbu$5N&!zIpg~$5X!G(+vE3;DT+?K&Zjl?tVB~^Q3jVI z<2=c<$Fn^+T5spyaJTw=J)dUZ*Gf#9617Z;Z&c|$Q7`d6ZM|Q@wR z?i=gdgHW(nc>uMN>LhEQi~q>=6~2u60vNpF-V!z$vMymaar~Z#5>=>{3ixm#Dl~3@L5pL zq}g+#mK;r#LMA?St7+=D$p!KGUH>~5Gca>zV=$?(dHpv2SVWH)CjAEfcrHEq>@~Ii z4?xX2Wh$OAy}Y%Mswx!gf%TDHt1f8s*88{f{QcZKpk+qtc)!;_cxEL4y~a=tGjbFCV&6Z zSg`jfw&b!cJ-j^JG4*j5f5ym)@pTkkp6x9X7SQyZ+I4gvnJxT1X7pj2V$@}$ee64! zP3%3o@6@iw9z<2LH<7o}*z@gvZzEu09YwM+1o+VPZDE*DS;B-u#M6N=kPU}KZh;?E zuLO#TS)`_cGPfCan@_n)B+!a;8Wn(_4c}0M+JqH=6+U>jdwS|ID0eivX!%ctBQ)J_ zpy&g}PBJnJ(RcW@F9zPqk}t9EyTZ|1;WDa5gZ-ttsPraT4PNDk(?_-%3eeePHSlpC zro)o(G#=j|L&3r9Q%yU`Zb}E$#y5^9 zDZExn)Iwu9(00?;G1Fi#VAJ_>53KU{FhEsinQmob>mkmWKSG|6NHG z)Zr!2Azxu~HD}!6u~A(E4u!Nt`(EOR;2EB32_6ErJzN2nG{at(XPH^08UFDMq|$jD zSjp5^O0s4M+4@S&bb~k8^*~mBHHw(&?<_TiD&XJ$BbCmwYBh3^gs{PQO$l@}%Mx<| zG~jep3n!)@U04Vc)Ek5^aeoy zIE~~gGcc2@oGOJ-zAZf60C@@4(NGNGvB4m*Ayhyej!@zC+_{BSR?>+Mk5(H!uikPR z5Y6q5+B>6CJAzYjZ}bYOx<>gQ_=;qSOy|RkvUFyYoxz8f7P<9 zoWV*gLYhl^9l&1ftI&5435NDE$=GyB{1(hYg1pjPJX1oD5VBS+70)!|7SjvFPcyzzQ0`JpIPA$k#1%Yy5PaR?pAAABUm#j6OZ z3Q3+L6|W+s(5qLPsg5e=y2Y3Tn(S0u5Za=Q}BhMc#Vrq^dST9M4^mT3D!aL8|uFb zCsqjp`AXun&@2qp@tPGv`Kp|8s=V3;^&v~o^HCh5yv`jTlFkA5WmV%Sptv{KTQMEM z6HUB#&FJcw>F$_0T}!BiYXtpY$8KSE3As0D@9zQ|cf55u#ulU^vP40w#DEkwJB{2r9Ztq%iRxDfd zzqI#=*?|mtmR4c!pybbzONLL;0RHR*3d9lxZvUI-_$`%e;h$ir{mFodAMB?8nIVee z@_49RyKLjS`>l|TmL;GnLL2~MlRdA8%oLBM2_v$%kd_e~jg|X%UJg-@Wr?)*11;zj zup7uh{Q|1HqBG;3!CNp7k-MiliYD?gE=cqvi;Ty+&_9ve>{vz;a`+v;L7c{bKg!wI zrsGu(<1eWXObLTKfC005tK+q*I80%4z#}#o)T6-8+vAG?kgRHAI}V!jTidO$gwA9$ zosq$umQ&dHZY3iswVApw9>wqBUAufL^GP~? zd%U#><5N_+@PXVd=)>8T*G@9a)36laYhje&J9lV&aIeXXhOy8ndZW?vkMJIRFWrQQ z5*P$^&d}-vHSqYI#wAZ12?d>87!RGADDcFBuHuC`?iCf;P%m^ znt25f$FF4rW;h7s;P1{p)RC2MB!EtU}GfXPgPtuh%-5O+=Zq;NBZ z`gDcH<1MXjIPtJKv3vuoH0njv5!>1_5Fy1-#3t8q0C}+CxiZeV;VGsPF zOAhUe+Nq`*@b5uP#-e~77$01QAE#Tn7z5cM$Pp{I9Rv?U>JB-mC`th6{;oq)|JqN_ z!auUpfN%3bp!b50Lz#a(3_J>U6pap!-Ut-iO2!+o7x&n$83l2KRWMzYarEu>c=#NO zUwA%Wb2>A7Ub%%<@z{H%b6xm#MDW%0e_-veu|0nKAqpu4^VRVm`KL37=g=)|SrZNuWiBS01nY;gt0BO#vxSh_t!`$i0#El~4D53(U_63`k-|p+uzj!fzMkBk+}`$2*glvo z`D+j`YCo_h3!y4Jb(Xn{9=8R@cw*M7m`Hlu7|c4#U$!3z=dssCD(0B6RM*psPHAxG z^hypFe)A*QB&V?2m`VvrbP*MAi+dl;2ryM=NcJdlD5H7-^A0W8V6MgMFwr*?7nh`4fhZc*tPB)FQkaXCeHV9S`O`ttZ^8G>|;1CcSIDU z5YEt-R0L9%^Vc2wyOeXVjgf3)vOeF22<_`Xl=%*qWni}-az7dib8N;4UK{8=Ti|Hl z!CS%ALvSptpj6OYTX>KOSP311>^V9r-5b;L?|YYn+o$s*6~qvhgJf4V9`Z;*a0NpR zoQ4LXbx;Si5~l~P;;IMw%laG?7_{0!wC!M~3;c|RxkRg><6O{jE-pxh zfJI$GeeLq%!JdMDBTg9A@gEj>+X%?#0QsEG4niJx7Q`J0|Bm(2_kkIjYSEiw(-6CD z+#T@eMPqOTc3gW3k$qsH7J)U$3@g}MywL6JU2E|p&0xK6OYT>>$8!gv0ohx*-Czz{ z;ODxPin)-%(7qQEy_eEE%bi?;|3VKC?Ivh|4P=IM8;Y&5;M`Fx`^xh4k$}0K9d?o< zb0mu-naU9J3y|0||FQrovf}_zl2|P}MDFjg{Pw-!a|x=N6Z$ndvnwUDNmS1zKZLw416yJaPX>)$8W=}DfkA6N1r;YB{R?|pf8)~LG%Xfm8x05;5BOM+U(iLN zlzj4KUAUYDar~u;a#~{UK=;Nwr(sY*RHJb1f#58vGjc3zRbkv6-L$pb&~|)!Xw37} zzZgMWF}nu?!7bS!SYC&dwx|&x9YEw*cIc0Qkl((81}N*gk6>CwtK*(6*2tf6i&sui z1g4au$GUlEr2C!7G25zA>$CF5s0uZ{fu9H>RmT4B12MYG=wG7VN&U6zow-coW; zj%z!1acFv5*jN}ky|a-v`+`nG!E8a^wqpgMQOG$16NSAQqCTyD9XqU-6^%L&IaX`E zs}&in&)&U)H|oA3{6yl$;M7PwBWRDrCAe7S5?cT&@ukACv7)OUz*0cCNnk=7NbRh_ zO`#Weg@MsE-u~Co5aOIt0+mCc&LU9LSRDelG!}7iqCAeY44C`>8zuNFFa}rVz9VEE%!>o54*SFzr2ZQ@Q>|BvC<^UOKs1z(vO+HZHZOh6-?_ z_LZP{Mcx|RmQfT3(n>gvh6GuNzbo<9m%a3ZqAn zu_FnpU_L>D1opd87}ygZB=)1lDtm`%8mR!&lHP@B-pxSSM1 z>qCRkzw!QU7?^>hv$t$?oU65tm&y(A;wtXKYC2p`;>zmAdGWZ$;ogBu!u1vMoQdB& zT=*V=QT>uY27OmR!uYff`ES5=7Ou;1?Z$;~NQf_lC4U_vaZleBGcAS&{eDlmVcV8+ z!%g@dM7i_un}_u8BJC^OGhFL&e+|-J#_w|c8peL}KjTAwLx4U-bcWwy|qqrJX1V8CiY`ko$G0AY??Uvz~Lry}McW&jrt zem54(8bjHQO%xsMsmB>C%4s4u<{ecph}O3uHck*7&!+M!(&=|paZ=XJPRSF z)2*AkuxOBm#?Nx3PubXmv)7>pvFY(Rw zeFycO&+9ukQQtJJJ{+CU439Fj9pfZIc0E+PusA;DNPLNiql&~wxCM@BNIRjkXZxB_9-qa!J_Zd)8>s5TW;RHai;+8QYa`W!C)Q|zk(c=b`B9!@ zw@*_2MX~1@17Y?BRL% z>wvr?K38E0yI9!5ZnRmS`pPuOS`pqah7Q7XD>m%4e!y#|+!CE%fY7tiwB3VgBP6wU zQ4=sl>FHThz>Y`r?#LZ1*il?%4o{8Rd2Y6?j|v&!qMNpOs?4p2No%4D_i?ZlW>4Rm z3qVpk+irboCpN{ygnt!=u7x&+;e3fFD4SZdNfG`u7W^o8yU-H}q`X*upj>W4nu4j& zt!8S}WRgd$|6!Ip<@xOf(y?gHrvh6W+Zk-Gz};3`=eHdTCPBF4iS!O(zdOSAz8Wy~{H zE6c_S!}3sZSC((s3;~0|9e_gPnSDHpljhauP{_mCYbAbV~ zcZzDGWj0gmN4;g!;<;^Wz#a|mykI`o2(597{Qega{i{_zg>gbrFX-qs&eo57{`)sk z@>`U=)sjqA>xNz!lSEc$*ummz`QK1R=qi*Cp*&R;9Oo~B8B?p=!-1HoQqqtP>xOZF zpmrfXk79ia9fq)>sSiO~;x%kKEZ`7q{z4AHDUsa>DX)sE4({eVWjP& zF6Axkq(h&1pjE?U%GiC?wMqm5Ya-1_lXb&;;I_W9g0C;Q-~vPcn|J_60S%yYry-O> zn+wBda>db;yA!)LoNKZ>?ZysU%+zae5!E57Cow_Ey?qqw$OxSe1{nyS17+Z3yL0z= zy4Pg&N+uUf*tc^3YyyQk?HL_*6P4_3eK%3k7`lq}=E5|jNe|_~J3IxhTU z$92~6e9E@1$pu<`U@^TS;?Jnbf;!$5@MCbSO)gQ(hlEnERA307)@d=d9YgfC?bz60 zX4|n*p`>i@qv3hAoa$cXzcEu-tGszC*uDVd;3nVMH;bKGg991Q2P83o4n;^pbGA7eCnx$9lOs8r{lAsEn3@ zDDTpZ&rzf76V+n@pxkK35n$RuU#g9UnH>Zq>ak?#i1I3JX5q7THrcXC%wi7?N6pg>f4jum_K93tZN@5hMey%sip(xN^6vU*!0A?gP3HO=^gwYw#5gv znS<}mlltVIRWIbo01Gi8A-&!jg#H}Lrkbzf6hosE6R>r44@&TzI?A2~97L0kBRODV z<=9q^1!N2|mtdFzeSuqvSNW8aLxLGWJFb(ClERb?5^|z*EQxay^AqzpD!F!13pJaN zFN$yi2{)Qnm7^SnlO0*@u&vC*mPAN5_P&zY)a<4Z&2Hsp^2;!LS%Go?P1Eag$;Khk zeTwH`aVcL^XU7uV)1ldEwX-=~iG}nqMRB4pthE`y)E3PfgYku7wfYV>9TC(^mRD*@6Fge+N&tI);e}vw} z&Mo?WAl8(~vz<889m_a6eeQyIN3FX!EQPUV#?JCK5kKx!O34Gpik7_R!O1M|k0SLv zN}cVH^EQzXho#nC*rjqo_!2Cqq45?ARl;tX*YyG4S4?|=ueZLgR+&wRR`AV4pvYkB z!N@kF=YrNfO-mYCPhyt*TjZ;AiYi}s&<)AgYTSUEb@>7#G%oJ{-qMr83!<>x5v0jk zINlYD$>a))cJv-Ti{Qiod>s{TW%)H=T)yayggcA2DJn)BLWMu)(jT{2H^sk=_0h#A zu`J2^+qu~6=u;Z-6xnLSEPBtT$)GQOXuX0ygP9D^L!k2M&-5gCKS_aS5%881z~!5^ z0MPPH-TZGC2TJhP-HRG9#XpW#u5HD=%u{%szJL*$q~&q6XTIBv1tpO|69pOD^WP{p zv@H*OO>^ySRe=op#hL)+244L}YEGt4iC)B;!(aM?YU1id;>J&2FE@ON>udD_K9S7| za4-a=r;S)^$md`eVWBQ9JWT8}^jac6z;;oIZI4Y*cZ$|1r*puTf*s5lz!diTa}1z7 zf{EB?S_1P$-avp=@Qv2{Xi}ZaKg8O`6{Fo-3wl5&(P~x2P;)Yl=I>Tk{XaCn=XnLO zHcXctVSU~2WaYv)$nC=pmo3ZXs+CxmAr?6IvzaQV2o2MJAniGKR?2(qAN*kG{y|y= zwm7s(Y(TWu^4zHB3K2i4a74u$uz3g?c4MZ;-6}<;L zDaHqkw6J&s5riigk$}xM8;FIFki~OMh;HEQwwX%Gn<=xrnKN1Q35?yGAj&nkmAULD ztp|jBNs&RvS5bf8QGfTTzptvl z+r{r?23Y;83P_=r2A%ZBdVU+Ahc4LkqMGv=_4i5j_ff5+4eDjeWd;|1%$x34-)>ZY z*NR^juK{*5a9xUP7OpFBU5)E^xD3XOEK^oimV}G`WvYF$oXre8o)OI21mp}o1Fu@2 z?TWmUWb+AqdiF0MGB5+=iUv}RN&P9_XKC-(QHzqZ5d7%|D5A>@@H~PO3wCfiSnunG z$VJ}Gz*&`i$BM>u0^YMY1e5A(TYkd{8ZXYEKX(6p#5*pTFxq(Rb^bmhp=<k=NKmW4`sdiX07hmHv7@Bc^H- z_)pQ(O`-1+o#d)K;t1lK%i=gxb~%ozYH?#@+r}D$i%+K#XVS9t`72mf{hfkp=Ao2!iRl=>%bztEb7g;Hy|j zJsN_KZaH)s5XEbJ>iTsY5uR z*}m?W$@=w3;GGJ=eCnDQ|v_^UyiqBs^7~MuTS|$4(I8nMm}WH6ctMRgtT#ZsR4&ifeUbq zNs?^_?rmwTOSaf*Nv9{NF!1YO62C@y4Hkp}FN|L4RW@V#i$Rd!BzJY-5WxFxyp2foXac`k# z5SB&Mw+MR0T#Wt$tYeuh7uU;Yno~JS#vgsKvVvO+%VW)e-iYXEZmWxfijtuI z{%mR#K`r%rRhIzxJV>L)=Ep%ysb#LPqH*NT1c73bCBK~x3B%B%L-Z=ws1SFsx$f%d zI$~&Q;T3?Gg6>qH3sm!xoeaX3^Ng_fdhZ8SvcMvmXR%$G{Qwb)C-DOeK#Y7!(wzSx z&PE_3T4`4-ycpn!LPN;#nS#wIg6pRjgnjRKjB9b{AC0?w|#q zUEfbEQ{jcNWl&zx?lplUb;IK|P;;}xcCvS^%UMgaPnpH-0jwqGeJS|-0$`Zn^M~A= z&kF{8$|Nl_$}aLLS=!^Sf-Y_==qvj1c?k-zO!{x&1pSTJEp|=zdhhsq{4jWvj<=$- zt`b(-g-KT01Xy`v`iMu)MhuM`5CvT#VUm_W_Mb?~(2}&K@?Y57t|9(!czm?D-! zhY^;ai}uwS=;S}HVqOWIjx|9n#C6PJ(lK?UV{D{jb}WF7xf;1uC6iA%U*WVcVdznz zcmegPvl8U5Q_jE>ER@)p0x}gT#JPPbuzv>FT+gh5z2*mYMap?-M`VpN13rTvs}<0I z2GM{9>vIeIgnSXs1{ASwJlqD=Hnf5jK)#5OZx$60WCCbVZm5N{a-0QE?h~yMgNhKR zv@zqVGlfVc2nJ{EV)EF|6R|#(97KWtMP7{o>y*=ZNgIY=%Vr85#xgex8*RbWu+Sz} z^CJa=h&gzz&z1X4y%gVX#c<>;1E_n*O(|dMDbHys@%mTrA+k={bp|IY^*ePl*O&L# zoB+3}=h#CNVOZiZoXFM&Qkn~#kz*Or_AVfR0lAV7$V=Tv*@9)PZYjoa(+&^{6@CYL zIR$Ph-~t?-xCsM41*p!mh;Kt=3~ayh-jC1`d{5-lsEJL49AWz-SJvB=x_jv*PZE^g zuFRsO2n8*mlWg3ZxQ8obo`$dFK-*12p2%$thR|5(h76pAhhbEn-5{#rE{qtd5!AX` zB=Y)%s#_kp&5tPfGHd%E2qBJ|C<8V01%i=W4Y9*%Zw`N;y%|h5+ZECRy;e|vpzP&tA zj_{Vi$HFO-$wmp;>u^N%`PHOm(NQ-kwoeu;ep}3;x=_{14^QWu48}pg1th`B4>l`t zfFce!B<-vpaA<8`hg_Rc8MgK9RE+nWj3ZKrjjh8V)zYZ?4M~7IRz_bHR^Jx2aFY|c#3;}r(6=`!w4r*AY^FcOq^9u=ey=dzjlm*%&@BJl#2XV1 zKFJ42jCNHPHBeElymXq-Oo%IN%HeMb|KZ}N{&xr;OhJA?`gTYN6^J`{0QG!=f~TYa zD$xqO&)^nH-C>k}PAW$^+|Rqf zCja~(9{ExxU1{0WsYW)F0uG5TNIpOm2p=x!dWq&Ko}T~+pZ~H6c0qEq2L3*D-4SJA z12}AVWB-P$(~keyMKc}AOzOh+q3zn?HlUd(|16ak!H^_x#x^v(Ff=~5<1^la;4R(> zp#L*N=?|_F@i`(lF)EMGy>k`RhDJ5S=a$Z=_#BZHR78Bvi)WhoMgcnwEcjmUgE)D9 z;5e@_T4h%*pd4U^B)(3Nl5<3)+uLsjL`|ZIzZ3B}XOiV))6==956;HU$ew?zyan+% zZoc`Vpf6k`OdI1oEuf=QHWi;% z1T-$=j=pYq>2FMMVX9iY`^}Met=w6D{T;*?ccdj)pQ~D(mPGI?N-^TjC9@izunU@L zD8ej81L%)*_59~7zk+eltF#Vs0}U^-H&MS*H_srm2R9R+pT0jZiMf#TlqbnUQ_Te0S~{#18%j$zA*M^BqRRn-~}yiQschp z%>*mNlO(nH_eU(w`2+lw2mYEw%Ao{Vd9}mTMI@s792|HiuaEOLf6mgM2eG>w4H5XD zGacw-eLiLCC+Yfn82bXfAoMkv5=pj&@}~+Y+{Bd0cVEGj@i*$<5ypQ$fBHIx#i4`0 zgCu8(n#(s7BI!m%)Vm7p013!jO zTqoQUZKM|r4$9U?!*-0?dz8|@& zpO7Y#2r4-(TJy+6)i`8W%@4<5zQ2RcN8hbnf8;nOIxs)R3wKaqEjHA0VN#;*3@4U! zR4emUs5{troK{uo-zZ>C5-=-7XvxrWSyHHtSF;t>h-EC;+A=de)HX0d;3}ZH=p0Se z#N_VfX=v^*rlPr6T^cZW0|q+2-B4Sv{B;+Q|IJ}M1g0r>AV(cu*9J`ZLKfcCDmPN0 zs+?*q^*2b3Z1v)6P==OM0vSpbz4y6s=A9_Dfxmb9Ulpyo{4i0HsDwUDoFm#gL4^Yyk=x=DvpvXHbT>9Z49Ti455NxD^XPlMTk4z?s-k z@rUG`gFBOQCiPd~EaYU#Id>1qS!pT0D%tZ|KVIVszdzts79^M6NTqrF5m-T2+qjb| zoN}IwkYFmb?NfpaM9A9+@3Xx1YyYgxNu8G#(iyJ4if+miB{0_RfRYe&lafXKU?0on7q zV;0JM(MXw_b-;n#JKiVGQ$`^#_TG2{MrzPJWPlJg=8K+1$ZKC958LvU_a+kwhH2MS z0WxsD@)EMB>?(kr+yP*d1*Doh#2!Q0FC2s_jZNlq>P1q<3;U1|%zR-}Ddv1HP;LVZ zjtwX8p8x=yyBvv}a|0Rm%CC@yLqoX?`4z$Gb)N`M#|brPKs{@6~6UoV+Zl?ky0+Fo?0~aY9l3%_?FK=uOT&%20PW~e$L(YmIXI^*U z639$_^826QJ=!@NX*!A4Aq^xF{I9B4a6STq$-1y~oT{~O05tX`X!>>3$6UY8Oj4z~ zepOc&b)W^%*r~#FWUMNhP}j=64*;O5TsOryz;aEws;hxUoX03$l#qCQPe28`qh8qq zECZ)0i!j{kP5mkMvp@hvj4$EWYXcs}du7OYk9ag6S7C`LxBVF(4J&*Wyhn3D7`VuN zT!Ho(l>9ef5`%lmcGspW#B`88_E#&%Eo!T2-p0T70q6$$KsH8Hukw%A0ox&9V-;`! z8z&ATNz+kS06naZN*f3tNYvm?sR5s(j8Y9!qK1rW^ z2m1rDWs9=@RS?{d@@$aLM%Y0)GslsuOz!3tdU{@wo4^&L-H~fZ{t|<5W;p8Hl0WrI5fZwyymY^jFo{`?&R&5e?|8?nLCfQI4%6=}zJb zH)ysRFZ_8tE1&`GLez2{&rO1>=U(Wp1ehy$^_70RUO-TO1{J6XB6mbZ)(tRDf_(xS zJ3#w!fJq@hWb>@6^{iz8jPtHQs>s$#{|9<*!D#!D4hKxnjV;)K(Zh4QVIuiyO4*`J z08r2#tAh3@f5ts|iMvnXA$~gcVJV+F_%9+oK1$z|i0Cw=D1njui5!?@kylA|3<)NR zC0{(8xcl>e(yh?c4f$u0@InK96b0@!?|COTPlW=hT9{b2CG24yk6V5l22QjU;f&Gv zs+3%@knBf%vq9YG(6N4jzTdzP8+P(9aw_wzD5}|&0b{+=xdnWUg}rPdM2n8;ZPwPG zIQ`W9%2bq~AxsR>iz&M{L_67H8$O?!$=TO0Q|=fBiNtt(KIK-8KCg0)u>~1~ zIu@t)f&S)wL)OEpu~iXTwJHDa^W!)!voEXRIV?O5&+lmT%8d(YGJ(RYaqlwsiO8VY zdZ!VCJFA+n_-{BFmlt8-%zR}DZZX!hbguBf!Gqu?u!>7+fKv;kh9k3ea&DE;n1lpbW|v^|nMe|!`jTg%P4+wo~Tbe7w* z{g%;aH)fumTY{YBlBq|=_b=v)^=GJ2o%Z0~3-&Gt&lPXd)cYT^v;hR0cyZSMMj%7r zX+?xANKaV%*p2X0G^2aGzzg+`0t_8Fm@(G=+U~@=&SF{#O?>T+16!i7H{QvQGE`U)~SL5GgH?Y9!F0f*hs8Lr935v=OTJY-uL1`9D&jAb( zE~a1Ne%25>+OVoJq0JX)kmVW47>*pKmoIxl8p_e#7X843qPUsUY@BoiK4C3wQgN<0 z7{x4;Twx9%FYIqM!BWh3_xhU*=~X!?!%mg6bYp*V2tKd|!h~6lJ9~U=@bS@9ixNw! zIiBWy#z(je)4{SQGXyNbt>qX0R9vP7*AcAzxvy7e)enueWaCQ&w`gx!e4dx^Rl{56 z;U8bf%wmE#E~dTwi!pWfH`g;y_%qs{r4x_iHyYQAxB}Iq@6X|j|CVL)9XFVZOF#7A zRL&n7)+c)f6!faFC%w{CeYUIqJlS&U?N0YqBR4W2n+5u@2PeBC*-aa@plg>g)PpUR4GWGV|m1!fwrXdZ_jKvOZ0CeqK+$LS*zgwB3pC-?%Bv1j|%Q^{)(kl zaEaMOI2{E1vF%|?o#ZG=!>9_&I*0)GOluT2jyr=&2@)QE^LB<&tSi^w{ER&0NUgJC zIa2Ga#&ID@N8GMIazc7dJPlKFKxTk?6G z7=69_fc#gj?%IKN{nsRUqDI&+32`GZ8qV4zf;?Qeb`G%2HH~CqWmax{Y?dxC)|x8@ z?(elv>ZeFZ??^WB+={PF{XD;IOI1~stMk9arlX^Tf}~;~dcIZ9`mbPW=*=a@woV`S z#zs1;r}2pTIu3A>8&<#mgUe-~1KU)ox;7UIyqz`xa{!;Bd$K$bU+PPgd)miqfg66W z2IIfl(HO_e zwaPA*p~keeU2ABdvT|GSezVMkR}RIn=mmC9MnJ1Ddgbi53ky{BFiP-7jp;W=&-Ps0 zFehiq8O}*0QtRaV^&VoXnvvWLF`Yu*7m$zRC_{@4VE)e0Gc|3Br}1IFmiL&ivG*p` z4v8#!XNv93G~ZA6wNEmAg>8qScd6TRIfC`*sM`5_2}=j7Uk^W+jO;)6V#$|Z!Rydm zfT&G>Or6lkQ9A4NhdSJ?;jIy`3&QNN`jq(!#s4(SSWrTzJ`7iZvmA3-vm)Zoe2O|; zQ22W3n>d%*tuElN?n#K^(^}<^?UnJi+YeX zw5q&4RBG%&V)hS%#E1L0g6{oBi_7k=vam~A4BkvRTF)O(l_k;|JIuh!pVpm`2tHZ5 z2j%k}njcM!O-K{gge%p-7j-kZ+XWAYr&*IGnDTey!_rUuO=k-~UE>j-ldn{v>x-mc z6~5bgBpY(Ydf6r&dg3d(LvfK|*^7LT(snkA3{(NuY>#c{fOFNfeWR5=Z za#C5Lt_2k_{?+4!(>~9<`mQ0!x;v<>S)t zOqK}bD-wBYW>%`JCepJwQ<>tWuu7~hcdN%gK9rm{M;gH_3Wi`ng}N9EI~kxe()^Xh zHOip>jP~Ye0TpzQQ3EuB9?0vf0Rep-#$N1l3c z2|KcAsDP`8tC(vnmw3?&LPasKXGPZj(R)-i+6Vi909S^mT~%q3SX&Y^@z_7){gknZ z$V?EmaYygbH}d< z93Wl(l(E3a{xgn0?-M~_+w9Yh|X&8;4wg4rx&>YZB2*)ki#N#mbBL)!W02Yk-9-r zlZ-%TQo!BJA%f&kk4qAiSFO_W@!Q!^v5~V(Rs78f z=XgzAn=JjnAN#JnvwAlAbv-tOmOa~WcK3!&_wr7RI;=(|dWpXo&sHwuI-fB^xbF5e z*X_587Bu{p2A-JmTwj32Oj0Ps^=GC>u{iy=hln+t7D_==#am#0yaFfK&#RkhR^wZ_ zNIkTQn^940h?~_=Vu6SA?DOG=;15xmRacz~PQ7vh^aU{-WPk|eJR(ZK4IVdiApVWT zvFp9A`f&^{JUgVB#^EWJaW5x+D*Rd;PM0bp56r0X0GVQyUXI^uMOSk< zFR-Jj&8k$pK9aYIblGI3In?cv?rDJY zW|9C4t44XXaTu?p{4fPxBX6WY-pmqUm1>R&462;Vh830h)Y3!k@{hiy^EWRhPl_g& ze&&x=@q#!iYP5_cwK%rQ%ZSB0oWzF?if19L>81rsr~4X)hyeGbYxy$XhvTn?Y>}-6 ztx#eT=L(}ut*eWwEj}C-{SfTTOX>dJ{?QTbZ55nd5Wsxad3-Zj*-^iSx-mgbFakkz zhw~h|!!yZG9_pPZAWB#H>SmzN4yNdOBUQ=BoM|MOYi4D+(@M{iVqKnk@st<95|xZ$ z!U6+s*>BnE1rT`=oPj_FzYZ9a zIfT$>RWfWxlYSB(0L!VbK>oH9@|Il2ow0wD2dpJ7efM|Lwg`rt#|$R#_` z{}}acvF0p?3{`m(lLpJOL#6a#f?Hyajj2>GZq$`x=H_PE?IZ1SwX9PA6B6-MHTV^& z2C!q47YIptPM(>k#Gh{@0X%t9EoPLJZsUE;^mUYCSsA>K$WFmm!x!Rlf!93msxJ}ERv zyoRue?VHnCFXO}Jbea#Cp24bWYHQTDKOrnS^wN~C;|=qXhh@c-u*v3%FqjpAnUb4Y zoa~jrToqD_6aLyy@g`CTSyUQP6~p?ET=ovl7bBw-2ltJQgC zp}hW6>NU9J^O}{ERcTwUB}_!pW@_s&I2g~V@a(mhs-Ke;OADc6>Du;lroBjm$ffoF`EN%fj51$KWF2u_WbFV<`;jc; zQ}y%95r?ok%|vK@rued563VMGjh59g{)P{SB*7ojE@^o;J8aoM+w$(+>iG}JO3YPe zOTu$UoMl_mSK0FM9_fD~>4|9u!AW=?COu`q8O6UDFb>6M2N3nxJhCu5z46IHmmfIo zP;%Y#k7vF7SL08{t|rOm{~?etQ;z+mf9YP~49Po_;BdlYmlY7E$-Q=Zfo!zCDS7#> zb1QN-RpA7_6{dVJ8zM3cmJBctfrkF;*xatIE@)!Ev^zRfoo!}?fIgP>@>|~iokP`d z>y?Jqb>QXvSp~%liAd(p7RJSzOiN^H z*n%-)G-09(kx4BxathSVQ0uYxOzN3r1kJjN`O)RBKhyZuLiZBUOW@_3S5xlpc*LvD z0CiI?rj2!GLp_5g2Oa3waW->FDj&lSs#Vz!m75$gsATOhUVo|6O-PO`;@L0pCjB=K zg*vdb@Tv5OKPE25rDGQ|w6ynt8hPNw78FIXcFpG_g{krO_w%gpckAyf-;&Iy%RAXH zooIbrqd%_JncvS+Zu|Se{U-1$^!MxEDm_wnh8!2Edl3wlzKJh|KS|Br&*}`6{;59O zc+>hzVwN58ubD|@J2l_;ewMC)Y8XsZT5Mv=X-~GT=D@xha3qw_^8htJwYe6 zmkq6(7c=3Z_WzU7BO?XEIX{@D5k1btrc7YZW1WdjV`S`7X9zOPZ=-6g(UzE2)T;Ep zcq?;uX;$gKWX@KY`{GLr!s-e3ZRTwE3fmlz&@+LK^Jz&rP_s(z^+0Xc_=8D(sv_gr zcZX1@>B0K*v^d3>?@0?9dK|^wPEO=CTFxLn^IH_T(`7#+{j^I>$3Y)lP=6j{G=@2Y zQ?yq4p`wb8>rh`KVdJW~S*D6a^%rh^wnwb9wnKq4<+N{?+A9+1UE3$m%~HGO=y~OD z{*laRO&kbqYVybgrYEqWUdcr?WBV%*I{<5$t-sts73yXQU!3=W?o%y*Zv^;%Ab`Jt z(+N0MvymWD9Z@<6;pRN&8G&uT_^CQgpwGxvBYsOmzo;fk!7r*8XxNhX;Sd6S$zS>s zGnJ+5@eM!jd`oFO`e zB&SP~-anthXHOrW4GCI}O+It7p16c1E%UV3LW7kxEwsa@p*89IYRpi&G5=h5JOfI& z1Q&L|=PwP`_t#zA`D>_9K=*H&z0mPHKUDpsn!DA4zwsl>RjRCBi)D@l6)ELI99 zb^km@8mVTyvzkba;c>u$GjC)1LPUe(=O;W9%!3z^cb38SV{9>sIIty2B8B3_0)0+M zwnQ0aiv)q@ZE4rCcNKhfHV%}# z+0XXfXk~}rO=Dv1-_3PWEOdzX+B3n`b^>GkT+z9hkahzi^F@nndHD=<*L8j*Sd&uc z3#%e4>rP{W&Uz8%jK+6mm?KIl?IIVtu;f__#dKu*_uJOS$B|9bifofYk(sRIW65t# z`SS>?XRLgTuvBq6pWENG0qpw9*W7!)(r5k6!r045k|i&U=>TGYe+-hX7}182jWY;# z2(jIvzSD6e*|ZP2w!dkoH*4GNd=$1OWdz@9av%Bqn=p!FZ>4NU6!zO;WJ!FMUmz=rz_@ z5l32?v*i{mQ_tBFJ-^RPm-Uq?E2@pT)|H*;(2(g1-{6}Y+TP4(5jigriG_nGP7n|)L=t6n_&(YUtfK8Z<=S|#d>2+t5G zvvByEekTIN+IcGW4w4RbF_xsGMr~ytiDDu)DlGR}W~SE~|Bba|sp`x@E`mp6+?^9U zTGk#3c-gy`uNn)*1GV$jaLP%QF<;6+oslw7Wh$s$pbkU-wQ{63Klp})gV?xK25J|g zd%w?4psgiNvH(befJvn$+0+twzm^w@t=_S>mi0CkBk z+#$0yPb;5U0MFC_-Jz^#UhN_^$A)5wQfkzlRu(C2h>62BHl>U%GS%41YZp`0DRxmB z_shwb()^rMdo>9@V_8Y7hK{!Y?^fr+A=gIy8d5W zAqTSg73^Wfn)Zh?U~w(&Um{`r=plG=>T0t~BP@1FLc;Gz4iR<=k+;c05$@H&LcL}} zVSuWN^ML69GEv9VFf&2aJw2TsE_lP9n$_3@?oj`f(-^Q41}!WMT5AsjJ*KDHF+Ihf zAFKUO=rhjKdf~?P`SAK)&Qrp&?3#MqCq7^n$|PRI%IGTDM=O|p=WqJ0td+8&ctY&u z9+1DRA>kb<`{d}ig-<+>o4@(z{2hrtDaR=YDmW^+_2(i!4$w4ZY#YLnm0D3p#AUk8 zvG~Q~sADQkOijV_BYS=WlBp`3p@BUw%isNnLC!1;5e!zW3pqDFE@ykOq^ISU*+MUw(iX^-|PT05{>o${N5 zBIXXbqQ2O6Fa8Pd(e@|8McDKzo!-ay#~kU&zonP-Xpc&s+96@pLUJ~5HYoiIGno1w z{$0=Sf*Y7z1>{5-R!MW^VY;V6)yYG(w^G&WPq-btTz?8ws4@D}kV^Gc9)#0WXUfC2 ze5zr=J5G`aJfA!Wywl}D;GL*H0dKJW1U#?)MC6C$-2yMSS{;ywG`vI^jz|B>yTo)~ zg?e2cAfRfGJd_2)s$GA|tx%iwr@Tt_JN+p?tiG>5omQb@JjAw#s@3=8VOz**a*c27 z8?JgE?tH^)mHy~SO!ro(??~2aHa-z~kf2HnjS+f6A{=rTSB- zQjOA|knVkjhuHSBtCdS0wq>~Mwc9I4fATOm*vKERQF-}ik`0aDo$|2FJHJg29o+5V zL0G-2Upgb7o84};|L^#$TkZR1W)0ZNdZ#n1PG3{4nk2(&PmQ{chZYO%j~ypQ&{!Jzg0G7yQ~DuLG*p&snU|>~aonP)w&ER;~Qb^vgaceO|SC^H&b| zw|!3ff@<}sGyUVAlfJlGUGGfKChVyA(=#(t>4)Gy@TbyWbj=C!uuU8si994V|4DL6 zD*ac}LvEl>ZVtK6?xGiD$o-y&*!E+q)eG_{N9^`EP7j$aIv0dvgU)54 zkVy}m_}r4p&%9Ve9u4KY@*opnsSWOG4NeEG$S8kCD*s68Z|6Tj=kHgc0`eeJ{w&GA z9lTDKhi&NkSheZaKFMF&^_-kn$nEwTQ4jnZ7VQKi+^a4K*{0nfnhB{!4cEv`Z zPVYw#ESPVhd9ejXd_QV53)EQ_n7lUXUqJrRI{)aJO(GHOmj5yzS^3cr!=E+z^QHZRy8U5c=mKefPH(-@1>|C= zK5!?U$-7GR6i@U%nK*SEsZ|NoP4e}U(7+0{iYI!4U>4rmf#%1rTZQ?AzUJW?(1cT` z;plT*J7pl1GCieC{POz5?`vkcIf8-4Z@4_Mf5sm34#8Bamn)@8>!~C9omr~S%<$h3 z4QWhMX3BXf8G@!n(Hf7^7|~&R%soSXvqf&#kYw%m)%G(Xg)Kq1}wcJV}CIt!`IDC9qbKP=%3 zRj3svcnH@uJ;4vk0H1EZFNFUH4L>&p|5$m_gTW(DG*yK<_#>&378lcQdd&P7x@EQ7 ze^#H-y1ey31Q7LEEl-m|$A(o@p5XZ_)H?GkOj9FIbdIwzPfC|;j`{zre4j4=4x9l& z2ram}M$bN+s!@6_$cNC3$H}b~%BseU{8n9tVH6*^R5mxT0uOYA=j) z5jJVt8;&Fwii^MJB~yC*i*e^9M-!m4=7Cs#812U*De~bPn;^MNJIjCbUHlc-@63{+ zi=J^}I=}o|(aXm*^3{LSR=ICz{GV@>5xc$l`}}OY<7qPn%lEC{M(a0f{YI?cxz=yk z`kiF`jfsl)2* z=tZeRY*91e5ZgNEf`aQa2YsZA#RLjsjBIVT;0Q9}eol{2^ED-y2L^KbpnbfPxdMH| zKcVvhClMmtpkaz^~- zE^otWVxB2dAZ?lHr;g#sdd9X`X5O$vYRqX1rKNh@YG13n`?3eM{6pqyRG=>LYW)b5 zFP7i3Ck^TRtjOc6crKyd>`5;L&v0bFh4u68f^{mS%NHweB>H9EwbP4rdCnF&0<>_X z_!*&^)#_Re+je!C>R;=;`f6hsrcQ`xIIq5}CUJjAdI#HdnwNuvRM41iN?F4-Od>AC zwmc>oAdI4Nb=y5W$8VBXTB0f%00jhGcyvLgy>;w82?r@o5F0Xh`JuWlf$6vzfnrl@fIzqQYOC6h$i3KuIGWR ztSpWwk7ex`J%X~w2he=ND;6SZ+^7hlr`p{P*9)!uoUsMmkw9#-U27SJX0313wZ=Vz z)_b7V{xw%2bkprZ{IR{J8)zh9d)*5ntirTd!ZXONv_A*2$;lIa6l8U|V1QS4UBeF$ zt7`Rr%?}v;5%1|EojwA$G(Brq)0VR1-tmA~+w9fnx0WkMQ!k@i$P#yaex#@OTG7tV z6K}WL=41H2)Bp5E04*_eYor&wV~s9w$+Amj5(r| zv`@5i=U}rzrjnM@HgI4Jd=V^`9t8_P#Ah!wsfaxq&MdG;1E&o~8x1FIGn?5O4R$f~ zUmg>o`;Zu)>z*BukPwXBpgL8~E5wlKcsp1NTFN>^3%<9KMyELyOeX|AhT;8fR>2GA z$0HHZWi;d7NxUIBV);~!Iv4O_reZss7A>~iXdvTVcKsFT!{JB33!jDmfKLjy;!31p z8i_d0#*lZZ&p}@wrO-5eJ(a(p(QL#KLyx9kW7}lUss+zy5SoDqPY`X0ujujwd13#Z zBE~$JGyg`IFgPb~qCDBW1B(cPvR>$mJoa-$>^WhzajUMY2y?4T4xoY9Fz_WMhf!Tw z%MXazk0^Ot!{F4EsZWN2H+pSTiWovVg3pwK)_1%m`)_#1h1qk-{%X*x`hf(+kpfJA zt^XbkLb9Bh$49ek#Fyw&cE*{j3G0DA&e|@?&4~s*5f7(t6RCo!?Zt{r6J;5*7K&$R z{{VUg%Elfp^+kOC(gyLeMLLIMo~|FA?Ir6$Ke&}>i5OxIHf|PI*y+fEh^>OE{QGRG z0c%d~qd9GL$5$^(BXD$@uzKMahB?;>^OSV9Zf<4=#8*c(JFXr~f zcdY@xRFp7JX4Hy*rE?+ry--9J$_Y-?b*L+|o2^h+7V36frzN-(2%D%?a1^ip43)NN zhP|V>M=&%Azk(+?&*{rDx}`E7Xm!GxzDza+eX4NpIq z@bu%Cgg4lRryops`teJ`3)=AXg9%SReo1&kZFu^@gr^^Ec#H0Zu!+~A9cW=V;<;(H z$9`;gWdBeUQ!zO~@q-qa$kwh3&BV30Z6NX}r@wEOiWOcfaX>|5J6w{|>)%zdU}2 z;@~$P{MOul6#SZH`zZ$OU#|UrL?K_Y{pOH0(#Y5b#W#_}bZbIpPG=AOC9S0BSY?kI zICEvHvsnv=iU)tV3s_@^r}sAFMqy)_h(*{?`c}(UqPqjJf#Sw~_pdFNVLH9=*JUr-q*YPQ;fYgORKfZqzO zfyDq_b~;}tUF3g6q9Xc8#VF|%NKVbMp~q0#*2~7vWaR#1?*uiLIWXnqQ%=iDO1?+X z)|&YoArx0ts)u=-S-NaQZoP*Fwb;n<3sY49kXXz&NFL#gkThwnBx`G;_tr8|OWU1M zUfurY7~mEgH?HBQGiNadi`Om20nXCM9cDuyvk(jWlhbhRefe2wCMi1uX8iyg-T<~` zCQSbmE#b%yeyi>AEmWVsPQ;m*%0Givt1Hq(dEy-)kD5QmCk>rW(<*z~_UMZa#>Thz z%WyE8rlzVwT`nbINw+OndT8}9;}19d)$MXMemCdh*mH+3tj|Hh^{m7*!sf%~O0CGO zHpkyRWUOQ4i4q(|DZZt@`Fq*kN;@P725DPw+xwC34mUD(-a-PR0kJMr z_Z*_69qI&>(~z{E0^_8sakf&=RvE+*N$jTfWJYml7qr6$I*t+(Tg zWRqmrBClM>_Q~hiKDpxyf^#sVg#el1ab(YzjR9USdp`N}iG1o4Igy#@xs@`9O9yqy zj-HjG)9(6Xv3e5eL(QX_?h?q7KQ1=^V83*x{8?)LX)kE(A5=NJQlWjsKdUg~pG`zo zT0a?VvvnidA^5gP!Ze=JRt^azf~XzpE|OR$Tf5aMVhooG&7g}E*{mq+zD=-4Y0{L$ z^%iDh0>1~tuwl)NN|zat_t0Y|hoYA^TLf~tUh6Co$S^I!(G*DBvrI`%nQ@UzTS#3WlRA*gX0J{Y z{QKb(Sm5FMUEN|O5Mlz@u4R8=5@fJPFA%1)an&MxcxdIw$u5zYnwVynSYW}Yz!;)sM#b3^f0kVuO?e2k7Na(wm0{fWJ;5mF`ic#+x05SI6_ix zg;OW?w*!3K0>4vTAo|SWfK&w0R0u)zT-s^D{Oyw$WzEqwlkwC=%t>oJb&sbvk5D+N z;j#aS{f9jo(HG+Q*vP7`OoqkPjHO~teVroru3uaAjRZJQWSTA)b}AJjez*FuM5i$+ zOt<~<7bWIqo8bL?e#gZC17)k*;0Mm_!4H^5ZsL+GB+}6FK5UfBytr^{@3$ASi<>(0 zb-XMHK`n@viPC!@K0iM`KNO!|khrGE*u_ear{-UGFu8VK!DCr#%jU-C&z3H!@L`LT zC)tehyuyn^@#zbx@dF#EF;rF@q&diHW-J?NRq!qEi7(>{T^JK71Ts*4ESPo+QtGK+ zO4z-(HQICaOoEbYub0-qI^Q|hikx$8xN&_nzIvA61V{%zhE2C6DUI?0pM5$_YB6wP zjXht+1d;wLOPT5sLI!P=f_5q|{{Qe{iLYS&6)&lpbnA1wnqP@rIZSLyab2k@WuK~4uE~y*Z?0nT_zz36lx68V_lx~_)Mq&hFGC_-II_M?+zzxup+Y; zN-LYB?`NB0oTT-=F%*mrHEX{p)|JeRf|ZeeXevGNL~F5dO;$$if!!PYvr_3#5=pW+ z`@!?YMZVIDef5JF=9Y(rhyzK>U#Um@pPmdE(B^O5j=aYF(wx67V&g=lHmDR%(~RA+ zu8!vv3;M|ds(wQ^ck_n&!V8V##?uv|9)&;KO>`HmiN9HdwXvMBe8HdX82M=&H(Ju+ z&laaCu6v95!!+g##E+3baA;d32~3B!ON?=n%jwY8_@wn6jyPZZjySWGq-kfilE2}k zP5ETTnJpe{^W!VC0=kS?YreR!?Zk!cegSUi!o-DbJ}zt}BQ9)RC{c9Y4MXMWSPFQn z<;|aaWu$4o!SqioB^$>{&G1hwIA;1ME{lVML)}o~ONoO-ntu(kG4+wdbiDC-)#=-q zG#N&a#Da-VC9U%I^2r@7mQU}u^~{x3A8JlU2jC3`QF~tJ@g+(9ivz(Z&d@yAZ_5jW zqaO9aaNBK$UP_4!+-*2p<6kxRQckuuf>X7_ivKG+7LN@9eMX%5;unJW8Et zw}K{73!ROSF+V4#=3A*bpD|^tmwq6Y&XwItG#!QuX+dm(&wlvG%ehNl;+RDIPM z-Exatg=`Gwz;0kKpWJe4;!*!>?b!e+t4M+&rr^__L#d?Xd8(H@+0hH+(>=X>!c(1m zYVPGz78_rEeigJ^Q+!BTJc`2>yyHQWob22_VYW+vtst(J>8#~*+S@X&#i`^F-QJcp zU$rrw@gtBvXzAGiRvq2RW2-m8IN#KZGN>HAao8LOw)lZR0~4-b&C$yj}U*``Squpgid^1 zj&#!B`-J4-aQh6lW??mMWelS6ffp5);SA<`Z)!JCp{~2noNfCUk4J@nn!vBdbn3}?t`2CPsAFqiNdc#PP{twR%l-&ri)6y6l(7yCEl=&fW#ZNwoDwiCOh56YU+UpMB{mp zg%DlV|0tjsEdjj$gliHLu~a%~Jreh6dcP>K*6RB;P95Xz^fX>M<`bh7~ zBdMgQu)6eVvk}apiOxpKd7X`l!|f>>+SMU;Z`$7|aW8FrF;-6Dn~hS2{a(jP2KTZ& z|D!0P*Mt*>xcRG~c(wE)khLp$G%5M&l!w#RqPS?Hb+i%>P+|khyVv8#oRX?^v^&gU$QG_>= zTvhQB1AI!p>9_le@Kq(t8|hmtaQX(MmI@D}9J0VxR|!$}e3wfWjUdRp4i_hi!nZeo5` zX`48x6`xy&|NSWw1gh|xc(L(O>GILbb`de9q-6mf-kc4{mk32+jl z4}NA7qhaRZS7pKC_>{{Wy4efld6Qyj7-gZvHTgQWkVzFC;e~8>fV-eVIW0;8l5#Kn48C?!~ zT4+__e<9EEi>Ijj-eKhKP%mJDE{LR61(DGv7a+)(H>YC@k*HEDm-)c_>TSK$yUcJD z_OqAMmDpxEU2)Zqt}RxNF6wQK(}ydA5$}jIC+21V9FlSKkVR`4sYyQp&puCG(nxlc zzWGJg_nO)QRMbub8DqcD(P#+WtkV4u>LB7i1Ss0C-YGALY~xiukr>pdC8y`7wK3^I zkK#IFfybst9fOD!mqt(IE4{T}P3;))x$VlM<8!yh=dGjR1MVIK@Orb@_#N7ezr$)V zah(y-f-~`~^JE&o{Q~0_f`}K$lFwV2SNw~#+T|rKEH|QE6Hf;&=vn_|8T7d0`F~{8 zU*dCU507EI#J%Wc&Q9}1S_sCcMt#=|5jq083}1nkt;o1oH?{hyI2+LO1Cb{T2jbGM z3<0E5zUgJGK&?;!>QnY?$;dxHN{)H*lp_52OKvcxq=}_*yzHYYm!R61hYq#$4Dp|y z6`Hy4yVOHV_YfwDcO7Vv6U!^`Uhz3t5~)S)ThBa|Q=iE$=BU*sqRQ-FvtQISX}-6l z`94~%gLszmLf8bspFJ_F0GQM{xZkLQ0o8j4}l! zEmaECmV(r8GZOqe?7-SvJC+2uWh8i264-$i7fBZpgspOxu@?`#wd4Gc{z+Ytk^X)= zz2iVkN9oN+8Dp>dT1MjKl2}eN!O`MDk9P1de+3M^Rz{!SP&+|&+~urlp|d97S9>8C zs%JCO^tX`{NlIcC+#bJr5%_`J6_UWMB0b? zO8e*O(hgF$MUwVn(q7kB+Q(CA*Gk%{q@B@M+8a}8ACa_|koNSx(q5KIyGPPaBkd=8 z>FA{$&Q7KMSkg`>?el%5%}%AwWmjE0gS2<|mG-r1b~}ufv|-ZL^_BMFRNBWRZ3Stk z^p$pXD(z@VTS?mCeWk55)7H*ZT~PlNQ7YxN&>K1_S-G^95wG_0T@xfd_fM1rnUm{i zdeZyYiq2nBTcvKxfbyywBIr|frl`5&cBu1O+ScjqzlO53wpv}10p(_(P=WJO6~M>U z_jo6P2K)dL_7!AvhQ(=&}+te2qUm{DG5GE#c_G4LY2{4Me`F{RS?% z_TEALwVSXUi5P!^E+F4t_U0ib6*}nD&|zztX$fDH<^(OS0js`ynC##fJS^YWGdvUnE(c*$=7 zXf~Z*7~i`_qj4flbPi;LMbt0s?(bgL9K!tFw3NBz>UDCnomvZi*}g<&CCvSZ#HK-D zfORnbV|%#KTQ6L!XTpLx)~TN9uC!mt`_@jbVJbdXal9&{F>@2=jO@PnRaJvRkYag(!Q1VB;t=Os9R6=YPx4tDT&Hv$WgEeMTkRm^qwKNKzo-=bi|qQT!YO5e zi{<9uG}nRQbRL6$c#B!6gvr3b3Iq%6$ipH3qsrYmKYlH4*kx~>F4ELf<#ZBd_&`Kk zFH8ukh97lf4Tw$cGO7c{Wr0XD?2f7;L3#@QSiVjV7!!gF^wJ4|x{>PR#YFPEk)+Jm z0z0wxuvcp(t{`zb!E4o;fO{$cWx5*@8&fA`F(;F<4zo8G#U*U@u8^e;7A$YHo zEH&0iR?pzj-sA;BwDaFUZ2|soXCH)B%s8ACeo1SeEY3n7b@d`w^c*wWZ1}xy9QEzQ zf)jSWg+Y0i95|y2u!R%NZV&~(eys5fwf-BCpmM&4)^I^gxuPeJ{0uwuXn>8H=}B@U z`d@tCm}CBkys8_t7hdpho`B%++sls^1Mlm!f%kfT#AmNSZ_^=N+l=IodHLU5_i(wg zv$ExX$GrwsE6=eoWuj>-!!0zE``rfrwO4+aPO5fkm_dWW)L*HBUeWSiVrtj}zzQON> z{9eZOSDruS+QYSizh`l+J<0ZwiiTxWUe*PK4iNhkN%f&GNEHn zA)Y{dfrsFd@dbpK^u-tWj0TiHgGA*L&y!zNl)ox|nUM*sXGVy>kovWHb?7`^ zf?!_gtB9=pwP{;ASARgK*Q-7}NSZDQSg5&?*&>_2H9#4;TrRF+E-#mJ%BS#aBe&pZ zDr7duBJy>)4F{77L8VKVSfSp%Nl-DZLNziG&o)6atoG)Vuyv^-Ume zFDp7uaGYl0c##7~RceIM- zqzhm9x&c$703zNdbh0D)|=6Pe9=Ivi23n2@r zxpHnqx**G`x$180r~g`POdqkXwFUpC?y=dxGnd@4oFQ7vZb=KF%KblRnV*>C>eqJb zJ;1!5YZKQmxgO_g;d15V5g?^n8xB-bHJUALq0FMbr_Uy_>K z@R$9t5QAPC>t7tN9?@_jUPjG!tBj16PR0paXS42p>54``bRTft=HqDQBeE5A;Eq0b zV%D^*f4SS7)cvV@%4~huYqTvW)|+Z_v2pR#iU@rP6(of@e*ekq|Z`cZGx-SA|oP$#v6zIXOF&XJk znn)gbwaLgOm~#C4VscfFX#A_cQhoD4Duej2T||c0_#E37E@^p2dQG2$_cP;@EHf{Ow z2aZW&Z@F=_zWj6u>G%YTX@F(A^Tdr3Y_W6b##!%9adrAOdgW!##=|gerpZASwgTc! zcQjBL4@DL%F*%Tkg1P?hUxvtcUD=3`f2=op%-8|Z0b>VlCyJS?K1Y5;@Ba>zOJXgI z!T$c6nwjum5C(&E1tN!;ELB)4ga}>y+(ptBdZ!K6ie&)3IKuN4f8!!o$8?5jANg*} z%!jjrbUwQl*GL+gf(A*oUSz+c@M)PqRtpeXLL432Fh=Mk!H%b(YuL;YA8t|~z+9QY z&gli%pUS1Ox_i70_$y?KD~KOz0=tkHH7aRO$xOzNb( zHaqe(kcii`Kz5@NbbYd;>7B?nXO^--EKkOFL-ul=M%tc;tk9U8%?*g?b#%v6Y)60d z9wwxtkVkY?CNWaODqpaShC+_fI*o$-Pn7qou&M)vU`T&b)=LN7<$&~>BuJ0>{(`O- z7pC+f zNH5jkW`#ym-WeKPe#Zt`Tf5I(6YcEG5=(&71MNRglID@R>t^&fEzX3u-%*3db=njq z_!}~;?oD}%39chQ6H5LFb9In0yCf6JPl1w2=%-pR-hf&;YPQg-yin+ZOc<96Cf$f+ zjwI>cA0a5XP1oL@C^b*j<~U&VBm-L{QFkcj3^dn@pJhUMk);?Y{W6KkcXgs*$3SXy zYt4;iu8X+BT=Th}=W^dv=DL~d;k9M1|5{h(y4@&qedYUQu5WX}7u41g8}Z{cu=`6= zhjUe`wffM-Cq;cXd|r*K+x5)+CnZDg5e&|`n0N18j)+%2r_7Nb>bx?Ch20MZba?1>R7({pV-Z;uxc}n&+BFu zRjMH2=W3T4`&H)+&g>)k?%yzRWbJpbf_(2;%WQuVx}7wwZ_rVIpd1thc4HL<8V83EH~UQyc9NlLP&# z&3>iM&nWCV3Zoq6TM!M+IY83Me;~=Vd;bbyYihrzvdP8)To|ROnqM4Db`+CT=Zc=G zb6g=g0x(^{aP4(?NX=7w8dEvWAcsyh)YdYrH6Ve)Z_Mnk8`)oHx7tJKXIY4$kM zeEhN0&{tdEaT|Px&h{5x`JbTH4XQdL-yP)BLol!B(z$ZBlq*Z;ndmvHp9?$XUz``_>H1<1I$Ci&C^fwO&8G%!!aVZx^w*XqM0kvMAYK~z5 z(m0Ql^2}zgT|q%T2$241tc>vVCI zX+RIzfHq4i85e3aU(>DMFiN+6NpiDS#>;AT9G^{LcUF~}&DYxNRh9s3&(bk^^*9}` zbB)$0E&{Uu2~TmP5dbn`)XOl7tdP0saUT#ktJNkxn6R^})Zud|87J=BM#nx2tZeT1 zqdi`SrcjNOK8@=0k|8x-e`zOwTOzBPqffWcbsbY7ZyL3oe5$QumW{Uoc{;zPzdS0L ziX%4wM4fJb)K$C6EJde^lS;-_WR0Xdw91LiI7hn6&2;@DF-iAIM!Mt7bPH;0)suWk zRsTq_)FxMJh{&EV`8FGYV{a~V{fplkeqCIHZ$U=LwVJEnt!1vmT(ABYvOlK#7%rzg zhInS$qDDkU#RPD(#TJ(D&gqVDVW#nkp6}z3Mj}?s#R_gp zaAu+m#WXehL0PMOA}8_RxER(J25B4NB-vE^Z~BnRLyGqQfVG0=Lq9|Uxz?!r%uH;E zFKshFoMV1?x5tNE^TRn0>0%r?#AqB)YkPcn$Nccm9v^m@A8vG%p^^HX`Tm-pN)c$2 zrI5PI{E)LgUA71X>Q5@seBdfR$H&B1c;YL(@fE)K3LVU>jSVpDISX91xQ+7}JL+>b z3G*y6Kvvqcx&FcB;@t^cqqr{Sa*hYVKzyyEJByGYENa^3#~QD}JoG zh~4T|3FbPUm>zn{tdYNvUy4}FNY;?ZzLs@+zKXx?GE(wFiSNZgzw6ypSz{@y_ztVA zkU&S)7BBa7PSoWMkvHOdHtgv&lA4>XyHgM9->l6B5; zYn4xtrhHNBU1@=K8@T#h z+3?ngfrsvV{Jr@Kx3+d=iwazG(%FyTx-WE?&pkEJ{cer;5|`{lztt?F;C$uJ><(zGU$*ym;OPImccMcM^Eo= zFWupf4VD$Y^(AHJeu<&8lcBTY^E20pg6IivGfQ{4Urgl1-TU18W~xHj|5P!EJ(bnr z_+(Uzz2S=X$%m!W)S-WndYTuesG>Si^+sh4DSWD)B~-FZ^D(z8kzymnW;9iY$y*Ut z+a;5hk1=d$rQXgG-NY(oiI!1y)g*INO%5b{TikmS!L@PD536NB8Ph(tbnIaYjK9y5 z;We4y7^BQAwQM!ibLHR<*_r1xUh1WlOWWhq0(A`_DRU-1*$d*8)eMh{nd&4#bUL*Q zCMLfT?lpU1R}I!?GzZ=3Qe#D!FxhL3&1r8`=%M+}U-i)J1=+;dE$*bz>P{B6+a*`f zKo7hFm}!K6r;c9T-jy>|_;2t4py57LGgIBJK^6ltWo2O1-zMey*CtgpdYnO|yf%^Y zmA2Ovbf+8CmB|sPG%KZ!MUV%x;f0VzOJp|g&}6Li)4DSf!6!@ia4@o?Q09MPY(hpu zO}J8Be1UY9&)p8@I&TI(dIpJQUwYiX)MMNW`-(}=xu28D#&z#ZIzU~BBo^zXTo+M~ zOKXhPUgHmiJwcc5tve~<`3b|Zv>mSo;>a#sQ==Y0BOC&#Q5F~}oFN8J^&keOKMul@ zm9*4oPa6|F@d@5I4ElRPc<9GvN#uCK3oD!w5nEVXF+=_Xm5FP`9n_c~ z>d_xtg-uV9agEPN{D84S=ML4z0?FI9@n^hQUK%@$ntUS*_blFU=ZV@|b1o1Na>$)dp3Q-kW)Z9cyl3?dDt^^{8Y08)`;Mu*^|3x{m$+ zqI_fJO~$7btEZ*ot+SnzfCG;+>E~rMuTR~3D`qS+iV>r#1I)ZIbqlMff1vBqQ6fZ^ zL@U#YULp}q60T4`HY?n5td*!Ho#+us1g~1D9=9NMNVS19DxK)2RB^kkMAAZ%=$Le( zD^kUES&8np5~*8Kh>uGZ=QeTbTt$_rQ7Bc!!CRz8-cB4V`_!+}S+l#t@4Rr`l%lcy zqUWJJh_nnFL)k&?sn2=R+B(rZzuHGbv2*fOTKlF7_3+g)aPm4m+oz0l8B>}1Y;TGa z)qRf8OTWShorwwG3+^hQ`Kmte4$j|BWL1V*rYM65BDD#RBb+%CX^L?m5Fs)-Elv=t4Sxf!Em^}Zh`Zheb;{%(PapLu{n|;2nM|qz^?N1< z+N3c-EMCy@m}H$S-D^vLGdEDoTyml3(7csul(cln_)HbFrJUneW544NY9a7qhqC=^ zR?7oo=&V?0mRa%~p@n0l0^(YJn4nK&W=u($$07C1TYQBV*LmV7QQFyX1C}(t?IUMD zO}%s$WJcd7Lwu>PL&6VqtHC6&O5s$0fms7hCI>*7i!@(cN(0o16D6@?p=FBHQ?j5_ z*?7^Nb^~?%7r@iC9pAmS%lI5Sl;vM@t2|`X_S^7qg0@&u6&qPqZ2n}cWOS)l-URU# zzK*X6?4$#&cGz_bEoK7YWHnkLL5sl?FSKk8KL3yFrwhiVU7KUl%V#`PnRW?k_b8%X|& zuNtAsc$S?VtPG%%;n{-vx@jX?Iy{YkaW{UNT|Z&nuQg8D_pXhO5-ra~`hq`_Nsvhx){W@0|LToHLrAdv0 zeAHhiZf}A*;S5@1s_8r*{=xLB;xHL7c2ueV{vH!)qPOpYt7x<4?~(|hx}SHe2VXgo z)V*5T&KRwdFx>7`?Yy7!Ii45tJm^8#nUvNST3|Ws5)#lIm;G{;d{X;mtnzq)ob619HJjFO%7UTLdVTSbV4 z$2Jje;c;edd9dBpM7zYxixc6z_`vwZp7_Py_{F~X#ab=W)YdZbH70}{*uL<>Vq-$V zVurSRR7>09arjXEWbwGqk{DWAsr*k&K$$-)l_w>CJN+fdC;EEq$l_%o<>Alnx_46I zx(P*NkBjyn8;rU|ho5>lTg&2qoV)PM7QTU1bfL!hags2XQKQzgj_J=0$@Q231r{xcAH2%c=ZS(>Y5&WSwTyd7G^LD1Yr(+@D&5p9}_s%7~COxJR4{TYoGe@236ygWBH(%GK($y@vxU6q87R^R3z z^wQMO&=^x5d)wk>{0zvDj1ErB@TjvAhmtkw0)5=-fr|~d_Y0zfrC!k3dYo1&#Qzl5 z6^FF1s}`|tLI%%74@l$5x~y$Z3nWC<6j?1SPdGvg1D4sh#I0qS+bl!v{O`zG=X5vm z^c<5yBz4fJTN_ElLBl!5@xn5sVpNgOF-O;0d0IFSoEoeU7loG?IusWj(=$AmGH{Wh z4fJqWYx?r-%L7ZU!w|n=kOsa>4Ol8%jMHkEKWtYxpX=Opi1^`w`?>u-pzKg@%;E>X zmMAQ2=a^rl0kU+M%~-nMzvd}fC^8y3B(2*-^J)JCvXL4pM;AD9Oc5{|)yWH7eVN&) z2h1b9v!rKstE^X8oLfFayWD@1Y$w>d-t!oHfd-B({7u=CNFQ6|vmNXG*dpj}zLO3r zIneP#eyof#>CKEi&O1!;B_i)&JygH*N-M{Y`_5sS1;|QUKZ+dZ=p4~+em;B;sqyjS zH9ly5KYG5g3Z58Wnp1O;ZPW#ivX49bDC>*%3T3!N5R-0Rn%UTI_fSZ>rjf2;_15Ps z-i{%-i#3v0Jjx!D>snfJ7r#j^C&6Gn9p7U;wf2Kdst?t-o(GIRzbMMw66(z$%Pzlp zT=~K|u`wL0eROjSCMR3(O8iG2$!e1I(vAR##H zcy@LUfX)<|0>!EAAQd(TKOG>a$Bqv8g5&+4!@gW|KOy=2 zGDU>G#C>ayIwpTH>pvgwU;E`3Ywl?_>@U#VKiAETQc_57kS}2?9jr)952+PW9lej6 zMSXHjhhra(5Kc!<@(Q4lrEPkT^M>^@bC1)FK3>^7ee`cw5*ll~?%zCdWT~pI5fbQc z8t$RrrWUi8`vwx+ttaX-nX_nq!Ii+iz+xUJ8@4D1O7aH2h}~Ur=Xu)iQ|iwGqHH01 ze}jGKp7=~wPYllLyz%RNu~tu2d}2T~$w7`#-KhvK)OLwuHr0!-Pa_=EoJ{F!DGC)< zpH!MXMr5#%tafJ7^OpwM9Cjd4$nDIt=z~>n4sguJf&X zZp04%=9a{yFh@SrinKF{$Q_LB0foHvNyFk`5mW0p)uhS9lEH zDI))sO7&bDN_R<(MDf2!`J_f9Lfn;?6(21VGT*;BJklNZ#oo_KOiso=$clA(O1JuN zs$l5I5a@VE*R^h>yUurDZ)yEPgxN#=u~)4Ypz2i8-9m*q4dg^zhGS=cW_!N)-|wTo z*7?ed>L)`o>nrt{VAi+v**cN@A$O}%QAvgj&bZKnH|{*c_e39+rNI2s7t>uh{2{Bt zG6$YhE*$;}I*KgZVML-kQ>itpkOMtyt&s-L@6 zg7XM|$}m~t=c{rmEh|1zgEhDHCVgIIg$#BuE8XOGYP#7X?;ERd32(Gpaw@`*8c9bW zQpQOjTAG=lTm0wcd5+Ju-f-;MyejpJLaD2-v$TD39{9M#)8I{V7?$4sY~!!EerHsn zcVZv8jNx1hC+_jd`BojY4-Ij19uj|Fr!xZP3B!ZFm#Bv|l(C;1rd>^BR@SNSb!eJJ z`-Ircw)`NNaJvL<*RrRz`kmDadjH!()1zpEe~DwYIVmQoyVVseH%`fjnF0R!x*qET z3U0W~|5R-aQv3a^I?yz4%DQCjaYE}KUgQ6N@>~?pliAfspC6P6J|BNBKKCwULr+Kg5yAXz zs2Ke;&7R&aeFnX9QUU4sK086u~)uRj-h~R9* zd0nUoeuww5Z6WPYBjRem$Q60@Wv$7Ss~QTyc2dYE?FV%zAeWE7N6TAy-Z-@?WH+)4Y^w1F&#&F}equc%b+sgfT*D)ZcJb7Vv?e>V1*&$0LN7!EXX z$kMyZm!@X38xR(0jIk;wyCi#6o^*b0U*==y4xZ|G4SXWaq5fevz^Eo8QZu3u`@*(e|4*c~i`rBKys6 z2eoL>01+zu*GiXT{eH!b^VYq+lzeys4A#J*=4QUheDCY7Q zE@S**V}{qX$*fSvo+XumK2x1MM@_tr4B^9YigS+)l#0etjeVhP)kCCK`YX}{2uOKsY-F{=|QxprPT z1hPth_d*~AeEkC&9z9?7?h7X?^LddkbifrYp_mh8`Wu5QBQ3yHTR7(qtJk@MGG9UvEbX{TFF%Bn!1R+8Av4daFN zVPB8+LHNBq_`R10(yu-EJv^!HR- zdtim$+M`(^pZeBm0QQ6ga>5sa9MD0+1i46Mz0h1hjC7e3Uf0Uh56<7${YdqO_i}SY znWp&-MrU;*ahOpRpS%|hf)8ur)81>J{MHVNiBEpxzDHQS+jG`)he2k0nw@w?^28_a zm-B$dM%8{}@>`f#EshUM%$o37>A(DIenVEHYH#6(FMY;pGA;mdMavjUoOs`Ze741W zGx@F6{V7Mj0>RC?=?)!M20Gh`ymQf3zUn=ref3b|g~At&L+b)-(ZRtB0&KuXI<=jC z4(W}_D&hN`v|E`hhC{!NbY>^J$&tWB+vuPYz+^_rBu9vKbF8AMZHxK?T!Fk2>V(Cl%W?Ad~TYU2( zyDtLeRsV;!w}FqUx)#1?GLtaCBr`yOph2SGXVjtrn=pV0WCDo6fk;BsfLftxYHux^ zgU}KfJV~3$VU&BX?XCCehcvd=R-aq%ty0=rNf=CmQsu*16sl3Fo;avMX%ZxIp8wis z5`yi$&-1?T^XB(EnRE8X+G~HUz4qE`t-W~bX(=$!AWEryuf@tOv)l^o_Lgsdk$6;m zdp2i@t}hy*2iSne!pGw!{YL-Hz<0jj5!I@up8djS#5eGx-E5rxTA<;_Ly|8-Wq%Awb#|U-(R%mTJ7Vf7g~P*A!)krFHZvl0vmhYyB7}mA~&uENpdKV5w(^P6isc5_4t$J*LTLDzB>FCkZ|_rIM|dJYVO-`s$Ad?C#oBhL!(G@QPH1rSh>@(p)ZSO6BeMzb0&!yjA>` zx9O6UqsnF0v|Zfsv)9*sk%TNbW!^G?US}W`I8r5xEkE8ZJh(Z60o46hc?+Qb-<^~< zsz`K~ijG)izXA9GKCEqk=vGH;)byivKE&b|QFi7P#}~7|S!TWdKhDyqfyT$2ytSwJ zRWvMKzRjxNiP(t4#gz6vavVbWP$cWXaeXlF+ zx_pF)R(wXKx%{~2bZjEiH0)#AtueD0iOWBP90Yd1=1FY0M8@glHAQ}BoQ`9*sBxN_ zL!Uqs$-BIr3B(MDE$`{>BB(YfQznBqidL?fl9@{DA&H9}b`X2wKRrO?=QZsU&+WtK z+6!f_9)3UN@$x>FX9~~NJViWZJQX~5^3?I%&+{P9_jzodpYS}*vybO6&!2hTv7Uc>elm8FCI$0iPW(XT=ItdHZGmq z;Tnw^Mnw4e#(RkaP|Ht^v zqt0>(i5oreCH|r%!F8UP_|r@|E~RE-tK^Q2iqG1Ld!;HX9krw6IQM-k`-hd@ zDl-&1qm4%%cgyhnH-^rT|G%jJ1f?$^^&fLy{a31u_~7_3UyCo!vrzU%%bzaQzFcYE z=WFb((ymbQ3G*y!+nlRknJyhC(|AAqTxGR8y^X=+pUn!?7`^$6z1moFmU*zPn>#i> zdBS|bc+2z2F93>VWo)r`)!=oO^Zn90gGh9XzQg(LdHdgMPfjp=<~Mxt>O7@?k}WW- zH_0nDl2w0;}buuN)?2@Xo|C>QBM6_UMzbK{EPF0^1VwlhJ=$ z;2}}_GFtPxMc!6{X;sy31Q0F^8)pFVa$`>I?!_+mX2?;6HFZ8}Ow~#Mjynkp?DVcM zy4(<((a9QUP_K7|Te~$@)8AI#@3TIh2O^!#;eI^P^_DJmN3}p*T2t8HRFl~r&T_3t zjw)zvs`0mnGhM~pm8AE?%LlMdiNwSHNR_RhvX0ILt-X1G_nL|11W|9x2BpL0PkDy1oIK)y=<#lrpCg_Twns6}kO z-@Z<}d`U*BR>7iRhf!e7N+nwKEQvAq$i*w{^=1T3A4| zNYaEklELi_E%mSCh|_0!w~O72koUrpY%P0-qzOeNvUo6(1!hM!!QgaBC8ww87q!T@ zbql3dTF05=srYKWYh}WiBaw{sllth|e+3ci4;f%khlwSu2yMny6q%AF=Hud9DP2Kh z+&9a(p9n+0l+0Bzy{98%JENB~kHPlLWl-E=`gf_e_`|sK+o{pMzsp|lvnEcI;#^4D zxST3yF-KzMr#dnUZ(rydvWDB25L#Psv}k2y{X}E)ts?0uD~1S`6=V3BgJ16IY8Jrw zk`>mUZaR(kXnU0JM*dx?Y1VPEaTGFzAAI2CUy%eI=>S%W`tQgmb=-LdPC!25u) zCacfMDy+=_Y7KlNMIx5uSv|bRH_zsf^<8=6KIa#$W4wu+ygfYNu?iMRB}H3JkC3h2 zhqq{3mjm!g#L!L9rd@&#`e)WMl880oFnXr&cvtXPEqJJb)7Z-R(C?_5VP#_+SZ#K~ zuU)JU&|9M_9mBRB`n%UCA7I>YaAr$Y%YslU7u)XRQ=wqiEvN0+%v^?tP?&yuowpcE z&K(laGEG9yYYWxt>uGh!bf%gKkB?z%&O{Pnq&R@s;U*f1bBFg2k-CzKga z>TD22IgESIDZpJj>*oZ-4vnDRp>wxMp0OrZhP{dzfKI1kj5T?TB`F*v(MHH9W^k<^ zd$vh)@Q&`17uOcJHyo9k?|-kZGCki&5W<_3lNPP z8xj9<<7hAu=aJF%hvB2^9|S~dboEOwyotatHM*=XWWk~9KDAsd83ev^$=?}C0$0}8 zp;0^G9NZ4~lOWYyNwK>oAESs(6tVS06Ul|*cTL2u5vA&>oq>jjWiTHttnq6jDk{3S z3cxn6c1`VZ8O|(Ldnh|rGayS9`wt6$i*`qNzksjps*@#be{xA(+U*T5Y7=Vrr}8{V zp22zFUi-9!#_uJgr4tcvlvjW?0oD??2p!?3VepzFRu6QE(K0k`e6C%pp>}e%gOJIr z_c=tyx-HWo(ME@#nKam3Unn0M@e#W$$ zg`%S@8_LHO>^a<39NU~1+dR!;pJ~^5ty9R+LLJrGNYqyfnFvA#SE0+j(ph?7;$`)% z(gW5S7AbyNFhxGMLKt z>Q|mybki!Ve`m&iZqZF+3CLts)SYEFEqQWq+5HxY|DPtE&|UeQMCjKTnd&nh9*F!VN(4j8M}(D4=Gx}Xtzws$DCX(4Ih3QqFcDlsb2aGxL zJ8JDa(#K1UJeLq%`pM5={M0z^+-HP+-q`gJjr8V;O%uv&#Y04kF42Pp zhl-XD1RmZ~5?em-pO+-Bu`#zH)fiGWj|uGjw50btTgTk&@@fGU<7=MObP;8gl{6gE zt~crjT>7r)r+Hd>^wW|0zmt_4A8l8Gt?Ys<5NIAV6rE9$Jh>?Oj*9w&j4fFt&S7VJ zhDx@jIn|1GG?`X1KU#E$c3QBV)|+talaXEf;Gn0OZ^#I%iii7g zy>!?bE4vSUzzp}dy_@D~k635fpUM6kFAsXU(P<~Imh^G|T**R)w?vW_9;jYe-4X{F7q?Iki14egL!^RwHoG+A zZI5x-eoi8r|Nte!S;;Iytl3{%0lG+(z_vB%DF{eUz~MJUu*9 z4>o5sjo{d_X@R@BEDf+t3)19}sY3zZKLnh;_)uDvii6HHqa#gF_}NgZ?M@n`)`B1k zO2jq|#R6j;2;9lDf+xbWkf)fZkY_rNS^D7dSm{H@`L+1vRP4bM{GQ;K+ZP||;rA53 zr}*vXx1Zkueh1=Sk^Qnm)I^f9{%psJ{1Cv=d}pU zF_<>4T{jTlR5Xz4gK6jbAoH_NemX$8IbD=u_q|3-cfMIB=d*)-a@y&WeCd;1qDUc$ zw_nYBgl7X!bD3xA!KMWsRM-UcN2>Mya~NpBEtTe6UwueQ)eB9-Qf?oXjv7$IRG)q5 zF+P%>4Ll$`z_1*^-VYA1@Eqeg&U1q26wd%pKx$U{U@mRVLDPdd{GxmJAf}QJVLtm{ zkY5g$9>n#*L+JcH=;IeVBeH^Xn|pUp}wi@uzsL! zq;bN|>$?tjt}GafMC3DKsr5E=y;`wZn6{r=ZP+^vt~TAfNg|ZH0z+7%)eq}_j|ur_ zK6~zIQNLmQi1^Jf4RD%hcip}ZL$wvv-|?mU~RxrN9yB10CUh&s*Xzi921{ zIKr)2FCqjM8{1;9(e)YLQP2gs$7DA|Xw5(@bWcnbCL{pBKr~K>2Xkbu0|l*-2;0vA zME1507Y{_AHDLkMdv6}mWPzmM03|WNK2X%VLYW%dZEiYeTWBowqEA(fW2lIIU$%`O zMi=X9o_$|Xeyo>~Qv$}}OJ-DTt@llZwCH1Z-S9R&0hVqucRvc2#_A(11IO+re20LK zg}cmf4kBSH#hHQ`&c*kQ83v;sWA!PL_d7e|)u&=#>vwbuI2A*_;j|_UqO2%%Z!CNO zzb&!wEAj9FaS~%sx5rzM#p-Hf^?p_*)`f{fU18Q7iFs0Oh0VYqG&8(EMdK@=#x$}o zl&;!fA^@eyJ8?*Zn+`l<6n8f`<*J@o!{QY7cN9+(WQa`Gu`3Vz?fY`n|7`VN+6-$X z36@Qi^{)s@Xfy(h4bxouXu{|fi@UYd223_#2;3q3wbGc@qpT9f-dyP<89%w^SM%&H z%1U8u)calZw9xqb{pPBm*)H2g-M6XGILj(xZ7ipm%7aVd-kou;QMAxopB`H1+ng@3 zerYdyNo5c~^)E^><=JJi>&)_;m^-wvp(Ir9xynR-?mm^5R@r` zgOXU9y1)TRK@~y4NZr|54FLDpY6_<`Ux>*wSBPgf8e6+IgvV^{iujE6rvFzW#T2gu zn||dLk&K*Mnx((;S;Z7(-})#Ke)4+G0%qxwi1qW! zU9Muhw#Z%>5dm9sqy}G%SSJ@lC#zxY)_7g35XuX>=XOQ{DFtT%!VVZO1kKttfSiiN z+5!0&1o?v?C)oERw*R36bELpbdMHZ74^-0F2$F8WN*if^0}Dr5u{z;gK9j!dW`#T_ z9=-@$hZ`W~9U1pX4OHI2{o9()g?G3mP4^ChWykTz@HN20nbF{mgSdmkAr;4Y z3}WUgv8(?lYF}AlzJ`WMc3->jS+qb{$< zv>RySj|z`zmp2^O-fOdh1dS)?7(p2Xy^{Ri%2f`|^Ujhl5uf*&^D`hn%0FBc-CiDi z=W_ZUYTZ}R`tiT_z27TEWvYw1RJTHisljh<9QsuBsc&-%$C zhDuKyCuONc{GFSm;eF`vT3NiJUMcFyHHjUqQ$-+KS(m+%yH8}7oy-We*N-sUTO_8A z>GNUGnNTgeWHWP7owqVJQ{t>Yo)?i`cfkrAK_2?ebfGNiJ0x|?pJue>N!y)%>bb?P zP45$3Of)w+^{2C|y)%d)?qlQKDWL*DkQjk8kjy zjnYn4GbIa>$_4;dBdb%=gFBEO)MeM+$2_(kxRspjGVSu%P9)AjN?KFRf$kHmvxy_tWkg5rH?s}S({Jo6LrDb?E-%< z)e_Ngm#o^tJ{=E*gZ1NRG92J6&-Unk7Jr+g_P?OgbAAbu6-{}gzDt#mqX@lX2j7Cn zfWJk2#a{RtV@@f3=&97lTPv5VaZ;&`idgl$S0kB(otaro0(*QeE5u4!1D}h~t(BGw zuF~v>yyiq;4|6K5667_k6-TUpQ2Zw9zvy|1cpX2ra+xMq3V8~SiW`?%YkrOyJeQOD zs?53h{f+kK%c~;x`rzP|7x>o*kfWh>V*myinRs%9vBaNeyoiEjnNL=MScU?gs)atX z(z=>v6-lZkN40XcAbaYSiQclzVgw+-zVa>-$ky3$c1lGGdJB%S$5(Se9#cwxwxV5la+yBuY;k-Cq_`z&8C# zWi%67nheR?6C9>*BUyE#_DQ&!@cl0ys zNIAlZsjjU0&GhI^uHB{l!}Q^0^W?gTOt~A)EH*D`_CY9jsBi5D1YKR5y97yXnqSVU zNNu+7zM3CIjq3tt1|ZXrL#fm!5jZMoV`V{aS<%ed%+V^@JNWGJ)4>7suI5KL#%6f$ znT5pvL?*Jn%*=cW8bQfd?s$?H+`fd`k`qip80bS`>5{5NQmlJt*FunZ?pDF1-RuVy zVJ8HY4lllMPwrYF(Rcn=(MEj`E=3;;avkY{sEm2*-x$y}j8wHq$xM?=O zb@5<;Thdr#&wUbLc~YN)6G0}1J}xwKI-~yn(UsQax2aj7Pepj@E^|`3H5ToF@oot|uuT9guT{zsOBduQmnUSbZC}J^#JCd-)2o)vl4b~ca<^WY7*k?UY(&}m@ z4qR%?@nu0KMQ&SJ6=?Xm5RN%B_P_&aBaJg#0^b%(`hs3{l3K=5>Lo=p&wyXK(3EgGZ(VO*NmjhtG0kIb3>3IU`Os7J_PlXXsYxVyJHByJbs!nnU{P{X5 zfpn@~`|}3tb?Kl~`fn?CmsISV@%dd+F{S=vP65TC~1=)-= z?%UBruW!l-b=IeuZI$+n#$vvoD`wDCTCrm3X?R&@9aUE-%C-&KD8t8JgAo7vx0 ztNR!~OF@6W4yCF3Eb^d|G<%^IpwkEmxo`o%GB~>wajE8-0=L0#5aO>;=^NRlSkZG0t`U$!t{CgOB?( zfA3zeKBA*6N1cZ-_p@bfnhvt!S;)^qf@jP{W?M4zymoX5G?F9Hp};e6;FtA5j09hf z)%U~B=p%5h_XG_JGnKujugvdvqcl)P6$g@XV(x;^!%qfo)|@yzm5ZX&)KI5+8dI45 zD*J{CtM&qy>&klHm7BfpxnSaX)2#1LE)JCsti4t`*=*BB798qBg58$CCsH9;9|vnv z0_g_f{YtJ3qY` z_9v6F$R|HkA~L$8;#@`PD{5-KsVe&7->)cI&8nj4i*0>Nww>CQPBkwH9Wl>1)nrY( z!P+v3il%Cr|E9a%mz)=>8CW}ybqsQUGv{$apzl?cJ|mSj6I2_w(y}B{?Xgv=+EV3Z z@O$}3LLF-tNn>3J(t+n(l@aT&utL%R)!L;pw90Z8i$3wd7QqqBaOfOp#3js7L(m8? z-qHp=(guve&8b<=dH^K{B+OZu7r7@pf&o|l*4Z$D=0XW*gq`(e;zpe ze!|>Sa7f}UCmw3zvln?`fXA?}@;0T}?!eC0#8S2NECN@So;A|$5xqV+TQUoQTPdZ-b`M&3h9=XHJGEA9Qwz%CnW7( z%uxj|s=cY&lNP)@v>nyD%$o*)KlS>gHmR*U$g7{%v}EVd4%69Ss{aH0PwdL7T;OUs z#ahsj-p~J6mo4CJfVWVEytxu^11ikR+r@;n_;^WJ35J}tbQNP0F2&WN(KNW``f#Po zb@c7?+Jh-rsYJ<0lOqvxxnIr@(njHCoBem-3GcMzN%kNtV}xT}*PNlE+TDQ`@3eIv zB0<`l=jcwsWixB6P2*+r>c>jzg;~y9e`Xa~6WQ47KgPT#Izzb`f zMHW(8WxQ-ZUaWZfRWLGA(~XH54_fPbV?gCn!~p(GhD52}ON_ z?V+*85C5oyllD#C4I|A_ft~J>*r>!ZtB6@$ov?m#r!3_9XovcW`es75H^RKB$C@O~ zw>OxmD<;Sn2zeyfPr`Jl2N4qUQ)hB^aPbF389bIE%}X$jbZ5II?NkAFX7vJ01(ijYJH;79vp=5-e6!Fl~9246${=Xz{J6} zzbWRxhvSUlg-y!hst3^YS~_UT{-^Iq^}!JS&WePQ=Tev{c3pT> z$!Xmsh>H{xp9=@3E=AXvwH+BQx(YJu&=s=p^CFC=k*xV&avEqj{bD?c&>BW)pZ)Q_ zGh+H)oq`e0pG z!J!p>CvlAGTjv4Sz%QwUC`vWex-Jm$sTQq zcf%+&=4A|LCDAm~5Gz#6!h|ev!R%35I!X1{+DE|pv*6YwLiIi!Wj9tCApm;TjtyY{ z8~In4hUVoa`I3Ki;~QIV(*iKV+6d!f*E0J+HHQ#LT+Pf!pI?l{G5;!yB3>NJ%~-?< zSbWAa5)^7*`+nTNDDID|ueO!z(j}3M66sM{&kfrfXn2OPXV^FleUcX;BxlpK+l;g0 zwdKay3EF+e*?{&{xJpn_Q%cA?d+Mm0dq^LPf)XAk!taI1ibq2}*_=U2eMd@=|i^MEhqE#3lW@^R8 zhZ)*6OY~dK%qYRJIr2Zb$R1xv@|II@wV&h3I5fzV=8Dac|H&z4W`p{Y|H(0CrZjA9 zj{Fzy%MVxgVyYc{X2-&X+6taBmIti__o>=!dArK6GPIn9nopSLQ&Q=fg2gU{N`X03 z3fiSgyUd&^~Btv+))2P`wC&|UJ+I1BGBdq}pgBcMofsZs?;0-@8w z%Z?Ua)~jD;PA+7FXIv`(U7^!@DK?ic-w^gd)Zc>*fSo+%KRJ+HDe&8o6rrC1TqQ0_Rx_Qh1uNVLMf z7DZ>{DH*(-B@t|Jfldtv~A#H9!40U9ZQq#{!lglw7BD8wk4f&&ApF-Tx; z78)T0=At4+V6+L9))-Xzpw-#}C|2OxxlDxQOtT|7OM$5TTxOQAi;L0+=zk$iuX36s zSvi{OTK{sT)y_8)T9E`Hm1c>U>Q=>P7o%nP+im2EUtL_#+uZQQo8MmKYD#Nvxb_}- z`Sy0A%H|noJ)7QXPZO~)|8b8LU+aFPZqzFC&Av0gnr?nncTZZPDI@K0S<{5}GB*i) zkMwFkSo1e9vWYN1677-Jal8(}GE1@_sqQ-+U*b0RJkn>cBEnsg zcDQLwdx?8gJGZColKNmcqDYVso4Kxf*)LtsP_gd$GX0)0Cwj``+Pq@UmeB)S>X+uH zKh7{@%Ms@W6RV08#+)Y!VF~OBG@NEARa!rWO4Fj;vcTt#r-)_qqtah45PPaS%JP8k z>V82bAA24U?TSikr2_!#+Kl{k$v;$TDksx{c}!#qnTopE)sL93^_^)v6q`^#!gDY- z;mUHEG%Cbne{x!cbMLJuV&aFtXAZND`5O3TL)Y@Z*5TII{z5ow6vzS;XIAVR1kW`WbD#=#} zVB#tzu6Vd9QqlB7A!?2W7t#64iZ`Uo0EyVov@(>eW7UG-@DZ}& z9GvefI9xozCZ)l88AhC=H&q1v&sV%5<0)Vnd#BCG1(*}Hen!N4jL6@7g+ZR*iP}NK zV4goPKF@EB~d7IUtVd zPuJ%p-&)g`zKIhazk9dX1L~O-bzT<2(k}_rpwpa{RHHV?$f~k#dWXBTt##Z)ME$x? zb6ckDr|)1<$v4;K+!LBf!y&k?v^KpVNxa5cmo^>oaKzdMo}=Yrr}=qvre8n5l3n2Z zX#|X|un#0N&H1?zq?{@f`wMe^wiSF6iOFH}Hm~_jpSf04mY6Ya`nRBq@J9~xhT>$)oL-2ZiD0#eq<H%Ru5QNsN1IuJNYWln2DYobr^|rb7x#mIR?KExV zRwREM+}=MDvF%kw;eqv+66o!0yMg@^iH_i(9^=vC38X|X~% zBlGmt5P)sfVCZz=@DTsO?+o8r7YqL?J8L<$Ik(}yG8HTuMX{@5w|QgV^u^ZtV|NEl z@3h#w?2dVPGI~1ZO#`9S%}B9%IqZV;ksb4dPqLFC*}RU%_(TLfv3b)L!EP4wlAFAk zkRUIMw23f4_z{VJ^9tj1#`^T%WB~0G%(L=w!cKNapX1jAA_?|YI@%Q#+L&h1+(0*= zD5Y=lkvT%CQ>2tBIM;GiDJ+blNp>;n139qcqD&!NxvjsGZA7js{e+)ud6Pt*D6p&3-X`+k5_h6K>k2g-_8OM8G zYkduWFmG~j`sTgL#g+1j${3mbMt9?(jTgO^JI(Y@+bY-0Mz^-fIFxC9>$Gg+kSlq0 zD%J@<;)K8MN{Vr2cHbT~YInVc(`0#+{6M<9s-m)ajA+}?3SV#jhMRgUH~Wamrpwyh zg$J~W^hc)BtKnl5E}}kJc{?6&5>8N$-W}g;H{X>;k6j@_X@y<-bIm0la^*CyLB)Xp z?aky9Fw(cLYTnab{%6dX7TA0w%ntdl_Ie`Z`s3x&(YQy1|CjHHSIW22<(PMckkynf z$B@Wmj!5j+W#OW0FCxW8*TbeOl8`H1d|SIE>Kggi=ysBwz?Ob*quYGT6!paj0#f0j z@Q!2czJ+o`fHQXq3x)6%_V@@?8(C>xPHhj%jCFSbHi>))1di*K$*Kp&#Y8ao4GE}NZmm41P`*5z7@%Trahn!4m{)ryvY zTm67l33u1nTJNj7&^iQZsisL}doMctRvN;+md8Qb`ljbJf(BCgtS2Rvm4|py1&p-* zhXin>ze)h(tR>W;;hmyULU-hnxh0Q(5qqX6?AtSg0`9B-EM5>0fX4JAMfJz^3=SIJ zLKyoM{w4F#KB4bM#>%^JAJK{8h6uCi2)#=wh>&=?Bwoxvp|@sxeD!|oo$Exr{WQ>- zMgi$&`+#inL~j+b|9SFUM!mPM4X(tcO>1`ip=nE;0R1CaK3I>(6!}d3nC|mvSlbW{ zD-jxYJu_mOL&L@?8ius`5AhOpXqn%JmD*V;PrZFM^fr)sQ)8T&@&C$R;pzZm^6%Iy z6lX0E-T2u=i@icCpW7q++r;xI&yWqme`l{Cz>#MUrA_I+f6iV(QvKKV3WG366y)*o zxOn=(p@+xf>Ec1h{r`f!f@%$0DqYGG;kk#0o!bA;_6nUrN^$HJHtEZE?8P+%dU+fi_L3MV-(R~)*d;XLLGTzJl_*U~r5_Pj{ zU56p=jqGSp2bjDIBB2*nRG{BeSvvsPuNB3a3VZyWP(G-KFE&$>B*#0VPNRQ=jte6R zf+V|&YO*(92-^rByr?io>z{uNW-UsQ8k&n0if zYC5K9_HjY;OA78@DU}TkdeDN7980AT5GPCT5?N8ATG>t6|-2{d#N-5btC zg}JB(7j(P$4Atib9{MFOww{YR`scHD%VJAyq-EpY8&kCzeXcfL=hp@gP^va6c(68I zdJcIb)^BlK%nH>}Vm0)ckFFH0AcRWi^{X&A$5yb0#lp`D z6E3p0LNbTKd4YzH!LXttUY;#l`qI@_KS^PLu=k)6uc$#mxYN`tQlsFQjDnw$6%*f7 zgT0Q9r|>ERvHD$=Y)@Z6KF0!^WH>pa;LuIdZk+G1VB#-js;wWhOuQphbIJM{?K(cm z^{|txBit%YM;ML5AUHA{0a@S^I7{zMUgb2LT&_#HJX?R(n&n_GL-j!48yEIY)sG=2 z*Pkw`LA|2N`rfM)n7qKrH(brr9`DqxsOE??^AYP_Noj@;&0V!V8mqah_uG6wKXYRy7mf|Li|Ds5jP@ayoXsbRl!9Cc!vlHFC%y3ZF) zc80(J(=E{OAovtbmidiG;;DgOr{5gFr>uO}dSO^`sPH3{>5RRypKe@6;#wCxiFN7- z`}&>^?=-QDu-@e>^a-N}fY%WqGxbV-3tE-Nn^}Im$qNnY*z{MdKH#zhygmLNhKkHr zVRDUnD?RX?zw!p&7KErp>Bn7NSo5KFc|814b8yyS?V`ZWg*IlQ$x*nVYRbi6HdqpR zVe`ku#f2+ma4<^0E$u5^eVi#qlU%MknMA}M3WU>W(T zGD0tGnG}C`iGW+vk>-j9b{3Y*n-_X{^GUP*m{Z`(%E=Z*LKl#G9A$W;h1??2fE|y* znliR!Xr!mXqerZ{uP|C-b0k9M=ojR36=!_O>){zIttosL9Ic+8d|TypGIgX2uq$3+ zU9fR=P#v2r*>OEsJ|Kdi8>!2_gd)y~T`t-*QRl0jeuUIFvU?Gkis(~X57U82Pngtd zn#t@!4(ceYI<{oGJJH<+mP4BvUSySm2;C%mc#Z)-mTlSSKVgch75@svGAZCZeHSUu5$Ah60=d5F)K}fN6zp&F;;~|)AB$0H||MXg4fpp zQUweDs{2u+XnQ}%S6bm;cLCmoy{vJ>UYP)gy|{J{6uzLpC#B>TeyG18FXONcU{AjF zZTTNMsP7|?LX_nT>dBKT5e)=Um$h#Y*@Tsg3ehc`&40j-SMBl;qttGvAUXKG5nhKQ zDz=P!QDN3Doqer-MZC<7S+JH@7l_2a6D489I)WDmQnY{PAwKDc?(gtptj54A`Bjn4 z#Ai=$o}!O2`is}y8$ENa_T>m<-IpvR&dtFY!ONp(R%xhbpmW|@oSaMqH)I<9!F976 zj$+n*=4!n_BGaP)MjrfSr$EBBsU(CaAoJxBC&WB1PG^5?exUV1BCqEwPTTMxjl0~?;>)S zRMwXi$m}}*%HK(vS}&DIMMWo)bEkyb1=g>|r|1pmjrX9ny&yhg3-;IX9|;t@V7a}s zm6su~eg~{!r*C>vRJi5bNFSllPUfWG?>RtiFO~eR9mn`zy$Zcu_^uypJ@F{0E81w5 zYv%F|1rJ;X1tbG>tEn!MK!98`c9WN7O&R=+}1m- zQD6;tqkg}Hdus)@t?#!!1{mQmB73c!bQUVDiQCQcJ69F_VWss1zGIB%?_t@YeYb5r z(MpS{_QiGTak^@0Jl-ik1<%Lv{TIH^3~xe%;_FT)3YlI6HLZx}u5WuM&Hj~iSv-6q zV*O~G(^mRu(~!XKi%F(pUg40rIAVS2kkd}F#$&(=Gzc5(B&~`yb`cbx{fv-Ed^$Gn zl~3>bI1V;h?CLTiu|{#38E<@={}F2}^>aAh#v>9;`Svpc)#{{kVygVWuN$Qru@Q9{ zarH(Lfnog-bWmtPJtELJp1PZjQfo8wF*?`ysU&f=$nv-2aROqEuMn`Sfmidpk}ed) z#3E=bbTHkFOLXkJ&+^}laAT#{jLSR6PII1=?BA96O?#8qm?{SYVJa-S0vC*pSHEN% z-y~@Vp)K?pzZW#p^{>M>D<$!G;|T)nX9R;t-Im(o*A~gTk&MXj66ZQdf1{6uKOov& zZ1itg`?0g~scf~yEI1MC56Xuy4oEMAuAx1GM;~h0qKeKGOt4Opj~3C2N5O%PR4vnz zOEUYPJLyvj`huzY%4u$=rLA;mpsD&SHo{arq8gCH@Z?2Xe=l7d1+M0|pOJU#)&0Vi zsZLtOsJyS>57tD%?Rm`^liRnR5O&_-hnVb4`GTXNPf&E(6bs)Q*e1rB#@TfC1H6Pj z(Wbz9`m3yKm`>H*qX=WD{9+lZ&2GINt_?19Ih}UQ+6ljo>ZtR%&?|M$CC>$zQQz-pf zx9*bx#-!IX`Fa&~ilT5=wU%Xvj~VU$t!D>Fz4_35MP4hcci9RkC5dW%qyTPw4Tz?G zj2dp4iVc^=DPJ1OaKe|hm(H*Jm?(HmXbs0I8FG!`>R3VMt5(ziWkF{~?^G{F< zsGFXCakwifC`+76dbWuf943sNnW+nl~r3aviuI?t_VE+}QYpuPLY2X^4$t6|nPtzrV zaAIbCFr;T|_h4zfIX!g0cT>8xg)`IKUB1@X4# z_F6GA2(08Jq>t8G>Mfh+6m%(5@1o4)zX*qC!S1-E#B^&S*??uO2D5}pcHEew5Z|0( zXUdE4jaLZrBLsQnTjfG?VXos}VT=^86q9-D#B;Q%z`jr*6|@$jr^9`>;L!bTPUytF zoZHhb$Zx{@*=sKHnKQ08{aKzDJZ)mZRis)&veXsV7D{>ll1q75TlzWri`8@)t9Rj( z7qhuedwq`ho3duWmSU+K-n*j{JY(V39sAYqv$2^HfPAAx0tCfW+c_II5mZ!JUm`by zk*OsKlxroC+X6@I@|=#;ujAF&5cKF*NZ5w#y!3ybgmVS;elhRj8h`}3gY!{CBm5YR zOX14EP{b@H=xH2~YG5H9K4LBn#+JW=UG4Jy;;L_2e8xYSHLt{H{K{PE4J9_u36=S_ z6vpSfCF$}5rWb>XBax*AyV<_NeLNs5bxjFBpurBMd3u*Rw$;X}cGQ*v* z1=vmOwdS`9$qTo(I8E}bYLcyU#TrtdYiy=!g=Sgy996Lqb5xx!H|lq}5W&}XxwH#u zZ0q=LU@+;ktm|krwlm#A@Hlkv)kdVJKDYoJPI4TGwu*!gBM3CerbMIn{_#uQ_Qs9ze|{g!L47NyUIE>6e5h1IX@>hBEH0D z{Q?|fBf8%pOeSNQ_0&+h=LwUXza0t@vlV-NHicAKKi(zH=r=ZJdjpL>7LeGiIXY#@ zpBbBTTzY|ZPb#NYFL2fletjJnlnoA6KE*@SmN~$Zw^`Q>Cb~(o+&K6(TNED0HxxobM)uDhNN8W zMJz*6_bb421k7dfw_=4yF-w;+>$eud+0%6*wK3*cOe>CfY<-%No8%0MLb#)XG95X? zW){#~aekyk5R{NdsaE>$WzpgMSQdhC|GLVG&=)t&gXnFU!`_-(Yb*tCxCH3IZovjC}@-4gtFMN#%A7+>H~{WLOrXSYWq@ zZJFGgur|sGl?ai&fa85pO57Tf>40%w<90XI`&Q7iTjqnl5iJEd405K$SB-Dwy7bkG z*vNpngS6;<3yG<7S7Nvu3kN9!xx%UxKbmgs8i_iFnrwka5q`+tPRL2FSv(AKmI?-V zy7e703}F;#6cK~q6KL#}fvV6MtFdimihvKCp^`8fElqqr`P=GmCn4wbCgdhlI=6amE^A-E+gO!ny;f zu++&z-FYZx$ll%5bGX0kQUFd-y+{Y9Thoc8k$a21YqTlGW>(Oz%Vg2NQfJd{hzR}G z3Tg;-O;#G4QKX2Z7J#dZHe|2AT&;Ja!#z2$b2+!%2|Bq>#vpkk80vxp^FhMFbXb(N z-oX(5Kz8BRJjOiIE)mt>iH4P_`4>7@xO=_K?_Fcne=o=;c8!tus=DHW*6Q6+{Jwqi z#4m8D+AtQz`5r!7?&RO@?R-A*#1lv@P{ylef;%@-CQqD4*NlV8khPMgP>`@vPWi{7hX7Y{$|6dOU;OdyIJ@;^&Os^Wwb%1*3u zC>pZ}$!GcB6K^_0X+ZK^nv|WVN_SjoDcw=fy2iXY{4km<+JtD6c!>)(Z%Y@@O-+wd z>twE|tpuH@Jc$Bg@}2gmM5=1Jjw@fbMdz|0u;-#i)xXXeh)CC$O3xmGt$Hd4ep&mn z(K>zJoE{2T`++dm=mUs^RUPWcWe4XEGkZZ%y%kdsW0R$&1K)m+tkL=pUCxHD2B%c8=Nzgl*F1BM$Z{I3@#Souy~S7q~+`T1HiOHZ7tu`N-s*JxfnF-^hP+ewCFC)mA%FM@Y6q zwMMvK2_LI0KLC}uORJrYG_uM%Q=JO|MXU#;FOpxZvi82g zfGN#!N2~~Jv4XX@N?53f(TUTvc#MzJ%=lftCANZUjCw0izS*AMSJ0?A(n-tVhf&L^|#ISUURd& zabZxBQzM`C8f%5K?s4WL>Lv(RV{=q1s6mpvz|3g&6-Q5B63fsp#Ay@hWjvK4$}XC# zzr90>=49)l+B@LOBUUq&LabPA-=H0~O29sO5S5}b{BiWhz0W|MNK>|3iT@m*l?%*F z0TFt+MM{q;WfyGUv&`#b)6HdGl$Sz((m#$B;uT_%Hxg5cttcD^c5qHcvrRv)98jEh zUcfm4!#(BqN1tt`&2sD4j%w8|n{}64zjV}bZ8BbYW|gGrlL#C$>n@MZF5HVj!l>i= zA(QEr*nVN_!7i>KO7!iK`Gm?=8n%moc@Oh5G9ByNL$|rK$JUrc2>h1_Z5Q~@1ONA^ zcO{$Hu-qvdmf7q`cbuSxblo`Ff1sf{{0OAm-N_2%tG!PW2PAPelBxeH@y{3w!)vST z-Nc6qBM*b2BzV z9~Upnu1gbd@EI#&Sn-#6(N?}uZdREaTbaWR6l=CF@u!VJRq^&>$C-_y_m$ekbiE&s zH$ky5G1zHF*JOTZtjTd1m${5JK37t1a`X2VlYsN(yGek@oZb?DF?zi0oV00TBtF_4 zlQIxb`ngvVf%@fad)O?(r+Y?bBjCA`ZYt^m}>)vldCQ7!MNh| zp%^Xf9`iNrVq**2vJ0hbcSiDpW{*wJ;cor`GR>DDX*QnVrJ^|}R=&SrU&GN@_^DWVYpnd)SoxzUX^(&jtTOxA z$CPhhVAMa0?%z{^ZMg(T&*W{&j-J`DB@lQn5qK^tGu-G3$cPU-*U%Q_vu;FNzqdNn z77K3=eCKEeLvUK-_d*L8{YH5wKDQr^g?|tWKOPG|ji@FTeysb~qyZW}x3!Si@?B$C zK5Yu-ePj6wG=86Gqx^uc`yuDW+x>0l#ob-cOSJqzv|DpR(z?GYA!n{apc3Bi#aktJ zW{UTK#{==DP7-fl&Ewr+-c16Zdok{f#!E{;9AJKS_A`L0|Vvyik*1_w&w6UiY)S zpwNDUo{fllhMu)x0STkDcK1(+nO&g5uUFx#4{nk0W(mJ1(C~o#ekIWGP5J$Lpkb~2 z>Vbwj`P~p`xLbZ#VD7`Ov3ffuhjM~#tbPm@GSORFf)g8t;FEFv+2({blcfy>ci;~N zT|!XzWHL+7^nW?<&@6_O(Z4znk3v<9{uP0T4)GFbXpwMhexRX=Pde>3o=U^=Q*U-5 zYx=?mru%fS)ZZ-c#B&Q|m!Z2w+EyZim|;mTAz2JGTn#MPA>WQ^tN?_V;k_N<#~7)u zZVyo%VcAT$qKQ0Ou~?4D;`%EweQzKx95XsR^opzd64DGW_Pmm`Re{}dXKDDAh_!K< z!z&=ntY6*{{(-)0&%yq| z+CCyV=&SDSyzIzxS|g&|l;~N}Ghf!hNNFr3zo`7Q6oorCdyv-dZUM`p`cCfB33sN~ zP@{--Xs1IP!;fksq)mJ90$JZFt&TkEVUDmkVvMEwpn=||aiW!xSb5YQFK!ad`U8kJ zw!TNTSyH6Ybsy`T_(`Z1OvDAZ1c)<*>ge2SbRT`~E~8s2tu_v)tGmSktzj`%#cRKT zdP&1Gz*^|scd$@fDYLxcO~%_o!v0C6VcI`Ju8#2cFDGd-yl4%+PPL5UV&s~i&lqbMy@f-pIsC4aiajF)0Y}U z-G`;Zk}@F)wXwa4Vr_(syGN42z^{u3l6{1bU;n7!ki?B|JhWxZCcMh58{KyVrTxCw zr3oAL1LhI)Q#}nmELy!D6B(z=IR`kLaW-;X`4fH{sO-Rh4zq ziLst_k{b1oxiIIgZ*^@hp?W4dlHqN3`8JVHcp~w}S12xGeGh&1`PK7b4K`l|WQO*$ z@wh};j|iChZLVtlg=E0iIj`C)&>tYUnjXeF{~UIU28(>urDfXsqt=;Ul6m!`7`4_v z)jXvEhct&t0*4t_t8DmLQ3|^1n2061D2%f&d%_J1T;HFu!1WA|d*%YyY@RSrJI^n7-EvDejJoIVQLP9!sVYn#O3 z(CKY_hu~chVcGa7+~*p2gt?664)ViE6pKXlck(`cdA!!UOL@=eiRWIsDb4IDnkgmK zFWY?&KMqRU|5Kr)6&el}oC!EcOc;(tU^oKrV!Pu&+Vs0*hN)l{aDTw&GSdSyq}|Y5 z&gCX8QJ-x0M6+JVtP>#Qi*1rOH1Aw_IfU7$vVoQ-K#($}ZB+$E!&DAra zOT5K+U&G{Y6tBLdm;cfE#u?A1AJ__Ud%Ok^gb%G;y<3V;-#X9AA>W6k!+alpp|{v? zXqgdfEAo7*S*^LTIM3cRQKhkGJY}{0PgEMjIjAx1DOdHN%fn~I(S>k^VtOb39v^?e zTp0{Bd;*e>7dsP;gV2fMz439v#YmrP@r~OI!F7r!_=s$^HtC%$NGz&_t@gRAw7YN)Y0gD6GL~g7$;t0u#Pujkyqhzt&|s;_ z6sFOioNk=KJBE0|OCNM!ia1hwD4D+N3g|x~-#jf-{Ek&vk3eVH&;z!)+}GqwW}~{q z0fi5EnZP3okVW6*x1g!rTsD z;bC82v2tD=XcQqEFgVXdX2^L;Z2o|`j!OxB71lPI4pT|2EWaggs_Wza^(Mad`L3>9 z9{(!N5RNfz`#{Y~;1YA=hJ`Bc?;c}7?DdigeWM=r;Uhmz(DB-Dt@|mm4(~&; z`PgMXgb$^2aL6ph%y=ldO)29gr-H2bnpdu@ljEh_I=jO9p#!o;1rK`VUM^w)^GdTM zH-eV}yltiuu{Fi_3VW(Fu?zRHmr7r&EMMw8E97*TgZDZYZiH%Od&LxLQggGVnE9q% zWg!S-Y4AT$aJI^@?Tc$;=~S#j{BoKBrDE(@KS`NBR}Hb`YHAi zuC*iOh@)-o`xL9X7Xbiwv#A^Sxa}~1Bd%@++CB=HFMnm9m!&?w&0Pv&+^uD1ErJxq z$_HRsi9qM+I&)lX`6;uK8)o~><)?c0xMMYbU2FT)dz10$jq5#iH{ND0_J$Vw^m)do zc|u8}>n52m98Sh>PV@F1zW9z^rDsR#Q$gV3Ny*&!OoU=Pvh)mF_ZMtOBNTfZHL5ms-g4`i2i>&@*|@DV!&oFCPA|@70Sn@V(jN)h`yL zu1j7JU)-g_pLVd7D24AgKocn3SLKB`I1o`Th;d4b`!#WKBDWdpzR>G|hA1U4|Kk3G zW;Lm~_R$+7KX)#3N!4GQm(kd%Q~Myzx?rV@=Yf4qQUd zE}ZWqSQw0MobS>{B6dEjLW~Wt+Fz+)D%|I{UsXX|bZ~BFh?8J7$j$L;hw1X9nw0` zGi6R8><@`(Um8v>P%2p-|eYbKVE3p2Zu_NiYE^kOMEs$n$2E2T`Fak z1>r7mnxV9WITx4NEdHmy5v;-sljmR;Y#r`25?^Um)45@~OlKxSxc{~o7j1GGMXT>7 z{Zt)ZY7`-BdoSSG=&zNoO`#&&2UeNxAJTpCe{tOh>+~rG*!RyjU&w#Ct=k`85G*kk z_S;6&2{d=?`1S!&;0f~k5&rOt2YTc);_Zl9yvRqokg7%ci>6p{_ow%RQ2Z7@>Vn+y z7QcxXxf;W`=SQU&_AH1!`y&}R&1LhOJI}T?w9;QqOXedc+Tc}Vjk)=L-=T{mzH_c% zjT78bBt%X4grK;D;(qm|5VnbJ?+45mK1bN(N^RWiE()ELD|E~$n9*~D5O{DoXu+cg z8pFJJUgHGoAyIdO0=1p?E;3Hv$ORGWGwN=v=GR>14XyI&^NrIfGIxPY%KrGxZbj#| z3!S@6sK%t^6r&9~cP{b=+ogKLNF9Dsajpu@yTxm6@x?YG5D4bKj;7>_y z)^n+bzs>gEV%RsvZ@z9oXzePq=2SfQOspmdos|4F!B{m{Hh6`wEcWp~RPEENnr|Kf zF&PIju^}cSyz6qK_2Yz?ygZCdOp2FoFEw9I=Bc<~{FcwrkOqY`!GqI1DD=2|AYOX? z05@&k>>hy3;nJ_n9h)~0E4{wIdp1p%veF5}zaZ^c3Q!&jww?7Z zG0xt|B0`u{X=N|IECY>Esj@zhidGS#7I%xRD`$t+m6upOw2Z;_&N{cQEK%!>lpi`?jqrsbGy}WL83Bsu-Sm@!1bxi(Eh2c*#Eep;6wCY@4CSL@ww(Y%%?J2nS&v z!HsX|P3+tmC!wk3{Zr45epw%FB(m{W8msZGeUD!>C|<|c*zgpiB*hU)V1u%>5C|>X+@{8fxoLapAm|%R6*P5uznpQz7nYjWP1R40e$~`Z=@ZR=Y@o4- z<7^8Fx>*D^f6}^zPWduZ=v8VwcM6}>tm!;5&}s;ib1GG#EO>cISgvlm zPoU2p|7d>gVN9kl3wmF#NlwhfuIS51uXXlpVwbgdLztWWd!fm`&@4TGVI~Gv)%EgQ z9QQEPm4i;|FFQZsfx5YV{4QCgY#5fuwqSe`EVL~a(?eh28L?n$)Z?$YWJL%FAw!nU zd4BxeCVd;xgLKUD6DEl9BS9!F!F*w@32?wfJM2QU9|Vx2S&09%sLgyW*E(zx<^iq4 zR!#6$C86R(kCcy{_+p4%?(e&OLn`a$a!Ub{W9zrUP#0v zPe)C&Avu4(T;{E_<&HM58Inx3IyzpXCW7@n3DPThjVAD4Z1$&P1Y z9M9ru+MTlFxlBi$y_T`B{ZZ&W1$OK7!94}x>sGt43`8gQd46bv%}IBO-2TWkIf zhMyJyGO>n`HPcZOO6iZmH;Kv&sh?X8uq`y1gqe_ru0FIA-WgOmZpD%|h}xTx}KQ=i}HMZi8@uzHZbk>MNYCS8 zLyO~V-?W8>>MG%^yN**1gky#EfTSz#SACANrqJJ%4g_NyhW8Q2E-enzbP)%ge=CmN zi~|!jH)GYkWTC8IUe2^jvKseI!P z+_3>iB88NaGf+P9y5XI2U)3dp^cEIJv*$1t21p(?)>KvuqprEPqNxg8ih37vNN&y?h<2o5!wyw9Xt`}@FS#8&kt-T+h)YSv zHFjy}S~($rj^)kx7A9d+^p0~`Pih6rkS4Er=S)rM)|$hpQZjrR>4J5taYBRzcwcKw zgsn5ASlKs&3BcSo?l~dU3WMFeN&OLm;Z%SdFIbfNKKX2Jx!BTm;7REYXd}VpO9_^) z-o|j8oc9;@NHTBo-U`L-C-bI$vB~?;@q#A?Sh$BV)gCEp+3$I`77~L{GY$fN2goT5V91 zo)EY@rp3{TK!#=j6FJLt;3c$8PFNx)nVs4o!`#6^=8nVlq?F`O=13Ort9?C>iD@wx zQMi=F7F4b}g}H=OrZvXV$*zD&k;@-Or_F0m#ER7@8rN)seLTILFH-*1*-6Eo*oXL? zomO8f@`STMy&(@%3z z6k0i8Hr)|+$qAR2BvC5~X1W4jRfoYdTTb8{hC9=GM;OX$M>ZRiWozBsTjN4g?BHD_ zd8@*SQe3k!F*Mp8;|{x_INGfI1HA~dK5?*MYfPSl%p*V6Cl_LC0FIo9Gha#wc+iW7 z#%5ywS_VsUo&T~k>y{m?Z@{d>qg%-*T3zay0>d9-6a$Qb45LaO=pDLJjTkQ(-l>nT zPkt1GyKd;b`k{64^^NsI=hfiK2TxWpVhiiX5*dn{@unvszupYYH;~YQJ*z39ByaC( zkHy>Th+w{u+X}onS)L0yX;Mr6fTtKw-Ltma{h(udRB;U=N2azj4~=KT&g)k39qhbN_2If5I` zd{;5l{wcrmlkaB}#eC~kUYs7)$ zfPx!_aA+FNghDyAQk{=%-~iN7jOPk2T&3T66Bu-QXrseoY+a&EWZpkkhIZJ|b-O7@K1p zn386(0&m8{or1^Xy4#y$Zo&)MRh5a)yH_pmzGQ&XP<$uyJ5m2O%%W9C%xYy#kj5R7WZwU zhdH2z$>gZ*s+!vUcRjCCd@g48N|PV|A(WF2`pKX#ac31N|Bd@!Osx$c-cI4*s)l zZS?i@)g@1bzjCs@scIs6bz*(Od`M>Y*3G{Jxj9R799u1>SlNzDAupj(kfzpw#1|{S z;1%UT+lu8H)PQE-{99#PO{3K|hi5AOmrElwDQwOF#adKlO%X|NDvwacvh(2rOcVYV zpgb+=vL^6yjAZD<7?k~JAG}NvQ+(P7aZAyiJ}B$?AkHN`9UnM4PD?$fojs=?>-eBd z`M{x^9^3wh1!Bz2lH$br&b>iJCFrAeol+}S;uFj3L@{T3;;`PfHL1TqmZ)bJ?UG`j z$sMuP_Y~(=abMJZl?9Y6EZq;6C^zSz*|>D)MQx9abjK>A00!?}QHH`}KZLir=_N`m z{M?c4(iRJSij@`Y$v!Jl+;?E^|4cTPVugWx=#V01GQK&X`~AEJVN?cO8_(#x zwH|98q)A3&4SGEW8_kdfz3f;_$o%>cfPBYdq3l$B7gb_EVXZj@7XnDWp8Gcc!1It# z$;4f$at&_ql%Wu#{_K>11boJROZ(w%xJRKUW<-UL75QD z(M#A_7h_aGp}|3${mm*& zT`-t%aTDYzc_k;ORNGJBwthD5@Dd;zUHN(FE_qsYXrhescjKqAO5M+Rgch`ZlU2L- z%S*ts)HJyp?<|M=7TLmNb1%2}mz(|9`j@BE)}|(xwFcR)K5s+5b-Ao9D19Mbx%+FM zfiL@QY@zLzLpF$2K+eI}GXnC`9oU50e@KwEb~r=sq1YSMXnu$w_5+t`^*shab#EX3 zTWcr`qpRwzaot<@GdA(%s(Nd5RlPnuNu{dZ8fxYpiEC#h3q`%x@iPIRJhIjJ6uaAK z?5PMsJ!*-v5|-Fd(3t9lf~CBWu*lNSyWfq>^lx^B zyf&;!HRR5RHK`t0lbR1}QZ78^`vDZs$wyFycn$pneAha$W8Kb^(HjCW@4%>^Ej1*mS8(?^vwLXtW5O@D^qe=M^ag*bR8~3vfoyD z>j6tspJ~UCk@)f*3Cjo6gYap#rv3n5)Yep=x(%QIr>!ZE#z%k&ZskW=Y(Sgc(IH)D zFY5f?O-|i`8k9PPDcv5W2qA@73xfaKR;N0AWu4fdp=d@&$B3d%F~l*I^1vYuRVALa za@9cVQxEoApRyJ!^U>rn*x?N;veEuj-4D@sX+QD*v_C~Ve-<9Qw%!8X-T~yAC$6EG zg08eb1zQK$zKSz__F=o}ue&(P$IODQv$bDxsE>t8+zn}3lO&_Qn`F~pcY|gJt${Vo z+y~IwVKa}w(P+%@t%sJeh_NufS%3&?Ja=f_?J&^+dr0WGz6(Rv$9WHwgpA$;S#`r^ z)i!MSq&dd0pnhb1Ox>^rb@B7;U#|U1>$X+4L~J&tMBJ&w<0S7C`XCU^QoKs-y7pW-}%p<1AkK&<~x>>h2k@8fZlBK;mwLM9cg6F0n&v|m3; zj`!x}%!F(Z9?z$VvkY}`SRtTKD~;0MaD8<@jt=pGxj8YRPO(q92h+dXv{ZTLcPLb+ zI~|77`9LSAZ8kQ@Wv2sQ#HYL8op33$SMFFuMOD5}zVtN@v;N^r zYQ)-cDGr*gParD)eDV~qJ9G_v2+z#mi54S*}x%QrQ zT(fmR)|a=SC7Ac z{M_;Oq{C8Y_t$a4o z{r-ioXW)Nv?l9U+$@euzZKfPs8w!~61EyNy?XBxfAc@7P=&-eBJZH{Q*ub#XP+5%c zVw`00J!r;VO};u*0I-gV3*j6r0({ryuhu!pL9vHgm|Y6x3Y z-TTwaV6}wJsO|;7J4*K?Vb@ppg2@wwaR(e4Ufuf>!Z0E1L^ad{7Bw4kqSP-k1%o0e zyDNMGgS=D}6D&o(gRz8D_n`yv#3nYNzT|tFq20%qoKHvWmG}ZK`~8Y%u$pr-I`%xi zm7Bq?#&e^up*CYIYBT3rYYnxmZ0`UP%C^R1ty>3uAy`~N(Qz3D!t?v;FqC10>LnhN zmD{kVus4;K?qE=B%|X!OMf4}f@F>KHM~XSfhoV4!Ydd|uW+P5cbxVyx(p29p&MQ`a z7YK(RZm?nVP`ZOgAMi#g(__xds!Yhs-E5o}`ht(5?gZhJAbg}DFGiS#00#}|1U!Jt z%c}Z@Bx69b0wjasxkruf9?R&#$*?!=pkWJZjRhGNIn85E?_^Ht!vPK1RKG!ML@EV> zVU16t=>D-RYDGT&g;N_)`&c)uHKM-}CMQ3K|HvdZ^yRr@pTdVfm6a|^28{?`KGKzE zY!+X@p901+X1f9h6+b+)5h4Al%-asy#t2#bWBK79%P)Dlh0_Jp)D^n#(kj;-u9%Ck zg)lC|$rGmnDN)pQ-O{^437QW&AoLI{8bWNjDg+T)2;qYTW9?FpXBzB>z`BrI+@|O6 z@4iSST$)}MSkox#fxugfdleDTlRhr+^rHy|!}EWB7PU%$Mf`gv>Swa}~&^2tYR8efaIi5XjhU zYzoxGP6CsPN#o4$NJB#A0iz?$UX->u9v7~?;2d;-BN8XA_f_>624r*WRoSG1cG-K7 znH(a#&%$f(*fhiUc|vG9N_KfE$6OVBh&=5TQNjdxSUNmgf8=nU(V2n&;7G+t8Aj(s z|Ma;)J$zWf@z3a-?4QX&>Q64f|ImD6G8@=G-Nn$(iTzZ`_W|yoz7mPEz^a9iGx$H{2wU}yGT{C*af+@<~(|M?sWD~ zYt75>m*-Az=f`Vtp9m-U3>+6e&+6{Sbfr{4PQzDB)ZYmzDZ--}-CtZ>QVc))c9GD< zfsdcy!}?nCGjL!{0?E`c6cEqq?hololK`oMPefc#P)QL$97e^;BZ7@FF*E}Zfn!3U zGsXNXDk&;*$Ch$;Fc)M3=8h{VDkd;-sd9@5TOg;h5w^3M?QM9=Up2~pq!Q*pH;;n~ z#Bs1UJ4QaVq73^ERPi^^UihWGb(7hCM4U}OmFJi-JdJZq{BL}?fh}o2A|+#67{_L` z{<1NY#1FO^m_jgn^(WuVPUIaon94HT;fCY*)x;(-%SmV`T-;J6*$1e4x$*gu{oZj; zC7`RfJ^Z%!%;P=ABYVBsAH~>@V3C{$lFBieNAi*3l*}W04YeP~&>xqdc_d_ng4-Py zsNs?ui}ri*r1^RIi|%jBL_EL06gD2I?b?w7^c(EhQrsKt>X@K%=b5VFXXl!JUU^}m zKh+F^Ow-TZ2|G-T$%rwx+@0rZfVrYea^oAEpZ%#epzytX#SQ~}4>xo`%@@?}Gy=Ax z4`oBuz!cV`G$7HrdjJXY9}m(I3l-qB`7W9;t)zIyz@F^dVb!RZ@Mf4=cpsLzF6KjH z9hSGpcnB!=eR@gx6P`;IE8qWIW4wHQ021Zkb1t%YlH9Sr!zR2LTLH!+4KGOJN|bH2 znh3T@_ekK z6YFL;^&qBQYEQM+V4cS_Ozu{N0+g6`caYjsS<$WmDh|@!kpUnqerckbJ0{`_@|L@z zVWu)na>cV6V8>*9Zs$MD;(1hO?im|!_APN+0?v*lIDNttxrU7I0`En-Mw9$Btxfbg zhi8Ot#1?cqe5TO2?MxTJM~3kL0TnuQJCg<=4#q{~cAN^hZIH~+fy``+34<4l|G>rK zV!Zg!E+fq{w_4BvB9tV_27Df#iJEHwS5$7Kt|C4NgSM3t1c5}Vs5HLdMy16m*W!ji zp1upm0?4U-Ee#K4<;{dJb+PijUt zEY+eY3QZ|irX!%NIJ|exEcIMdr0fGdb{+l%&mGupY!o+(kXbi=lXI=~c37mWq-c1N>xe$TRi1tLdqALNklKZ+}R~dwr8PI1gmo9Ni;IKO!g*sY?*XZ z_+9RpJlG$SgmHzg)$VbqHF}7AXb0iY&qfDF3aJW3H|wDuFVDSJZuSf{9xBgGlX^Ah zD|sf@bEy5wY%Vp7F}zGJ6?!cce;ds#|4a* zb_78FL?b3r;fitu?S(rSs9RNzW8a7y<+&9$_P7s@W5eaawGbXT;s#uT%BFo-&GDiU zs%P-1kt(#0`m0`+)BI&Y@$kuPr&+rnp#B5Swj~%Bt3+y^>wHyhF;I04t&L(|tb>!# zjdLAs65m(hX_Y69Qt&4E>ri5`a^_deRmVI$mI*=W%R%6!(ItH4z7IFvycd2zR2%U2 zZqHJj;`)_v-}g&&9B5%a?JwI+_1fT(&H75zn3!-zAz7i4+kxpZ8!BlDMH2Q8rE9Sw zDMi>eV-9P_H>ZEDy!s=XVk93Nm;=hY@;s7T)!@k}fmU89PHBMZXHib}AdK#EJfp!o zu+VZAVq^*aE+?RB0nZ#5o>flEOc<0<_HrAD(C7N&fzT){4jxtBs{|1$J_L0&L0JBl zoqPN-sG_pnxm7QF5(o8Yr}SWgnIRJ__8-!Yd(fc7HVx69=~)N3chls zG(0&>!xH0nq!mM*4CgoS?xc(Xn$^?v#)SIv_FC-MDH0?^z0&WJn{>_E-v89vw9_x0 zgrF~$oR0n$#Z7_MqU#_&n%yPZ6H#?Zqe{@8we_MsJHYk$uCBGr=vW?N{OmaAxTFOcb^z~#RTbvs1BjK2%cA}%|1>*v4{%8E>nE6COJH@Y@?)IWgsRak z)#sl<&4?jM@g-l?niwq9m43%6=r*#}l9>gwCV{fE6<&B{mCQX2vI^<>-qbBE_x!6dtSwT~(NMFa%0HGtgT>qt_fs<1ZskEmqzHDVRo3mgJ9t zeMcxXL@&IJ1;D&5J6CCPJQDN^_zqRz9vdvBwXph&V;pI}U#P^BHUtrsH3sP@s?798 z4muYaLS(FBGTELfXrDbW8LMA-*F#Y@Eob4%yLtygUtu{5SKgkH^$Gtku}h6@nwm9l zUiBsFL9I)u+>a4mfgO#upAdBk+Ju>lKFR;HvPu94H2V7uEW z?kWnEm)EiNY=w%QVIZpk^$^1P!TZ0^2Wd&MvKjI3=dA?%KKLtW@DNX<;Dx&2AHV^^ z4JZ5xRnWrrB>esN70~?*W#hhsd9V?882y9BmzON5?ZW9|IqD6km6dR?#DPmFRx?~b zl>`=~h}*ZeF4CIsi!kSX}OG0obJjY%cdS0r-U&pZO$8 zak-}p7`4d}kmhpVE&yu*D0bfge^O7OvPws1xZKdgk5mf#VO=Vd#(VyqXY6>ZifII z0>F1rlqlcjo+n`cPbZq|a?cllZ91U9c2ta`jc);a$3cwxx(X4d27YWz|ooJQIy;uN->wpTEJ4XOwbiku7cdh_* zT!C)xKYezKTPc*ux z$UJm`lS9}h9me}U7fh@Z=GI}Hl3ngu0#@7~CGW{xZiqvI^e&zBIRTp^V3|6Mmz6H} zWC0tc!?p_8jRI!uk8+y;Lp>Y%-T7Wo-luj7ScZVL>#$vfRTyo&$OUO5z zCO^DBU-?vk<|-cww?KJUxc4Y;3D>2x2=_i^zi^i-uL<`7O|@ok6)W38+*W@74&Q+)bBWuAucUV6KgDX3mDJ=(DN;tD4vLiTBOBPksBCjNAvC<+?Cs5} z9PaJS-JI-Iv+AJ1D#swHp zz;%dTV6c8r)1ts}NXdT_z5bh68L|U+4Zo%^RZH9&{KrrfO~7+rv=uhtF4Z2_0CG0N zfiX84^AZhlvqdMdn4U%q;Yttc5Xpjth+({i$At37~+NZY* zNU>5(NTfO0h-l7it?H#ry-39dbBcdnrG+%u)$ud6alC`Z*u|OE29A(FHo z8t<1I%bLoolh>gAO)=2^g{}6EjriE%!9VgVedje+2Tnrrm$hBI_PrI>AUsnm+P~sX zbI~8QOES-xijx8`QwK2fE9k~E*jBAL$UaW{MU0NN6ckpjx1OH z^gOvELQUsHQ@Opa^V|Yh#mLY1^`xu~al5Y72(Q6MXLsRkT}r@ohfqEvw?1-ss_bva z7CzT$_DotA7uXm^q1VLNyEnay)0KV*)Yvm%ft68`-f3Cjxqra|kJG1`Ja_WnE!Aq5 z70O~@7k21^1yb`P4O8R#5NRk6KG}Po-dlzDEWOtg-$`FOeI4`-r%#~|?DDB`r{N?Qf3 zeA40(1U{5sr|X^V+G1q^#t~(aM)eUu1#xX_-N{o)pIAf;%Re4{*Tc(tFHpfub6PZ(JZ^D@XDw|fPb$tEP7?AO_)n@BI>V^XUAwY^5X|NaQ8cup&hK3Kn|EWcvxZZ93v;Eu_! zSh^XLJ;yv0Wntdex&dCt=uL+U0?`Wl5KN0f1cq6b9n7<`GZGy%)l6dD8uInhKo)}0 z@}hw4Nk%3fV~BC7@cg=iPGl~_$?x)Xu$6<;27m&Iw?`;NG-aX5lWAa zeD#CKc1hreUO384%$c~u<3k?nYb}^n`%q>sP0s_uM{aCLC_~esld|VT&xg3wJ)2c~Ic?k>L8r!Y)iR4o!qc zanFhDLy{_rGvjs`I*kW}A+Jk+>j%Xz;!03Co{Gr{PxPSa-%_%lUAGu-1{Ci?0I}`20Kj*hXbZ$;4<+5~HRH5p;+}u2R{)HMF6ou`-_Tqq|g?BL}-g&j?KV| zvL@1aK7?+(S3{pQ&kq|ypGJ<#*nNz|oi~KBUM$zA{UqFqKJ;7mL0wC#mQg8A-TE7_ z7CEYgfxki&c$D?k1M{_-hpmnJ1Z0J>{6n%2*PokT-zpymO*|T4UZep=)DOjei~EWp z+3(l)%&UJ-ZYqa7dr~~P!L{_3n9l1 z7VE3S^ll}6CPPTt_i;?-fr2J6Ly=gDzh6~xwxcd2OdrL}x~(LKcd0km+n^V{>uIf5 zjG8e_GS|CeW-N*Eqy$_sIin$abRcA!F$@|7adLSZzme$3k%Gp}LUjBm{c*+e`k1cv z`>`#-#WwP)JuMYEzWf2O@60&s8*`y*`Aj}HP-qp1Z=j#BBJRx<7QiG-5Kc=uAJ=ZU z4NtW&dUFC!^AhaP_=FCIFYsiRCrto&oue6`wKsd>awW4zmpjJA2QQy(TU3100`W~N z#5c|Bhb+p(Me~^ZCZ=S+51$!6OZO=#H9Q5Wclm_;9@ANlV}mAHA@s5+x2_U>jxwvz zlY+g|0*kq2RvKTFgofe66quC)1VCH~p#;YFpvmBm(e|Jj;vJT}+}zbi~H^)Rv*=(_%`B= z5A0x>XZso~_IKCAm^=imQ{;I)c1NG}N$MEIZK98lakg*4d@f(C{?vf248(C7HVx0s zdu1Dd)|yMm%{+TY<>!=+AwIesoku;GEYFr#=Q@{J zYlR`7S$W3B>KvDYyWpEaR9?L?EeQdbe&&1SzK!u%h6+-kjwQ|dR5F0_EQ`H;tyNxP zHn!PMt&8uPb%R&hfW5*Q#2$%v}@sXS3F)xI<4Ctfm z#7Ml!ZN1)1VF#U|hlCx&pPxy1>OPfCT_1dZuX8A=-Zo_4XsJ|4m zUT8CBz#smYsf}gYk&K+cl3Du%z|P{$&2i~%8>!i9=IeWE-z9jPy==~)_p$y1{g1O@tjV)D#ktoFTY2$Va^O)7kLr>l*a!gkgfAWYr!&;sy@S`AFAsPAx9jg~D43QaUF%Z}9$SIO zTp*1oba#f#h3;=c#zJ=&CM@&=7=KKU$2|Y9Ud{=Ac-@#QChvf$QKV>; z4X`*T)Iex&Fd`}%P+4YoM(Ok2z3y?PnMcsRCqCx1*8O&EO0{PQ7qGl)gVYUXjIpv4 zlRHy0gA*gd;Ax`;Y%$YoE)g2SbtgW)7aXZnJPE;0Zqdf{K;CQU6{#iIw%nmyvS?u6 z7bXmnPc;RSODK^b1a2*h-5D?fp=D-y=2wUg%1=IqoIcFTrEKwx4=j#>F0lpJlJJ}- z4aF6^S$Pzn6z+ijDl;DjA%xplIzDB~9Q%7!LjrkQGT#&%3kPg*U_-;~vw&{nvdq?E zImM-Fp?OS(4uePy&(b=KOyU=|Nlb;33fGNS%Je$m9@hnRwJ zCndy}9^`Z+j5)^4$2A0UyU1+stxBZc3%YJ;%OU#z*7R*r^_Nr zgC8t)GA%%}M?{+eeQ34zJHzWOmE$83dY#=~K@wnq)r2-IgDyC7`#dE;q933QofXos+Ws;pnl6gER+b-r%U!fMkUx3Ij*_$V8qU@*tJCa{UBf$pnvPgaui9{~4$qOw!tkk~G+?0SR z-5j4Kw`>{*wMp2U!tjnK-ulMdvqDC9)-oux2|LXa^fuv9QZs~UhkJ9US0;yyc)Si} z1Gyf&iuc}ms}vWWZ3+!9Q5qlTrW)LoEf{8KepHtB%mUkaa%gAAV+`yML*SjlL|$4N zY;9Cclh`5A=OIx(+awRSzV_ZE@G1=u#T)?(p60;ohCD0^llQZKhQ`BaYLhhFegc}# z9C+u7_par5@EURkUXKA89wo^~8r9UsGf7FUNzf1@(C*$jKO@_WZW zZVZh}I$=Cq-2%I~hT3bDPet$k9`HE#eY$CtV;?mv3yofByZ|-Ft zCLAe#Lu6xuW{$)&(tZr79g#*PGpivaicB$4 zXx91k+bqOnCKpIBoF-tV((Gv_2v$uQv3c<Q?=a6&S8PVUSU3^^$ilE;vY zO%aDYkJ&$#&?_Wk31WZWP7fB2QJ0H%YGGAODyUcRks-}H*^xX=Dc=lP*!F=E&Fc<|dWdy!inZnhN=ZrLH$^SQNK;_y zc`zwrE$fV&Fa1wL9+!3W8`hBoG4L^ZH92vY$!h9@Snca?|q6M)7ioBhXV2i7UQL9ic^rT^E#{h^TTei|Qs374&;CEjNy4^g2NlAeCStKz|DZ00e@P9=u0E~g(j#9U%!~IAHEJ$b-egu z;fo3m{+M}};Xk)$m?|*~7AgzzEjtwJ8=7*p)jjA59U8%Lu{}=@JCv~Vtn_O3+qs2i z=@zJ;hj!Fz2Xqc%je&AM8_WqCp_t@zTjNKzq%Uzyg39D|Ccn}1uKz#GZ*U_J8d|7) zgxC;@d&$z;b!N|JcwBHEd%zXT%l&f_X&u9Yt+9TMysCdk$sMd?D@quEIbG*L>cPh~ z`!;M2W|#Q!grI0A?Cc0LRlEJpU4G}werK!S8I*fqlLU5@GCY>NA$ax+ZDx7Nl5u`0 zXNZ<6)tl^Dn2iGh?I^I@jx)=G=_BHsSGjj9>&8A7v|l;Dn2Z^5UP=BP4- z5h|-NPvgh1U98ez93BI@iTM0Q`ye)OF?ZAdXmMF9t&sGQL2dg)io$5iebL2N+e{-WJdGUg8_iJ1Lw1}67= z&%a78T_iUQX(2@|ImA+z#>D=NDzVlK73I0fS`!D4`cEXP#f>y0rCI#1qPN!UM9s>_ zLWQWSzqy#zf7VSOeW$+3oiGzFdzn&Q?< z7*)#MJj6Yubg}wZ+29H$ zSi0EPn`o_-@u3Eo$EpS)4%On=g=T}X$cQ4m$g6-yAXYiptAKQ2S?tw-XI2|bc%)$e z8ppb8cw-6te(B{a5t^#xlJk)Uvo`9&L8~6TeUJ z`xHL~KNY`o_=WI0kKbqbeSWdo@x@&&jy4uWZiC{MIk7i|O!%LH8!)-*w3Lh&J414- zpn>{pkd)iskv0Zd6ZW3+79-DpzN&VE$J)(JKNK`pWOPDSY92D-NrlE;oUou93KY`K z6=}p+?LE>20T^3h10XO5Pf~o4_GzADjDtBT+}Wy+A~O}{2(ny5#)m$#z6L2d=vHtd zAHLNc1{tdH(;7cF2P}&oIqVF)9Ao)xAMUcC(d4VfOE&BN=I(a9Hsz{P?k~FFuj*17 z!G=NOmRDC@2;a5V#^VXm^OUt)*i#$cJfwM!DNF4`Nqpf{ zsGm+z$78aHT*^A!%ZHsOOC<={RgLQYJCuq6wJBL3Yk*u- zDt!%hC)6^}fh6I{O^y18!YiM! z<0M8zT}-p%qCt99cAPAzHy3z&rw8sfRpRIbP7oe4f+b{cT=zA8ru_1-@seRm(^O;K z93#}SHP1~mVJxJ&8k0yJK*!`v!0B&@eoi z)%M^~nzg1A73Yox>Qoe^X&d7nEfX!XNfMWKfm+%?z?$>J*YO^Pt6`y1k;rCF@z-_& zB^1Khd#YlgO-v)kE+pl}NO~SKBisC5Xe3^@2Ret~fu*pvW$U_XL4wyG%Tnja@rF;CRPd^$u+WyJ$pqSpCo$=C!67N7ny7Ur3%SZe!@h+^Y0V(@DQh zNW|ZU$Rpvt(84M8NeE}2am4!6S`e5o)oz)%FTh*TeYXcZMdaUGM>Z9R97Yzx~_!$OPey{ zb1}gny<`~gHYGr5Kstn8(jpqc+U4fVIKI_i-q?e^O4H?^f_sXK<*?i$#X|G=U8pf! zX3c`-NvXRKcg@_FV8(lL4)#2J*@9y{hRqPAbp{S&veHD%wE|SUE+IZ}(i2J60%D8>YJ2h46)VqR!_1~Gtz7K0 z8$1gG)BcQO_4zx|gBxI>y%ajZpeA`Ju8?G@2M@m8u=F(FKNMuS@pydFqL~_EewC$Q zXVo@<4D7o(A?Ub)4Vc>hLKWABv5ou?iXFJVLoQcPPZ8AAC3O=@9Iyn149KlW$T!{~ ziXkMK?M=) z!g4sV!E;+ZdO%G54ZfC`oP(avr_Rb7J^HZsqm0-_)2ye?4EW4B<2g3EAw7&;!Trlu z9EQY>9-q^eblBsh7Q-sbYqS2e?9~kHW9zR^JX@dOxdCZRKnje%Z*6?e=?$^5pXBtw z*A8EE&Ow+7QDdaz=r{*GL$E@J!)s%^-;*0f5~3Ss=?fR{zOZ4yZu)S!e0L%*!SJFS zYytE>@G{Hgd5K_G?B!N>!jbHr2?rqO;>8|pW_WWTCB|QL-suW=BpKJX?BjyfYV;}TA+^RHTXkg!i(Sf0Pwmb}Lt?jYC$Iirtoo!Mp3?{^i z9iGC7H*W0-9DDiufoz) z-|DXnzN)UUG}gDe3ssKobXZD4g_XBJYlb&8v^?y%5P}7cE*|Z_Lb7b8bz>k>_EkAY zWv72pEC=YK_@tI{|GdP|nDXuq$AoD-63vR^MRkk83){@s8(=U!x;cIDyHQq+cIApu zSNP`!yu-^r1jXf{mAOUiLVo9Y&;3w9Gs10>vD`llc+V_wy&RUtDvQx~ zCc)QqA8u4`pz6M9zVhlj4c@gD!MS=d?EDHF^Wr5+2@b9tsOQ0nDzZpTFs@1&^ZS(( zkWdu&R=Sj3@w#$o|2;FV@r)676M=}S4LJs)b~czn@yr)osY&Rx2B`OjDtvheY^j;N z<2Q#!RMU2PK3JP0b>I-Mc)($3fJ!2W#rEI%P^6jrQ+>0jvFLP}NboYBz8#Z-(;T`L zVy?P4q9=WpxIWH>c&PQ&w;?Q=bRZXs*^>ja!evd?*V))x~{V?9Gphv=z&O( z1)Mw83gAh%l5{Ic_Z1@4;s`i*sRaVROU>8a9O0f+vq-;{^arB!!HnDS{m1Bc!1=Oj z*69tTzlZprMDZ{RsBX^231JQ4PekF75(J!k)QWKkXTAgYWrN^%tGm8t{@c`TaD&rG zcUzQB)X&ebOrU<25;ZD{5=mfKxD+Vk0bY3VxSgamBs~wmJ43|a_z4WZ9W*xucM)*{ z2t9)k$5fT)dcwh@MC|QHMDcsnUDqOC9mKzI6}}?t?KuW_JR|~Z@4<}dQbOoEO~I5L zP(KQ4k^0}JicIAYSTZn*fU{lQ^%dfOfXEpGk;sEqel5J0B%=nBu-z*dekYL^K&WRt zn*W_@0r2c6`NBP_=8(Rf^hXAvpRBh3vp|piC-F0`#&dr7*%VQKtt1&Wkc8!%jLscAPvivO(SyeK%^+&PSq^Ru~RkZZqFB5c{|_+*D&0Z(QwSqmLDTO&k+s< z6<6ek=>-`sNc_S<@Md)>!=EO8${_eXYT6itH{=1Icom-YSpdUs!HLA5yYb5O<-nsD zrfS@+z2RU1Nm>Syi10){OXN!fk*E(jP|5IzvOsd4Bu@_{5%vAg$)de%GlBo^6?kWd zPc2YWvk`t8@$;|3t4s5MTuS7Wfk@FF7;j9xlK8}{@G@STE338iA7%bNg_Q#9xYmH@FW!1PUkP7zI=`Ms71H+ zhMR=nq~^jOtYEN5qQRm$;5<}-cwrM>bzQ@LbW$zQ-F&#goeX$eG@x9|`gSQlflLyn zc&+y5iwL~x-FPh&Y-fO&NC39qWahh%;ByESOh=_0WNoULlz&CGwh`Yh>olkUkVUBJ0btyz3eiiYf2f<^0W_jy~zi|DPJsJ|;ztjH-=mt5=iqb1UqD78HLJO7CuJn? zLE=vhf>+#V(M`H9@d zcBo1!;_V>h6d;k1k^0%Awi2H*2l%~L;kkaxPGyPmCy%~^dX$7eju7hU{|%>?;IqVR zh+wq%nSOx@$d`#+HV_FC;wJ+y;>lM7jOPqVZ_!8ve5EP@F1%}0H%TmWL1F=k0HXX6 zJjx&OW~q0PG@qm&P0$Oj(@%;JWvHVg-YnG`@h(;8Zb8s(4Eo=ZprSxQg9EUiL}6P0 zzfSc3RV3dKMG1POhw+cNCNkWzfk?gl1;B%@x{;?E^~f(k?IQJ5PzSUbPpV`W+NnMU zH&{ueRf~%2=~4o>5qJR^5y?jX1)RIpx(~la;5O9@H+YnEZ%63@0dQDwXB)%#x2iYA zBB~ye{6QmO|7`^_m_84{7oy=J39#SRjX?h?ApVJ~@WEY#KNN+F`d_KO_#e^sd_nW- zrGExr!P5+Lvj`*TEviJYVLrg4qEU$~uzr>4Ku#p`!uYGpkM(8*#!mt9r>??__*2x> zNPZ@(3xAH-Jfz+YYMx(q4M+L55c0ym3jen!5NIDsHVhBdQZfFdaoYOB@ZIo7 zI;W^#wEr;F-x-EDH4q8B2tQqf7v3paRF;LH-VHx%qGuxuL&yt*hyUhUk^X%o*)WhK z;CxnXwOv9@ihXC94Nc`G-C~VSui+O-f@=LG+~98FZ_)8ce{!c*=NWK=?L-cbCc<@P z%TJNNKEf{`BbOCkl>elfgZy(H&SE(x-wnFAqjdWCPbEo!y8ty&P^107)>3_mt~Lw( z3f|zOjNr$S2t=c#sDIm_x6efNNW?o$4MVY6a2x3#jL>sDEw!Q&4idaD0*+>y^GOcz z3h`40!S7TzT3K0jstt63Km{`$#~|tVAV~Mv0ac*qZ+awC6V)m31`9}f6r{kbY2O0! zC?R_X1{U>qR_$32{IkTrFbMuRwH^3?vqo(b?ooB)S6a=jfg3!^a1TYpv5|vA(a0Ty zFO0$?6(Bm{i|L|2r8q%y!$1g>Vs$!qwtcX zWgv-2f0CB|PU3$v5YO}#34vRQtRINf({E2k`sayvUxgRxo7EQ?g>4Z?<_{#%%8z|L z_LI|yzu^iz&l@H+^-EOkQsNT^;segfD&Cc&JjYC=JSks zr5-b(K|*bd0bO`idR&CJ08jT>;o`hO`njYZeHFc^FKIOEOL*P=-W9?d+{l0*!7mCf zh#VSbD={q*jNU)UZI&_{&A`=H9MfxYzrHp?Y@#hdxBxcPeKQl+< z5ByKk9VOj?C>`^cMtBF|FGb;zSVaEfwEU$k0m;(?NyPd4pJ`fq;3$5o-}_d-_h7&G z^?vW~`@K7amzk0Oj?AoKN@JOlDF0eawvJYpQYEN@TZs+Bk4%dEt=8ZTgnz2RBl%~4 z&ta5ji99k883{j03va#`B)=I*!usp^fbIL7+Cf)4U;eY-d#d02R=@Wky-0f>+~5O@ zc#(*h^MML}$nJ}nj|jfw%Jk4*ax{K~Z5+<*}}LHHT>skPDY7WHw4FJSopygIzTuGb>}`uh2V871_P{85l^PdO{j&vcrC zTL>2x;I?IYc_GlU{^qjQ!DQ{4Xs8 zvg#x`jxY|=x=8yjaFNW4@?!ocau<<%2O@zN^_wc<3mzp2b2A|PR#iF0M7FADbhll& zN7Xj{yA^KGR*b;Q1_l=Cga1$bG~#CrfttV@WF{Cfd3>4=M+^Jhxi^P{D~+$QbnTv{x(AN z&u2+eGLR&AhQQfTAnpj&9L8r_3iy;LJQAPS|2&5I{~qEKuflUb*JDEX$;6*S!jX`g z%X-L(!~SFq@ka*1gFmfcbMYMUFI|O?@+RJfTNiZ z`(NS`;PeU>@VSE=tGFoQCimhc?EuhWOYhUf*B+>@607s85Fv zr~)YIcPS3QFrqM2A0u4@>Go@M0cV4nW=Fi{WdOc3FfdBN`VHO*{8GuPFJJcaHv@rGHP>zccjjH2vGAf1CAhgZ|wUqov;= z+T3K956|n6+;W$XXpqf25I$PWa7GF~995 ze8a#f7^szj+K5~>5Q$`1A6qI=ADzU{7z7Xg55uP|2Y&P*c7OBe;vn=m|AsNC?IHeL za-<$239`I7!0YvL6G=~#biYQ*dNh9*^=McL;7fyqKdCC^T792^8=OkIC!=(tKm5}o z`h$z8??zD~3oJ+QZEbw+fg4mvG&@Qp&X)q;ranu2%7egPcNzYqx{>gG43`*%_m{6t zT}r%%_;bie1f#iZ&m7{n5P#$ZbMc9f3&WsAV?QJ)oVn_5S@EuKf7+*bcE#I`*HXgij>= zT;ibR7vZ<4S;Bo;olN?rq~CiLz330A0D~X1jU>MqNW%V5cM;?9AdycDL?Y9iU+ZqC z{0Qzhw(x%ArSAwORd0XF5T_&9zmfG6Eb(iM;{HcH3z z+Ettrj}m@v$d%<6<#7Ov^5m=rNy|VIh7Vrq)$&`%9A0<`sdyOMR*(|EWdQyZ@S=1t zllmyBcai#gB4X0Fl3&q5*s_6%p?+ANT^BG3r7$xyuEI0Cc`U*|K>X;d@#NRwtuV{u zB}q5@kHE^gtx?kNWX7rmICrLU^aD^}G$+Me6g2 zmi4!B3Luq)oC4&s$`R$q`p5V?h~GO19``@6f)Y&mF7Pj0g%55a{K+U>WWuB#T8Sk0 z5%t|DN+b*kRhM!oUX=F?@$(1bx&G8Ku&DybDFcyOdDV(ffS*i!;#GKtFF<(C!}*No zKGJ=R1hsO@j?>uxi}Xo4mLy)1?AJ)N`CrT5PQrf^4JsmFyghGXzGx+~ejpMQoDVj3 zqrT1)@4gBz;y)B8%5QrZB=ZN7F#HzAKaI#K1Cb*BXVi_rbDmp6x|O7hjnc8bmwt`? zOby}ZkdRjH$bZp38ES1ONOqB=1td(gsSBAtO2{jKFq)4nVjA!@rm6o;WDk*BbmT!G zgXwNSp3)%XN^b_4o`5If%~Kzac$ccn8P8INav>DdUMPD_qADs0%hTh&1+!Uj>LY+m z0fZ~!^$17zTDsaz(g;RnCQ%%SBE>uU`k5mzY%y<2FYFq9FyEk9a6?ckG)HPAuOB7; zdg3#PKM(f#<@ky+ivH!A|8x59)%;)3KQEf9 zD4+Vy4ZV7iMS0Zb{%;!uRn+V6jo_i700pqE9lE{qA9ovE%0eTB#UaGr5=R8Zn0A=p z`8CnV==L0ZK$INH|Hf&gEpY_#uO%)o>dV)CmzRw-BI-+Be?wm+e=Mz9-u`XmyFz>y z^@U%bm;^f`d5OK@*S++Ofoj>N*WaVJ4PKF=!O-?-qTw`tpW}B4zm&%k4O8&D9lrwn z?!)gP{5<&8;kOmPJ^1az?iK@uiqS~X=-rDeNHiZ)83q-x4; zy$#!{TclAMrpsp8RBf16yXB^8%5B}2Z5c;Nl(@hD`M7gu2olQ2^Vqu&5BcJ}|M$M< zx zW$1^YAA??jE z`~5)xz4hk);5u{-dINeLx&*C47ohXd%g~F^3()h>Y3Mm<0V+dBpaL`mC7?cN2ecL1 z0&RviKyUxM{lN|B4d@c|D)b6;4tgG1hU(B!Ce&@!|Hse;y_Dl`opg;INZdU{BYLN*8{mr6mYQaUyRZk(DuQJFXP zbg3~de5_V&1dWCHnYk(K%G7LSZlR&HY*Z!}W@>YWpRZJFlW_B;ljYJvDX7lP)%0L$ zzP4D0nXZ(|^0$0yt~5I{85}DuEX*UX)ffDupnGy=Ze}3}x(nIv>C#-eTA5!c9kcl+ z+0uOFxWW}bGg&JuL&YCkoT-+(<>Ab+#f6H3HS+p=r7~Mz=$9OD z0s$&63nmGj-HUy!p_l3=GZcGg7aP-aHtuAOl}|ek-T9jF#M!+Hx0_7zc1f7`Rf-o& z^Yf)s!c_%Ndr@03X#bwAo{A=ZK7=l;CEnX5Ah~Nm#bmA=8O^&@Fpm z-q@xPNUvNuwm2nQrN-IBwtKQRtAd6o=(evPbS}<4J6Ah77apfFKN18ap7NJ+87|bq zsmelF$aba11_whE;p3&rN_f0BAI{b0y8IJ4m7jgTl?~2+F%jfGkf1Hg1kX8q9(;65 zDtOJ|mHRE;{57kecpwp+hYAk&Y)J$w(2EXVg}=Oz3Ep%#_n^f)e%rdg4pw*z4lh4s z@v9DB1&6rb@Rp0;2Q4nm&lZo9CiT)n_ayN@IkPZbTU-cEmKuiFJHhj=3)JZ@O7G*& zej+I2*YdX{g0r6>?lJxZ^|v;^ukbmNuNGEobL4~C%Dk!bj<COlBlk7)j>B&T3_16q*M+(V-{4?!1=6bCs9(VShr!3x6*r{|g&-Og^Op|xA-Gz)gaPu5KdcM10WqsZb zf&sPp$*9TSCSBq*mZy-K)JbMkTy47^Yh~4z7ip{KDivC0`&_t8*W#b4t;!7=U-AR! zI6jAWp3jUH#-En^{E*Fz%tSUl5yQ>QY3d{kh4Jjb!9phAl=-N5e_T`|f5D0lc(7;! z&1X^t6V6~UH8zsY3kR-kxeX z{#TkcLJHYuH3DI~`;`LXdrCatiYJpJ^j9v#eQ@|pcgX(v}E zhn+o3+k18{sn`WGb0xosPysK8!=+PdX=Bgxv!!Y^Ox5NVO7xKPp;48`k!p}KP4x_;mrzZ0 zSeiR^liEP0tDmqL$^A;7%~{CtB0c$Xdo7r<|}ICL;CK9>mP5a7tmBtC>bPYlnBi82$U~%$JFndh%nH#zI({oLrozwc8Ok z>eOPAwj4H0jxPwlnd38)wtly|Z#re5xVCeXX7eYkYYy~^!Y@rtk>rh;6P4;I z6Pae1@tF7^ZX1ud)7F?o&i@ecP%03GW)dhxB9CsD9wq^Ikn|)*tMjQ^E#^lvGNZMy zUYcK+nOv-v=EK2U$N*j$RMJc!oT`4e@tv6f7}bLRXCb2qQ(N#^yeMsuL&iJXZWag9Jhet*xXv3x!%`DQiX7y5|p=#Vv zg`A}70*;+BO}6R6O+MY)9VLdMlVyrh{d6O2(W9tRVR=g9MY|SFR&N^*>mMWHYB)Jf z``+bZHQC||C4bGgaIWcY8Vgjz(tJ5gCb=V=-e-QMWal$_q4nJ#LS?=(HPc}36@}%! zQ5U8@&G`Ke{9EU37+>%{v>ItuX!Qit!bZ5*sDz5fjHYdiQGf7Gl<;p|j}GEJP5sPl zz3TE@vkwAf-Z-gAB__iF=oEb-<;BJ-)ObVPD$RVYL4P=>zJw@}OlHOxbyOww_>1(G zG><9-^sUEc78)87m`<0#7lI5vD`Ra>ZoAiAJG)SH;p@5arxDiZcHm8f)bF>fM0^89$U zMqQ%t)oYYcm3HR|@tb$qVyc=(WtBOtb`k2l)oRyif1aJIER`k~?1*l*` z>XVzPGDz=g3g?$A^EJhVF#^THEU~32y1YjCBE>D=^Vj?j9gehn0 zc?-jNTSP0YU&iES{u{%G_K@CMAEGY{$MWIMo}NCnfyZZ>UZ%-rHqn9h$y zTCBqu8S|Rz%%tgQV$TMYk9E>i)hZ?@4Wka#hG**ta#yZKGh?Ha5&niJdhJ77X54d) z4BYr5_B>ykHGSNPU0vzkJv0E#o-XpEsk6@Wo$EaBUHf_S9cYWF9OaWFf{lA&nx<(j zS0+xkd`ceaz0C8qBSn}=rf9c*-&;H#nW5WNr#D}#GI3-YS~JT)aI`K}%maG#!66EG9T_>pJOm`n+!rrndIgnxLBei$CRxBDUR4_t_Kyo}a z#7fxMV0JhY2}wKFCL%bJObum6GsSG$y64q`!qCByfg)N23N{?eRWbRlNUk#9)ZZD& zceluUBe@zYjb!|?K(T695R5ESWbk31TR*j+VzJ_3k;PipDKhVG6#4O?!MZMfruG*P znHf6kFT%WmvF+0E%(0p3%mU4xko7)O{TA*Y?gubt%s4QA9ZP>O9NAc4dy++ZbwymHpAG{oB+zEd(uj7BCejn8j z0NXw>6x z{SI+2#HBU55Xk)AumPPnVmk76BP8SPdl6oe&Z-SdIw2$zn!oso@B%vb9&N_wVfRcr zdark*^Rjf{-zL(Ej}ODgXCpc8_Wd%YK(eduhsO`P9{PAHw_ra$fZ^?r0VwCRL_HQw$(=i0|x{qfJd{Q-2YNGEaY zG`t_3i_%$b>U=z~CUo`#=v+W&8LTqq#4XkqbY5O3tOwCKhmP{ym(}*L9zy4I%pa8v zl?j>9{0)K+qEnX+SpKx@NdIAUCKOhp`Cje*dY!xpqk{<}Ym_IzurX<*9$>?d|CFt)ufT z=xkj_=hNtHTt}x9of{u*#(AyyJc7>En9f>h_$WG;*3tP4Iv3h>?sMtl-+c!N-08=)AIy&J*aIYtw1Z_r2(xUPtG%=+xKI*@w=N z+vq6YpG0S99i7ji)3=V!x1zH(rX#=G+uj5^8>O?{EE{nh@kw-UeB{0jrE_EGcslti1smH_BW9D=joelzADf zqcFUA5v+d71s^;QeqRhPgSGkAKd*y*n#zwO;17s#W(a)02iSe!2V%Gr?E6=V9|k`d zd%h9;Pz=BIp`qY|F?3PT{*<`_{uXSFHDxY>KaH(%rOd0~PHc@KWnKYmBZbC`GB1K3#n#wR<_!2V*cu1Q zEP;1mYs@E826tg=d?!-?YyDSaIhlRn$FMbSlj#KaU~7yf(*f?q)_6?j?GFwGS`^mU zOXeDQ7q-S(GFQM_Z_$`aW)-Y;8I7N0&V#jnqp_0A3Rvqr8W+i&1@~iX3?%a$_z7%{ zcVwzy?QPN6MrH#1S!|7CWQM@|ur+3p=?6cFt?`LWC-`&N8jHw04E|PZjXPvEfD_mn zW5`^8XedZxYdj(I26zBlV+WZ_;1ssT2{NyO)7Tml$h-p1V5|R^IR_rZR$ni32CNoI z{kqHoSS^tHaG5eVi>>}zrT{*Gt-e_%4c4xB^}{lK;9+d_xiZ_pBiQO+Wjeqt%LeL8 zW!`>pC>X<5zbSJKoWoWhDRTwgQx$0vE8=r^&nkK8UUU zOXf8A5Vra%nJV}&w)!QR3Gf8A`XHG!_-WY=_kq71tiDBN8@PzAene&q_^9FBA8;v# zuWuO&j>Yg*@MH{M0+(a>0=N>xFM*GP)hEfk0G`5D|08o6JZ)L?m&?t9nHVmEzZk;> z@Ut zis5VEWw39*{XS8z@&?b<|M>p%GT8J#F8@}+Kgo07f1C&Z6xjD4FM(eM`}{u#{_9}h zpF9u#ajm%uN9efv5M{t2*eU)$q1UM%b^j*J~*7vq5HmB)vLi=!z-R+dYR@9d#2 zN?&}R;fL6Uni}uzMQ((Liw6#ls6IzHl^j<4;IZ{jy1UfuAUCVtnPOo~&4R>FAwu=Cyr1EcX8T=iU$V&elPcw~?&-hLZIHp6cQ?^FOvM%pwBU`Y_S}xTrzrw~J92R?fi{5WvXMDTiaj%A+t>v*`3wv8x zRt1Q~OYTj%G>v$hZq$%lxzRHfD8h$L7%~6a{W4{|%^!KOE0#}%~9Uj>OUUk(Lgevu?>rhGij`LZ)dFkX~(v+v-&x;LoPnP9rN#G{Ep=T z&uRCXZ7eZQ7P5yJ$XmY@PBA|`7PY0rV*^Eg9`?^uV>t$`E}pdag`D#)CQC=crXI49 zv9`8-BA43f<1OCzWh!I&!&y?zx`!tzEU)Y>Ceut5oZsl?QcB<^j;D<+4{9LobBb2v zufhS-^GDC3z6^PN=iZ;fz$Z*;R>JY3rX*bdP9=VkFYN3yne_VTs-w7pb3eBV>u zEQ^QL?6Kl{q>t@d;_q!`?dfBSXI#%ay-5}iSMTD2i1fT{Ej`g-&t{-ycG!s3aOOQ*iv)4Ow5-|jt+_doF&ElqyYearfd+5L8v%xbg zUQX`m2~zAlRr~e~{W;%82hXqwDqTduGmH>ZseJGZ3#aJ{-)q(C+DWfvyWklXSH~-C ze{WO__B?(UcNcdS)xPfP-W?pYpPCfc?(N&#*SmMO8T)B{GhLZ9>z<>v6J|Yh zjLpPEH^^7&W<52@N9|f?J+N3c>#qkE=ghk72p`%LRrW^Cn|0ig(!5#U9jqKP>%Ip{ zbHVn>AV4qN`MCDiK4I3wxASJ-Y~NUaqsrwqR}NPil*=uNpyzjOIqg_Tm~ZPRRW@Q@ z%il@2{pQRMie0ckTJ=1e4ie`RhUy2>!OC#j$X371Sq0GY=hMOUF-qxoCW4OdXi|v$ zs&sl2#uk5m1YPV9y#P0o1@OWxZr70Mc@J(BpI3=j4tx|+-0Ikh*V)sF;QDikAor(i zyn4QmXUO7y=e|D?tiG0NiPvSh`(wmwneaQlHxXp!=fiIEuXKzL4rtjn(f0HY<__*L zZGq)AbED1K*>BpU)Xv9^Z9Wo0&XK>p>shx8?8?Knb)}+ zomblYd6#qVb?!mu#WsJ`U&(l#4d|Se4l>0@&qDpdgyt{5t)p|g&7XK!^6OpbEVSwP zFwApw-i=NfoqOGT-GwZ!qu@58Gts7lx-s6q51nC!h4fZ&-h@u#Ht|uo??I=h&7b!8 zY(^(sN9VohbhPRCxO)42=mcx%=(!K`{peipYJD&N%-h;0@uqYV_TBG^x%WC9`187S z@LcJ0_Zm8queaBu{kIpq2`=Jqrx?8t=2ftMe^;56ISx8LsYKkc!q^3gl?%|xybE_V&mh3lCoZwcOv!5^pI(ICN z%eA>r^ToLNxbIH+cjGq(KBw7BaNF@4I`x>2(*8dE!Kjbcc<*j>%F;Z1wNGtZ>^0Obt4-JXifN;F_f5o_?N*s>w(qo0 zu6-J&ebU<4GHs34AYO2|=Py|NhQpV^I`40C_wM?gcK+sbNVmP64Z83wgTaq*B zG6Xf|9t79c&{5caYOw$^79}%fpikLUI%>$o$IOA_wr@S+aE;d zs?oVCsu%u!WGhWoU;ZfTsaNpVyuad#xeR^~+tfwu*T75Is&_IMz+c8z9g}$ltnUL< zpJZ0R`aVE)N9F~vz7J46kvRj__W`OCGS7j}V5|Jg)WJW1t+Fmt2LBmsm1~&^@Snw2 z8I~CaKaZ{QDw6>JIc$|pnLh9jVyhg=bb|jpw#uB$R`6Nu4u?CyKLl1;lGy;RG9vR;@C(=~4>DK5KZ0%Y9{Y9hOW4Y1nTz0`z*e5h+&nKGPP1a0D?X(? z_2OC2HTwn~&r+k6KWp}RI9|)BPX3hH58~u;-u(V%<-=yd(((OGx7C=u8k0X2lRp)c zKO2)j>*Vx;xneGzQ+y0RkJa6ZDrBcMlWvA@5AJuv^j+2f%4+BY;LtL1F|5E*?z z%h~*!kF}exyBsjD)c9D&kASno2yoe z`}2kIBD=ElnS#QI$)6rsOP6d@`=6O{IdPi}u{T;X4?{U`Y zT*dDBr-|Sylq38V#YOArdzQkkuuy4KOYrQMU@--|uZOfr?dfwE+hDt&BDIH&J;EfT z4o!vCng53E>(QC5;V_q2goRV}ik{hXTw7&In)uo2xoj#t&K@k;I^NRxY3~t8?U^VN zfP&Kb{5B&Gjvgjkq}P3QHb#c>|yT4&RDmm9|x z@LOvxI-5;rh!N)&tanqqq@#o=a;V;K6Ji%@YXs? zi}#~*or(ZhDcbmLW`0;cWei)rlI;%~c_`6HzL+ETYVXdvB zus)2=je^2z=6l>9>3js8H_=huQQ1(MeH@YrAz{han@^$^ypBJ{$Pwl>uvmZo%2&XO zyFXv$CGb7qtxo?1u*#_Fyv%8^;-$JGvjEoITlGPv3|75TeUmAG#lG9&G+1jZs{1m1 zV6_XX=Q1JqJ=mt~V{Znl4yv5Xyp^}-v8YVTTm!!kTjf{gb+GbIWmRSstn^j6lz9cL za-lLPa}KODS9y~;4SoPyWlN?G-h%y*!xLb&bt*G53GhSMDjzbPV68!^EXZsDKa8z> zm)QXR5VrDI=EnF?@cY2+2kK545M#$ zJ9*yTHDu&wCy|p6k1+#mx@G&5b*l+mujA9%aecjS+}h!(<(aj(=tbB?F~TmI5%%BO z7{73DhPQTT9O>|Fi8-Hjh`nM;Z?Eg+%zf9CALK*OcKx;dkc^aX@mI2eHrZO?NY?IF zvUa!j+eSOeRJ_-Un`G^NNf!5u6_z4#i{dIwcr7>{7TH$RrYxUk2Ae%?HZB(Ho6s00 zqdmrdRsovs!OikPeu2#fX|Hd;!gT8ddwR^r$ND%}bACc-$zLz?`RMbeUGCGpUGCE` zE?>(J$&{|`dP>*0Y^`u4Yj-PIyIZA7+^@Cb=JU5*FXor8KHe{1eLVKn$78b3EUm@x zZQ`))S3c3<`(ydgH0nNI zcRCwSTOB=>+;y$SzU*}FU2c`fbynNLl0WU{JUSu5pZn;~Z}4v0bzW}M@nZ|=dpI`0tskG~iz}{q;LrBzV#sGz=EjoG8l;~#xh#Uyyq(@V_0Q=! z_xhI1+*jd!SGt%W*VgMYmw-jet-A3vJhpiJxDK$l`zw@Z_2Vb`c#SJ5bic>Rc`iX+ zzS$Sn)R%ib(wfxiOPKAhvO3dI~9`!=i| znDFAr1=PAS4Gxd7Xo7J zjK9I}CW6gh&jua;DG^LyU;QtMp#Gm(`+`=X6(~S<9Xo;D1FfKU{=dS1VK4|c4Fs$3 zm!WIOd)|isy@c6Aw!QmNliNG^(y)hcmTy?ndfHj|RVer^{DTr-BV1?&nVz4=))$J) zxC?$C`fV%EVaMIAg2Ufwb$5*VJz3%c0?e!Uah~|Bemoh3A4>)+4<>^iXmv}HdvlXP zM@KS9Y{b6nKydc1WH5n!d2=#253NGiKf&`)CWEsO-+!8Qy5n3LC*~z|{XMnSGV2(N zK`@LxjExD4D|ZjP|I2Uv+)w<-&-DL;fB0*^{%@cAH&1@g$S=*826pW?8vKzz+w0AH zAY=DQP_?;2iag%l^=RYUnMBQ_ORbvfp2YLc5_wr$n&B=V-7UN$)aA#aIeT$?gO6E1 zwSAF$GeexPj_3AIz;~qy&&hSK<{}#~q-4qne$28cNoAOvu9R)FXdZC&WMzT-XYBno z?&25K$DV$^qt)dFm2!hVz^rLnPrAbBb6LFicW9CGJFIh;8j>Qi9dBjm%k_gtBq9=P`C_~Ed#$BGo z`^?TP;ZyC{7m2^wV&|GawQ!~-qZ6#1M5XhS+Z&%$cg1Vtju)WYs+!w-PR^9MX_E$x z)^7(H8h&b+vf*xcvv-vdp(vXbOz$2Q0cyR~ zANs@S=klp{tR4)H<#Vang>yDKz9j0ZIa>@nTcX#q^!VT-+#Q!47$0vB>z%pv`DepZ zs_K%mu3EJ+H?=VBbFr6k5*NxZ=uWvgU5RRoh>8N~uSU`P)1{JFo1b!bzjeBjt)dd? z%-3ugXe%mS{G=u`jZ<`5R7KM%fZ52eyU(HmP8q3|Cw0A_zj1c^cl5F`;3hp?u3<_; zRFxDJl`F)0HalbQDAaqm2co*oO=J{7nx)BU6=+w%xi)XkJc!p;U!9#dG@XHxgDZ_l zv9^{$sd-%2b=?#fS`YqrnUpk6eJST|UASfkw_P;8+SS^OsYy5!OL?c%P}-T8nTtn>r^{e_ zT^pYB0}GeD=mJR}db8QWZF$k&I@QcblL@Z5Y!;XL^r;57Q&mIXIMY133*?khJ}IIy zW!jmtZu+(DPwXzs7X7B)+8!#u^f3vwNyG9Mw>Q5KS}s;f7iFotfzUR#rj~FH0}(c@ zrkb>HiuQYs9zY|+3Tag~X{sCGXLU*OJ9DXa-?;OIz<8|)l$d|$T6v{|uTi!s4Z6%Y z-fwvfZFcYVIcVBuzH<)eOLJ3|hK;fMFB5g5B_DN(th(*M*E-uysK82%F@tG0qDtlD zVW$h#UL$NnHu0~`&v5nZJJ)}w{XvxI#MQWoa;o{nw^^j2-aFoXx#C0D;WH0^;%WU3 z`mVTBxow7Vo4BkI3Ej;Z#lk*c!vo^y(sIp*E??Gs);6|?bnr6P7PO9YI61`JI=6_n z-?z>!j6K_{OVes7j5haGa=~?#p_a*O)veGDQy6k`mo^!HJAV{@%uVF|tp;12*6)^3 zn{Ani(aBQ7G>=4@7D{!HPQGMkV6Ndn&|n_kIPPv5jqb#4$wI4qQ~KN-N8hsDlq9-l zvhnOpy>4nULl(v!zE+t5n;k%Pb#aAdxoDc^u-QJU|3cr68=KWHDx+&W3Vd_0*0U}} zz+42|a1DbUHQGqDmJsEOt-`c_?#lLd4eQP{9VB_IQ8S$`H+?GR>Q8HoZRQ(MJ8rvE zT~SFZR+-;x2IV^^g67r4=CXKqpC`%f`v(T^4BbgX(+KkY$CNG`RqoD(oI#@=iS>kI z>Tyd{b|R&?tMsaFmCOh_R8li-CUZ67l7d-52^Y+c22DM6Q@sm3ijwc2;}7w|G>A<< zVkJ4QXz!J`jcja8&~(RDlvD1yGIt4myK-9@kILX}D_Li=?9DD#7iOrYelXztQ^%!? zN2#T@ZI2~&%RH%%9)3!*o7fyF?9?cwYgVPaYj)R8H2`yFz-}{$8H@{*l%i(Y*7q@r zsO40~T%Tj>9oV)wZe*#ttI<0Bra#|<@eHT-G)J;+kArBe?_b39bd<2c!NHy`V-3nr zb^ZPZ`nI(7gK9#j!o;%FjLwN;o+*r(Wce_7y*59hGWyPnC>N#vA>=#!33JoTn8KY+C#)GY)vQM(nVouB|NIO4)Z$o{ z>AkHJtL;5~^c1uslYXkuGO=Nai2|j$-OgUA1@xX3yPTyvfqeiJP4fb--rB2lTjSu` zUFIw_v}zB0?z&z}e&00rC7l@XM{UU(6JOJ^kuuZ{`-zsmK;znIuKZ)2W0DoNikTV3 zXVfMyqV7a_;d;rnhsuH0H8i>MKR7%O)$?dsLg6 zW5rL?kf7^C`+!~HyS!cJxqfUYWV;Fz1+|sBY`I*c^NAI$u*>%?JE-k$iXRNj%&Dn$ zZp@O!bcw}_k{>WcgB_dQil@RUO-&Se8ZDE6tYNUy z!{ld{5jJ&+jM{74P}hGFuGW}LTF=pbut&_cB1$9mjJlX>Sz ztGS2iZQ@OOOwrFoZP+D#eVDhARudfa+s1}9uC^(0OZnoR=&#J=ikNrRVv+Zw4C{|A zV+YOM*Qy`PlP9(4V@4SA!`#SCqEM22#Z$58KkG?O&91jGwxS`RcXJcX28pIj#ju+9 zth#$UZZW?D*tIZe*O_*jF&Ni=AFI|Tjpi(Ext7MLU-P;vI_#8NlW%k;5g$$T8qA+G zMYk$D7{1I*PWu6Yt)u4NdJ}eBHS)o9btUr-GqpvV0_wj=KMe=M^yoNKNgi{@GpvdJ8ammi+k zncO<*VVX1V;*XXN-nCW+eFZmb4C@5lrX71t%Gf*1jkU`IKI`Wm6+5%=F{etrer#@b z^T&ykFL~zs>qoXFzUquiiV@p;=Vy*_b-Z7LRN>xX8x9R2V%?Xy*I8|u zmiS`r+4?~@)5+!JEs}@vDL<|(d^Ti}%`e)!Y$MCDz_q$1y6|W@om`x&@Zt%(4|zu1TgL^o6!LRc4y(sWVBpU;R_d&EhnLR6py?&(c6^ z(Bu6sl^L9B_2my0NP9js+c)m~jt0D@Sgq5h+@$|UY){yCuBx+nBB`(z2+1qJ1#Ccjy7kB-o6{2=|-m zoB9{NM?2Z9xeH5l2ASvY28*6UCR=hZt0TK7h9#dyw!z7~A4ibg+a}8))4pi$r*wyq zX>YWb$=-)-BewTTvL0mjwaK<2<0t+|Px=od(_U%sR(1!n&DiqC(?(?PjbX{({_fU$ zEG4^+?ETpCM_A@fWNdMZjO1@1`vA6huX`EU{SJHCYsemGlU+czCFV|kyn^gOZ1EzQ z6=V-tHj=-9?1RX>p6oNo9&XcHLZ&^|alL6|A8wOPAo~b1A7AMYA=}y}+lTCjNjMo%bR51=z63$TqmyAzy9@_kH73Uk#UE2 zi|ln|zmF`QmKTxzL7UzMWb8F;(Oc`?Fa5jy!K=_K&^hQEbv8HOH6F^0k7hFI(Sswr zdlP$}#*jm-nlCz2dtmCi};}=-&mkWyt(PdKDY0H56G37nY5Lw|B}r7+JPwQS7YBa zmL|>mjYc>0(e%s}`acF+W^zU{koq;1|>Tj)o?u;GDSlz zMZtE$c30GAZNDpJh7nqf(|$0sLa5<@#tRw;xP4f`_G&rkl0jzH#IS{MkIlO?$lnyE z-5X`+?4U*?TsP|4wCNk(CVjKC3;K<7Zi>0PF92+Xs!cM5(pr+)Ii?AE^sAGdLn{9$ zY_`(za19q4SJkVfNlngXXDe*yV;?m?ubIV5xz{ky_)ng=Ur@>S$5^w_Q@@aJR8&0p z5z5EVKWonJYzEu4T(c%vRS^!z=3tb4qYuz zR=_nF=4V7Nmo0a)*-rQkFGCOi>7n48r5qKD9JrUI(Wh~|#(q)l@AYGQGv2p9l}573 zYRPPocHe^AX$h5lPoLRa8DT$H_xgPHouUcN`)^e|)?RjnVNALMN2vBRUn+A3|F zIezDGe!$Cjjx>4iM9=K^=4yC$E^$x5%v6bkxEg$q&JyyNI<=w7N%k=;bmiE4tzBoM zoGqJQsMW)#ILfP14aT%F?$C(o{|rBnSCh?M1KfX7HD`l07HWKZz{+sxOJQN0`wK#T z%$Y!EaK2KJdUo8vAc>WyOy+C+vN_WThG*s$`FST8tt=Q{+v75n>pCcZh*NBp*rbhp zujIIShv+>=^G~7PeDASbX4J(!(vi%)LnPDp6Zyhei(B(1F~0^mBca`$d$GtLyZKw)nkmTJ2oL4VJ4e_R6km?q0)L=f)Ni@wcb7tCiAFBVCj9wD z_oc+*oVHT&yHoq4(0pqZrt>*gA#J8hdYGBY_JUw^I4&s6Ba^!s)0se@ey z*;IEb99}4Qn~iadT2ktQa~1Q`22age%)+T4IX_8J%d%Cp)kmdIo?Q_2urhnhY!hQi zAs(cj_ojC33I|P`V3QTd>|NH{31WpE{20UM^gIeY}9lq3_J1_;#-?5FPhD0 zrr1v|m>0e2Jw}ofVa}&9ejYrA%h@oS+qtx~WM4ZLbTbd~1(Rm%>768Ab2F2yXPi8F zvb({pNVVBV!hC`AD%#!Se__6IY^D_EM{{8>r?|vYK;?jaDIqnD-(8*!3%OM6=`G%E zm#({^CsPRs3e!|@Wx$B`H<%95-7QiLbBpu!8o#B--!)mSPnTwEjS^$BL+tdfrSwC0 zlzWO#gB7F6QaHiE){Rm~fr)-$=3V%%DU_2&SkSh;xrMIeZp5ZNGO6tv-Y6%VUI%rO z`9SGJN%|xF+`ZVq=TbN_+S_9e`e>8w(%~N?%I#w_Xog%-JRXc@QsIgI-6{(4XX#x% zhgxtiI4UdSrsxF8g;{o>CJ&8kiCOF8D&WnW4)QYvz8E06W*W2dpA!^MsO@c5AODkI z*9>QV(*m>el-2NK(I)mrkgieq%i&XViwo1AW)+a~=u4>Uf|?03oX>Jt$rL$Zw|$$+ zAIq$a{i!DG?F*e-wGK@MMxd-bllO(n`!CGcVCD z8>-f!B>lt9Wj|l&ec~1=Nn4>pMAY`P6`3DK8)5#Cx|CoZ|^(M*|Ubun(y`aEnjQxba>)3VgF-xf51(Jig(V>=qI;EI5@Fq&sxuY zI%oL3#N1q_8dmQPIWMbA_mbZBIW-|)V;^s8(Fl?w>2RrkPZzzuSu%BdM1o}bM2TZW z%dX(rfC@8nrw%k5{-}h;`kyt^iPkLEbOeRkDZUB`N4TydE^g+zHY+{a*5HsnX%eRv zj;6 z$7tJz+HeqjGC4m*^T96#<`tDtJ7|BMtfi7?=O(*9Nfe{9RhXYK2^*zS6hU;jydxDJ za=*qr5rxY#KvcF&zkq*H`7lu!u{#_ZA(t=5>g9Nf(KvnA_~CGT$b1ePrTgIcPSZB4 zojzo*#|p9oBVqm&dtzoE+w}w+ykcFiAD8FY@-(kg>^-A1YpY>@&lBAJmzm?ULNntt zBPsjAlXlCS7i*3Q4&`z-&D+M#xn!5#CQvqp<9X7)Cmc54Ty{m@T*l-0cv~EeyKHMu z=;PN<{Gzhc&kOVR5#D35*WJ~>$L597x$rH8@NkCKno0y_>gb1%L1v`boGXlI0(5Zn zU_O&p%JMA2x>vOY_qXB4+c4v$7JYi|7OeSA-2Yu|SaYHHbK0gB+!jBsGHiL?(-yy; zw)pk5#jmF=em!mR>uHN$PZU2hmR8uzcv55Ilva2uK~i=;lQWp>z8TMw_Q(c?lc}dz zcoRR8&)KmiydP#to*K8h3?Gdf#*0rG|1|95k>N*ky>_lcI;lM4Zj{pyBH74DaevN+ ze<+*IjM>;3y@^6*G@rEo5Z9s^Sm9nXBU66ia|c`;{Fn)u#!qIfBwk}A>_ZwNVViN0 zY>kJo2Q?JJW)Nh;%;7OL+wemNlcP^Neq@9x6ME0&ZCnSl;~BGDiR?h~P=?u(ag)Nm z^fW|}tucYI4_R#ccby)6^@!V|gSgLxxUx2b1zhw2TDOuSF? z99^HDPxS98noIiN3)#`9l~mSGTgAkyZ?ZB{SOo)_Iv!)w%g9zYBAYJ6*ik2eEHyTq zR$7?nG$%z~Q+zgQgBCy3Uo_2-X`{^*Ul)deG_WjX^xD# zcr}4Vn$F^|txNe`j~l-w*K;+4#_p%2gZDUFO`fo8sjXjTO@(yVf|s^FiKUB~%O z8|s)!2dlH3!#K}*R$0eM{J?#EF&(UYhjphoJx4fU zjn(}%!s*#D5FG91*_MGIyni52IG2B!_R&=Ns+MqRYj(E8m8m3uk%X zK+yB?fj}#x3hOn(>iB7N|64NHe9wX4`cDo7*S`~;FAW6C&}FFSdj^8scj4EU2ZH*K z!e8S1a47N5l0h9i{N90}eMYUH^0lpZVY;Rdp5uG0{053vmkqrL<^o}@93Kc)znBh=k{VK{Yajel5U=Cp z(Kq^c-EWq)@16~mRnGEi&yzUzc~<|eX5K#M+#S7VFsMT-|ARcdK{@+v$|ZCbd>MNc zx(X$J2m8M#gZ<+<8qE>bv-$nPfBU2DRCY593(kH|nqA)1uP0OUwZ-_i#;Rj?^3R?* zn$(xcW!o{lMxH3&f)3igvdz<#BkABW7nyf_!Q!3`v=5xkE4>8#a*1{byAJt0KRb^8 z1pUFJS?=c^%>%(v-6-z-y}psQDCY0kPYnj%U$sMVf3Louw)Q^4!EM}M`ZRTtx`H!! z9{*R~OI!H6lp)S43Ex9l@1xy%o3lOObI6yW9-gh>pW38wGvOSfzk(9I33JBDGU2R1 ztI$;_KtDkLEOGDnI)32i(cfcyPJbHv;ZHvsYf)=5+P*f+7jyjH%8o7;+Gx*-pHG|H z**<<==bgl_hxm0IZmoZJ%C;@r=FFtJX6UT4Hyb0G?#uwh_~$lH7~aI)$8&7I_0{>S%@WRi{3K|( z+dq1+$Zs%n9Q0zsa+t6Aty_orI#YPC$knpOZl>E{v6)7LMJ8ZR6}j;?!#qytvu&w`kc6dB%6YO0F zg52srP;5-kl^G}7FPQ8YxH0Vp(YRL~cGwJy`91MjhHUvs?mE}53AKol$=+}JkNm0G zV>Oo6(x$O=D9=yl27ijhN=ARIAxX=Qv_BO?dD;j*FeqpOAP4N@uxGWvk82Y_XuZnY zT_K^7l^8{$?81uNdL5l9F29C&=jA_01=kC-RsFPGznuzJ-bw{$kzZ$mcy@RoxFY^K z?bitHI9PaHRe17=rp(tn^}KBLkG znN7hkZqyc@$Bu`wOn3=}3H68=^C^ti(9;-w%Y9b=@*x{1>0gC!*T2(F+IBKm@N0Qt zr`adM<`87Lq4c=yylbk&kB(8xu(P9u%(&V@c;7sU*D*>)Pt8nj&@4U3K8&htRbAO8 z81Z~G%svzvV|agItv-GBds57t+W~ERG6r3J-Rd`}xa}3uH-+)>e;F-)hnzBPy_t~d z23!|Y|3DGJupB+bPHZn_ce*(wPM^?tA5Ko|$I27>!qKFazWFxCUa(7xO+7kVP9x4X zpZE>dwUK5YdfU_1aO}$QpGY{F>Tz?GS~$dMh?V)kw;Os_MI`K`ZE;B>S<1by+LWa4 zAOVBANEmy>p4Snzd4u|{%AsN92ZKp|bv2FOID0i>Ffh7f<}f~aABF4Nun@Cvd--#l zc(zH)?`c?QNzY_TA^E4$8D)#vU8fHv`CWn^P2C*Mhc%mbd$kmYJ8g$;JMN@|O^1A8fW|MC)Zj||{^79!0r7`3 zNwc;t-v4NlFGP(lIt4qH!e(weGR9h#6rjA^w~1+!mP&xW$;bjE~n$TsAoCfddwJD-yWhYJAQ(MhgVi$Hpps5 zZ%*6LyJp=t=uV9-L!9r*_)eyv-=)}@60HZY9B`~6@7+OEJHk`7Mf<6tPT=5YxuP4t z6lcnvkEm+vr#cjiAI}_x}+8bCKBX{-B&K2 z^QRfpjz;;d_c+41MdKZfrB?nKW2ist=GlKK9bAW2kYD}Ftp8#AIbzRWq`!ThaTc>Fi^Xs5om8n2xU-0+uMJ{!|^RqPzL)(n>a6*IQ~fPd%F{W;|L@AE;n{Fi+z|KqxA@vHLx z&o$@rF6D0;dYhys{rs=xqfFQ|QSdlj(ViQ-sN-c>Wi~zUA@1I>Ux@DIcX>N`xzmQ* zHeBr&HB^&S)9!klIygSAj~G05?VG`a!~2T^$$X?Q?Av?k3w!++C@=Nj83kGV;J)2=sJi;rP6uQPzN#2t*`u19smxK}m^2Vg0i!^h=A zH$UXzO&#^!>i7uKcbTzca@72HmsPT~imoW~|KY!&10qi~UD@ zcgl_}I}_AfwGUVKrGm@U>lKG{PqOCu{i)!Z!`H!jK3!Qd_4y?A_R&WlwYO9Zjxiw` z55Z#r28ZbV}-2svu{G*qdwu>KPAt+0&=eI z4fLHs-grwm{e6AAclHj*ZT<=EyXxr~Ol{)Z2p1{IAMarUkTruzo}uOAlke~0l1rIE z>j%-_-m}NV^&Z@AODZBuJLLb}{4wZ0n|_&m{yu$dw8<^i-6tEJP06B3-Viq$*XT9} zWKuN;*u#%z4)cpa#-3;YCEO&8$D34t&Gnjo6tkUa8n+zO=9#at!J@oK0Y?Smrc73v&={h_CL(o1E}m(8J)?2vGKwqcfO7Eclq|b&-JGT zTd$TJ&K*pddmmOEKJW0x_gnprL-zT7YKS#U-e*tK{@jlHv}pPyc~8kP%e&%Lj#P|P zPqox*>S{>i-aJ-K7X!HS@(ioveCRt|N5Q#^C(SX2_~AKwS4o!{lXKaKVMcYxp;^k~ z>rQmt?<+0)u?n1h$=$E!s7jUuqF}qbyGud$u9pqWpyEZh`Mxuefx}&Dp*(yx*qdd9cQ?(++pk z?DO*u*ByS#;mZyu9Q?`Z!)G17?C^E)*)OGn=wMp%qW#9#euY;FsncxkFbKhg1Z+pm<8HcM5cYLp1-}s8d%V4>G+u^HV zm9g{(t^34ji=TIR#o^Z-4!+OMqqaV5_3L2yS9bWad;W^U3H+A-v!$6iicQdE4rVjo z4wWm7$@v+3YA|2e&Qvw{QV}WW^lkq0`wbrq>y%l3A?Mj_cNpeO=WTx?=e*k#cRbZ* zEAyN3b^>6}LNh0q&GO5$&dk+u#w8roxi`d~S>HVHag!cSSE_YRnbfa7`h}Q-1UN-o zKOsG<)3n92frkTW*(^ph2(X)9o;S5mC>R}T-J!Bn*GJCg(=Wx}Y&0+f4?av}jaTo- z&t4UFhbvmgsZ(ZrY0g>W0KUnJNf6eSn9i{8%I-UsE+@9Qd!%NXpOgjPMz}Hm?8%P& zsK$tTip_>!P}|!YCwr4zH0g1%+J)XuXkn(PYHsgRaEmDJ%9}tlv2GT&P`gu4T|EuW z`Q&EJR}1o|!kiA)+k4-Ap?(R}b`aJBCnzj~d@!xUxWf_7DSpJu%%R>+6m;&-Wyf08 zoUBES`>0dduvLUCcax0Tk{oAKTxK}TF`Fg#6wiESJj*=TNtig9%@m>8cyS-IcImjN z@4y2tK-XextV_|JWU?5B z$c*>RIM`F}Zj4VO(Lf8z$MnI=0H`RuKbS4^mW-*#+!xx1S`s%&v}!&^Vb4i<6; z3ud*+IFp`}xzVdVVqEgku_y%E83avp(>s|QU}LJ;7!aC+q*$YJKiWS^*sW=hqd_#u zSs+FW){x*}0l55E-}p5NN}aP8v1ulO6S$9_pyHz2QD{ucOy3jPR9Z zPfCk{Y{_aJPo3D^y|deVIcU}#S$6!BGeq%D`|aBA8*ZEuykf^m`#$8xHQ(af+&CYbw;hHX}@gcr64`| z<(L-c|%zW;;|;DzIEh1+F% zejWd`2b+)5MH7l+V^*I+>f#6Hk-EXu@tyu-T0Np7SUok#UeEH8o*;UK(o``GThwr> zYHUDfr8_>D5j?TU4T)2f!!Uh$* z3!Rs4p%XftccXK59i5HnETeO~G`tU;YMYLKFCW$>bdJQrS}VUeZ};muWA}E(pTX;O za`>sdRC$m|gCD?F-pllX|B@KOm)QnBhpjx7=>Y#_Y~`OZ;J*T+ypp+oWhnSxu$3<| zZ-8IKRvyS)0{GiCv)vc8^-Ga>$-ED{jP7jC7Laf zC5Gg&OLMB+lM&tH;N93A&$oBt?_}_9+}C}^QN?V&Tr;HGg>`FZ*BBRG{neDocUE+k z$nMtlgyu(fdo?F)S!=KxxEp$)%RX*$>pmWmLem|$@wNNYS(&XboH7eIMsFWmAwL(g z16B1tG+QR!)JMT68rHu-dyAgi%fDs#qmafTl1;$ppbx-HCiiLZ{SM20KUiZGx$lI37}B^&vd!=T^dP)sivRUb zWX)X@!f(P~hCT@Y5Ofj#0`#!M=iyhN4}oRQ!Jmdc3@_QymxqES@JHY!tHYNe-6^5x zN8pDc-6tWFhVO@TmxN?H;5R}aclhm){DeZVWLM!YL7#AV75-)DlMbJQKMj4#;RX1k z&^CvM;d`L%4sV4Ipl@;b#>aVI=+h3Lhd&E-I(!;F2dR=PJ_-2E(4!6q@K-*T4cPK( zo?n7rg?2c69)1bxa#-cJ4DNRL2>d?iF|g8O8~kQS<9Nw7z+e4nHqdgH@MZW{A^jd9 zd>;NBw9Db=;p_`hfj;l>bMOUd+~Fbktx(?K&G1)0hz?k?%kUSVgATs}e+D|_@N@7J&|$FR zI|Sb+8N6hj@B#ERykyG%s}E&^XB>VVeiiyQuw)nDUxKuULHI@Zv(Ojd<^O5;I`r-E zl9l0eP!V3TbF?S>z(*Zc`Pm9CIlKk_`h(fvn8R+m+7 zz4<^kP)99&)vxp5n!_vbr=hyT3-AT#OAZggZ-tl^825Ug&EST^0sL3*&jt$)zXAUm zwCL~!_%qN6k4eu7@JWY#{aSK(h-W*XQx1pl8=)^d{MHAu!Ryd>ID8TQW#~DF&%u|W zKjpA5Z{O+g1kZ+`?{YW+zXMu!IE3E_eYeB=XdiBLWP|T<*tZYg>#&diX|VF^O>|#} zz7JlqRrr^o?{`@J+Y8`74OX9}{5TCh1236x-+sVh<>xfd{|s2B3_k(=S$N6RpY?;E z_ZWUF^yk2mZGjJIUD@6!#CisKtJQ~CHSvE zf5YKd;Lk#@ID7_v3HqC0$@Koy;GcERkHQZ_e+#Vm?t|X}orjmq_qTsrJmkyY|LSmv zZU^*tz>;l*zxp2H+y}oIdd=Yt@K^532EXX=Mfew>f8y{N_+{vqzzW~D=NI86Ti}`6 z^IwLSOzB@h_D>xihTjJL9}aJU*ZBLA!yCbBkN=s&0r=>K&1b@+?W zWrr`ozXbhrhtI(;L%-_q0{k%aFC5+nzZH5NtoPXnf8*WR;9tT^_Eq>R(7%G0%)j5S z!As`f?~23zeSRG*|1RS873g2XOSS@k7Wy~vlAVEHfZlMp3ZH}iFNf3cozVa7a0tHv z`nO>D@7w3A@J2>?RD1mYfF)D^eB)i&;5Qsrf2aA#zXKchJi7?J36|^v{7cZkhnMUe z{8{KX9X<{J9P}T+lBxVJfUmjdRroUW|2ljGJ^}qlhx_4oK>x|%t?+N%OP>pt?5psX zq5ll8_^raf4E+~)${{fcl?F}|Q zHypkW*8BYySTg^9Uvtmji-*)(A_!a0a@K(t8f4>7SnQwo7*I~6U>i>QZEOQRG zr=hpuB~$-*6#V-R%fB4>55SW7`NP*8PVlS;(ga^J&G$m^T@L&4{oM|4<=KsUnD2un z^LT^9n%`dI`MnNn{(A}hF0f=8U%m={x5Hn7e+k;?u*%m9;QPRmoq=D1HaV>E>@@g2 z4r{)A1iabd^WXyby$=vvZ3BPYVU>q1VExV_{f+Q%Gu!$ESTgBf z2Y=FG>Awm7l*3ox<=-}kUjx4kZFgAXMXeWo3t0a9`O2rklKJ^br^mQG4L#zpA5TB( zu%F+2#^LAC<*V{whr+mJ` zuRuE;ei8mOw9DZtd;#incpv;WXt%>#;BWlFP_PFq*>(6!(Btrut-_y$`W-$Ee-wJc zVYR<~;JskE?}Xn7eb(W(e}5==1KJ1H`(A-R4?PK%O!;*N{5gl8gD*he>Tm*n3zTqp z1N<9r4+Tkw^*$@$0f*1QKM$qAlAVEn4obsI=JPY-u-<2a=YwF$a_|Xgzr%g-TcIJR zzXkrr?+pc6uw-8UfWu0^Ydn9-;n(5MLBkF!y^exMz>1I3cN=&VUNZ0Bn8ONxGtYBi zQ(iQ``Q4%5^A4*#Tmg?e{2Kf@DDUtY_$pLz_y~LgI_Pj8d3<3QG&mlgXB_tN`8J1re2zGL0k>zNFF1S}ehK<^uw*I^Rd5krvI+P;=%~Y; z@SC9$SmD3@7V8brF|cH>!>>Y<@RGd(|2$N7_&N9^P{rW_{66To!+r2up(%%zKO4Z) zV1@VAZ&UuD8L(tZuS?)By63OLuRza&B|8hh09D~7E5i>#vkvcr-wMq++yVd9uMGt? zu*@}ht#4oZjs3w@=zp^JHt=y>*J058GMMq%y0$(0a|U5{IpsAHfqZ>YQs&`lu4C_iPbIBs)@2zH%zM}>_*vT z6E$H|b${%xw#(MqhHaFD+i2_kpL6eh@6E$|B&GJ(WOq5>;l20VbIv{Y`}5s<3AhMc z0L}xi0_T92fYZP!;3TjDECFx9AOFd|Zw)y7C%tAC^Ai4V0vCY`!0W(yK)$bd4O8~j z=KmMk80fAIA1h{=zz=CRZ;au#})0A`AHGgVnIy?rC>_4W^ry~-D((KDJ=&UD`dVtW7py%O_>U+#yv~JA zjfVZ6GFL%VDdy>PoM{xmOL*gagqP|s9=xBTUyI5&qH>cSC-;jXF;O)L;cL=@^QWCG zPt8;+@_}hO%eeQCSkNKT-Kl3hM#2cw0AxgJZ2UU?_Cthl_9+~q9PTum;|C~cNJNHDSBK50%7N*m~S z3o(J6Jvm>iOlExSDQo%0lQXW(=@An}dWSLLovelW1RvG7UJfJ`KJ4jXxOK_MxQjV@#cjVh7|vb*+njGBmkR(d#y2<;|ne zk_+JESr6olFRK*749lJ`^YUC6N7W~T8!-~bjICRIa5JF=2Nd6-yL;v&oX-Ak+aTKv z)LBav?ugZ$imWT_xPJ>(}}z&NxSZ_ z@(_abMQ9^Ef;0g>jU{WuO>pvERM=s4%E1C&7@Q4yGN zd>WB6WQgeC^HlwD4>y;zP+eOBeP?VoHJLxDRWp9Q)JZcMtTC<)$(>7%E zVRJmC7;8FRLD~#0g=}I*`}nPm^05W^T8=N_ic^G3zs_BZ7AJbRHe#YWyD(P?DhoXH zD#<|~DF|)r_;P|wwT*{=f=9n2FX*uv^eoCytXe{SThRh}b(9>Mt8o^&F<*%LA)6-E zv)X%VUFWTL);gJLw^6oXIeV8j$MRsiWs2OEF>+f53CpqS+kGW@yt7)9>uAzAJr5sQ$=%X<^8&pz5j#%nHf1eFI2QS|CUU=$Q6=jPRMuW_$-RQ`VczoOB-vJkV!8yVsUA95y z{a7wmu7x|B5{h3a-|NdTgSN)Pb)hdQiXRRx+dFtAJ{h#%u=2f?8Orn8Ea;cQ#xL(OG3*y zS>!HOisATs*uQnH1u599wUSr_JZ9jpHgy^ky@!;yN{1nhj>z$Ml8c>ZW~N2HJEIoJ zLkV=4#f2pvk}c8%xROzxoqY5WeMteY)%0@Z1+oj?oRC~k$P5z^y3n4W3Cm#=p1jw12-abb+1&Y%}cpyrg1kNyR@LU)0>Y)j|3fqkz(D6GDJz9j!DqW zYhp+aN}@FJ4RwAk2YAJSC7{iC?pPHBsH%z1-L+c;%HeKA#ZW_`byCc$J_Q^ zTFui?hSWXnmfZMF82+Nt{TSYIVmeZ2jJOxEq^aHw~l@}S&T-6gZ`m>cnqF_sbh80e;85@VAa!vEP zTjjEGR5{_ie{yE2T-qwhty1NEr6#$&-9l(~wZQj};c%Jt73unmEc7+d0b1!Y)f*@C z2K*2weWRVh+vZP-A+d1E2ey1nGmMz58pbb2{WRVa*s(%bEhHSNZebiWPh3jir^@O$ z(oKWNHZMws`@$b4mX8yWcHcAGTNzwjWPMVv@pZ%KCbx@o*iL#{jgU*=)2 zIvq(uE=RYQwL4`+Paz4z^n)i?R;T4+C@;$wc*h&I7yf03FwfAdW+yQ4+UGi=xJ7P> zTg~;#o-Uq1{^5{X0c_($BukdtGzl#QGUVo|6Nn3GYSYUNof1lEVVywyYK5A(LYl>y z`uqapUr$n_DTw=vRNq_FqU;R$eIC?Y+2{KVed(e(4QrZ)-p{9D&C)gI$iep|3<%=$LVZ<+m6XPp_S&@f9zUTrH1vh?0AiIrQ>Zqe6nl@9yNJagBXsHfgJ}sf;)>3>XA0WhD36;* zK<}p)!pp5sk2>=aXYR0J_=N$tgk@=YXE&K|I_4^CIUchy@!gb=HjU~%uf}P1(!IAu z{blYS7C~)s{99bsPv}SD??~8e2+MC%C4kntZT0bs$8mm<7pD<-G+%V}1zZ=a2^Gnk zfJ=zV^{wMoR>#0|SysW@BN}RyTf-24sb9Hzy|^6UvQmW4+33&1F|sQ+TU|?|ePKy= z474lsi+_YG^@CnYJ2@%)O>2s*h1R#~XpE_fEp?0@W9uEVZ{unwIXssNoWJU$JpiTcx6`f5%sN8_av{`Z%Sm!IYSCr8?Nv zVR}#&xEhTr%M9}D&hZ(xICQl(R3IE@ zHh%I{fvgH|q2Ptq;&_AAxcM^IxGELXAzdJlbacb^Xj~hMxQyW9<5YkDmrG0AHv2kk z!}ndEu_1+BU#y;_)sIAsV?$I{G-su*9_L=Nunlm1kLafUGSG88GRRk)BObCV*lxsa zsVBK0)6?rVg&!Qi>wB3oH(?m9bKBUAjMweB+-(KOD4ntBbU0Lp)d+$$Bs+G;Jsgdn zEwdlg+ftm&%h4Ab+*+qt7xa~mV17~UT8a2^%ta)4{ zDL5WZLs*p-D1t9ER$__$n`H8JK0u0Kuq%QAuW*Fk&3QEettpL*Lf)iyy(sIKXlg77SSqxnUu&bMODTnF}k=t8Ky)+!?b#6 zTciE3Ehtj;#5=C0##?#p@`CM$Bl;*w{Zxr~*>toF3HkNnalQJQz1ibB5OB*Dak+f_ zn%V@1^Ezz{tqvN8rn2RSmQtu~FHW?I_8n$)qpQ*tqKFzzNQ`5A}6TCY(<@L7n z7S9{bucU?1eNl<4tVK(A5N<0Ow>+I5W*A>qyzL$)EoR9UBJ><5NFSbU?rkxV2ujBz z;}tzs5aZGTXjU9UKAUOt^xu%Che5Q81jKER;Q&os*Qc*k^$yaA#Z;xcSYll)MmrB zHEysG(WW*TuFbH-`|MkfdfoG|YcPV%vT5_!&aK)N*mvA~8-n_w{=R_;VoG~Duea|n zHrE#_5BX+X2OeP)W87R@$F(9q@8{>6C9j&eim|LTeje``{WwS$xRB$`?r07tA=|4r zwF7r^RcN(ivODi#{I*fxn`uQR2IkFXMZN5+M*h$yWHQHq$1sKdXJ2s2x$RFnK+5Yom+ zrI_;$7(|^ zlFGos+QR8lY~1gfdx)GZB--cpPZLGgQ1e)y(W4CdzDlxe`vntyY$R3(Bn`#si*sT< zL&=*KG@xIai>g*A4?OqnPB3h0TH}y-+Hq3D;qA(&U;ni4kK6SuYma3gynbLbVlyP1 zliECq_LlwL65Xp-kZ2E>gjrw>f~jw0YuYo`{icwfFpGXa8GDFl3?qU=KX+Ji#Lne( z1;^R@yWq2SpU2+4wP7bR6RYlDab-aR@ollTG)SW1Z%C$!{)5-W!WjH?8QS22e zz8LG?e^K|w>_Vb_X+6vx9k*+1T4=__>p4^QVx7a9i!^##2ke;N&J~?=M%G7Vt|i^-Xn9En`+B-V zOKs4}b4qPNP86Ld^B3yUM4P8&En`>~QiBm)I3>obc()*EVw=eqXXotP(IMdPmviF5 zfe~7Gm1o_Z)jCfP=@e9Ga>Jo;Ia1)xJk%ML61eobJpSENFY{1#b#k7A3gw_jmJ5}i zSwb&fm7tHSz8j&O&W9h?CEncdzF=U!v`yj?kH6rParNoRnMFN6=I;*IbLY|}BSRa8 zV4e}zgeon~>)GXZP5A&`q5PXC?FM*3+#QyD^zR`MaZ6x#5 zqugZ)Tm*OOQ(dOz9^T0X@<0vn^3S*9|8eWie*)RgE^oei8Zj>;W7xjtDc5{E`y*<{ z8NNSHd6|_35c@W>KI6Q5xAZ((QDhXzo5RQ1`q0uGqw;AiJ+f4!I){<$C_-+7uhe+m zTtrA%^7DC|8Xm-}!(+ZGHPT%LWR46T8$>MS|*t4i{Nq zo|d94&w$BjM&3b|xKHvv0fnAiqy|+Kt?iGaGsnjtrd^}qp&*FK#Q$O8b9QU)TvAgm zd=@`$E8O`gwjK#^$Sx$(zG_uom>|7R_fMt+U?yM{wVtr0h5rqn$t}d@$iYl zvKJTIe#gteps z^m9&$la9C2r^6~!$4f}m;_s#?64o|%FeaL1$vK#rS&n%5(T?h&^8G|dYowbj5%#*k z?eb}6_D9j?4T=9Z-(U7Yzvc4ZZpn9B@_m+ko3)t&D+^@t3+5%?d|vu7T@cVE%BGXv z(yq@6@kTMLBQWFF!_lyY-r%n3Zb!zWI)9guf~zxHbxC}Fx6u)#tA^O%y-gpuk;7GCE-XHzt_VE7bQ%|&;bC2N$1?$!rkJNkRgK>z6IKsRkv zuCtGaAq#q^zI`s%^yo$W1)kWp^ww?dQa>fX^<4pJ(8+y&AEMwVScssfV`HmC7b~-J z-3*)O=0f&b^cik#>uKlW-m-%Miqczph;~x$>|~WZ$PW+EO)$>m8;YZq>hX%4BhYp? z(Ca&WyBs_m@bO>hr`LF9`N?&j&3-Z_4Da>~{OdP^M8m!*E%9oiVK`}@$gyMbE|!!R z=4AYNs~-4vh&Cj!*He$#7I2VxO1L2~Hdh>^Te_UT4td7)4CamFHP8ixH>G z>~tr-EoFrnQ#xIb>{!OdnPJvryJTf?SU=L#qA2H1L%hS-v(k1z5vUkDr;&}mAPUU& z)my<(5jZ6n^D-QmwmXBgxwi0Y)9rY6yK{iMWu3;g=eNq2FJFf5p|9=X?ui!eY2YVy zH2J#?nyW&CM;6WP(7X-J+UwBV0nMcw(5!*x4QQk@%nIvHXwKh2&Rx*FaswKf4RRjFg|cXVj4B#a0qO-(Ne%|~nG%qFO1WI9yH|4IG)6m=r zUgY2m!|-8A+0r*2Vl+MsZ$1Fc^D#M)nn3>J7wG?1zKr8<^m`6D@{=}Ae$V3mYhrQk zdGT+zcN__N7WZwqrR|bm3HR;o+z;#AhjHJ5TiPV~jpAO@&U*sRJ%Ia8+|t&_uM78G z?e>l%aqq!>H*RS|&b)I*5&V4`bdvQyhm){25>)Vaq zdnE3)xbMR)byS8awwn+#ka&bwz$J;r@6#b=0{}C??+7I|6%Y_KIL~9_eU_LEXptWzC<2>X-}k#$#3=h4ZIF8 zFf=G7Yq)^Do11j_c65+v#Wp1y7LFs9PB1Rgl~U`nz=5aD+~?|k~qVKT*nCf@&ZuHug3j(z5xy`L)vl?iG+|0A-lb${CnZC>)iF#>#kTsm2#c7gSJ66SM>N+}2VQ1ebsqE~U(q5LNwzF%Bt6ftY zc`o&Djcxtdwon-DFYppmnXQ4?7MJ;gojvHg08EtS1x#Ht%h^vVg8iHX3gn;*YlH)w z;$RLvB%hdcl^16w1j)~CE9l@;y!qhq zb1PzXHUzoNBq92yVs~q8)vm3!HtYtH-$@Zz`S2-|<+g zUsvDQa4gj#*#n0P{lncu9X;t`_YNQE?e56MLkxL`_vR1wJ(bRPuw(G4!q}m~(I)RG zErvQedONyDQ+0i6XtXfW(S2wzrf@tRNvMM{#!w%UcR1z|;wj8ejy=`8KaJ;*sL^q7 zFwL*0b1a@)p}g*nYS17aRN#1iG=pByLuF&s#WvJue zaBj3I`J-|`P_bym@SS5r-SOHP(=So1LLH?1=W`>EM5;&fq`dX?b`N$&o*^IYUhm-O z=9l!xw}J+TfTu7kum7Es7@u%o9lA4}Lc&%v?Wf#L2% zjg9HJfB0aWGnDz%VDDg}(uRJC2#5H+y>tz^^zu%;Qp=gmt5~biq}$%>wvAFJo10tm zSv!Q$dXZ1jmV=Iosm1Z)_4|p@;hc68hQ8T%BF+7?^w`v|9{PY-@<(M#%SNH2Q#y&J zx*6%RSPS+q9y?Yqu2yMP--SZM-D7!G3Y~@qd&csj(8GH|tLXX^{ZMX9!+Zi=BqN{L zS1*tAG1X-KSWr23jOo?nVsU=YcJ+g%cPx`cytLd59vmC&d7^c0&vt8*{O~xWM`-XG zzt+|{#j67m=xLL}_QcXa+VmAar)SSZy|&nx4W<_4_MXM5Me=H&g-* z&*m2=r|RWxoH<=yJjRu{%Y2m42wIOWa+GD)b~Sc97A#H%(?q*DuJ1n>hG&`(VVsXn zEuPRc^r<0naPbcPY}A|M?IJ+b6LFrXP%@Xf`bvij!Q>QQk)GHR>}stpP6a2%kJZ!T za1(6FJhVv^=2)b+CS7do6wfa^NRk}8IlXs0wn}l$XHmwde}?W&tjTm29i?)orMve_ zO?MgO?Rd-;xkMbUQ{G(P^+5}q6mEXDj`?`MkKkOvi^?5w6|5J;FsiW{aEt<=}?fhcp zC?>eV*}!9IDy-IFHL0o*rW3*Y1ZvVt`9jqaZBjVk&;)8upW&liE^`d^dh1J5{Ol07id3sJSO(wME%4w zi^rxGdtHa!t?Frw`|7sheTcA; z3G)V>8C&^k5YQkKED^q@!>GGz6sqx^8%Tr&ijZYV+zBoVi zRi6c}j^3C&D)&zf_vE|BbbR!L%9GJcgwnKdZOUYQiu)VTqM%y%Qq|nHBo-rxhKoZd z*XB@Rr4lTUSB?dXCph#Rj8~7>YkaxQe=-{M5wZ2*CRxJr6IYzRTgL`*T)b}B01L&+ z2`(R1)w1HVYJtIKjgQxL%US+Ey_{u;NS3o&MmbY_RykvW*<8+Ck&2-4c8)!t#+ zyY>@K$GE!8M}8Ul_{D=Jow}wMDg7N2Od6z!_!8p#^HtueQCR;9+wSy@hrufwOuSEZ)K z*L7))MOsyE@XPaI<2Xl;_F)^@N77jI(@_G}S`I7-`4mlvvJ zN?tg8dS0+7GTa@{i`?{yDxcnsHv)~u;#B%b#*Bo znd0<`MC`(HHonYvgfgZHt3K)F>Q?AyW7u4`+#*;kU#BN%lP4#GXDa0)S(+?ktG&ar z<-#kD7b4!YFk=hiQMes;xOQlKYP>wYTnTz^IKIpvb?SuW<z0AD~>^pSh`mxqLdfB*In>w<&;HMt1h%n z>76}+wQG)H$CDnH_rV^<)0Lg&@yUr=6pb(r9`91Wx$Ib_Br4nXsdQt3#_N} zXxb_bvfHB7B5Z`hy0Z94 zt+u=rRTP!&%dYpck!o&_oMa+(Q|+oH-~U15vYI_L9_eEz8%O-ILRwiIYx0fp z+8y(dv}vrNa%I;d<}JzZ%iB#ST+`NwuRJQ}eWibs7|j5c5lidX7E4oF3*II6>a@1o zD~UEu2Q0dY7gcxS9oIKbVzt?}Cq9aWJ2Cr!U*;4X=kdpd5_62E5saj>D&5-JGy9Sw@KHPVa!Z7qa$|8y#uByhBCl0V#%j8RA-dlbi$=0JjxLB*@pO4ox0}t-dn_#n9NP2kPBdx=H zh{R-+r|95~4tVY;XzTbtf=D6N;Fkz$KoTskT$BVM9t5SBG3vRsr9b254 zl!2v9zNqYad}{r(5s#(Suq@WI7Ud4b1&f?Am|AQsGKXLtg(aMDFdnuaH^buVr>jrL zY)|Rd=B?l`N0ap{?Vw*%ed}egY|^#IF9gNXI8t|&jyEDt({0iP5h>SPx0?=Us&cNL+#o^hl*+4U%lu8UgmpX2 zf6~y)OKX2rM|%Jj4R20A-RSY^!6Sj*KtIRg)PpBp=@vQv5qE1_Ep?ESXBd*TMg02#lzxV43c$H4sF?TP1JoH{CH%%yg1JigVQ(GKQxc#**ghyOVc(s7JNS< zY=k(&G}t{VWhI_xqC+wlB`mk(Sgx~!QkH{0$u&ru$FclmhI1{dJe=lCahjJBv&<~^okUW^wSVS4HN04hgwBL^41sCq8tuk3#Wc|ih0OBlle{%7}glzWMfg^d|tg{BBiTW_*Fm|L)@{)sp zDlNY~&t)=#+NZnmtnafCuJ2kZkmFXWw8Cb;~&A6&-AY)*ais5l?L1 z;(2yF77yz>>F@y$az*iYAF^$H%ZzCmc%dSmpu7oTBkz)>z+6gIjwyCPpu-X>RHek;vo> zknr5NEZTE2;ow|&?YWwWH)R1L{lJXn-6i3!KA^HkPm@rG)P&}yPIEwKPj1BGlBQ4U zsR+@B^A1j*M_Q%R4g9GC(&!o0bH^%tHH^E=Ep-P98Lc5Fx=hRNs-874t)-GloH_s} zX9r;7cjG*0-m$;Q`O*89E4sAm9)F~h?~TIEd!ZSR{Ihq(jnSQLrI(F%?r^>NO=!cU zgmCQsu;>+z#Qi2MI9I)Pel60cNB%D)$ajf_xW%lzH0}bG&=d8^tzT3N*jU$m4?(3MQ9T~#1?ql`p^t@jM)puWAdL?&FOzR?X zO73Kc&bsY!qxiBG%SR4P?E`DK>>1odI>F1w9S38~t!{mu;BUZhd7}k((O1{+7vj87 z-OQr4@=814+u7(m1aezdr12}lA9#To`Cf)B2aBE}y49^4i#se^DQ#HBqONI`^;eOl z>#FZVMpMu1`01Lx4$%sq+-1GY{b%ej63$JmmYG(!z7>yCw0x8@Ig!OHi39)n@U!dJ z2U{?T>vGewVbT>L(ao;qn4X34XBY?YAw!W*9o)kE@_0>;o9P*wZ~@2Mcy)$5u#*cY zdlrv95nDP@y;Bx0giQQ0`Rx=x+h3>2+)Hyzr0_klerQ7v7#rhoC-V3VCxq;`H@a~` z(s4;1lj7+U zJf*Fa!!ziVZ(Ib=)qZjc_gHS<-&W zb<|;hElB5ZZR5=?0HB`^2{3(GmDwZX5PA-`CXAoAwT7OIX=MAUc_NPPZi#^@Ic$c9 zz-@mce9qy+8NcbtJ$H^X`xbc`KJ#I*Cug&vKb9NJD3KGUcXCE&TKSee_AzhxWt7NI ze!vytR)0uEp2-JDl6TRh1Ut2@Ax)g%#jX^dA5I)6|fJB#RrxQy^Hy!hz>bIUIWu_cVe;bslT<#_y%u*K^jv$eJSOyL<0?kNtt z3^%Ra9fB3PGzQDdvwnEk>IRCfZeZ5hN(FEO66`v#!VCvWt*xbm1rK*n6VS z+fDc-h~V|}4mGuoCQkI5luz!BY`ns1+$X$Z%A%(6C%V-y`uyAIX=;!<6T);SdySrS z6}SB?ns*}nx_^)Hrw>Jz|7>0DgPq2X(3zuzpVng!PeL(qR#Qf^;+9XA#nd>ms^mX?HL^n~I_NI9Go@6^E~en!&Yy{P(r8!pQ)V#}S4%+e zaq(*yM2@a0Tg)MUjR1E4IWc(6G%@`r;m$6f zb7NIJR}-kIZe3O6Zh!eKUJ(3l-JN6a&atUs|CcKRZwK7ffohNY--#m*-p})h-yI&A zFoniL!Yg!oIbyDHSZ^2EV)wteU2tA^u_yfm7yrfmW4-Wv3VrN(3;T^_ImzTKoUEdQdmB$zKgwy)_pET#5X*WlHvdgSg zyUnO`U&Vdq2RqG+&Yk}$-YTB&Hg7xkdE7$3X&^@Fx`N|P_vc`3Y!W_xRCogw|W;(ObK zTm9;BnyVz!spR*w9D*B&X%E3qt4S ze5Z~)1kl(fNuj@|<*8=~j#svL3LgjiOgLAP7Z+yHrdX@-1cAGMf1$ySo` z6#6Ux$-_PW)dt_g)Tb8g>*upG4c;1v!fTWzR`UD+A4SPU>pVBmsFf#XCXqeOeJ}EG zfK~ND!gO-NM-C=Le1(1d>YR*SWsAa%foUt^o5Psi^1IFHC41vdRQJ8)%~P` zmt|RzCa-Bw5aq1~`vwFVM2QHBlGQxSxPYQAAe2MIIMl<11fzY%32ue}$Z0^|rh`E$?27mxm~xcp~U4&(?Ma zgTCNW7K`&lTr#9#-wDuSXiSj#ll$m{R>GuKu#XAEoaX7=@L>O7FSRl(@l`%CsLzzj z6!v;~qO4D&guar)tLn%Ex3134Oi&0Y@&`!MHc-A zN4dp1HxRf$7An&`s3A{lQ(_j#K)r^4p3=da=wELweFHA8;%~@B{8Fpa!hl!`jeXAk zL7rrJ5Dsk@luh}H{wN#Sr&@g-V9 z2~)GH(UfER0L4+MK2 zPgtP(PYPe(5NQtf1IVL3tRtUdk*ZdfT)e3zNH{(YvUtf5}U}-_)g5sm?CE; z3bwKuo@Ostc4MZ>#*}&gLAud7-rJRi_$ap=@$S7T%*;_~c?+Umoh^bd@U$(@08I%^ zxz3q2j{D5cE+1PE3%_}2>(oKnkgkm{&zB)AP%*}7>(swqt;{S*m?hJpZ+^Si*YTW% zuAwiNql=@ja~7zAFp++f<+KqmrpbEY3XrWFbzc)!*B@!?c{N?C5QofY>v#`)t0J8Q zSBJFpp!-mMw4WE&x(By2GJ#}UwM2>%PoQ3`nd0%8()=`bp0$-U7QY%5zCrqEf(qSo zP2P()vkN6nD=Hpo%Q-FlCTgU^!knp0i4@XmqHaj4f;624?9ANE zyqRRYG)I03PlHUZA?VgVxZMYT#f`VlKhv$_!}pv!INEJwJlGZ3@!5)VKkwX^o%>Da zZlCSe@#OsvSo(9gg}>z7Epy!_V7&RVbFbi*@#nkFeHFLR@A&$$mfcT3I6f62L5aLf4j9p}F6{C940;T^N#J?q@2Zr!gtcMZ4juWz;V z7jcXJqt4ylup$S! z=bZZm=WaP}<-O(HE6%-Xv*o{vTheRRx${d_-Yd?1*||C4*Vw^uxV6+O&smv0UwguQ zsjIsuw|`(X$n(}iu;WXD-=r-gZw|xX@-yAW{6x2D2hIa|pzUv90>Mvqn^R}-2imb; z1cIOHHZ|a?m@nb~H@nScOatV98oJ-^FzvsCANG;H+(_T<-NjNV*sLu>xvp)!dqrxF zo^`s|m=2CI7@X%OMQM}cJPn@rDZ=7#<$94GIwmP5CoUpE@1=yY^*#5P7*B8U5jo?f zt-)~hINiVKDMp#&dNXBt|6BZ8dFQPp6f!t22RsWuuk)JWp{GZ7%ZMjvZQI50W~Bd6 zcavMwC6ErgZP)CQ_HT_+L()PgGkYF-(j58gDe^x zTDR_KE0NePZ9|JBa{p-ezLDLD{Fo(!!mygiZ}l_0<$EN2&v#S1q!X{ze$ASfzxHGQ zt^9uJYkOn{%sNNgjz=Ed`Q^vHch^^n;}gtPg)YM7Iyz~K1ZVkv_G_Dkj}{?#Rv<9^ z`!kj1eLvrCPXBMc=6PTRr~yZSJkSno2JQ!1fcHqJcY!OwW#AHU5x4-H2VMov0WSfk zfm6UqUJpd{~_$ykoLVBm(D{`t6O8fi>}%~XLUZEuxN zar%H6Q;td%305XU!_oe&okKl6<|OUT)qg|V@O#vA+HmvFsMo(u-*dRf1lZ5Njo<%H zeg7@mc-%*TQ$QZtBf#YkcbVW{U`(8(`DL#JWvxr)+ylPAELuQCEPzk24)LTLx*$!G-u9<9{&>j@1pB__+6r%`~&>p zYd1Znr!aDG-@fkQUPSa1`a6fZx-s_;?j0O@dXO^MQ|RdLRdbBDtsccK=1$Ck{?X9^ zxP(SG5Ma~Jx-7b_nPDWv zH#2b2!Esjq$|Y)cXO-ay8Qvv9b@R4iu_7w)J|Z(=9Z?1G#jUw=U1qKN_Gxi8XlQ9+ zse>Vn2n0XFf~cKT$I;AN?Mh3%EH5tVDxJuUak8dm+mK+gAjNif!mZEzn)nNsL60ALmRS`wCE7 zL*2No$8-+u>&kIB{Z=~Kbo6EQMs4u)LJ+GGe(=vahkdqJmsOGk%eru7pPVjLSxc3! zw!Fmfl>1!9Ck>M!T{O9s7d9_soW7I(scWWDn=MY1Wv4>ggPxi4Y$ zm@f?U(n`>WiM@ZM&^tV|KOedWo88e+%F*i(%i8m~uCDGbYai?G932|=_>mDWuXCV( zaIXuiV_>M$+g+flLx+-E-qG#@qMYJ~yLF7E_Q9cnA=*T>cMj#{;~=%u;xWpxcJ#sO z@FOTBuBgw-YzO?izp_ZlIBn7m&UVSO@b%&ZyMa1BdmrsdtP6E(3F&%-O@|v7>dw!c zuEF{|3#QA(k}U2@O$qzkMxy_Kx?d6WV45F=^(yFfUy_He#HxJAPIKE{ifZR7NPj04;8s{w86I?Ng5 zp22<*Xdh!g8))CrZUX#j6ZDht)EM_&zNdqYF#!7+;?R!F+7a-;hAmH;mH*gj+Mh<& zEMd$*bFI@H25;sF2Y5;BjC;>uKL?xw)@j-WZX>`BVPwgD#8xhPgax;bVs%D_@5XO7%2|OrHw=`e48Tl_v;N!#?yM?KZ8*i)IJr_MrP^vC4EN7m{e#~rDFCHk%W)45+ zWt>RU6;rs#-3H6hxV2x?8H)?{kJ)JUd2e(f= zq0#=p$x)(Cnh)OM9o`r64&216|<8ay+5xblf*YbcFZ7s7(TEck6GO zPWX??V1WC6i*7C`8{gw)Iq|~c9lZhj-^C$@S=#Cpk4wt9o6ihwXS8N=m zGqn94vu9n{-%Y)9{iAKorMonPI%U_ms9XEbXy|E1i&LE7U@aQo&XN7$fVHb!pIIcP zqc%RuYtI7-W;gTUs(g&k87MYx@U_XsaUpjiY@xzAjOtW{r3OwdEG*5;&aefp^AN66 zA^BYT>Z;ymT@4R(<9rKKb1Ry|6Rb~wloJn~#foMDxz=#Y7k&{y&u=s{wd&YL;&0az zJgJ@xDwTD6He9afPUTWC%RGlIn_!&b1DQWjWlKkQMkLg6_Hrm0(tus1554$p=BBK- zocYZTbN+`I8~hx7@sD%V6M}31UDl_-2Y-V;_%AW; z`0Mcf1mlpujSTRkTc2c)1OIRJn5&rQ-(+nEd;4EyOu+tB9#{bapbcpM(H?UKX!|DP zfEDJ>m@D58|8tB};Jf%Ty#E#B1nez8(qmpkzMRuDudy}-yzShloSV8*FU&Qj3dP!t zY)brD>*xNo`ZXrLWv;~0KJ1If7OL}KHRg-6@;~O3GmEuqL-579ns{)AiM=-VGPk!j zo?!GeFhyHd zU~#@_UIZ2=rNz+wJsaeFaSFL2o0|3b=P?QDRzACVr@3Rzop;^6_MUb3uD|blKGbr1 z)^EedZohrwC*r;zz5Vu&$KCJS{^8p{^1gZgvoqXwI|V|2pERH1@6+Mm{pK^~v;2Kd z{{r&>f1i*2eZg!pt>%m7L9^LBWWL1T!<-`B%HKBq+itd-HvV?FzemiY{O#oL%ltiN zzL&pU{C&mj=I^Wg?cq<(GK)%b{M`PnQS){_1GvLsylMRfZ~yL8|2w$bKzwfJFERxu z7%Rm}uv~(>P2n~T*Pf=n1N&M|$9}=cH0XA77ysW4tTA_@vHk5fA2Ka!z1MV-3J+u7 zWOCRa#CDHaZ#vZX^Q2QdDYezPCAGfCd`#;XNAO zM$HS!3CV@WX)V5HCW-mIDo@J6HcCN{={0?v&RlN}n)}RNa($CAE2P?r{kv0bfB0Rq z@*W_6-($Mvgt6K`MObF#)4=_NX;wZbFAXwnBcWFK3vY-+FYke_Kg;!LBEDMA~|FdAfnnMGCHbNL>t~S4Ip&{1r{D6;Eqc za_Ub>h~XkTc^%@v>*D_}FfV`iAAh&g{w*hn3}jk0_PW%?tSYxw&b z;eLd&{~?Xbed;5zmN;)fuSx!w7~VzMJV1HbNC{l8^!HKIq?X4J z$gogO88eAIjPjxEvAAUF(USK@L6l!2*oU0EdOU>rIY-0q&<#}c#OwZh&Bcm|+Hi2n?ZWC?|p6nkD zKNu)iWOq+?F72;}DNKBWlGFEm{2+7AI%mnN+}J!9aK;Oe*(Vm}GG)%@S1aozGkAD_ ziB4I+CWvcWs!r$!4^{;^(ywd{)4ikzR^i_rhz2r`6PqlBin+%JD(k($f=zik2og(l zQKp<%ArKYHr3a8B>Hqudd(9p9_2RPbuWslyUjxMN%OB}AUjf8^$47h3-N3CMWq#G) zX4+Ewx7u$trjPdPdVkNE)ql!N{1-O0e(}N04}Iz3EnBy3kB(UG{_38`pZHpPPET6)_VquxcVOS(P@We)M)!|B zec<4suOI%#_Z5!V)0tD#GtV5IovT!9$Lfvwg~j7b%O}41?4SGdf58lN7DoH`b&EN; zpEGo_NRNHr5KqhGxX}@NCtJj_#H{wAfq~p8F7P=%g*1h2TbT3k9i;rnPx4pHpLxLM z?;PeLAozcW`5zqK(;fYSrTdxB_nJQf1mD}*YxV+PVj3szpKj|lKMTlD+`onWcbuEq z#9fAx)ne|r%iMK)%bM=)?mOl80Gz9rucBBdug(?uw9XE|ad*_KM_Ep* z&D6^554h6;vojU>sA?FITlKV}o+xcBvyd*EK>n;FV=?_M2wfXB&T_CI%s7$(Sc&ff zC(1g`iih6MgB%RGSZ;jgLDYfSmPCr(dD}(Xgi85 z*Sm8*`Ep%9Bi2-?%xFGH*yT!fVQSi@ljs-9lp`Cg-PdP06w0ewQErRQ?9I(^EC$tN z^j;=UBrMGhzT2GOARk4Fac-IGwe2}!pRqZppC)4X z($UXqXuZBrlP`w-IeiA_@`;z|rs?NY3*D+4l4D74hJ5a7LC3*|UdR+4udXRS+}7q- zVi14+&)=5MVXn{;V z%g`JQVcW-__?2TLf{i9t+h|7plxkg`@86l+$VxMON*N1)&#uD*AZ2DlvgwojXnC8) zLv-9FI#Ooj2qjapnF`b5;;iiSa8#tGWEz+66*|#7UIicxy{Rf;Ot8gKc^u zT9-!UCBAc)ax5tm&u!9iho;X0Av&5lT1~!h<_HygT(Y&L1uBx6oi2_^j`l)+-?~)= zNWLp_#|cqJ%88$AlY!JWK7Ew7kvP-9F#}$xEaizYv}qcq()t#+p@}23k4T>Cp#j-Y(USmL^f*R9r{vPm)zfZiKOb1Pj@lj0w?`H# z`>K`Eh4Rzo(&+R;Pkm-Y&mTNltn`$}_Z928T76$}`N@UKlMA!Cg{hHpZD?YCu)5e) zo{%D{_Z z3-y_K_NFBZ^`x9zx3X(D*NM=&j0jQSZ#F`R$czw$ZFPju+4tF@=59qPOmbo;`8HSY zHOBz?ty{zQOgr0(V!!ln`c3yp-duF%F228yx-Kw;Y zDD895bnkyEGj8h`2)FIB>F})3j_fn@nESd9tdhIl(#GP}VP>I~b2mvH?q(yQZK6$< z!%YdAuI`*UjL9jSRkZh5TDB>uu=1iZ`j;x|xXK6Lx+JtswFf(rJEp1F+cA?p&jmDE!Wb< z|dQ1>oy{{Dc^GDDzy2OxZQI+3A7 zrmxkv%e(My z`R?J>I&6VGf*!jw`|As8?PSs*lfCYVg<^^M0doO5 zb4C{6n4ie=BJ2yyR_DfNG+)NbmGX&&vfh`${E%@Z{Rd0^HBJG}P|`-27EA}Z$vSx9 z&GWM29JYalr7~ZjEy#O)omKjwU|12+O2EuShK#RW$kCyzWfgPIg&FkVfJb7X9_F2WrV`CgPV=!X#j3a`IpEyyLtmT}l73L|} z>G7(V3;$mFk^SZsXP$B93u@-f^O%DJoE=klr+F6hP+y-}QnTOGFgyE3%wdP`bMBqa zKT!9mX~7gZ@BKR)-c>bo=CYat=1ny_&3QFD%qwd4o0rsl(wtWF5Z^Nj|A;B6Icg55 z*=q*W+;7^Q*@oFO+`%`JVsa0Lngiy&tKuFp?_f$_dr8es^SYV?<`p$Z%uATvgZ<_O z%>L04a}slq@-^?wBWezsKFmDdOYX$%=F^Q$YIc|nY7TJlPw+$Lo!=L;(_B=u%bZuU z$Gog&w>hn5uX#?*J~OZ8K2uV2(B#$RjJBFNvqjBA=6*GY&0010n`@Nk?vaD$Z8gWt zo0ubGJ?0I}uI>@72i>gENx7GNKkrN~RAW3(xu;wwHw9RMeQF#oa-;Vo67I{f_m5&c)tm4?`>6za8aKU;#^8C*=66G{dG+tsmzYZ;_j%ma#WveJ;X{SC7)aG|}Op zJrMS-K0jybl6%rRNDD9bIZ1yKdVBY5tV;`VGZWJs3uLj8UcvFPLrtrQdXw6RL~@+F zNshyjP4prW&$x7D5<{oeRw;*(J%%U39v`;FvJ3CpV((|$-Keegcxgwy{TX_0>7>1z z71Gd7X`2}z=kZ3;$NNj!@^%zvaVhd65kf!Lu4;aj7Pz}^YZyIkgC$evqh2(`$toI0 zK+(ds)k4>hweT6fb7FQP?YH2h?RQPT$B79{n=oOK;X~C7(js7t*DaR)Aue!{gEhp7 zeW){Ua=>6%_6EbUC-cM~`!VM8fc(V$D?i?Aeii8J+dVh8TbmG5;Tcv*Qa-4KlUB>>reqDPnf1Iih$;r+a_4*L(;N`&rDFfj($H z=x_d)_nLt7F^}EGy6s5U$lhP??yao*Cr105yN4wMq}>Mwyjpud3|l=$xuzv-#eZM zFX6~9jyHeUZ?3%CZ#~@qw_|PuAO8veCUCE0$mz?Fb0i^0_-Dbrl_BR;hMcnrIl})6 zxV7J(9*NFc4f#3{wO_tc7c!ogue@1DMQY5hMbjz9N~W++^GyX=Q8A6 zNXQZXH^H6HkaI0VPRk!R$4mI{2X`eyPP_P}l%E3$Il^B8xA6zk^Xp`WoHGeI!v8Y3 zfebkpGvr)J$PxZ`!Odg(U%XyCpCP~P8gT&PKdCQ$37qhcf_oWL{N)#yzl2|!tUI7P zm5?Pe&VUPk(CWG-A!`79THSsNp4StyM3;9HIN>+{7j@|`r_0%dUs@jT0U!Sfe;>HE z3^}tIa-K`b5&l!)&i$2ieO}3s^F~6B@LvM=c7~kyGUROd56$rs{s7#Ozm{HBx)St~ z7l#u#;Vpq%!A#4mllUd&NM4;u$PxaR!Cg3$F6Ux~oGS@A!v8L~SAQm5&c;7U&+|6$ z@t^ST5!wtnM>6CrCFBVIbKqLert5PyL(chx9N~Wh-05$n%ejhQS~{|{IjLI(YF$eK-rA!Yx?1Wx$Rf;;ErOF4|Usc$6c zMYp#TIN^NRxIO+2!tiar$FtOK*8J*|?#z0# z-p>)nEHDb}0pdTA`J%&l`6A~WxOh16ba)fLv^15z<(-6lk?|h5c4T^;ZNAKax3UE1+W$`M@-B;*Kx30(WHrKinF{E}%ba?T{=2>;9APGkD= z5RcPE{H|A??nLGlCzI7L{fR7d8}%YXw@vt^>9z-a{3rZ<;MV_odRdyqFKf*6Ttb$} zcmdqTx1uoO@q9HwFL`${ffL?K;PzmqmB;t+OUjWn-*9^rro>P918_$$#b17LUApi~ zlO=WJa6*>Im<9J-hEAvOOVjCWLXPmi0`6>voJ$#Ut|sIN|9jxx$dD7<#I;;8s-9`=rB*UmX7u__VM`k+lcd1o)rSKM8v_h7&)L@vNg4xBm(KnFOuqaTZ+5 zmGrcG1HZJidpjXV_^*Q7nIUJxUFmYRfRF!#e;2sJ8FCJ1$eB;b5&ji$D;aWL%8>I~ zLXPlX0QXXcoOd$hthu{6Uc%o3?gFO&#q)h{5oFEZXt;Dq-raCABNa{xF?aj=AI|npHClCUP4Az7&30Snh3+oJM#zW zb!#(WrPZx=@bRDU4}g0eGcDdV{L*AeyiX=%iHy_Wu3*ZKqasadyW!m^?0A~Dflmwj z9b~-;ycP?`r}>(7kt_*IWNZK@^zon2?@G{$9_`@H{BcAZ*Qb=A7a7kcaKif>xRyUj zmvJ^hFEY+2aKd{5+?EU(?cdT?j{V|qDg!!K>@-ItIf{G;Gr&ycf} zA?H*=j_|(-?%fPI=QHG7O2`rZx4{M9O^?^w_37~nz{h{WzXe=ZhMatcoauxd;hzUL zn<3|PhMaQ=Il})MxYL;a7cYC46ZDej*Ah78y^r={-QLu3@+SP!@_Y~Y_)qxzz@5#I zGn*mjxr7|yKLzgX3^}i4$ay0nNBA#++jwt!yxz-@v*CN1<0bq7xULL2UHGM?&*6j| z;hzR~GDFVu8FF4q$PxZ?;NHlP^Ja#ecM@`h{~EabhtkvM{tu9j(mp?%kR$vj!M&Iv=j9AJuP5XP|3z@GX2^LrL(ck^=6DJJMsROt$k~HmTD(RR za)kc~xT_g*p39K)VnUAap9QzRB|X31$dL1PLXPlX1-Cgv&V~=C$7>7t_)qwEfxG(Y zbbSuvmsT(46LN%q1zd1{x}29X%keGZ}JT%#ia+LXPmC2X_fm#*y-i_knNYcfIx1_nf@7mR04nY+!u- zt9EQH__(|cpWVx+m-ZLO55SWQYbUt0utm>%fD-=lTd)5!zDM@+;PRN_FTZ#g=kR;K z;jBZ(1sBe!O5}Vj^4|q_?Sb?%wee%=WuXmx{3rZ-z-{_`x||~!a+VTug#S5k0~vD8 zX2?08kR$wWfLqFtb2UTG+K)HKOZYc{JC`A67k+7NKt3Ty_z#1-lp$v&L(b`h9N~Wn z+?p?>r}KpjIhPZ1g#R6IyE5dod?Gzwo59C_!oL&TbcUP*8FFd~Il})exEC|zoXL>$ zYC?|izYgwvhMX%Ia?Hl&cnSY{aBDWDr*j*AY5CrlkR$w~;C5xmS;~-eDj`SsUj(=D z;dFh@XUMsfkR$wWgB#6|v-Xqe@e07lf5N{7+_M>S@)>fb6LN%q9^6YAa!zN+IhT+l z{I7w#lp*JGhMa2&Il{l@Q>62j^mN{gUs}GmgOC4&e*oOIN7Cig@Jrk8J(-Xr{4anz z^Z4FSe7qlcH9;@)x{C>%@LmGfl1ta+J^a$vbT)jtIZnbKfNR4{TUY7AFHM&8afcJK zM8+(*tG($uox(3Iea&bK&iyy(axUSQmS0yBa)kdqaBpSE3GPpqvkQFuC;VOD z*8fntKGPX;RuXcA|9Nn`GUS}gkaHm+NBG|aH=7~nT85mK&oswN`0odIHbYK3erf4^ zAR$NiOW@wlkaIFa&Y6T9;eQ$2{m-YT^TiA~R}ylB|6OpS8FDs$Ha%W#;Nw5x-vjRX z3^_+K)~7Ud@nmHbc(&gdE|21KhO?Iaf2}to>Ybyo7%PxXphtJ)L*qmzMAO zgdE{N4DN7-oRthYrxS97|0QtGXUMsbA?I>Jj_|(&?zId#EkSy`HiM7FInXL(Z!SIl})sxULL2S2E<72b$w0{OiFjWyop6FD>8u5^{up z6x^#Ba+WgWoJz7IAK_0dVhS z$f;$>Ihl|n{4appd@4P^Ud@nmF(F6z-vU?4kYhHb$7>___)qvZfqNlCPG5$cBMCXe zKMU@BhMZFwa?U2?2>&bK-pP=2DMQZHgdE|258Q?yPEY5cH9dWHfsg-$zYAP@hMegP zIV%Y{!v8$D*$g@7GUQxH$PxZG!M%_n=URrGmM=EPOZe{xcRoW-JAP^P;y^-<@Rz{7 zmm%k5hMY4AIl})kxXphhJ-;qy$hne`BmD1zD`m*p_+Wax+Q7$u!oLUHiy3l`WXM@c z$PxbMz`dCv=WK?Y^9eb^{|30VKa!q4S2N_S-P{~6;oktRD?`pM{L=D0pO7Q`hrz96 z$XUsdb2=eM_+J9I_D9p_gBKF?G9SF0zzOdaaQA1(SpQIS8i2tw6 zepz$D>4Yqiu>|f+hO8Gw)@`fjs4}m7B_T^>ybkU{hO8_2Wt}rKUuurG$Y^mmf8OF9 zaP#2AOj~2_!|!_MEsi9@@badAB0U{XL!Wh~>|8>Y$T$yfx7ByvtB zW<~u*nEvtX`Zqo)F0cyZ0;4E+fxC-3+_wF{20Yktv za1!_h;5UFPz`d{BZ8if3fK$L(;5UFPz}ml$Y@iP~3Y-Kk09Sx}e*r#VFE9<90bT_z z0oQ1ir4gf2_F9KJA2Yv}YAP+17XMhX96=3au zPnf_0@E3t^0T+NPz}j!)2lN5cz)9d+z(wFHu=X|50q6s!fgc9G1zZ6B0QmSnxZC7_ zXMt0|w}1=49|0fzACL{?fd+6AI18Ky-UaUcW&D9YU=cV8d<(b$Tmjae#~&C2UIe}k zTm-%YeEe7LHV*@Rz#?!G_!jWnz#jlD{}5gv5BxCjE5Ie-8u0KxLMAW`oCMATmw-P3 zHoi_e0$&Hd37iIA1^zkkC%~tFl`w&6;2#2)fVICy8USAhz6qQL&I6Z#KLIxWIx>MH zz!LD|z?~QFHeUd~3LF5w3A_n>2Wa`ncbi_|zXpB*_)Xv{(DFZ`J8%G40Zs$20+)c# z{RU+UmC zbHGL58W8*re!w*FL%>;GYB6fQ`R*w`m6^{-5@~2QIFwO#9}KEmo{pqoy|Ms8rEnoz}F{ zHku(ofQG;nNJ`tZ!-N@Nnqg)-GbE(ON?TM^R8&;<+o)7y%_^(tMrD<4M~xcyL!}m# zZBent%C6CmU9;cfO3n8?_ntFz=5kNlkhrye_wajo&w0=DzUR+9=iEOta}V%lU>Fz& z9tIWx&%-DmxC!V2-US>4eh54YECMf{Mf+`m*EDlqs5bZZ;M!VnMgCe&x_RC6#T=(p z!|{MaZi(P>jrD7|KEbUK(l2C-u;q7>4`^(&bwY%7W{}cKS^sZ-nNLj`-}Ly*b0q7< z^B-+ylrp4l9y$;9I$<5g5hs69;jxXqqQ3p2zT|AW(z)+O1c&8yI&h%Q{_dQlHU1$tM*JF%2OO4tiQux|(i*N$@i(I3v?`pV8cwgmnb&Ye6i#88b6;c> zj#tB(Q#j2Uj&UT{PdyrrN8udQaD3pfFKdMK3mYE$jK(Gb4nq$l$78RM{lb=G{-nls zL~v;5y-L$Z3a44anNv7D8jkU$Tpu0Oa6I6!{Uw6Sv6RtpeTu&m8cwUiDZ1LZeZ2~2 zqlPmA4(oMT$T1{EhT~B<$2A&qz)NqiM9cPToaHY6@V4C(s$!4oxcpTOvPF)$K z3~XB~%B1WRGNIJ7Q{k#MgMvFOxb%Ne!yOacaY&Y*5jGqP$22x`fIT=+tmL3THsW@hO}!4X0J%Olvs33TIKn8BsVJ zwm7#v0}jJ6!Q~kBX}EKOJFjq~8m=*s>#t!A#{&+-C4$ScCp282;%{EVX;nCd70&H7 z3&g)(aLq9;6+(XhXt^2VIAwh(Yv4<+NnXUMYf=2u&xlfXzmf;48OX^foKX#D4jhJg z!DSt$G+g7KEbg-)SwC`@G+dA1UINMbUny)j2TLlQ`)WjR$ls;m_=Vq_gx_{Z*5fu| z%eB8(V~ecpF<}3wX~tz}d9YkY&APKbv+&6_)BgnG)SXbuG5cH8fq5IMoZC1D4#T|Q zvhF?&*SJsgH>B+EsD|qi9F{$-;rN8V8pYp)hTAH*dlc@xhTAJREPLHn=XQ?>f1qUB zQl{aOV?RDJ%{&>(ep4=^+2hm)pYk|`5NDl+lyc~2O4Q|HNajB(>d&!xRN+eJX4&`W z)|W*M$D?pIR6F;BPvQ79oK|oc_6RP=NJzu&Rs0QVI3o(@h=!9)!{Si_4l;gY(aq12z<(U3(ycnJ( zjvL!Ds&LFq{3F+=9NQTUrxhG>_bC3BG~8arU&*!3?H^G%bsA0v9EM{`nF$Sd4jk6+ zHwyQlhHHGo@>>8Y*Vbbiu19d#$0s!$pYT_s_*=itx!tXTy9bg!_d=TE43gvQ?U1Y! zpLJAfe2jp@@L5Ru__DB}eZR(LN^r=Z&~O$M&YXr*^i8Ym^^o-CfnO>Rs0^-aC(K`zY%`F2+8&1tHPG!V^U)~B{-~4L4&6K!r!8h z#pr33CKP}38qT1?DZI|P55`29Ula1% zLOvkmtdPGJ@;`)p43cXqeXNCN-kY5*a5|Z^l7j-Mv_?#0Q*1t!?F}`c{M}d%_I)$DeBm zeNMn9>%cjG5OL}zm2%h~kInBUq|NaUuC!fJY@jv+ZCi!y0Z4hQ%9@<}Z$xlEt8haa zZbooe-$4y$4jk5DUh#KC!!`cd;ub*4dd_LM9>HPRh0V@w@dV@ekj}F z+;_+_L#wcnX(`XWr^1Y~|JgRmKKNo?=r@Wubwi4Oj)PuNHuH`uc}SXpoWr8bF(F5U z%m_IS$#Qs&I0`la?QH{2Go&;iNSjA2_UcjgWp}!+sdn*d!FclNt`p zO}~_C_{9TO-&4oB6UOyc-}6{3z#nx*(8<91O?@xdUZ0Yuaz>PTg*2Ru!s*v==#yni z-%l8`6miylQt?Ya3rd+wN}lvfj#p`)rzO{Rl~bf}Dm5Ix!s*m-5(;NP z!;$38I!imcNT2<(NOJaHM~7y@EqO3mT4J z;jFvKxla<{$RNus({KmDW!WDUetFD78t$0zI}XV@W<>fJB-g$vk)DC%T0JMy^N{Bv zy&%$ykmkE`rmT7vKt2okMIyZ(^4UmxM7jj>IY@g&x(xEUNc%*(2J(4G`$f71^7%-& zigYLB3z1HUbPwc(NcW0#KjcM74??oPUd*_z55Qr6eNAxLUqic`kHeJUn0=+;EGV4g z8cxvzVhjoSN+B;3a+8qNkgPwS6&Bp=T&GsSVV#;aoL=GY-Ga+D_Gq{xioZh|PDbGz z({Sb#&It|2_@UK4*1hN!=k|HPVJHz?)_tRf>jQ_!a+|_!)o@z{hh-0FIK2vIOv7Q_ z7)C_dRx0=Zk-L|#GbiAS$CYzz8gbTPN%7A%WR$W?1I~Rjr*Qllj`5(?Cj~+lLCUhz z8XK?RuwI8X9KZ0_BDg#*lNxS9@wceq41&WjtoYl|>fG)z#b1qvx zdlYU+!yOddVMx~ZUSY%f4r*+?fqoKg+P_?KMU{Thx>;iNSj4>$~$2rlR8 zu!cLQ)a$5*)2fs?ui^A6oWc(0K46`=_Bu)GWN15ReFs&h<4T(2l<=brwu|8Srmht_ z&L=*%^osn1QWuszrquI@k_QtrkTa!lW;C1yg|npL6g`wXo}NzUKJkLXP$sx+Po;+I z2Z!~$N#Q0m+=Sq;Uk++Gg9<03;fyJq;~LJC!YPP2w{t<^lxjFd4~z2)q+A#M8m?Dx z*uDcAj$h%7XgFbob5z6G2M)tq1((NYUc((y{H?pyxi9V&{=NXo`cFX8=XZoH$8VX& zc2;m`mv-PlZT=>hl4FIE-#cxcvE~$iqsyS?eG++`Lr36m7?9ruf8S3mn1sGlfa|E{{;%s7cU3OfEwUN;8x&vU=SDqJ_lrg zDc})+;akSmNGwzlji4dX#mQy=aTig&EJJ`xI7bOw{n@$KEw zbY#o^blB)#RUJ-m$8N&WFzxEG2Q_T}d39qtx+As^?v1})-589d!c{$O*xosUEtHMI z)ivQ@Vrw!SHjK|3RXvfkKN)WeV>9VtdSjwI6iQNI?92JD3C2QZ%^KD;V^{M?47@N5d8AWYnr=(kL=ZZwy=I7ntS6 zyRaF1s193wmm5E)W@k8=LZ4Lilp9yCuB+G{Of+%l^A7akp4Hi2ZjQ^YH?C1x*W;es zV7vXbvG%y}pNw-eZ{ywc-B7ii@oU(o9kEWc_d?mjfcmGg=k^PkYgM@--W^LD#uv<% zrbCv}Fm7SmZ0-I;*!aAa8^jLw2^LyzoM*PPGK`JlW|26jZX z8jgpi+(_MSSmTc4q1@Zg{}j8}-u7veXeP3nat0g|bY?zOZ<)cskG-kHwSW9Np1xeD|$^NGh;5 z91F#hfm9;g7HN;PWs7jM*}2uv1BlZ}Tc>2IbqUK$C>&W;AB}fJ+5%x-*!WWE(6Zwm z4aYjtoi+l-Q0p(vdyxdcV|5qcx6+7N_t-w9SL0G$rc02Mkj7_h z+4RyQ)y6rB{Yj+HRnqjKhE+(^{i52~3m(cf`X067yw~Uvao#U5pD6rQb#@O8atx&D zLxzRpxis?^ZRvR>O`BPyQD4(1%b!M?cJ%pjU=nHbGeN|eKd#u*E`u~b6J(&>n37N3 zVWjyPBm?b-lziGBMEZPYBG7(7$)~Q*mOg+q`ZF8Sw)_y%MIx8}nvv#boIKtPyO8F6 zC-1!&e2P8mS7S?WL|XQT2l=J8^g5(zC(GP`^aV(>42D9aW!Y<>T*7#f$BXH;$XC-R zm3;QkEYc`HJHAY(%D(}NpB>M=iaqOYUtM+)!Ru*HGcxSyi_+Px2ryE)%NW9`J3n*dfn73-@!`%-YjAKp zKHcUg*MVWI;|Z+YTn9scvf@0Z%_7eAY?Fv{ttb_7u3PIxoKG(bM4apK;$xN{u4D5e z&hKi>h&b2Oqax1rc}&E)P8}3+es`l^#JOgrMV#N^Xcck3$Fokv`CX2UBK`uz*NgZI z5jRAf??{|qvg*d~c1()+ix3|dael|+kce+Ud{D&seUAeo{u0DnMf|0R`$XJ>c&Ui1 z=S41}gXrf@^z&-Oi@{-hE#m7$ypjv8h@XQv`;D9e#M!ru`w(CFqZQwR_?(EJhd7TB zIfaN%3;p?sXGC1B&r`iFyX&aCj&kjBuXE4|2xs#;r!(9Wh zj(UwlUKCHq0+B8}@CodW<3=hL4Jkas?p6chJ>T{WjD>k-hE+gH~hn3GGdHQfaf6A>xPsh)nbk~vU zwIh%7Q$0W3^IdM7x$_R6_bKbp({bKC)$>U`-^pj1_`0n5{By6vLr^DvDABcy>BQ@b z^n^p^v-vqk#T8fh-RoKF`-ATH9sjz& z?`XfCJye!^E-Igq^1D5QLjRX`o$GY|jKor@aC+IP)?6su^QL>=bkCdeta*07$Aj~x z`y2>e%g+bg^QL>=RL_-9_5G`R-gD1;?s@O*o%h`NTPSe(Gsr0Y<&8usmvb?z*6;|4^vn$wRz04x_)3LmK zSud+vySv+;pk}IX#TM^Tc^uoFn~U)gGLB;!Z{4W$UGB?vQC?kk<0o%zccR)8} z)Ad7FVAH)5x}*CnTi&lQybHQcq2sxN;oZhA?mf_XY`XVCcep#>_I>o1 z&esh>*KgCkAG%7RWBqu1KLFiWD&O{l(3RM9L(q*U^LZa~(0v#>kB#>c=tgeKw;hJg zFLbi6p4o_ZN(!AESLZ=jV6%M|bPEZ~pX3!nH*3>98@i)HC(Ae=xtajZiCRtw!I3v`KVQ{)RjOtZqvP*{)A4p z?KRL9*mRdbH@zpnpG%=TB6QOBwa^XObeBTcCv>tduY<1H#`8kAPUvL6Tn62VTl4$x za_B~dPV!z4U9XL|5xN?i?h5GE*=(-i#HM=_bP1boGjt_3oe#QW9r@*!L)UN9ZGo=YrmKLiz^1E& z?nHZj-&a95Wz%hi?uboS4c)L!R|8!_=w$!ZLg%;fu7z%$jkgWDBYbn+P0 zLpN;WH9*&C?5O$(iDM>BMXg-(v~9nd9gyq(Z(wE4Rp zx^*^P3v`QZ`Q_dK-Hc6lBXoy_PS)in=z49uUC_1IcsE10!KS+fx~1Lu{TzU9%BE|D z?x4`gz7IkdwefaCS0i+?U)rFX3tDCH{(~U|-MG-nc7&lDwCUQR>lHd#ZU=PDHeM%m zUYjlgU6D<9D|GX%`R&~U-Kb3$g)U*!bwTH|>0;0o*>rK}<^uU;B%nJYbh2M=gRbAk zOG4LT)1@4AY3NF9yl&_gZn4UheYF?5L7Q$LbUi{R>(T?AN9g47*bm)_oAcYT>FukG zjL=D2KXfDiX1zC(&klIab)BL!k2#c$iq0$px+XI`WnU zp>yBM=f0Ou9UEu*{Z9AuI`{KBu3_%`o2*&o&L`zPqU;j)y|3nVfHgXBy@$^ab6gHMf59n#mr{bUvxiLh;^~rsneID)}1(@#>bmXTs!ERW#Q&)CZc&x71ZRarjPH zCz4v0^4{3oOJdMCJEy6tdV5uUb6#N@j;u^d*3lH z8>{f%_a~Z{P9$~i=D$DQWLxJ}pD%BY%kt!jSM|a9uUNY0V`ZGX^WL5JXY;z>yav8u z`<8~fKuvj5jhv45xw>UXZCz!cyt%p2wm{hDt=KUlk7eiVtZJ;R+L}knE01*or@pGH zGLNMCY1q1@9HjcnhQ>fsMZKop;Fxu;t8Hq|Qu4~;JwkJ1ZGE*>5^jI$%d4vzvt+eQ z)=SqBD$nLq>q{*-OTq+quXEh%9QU~)&vaHe)Ai1sPwsqj=aZaGXa4(ZcRsoE$(>JU zZ$8xb~pmKS=su1$>a%JVNP~G|O&VP6Q z|9R%Wxc9~Vu{+<`!~7h0-hKXMxbyALIN$0ktNdcRspmy87x^42HyKe4_x$Ic|J?cb z=b4Wk;aDKnjd$E8;*l7BQYg3XQsrvU+v}+d3n$uq;^hxwWEUyT82Iyf}B)7k7Pe*O#-mzIeZ4 z{XW5+SMI!W=hfMpSLuJOF~7eXg>3az7$K3~1vyq;VfaP52GUzoVQjLcy|#3*ExjIT zey^tpaIe5Pv9Cq62m)00=#gSSHt<&?A&)dwtIg% zoWge7=|ER^G#yFcD&N|#oBMAE_C-SJPHC-POVc(O3MIp-R3O~b77m9}foP;FqTV0y zCx3Pu?CTwgMbeRAG;%vO!$^hO_#zp+fCg9Pc5X6!TX#5>1}z!xFkkx}=?J9uckPZx z%?h{2yJI0~Ec#UM!`xOp9o&ruhGXgEe(UbX$&uX$>a1F%65+N;dnBA!w0qs-UiY}y zJ-LPLOutW}&Ov#PpAIHF@cw_URjKYoBA&$3Ag8~|FK^r)Q1A8CJnJ2lx!k-wbKhi5 z9{0k_W#z3^=KIn0d48SU_9p+v*L&4m!{EFB*o*FZ;;tv|dUE#G6L&tj^U0l0XKy|k z->fm71$Vs0KlzOs^Y{0RpHSk*5r3xO%p!iSh)*NVV?q8g#Q8o`#xqKM9C5yfg!(bW zpDp5t5$EUC)Q=!u0LgRa5aQ5`N$_* z^73al4nE>tc~6L*j7?Yg^lkVID_1e~o{fE})GN{vi}T&KcmS4;#B(1%KW=~Q4JV_) z1iG=kJ|}c;ukGb|j=?<-xaR@)JYdZQ z{y*F2f$o_3ggKFnxAD<<-omBMY4e;B+l$BGp(k9c@ccOz?85mWCa8h9eC)MsUBk2Z zXm==VK3K;BXgw@*cwlX>OWgc^PdJ&3C-I~`ls%Q$c`@sOJiZjv6^w=QKU}bL(~&?r z*wKOK_wDgyS1`T&6NUWsm3^{15)0zlyfDDIBL5?ZW$k4d;U1hcb0sV@ve!##tF|AN zb8&tj;tVf4H^nn=*2D6)$nQ=?_?bg6iSH$)ah~o@W;++-&t5n4^AUb*qf|gWAGzze z`+a4uTf6W%vb&D6C#-O$>$p3w+3Lb&`~t9&CsxJ=1YyVkd2^JJQ! zty{Lh$7w$gfqTE^-mkgm`P`axrt6VApWON6&Zo0CpVV`-_&&?_@`{?;`l`Iw&bsF@ z_j|v8Rrjm>;JA3H+UR_w+E|VFz_hieEBALjAmaS|c`x#bfnS>IZi1gz-v#tqX>%g- z`|$}|+RRY?x#vCiz3%)jf(&Wfdg8v&L`~q_NcY)@H-+sBCf7S?mj&3K0Ii<5W4#jDCbw6Pu%?os*T4^or-g8us=p|z4|95O}!fO=G&HQv8731 zYi({jlf37mdcT)LYA>WBJi?lnRto4M~Zzu8HOkAIs>kHHN;Lay^ zK0Tf1Q}M@Z4G+LJY=Gn#Uk}M^4H?!U&1XPGko@kK3~Q10?x{42K3!?ly|dP+1U3O1 zff8T?uns5ymilXrlfZFc2ABjUfKgxw=mmO!C=dd60nI=iPzjU)UZ4c<0PBGwpa58U zN3C%Jm;_+0(Jq-Kpjv9lmH%JJx~Z3z{$7Q8uP#$ zFbzxs8DJb30}cZtz%VcX^Z`9U6leunfI46kun{N*)&XmQlW#-60F%HtFbW(527!Ly z0FVZvz%HN}r~x(sUZ4c<07ZZSEcBtCz%(!kWPl^UAz&C71p0sjKpF@EEkGUM1Ihpo zPzbCA7Vk#?0<*vra1z_w1b*tAM>vIRB=E-po9Wf5(K~5lF&b zZ_ewn75bL-9)dk#_s#WU;0%37VNa~G9ZRl5D-E*V&G0+dYx$PGI4`-rtu)NQAHz5# z!62`{=$q^2N`v%048H_}>YMBFN`v%$0DcJu)i>Aql?Lg%1%3$z)i=){D-H5kZiHWg zLG{h^(n^E$T>!rX$Drz)=Q~4`dAemRzSXMNQOHgahkG+{obWsv68h8iE!WsG*b@w@ zZ=Rn^SLj==g9WfB?7n&4H&*C-=?=@^JS1WF&FhIdp*J&6 z_?NyzuqEuidHvG@ee)UkuB5GlZ(dg|zQrojEci73$$B4$Jz-yCdA&A!hQ3E(PuTl} z*MTD|^eyL30``R6H?J>4XXx7td&2J9yly>1--`!u%mBM@UJow_y_tC$|Kzcpg*{>S z&Fk!$GxVK-Jz@84UcZ~#)Bh*yeHeZT`!xjb3sxGW?_u~Q7}WKf_ZtI3f4XHz-yzr& z4C)%o`AMns2?o_S?~gVK{ppq==S~6a3A=CJcNr`7{btMG93)})&HK4&p*J&6 zS&F4MSXXtwb_5_34 zCwz{y(l9LiB_Ig~)i<9{tu%BBe|3-qgSwvZxmTsopKcklzl&f`FsSwB^R$8$`j+!@ zx(CM$u>0n7x=EooGf(56toI?<6L#Nx{x@=lz7N2ju#Z7LSL``M-+tH=_Ie+M@47Se z?S(yI_s!>^D-E*0*TFAg_s!?4D-F{3;yzp>1K9xxhvt1Te4nI#1wr~g0eixJEcrZm zZiT+(_#TD5U-(exP9J<%uF$uv_j=e9461KFzb-mM-^cgjoD0}}^SStp(3_d3@lW>2 zA=uYA_zuCh5Bg0j@GtwM7`BAH-ltK`Cq-31SE9kmZj2#d7MK7=fg#`k5CZ%_DX<6BECLo%c*I6K;NS9%LISD zhJPZC{sUxv4;j~(N|9FzxsGx8Tk5jfHv`G`4MTbX zX|oP-mcJOqd;n-;@8ePE(}1+uMILM_Axjun>b(|emNUHv#|@A+{fN^h0olShI6g@B zy$6yu2ITCmIh&)1(`FQM2=D_1!0`yi6fg=500}^r(}Fl{e2^tT5ir$>u?NsD1gY9e zyE^D;w-ItZuojr_Kz{*}a{zI2LXdSp5ir%B%O6La`6G~hjH6BV{;z?)0FXWx!j{bp zkfy(dU9bbB%|XP? zc0)!P2Z#0HJgPx@Bj5o{+naDa0cm>(aoP?*_Am|`x&FyM^Fv<(NSh+^V6%85$^mF& zAJZeymjTkoLmvAKa^VKdX&?iP0Fu*(I60k=b&M;1<*_J*z7UW$CtEC=S;(V6AK(Mz zymnd-)+3+goV?yDLynOtq}fLYAv*zCMh$u3mryEoT8lLK(>rm^4M_d~;^e0xcL5uK znH{-0ajmhhQ5odZ<}l`BBIgzzeJeWd4apD}Net6zBtFUZ=>bgY+_*uM@tz}a@(S^nO9xz`=v zg&$9L1h9)y_v7tp(-w?z&+d3491C<|qcv_dBww(vtB2{6yZQv;(QvFI-6;()*6cQ^ zL}Yg|8AygZurpgYY1Joyosh!eP%03ObVbrxYrAbUo=UVOR%RQyye*Mxv)iVVc%^?( z*_wP=ePP!Y-Gkls@+-W|&|X)|E_&K_ZC&O@P0_%z5|;NRx!Dbr0v*XPT9OQ;JA*Oo z$F1Y?*b>**xI^bSzWW zFY70F03G?5&>WSv!{A&ule>H%I{FpIpevF}VNb_wB^yWQ>KWE|Zgw&*ms*VNV>?yZr-6*7ozQQEMivIrbV z+wfS{pXqoU>uGF1YsD?YxUQ;uh1u&xetUSIBi+swd#I!w4(qad@I25S4R(N=3g?#E zWxVYCc5rGhUk<^nO|}P@k9qF%!sY*o#$TvA5sh$Zmb<(tonvGL^Qy?T9Og$ zB@+wm-v1sFpm-1~}LfAGG?eedha z-}~BBQ{GhL^X1LWrn=guX6W2`mm6p9yfX}+@_fOacZM;6-|4ROeap?Y6%AW$uT)mg zts=h(FJ-Q6s1G!kZ^^xwSwv-2UR@GNFGzOX~>g64%GtYErK3!_qTE(iF!98!g=WX}AEhYnmdmZe) z-`ag2Z*D&P1)jH?ZrHx1q3&_cjmyr-mPPiY>~MZm8SZ%zJuvS+mo?w{$Guw_+|OUC z4eVDN=VwpEnSB1z5lkfTjgffn8$$Wl!5yJU_WO_PP!{*eb+1$1>s0qT6_Y`PGrdk# z&w>1Yb83Gq9qb9%r=|P(q>LsE8-_E9%27zZW9I*$@-L+x zi~nN%&hq@XR2wG{@4bJU!T6kr|IPEOjcE~o&YP=^Vl*7=IY$0LOp{U=$bz$T=Wn zCuB2F1{4E@0P`61iy)_eUTa(gc@S~~WE%3tkW=Wh9>@vE{g9)Ow?iI;tUY`x{H=L|9pOx|%3EM$Q9VOerJpRU3=Fu;0Df!!4 z`e!?-V>{VKf_lye>aP&#a*?hOX+I=w8il?|$m=2L{|10%M*;fj0z5zhVBaJG)|Krb zzZYPg?-cSbNao)SFuxC=pZ5c=20kXz_dv3~hX9uMX@I=10Ic8l0p|Y%VE%e^3j1f3 z0E8LPuNmeu;Fx9D-wYpC;_pG+Tr{A6uM&Ts5+79JsB4!00VV!HCC=l^ zW0!sB0p1GG$4elu0d531KRyC{377_c4?Gtg;RWh}E2ALjsX+E5#TVe_=*~10hkBo zfEi#4I0j^ZabOHM42%%483G1?K7jlKkZB+av;r+a9pD2t0cAibupTG`p2@y6YwhrF zWVJ7=J@$-T{J#sbao@qhY~26N=Var>Cohok-VYDIK*l{2_g!ek*WUl#i{87D@q2zd z`TdK&@nF5rv+%JmB`!Jq_uu+x#5Z;GV;BGGMel96@Hcn+Zu{_0K2&l3Gv4#+&wtGK zhxZi=Qj{<+qOhcja$B zJ^lOt`pqw{z5PQ!s0vSh=l$p3`?-+|fBDI+&knz^u=~!pcklgf&Gwcp$3OkStFF0X z{ENSB+WzTZ-TcOH-F(fvKlXtePu+a)!abf$^QQ*h5PaaVci;H#nTv0J=N}&K_{@hE zfB&lcKXL5lpZ3P;zWcWy@w{twW9!k2yU||bdz0Urw89@Z-}c7ye)7o#|1EC5F?7w( z8{YGg*adh0=jLxdSQ@_Yk(L*J<$-_SJoTJc^i^L}J^HOr|8BGI-Y-X@pMSTdeQ_M`U=edy8eZvMd0rfa$@ zzqjtb|MmIJKkNAF&{b7`|B^5KU}$skE57~6#8s&~)H}uLU;$ zu=le!&f|f`R{56Z@lW>cifk`{-ICZb?+y>bonElUwrPT8$Vuo z!&iz*FRnfQ+AB9UG=1*-doF(84Qmf&e)f&G{Bi!(+>ao@?4T^76wfbFDj;uSCky&mgwoEi?}E#391)RfWbn znSdNadX6ViTR__k58wk-K=# z1Amb{u<*xI#-WiB%;R3v50|dIdc`HIDe#|Hv$&r8i>$j_DYpmQ9{8W>0p3&Q!Z#6J zW8qJbOT?;ErxvkPEG}+d@-Dq}Y1PuXi>qeVEE@f57JxY*1N5$WAMl-XPu=~U=bY-T z6u1NOm8VYi{u1~#0M`dXK6BOjRvD0 z>012Xia5hRt^GfE4!8=>IG%x2PHr}Hao-D_m7(~ebqBQRkN-rFU8fc&HbYC z?{O`h>3*4IG#{x-=ys(go)hlvex2nt|ElUg^jwzR{A$%}dN1Xd@vN}J{fcrtUJxGS z{!ccz`S(@7(+ioi`DE2wdXe&G{L1hU_X*a&`DoP}`W4Et_`vW0_ivT|9q$|N=l%`r z)BNkIRy|*NKVBNX&izL=zWL8pf6~XX>zhBS`dFW&d>Ee?p5Xp~-Prtj)ff6riW#3C zp62dUK8;TaPj!FBZfO2X)hGI7=4x)Q`ak*z<-g-4;gRk?C}-ni!eiYXY;^OPs-!+j zIUT^)hYdI<-g)rg^S&9D?8&$!?(M4vE|KARXwRMV|O$+ zRPEL8RQAMIhF7?Ev+p$jwCaHV56Z!KW%#@9e^&Ozza9R2_kOmzIaU?bSFv@?FH{}U z|55qZ_^^E?% zl%L1%3a@ehj4f#1T=ir98_JgWH^Tw9p+w@r@ZY(&v74K>R@LbXl^yZL;R^RZu_et< zR6VZW#%^t{uiCDEOZiFsmhd9?V@h?rJUr9=12(()hgCKDEHXqEDxP zyW@LJH&<~eN@bc!q*73tGcxr@9DZS*1k`yX)BG>)*J<91lD&C|u}<^;lM-y$6tTe?W$J{$7*|ef|$Y@O~B zw^0!2w_KUZY8#HZH!8v1EK%a#=&ok9@nhVz-knWxI#v{gZd03r!+Hrgyw`)kVDB6n zVzo1WRur1R3ZsRg)n-wsQq8N?J(D$0G|pl##18k(WB0IoZ0)}u%xdp=^9S!z{!^YS z3YD@PSFwI|h~*26ijAPn)vgM+x`3eF^?^c=)y}!n5hdFoTeeg9L~qZDdP}@%HSo$B zcsF{}YT(VLI8=iQRWp=;nzRLOL5uMEWC=K2LYIUiBpfMWiG*XaMf|Z6mP&Y?gyT?) zC7@GIZxL_2bob5??g`SJnCt%{?}(xo7)4q#I=pA_R(W%(5rA>eUVz)9{6Ad#n1wIoUiMT zZGOj!p|&L$#nA$P=5dCku*83F#Yu21LnM~sR19{!dyHZk!xhM1?j4Q(a$K)nbiD6G zDoJ0P9=hoe<>U(diRV-h=*>&RPDmatU~db){808Rmh(`mPpW}}<(?9ckpg znVQ8hdnAW@vMKaWE2wv>fj_JeJ$X|1o@|sP-CLpt+qC<{ljdt?wC*W0hV(m`+sNM@ zXQK|qMl1DqnDNKlhI_FxwO|LujBTN~1t+><=WpL_bc@X;!fQNFHP9bv>HnrikSWBm={5bYn#x|1GT4%$f-upe<+z}u8VTIbuuqT^>W!Y+FnX9^= z*Vyk;m}g=3@)c;;!H1$QGcWdp=Vsf={fK?HO7cDad*=o<=;l3z>bQp;L0-{{vMu`! zJ@mwb4D!WSsIUWzV^bbFVNWKEoi&Mwq~kVk#9uO_gz%g`COO#fExdY}7cG5Sj1-W# zAIq=?BeC#`l@#{fQ)(sX_{g?z9=4bE2d zP4&kp6tfG2?qcLe_zwbqG3Fl_->;^5#lf~_Ma);!wq_>eqB2!SN+B6Vx;;pD1oMF3 zKmQ}l2iQHz)P^R^6KapA@kq*!7C3!uwy52DjO>s!$I*^^Sb>x@OiCK1Uer;Ob+nyj z@Ifsj0<$RlZuSbwOtKs_I!zPV(jb2I2+|ciDR}Uhk+BTVWnEPoqC;ZwbD|*No zrf{`wilnNbC(%%Co5lLJ>jU~9$XJfC4z6#MDDAN?9PK|DPHo~fsNBlbfjb11*$K%j z>j`7`vd=?3Co5D6DnFH34bD?UeRykMpdMbsv3=kU8YvvxV^7TAMx0-NY~E;#SJa8~ zw-CR0w^Dhcb-m6jj}?Co=PfHf#rAF`K9AN>4RS1AM}HLf=Up&T^ymnLL*ThI)o5IoBxRa{*9)s&^ytB9)1H=fSoqilAX8r@NJcXfm`W)lQHcGS>1y zp@UhmyvBjW#tA*t^q|q%_(Pfp&c;)P#FUt$q zyU8)kj!M#2f0$LOXUehaqVhBdE;q8_*Ay(zCOS zn_+Q|6?3ZM8c7f1vmIp%vz7}=OTV&gJ`?MTQ?@W?`3&?mzcJ{{3~&i=Dez`rJ{KFB z!bO;76y_ry%_z~D;D8xMMpD@GLFWUDAK_d;<1+EU*U`fN#@ng;*m^PTyAyJhS~AS% zF6g&>w84rzYjZnuQO~0GqLng@EoB%}+y+UivNTCm&Uw&jQ6P=N=~U^zvK*A4mWrdd zW9~<@f{kbyg5Hb{KYCv|rz^=lt7Xa-W-c%1R2QMNs+hd;^BrN6=FS!B46H)f@m!6) zF*K-bj#aCeV-dzE*6R&ihA5lMUvDxuVxC(bnSmKm1!kQh6?-FByHKhJ%!hfZaw9X@ z)tWZmg4L-O92|PzWNn98>AOtxj2IBSI&?#y{1MlNSY;0(%GVdtGp7IVD_Y@V>0s-m zHY*B^XG0Bl(u5y`X{)qgkWOo}wBj>j4g)n^b)i8+sF(RN8 z=v!Z*46+8RzFPiiG@zN@SIEB$!{yYX3roSeODxAVyftmWzjtd?k9gc)K{zE)L!i| z6Bv5xCzn=>OT{3lnUD6!=j}1F$MzWcSKA{E18;VaQ%3~v)1Z6e0BF+IxAF&Ai)^D#{B zp(g*YF%(~R8C;i(fw#w)9(eOYv?%565l*$os4s2R(hIc7xmZdIXs7+$(fLv^j4HVL zGBK1E^dx;RREBY!7EA$ea(OY1(_&l?6diW~TAYWa;ENt=a%mXux@-(5$# z4Ckrt9Gr{?`hbR_^LuqXsR5tTTeL#jgl>RsW2@ zz3^M3+N5TO3P@-7eFER*E!S|Y4m)o-h(q!)1GV{PUWl^pzJ;?2JD|& zF*4F)^iPZ7vSMffd$P{ROplkB7SCzLbEL<}PKyDoqBL3QF>XwY;U;?Z3Dm8k)BM9v z+d7Fesb8pp2Rna9KR!Zzp^o`|QqD702(xea-f z&v>ep5yen=Ysedi-QMr1({ed)S2yI1JVUe$2YQ2+?pr8z9p6RW5fQ!N!&TG{(;*3n z&(**n-af^A2bp?;Xs4@;-m=}U>hGx3Llb{2Qt6>D48jlH6W&(GkGXHjIZipOIU#bu zX({STXAV?bPl+haKpq=?GMASK<;+e}>EMI3ainbudK6K@|6b)W`XtFWT(5@){essT z=a=ylL>Z!x9(w9=kw;FasD~1W2P+g`iO*MH=?UH^%kXQXnT zgOe9OPKu9PWnF&|=b+Y}x;SsqkIQ->Yz{O8D2D%WI@yYCj2#}p_0(tw{s-@7iL)*` z%YoL9IE^9QAzwDp__VpeYzq2ve2@jF%$l!}-u9%&WoEje`SbPDlyGZVg!`*f?Ul9} zsS|8|&UGGb@P2xm5v0M9o#BgkHh60KwyMFcj()9mua-qT zHC&Eu+NDe~>fmCVo-HHRv9{c2OP}CHce3LoD@D?tt%lojlYl>odg@S0Wr3FYP{8K({*YcMly_Bz&RdRXl!2#Z7uJ@YY=N_((=EO;u~z! zI2E+gNODc%XQ#^cgb~}C*hbi58*^KUbL!T6Y8)7!-+rvayc0F0Qp=ibx(Vg(Fc+I1 z?OY7rYS4UYZmW=ogoD=-bFh5mjhbRS>6I#{cE)QIg%+#XJMwvt0X-lmbzVxug&(DW zrYPE;Y@R^BJGhPJ|9lqNONNXO3_+?K#F-Kpi27#nlFQsVtyAqFsSkXp!>64B^LXfK zQf#W3$icHgdtqkV^2BgSVfceuufMlc+vHoOvfm_fk2T zc+nThN_sYYSQCpXSsyyRM&dCIJo!Nlbif=5&=IvE?$h2u>BGQ0zCMrB7r7y{t1ew_ zEb7o{+0wrR4uHE$uPk*GQC{{nr=D#cOo0O>n4DGumF5a!2~x{~RYU3n%_ z^`<`A9b*Q^NG0$ZxuD#+r7$;BIeLLQA|zoPso860wUXTH85foALeip3r`gXnpvBz+ zCiF_UZm>T<8qkZ;f5t;cp5O!tCpv`tdT4-?|0LWLAUIk2-yq{nk#H*3xN}uI?=_t} zZo(>8xGGe0hXNO+ohH+&5^56W_ZHz9g9W^?uejd;8b%%Hm5zG!-8bfK*F$x%aVZ8J zb6WYFA3~CV>h0+CJAFGn(HSK(2A8hQxMM~(!7tET(ps_LGn2yehl}w1;S}x%2Y?U2 zIX=zNs$>bt2>wF6#Vt0K>K zmGbPF!&tr0J{C1Ox8&(1b+r04tDHg>epyMaQu@H1=^V!D#kl8ldZKiXc$!=~w!F83f4w|7p`uWulGS2D2fa~=6*7AkaB!c`rH?{BlNhVr_j864lFjq9 z4Yu)Y95kl|v@zUiQ3^wD^wb+DmwTuLluP(GRxX(>=C35q;!K_ke5OmEu<#jB@GFeH zjY=W^lwy7*gMD);x$I8K%dZ_*<<>{P^ zaw1HW7(*h|!)cC2J&VI@nUqVU*5VmF6D2S;_A%1-L91JursZ>fB1NF+PyV$9futyoRqbEj?y~ zg!{p__V#XYN)1syL#%>N4C7jzBe%7ortVc=qzu?RH9BHbJm~xzojb}Za!lKt4;=#5`5w^HidFHc8d!PhCaK ze+2sZiJ`&0nYyV28(8^^XisBi#Afq2{aT#8@Pa)#v&Cfg%9&hN)TFhl7_+fDq18h! zBo5Xq++OX|CYcQf$%oc5w6^H-$v@9$AbdPEgyS?)46t0)r%`UgL%vt^=-aWI=-+vK)V z%jD56>v&oZfrl$>w%ik91>~ur^xg^!=et-Hd8>Wk44RLQ=ebj>+=v#hQ~H2I$WATQ zGpA5Vt^PxOq>EQBm*Qhhru#5Y^cI+TKEA_M7U^FJ-(p{0HupWS*k{YT+S&ku^ z#?>*&)%(uj>aNw7kR+E&oien@6|H4k>Wt`Qs&D_49Tc)ly0Nk?L^Fz_lrn}FVwCMy^ zYntU4b$2P{6|}atu3%EL*7@ZBi&( zpq#f7`3ySGr{FxFA>3zXB(Kt^`D@A(4O?g*yLX!F%;Q?6J@Ch5M&P3)cC~75Y?I}f=2f{#+&KgMPXD?y~Qd8NbD< zi}KCa#VqyfDpP-1rU7YXDv)Jbh%)`>MVHCe$teV?Xh-gxM)TPTn4#YF!VrElTMxbW z?3drpb`QXY;iH)C zit&|JY+b%K?n`4?hj{>VouhgV*1Kyl4h|+4pB-hl)`8w|xm$tD!5(uvQ%mT&M~5ytZ=;X(hx>`fer6?J$3k%H<($JEw$s>ndd}FVtfBD|sxN z|8|t@yw>UyOyQu=^Xl5yFH?IuQtcqyGL!Zds5WRz&h7n5A+f2QMO*d7tkI%OSIvnQ zA9IR)VHN;4PuZs*w+%M>1#<7eyj6*Z?9H+2y;?)>z0TM*%3INE_BxA0Vq6q!bgh8& z@*0)Q0>)*GqhLCBXG!;fg81iowe0=)x2fE_o-kS4o_G`=rOlOfVL zY^;Y=Wq&P|9ks1c)u4vH0-X-DM9=wWdA|&kD6<2tM|uk4MGV?iq!nF`q69MWLPkbX zyf|U`XDS(d=aJ%M+O#gaIy7``r33r4MAhtQW_{Gv52yUtxo{3m^S8raX%+qhFk{az z?(v8H9G+`K-XJ3gGWv0km z!&*KMH`p+u&9a}hOMkd#*v~prvBZhyuRxI|C2N+w19|fFaLu)MSlHkyvv=foh576q z#VMCkZtu{$Tr=z);V#$gjE-WHDHc{`7I&w@9X{^1r^07)x5IKXoxAf>ZVz`Cr`#gF zo^t!O4$`?`;gnA~eE2?n%4e3=Ve9VW&gk%HMP`^uisSYfxlwM>0yCuBY7vx@hub|) zy19)uYGiKku(%`NX!S*w#@7w6QX3UTQt@Z>5T9OIkbPIgFXnxQG(a4jkFw_3&x$re z{=k>ZcYy4jdg$i;`BPV$dZ_Ao(yAK^qlfN01WgdUEA@BJQyFvk&R>(#3y}0ZvIBjW z6Rj4!gf%;lktbv1QVd9r?7;ij@orMG(^Bf8y}Kyq{OuanX1_et8?)a-KT(dlYuSsj zoqFh%pV-pu6qD6EFo!<1M-NSULJ$4s1wGV?+=O0BUQ!P|^Ur!{O;`_o{&Z$-@vc~u zN~4FyZpnZ~OXIV8Xg7}Y?f8sPk^&AP{m`=Rfo>{J64H6U3W$2dD; zEY0igg;cl>^5{PGDnm-rZBLb9wK=4c;=Lo%8I^(Dm1%C2Hx)NKGd*TD)yt|&K2G-Nwz@JkR*iEB z+;9~5vaU)SEQ8zWg4=q zdwBolUE!=gu?2g0*rmwYn_i}bL*+c8;#~bZ7?+@}hcjAvJMZ=SVFKm$OWXlDHHR`|!wTTV-7Q;*iX^+yh`l9wq+NbtKeOTGP zU+;;;2Ak$TCU3#ZD&R^!5)wDB;qKQ{?p55qeg|G zoV!=2+&Xs`J#K|h=I+5McPV#=wp!sX?slSAi~Nf#Ck6T}n-q8_IX>W6Ha>6&BguP7 zEpR5;uW~}*)#SuLG?`mD1z}SH+mn+6KTqBecpj_HsevCQZw$PcBp$b+1=gA!=C;mh zo%HTX%*Ec0x`u?;J3WStzs{2vP**|^BX217`me-JKU=yE`wi^&d-07gy`RrMaGvlh z8ryK5ke@nFm@a+vtjG}1n=Rw%mh*JWL^_-Yd@f_zQYQq~$%G>_vaZHq8`)atTvsy+ z-+OD0!eBjsFZMCvOY5S0aoX(JxE?2vj@El?$X1M#r2JNofsoBHxJ%)txVAw@0W*ZzyHfPEzjBOcKV}SYVumiOWr$Xy$up{96qGKKH zkZMbvOQ6}2yI@IVY0D?3ZNbvW(!zCYDQXNVDN9ke0j*1sYFUAa6x}eKy?=wFcFl?- z(fc>N5nYEjfJ%97$F(w?fUT<;16L66npTawhjITPIPzwkX#}~kvvoDatwG>-8~xF0 zk3z?85~H`p=o}><5{u4t{_=}#=~K-5p^YYD?L3L)NIzZ1@;sX>eZunmg=Qo7seLiN z-KWwn!+n_X)3?8~k%>gI(gA=?wEr* zVkYf`8(;AT63L;&##_yOmRTa(uZG8g=AY#^-Q54` zzSm|s=hc*Bhk0JjEbX*&XlM>7M-(iCO|hNk*2Wn@!ZS^5vUNO-d%-sIyL@ z@j6-fQCT}$JAZ%^9NJNyFrXM8J4=NPt2NjC+fIK}QPY=k`_m}DW%k=$a`u;L~f0-VTrw8Qe z0eSi>Wcn*)`YUAmD`fgBWO_iJ9+0O8j0<{Llo%#44U?FLNle2ereP8jAjbsAF#+ehVp8xFZ zlG%KYv=Dt=ydWoEqDs9FBi)el^zPg2b6)0}-R*stQOa!0GAoa1{4KwPF*vDBWVPSn z+At@2QP@9NVI}1HPM6DI&^`HwXFJSnMWkVkG!F22iOrsXGSyib$B7I>+Lg3Ck17} zY@R}9Rp(oyE!Hf;uaESZrOh`Jk*<>C{g)w>3-R=9`AXOMuLBX4ziUwf{HTWxKC4vD z#``uKuzqNIaCSEF=xOt3o&4<^&g<3-M~`+MY-?0uY%mH83&S)XX-qV3Xsl^`L}h<8 z2Zn4RJ+y9rcD)Te7T&LiKHaY|THRe`)_B3!gsVjF);dY6qbcakhQ2&zM!r`g~GgDhwynW`7t}? z1?Uj4SccQ>QtqEGVX=g|gkcV`CM9?!X4nGKs|MtzxfDS<{UJ#6YJwJiD_rD%rOY3Y z=Lc9U;)`;?&AA6qm;Pabn3M5x0`hP`ULQbSA3%-|u$VYf=p|75l(1r)jxheDizX?F`X9i_@ul7H{yqn6BGB&B2#h`rU*~++QR2 z0wG1A)s)5WAvo^h654pl^hVO-L(3_d?zRWM3mxWH0^e9kcWAICKFQN*S!Y%ct1rh1u&Wp&tXk|wLs}UxJ#2>t8+1w@p&K%EyJ9T3lU|19^A+$L zy<4YXJQMrm6=&$yOhI4)-?8gzOCN8Eu9k}BS}$?a4W}RS5~*z-j9Oi3Als8Zj5YD& ztIhP+B|Y*U)rD(7uble~8a4m2Ap>{^$v?#@!-R-CvfUY?}a23 zwS`8Pgwkt)3d)i@kGprK+~)h_51F53#W3@vPgwZa3j_|kOq;)e&aD%Qy(N{_p7OEM zmI|K?nSaKD44x)K;wVnJQ#dp$Mk@a`!bg*J(PY}z1vK_26s;@&+?0=%f1G@TL|Bi} z9Tbrz$z5RMsV&NADM|>+tVy|3C9|DJnNmraRPC(#3mm#dp+d&X14>!tYVA&!UMV_= zl;M;+m3!`ablEBCB6H75(L>J|E{vi$?`-7KL_#S7~ek zY%xC}2;Q&{0?l?Rg?!JB`zVFnrzw~frV!Th0Cw|uh>h_O)?%KrQVSoYAtz4)lUM4i|bVi!9;2*LQj1h;$W41%Z8 zQz1Ix)r^cl?zwoo#kotp2KzB62kz+>Af_k_-5R1Z9-2>Zh6|vx zIc;nU+sz0h4SZ3nB`W<(0KU44Gc6kT$u$n`13x1Z+9_SW7QfMJ4yqbCD9*QH~`lr2@V9_xi{j#1NF|gIdulm`)A4;@*gGdjEfd zG6^;c&*0$`N{E&sg!_9m?%x!gs07M$p%tyX!d*4q&a zr7O8OX@9XCY)hLZo%h}eA7Rp8O~Fd7mH6@v+&O2hdMFsl#|xY^hK!3mc#-4K*HW^A z^mkO~EXFET_&0ycQl-BSb1tp^yzOsAtMnIA&ZX5?Db>&r?N<)r8ao8Pz-*vV=__~5 z`pR9i0V!R$0q9YU%7BzE+yJZ@X(q3Sjz3)#I*m18<^qCQxV0eMIgl;nuR;=8A!{I+OD^hVD%55Kvgb-KS#_Xhll2Aps;X46Oo0BQ9{q7F8 zA#PFA-3q!nQHJ|vWeX?bo=Dju(s}m%$zS5fUElmWeb6-X8F4c+7E54p+UCY+)U?FKAZ*l@>J~J(6~oh zy%#Gj?NW{ly&cG7!-o~`g(0OZ?eX&-Dl5wx6wO^-pFTPc-zL_2a>5t z$$%}V(()(07cna%-5E=UFswc;4WBHjIoBKf(hK||b?`{HN9yr(r4o7NL1qe^nV8R8 z+Jdb1$FYn0Z>pld^50Y(BX}o=X2Z@X?KYJ%WsnW+RmwC-?^2e@zjnTAC}noO(}fpn zY{iHJSnJ3c78SPqoH4Lbdip1;Qk-HagXqM#l;v_9dHg$oe+Tk!j>Otu!W@nr+UTiV zTs)UjC*5(xZZghJd`##u(+wm)&U)$HcY4uZ{L6*4Z(R;O)dbFhk0Ms0<^$Xx!F_)I zJ&nA`bsBkaSYUo8;m5+C>9{9hJL;r$#o;N3pFX_r@RPPqWd!ZAEHb}!dvx&wKaM&` z`)l`>-Ze!2mdn0pK z#2kt_ZP~6ZJB{m2O5xEanzgHYtR{kH|V-{z1*>5%X8benS)_%)lF~5njd@FWq!?k<2MtCaPCBf@D4>msB_`}9W zHO998of&mJVBTsrZ28mDD0I>H-L>C1Qwd!-_J_(_&D~q5Frb*- z;0_u_2fQL-LQl`;b9x}zvsb%tbLQkBOf)iu&nI`#ZmW3DyO__YtXH;9*<&B;8K$Y-b8$_}<|*WB;jrHKFG6DL-56Akw|@utUC z^t+r^Ki!-LW=HFXWaGF0&{rAX0n@N9%7C#8uGH887qjD^_JRX~g~9xHnN1&21ieJt zh`~5NiMiVF?@##mmaM_I$3tz0>?86j*>=*SwtvSyA_~~x-1YIp*X-4HRVi7dVXZD- zY}%*BZc*OKVoB_5)BRKYf0U_Y<=$?FOjD~=-a7o!Ugw?D8jlEl>_z6sOZCt;XhA-G z=we6lbN3S<^>9yx{x5K?>cGv0!qCO7{%j-cBbEej#l6xc7}p_(KN=YHu>IP&plw8P zs4Fzcc~gXnuv<+lb}UvL>T)4fXEE1azE35&e4h%}`=#7Q|5bONIu5e+K9#r-F>qQ# zuSX@BAV-O&L&`(P-cwVdl51@tkKH z7<=zk><6>=YViG4dtdykBf~#A(pTrBA!Ny24fyw**v6n4tJqE7#e0mrk9HR|%(s1K zu~{5yh(z&!Z9Ruqm{Ei3x8KTClAqmEsT_LA89uA_CxxSo*~|3TkhZBtBLJ=C}GROJluKYMbfehs@6Nh;nrUW?N0em0kGZ^g$jP-#T0y7+D9L!BHVYb3N5A!}Y literal 0 HcmV?d00001 diff --git a/bin/ice.hex b/bin/ice.hex new file mode 100644 index 0000000..e8ce077 --- /dev/null +++ b/bin/ice.hex @@ -0,0 +1,981 @@ +:20000000AA080000000000000000000000000000000000002BB8F5010000E2B900FF80DD5E +:2000200000000000C1C081C1400101C3C003800241C201C6C006800741C70005C1C581C4C4 +:20004000400401CCC00C800D41CD000FC1CF81CE400E000AC1CA81CB400B01C9C0098008A5 +:2000600041C801D8C018801941D9001BC1DB81DA401A001EC1DE81DF401F01DDC01D801CD4 +:2000800041DC0014C1D481D5401501D7C017801641D601D2C012801341D30011C1D181D053 +:2000A000401001F0C030803141F10033C1F381F240320036C1F681F7403701F5C0358034E5 +:2000C00041F4003CC1FC81FD403D01FFC03F803E41FE01FAC03A803B41FB0039C1F981F8A3 +:2000E00040380028C1E881E9402901EBC02B802A41EA01EEC02E802F41EF002DC1ED81EC34 +:20010000402C01E4C024802541E50027C1E781E640260022C1E281E3402301E1C021802054 +:2001200041E001A0C060806141A10063C1A381A240620066C1A681A7406701A5C065806443 +:2001400041A4006CC1AC81AD406D01AFC06F806E41AE01AAC06A806B41AB0069C1A981A8A2 +:2001600040680078C1B881B9407901BBC07B807A41BA01BEC07E807F41BF007DC1BD81BCD3 +:20018000407C01B4C074807541B50077C1B781B640760072C1B281B3407301B1C071807054 +:2001A00041B00050C190819140510193C053805241920196C056805741970055C1958194A2 +:2001C0004054019CC05C805D419D005FC19F819E405E005AC19A819B405B0199C0598058A4 +:2001E00041980188C04880494189004BC18B818A404A004EC18E818F404F018DC04D804C33 +:20020000418C0044C184818540450187C047804641860182C042804341830041C181818051 +:200220004040FFFF80D700000000EEFF58D80000E6127D391358FA3F6AEF74BF00000000EE +:200240000000000000000000000000000000000000000000FFFFBED700000000FFFFBFD777 +:2002600000000000FFFFF0D700000000FEFF76D8000000000000FFFFFFD700000000FFFF9C +:20028000B1DE00000000F8FFB2DE000000000000000000000000000000000000F8FFC0DEB3 +:2002A000000000000000000000000000000000000000F8FFC8DE00000000000000000000A1 +:2002C0000000000000000000F4FF42DD00000000000000000000609F0000E49F0000B99F32 +:2002E0000000BE9F0000FFFF5ADD00000000FFFF5BDD00000000FFFF5CDD00000000FFFF01 +:200300005DDD00000000FEFFD4DE000000000000FEFFD6DE000000000000FEFFD8DE000090 +:2003200000000000FEFFDADE000000000000FFFFDCDE00000000FFFFDDDE00000000FFFF99 +:2003400049D700000000FFFF4AD700000000FFFF4BD700000000FFFF4CD700000000FCFF22 +:2003600068D700000000000000000000FFFFECDE00000100FFFFEDDE00000000FFFFF6DEDA +:2003800000000000FDFFDEDE0000400000000000FFFFE1DE00000000FEFF7ADD0000DDB9BE +:2003A0000000FEFF7CDD0000DDB90000FEFFF8DE000000000000FEFFFADE000000000000A9 +:2003C000FEFF7CD7000001000100FFFF7ED700000000FFFF00D700000000FFFF44D300008E +:2003E0000100FFFF76DD00000A00FFFF77DD00000100FFFF7FD700000000FFFFFEDB000023 +:06040000000000000000F6 +:20040600E239000000801F765D030792025206ED1F76BF010D1A0010056F1F76BF010D1AEA +:20042600000806001F765D030792025206ED1F76BF010F1A0010056F1F76BF010F1A00084B +:20044600060008FE03E2440103E2420010E7400000776FE800F0007703E24600AFE24202CD +:2004660001E8E8FA20E751000DE8B89E00E70800007703E24800AFE24803AFE24600AFE231 +:20048600460100E3484200E79900007710E740004076F8B802E8010250E80000407675B608 +:2004A60088FE060002FE412B419218521363013B008FA6D741850156A400C42B4185418804 +:2004C600008FC0D70156A400C47E410A41921852EF641F765E03BF56260B1F765E03BF5691 +:2004E600270B82FE060004FE2276008F49B01F7634001AA81A7669FF1F766F030F8F404272 +:20050600380642A8C000A9B8A9BD120F0077007702E8D11B008F66DD89E6000040763AB65A +:200526001F7630000C282040237600101F765E03BF5601021F765E030228E8031F765E03A4 +:20054600BF5603501F765E030428F4011F765E03008F4C1D08A81F765E0319020A1E1F76AA +:200566005E03008FA8610CA8432B439218521363013B008FA6D743850156A400C42B4385E3 +:200586004388008FC0D70156A400C47E430A43921852EF641F765D030692015203EC025225 +:2005A60059ED1F765E03BF5626091F765E03BF5627091F765E03BF5628091F765E03BF5633 +:2005C60029091F765E03BF562A091F765E03BF562B091F765E03BF562E0A1F765E03BF5618 +:2005E6002F0A1F765E03BF56300A1F765E03BF56310A1F765E03BF5632021F765F03BF56E6 +:200606000C0D1F765E03BF5633021F765F03BF560D0C1F765E03BF5634021F765F03BF5609 +:200626000E0F1F765E03BF5635021F765F03BF560F0E1F7670030C1A00401F7670030D1A8F +:2006460000401F7670030E1A00401F7670030F1A0040035203EC04522DED1F765E03BF56B4 +:2006660026091F765E03BF5627091F765E03BF5628091F765E03BF5629091F765E03BF5686 +:200686002A091F765E03BF562B091F765E03BF562D0A1F765E03BF562E0A1F765E03BF5652 +:2006A6002F0A1F765E03BF56300A1F765E03BF56310A055254ED1F765E03BF5626031F760F +:2006C6005F03BF5600011F765E03BF5627031F765F03012B1F765E03BF5628041F765F0316 +:2006E600BF5602031F765E03BF5629041F765F03BF5603021F765E03BF562A051F765E0361 +:20070600BF562B051F765E03BF562C061F765E03BF562D061F765E03BF562E061F765E03DE +:20072600BF562F061F765E03BF5630061F765E03BF5631061F765E03BF5632081F765E03AB +:20074600BF5633091F765E03BF5634091F765E03BF5635071F765E03BF563607432B439228 +:2007660004520E63013B00BE008F8ED7035643010156A400C4C2430A43920452F464432B62 +:20078600439206520F63013B008F9AD790E5035643010156A40003E2C400430A4392065248 +:2007A600F364432B43921C520E63013B00BE008FC0DB035643010156A400C4C2430A439256 +:2007C6001C52F464432B439220520E63013B00BE008F00D8035643010156A400C4C2430A5B +:2007E60043922052F464432B439228521063432D008FC0D8408F58D812350156A400120238 +:2008060040763DB9430A43922852F264432B439218520D63013B008F00DC43850156A400AD +:20082600C41800E0430A43921852F5641F765E03BF56000C84FE060002FE412B41920352DE +:200846001863422B429209521063412D008FA4DC013B09350156A40042850156A400C42B65 +:20086600420A42920952F264410A41920352EA64412B419218523763013B008FA6D741858F +:200886000156A400C4922BEC4193A892008DA4DCA2FFCBFFA894A3FFA9850156A00041928E +:2008A600109BC0002CB9A92D019A66FFC0984192415C013B189C008DA4DCA993A2FFCBFFA0 +:2008C60018DCA894A3FFA9850156A000109BA492C0002CB9A92D019A66FFC098410A419249 +:2008E6001852CB64412B419203521463013B4185415C408FA4DC0156A50003DCC588A4850F +:20090600008FADDC0156A400C47E410A41920352EE641F765D030792015205ED1F767203DA +:20092600251A8000035205ED1F767203251A0F001F767203BF5633F31F767203342800C0E8 +:2009460082FE060006FE467D459744A8419600520EEC448A013B4585C40F0362019A116F32 +:20096600448A01020156C40046920B6F448AC40603ED009A066F448A01024156C400469298 +:2009860086FE060008FE44A84196C492459647961F7672031E8A013B41850156A400C44D30 +:2009A60014EE1F7672031E8A41850156A400C4CC00E046961F7672031E8A41850156A400FD +:2009C600469247CAC4960A6F1F76720341851EA30156AB004792A4A9C498474800BE00B63D +:2009E6000AEF1F7672031E8A41850156A400C44E02EE01B6A79302ED01BE1F767203215663 +:200A060041001E06AC07A98AA6920190C4CDFFFD88FFA8CAC4961F7672031E8A418500BEA6 +:200A260000B60156A400C44902EF01B6A79202ED01BE1F765E030592A9CD01001F765E0369 +:200A4600A6CBA9CCFEFF0191A9CB059788FE060006FEA68E437C42974196442B1F765D0374 +:200A66000B9204ECBF56450A036F452888134392AB28010042540A63649BC0001BB9A828F6 +:200A8600FF0FA99F42550265AB2B1F767203013B008FC0DB1E83035641010156A4004185B9 +:200AA6000156A500C5CD0100A85D4593AB9240769F82005203EC441A0100AD5CA93A84DCC4 +:200AC60004ECC492A08AC49686FE060008FE44974396462B472B013B008FE4D7438501567A +:200AE600A400C492445423624385008FE4D70156A400C488008FF7D743850156A400A69228 +:200B0600C45415654385008F6ED80156A400C488008FFBD743850156A400C47E008F6ED81E +:200B260043850156A400C42BBF5647014385008FE4D70156A400C492445423654385008FC6 +:200B4600E4D70156A400C488008FF7D743850156A400A692C45415624385008F72D80156AE +:200B6600A400C488008F6AD843850156A400C47E008F72D843850156A400C42BBF564701C1 +:200B8600479222EC452B459204521463013B008F6AD84585408FFBD70156A40045850156C0 +:200BA600A500C5924694C4944696450A45920452EE644685068F801A421EA9A8C000A9B88B +:200BC6001F766103361E013B4488008FF7D743850156A400C47E008F6ED843850156A400C0 +:200BE600C40A008F72D843850156A400C40A1F766103369288FE0600BDB212FE4396512B96 +:200C0600522B1F765E03009E4B96013B008FC0D71F765E0343850156A400C492009E4C96EB +:200C2600009B009A4B4002EF019A005202ED019B4D974B92A0FF049C4E961F7672031E8AEF +:200C460043850156A400C44F1BEF1F7672031E8A43850156A400C42B1F7672032156430086 +:200C66001E06AC07A98AC41A0080008F00DC4392189CA9850156A400C42BEFFF86024385BC +:200C8600008F80DE0156A400C4E2C400007703E246001F7671033F4405EE1F7671033F4152 +:200CA6006AEF1F765F033F9212ED4F2B4F9204520E63013B46C4008F9AD703564F010156A6 +:200CC600A400C4C24F0A4F920452F46403564B01408D9AD7008F9AD7AFE246010156A10049 +:200CE60003564B010156A400AFE2C40020E7080002E8D123407675B6AFE2C10110E74000A1 +:200D0600007703E2C100432D008FC0D8013B408F9AD712350156A40003564B010156A500BA +:200D2600AFE2C5004076DBB78CE600000077013BA6BF120F008FD8D743850156A400C47E21 +:200D4600008FD8D743850156A400C488008FE4D74B850156A400C47E4385435C408FD8D704 +:200D66000156A50018DCC588A485008F00DC0156A400C47E019A1F7671033F4406EE1F76AF +:200D860071033F4102EE009A1F765F033F96008FD8D74385AFE246010156A400C8E2C400BC +:200DA60003564301008F80D820E708000156A400AFE2C40100E70800007703E248001F7621 +:200DC60071033F44CD56DC011F7671033F41CD56D701AFE246008CE6000000770077A9BFF3 +:200DE600120FA9934B92407663835196013B408D9AD7008F9AD7AFE2480003564B0195E6BD +:200E060000000156A10003564B010156A400AFE2C40120E7400002E8D123407675B6AFE247 +:200E2600C10110E74000007703E2C1004D920BECAFE248001F766103AFE6000003E238003C +:200E4600EFFFAB00AFE248001F766103AFE2380140761E801F76610303E23A00432D008FEC +:200E6600C0D812350156A4004076DBB703E24A0012E8401614AD056390E503E24A00512B82 +:200E860001E8A9FD08E89927407675B643928CE60000013B179CA6BF120F008F00DCA985D7 +:200EA6000156A400C47E1F766103408D9AD7008F9AD7AFE2480003564E01AFE23801AFE6D8 +:200EC60000000156A10020E7400003564E0195E600000156A400AFE2C40120E7400002E828 +:200EE600D123407675B6AFE2C10110E74000007703E2C1004392089B179CC0002CB9089BFD +:200F0600A99F4F97013B008F9AD74E2D03564B010156A40003354F93AFE2C40043958CE68D +:200F26000000A8940B9CA6BF120F008F00DCA9850156A400C47E008F9AD74E2D03564C014B +:200F46000156A40003354F93AFE2C4008CE600004395008F00DCA894A6BF120F0C9CA985D4 +:200F66000156A400C47E008F9AD74E2D03564E010156A40003354F93AFE2C4008CE600002F +:200F86004395008F00DCA894A6BF120F0D9CA9850156A400C47E4392013B008F00DC5188DD +:200FA600189CA9850156A400C47E1F767203208A01E860FC43850156A400C8E2C4010EE8EB +:200FC600686600E70800AFE2480394E6030014AD0565521A2000521A000103564B01008F9D +:200FE6009AD70156A400C406461EAFE2460103564C01008F9AD70156A400AFE2C40094E609 +:20100600010014AD096303564C01008F9AD70156A400C406461E03564E01008F9AD7AFE294 +:2010260046010156A400AFE2C40094E6010014AD096303564E01008F9AD70156A400C406FE +:20104600461E1F7672031E8A43850156A400C4CC0040CDFF5096AFE2460103564B01008F23 +:201066009AD70156A400AFE2C40020E70800407675B601E861F200B60EE8696694E6080080 +:2010860014AD0865AFE2460012E8401614AD026501B6013B008F8ED71F765E0303564B014B +:2010A60000D50156A4000893A79240769F82005205EC521A0400521A0001013B008F9AD753 +:2010C60003564E01AFE246010156A400AFE2C40020E70800407675B601E861F200B60EE862 +:2010E600696694E6080014AD0865AFE2460012E8401614AD026501B6013B008F8ED71F76A0 +:201106005E0303564E0100D50156A4000893A79240769F82005207EC521A0400509203EDBE +:20112600521A00014D922BED1F767203208A013B43851F7661030156A400C8E2C400AFE29A +:201146003A0194E6010014AD0765521A2000509203ED521A00011F767203228A4385015606 +:20116600A400C8E2C400007794E6010014AD0763521A0800509203ED521A00014392AD5CA9 +:2011860092DC4076BF8292FEBE8B060008FE419600520AED1F765E0305921F765E030696C0 +:2011A6001F765E03052B1F765E0303560001415424651F7672031E8A013B41850156A400E6 +:2011C600C44F1BEF1F7672031E8A41850156A400C42B1F767203215641001E06AC07A98ABE +:2011E600C41A0080008F00DC4192189CA9850156A400C42BEFFFCC00013B008F80DE4185D8 +:201206000156A400C4E2C400007703E244001F7671033F440FEF8CE600004192189CA6BFDB +:20122600120F008F00DCA9850156A400C47EEFFFAF004185008FD8D7408F80D8AFE2440113 +:201246000156A400C8E2C40003564101008F40D80156A50020E3C542418500E711000156C2 +:20126600A400C8E2C40202E8431C10E789000CE8030020E7C800007703E2440050E80048A5 +:2012860000778CE600004192189CA6BF120F008F00DCA9850156A400C47EAFE244008CE635 +:2012A600000000770077A9BF120F4596472B008FA6D741850156A400C492095203ED482886 +:2012C600F4014185008FA6D70156A400C4920A5203EDBF56480A4185008F80DE0156A4008F +:2012E6004192C493485CAD8887DE40762583479243ED1F7672031E8A013B41850156A4006A +:20130600C4CC0040CDFF46961F767203208A41850156A400C492FB9C455409631F767203DE +:201326001E8A41850156A400C4450AEE1F767203208A41850156A400C49245540C63471A09 +:201346002000469219ED471A00011F765E03051A0400126F1F767203228A41850156A40016 +:20136600C49245540963471A1000469205ED1F765E03051A0800479205EC1F765E03051AD5 +:2013860010004192AD5C87DC4076BF8288FE060008FE41961F7672031E8A013B418501568D +:2013A600A400C44F1BEF1F7672031E8A41850156A400C42B1F767203215641001E06AC076B +:2013C600A98AC41A0080008F00DC4192189CA9850156A400C42BEFFFBC004185008F80DE0F +:2013E6000156A400C4E2C400007703E244001F7671033F440FEF8CE600004192189CA6BFFA +:20140600120F008F00DCA9850156A400C47EEFFFA00003564101008F80D80156A400AFE233 +:20142600C40100E7080002E8010990E80028407675B68CE6000000770077A9BF120F4596B9 +:20144600013B4192008F00DC4588189CA9850156A400C47E482B1F7672031E8A41850156DE +:20146600A400C4CC0040CDFF46961F767203228A41850156A400C49245541465481A080001 +:201486004185008FC0D71F7672030156A400C4851E8A0156A400C44305EF469203ED481A44 +:2014A60000011F767203208A41850156A400C49245540763481A2000469203ED481A0001AA +:2014C600419203523865FC9C80FF47961F765D03472D008F00D80E0600D522560190A9885A +:2014E600035647010156A400A828E803A69240769F82019048CDBFFF85FFA8CA4896470AF7 +:201506001F765D03013B472D008F00D800D50E0622560190A988035647010156A400A8282A +:20152600E803A69240769F82019048CD7FFF86FFA8CA4896489207EC469205ED1F765E0325 +:20154600051A02004192AD5C88DC4076BF8288FE06001B76F0FF00E2BD0030E600064229FB +:2015660016562376391110292576006F1B76F0FF00E2BD0030E600064229165623763901EE +:2015860010292576006F1B76F0FF00E2BD0030E60006422916562376390110292576006FDA +:2015A6001B76F0FF00E2BD0030E60006422916562376390110292576006F1B76F0FF00E29B +:2015C600BD0030E600064229165610292576006F1B76F0FF00E2BD0030E600064229165600 +:2015E60010292576006F1B76F0FF00E2BD0030E600064229165610292576006F1B76F0FFCD +:2016060000E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E60006422949 +:20162600165610292576006F1B76F0FF00E2BD0030E600064229165610292576006F1B760F +:20164600F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E6000685 +:201666004229165610292576006F1B76F0FF00E2BD0030E600064229165610292576006FF5 +:201686001B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E6BA +:2016A60000064229165610292576006F1B76F0FF00E2BD0030E6000642291656102925761E +:2016C600006F1B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0021 +:2016E60030E600064229165610292576006F1B76F0FF00E2BD0030E6000642291656102963 +:201706002576006F1B76F0FF00E2BD0030E6000602FE422916561F763300229241962376BB +:201726000100267601011F7633002218FA001F7633002128FFFF1029103B1F7633004192DA +:2017460022962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300229241965C +:2017660023760100267601011F7633002218F8001F7633002128FFFF1029103B1F763300D6 +:20178600419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300229220 +:2017A6004196237601011F76330022921F763300222B1F7633002128FFFF1029103B1F76F8 +:2017C6003300419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330061 +:2017E60022924196237601011F763300221868001F7633002128FFFF1029103B1F763300F8 +:20180600419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330022929F +:20182600419623760100267601011F763300221848001F7633002128FFFF1029103B1F7621 +:201846003300419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300E0 +:201866002292419623760100267601011F76330022921F763300222B1F7633002128FFFFFF +:201886001029103B1F763300419222962576006F1B76F0FF00E2BD0030E6000602FE4229BB +:2018A60016561F7633002292419623760100267601011F763300221878001F7633002128A0 +:2018C600FFFF1029103B1F763300419222962576006F1B76F0FF00E2BD0030E6000602FEE8 +:2018E600422916561F7633002492419623760200267600001F76330024180E001F763300A5 +:201906002128FFFF1029103B1F763300419224962576006F1B76F0FF00E2BD0030E600065C +:2019260002FE422916561F7633002492419623760200267600001F76330024180C001F7699 +:2019460033002128FFFF1029103B1F763300419224962576006F1B76F0FF00E2BD0030E6EF +:20196600000602FE422916561F7633002492419623760200267600001F76330024180800EC +:201986001F7633002128FFFF1029103B1F763300419224962576006F1B76F0FF00E2BD0030 +:2019A60030E6000602FE422916561F7633002492419623760200267600001F763300249224 +:2019C6001F763300242B1F7633002128FFFF1029103B1F763300419224962576006F1B7667 +:2019E600F0FF00E2BD0030E6000602FE422916561F763300249241962376020026760000D4 +:201A06001F76330024180F001F7633002128FFFF1029103B1F763300419224962576006FBB +:201A26001B76F0FF00E2BD0030E6000602FE422916561F7633002492419623760200267602 +:201A460000001F76330024181F001F7633002128FFFF1029103B1F763300419224962576DA +:201A6600006F1B76F0FF00E2BD0030E6000602FE422916561F7633002692419623760400EB +:201A860026763D011F76330026183E001F7633002128FFFF1029103B1F7633004192269638 +:201AA6002576006F1B76F0FF00E2BD0030E6000602FE422916561F76330026924196237614 +:201AC600040026763D011F76330026921F763300262B1F7633002128FFFF1029103B1F7661 +:201AE6003300419226962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633003A +:201B0600269241962376040026763D011F76330026921F763300262B1F7633002128FFFF11 +:201B26001029103B1F763300419226962576006F1B76F0FF00E2BD0030E6000602FE422914 +:201B460016561F763300269241962376040026763D011F763300261826001F763300212808 +:201B6600FFFF1029103B1F763300419226962576006F1B76F0FF00E2BD0030E6000602FE41 +:201B8600422916561F763300269241962376040026763D011F763300261826001F763300A6 +:201BA6002128FFFF1029103B1F763300419226962576006F1B76F0FF00E2BD0030E60006B8 +:201BC60002FE422916561F763300269241962376040026763D011F76330026921F76330012 +:201BE600262B1F7633002128FFFF1029103B1F763300419226962576006F1B76F0FF00E238 +:201C0600BD0030E6000602FE422916561F7633002892419623760800267608011F763300A7 +:201C2600281802001F7633002128FFFF1029103B1F763300419228962576006F1B76F0FFE6 +:201C460000E2BD0030E6000602FE422916561F7633002A92419623760800267608011F76B6 +:201C6600330028921F763300282B1F7633002128FFFF1029103B1F763300419228962576CF +:201C8600006F1B76F0FF00E2BD0030E6000602FE422916561F7633002892419623760800C3 +:201CA600267608011F763300281803001F7633002128FFFF1029103B1F7633004192289682 +:201CC6002576006F1B76F0FF00E2BD0030E6000602FE422916561F763300289241962376F0 +:201CE6000800267608011F763300281803001F7633002128FFFF1029103B1F7633004192F8 +:201D060028962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300289241968A +:201D260023760800267608011F76330028180F001F7633002128FFFF1029103B1F763300E5 +:201D4600419228962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330028924E +:201D6600419623760800267608011F76330028180F001F7633002128FFFF1029103B1F7601 +:201D86003300419228962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330095 +:201DA6002A92419623761000267610011F7633002A1802001F7633002128FFFF1029103B95 +:201DC6001F76330041922A962576006F1B76F0FF00E2BD0030E6000602FE422916561F76F1 +:201DE60033002A92419623761000267610011F7633002A921F7633002A2B1F76330021280F +:201E0600FFFF1029103B1F76330041922A962576006F1B76F0FF00E2BD0030E6000602FE9A +:201E2600422916561F7633002C92419623762000267639011F7633002C1832001F763300D3 +:201E46002128FFFF1029103B1F76330041922C962576006F1B76F0FF00E2BD0030E600060F +:201E660002FE422916561F7633002C92419623762000267639011F7633002C921F7633004B +:201E86002C2B1F7633002128FFFF1029103B1F76330041922C962576006F1B76F0FF00E289 +:201EA600BD0030E6000602FE422916561F7633002C92419623762000267639011F763300B8 +:201EC6002C1833001F7633002128FFFF1029103B1F76330041922C962576006F1B76F0FF0B +:201EE60000E2BD0030E6000602FE422916561F7633002C92419623762000267639011F76C9 +:201F060033002C1837001F7633002128FFFF1029103B1F76330041922C962576006F1B7682 +:201F2600F0FF00E2BD0030E6000602FE422916561F7633002C92419623762000267639012E +:201F46001F7633002C1822001F7633002128FFFF1029103B1F76330041922C962576006F53 +:201F66001B76F0FF00E2BD0030E6000602FE422916561F7633002C92419623762000267697 +:201F860039011F7633002C921F7633002C2B1F7633002128FFFF1029103B1F76330041922E +:201FA6002C962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633002E924196DE +:201FC60023764000267600001F7633002E183E001F7633002128FFFF1029103B1F763300DF +:201FE60041922E962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633002E92A0 +:20200600419623764000267600001F7633002E1838001F7633002128FFFF1029103B1F7600 +:20202600330041922E962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300EC +:202046002E92419623764000267600001F7633002E1838001F7633002128FFFF1029103B95 +:202066001F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE422916561F764A +:2020860033002E92419623764000267600001F7633002E1820001F7633002128FFFF102985 +:2020A600103B1F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE4229165654 +:2020C6001F7633002E92419623764000267600001F7633002E1828001F7633002128FFFFE1 +:2020E6001029103B1F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE422947 +:2021060016561F7633002E92419623764000267600001F7633002E921F7633002E2B1F763B +:2021260033002128FFFF1029103B1F76330041922E962576006F1B76F0FF00E2BD0030E6FD +:20214600000602FE422916561F7633003092419623768000267600001F7633002C921F766B +:2021660033002C2B1F7633002128FFFF1029103B1F763300419230962576006F1B76F0FF51 +:2021860000E2BD0030E6000602FE422916561F7633003092419623768000267600001F76FC +:2021A6003300301801001F7633002128FFFF1029103B1F763300419230962576006F1B760E +:2021C600F0FF00E2BD0030E6000602FE422916561F76330030924196237680002676000062 +:2021E6001F7633002C1823001F7633002128FFFF1029103B1F763300419230962576006FAC +:202206001B76F0FF00E2BD0030E6000602FE422916561F7633003092419623768000267690 +:2022260000001F763300301803001F7633002128FFFF1029103B1F763300419230962576F6 +:20224600006F1B76F0FF00E2BD0030E6000602FE422916561F7633003292419623760001FA +:20226600267600011F76330032921F763300322B1F7633002128FFFF1029103B1F763300AF +:20228600419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633003292F5 +:2022A600419623760001267600011F7633003218FD001F7633002128FFFF1029103B1F76D3 +:2022C6003300419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330046 +:2022E6003292419623760001267600011F763300321871001F7633002128FFFF1029103BF0 +:202306001F763300419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F76A3 +:2023260033003292419623760001267600011F763300321875001F7633002128FFFF1029C3 +:20234600103B1F763300419232962576006F1B76F0FF00E2BD0030E6000602FE42291656AD +:202366001F7633003292419623760001267600011F76330032921F763300322B1F76330044 +:202386002128FFFF1029103B1F763300419232962576006F1B76F0FF00E2BD0030E60006C4 +:2023A60002FE422916561F7633003292419623760001267600011F76330032921F76330052 +:2023C600322B1F7633002128FFFF1029103B1F763300419232962576006F1B76F0FF00E238 +:2023E600BD0030E6000602FE422916561F7633003292419623760001267600011F763300C5 +:20240600321831001F7633002128FFFF1029103B1F763300419232962576006F1B76F0FFBB +:2024260000E2BD0030E6000602FE422916561F7633003292419623760001267600011F76D5 +:202446003300321875001F7633002128FFFF1029103B1F763300419232962576006F1B76F3 +:20246600F0FF00E2BD0030E6000602FE422916561F7633003892419623760008267600002F +:202486001F76330038189E001F7633002128FFFF1029103B1F763300419238962576006F7A +:2024A6001B76F0FF00E2BD0030E6000602FE422916561F763300389241962376000826765E +:2024C60000001F76330038189C001F7633002128FFFF1029103B1F763300419238962576AB +:2024E600006F1B76F0FF00E2BD0030E6000602FE422916561F76330038924196237600084B +:20250600267600001F763300381890001F7633002128FFFF1029103B1F7633004192389675 +:202526002576006F1B76F0FF00E2BD0030E6000602FE422916561F76330038924196237677 +:202546000008267600001F763300381890001F7633002128FFFF1029103B1F7633004192FB +:2025660038962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633003892419602 +:2025860023760008267600001F76330038921F763300382B1F7633002128FFFF1029103BA8 +:2025A6001F763300419238962576006F1B76F0FF00E2BD0030E6000602FE422916561F76FB +:2025C60033003892419623760008267600001F76330038189F001F7633002128FFFF1029E5 +:2025E600103B1F763300419238962576006F1B76F0FF00E2BD0030E6000602FE4229165605 +:202606001F7633003892419623760008267600001F76330038921F763300382B1F76330089 +:202626002128FFFF1029103B1F763300419238962576006F1B76F0FF00E2BD0030E600061B +:20264600422916562576006F1B76F0FF00E2BD0030E60006422916562576006F1B76F0FFF7 +:2026660000E2BD0030E60006422916562576006F02FE412B4192805209674158008F00DC33 +:20268600942B410A41928052F9681F767103BF5624051F765D0308921F7671033E961F76DC +:2026A6007103BF56250A1F767103BF56265F1F767103BF5627011F765D030792015277ED2E +:2026C6001F767203208ABF56C4371F767203208ABF56CC371F767203208ABF56D4371F76FB +:2026E6007203208ABF56DC371F767203208ABF56E4411F767203208ABF56EC411F7672039F +:20270600208ABF56FC321F767203208A08D0BF5694321F767203208A09D0BF5694321F7662 +:202726007203208A0AD0BF5694321F767203208A0BD0BF5694321F767203228ABF56C43294 +:202746001F767203228ABF56CC321F767203228ABF56D4321F767203228ABF56DC321F766B +:202766007203228ABF56E43C1F767203228ABF56EC3C1F767203228ABF56FC2D1F7672030C +:20278600228A08D0BF56942D1F767203228A09D0BF56942D1F767203228A0AD0BF56942D0E +:2027A6001F767203228A0BD0BF56942D1F765D030C9226ECBF56410C41921052116741585F +:2027C6001F767203208A94287C0941581F767203228A9428B605410A41921052F1681F76CA +:2027E60070030C1A00401F7670030D1A00401F7670030E1A00401F7670030F1A00401F7615 +:202806005D030692065209ED1F767103BF5620C81F767103BF56211405527AED1F7670034D +:20282600021A00401F767003031A0040412B419211526E674158008FA6D7949203520CED41 +:202846001F767203228A94282C0141581F767203208A9428AE014158008FA6D794920452FA +:202866000CED1F767203228ABF5694AA41581F767203208ABF5694FA4158008FA6D7949295 +:2028860005520CED1F767203228ABF56941441581F767203208ABF5694284158008FA6D7AC +:2028A6009492065204EC949207520CED1F767203228ABF56940F41581F767203208ABF565C +:2028C600941E4158008FA6D7949208520CED1F767203228ABF56940A41581F767203208A6C +:2028E600BF5694144158008FA6D7949209520CED1F767203228ABF56943C41581F767203B8 +:20290600208ABF569441410A41921152946882FE0600BDB202FE008F00DC1F7672031EA870 +:202926001F767203008F30DC20A81F767203008F48DC22A8A9287E3FA8280201008FC0DC11 +:202946004076ED9E809A008FC0DC407619B4429642881F767503000EA60F38ED42880129DD +:2029660020FFFFFFA60F32EC1F7674033E0E1F765D030888A60F2AED412B419280520D6733 +:2029860041584159008FC0DC9492008F00DC9C96410A41928052F5681F7671033F2B1F76BB +:2029A6005D030792035219ED1F767103209205ED1F767103BF5620C81F76710321920DED54 +:2029C6001F767103BF562114086F407635911F7671033F2B4076FD92412B419204520E67E9 +:2029E6004158008FD8D741590CD89492008F70DC9C96410A41920452F46882FEBE8B0600AA +:202A0600BDB202FE422B412B4192805217674158008F00DC940E008FC0DC9488A60F0AECAD +:202A26004159008F00DC9492008FC0DC9C96BF564201410A41928052EB68429211EC008F0D +:202A4600C0DC809A407619B41F7675030096008FC0DCA8280201A9287E3F4076A39E82FE91 +:202A6600BE8B06000CFE1F765D0307920152C0565D01442B44920C52E3FFB40003564402CA +:202A860045964592407672B3429620FFF4014076DEB94592019C407672B3419620FFF40130 +:202AA6004076DEB94592469C407672B3439620FFF4014076DEB9029AAD5C82DC407619B46F +:202AC6004388A90EA60F12EC013B008FA6D744850156A400C492095206ED42284A01BF5641 +:202AE600411E046F422B4128110142924696C4E24100007703E24A004592029C407672B389 +:202B0600429620FFF4014076DEB94592039C407672B3419620FFF4014076DEB94592489C32 +:202B2600407672B3439620FFF4014076DEB9029AAD5C82DC407619B44388A90EA60F13ECBE +:202B4600013B008FA6D744850156A400C492095206ED4228A00F41286801056F4228CE0E1A +:202B66004128D90142924796C4E24100007703E24C00013B4688008FD8D744850156A400C0 +:202B8600C47EAFE24A008CE6000000770077A6BF120F008F40D844850156A400C47EAFE2EE +:202BA6004C014792AFE24A00469E20E70800A985A9BD160F007700770077007789E609000E +:202BC600407675B6013B008F80D8035644010156A40003E2C400440A44920C52E4FF50FFF5 +:202BE600BF56440C44921052E3FF8A000356440245964592407672B3429620FFF4014076F8 +:202C0600DEB94592019C407672B3419620FFF4014076DEB94592469C407672B3439620FF04 +:202C2600F4014076DEB9029AAD5C82DC407619B44388A90EA60F04EC4228FF07412B4292EF +:202C46004696C4E24100007703E24A004592029C407672B3429620FFF4014076DEB94592A5 +:202C6600039C407672B3419620FFF4014076DEB94592489C407672B3439620FFF401407663 +:202C8600DEB9029AAD5C82DC407619B44388A90EA60F04EC42280609412B42924796C4E2AE +:202CA6004100007703E24C00013B4688008FD8D744850156A400C47EAFE24A008CE600008A +:202CC60000770077A6BF120F008F40D844850156A400C47EC8E2470002E8D123407675B61D +:202CE600013B008F80D8035644010156A40003E2C400440A44921052E4FF7AFF442B449242 +:202D0600045213630C9C013B008FD8D7A9850156A400C488008F70DC44850156A400C47E69 +:202D2600440A44920452EF641F765D0307920252C056DF00442B44921152E3FFDA0003562C +:202D4600440245964592407672B3429620FFF4014076DEB94592019C407672B3419620FF1C +:202D6600F4014076DEB94592469C407672B3439620FFF4014076DEB9029AAD5C82DC407684 +:202D860019B44388A90EA60F11EC013B008FA6D744850156A400C492095206ED42286306A9 +:202DA600BF5641F0036F422B412B42924696C4E24100007703E24A004592029C407672B3EF +:202DC600429620FFF4014076DEB94592039C407672B3419620FFF4014076DEB94592489C70 +:202DE600407672B3439620FFF4014076DEB9029AAD5C82DC407619B44388A90EA60F3AECD5 +:202E0600013B008FA6D744850156A400C492095206ED4228B30F41284E022C6F4485008F24 +:202E2600A6D70156A400C492035206ED422892094128D80E1F6F4485008FA6D70156A400C4 +:202E4600C492045206ED4228920941289808126F4485008FA6D70156A400C492075206EDCC +:202E6600BF564201BF5641F0056F42289209BF5641F042924796C4E24100007703E24C00AF +:202E8600013B4688008FD8D744850156A400C47EAFE24A008CE6000000770077A6BF120F1D +:202EA600008F40D844850156A400C47EAFE24C014792AFE24A00469E20E70800A985A9BD46 +:202EC600160F007700770077007789E60900407675B6013B008F80D8035644010156A400D6 +:202EE60003E2C400440A44921152E4FF2AFF8CFE060006FE42A8428A11D0949244964283A0 +:202F0600428A12D00356950813D094CA4596428A1F767503008DA10137929496428A008D97 +:202F2600A201BF569403428A008DA301035645019496462B459246542A694692008F00DCBE +:202F46004494A95894CC00FFC7FFA98803564601A95D008DA101420603DDA50DA98A947E48 +:202F66004692008F00DC4494A9589492FF90A98803564601A95D008DA101420604DDA50D99 +:202F8600A98A947E460A45924654D8664328FFFF03564501A988008FA101435D420603DEB4 +:202FA6000156A400A60E4076C5B3439603564501A95D008DA101420603DDA50DA98A43929F +:202FC600FF90949603564501A95D420604DDA50DA98A4392A7FFFF90949603564501A95DA6 +:202FE60005DD4206A50DA98A942B03564501A95D06DD4206A50DA98A942B03564501A95DE4 +:2030060007DD4206A50DA98A942B03564501A95D08DD4206A50DA98A942B428A008D9E016C +:20302600BF569401408FA10103564501089C428AA98842060156A500A6064076FF9886FE6E +:20304600060006FE42A8452B459208521267458042060ED04588A70DA98A42069480008DD4 +:20306600A101A60DA98A947F450A45920852F068428A11D0949243964283428A12D003565F +:20308600950813D094CA449643584492008F00DC9496428A008D9E01BF5694014206408FB3 +:2030A600A101428A0156A5000A024076FF9886FE060004FE42A8428AC48AEC4616EE1F76EC +:2030C60033002192A9CDFFFEC7FF1F76330001900150019087FFA8CA2196428AC48A0BDCE0 +:2030E600C41A4000EFFF8201428AC48AFC92FF904396428AC48AEC470AEF428AC48ACC18E7 +:20310600DFFF428AC48ACC1A2000D66F428A008DA0019492D1ED428A008D3B039492015278 +:2031260016ED428A008D3D03BF569401428A0002008D3403941E428A008D3F03942B428AD9 +:20314600008D3E03942B428A0DD0942B428A008D3F039492B1ED428A008D3D039492C1563F +:20316600E600428A008D3E0394924CED1F7604030292435420EC1F7675033792435403ED3A +:20318600005219ED428A4388008D3103940EA60F06ED428A008D330394920DED1F76750373 +:2031A6003692435424ED005222EC428A008D330394921DED428A4392008D320394964206A5 +:2031C600013B008F3E030156A400019BC492A995C497428A4388A9850ED00156A400947EA7 +:2031E600428A089A4076E098EFFF67FF428A008D3F03BF569401428A008D3D03942BEFFF4E +:203206005CFF4206008F3E030156A400019BC492A995C4974388428A013B0ED0A985015679 +:20322600A400947E428A008D3E039492075210ED428A0DD0949210520BED428A008D330304 +:20324600949206ED43921F765C030A9C1096428A008D3E039492025240ED428A43920DD07B +:203266009496428A0DD0949203521868428A0DD0949242521366428A0DD09458008F00D7A3 +:20328600949203520B68428A0DD0949233521CED428A0CD094923A5217EC428A099A40765B +:2032A600E098428A008D3E03942B428A008D3D03BF569401428A008D3F03942B428A0DD0F1 +:2032C600942BEFFFFAFE428A0DD09492335205ED428A008D3D03942B428A0DD0945842834B +:2032E600008F00D79492008D3E0395540869428A9485008F9001A40FE8FFDFFE428A099A29 +:203306004076E098428A008D3D03942B428A008D3F03BF569401428A008DA001BF56940138 +:20332600428A0DD0942BEFFFC8FE428AF4C4208F0000A9A8A60F0866428AF4C42F8F000082 +:20334600A9A8A60F08674283208F0000F5A842830AD095A8428A0CD094923A52C056ADFEEA +:20336600428A008DA001949208EC428A008D3F03BF569401EFFFA1FE4206008F34030156FC +:20338600A400C4C4A692019001DEC4C2449609EC4283F58AA9A80109F51E4392C498066FA6 +:2033A600428AF48A03564308C496428A4283008D34039406E50FE8FF80FE428A339A0FD0FF +:2033C6009496428A0CD09496428A099A4076E098428A008D3F03BF569401428A008DA0010F +:2033E600BF569401EFFF69FE84FE060004FE42A8428A008D3A0394923CED01BE4206008FD9 +:2034060038030156A400A606C407C41E428A008D3603940F0568428AC48ABF56E402428A94 +:2034260008D0948A428308D0849295A8428AC48A09D09496428A4283008D36039406008D05 +:203446003803950F5466428AC48AE446FDEF428A099A4076E098428AD492025205ED1F76F3 +:20346600BF01081A0400428A008D9E01942B3F6F4206008F38030156A400C4C4A69201909D +:2034860001DEC4C24396428A4283008D36039406008D3803950F0566428AC48ABF56E4020B +:2034A60043920EEC428A08D0948A428308D0849295A8428AC48AFF9009D094960B6F428A93 +:2034C60008D0948A4283C492C58AA7FF09D0FF909496428A4283008D36039406008D380395 +:2034E600950F0566428AC48AE446FDEF1F7633002192A9CDFFFEC7FF1F7633000190015029 +:20350600019087FFA8CA219684FE060002FE412B419246520D63013B41854188008F00D765 +:203526000156A400C47E410A41924652F5641F765C03BF56330C1F765C03BF56340C1F7613 +:203546005C03BF5635081F765C03BF5636091F765C03BF5637101F765C03BF5638081F763E +:203566005C03BF56390C1F765C03BF563A0C1F765C03BF563B051F764D0304921F765C0385 +:20358600FE9C3D961F764D0304921F765D03FF9C01961F765C03BF563E081F765C03BF56BE +:2035A60003081F765C03BF5606081F765C03BF56100D1F765C03BF56051B1F765C03BF568B +:2035C6003C1282FE060004FE439642A808520BED089A428A01D54E9B4076949A428A008D90 +:2035E6003B03942B439209520CED089A428A01D54E9B4076949A428A008D3B03BF5694014D +:2036060084FE060008FE461E44A042A8472B471B30750566470A471B3075FD69428AD49210 +:20362600025205ED1F76BF010818FBFF472B471B10270566470A471B1027FD69428A4606F1 +:20364600008D3603941E428A440608D00109941E428A008D3A03942B428AC48AE446FDEFBD +:20366600428A089A4076E098428A008D38030102941E460F0C67428AC48ABF56E401428AB7 +:203686004483C48A09D0C59294961F6F428A4483C48A09D0C5929496428AC48AE446FDEFBC +:2036A600472B471BE8030566470A471BE803FD69428A099A4076E098428AD492025205EDC1 +:2036C6001F76BF01081A0400009A88FE060006FE461E44A042A8428AD492025205ED1F7600 +:2036E600BF010818FBFF428A4606008D3603941E428A08D04406941E428A008D3A03BF560F +:203706009401428AC48AE446FDEF428A089A4076E098428A008D38030102941E428AC48ADF +:20372600BF56E401448A4283C492C58AA7FF09D0FF909496009A86FE060006FE441E42A8A5 +:203746001F766F0384E2440188E23A0050E80940407675B688E60000007703E24600428ACF +:20376600C48A4692A7FFFF90D496428AC48A4692FF90DC9686FE060002FE41961F764D0345 +:2037860004961F764003BF5602011F764E03BF56020282FE060008FE417C441E41920152C9 +:2037A60031ED008F50701F76400300A8008F00D048A822761F76BE0109CCFFF31F76BE01C0 +:2037C600A91A000409961F76BE0109CCFFFC1F76BE01A91A000109961F763700008FAAB1EC +:2037E60000A81F763700008F42B202A81F763300321A01001F763300321A0200237600015D +:203806001A764192025239ED008F50771F764E0300A8008F80D348A822761F76BE0107CC50 +:20382600FFCF1F76BE01A91A002007961F76BE0107CCFF3F1F76BE01A91A008007961F76B2 +:20384600BE011618CFFF1F76BE011A1A04001F763700008FF7B104A81F763700008F8DB2D2 +:2038660006A81F763300321A04001F763300321A0800237600011A76488A4192D496488A55 +:20388600C406461E01D569FF488A089A4E9B4076949A468A0CDCC41A0040468A0CDCC4180B +:2038A600FFDF468ACC18BFFF468ACC18DFFF468ACC18F7FF468ACC18FBFF468ACC1A020010 +:2038C600468ACC1A0100468A0ADCC418FFBF468A0BDCC4CCE0FF0150C49640768398488A67 +:2038E600440640769A99488AD492025205ED1F76BF01081A0400488AC48ABF56E402488AA9 +:20390600099A4076E098488A0CD0942B488A008D9E01942B488A008D3303942B468A0BDC9B +:20392600C41A4000468ACC1A200088FE060008FE457D4497439642A8428AC406481E4392CA +:203946001D6509521B63488AFF9C0790C4CDF8FFA8CAC496136F488AC418DFFF166F488A49 +:20396600C41A2000488AC418BFFF0F6F488AC41A2000488AC41A4000086F44924552F7ECD2 +:203986004E52EAEC4F52ECEC4592015204ED488AC4187FFF4592025204ED488AC41A80009F +:2039A600488AC418EFFF488AC418F7FF88FE060002FE42A8428A0002008D4203941E82FE79 +:2039C600060002FE42A882FE060002FE421E428AC49282FE060004FE437C421E428A4392A1 +:2039E600C49684FE060006FE42A8428A008DA001949271EC428A942B428A0FD0949243963F +:203A0600013B4385008F00D70156A400C492035209684385008F00D70156A400C41B900186 +:203A26001069428AD492025205ED1F76BF01081A0400428A099A4076E098A928FFFF4D6FEC +:203A46004392335207ED428A43920CD094964392446F4385008F00D70156A400C48042062E +:203A6600008F00D782DFA70DA61E43850156A400C48042060ED081DFA70DA98A0356940898 +:203A86000ED0A68A94CA44964528FFFF428A408F00D743850156A500C592FE9C455D0EDCBC +:203AA600A90E4076C5B345964488450EA60F07ED428A43920CD0949643920F6F428AD4924C +:203AC600025205ED1F76BF01081A0400428A099A4076E098A928FFFF86FE060004FE43964E +:203AE60042A81F765D03BF563F01428A4283008D32039492008DA1019596428A008DA201BD +:203B0600439294964428FFFF4206008FA101445D0156A40002024076C5B34496428A008DBC +:203B2600A301FF9094964492428A008DA401A7FFFF909496428A008DA501942B428A008DD8 +:203B4600A601942B408FA1014206428A0156A50006024076FF9884FE06000AFE461E44A843 +:203B6600AC281F0046C5013B44C42256A70740FF0156A60048C2488AC49249960202421E26 +:203B86004606C000B8B804EC49CCFF00046F4992A7FFFF908AFE060002FE42A882FE06001E +:203BA60004FE42A8428A13D09492FF90A90E441E428A12D09492FF90A988440637FFA6AF2D +:203BC600441E428A11D09492FF90A988440637FFA6AF441E428A10D09492FF90A9884406D7 +:203BE60037FFA6AF441E428A17D09492428AFF90A90EE41E428A16D09492428AFF90A98881 +:203C0600E406428A37FFA6AFE41E428A15D09492428AFF90A988E406428A37FFA6AFE41EB5 +:203C2600428A14D09492428AFF90A988E406428A37FFA6AFE41E428A02020156E400428A02 +:203C46004406F41E428A0AD04406941E428A3A9A40766B9B84FE060004FE42A8428AE406DA +:203C6600428A0AD00219948A4076AA9B428AA95DE406428A0AD00119948A4076AA9B035676 +:203C8600A908A5944496428A4283008D320394920ED09596428A0FD0BF5694334328FFFFE8 +:203CA600428A435D02020EDC4076C5B34396428AE406428A435D0AD00219948A4076E6B319 +:203CC60043964388440EA60F0BED428A339A40766B9B428A008D3C03BF569401116F428A58 +:203CE600008D3C03942B428AD492025205ED1F76BF01081A0400428A099A4076E09884FE21 +:203D0600060002FE42A882FE060006FE42A81F765D03BF563F01428A13D09492FF90A90ED4 +:203D2600441E428A12D09492FF90A988440637FFA6AF441E428A11D09492FF90A988440673 +:203D460037FFA6AF441E428A10D09492FF90A988440637FFA6AF441E2FFF0040440F086678 +:203D66004318FF0F4492407672B34596146F2FFF0020440F0A664318FF0FAD5C4492029BCF +:203D860085DC4076ED9E076F4318FF0F44064076E29A4596428A4283008D32039492008D3F +:203DA600A1019596428A008DA201BF569438428A4592008DA301FF9094964592428A008D96 +:203DC600A401A7FFFF909496428A008DA501942B428A008DA601942B4628FFFF008FA101BF +:203DE6004206465D0156A40006024076C5B34696428A008DA7014692FF9094964692428A8F +:203E0600008DA801A7FFFF909496428A008DA901942B428A008DAA01942B408FA1014206C9 +:203E2600428A0156A5000A024076FF9886FE060006FE42A8428A13D09492FF90A90E441E66 +:203E4600428A12D09492FF90A988440637FFA6AF441E428A11D09492FF90A988440637FF7E +:203E6600A6AF441E428A10D09492FF90A988440637FFA6AF441E452B428A15D0459394929D +:203E8600A8384596428A14D045939492A83845962FFF0004440F08664318FF0045934492FD +:203EA60040761EB3146F2FFF0002440F0A664318FF00AD5C4492029B85DC4076A39E076F5B +:203EC6004318FF00455C44064076E89A428A399A40766B9B86FE060008FE42A81F765D0395 +:203EE600BF563F01428A13D09492FF90A90E441E428A12D09492FF90A988440637FFA6AF81 +:203F0600441E428A11D09492FF90A988440637FFA6AF441E428A10D09492FF90A988440693 +:203F260037FFA6AF441E428A17D09492FF90A90E461E428A16D09492FF90A988460637FFF1 +:203F4600A6AF461E428A15D09492FF90A988460637FFA6AF461E428A14D09492FF90A9883A +:203F6600460637FFA6AF461E428A4283008D32039492008DA1019596428A008DA201BF561C +:203F86009434008FFFFF48A8008FA101485D42060156A40002024076C5B3A90E481E485DC9 +:203FA600448A46064076E6B3A90E481E408FA1014206428A0156A50001024076FF98428AD8 +:203FC600008DA101BF569434408FA1014206428A0156A50001024076FF98428AC48AE446BA +:203FE600FDEF44834606428A40766499428AC48AE446FDEF428A4892008DA101FF9094967F +:204006004892428A008DA201A7FFFF909496428A008DA301942B428A008DA401942B408F1D +:20402600A1014206428A0156A50006024076FF9888FE060002FE42A882FE060002FE42A88D +:2040460082FE06000AFE42A8428A13D09492FF90A90E441E428A12D09492FF90A988440687 +:2040660037FFA6AF441E428A11D09492FF90A988440637FFA6AF441E428A10D09492FF9022 +:20408600A988440637FFA6AF441E428A17D09492FF90A90E461E428A16D09492FF90A98897 +:2040A600460637FFA6AF461E428A15D09492FF90A988460637FFA6AF461E428A14D0949217 +:2040C600FF90A988460637FFA6AF461E428A1BD09492FF90A90E481E428A1AD09492FF90EB +:2040E600A988480637FFA6AF481E428A19D09492FF90A988480637FFA6AF481E428A18D0BC +:204106009492FF90A988480637FFA6AF481E428A1CD09492FF9049960F6F4406468A48C484 +:20412600A6934076A39E0D6F4406468A48C4A6934076ED9E066F0452F1EC0552F6EC056FD8 +:20414600428A3C9A40766B9B8AFE060006FE459744A841961F7675030002301E1F763000A8 +:2041660014282040008F42DD4076C39F0052FBEC45934592D0FF0190A89445962CEC41928D +:20418600209B1F90A99F4697459246540267469644061F7675030E1E1F767503460E101EC2 +:2041A6001F76750303564101A90E121E008F42DD408F4EDD4076CE9F008F42DD4076C39FD9 +:2041C6000052FBEC460E015644004692417245744592D6ED1F7630001428104086FE0600F8 +:2041E60006FE459744A841961F7675030002301E1F76300014282040008F42DD4076C39F92 +:204206000052FBEC45934592D0FF0190A89445962CEC4192209B1F90A99F4697459246544E +:204226000267469644061F767503141E1F767503460E161E1F76750303564101A90E181E80 +:20424600008F42DD408F54DD4076D99F008F42DD4076C39F0052FBEC460E015644004692B6 +:20426600417245744592D6ED1F7630001428104086FE060002FE1F767503008F42DD06C5D1 +:20428600673E22761F763400008F71B81CA81A7669FF4076E7B51F766F030F8F40423806E7 +:2042A60042A8C000A9B8A9BD120F0077007702E84116008F6EDD89E6000040763AB62376AF +:2042C600002082FE060004FE44A822761F76BE0108CCFCFF1F76BE01015008961F76BE01F2 +:2042E60008CCF3FF1F76BE01045008961F76BE0108CCCFFF1F76BE01105008961F76BE0110 +:2043060008183FFF1F76BE010B1A08001F76BF010118F7FF1A761F76C101BF5600071F76BC +:20432600C101BF56011F1F76C101022B69FF018FA0861F766F033A0642A8C000A9B81F76F7 +:20434600C101FF9C04961F76C1010A2800801F76C1010B2B1F76C1010C2B1F76C101BF56D0 +:204366000F10448AD42B448A0002C41E1F76C101001A800084FE06001F76BF01011A0800A8 +:2043860006001F76BF010118F7FF060002FE42A8428AD492039003EC009A026F019A82FEE3 +:2043A600060004FE44A042A8428A4406C41E428AD41A010084FE060004FE44A042A8428A4A +:2043C6004406C41E428AD41A020084FE060002FE42A8EFFFAD01428AD4400CEF1F767503F9 +:2043E600BF561B01428AD41A0400428A0AD094C5673E428AD441CC56AD011F767503BF5651 +:204406001B0D428AD41A0800428A0AD094C5673EEFFFA0011F76C101BF5600871F76C1012F +:20442600082800061F76C101021A20001F767503BF561B02EFFF8E011F76C1010246CC5630 +:2044460089011F76C10107921F7675031D96428A08D094C5673E1F767503BF561B03EFFF4C +:204466007901428A0AD094C5673E1F76C101BF5600871F76C101082800021F76C101021A29 +:2044860020001F767503BF561B04EFFF63011F76C1010246CC565E011F76C10107921F76BE +:2044A60075031D961F767503BF561B05EFFF52011F76C101BF56008F428AC48A1F76C101DC +:2044C600E49208961F76C101021A20001F767503BF561B06EFFF3E011F76C1010246CC56FE +:2044E60039011F76C10107921F7675031D961F767503BF561B07EFFF2D011F76C101BF5600 +:20450600008F428AC48A1F7675031C58C48A1F76C101949208961F7675031C0A1F76C10178 +:20452600021A20001F767503BF561B08EFFF12011F76C1010246CC560D011F76C101079234 +:204546001F7675031D96428AC48A1F7675031C0ED40F0BED428A08D094C5673E1F767503BA +:20456600BF561B09EFFFF6001F767503BF561B07EFFFF000428A0AD094C5673E1F76C101FB +:20458600BF5600871F76C101082800051F76C101021A20001F767503BF561B0AEFFFDA004B +:2045A6001F76C1010246CC56D5001F76C10107921F7675031D961F767503BF561B0BEFFF79 +:2045C600C9001F76C101082B1F76C101021A20001F767503BF561B0CEFFFBC001F76C101A5 +:2045E6000246CC56B700428A08D094C5673E1F76C101074007EF1F767503BF561B09EFFF2A +:20460600A900428AD418FBFF428AD418FEFF1F7675031B2B1F7675031C2BEFFF9B001F76BF +:20462600C101BF5600871F76C101082800031F76C101021A20001F767503BF561B0EEFFFC0 +:2046460089001F76C1010246CC5684001F76C10107921F7675031D961F767503BF561B0F8A +:20466600786F1F76C101BF56008F428AC48A1F76C101E49208961F76C101021A20001F76A5 +:204686007503BF561B10656F1F76C101024661EF1F76C10107921F7675031D961F767503DC +:2046A600BF561B11566F1F76C101BF56008F1F76C101082B1F76C101021A20001F767503C9 +:2046C600BF561B12466F1F76C101024642EF428AC48A1F7675031C58C48A1F76C101079234 +:2046E60094961F7675031C0A1F767503BF561B13306F428AC48A1F7675031C0ED40F12ED35 +:20470600428A08D094C5673E1F7675031B2B1F7675031C2B428AD418F7FF428AD418FDFFE8 +:20472600186F1F767503BF561B11136F1F7675031B9213520E660356A901C07604C1A9885A +:20474600A706A60DA71EA92401DFA824A71E207682FE060002FE22761F76BE0106180000CA +:204766001F76BE01071800FF1F76BE0108183F001F76BE01091800FF1F76BE011618C0FC5C +:204786000F8F00F0ABA81F76BE01AB93AA9218C11F76BE0119C01F76BE010B18EFFF1F7664 +:2047A600BE010B18DFFF1F76BE010B18BFFF1F76BE011B18F7FF1A761F765D03062B422B5E +:2047C600412B419264521063009A009B1F76BF01014602EF019B005302ED019A4272410A31 +:2047E60041926452F2644292325204651F765D03060A422B412B419264521063009A009B04 +:204806001F76BF01014402EF019B005302ED019A4272410A41926452F264429232520565EE +:204826001F765D0306080200422B412B419264521063009A009B1F76BF01014502EF019B3B +:20484600005302ED019A4272410A41926452F2644292325205651F765D03060804001F7639 +:204866005D03035606011F765D0308961F765D03060A422B412B419264521063009A009BD0 +:204886001F76BF01094302EF019B005302ED019A4272410A41926452F26442923252046568 +:2048A6001F765D03080A1F765D030692015203EC025205ED1F765D03BF560C01015207EC79 +:2048C600025205EC035203EC045205ED1F765D03BF560701055205ED1F765D03BF56070293 +:2048E600065205ED1F765D03BF5607032276256F088F00001F76BE010AA8079AA82813DC2B +:204906001F76BE011A1E226F088F00001F76BE010AA8049AA82801D01F76BE011A1E166F87 +:204926002FFF101A1F76BE010A1E059AA82821081F76BE011A1E0A6F1F765D03079201521F +:20494600D8EC0252E2EC0352ECEC1A7682FE69FF060002FE0002421E1F765D03079201527D +:204966004DED1F76BF01004706EE00021F765D03281E0D6F038F90D01F765D03A9A8280F3F +:20498600066501021F765D0301562800038F90D01F765D03A9A8280F03650102421E1F7660 +:2049A600BF01004606EE00021F765D032A1E0B6FA9A81F765D032A0F066501021F765D035C +:2049C60001562A00A9A81F765D032A0F046502024207421E1F765D03069203520F631F76D2 +:2049E600BF01014A04EE04024207421E1F76BF01014704EE08024207421E1F765D03079235 +:204A06000252C056CF001F76BF01094A04EF01024207421E1F76BF01094D04EF0202420725 +:204A2600421E1F76BF01094504EF10024207421E1F76BF01094404EF20024207421E1F76CA +:204A4600BF01014804EF40024207421E1F76BF01014704EF80024207421E1F76BF01014B0D +:204A660005EF20FF00014207421E1F76BF01014A05EF20FF00024207421E1F76BF01084474 +:204A860005EF20FF00044207421E1F76BF01014905EF20FF00084207421E1F76BF01004058 +:204AA60005EF20FF00104207421E1F76BF01004205EF20FF00204207421E1F76BF01004418 +:204AC60005EF20FF00404207421E1F76BF01004606EF012920FF00804207421E1F76BF017D +:204AE600004806EF018F0000A9A84207421E1F76BF01004A06EF028F0000A9A84207421ECA +:204B06001F76BF01004105EF42061FFF8000421E1F76BF01004305EF42061FFF0001421E6C +:204B26001F76BF01004705EF42061FFF0002421E1F76BF01004905EF42061FFF0004421EBB +:204B4600009A1F76BF0100BE004102EF019A005202ED01BE009A009B1F76BF01004302EF17 +:204B6600019B005302ED019AA6CA1F765D031F96009A1F76BF0100BE004702EF019A0052CA +:204B860002ED01BE009A009B1F76BF01004902EF019B005302ED019AA6CA1F765D03209609 +:204BA6001F765D030792035208ED1F76BF01094E04EE01024207421E42061F765D030E1E64 +:204BC60082FE060004FE407655AB103B69FF407681B7267600002F76000040767BB940760F +:204BE600FDB6407657B71F76BF010C1A01001F76BF010B1A0100412B41920A521263012907 +:204C060020FF50C340766BB71F76BF010F1A01001F76BF010E1A0100410A41920A52F064B9 +:204C26001F76BF010A1A01001F76BF010B1A01004076A7A11F765D03109B06924076C9B90B +:204C46000D9A4076B99901D4418F00C2A9A04076C89902D4418F00C2A9A04076C8991F767B +:204C66005D03009A08934076E3A54076379F4076D3B84076D0B71F765D03079203520FEC73 +:204C86004076B3AE407670804076FCB2078F20A1A9A840766BB740762F93056F4076BEB558 +:204CA60040764F8040768692407619821F765D0308921F7671033E96412B419203521263D5 +:204CC600013B008FE2DE41850156A400C42B008FE5DE41850156A400C42B410A419203521E +:204CE600F06422761F76C001BF56292F1A761F767A03BF5631011F767B03219206EC1F76C9 +:204D06007B03210BEFFFA1001F767B0321280010412B41920352E3FF9800013B008FE2DE4F +:204D260041850156A400C49209EC4185008FE2DE0156A400C40BEFFF83004185008F65DC7B +:204D46000156A400C488008FE2DE41850156A400C47E008FE8DE41850156A400C42B69FF47 +:204D66001C6F4185008FE5DE0156A400C4926F520E654185008FE5DE0156A400C42B008F74 +:204D8600E8DE41850156A400C40A076F4185008FE5DE0156A400C40A013B008FE5DE41850D +:204DA6000156A400109BC492C0002CB9013BA9884185412D008FE5DE0156A4000931C493CD +:204DC600A892A2FF008FA4DCCBFFA894A3FFA985A71EA6160156A400A7060156A400C49392 +:204DE60063FFA84009EE4185008FE8DE0156A400C4920252B7644185008FE5DE0156A4007E +:204E0600C4926F521C624185008FE8DE0156A400C492025214634185008FE5DE0156A400AD +:204E2600009AC493008F00DC407609A7013B008FE5DE41850156A400C4080300410A41926E +:204E46000352E4FF6CFF1F7671033F4208EF1F7671033F18FBFF69FF4076FD921F76710318 +:204E66003F4508EF1F7671033F18DFFF69FF40762F931F7671033F4308EF1F7671033F18B1 +:204E8600F7FF69FF4076359169FF4076A6A21F765D030792025207EC1F765D030E921F76CD +:204EA60070031796412B41920252E3FF26FF005205EC008F00D044A8046F008F80D344A863 +:204EC600448A4076F09A4296A91BFFFF79EC596F448A4076C99B1F76BF010F1A0100706FB1 +:204EE600448A4076CD9B1F76BF010F1A0100686F448A40767E9C1F76BF010F1A0100606F7E +:204F0600448A4076299C1F76BF010F1A0100586F448A4076829C1F76BF010F1A0100506F1C +:204F2600448A4076159D1F76BF010F1A0100486F448A4076699D1F76BF010F1A0100406F47 +:204F4600448A40761F9E1F76BF010F1A0100386F448A40761B9E1F76BF010F1A0100306F89 +:204F6600448A407676951F76BF010F1A0100286F448A40761E961F76BF010F1A0100206F40 +:204F8600375211623752E5EC335208623352B9EC0352E7EC0652EDEC136F3452CAEC3552FE +:204FA600A8EC0E6F3A5208623A529BEC3852B1EC3952B7EC056F3B528CEC3C52C2EC410A7C +:204FC60041920252E4FF75FFEFFF97FE3EFE42974196A92800E0A8281C807E1E42920263EC +:204FE600422B42920F520365BF56420F227641921DED008F006078A8008F00617AA8008F16 +:20500600C0607CA81F76BE0109CCFFCF1F76BE01A91A001009961F76BE0109CCFF3F1F768D +:20502600BE01A91A004009961C6F008F006278A8008F00637AA8008FC0627CA81F76BE0130 +:2050460007CCFFFC1F76BE01A91A000207961F76BE0107CCFFF31F76BE01A91A00080796F1 +:20506600788A08022AD0941E788A2CD0941E7A8AD41E7A8A0AD0941E7A8A12D0941E788AA2 +:205086000002C41E7A8A013B42857E07C41E08D07A8A42857E072009941E10D042927A8AFD +:2050A6000190A9857E073009941E788A00020219D41E788A0702C41E788A000208D00119C7 +:2050C600941E788A00020CD00119941E788A00021ED00119941E788A000222D00119941EEC +:2050E600788A000218D00119941E0002621E621A0080621A0040621A0020621A0002621A22 +:205106008000621A0010788A14D06206941E788A18D09444FDEF788A16D09406601E5FCCA4 +:2051260000FF0E505F9660CCF8FF02506096601A780060CCFFFCA91A00016096788A16D0F1 +:205146006006941E6218FFEF788A14D06206941E788A18D09444FDEE7C83088F7064C5A845 +:205166007C83D5A8788A010230D0941E788A32D00002941E788A2ED0941E561E788A24D022 +:205186000602941E788A26D00002941E561A0100551A0200561A0200561A0400788A20D0E9 +:2051A6005606941E419214ED008F8EB41F76370008A81F763300321A10001F763700008F3B +:2051C600F9B40AA81F763300321A2000136F008F35B51F7637000CA81F763300321A400067 +:2051E6001F763700008F42B50EA81F763300321A8000237600011A7600021F767B03121E9E +:205206001F767B03101E1F767B031C2B1F767B03141EBEFE69FF06000EFE459744A84196D3 +:20522600005207ED008F00604CA8008F00614EA81F767B031D9209EC4C8A08DCC44005EEF1 +:205246004C8A0ADCC44055EF4C8A010208D0941E4C8A0AD0941E448A013B45850156A400B0 +:20526600C4855AFFAA18000045853FFFAACBABCAA81A00E0481E448A4592029CA985015602 +:20528600A400C4855AFF448AAA1800004592019CA9850156A400C4853FFFABCAAACB4A1EBC +:2052A6004E8A4806F41E4E8A4A06E41E22764C8A2ED00002941E1A764C8A0102E41E1F7666 +:2052C6007B03BF561D011F765D030792015205ED1F76BF010F1A1000035205ED1F76BF011A +:2052E600071A0008025205ED1F76BF010F1A00808EFE69FF06000EFE42A8428AF406481E1F +:20530600428AE4064A1E4806439743CC0080469643CC0040459643CC002044964318FF1F2A +:2053260048924D964A064C974A924B96469209EC43928052066743584D92008F00DC9496CA +:20534600430A459209EC43928052066743584C92008F00DC9496430A449209EC439280524D +:20536600066743584B92008F00DC94961F765D030792015206ED1F76BF010F1A0200056FE5 +:205386001F76BF010F1A01008EFE060022761F762C0035CCF8FF1F762C00015035961F7633 +:2053A6002C003418FCFF1F762C003418F7FF1F762C00341A04001F762C00201A60001F766E +:2053C6002C00201A1C001F762C00201A03001F762C00201A00301F762C00201A000E1F767E +:2053E6002C00201A80011F762C00211A40001F762C00201A00401F762C00201A00801F7639 +:205406002C00211A03001F762C002C1A60001F762C002C1A1C001F762C002C1A03001F76F3 +:205426002C002C1A00301F762C002C1A000E1F762C002C1A80011F762C002D1A40001F764A +:205446002C002C1A00401F762C002C1A00801F762C002D1A03001F762C002E1A60001F7604 +:205466002C002E1A1C001F762C002E1A03001F762C002E1A00301F762C002E1A000E1F76A5 +:205486002C002E1A80011F762C002F1A40001F762C002E1A00401F762C002E1A00801F7660 +:2054A6002C002F1A03001F762C00381A07001F762C00381A38001A7669FF4076E5A807F6D1 +:2054C600007769FF060022761F76BE01181A03001F76BE01181A0C001F76BE01181A300078 +:2054E6001F76BE01181AC0001F76BE01181A00031F76BE01181A000C1F76BE01181A00308F +:205506001F76BE01181A00C01F76BE01191A03001F76BE01191A0C001F76BE01191A30006B +:205526001F76BE01191AC0001F76BE01191A00031F76BE01191A000C1F76BE01191A00304A +:205546001F76BE01191A00C01F76BE01141A03001F76BE01141A0C001F76BE01141A300039 +:205566001F76BE01141AC0001F76BE01141A00031F76BE01141A000C1F76BE01141A00301E +:205586001F76BE01141A00C01F76BE01151A03001F76BE01151A0C001F76BE01151A3000FB +:2055A6001F76BE01151AC0001F76BE01151A00031F76BE01151A000C1F76BE01151A0030DA +:2055C6001F76BE01151A00C069FF4076E5A8060022761F76BE01261A03001F76BE01261A0E +:2055E6000C001F76BE01261A30001F76BE01261AC0001F76BE01261A00031F76BE01261A56 +:20560600000C1F76BE01261A00301F76BE01261A00C01F76BE01271A03001F76BE01271A33 +:205626000C001F76BE01271A30001F76BE01271AC0001F76BE01271A00031F76BE01271A11 +:20564600000C1F76BE01271A00301F76BE01271A00C01F76BE01171A03001F76BE01171A11 +:205666000C001F76BE01171A30001F76BE01171AC0001F76BE01171A00031F76BE01171A11 +:20568600000C1F76BE01171A00301F76BE01171A00C01F76BE01281A03001F76BE01281ACF +:2056A6000C001F76BE01281A30001F76BE01281AC0001F76BE01281A00031F76BE01281A8D +:2056C600000C1F76BE01281A00301F76BE01281A00C01F76BE01161A00C01F76BE01091AE1 +:2056E60000C01F76BE01091A00301F76BE01091A000C1F76BE01161A30001F76BE01161A82 +:20570600C0001F76BE01161A00301F76BE01161A00031F76BE01161A000C1F76BE01091A81 +:2057260000031A7669FF06001B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0073 +:2057460003E2BD0103E2BD0203E2BD0330E600060EFE69FF4229165690E503E2460001E867 +:2057660000FC03E2480000024A1E22761F7675030102015628002376391110291A7669FF55 +:2057860040765EAB1F765D033E0A1F765D033E921F765E03015419681F765D033E2B009B7D +:2057A600009A1F765E03064002EF019A005202ED019B1F7671033F920190A8CA04EC407621 +:2057C6005EB5036F40764FB54B2B4B920252E3FF54011F7672031E8A013B4B850156A400ED +:2057E600C44F1BEF1F7672031E8A4B850156A400C42B1F76720321564B001E06AC07A98A44 +:20580600C41A0080008F00DC4B92189CA9850156A400C42BEFFF2C014B2D008F6FD706356D +:205826000156A400C4921BEC0635008F6CD70156A400DC0B4B2D008F6DD706350156A4009A +:20584600C42B4B2D008F6CD706350156A400C42B4B92009B40766DB5EFFF0A010635008FD1 +:205866006CD700BE0156A400009AC493005302EC019A005202ED01BE0635008F6CD70156F5 +:20588600A400C47E4B2D008F6CD706350156A4004B92C49340766DB54B2D008F6CD706350B +:2058A6000156A400C492C056E3004B92407694B5013B4B2D008F70D7A9855AFF0635015619 +:2058C600A400C4064E1E008F70D730FF4E1E4E92ABCA4E964D92AACA06314D96A9A9015628 +:2058E600A4004E06C41E4B2D008F6CD706350156A400CC0ACC922052E8FFBA00432B4B2D1B +:20590600008F6FD71F76710306350156A40003562001C496009A4B930031005302EC019A14 +:20592600005204EDAB280100AA2B1F767103A9A968FF008F6FD7208831FFAC100156A4004F +:20594600C47E4B2D008F70D706350156A400C4064A1E4AC4AC28180046FF2256A60747FF9F +:205966004A1E88E24A00007703E24600008F7CD74B850156A400C4920CEC01E800FC03E29E +:2059860048004B85008F7CD70156A400C42B086F1F767103C8E22100007703E248000356D5 +:2059A6004B01408D78D7008F78D7AFE246010156A10003564B010156A400AFE2C40020E3D3 +:2059C600484169FF407675B6AFE2C10110E74000007703E2C100013B008F78D703564B0189 +:2059E6000156A400AFE2C40088E60000007703E24A00008F00DC03564B014A88109CA98581 +:205A06000156A400C47E008F00DC03564B01119CA9850156A4004A064FFFC49688E24A00B1 +:205A2600007703E2460002E8011C407675B603E246004B928CE60000013B189CA6BF120FE6 +:205A4600008F00DCA9850156A400C47E4B2D008F6ED706350156A400C42B4B924076AFB502 +:205A6600016F4B92AD5C83DC4076BF824B0A4B920252E4FFB0FE1F765E0305921F765E03DA +:205A860006961F765E03052B8EFEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BEC5CD +:205AA600BEC4BE83BE8ABE870300F1FF17760276407678AB0A9A029B407680AB4076FAAB42 +:205AC60006001F76C00121920F900A5213ED1F76C00111CC8001C6FF02520CED22761F76C3 +:205AE600C001BF5625551F76C001BF5625AA1A76016F69FF060022761F76C001BF56296814 +:205B06001A7669FF060006FE44974396BF56430ABF5644021F76C001114302EF25761F7641 +:205B2600C00111CC8001C6FF07EC22761F76C00111187FFE1A7622761F76C001111A40000B +:205B460043921F76C0010F9021CDF0FF1F76C001A8CA21961A76439202ED019AA90E461E0F +:205B6600AC281F00AB2880C3AA28C901013B46C469FF2256ACA9A60740FF4456A900461E6C +:205B860046061F766F03381E407678AB1F76C001119201900152FBED22761F76C0011118A1 +:205BA600BFFF1A764492015203EC02520DED22761F76C001039011CD7FFE86FF1F76C00174 +:205BC600A8CA11961A764492035215ED22761F76C00111CC7FFE1F76C001A91A00011196E0 +:205BE60069FF20FFDA054076DEB91F76C001111A80011A7686FE69FF060004FE22761F7639 +:205C0600C001BF561A031F76C0011B2B1F76C0011A9206EC1F76C00103561A01026F019A25 +:205C2600A90E441E1F766F0369FF4406421E3806C000A9B8441E1F766F0344063C1E1F762B +:205C4600C0011B9206EC1F76C00103561B01026F019AA90E441E1F766F034406421E3806FF +:205C6600C000A9B8441E1F766F0344063A1E1F762C0035CCF8FF1F762C00015035961F76C7 +:205C86002C00341A04001F762C003418F7FF1F76C0011C1A0800787680001F76C0011C1AEF +:205CA60010001F76C0011C1A00041F76C0011C1A00081F76C0011C1A20001F76C0011C1A72 +:205CC60000011F76C0011C1A00101F76C0011C1A00201F76C0011C1A00401F76C0011C1A1D +:205CE60000801F76C0011C18FBFF1F76C0011D1A01001F76C0011D1A02001F76C0011D1AF0 +:205D060004001F76C0011D1A08001F76C0011D1A10001F76C0011D1A20001F76C0011C1A0E +:205D260004001F76C0011D1A00041F76C0011D1A00081F76C0011D1A00101F76C0011D1A09 +:205D460000201F76C0011D1A00011F76C0011D1A00021F76C0011D1A00401F76C0011D1AA6 +:205D660000801F76C001201A00011F76C001201A00021F76C001201A00041F76C001201A56 +:205D860000081F76C001201A00101F76C001201A00201A7669FF84FE060002FE22761F76F8 +:205DA6002B002028FFFF1F762B002128FFFF1F762B002228FFFF1F762B002328FFFF1F76BF +:205DC6002B002428FFFF1F762B002528FFFF1F762B002628FFFF1F762B002728FFFF1A7694 +:205DE6001F76FFCF389241961F76FFCF399241961F76FFCF3A9241961F76FFCF3B92419687 +:205E06001F76FFCF3C9241961F76FFCF3D9241961F76FFCF3E9241961F76FFCF3F92419656 +:205E26001F762B002F4003EE019A026F009A82FE69FF06001B76F0FF0500BDABBDA8BDA0F9 +:205E4600BDC2BDC300E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6000606FE69FF88 +:205E6600422916561F7633002292459623760100267601011F7633002218FA001F763300F2 +:205E86002128FFFF10291F767A033192C1564B011F765D0307920252C056E400442B449223 +:205EA6001152E3FFD500013B008FA6D744850156A400C492C156C7004485008FA6D7015656 +:205EC600A400C492075209ED4485008F50D70156A400C4924396096F4485008F087101562A +:205EE600A400C492C3FF43964485008FA6D70156A400C492035209EC4485008FA6D701566B +:205F0600A400C49204526EED4392C852516503564401008FC0DE0156A400C40609ED00BEE7 +:205F260003564401008FB2DE0156A400C4C203564401008FB2DE0156A40002020156C40046 +:205F4600408DC8DE008FC8DEC8E2430169FF035644010156A100035644010156A400AFE27D +:205F6600C40020E7080002E84116407675B6AFE2C10110E74000007703E2C100013B008FB4 +:205F8600C8DE035644010156A400AFE2C4008CE6000000770077A9BF120F439601BE008F57 +:205FA600C0DE035644010156A400C4C21B6F00BE03564401008FC0DE0156A400C4C2008FFB +:205FC600B2DE035644010156A400C4060BEC03564401008FB2DE0156A40001024156C400BB +:205FE600316F43884485008F98DE0156A400C47EC8E24300007703E24200442D69FF008F32 +:20600600C0D812350156A4004076DBB78EE600000077013BA6BF120F008F80DE448501569E +:20602600A400C47E008FA6D744850156A400C492095205ED44924076C386046F449240762D +:20604600C587440A44921152E4FF2FFF1F765E0305921F765E0306961F765E03052B016FA1 +:206066001F765D03079201525DED442B449218525063013B008FA6D744850156A400C4922B +:2060860044EC4485008F08710156A400C492C3FFA90EA9BD120F00770077007700778BE65B +:2060A6000000007703E24200008FA6D744850156A400C49202520CEC442D008FC0D869FFCA +:2060C60012350156A4004076DBB703E242008CE600000077013BA6BF120F008F80DE4485A8 +:2060E6000156A400C47E008FA6D744850156A400C492025206ED449269FF4076F983056F0C +:20610600449269FF4076C386440A44921852B2641F765E0305921F765E0306961F765E0383 +:20612600052B1F76C401011A00401F76C401191A10001F763300BF562101103B45921F7621 +:206146003300229686FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BEC5BEC4BE8322 +:20616600BE8ABE870300F1FF1776027608FE2276008F17AD1F7635000AA81A7669FF407679 +:206186005EB91F763300221A2000237601001F765D0307920152C05686001F76C401021A31 +:2061A6000F001F76C40103CCF0FF1F76C4010B5003961F76C40103CC0FFF1F76C401A050E3 +:2061C60003961F76C40103CCFFF01F76C401A91A000903961F76C40103CCFF0F1F76C401B8 +:2061E600A91A008003961F76C4010418F0FF1F76C40104CC0FFF1F76C401105004961F7637 +:20620600C40104CCFFF01F76C401A91A000404961F76C40104CCFF0F1F76C401A91A0030B4 +:2062260004961F76C40105CCF0FF1F76C401055005961F76C40105CC0FFF1F76C401205057 +:2062460005961F76C40105CCFFF01F76C401A91A000605961F76C40105CCFF0F1F76C40132 +:20626600A91A007005961F76C401061A0F001F76C40106CC0FFF1F76C401D05006961F76DC +:20628600C40106CCFFF01F76C401A91A000E06961F76C40106CCFF0F1F76C401A91A00C094 +:2062A60006961F765D03079202527EED1F76C40102CCF0FF1F76C4010E5002961F76C4012E +:2062C60003CCF0FF1F76C401065003961F76C40103CC0FFF1F76C401705003961F76C4016D +:2062E60003CCFFF01F76C401A91A000203961F76C40103CCFF0F1F76C401A91A0030039605 +:206306001F76C40104CCF0FF1F76C401055004961F76C40104CC0FFF1F76C4014050049659 +:206326001F76C401041A000F1F76C40104CCFF0F1F76C401A91A00D004961F76C40105CCE6 +:20634600F0FF1F76C4010B5005961F76C40105CC0FFF1F76C401805005961F76C40105CCCF +:20636600FFF01F76C401A91A000E05961F76C40105CCFF0F1F76C401A91A00A005961F763C +:20638600C40106CCF0FF1F76C401095006961F76C40106CC0FFF1F76C401105006961F76FD +:2063A600C4010618FFF01F76C401011A00011F76C401011A00081F76C401191A10001F76E0 +:2063C600C401001A10001F76C401011A00401F763300BF5621011F76A001191A00081F760E +:2063E600A00119CCFFF81F76A001A91A000419961F76A0011ACCFFFC1F76A001A91A00015D +:206406001A961F76A001BF5609801F76A00100CC7FFC1F76A001A91A000200961F76A001AE +:2064260000CCFFE31F76A001A91A000400961F76A001013B00CC001CC9FFA92D019A66FF1D +:20644600A985441E1F76A00100CC8003C6FF0AEC1F76A00100CC8003C6FF80FFA985461E0B +:20646600036F0102461E44871F766F0344564600421E3806C000A9B8008F881342A8C000F8 +:20648600A9B8481E1F76A001489205961F76A0010018FCFF88FE06001B76F0FF0500BDABC2 +:2064A600BDA8BDA0BDC2BDC300E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E60006CC +:2064C60069FF42291656227601021F767503015628002376391110291A761F765E033E0A66 +:2064E6001F765E033E921F765E0301541D681F765E033E2B009B009A1F765E03064002EF3F +:20650600019A005202ED019B1F7671033F920190A8CA05EC69FF40760F80046F69FF4076F1 +:20652600008040765EAB1F765F03300A1F765F0330920A5242ED1F765F03302B1F765D035A +:206546000792015228ED1F765F03349206EC1F76BF010D1A0010056F1F76BF010B1A0010FB +:206566001F765F03359206EC1F76BF010D1A0004056F1F76BF010B1A00041F765F03369234 +:2065860006EC1F76BF010D1A0040056F1F76BF010B1A00401F765D03069205520EED1F76A5 +:2065A6005F03349206EC1F76BF010D1A0040056F1F76BF010B1A00401F767103240E1F7601 +:2065C6005F033088A60F18ED1F765D03079201520DED1F76BF010B1A00101F76BF010B1A02 +:2065E60000041F76BF010B1A0040025205ED1F76BF010B1A00401F765E033F0A1F765E03A2 +:206606003F921F765E030254E8FF96001F765E033F2B1F765F03310A1F765F03314003EFEE +:20662600019A026F009A1F765F0332961F765F033192079003EC019A026F009A1F765F0312 +:2066460033961F7671033F461AEF1F7671033FCC80001F765F03C6FF34961F7671033FCCA6 +:2066660080001F765F03C6FF35961F7671033FCC80001F765F03C6FF36965D6F1F7671031C +:206686003F400EEF1F765F0332921F765F0334961F765F0335961F765F0336964C6F1F7627 +:2066A6005D030692055211ED1F765E03064008EF1F765F0332921F765F0334963C6F1F7698 +:2066C6005F03BF563401376F1F765E03064005EF1F765F03342B056F1F765F03BF56340127 +:2066E6001F765E03064206EF1F765F03BF563501226F1F765E03064308EF1F765F0332929D +:206706001F765F033596176F1F765E03064410EF1F765F03009A339300BE005302EC019AFB +:20672600005202ED01BE1F765F03357E046F1F765F03352BAFE2BE03AFE2BE02AFE2BE01EC +:20674600AFE2BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF177602761B76F0FF050074 +:20676600BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6A7 +:20678600000602FE69FF422916561F7633003292419623760001267600011F763300329288 +:2067A6001F763300322B1F7633002128FFFF1029008F00D069FF4076D59A008F00D0407665 +:2067C6005696103B41921F763300329682FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2F5 +:2067E600BE00BEC5BEC4BE83BE8ABE870300F1FF177602761B76F0FF0500BDABBDA8BDA05B +:20680600BDC2BDC300E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6000602FE69FFC2 +:20682600422916561F7633003292419623760001267600011F763300321871001F76330096 +:206846002128FFFF1029008F80D369FF4076D59A008F80D340765696103B41921F763300D9 +:20686600329682FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BEC5BEC4BE83BE8ADA +:20688600BE870300F1FF177602761B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E283 +:2068A600BD0003E2BD0103E2BD0203E2BD0330E6000602FE69FF422916561F763300329242 +:2068C600419623760001267600011F7633003218FD001F7633002128FFFF1029008F00D0EE +:2068E60069FF4076D59A008F00D04076F397103B41921F763300329682FEAFE2BE03AFE255 +:20690600BE02AFE2BE01AFE2BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF1776027627 +:206926001B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0003E2BD0103E2BD021B +:2069460003E2BD0330E6000602FE69FF422916561F76330032924196237600012676000197 +:206966001F763300321875001F7633002128FFFF1029008F80D369FF4076D59A008F80D3F1 +:206986004076F397103B41921F763300329682FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0041 +:2069A60080E2BE00BEC5BEC4BE83BE8ABE870300F1FF1776027622761F76BE011C18FEFFC9 +:2069C6001F76BE011C18FDFF1F76BE01121A03001F76BE01121A0C001F76BE0116CCFCFFED +:2069E6001F76BE01015016961F76BE0116CCF3FF1F76BE01045016961A7669FF0600407610 +:206A0600D8B21F76E401BF5607501F76E4010918DFFF1F76E401BF560C0E1F76E401BF564F +:206A2600030A1F76E401BF5604051F76E401092B1F76E401091A00041F76E401091A20009F +:206A4600060002FE429741961F76E40109CC0008CAFF015204EDA9285555466F1F76E4016C +:206A660002CC0010CBFF015204EDA92800103C6F1F76E401BF5605041F76E4010928206EC7 +:206A8600035641011F76E401C7FF08961F76E4010244FDEF035641011F76E40108961F7683 +:206AA600E4010244FDEF42921F76E401A7FF08961F76E4010244FDEF42921F76E40108968F +:206AC6001F76E4010244FDEF1F76E40109CC0008CAFF0152FAEC1F76E40102CC0010CBFF89 +:206AE6000152FAEC009A82FE060002FE41961F76E40109CC0008CAFF015204EDA928555581 +:206B0600466F1F76E40102CC0010CBFF015204EDA92800103C6F1F76E401BF5605021F769D +:206B2600E4010928206E035641011F76E401C7FF08961F76E4010244FDEF035641011F7656 +:206B4600E40108961F76E40109CC0008CAFF0152FAEC1F76E401BF5605021F76E401092812 +:206B6600206C1F76E4010243FDEF1F76E40142920693A83842961F76E4010243FDEF1F76F9 +:206B8600E40142930692A83C4297429282FE060006FE417D461E44A846C4A68A0002A60F83 +:206BA60081DC46A814EC448A408F80DD84924170FF9044A8A9584192C7FF9570419646C4C8 +:206BC600A68A0002A60F81DC46A8EEED419286FE06000CFE417D461E44A800024C1E460675 +:206BE6004C0F28694CCC01004796448A01294C0640FF0156A400C4924896479205ED48CC16 +:206C060000FFC7FF49964792015204ED4892FF90499649924170008F80DDFF90A95841928A +:206C2600C7FF9470419601024C074C1E46064C0FDA6641928CFE060006FE439642A8442870 +:206C4600FFFF452B439245543569428A45589492FF9044F2462B469208521067444007EFCC +:206C66004492C0FFA91C01A04496046F4492C0FF4496460A46920852F268428A94CC00FF50 +:206C8600C7FF44F2462B469208521067444007EF4492C0FFA91C01A04496046F4492C0FF81 +:206CA6004496460A46920852F268450A43924554CD66449286FE06000AFE42A8428AC40640 +:206CC600481E0129480647FFA81A00FF441E492B499220521363440608560080461E460658 +:206CE60004EC2FFF0062461E440630FF46704571441E490A49922052EF644406AC2818003A +:206D060048A3AB1800FF2256009BFF90AACBABCA441E4806440F03ED019A026F009A8AFE13 +:206D260006001B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0003E2BD0103E2D0 +:206D4600BD0203E2BD0330E6000604FE69FF422916560102421E1F7633003292449623760A +:206D66000001267600011F76330032921F763300322B1F7633002128FFFF10291F76800160 +:206D86001E921F904396432D42063B56421E1F76800142060C1E013B008F006103564303B9 +:206DA60069FF0156A400407678A71F7633002192A9CDFFFE1F763300C7FF019001500190A6 +:206DC60087FFA8CA2196103B44921F763300329684FEAFE2BE03AFE2BE02AFE2BE01AFE247 +:206DE600BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF177602761B76F0FF00E2BD00C5 +:206E060030E6000602FE422916561F7633003292419623760001267600011F763300329253 +:206E26001F763300322B1F7633002128FFFF102901021F768001061E1F767B031C0A1F76D4 +:206E460033002192A9CDFFFE1F763300C7FF01900150019087FFA8CA2196103B41921F7670 +:206E66003300329682FE80E2BE00F1FF177602761B76F0FF00E2BD0030E60006422916566A +:206E860080E2BE00F1FF177602761B76F0FF00E2BD0030E600064229165680E2BE00F1FFB5 +:206EA600177602761F765D030792025206ED1F76BF010D1A0010056F1F76BF010D1A00086E +:206EC60006001F765D030792025206ED1F76BF010F1A0010056F1F76BF010F1A0008060043 +:206EE60002FE42974196009A005300BE02EC019A005202ED01BE427E41920DEC429206EC56 +:206F06001F76BF01031A0004116F1F76BF01051A00040C6F429206EC1F76BF010A1A010042 +:206F2600056F1F76BF010C1A010082FE060002FE419600520CEC009A009B1F76BF010944DD +:206F460002EF019B00530DED019A0B6F009A009B1F76BF01014702EF019B005302ED019A00 +:206F660082FE060002FE4196005206EC1F76BF010F1A2000056F1F76BF01071A000182FE61 +:206F8600060002FE2276008F91A91F7634001AA81A7669FF1F766F030F8F4042380642A8B2 +:206FA600C000A9B8A9BD120F0077007702E8D11F008F66DD89E6000040763AB61F763000AF +:206FC6000C282040237600101F765E03BF56010182FE0600008F000C1F7675031EA800026B +:206FE6001F7630000119021E1F763000062B1F763000072B1F763000041A10001F763000E7 +:20700600041A20001F7675030002201E1F767503008F080C26A81F767503008F100C2EA8D3 +:207026001F76300001190A1E1F76300000020119121E1F7630000E2B1F7630000F2B1F76A0 +:207046003000162B1F763000172B1F7630000C1A10001F763000141A10001F7630000C1AC9 +:2070660020001F763000141A20001F7675030002281E1F767503301E060008FE03E24601EF +:2070860003E2440042A8428A4406E41E428A4606F41EAFE24400AFE2460100E70800007782 +:2070A60088E60000007703E24800428AC48A4806D41E428AC48AF42B428AC48AFC2B428A18 +:2070C600C48AE41A1000428AC48AE41A2000428AC48AE418FFFB428AC48AE418FFF7428A2E +:2070E600C48AE41A0040428A0002D41E88FE0600BD3ABDB2BDAABDA202FE0129A9BF120FD3 +:2071060058FF5B61A85C7F91A8088000421EA493D6FFA85CA9BF160F6761A85D7F91A80888 +:207126008000A859A958A593D6FFA85DA493A571A8180001A697A418FF00A518FF007FDC98 +:20714600A492A59EA7964D64A90801FF3E62A193A09236FFA859A958420635FF0EF6A11F94 +:20716600A95BA3010AF6A11F2D56A204A32DA03640FF0BF6A11F33FF009B30FF54FFA20CD5 +:20718600A39540FFA70801001FF677FF200940FFA70801001FF677FF5AFFA7922265A908CA +:2071A60001FF1363A9A946FF7F91A85BA95AA625A79596FFA20CA395A9BD120F82FEBE82DD +:2071C600BE86BE8BBE8E0600009B57FFA8087FFF5AFFA693F260A8280080AA71AB92ED6FC3 +:2071E60020FF0000EA6F5AFFA493A818000196FFA85CA9A9A8087FFFA81C0080A4CBDD6FA8 +:207206001F76C001201A00104076E5A822761F762C003518F8FF1F762C00341A03001F7641 +:207226002C003418F7FF1F762C003418FBFF1F762C002ECC9FFF1F762C0020502E961F76F0 +:207246002C002ECCE3FF1F762C0008502E961F762C002ECCFCFF1F762C0001502E961F7622 +:207266002C002ECCFFCF1F762C00A91A00102E961F762C002ECCFFF11F762C00A91A000687 +:207286002E961F762C002E187FFE1F762C002F18BFFF1F762C002E18FFBF1F762C002E180E +:2072A600FF7F1F762C002F1A03001A7607F6007769FF060022761F76BE011618FCFF1F7621 +:2072C600BE011818FCFF1F76BE011A1A01001F76BE011B1A01001A7669FF060004FE421E4B +:2072E6000129420640FF421E0002441E4206440F0A6928024076DEB901024407441E420696 +:20730600440FF86684FE0600103B1F7633002018FEFF1F763300222B1F763300242B1F7625 +:207326003300262B1F763300282B1F7633002A2B1F7633002C2B1F7633002E2B1F76330083 +:20734600302B1F763300322B1F763300342B1F763300362B1F763300382B1F763300232B16 +:207366001F763300252B1F763300272B1F763300292B1F7633002B2B1F7633002D2B1F76E6 +:2073860033002F2B1F763300312B1F763300332B1F763300352B1F763300372B1F763300F6 +:2073A600392B69FF06001F763300201A01001F7633002128FFFF102969FF0600BDB2BDAA66 +:2073C600BDA203E2BD0403E2BD0503E2BD0606FE03E2440042A808D04283428A42C442C5C6 +:2073E60042864282AFE29502AFE2F40050E801000CD0428AAFE2440010E3D64B0ED114E3AE +:20740600974C07E3C41000E3E245AFE29B0641E77101007710E74000007703E24600428AD3 +:2074260042830CD094060ED0951E428A0CD04606941E4283428A08D0F506941E428A4406A8 +:20744600F41EAFE2460086FEAFE2BE06AFE2BE05AFE2BE04BE82BE86BE8B0600AD28000411 +:2074660069FF1F5616561A5610E6000240291F76000002291B762276A928E2B9A8280000C7 +:2074860001091B61C076E2B904290F6F009BA92401DF046C0429A82401DFA61EA1F786244D +:2074A600A706A1810109A71EA92403635CFF043BA95901DF0900ECFF1A76A928FFFFA82856 +:2074C600FFFF01090E61FF76FFFF066F01DFBDC3A71E673EBEC5A92401DFA82458FFF760D3 +:2074E600407697B94076B2B91B76F0FF0500BDABBDA8BDA0BDC2BDC300E2BD0003E2BD0070 +:2075060003E2BD0103E2BD0203E2BD0330E6000669FF42291656227601021F76750301561F +:207526003000008F42DD69FF1F76750308C5673E1A76AFE2BE03AFE2BE02AFE2BE01AFE26C +:20754600BE0080E2BE00BEC5BEC4BE83BE8ABE870300F1FF17760276022904295F565AFF16 +:2075660042065F56421E00021FF617564200AB06325602292076022904295F565AFF42063A +:2075860056FF421E00021FF6175642003256022920765AFF00021FF617564200A9A920761A +:2075A6005AFF00021FF617564200207602FE208F00001F767B032EA81F767B03208F00F0C6 +:2075C60030A81F767B032E061F767B03321E1F767B03342B1F767B032E06421E066F428AC9 +:2075E600C42B01024207421E1F767B033006420FF76682FE060002FEA0E514AD0962A0E537 +:207606001F766F0314AD90E5B4563E01166F05BE92E601004FE803C00CB5A60000E7CA000B +:20762600007700E78A000077CFE812F0007700E75100007700E7400082FE0600A85CA9713B +:20764600A697013BA98556FFA95DA48556FFA95CA5920FF6A41FA64F026C5CFF2076A69610 +:20766600A85C013BA98556FFA95DA48556FFA95CA5920FF6A41FA64F026C5DFFA89220762A +:207686005AFFAB92A48EA4C507ECFF9CA988859287960E00FEFFAB92A988A9A9A60F10EC44 +:2076A600AA930EECA9A9FF9DA85CBF76FEFF859287960E00FEFF859287960C00F8FFA08AC9 +:2076C600060022761F76C0011C1A080069FF787680001A761F76C4011CCCFF3F1F76C40132 +:2076E600A91A00401C961F76C401BF5618E069FF028FE649A9A84076DEB9060006FE008F09 +:2077060000C044A8008F000D46A82276412B419280520D634683448AA9A084C4020944A8F5 +:20772600461EC5C2410A41928052F5641A7686FE69FF0600AB28FFFFAA28FFFFA928FFFF1D +:20774600A828FFFFAB0F04ED00BE00D4096FAB28FFFFAA28FFFFA4A9C4880209A98AA692F0 +:207766004076DFA306000077006F1F767503BDB23CC5A959673E1F767B033A0604ECA71EB3 +:20778600A192673E1F767B03380603ECA71E673E4076B0B9BE8B060002FE429741961F76AE +:2077A6007503379642921F767503369682FE06001F7675033AA806001F7675033CA806005F +:0A77C60006000119C356FFFF06007C +:2077D0000301000000C017910000179100001791000017910000179100001791000017913D +:2077F0000000179100001791000017910000179100001791000017910000A6880000B38820 +:207810000000C0880000CD8800002B910000E5880000F0880000FB8800000689000011896E +:2078300000001C89000027890000328900003D89000048890000538900005E8900006989DC +:207850000000748900007F890000A08900002B910000C1890000E2890000018A0000228A42 +:207870000000458A0000668A0000878A0000A88A0000C98A0000EC8A00000D8B00002B91D9 +:2078900000002B9100002E8B00004F8B0000728B0000958B0000B68B0000D78B00002B910D +:2078B00000002B910000FA8B00001B8C00003E8C00005F8C0000808C0000A18C00002B9126 +:2078D00000002B910000C28C0000E38C00002B9100002B9100002B9100002B9100002B9173 +:2078F00000002B910000068D0000278D00004A8D00006B8D00008C8D0000AD8D00002B9197 +:2079100000002B910000D08D0000F18D0000128E0000338E0000548E0000758E00002B91BE +:2079300000002B910000988E0000BB8E00002B9100002B910000DC8E0000FD8E00002B91E3 +:2079500000002B9100001E8F0000418F0000628F0000838F0000A48F0000C78F0000EA8FD9 +:2079700000000B9000002B9100002B9100002B9100002B9100002B9100002B9100002B9138 +:2079900000002B9100002B9100002B9100002B9100002B9100002B9100002B9100002B91F7 +:2079B00000002B9100002C9000004D9000006E9000008F900000B09000002B910000D390E6 +:0C79D0000000F490000033000B000A00DF +:2079DC002800000004C1E89F000007A0000019A000002EA0000044A0000055A0000069A007 +:2079FC0000007AA0000095A00000B7A00000CDA00000DEA00000EBA000000CA100001EA1E3 +:187A1C0000002EA1000041A1000050A1000060A1000076A10000000098 +:00000001FF diff --git a/bin/ice.map b/bin/ice.map new file mode 100644 index 0000000..cd0ba3f --- /dev/null +++ b/bin/ice.map @@ -0,0 +1,33 @@ +******************************************************************************** +TMS320C2000 Hex Converter v5.2.1 +******************************************************************************** + +INPUT FILE NAME: +OUTPUT FORMAT: Binary + +PHYSICAL MEMORY PARAMETERS + Default data width : 16 + Default memory width : 8 (LS-->MS) + Default output width : 8 + +BOOT LOADER PARAMETERS + Table Type: SERIAL PORT (SCI 8 bit Mode) + Entry Point: 0x0000b82b + + +OUTPUT TRANSLATION MAP +-------------------------------------------------------------------------------- +00000000..003fffff Page=0 Memory Width=8 ROM Width=8 +-------------------------------------------------------------------------------- + OUTPUT FILES: D:\Projects\Ledokol\Docs\UKSS\ICE_19_03_2018\bin\ice.bin [b0..b7] + + CONTENTS: 00000000..00007a33 BOOT TABLE + .cinit : dest=0000b9e2 size=000001f5 width=00000002 + .text : dest=00008000 size=000039e2 width=00000002 + .econst : dest=0000c000 size=00000103 width=00000002 + .switch : dest=0000c104 size=00000028 width=00000002 + +-------------------------------------------------------------------------------- +00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*" +-------------------------------------------------------------------------------- + NO CONTENTS diff --git a/bin/ice.out b/bin/ice.out new file mode 100644 index 0000000000000000000000000000000000000000..b378f472425ed1752d3ad0466799350d7468e467 GIT binary patch literal 228274 zcmeFa3wTu3xj(%2%w*3bgd`wB2pA%GiGr9b1hG1I0tASY5Yd7GLV&bLkjqHbql357 zoGNsP(SlX12#M5VtG(#?R|qz?*5WDWUt2vbUjB&6*Av9{SnaXO{(kSf*50#bh=A4e z^?RQ0%k%76d;Q*bz3W}?y5Dx56*I-2l{2o%{lF#aOd&>#+lG8c_>9#f4owlx-}tBS znsB^g;;_{FId~1`rTq3=0bYD~CbqP#Y+EbDp{M2Z7ek1p1MvG*z=^9Qzw)wEKUDY0 zcal$k6W6w`hj^)90&zg^f%r=hul?t-Uz9uS&I|xvTmI@r*DhVRvSp3v1xU}Q{3SFz zGkGVI-?HY~=GANBOSItPWc(A?tX9vt14}uN&mta&zz5?%W zfS(>cAN7Db|9T<}lF#Yz-wDXG=XCfz6l|eIb0A7N0 z{s{Pc7s|&^!~yKBqu@ya1!ij-&{!-FM{cRZO`qc5E9e0(+Z;lb-KOZ6k zr~i>1Z2o}8e`dK5f9gFszkgUtmWerr`R7mP4~zqE<8)z+hMQH_w(_g3tA)>-7T|6)Aa`<2931G`1rzMc);{^er*zNa=k?f;tbzj|*>+z|Lz zV^8nRiCY4D#Xs$PX2VbYHyJs7N-%mFD*dG_G_dT)UN&gz-2ff!NRt3H< z>i2El@Gbup#+KfOL@barx_X-uR|f7CbNAh|q0`@J+}}Gtu^{jr(Y)`$4G;LQ5m)cq zx?!9D%f`2RuS(1d+-Gd;txZf1d_&CK_s<(T{4>PteRprz%_1} z9~9y+o~QBb!DCrhGu5)btlas^UBK>f>m?=gxb-{d?G@+k_v+2E4)U92y{g>lDjhSF zJ5#xJ?0#%5XIE-vS^WrQK%1i~^at#IV!Z~}&rFu}e;7M%-2lyA#p=s(>n7*zuS_HC zBj@cV#9*-0n^oLGx#8c)*y0GEgIKSJOR?Xg=*Ryc^%7!Ce1Y4Wbj8f0W8!;_!9}7V zt6jbM%nWM2L&Y1YzT@sgVZ(hWC<@*|8m@0Yg0+O}-G`#$@k2qEapcHHCGT7z1|NCq z0r3u6Hc)CosdYcj98p8OSsN7Zd>a%B?~niWDc2FhReuB)iLd+d#^a`N9S@8TBnx9_ zv=~#xrkyVb?l78mh`#ZGI|3WUrrwv?cXJ?zc#bU@6Tim2x9Pk=(mj9Bt&re3J~l2k zP5=Iwc$FyXE{eBVW8&@Z{7wE~jT!9j6+KV&JTo+3TraM79r^cBV$;%Bzk$h;KYq!N z$HdD-ZfS{sTwD}LiH3_@SLqSA^tH25I8g1Fg0ZM~l%kOPEpZ&&osd1@CQe7&aE>M0qQbHEJFiX1Ql{>+d{)?15 zQMnf@w@kU^%B}E8{z_%>D&DWjE?5{E;)lFm`0I7(v$Euo80UtaNV zn)k}kYSLt=%OC&J(-c!_?9UuiVQesKBMz!ES}5L-%cre9Xux&>&jhkD9UvZr7*f7M2 z7Gu7jv}}4rxDP(JamO8E(_`?VHR1Nd9ebB+pBJ?+3#Dwe``n_0a69k$XbV@P>{R|2 zxmBg2ms%I|c=Vql_lCOzT_Tp(AMP-wM(*g#cP}=!4rzzaWi<7PXmSwV`%L#yvDIWW z!04R_?>kOm`;w8aXfvB;*F@{kw`Q-?S;Os9JJP}-GMubA2ynH zi)qOnJ$?60t3|2%an7-{@Uva-8b98(#dXx!L-^TE0a0vz&)d_nGihw@d(rx2qty+0 zb{LYt)|u`)hHyz4?izPivgbtuwz$T<^H)9lk6XsKdVZC4FSXU?@tt>vZVKKT=nA7A zE^rS@diwV^MRMHjkXJU~sOhbvL+IyQzKe{X_9> z?xq0O6iVYG;yJ|Cy&$q>chVn!@K%BLC0t~P$L9B3a{EC~e_wKYM_-q+l zNzUPyRS8ap8^{E96HGFRL0<4NYUswwrjMu1jnaTW9)_`&&f}xxa1Jy)%>BEzkY4RT)vdb4IChX4^}au8=BS zeMMMU+=MnIS$IFyZ0fy_S$Dd~qKVhoj}}jk8pg!0b6+0LLb-<<_zL7UyDv`;JvwLn z9Mzge`^2WLXiev+)^tt|QQlwTZklQM@7nq@Q8Bsz^&vqR$$uR3OECUG|2~e!6^|d< zXUOr2`_Mii+eKrlA0cJSD8oI1aL-{J@Q0s#lNL{}H>U2~i*drHSF|$Xydwt=zdTc> z?q>AtXlY(SK0YD}RZAmOOJi)6X*5+DUGEAYNM)ClEOp-@o`=rVmcvG`knSoSMrs@- z<-FK*5IrDS>&2#*4H{QTZN>FH(6(pGOw^l}+pa(kr>s-UmbnM1%CM4Af>GGOR+^O@ z)Q^!H>ir`3;|S?KR3naAyJ<8hu|qY6KVF<5y8F;2%Bs?yWJC9%8Di)W|L|dtWwoHM zgYSy*#*v;+d`G^0KIKU$NqQSoN8B&1EDox&ax+Ox*L^n9S!0kEq(ABGZklb#^l)yU zBpsooZ`+9bsi*L5>v?d_y;SnIzC8OPyR5jY=WLFykKf<88X9hWVepSVN! zP&x1Jq!i@ZWgYcV%Ab8w{=p7^C`mergI8>H>I-bJ+FjCN99j6WtYau0M&6O-OQ|%_ zc)Ig#w}53^V?`w*RwN8c4aLi~%ZwINsd6{fIT)p|^KAoRvRib#54>bc3Tv0dbY4lb z<;uQ7)%*Rz|DsjjCF4rPZ`VG`W#h=AKZ_sd9cf$I`L++S`&y~Q%5vdqHGWJfznj}3 zPQh;}9^aN-s_oC}j}>`1eKOZbQ(a4{C!aMIq$eX5FUL}!bRQ*4&PtBwu>h<;HFO7+ zMbe3C=i`SiF{BN>YaoQpKYF}JM9G`a1;O>s z5N@$xCztC;Xmr6l-w?S++^DP1tJpBds}9bRo z@?;LMy-l?_gvov-knG!1JO8nbUw_RXKliq2$q?tHHp1c(E5}qN9m*cbzug~c%x;mE zR#+s5M`9_SNMmlxG}N_da^%rzC?%XzD4RohEH>7WMUti!6@ZUMl*mn#fN9CBe)(Pi zJ3lu6>s$(`U#2qfMda{LIiJ$|*3-$~?Py0SClfq&LA~YP1~c;P%|}Ej)hx;{nkiG? z5<#C5NK#7`(ORlnE`!Ck1vCrmRvFe>3rkQ=^`f?8>_?-5JCHNvhO&-DQTuAyuGH?? zITLC0w$!rKC6#6sHLV}tpRj1`yudvTvk>u0o+*Aiw#nGsv(b$)7D?>Je0?XkA;#v~ z7x!9sV4PdqH4P)81sHY8P~x|F=E*|cV%^E1YLnjnRBpOB2RAx7I4b_0B@R6!%H9@c z@Pgq@6kKp_T(l2BF}^s;z>@xdROZ6z+QD_4@@!1JQjARoy2fD(_Pn@(x($Ef zM`#}_#o48nRd7MURC*62$984r?8zkj_3x7)<42DGEl{`q4johqmj8Y6Yc`;f-ro^_ zO2X$!MM_HH`p>AxIh>m=NTAiuN^wqM-T)HLIZ1AwC?WTAOYnVO32e=C1}GDsEhV(B zk(sNXO~RPZDB(QL4-fL=OI$Y3E4*v~3Fn<8KTeRqwm5G9Tl@p06rT5aQ}g*H{9X1a z<$UoWUwoV|rG>5mQc`-7e7P`F0_#yaK)#$z%87coKcgQ16A}ihC!Z}9pH+giW&!e} zfb-+R0rTU+Q|5;zf%D_S0rKNyQYLV&mOzgwtjC1HiUIOt!b$WvK?3VBVE{cola#{B z&#On_C&`mcDP@JU(w^Bne-;T73dem;31x)?wZ13Qp@MB843tf7 zFDlp;6$4nb;v}{>K}z8#1El1$Nx1HFOIY`LC44cq_+q3KmVe&V6n<8F)X1{ov)iqj z!UqP>q2?sz;zSAee{Knz|M3zyM{5SCBcII{4}RX1dg_1 zx0jr^gU;LGODP88>v!HhzDQymt9s{H)jP+k-Z@shFL383&%=IdAQwC1u_3Ub)V#Cw zrfm5>wxhH3$5~|4g4my6)03aoAc-bU8Dt-omMwW+x@Ql|iroNgmD{CGcDUiv-u;l+ zO3t~RFLz?)Ef+kLuFld4MoO1|!8@(Vc4Ak~=741%wK?$qk6%J_H%l5{d`4=7~TP9+IVavc(6uOgFQSa}Pwc#(zDIYFJOF-q^9UIB{Q^G6AR1;)A zot+%4^6l(lzIK1S`dc!TKmJLQI}g<@EBP{x4WQlypk94NKH@lu-+ z%#Avk#~MM;oPN>{2*UOv?B1rJAvOHZ<-z2TenJyl{qd1Mb-_Z52s=Fwp33ml@2k2$!J&Kp#bka z%n*^Ji)HHZx=)C=_7w4+F<`vg^8=;JjjZ-y>A&R#O8)~fPjh0f!_G?-JH@Zqy59Ua z_Cf76b-CZ-e?_GOv^ty+Adct*w6oQ7N6$0E`J5W9z<=ZIY`ND(dpS7uBX?uy>`*v| zY<$?NxAr!LbHiv0-n2TtKzn=ogQb=?fRjI8yiG~AnN70)UaLKSXqvNw&HG#@*rous zxxu26=)tMN-1~{^m6z3SGjeCuK|2S?k{)#?k4{MTHoYz=+z?pw_g|nzhYVPfT1=GS z_uN#1|3_?n$$+swiSj$!HK9GM?X0=EMkTWYrLW|TNuzii%6-0}X%sIg)M8K?s5T_C z>Fw{&*UwWMh9Ji;w7$tFl!D#Cjv)s+li{x5ZNZMA2i#5f_|7=c`9h>C*um}CT@M+P zlb!I1yS@wUJKgm5Fm}%)Mkme}MUv6R3)`aHVuw3>=5_8D)-NpDYl<2@3j{(3P4}yh z4DRXZyjkN)TD%{X;_=u#IN1|zd}V0}I|~#?4@%%eMrZ+~yheLhJM;YU=bj98F)dAg z2r@er9yF!AP;!@*LbF~Cnykrq8QRS7do%n#$4_Z~fKqSxp$&!h-5>1e*%&lwk9Vi( zk6ZWAsVnn%u$xXW`C>ztMG`?X??7bZE~GtZb|%OcJIM~W(CH;#?7ijE@}UgNhr2@a z!fa1zbs2Baq?m))5qw1Cxa{~mh%eaD*U=vxjvZOdi*XjsI{pis=&cmSW~1KN{B`Wo zosHb<>lk#fugH%xDz`#PU&qI=7GkEb({hfHyT9;ti(Tv}{;r);yxr(b{`*mSo9gbw z2y-~Ue+hkVCu9hhxU0(DSxofH-JRpfy^P(#2c!>Z@&_tRXL4WD+d}aq>(Ezw+^%G( zu>_-mb?(V{!)ZYD?ZJ-FMsZiUyAwSb`Yp(;gcR!A*Wt8QsPPY9$U_=FIxZzw;+!UN zQ_5rv!P{gUr2jpQzP4aTC)%{l#*X|W*6RqBib00a?X#WBKFdKI&x8B@zLHHs^mOmc z_aO!E_g!rJmIZGk%3r#Jx8)qT2c=V{p||NVgpy^-$N49%f6RL5I9a_)?s@mo*-PWK zzGuT-+5N%W{?gIYZDjwYIF#(W&qSGgzXNB$e0{JZQbVQBd<)tqAh~jDKHC?uftpH7 zDvxCvj#+KT>CCRIIpVHMkVBW^1SsiH!#eCV`@DU{r0XPiXMPs)qYrbH!!DGb1D%N1 zci{FUrK_(ao8ux)z-fxRYTWnaH^Lfy9fzZzpibFZyo549=N-pmh6=M~lPTgWc1{Pa9RXE^Fzu9CANFZP9YE@NX8;3(lAHg7b+U zMF~JTK*Z6I$E2g0VUr) O;cOTFiNLh!o*hD?}dwl-E@!S zcASISi1Uv1N3#8NLS`eMkf9qeBq7TE@k=O|^loiF$Y+(Y4kGg%zkcMm3u_v)$#qeF z;uO$L;bPqNij^M~o9b5)kLX5QcA&O&O z9{quUhV&ME!iBd=QGt`w(sc>kX)%i80o2qf6wCFb0mYK|jU9`3zx8V+v&74>0J&Tt z35g6Z{5AUCJw_4gxs2<>A9z%(cRgXMScyil`&6v89f9OaU9~t7A1yY1+h*0GpOU3E z+L4Q1Tlm>6v|f**m)>j9@9X^gA^-l3ev4d!ehvKQ9PBH!_C~44-~WbX)c1AyQ3jhb8-Yd-fRW(VMS*q}ZooTT?1h8$Vb`y=Sh$lVE-N2#V9 zrH96= zX`jw*MTeHFvd_lsgk}$UXmK!K;rESUbF#JbaYAS=LvxE1Qg8w?0!XlfWE@6_;kIw% zVdzbA2t9K^bl8BX%VjhjM*9{v-$%$C)uvv85!+X{QR=1MBt7SVYh-7KKmO=8%pMj< z#88O4smJ$7Ct2Fgo4f;*Gx@a2T1oREl;H&~SKdK60}6If_|O7d=G&MRg*Jv!GH5(n z$+1(eT#6j;G=`vr&^zVSz$Jw=wd)VnkyKgvycWOM68hcxMWi0C^Yai_Fbn2h|^{JyBJAsJ=zH z1`qxXmQ{;h_aUQp0nM%L_NOPWwzzgd7-KAd{Ou>nr?)c(w=-0} zAEJ3m)j%{kt_j~3MV;}-mwcN>Aaaym%WWW)fm$vD-_^>%!>SDI$S4D{WwZMrz30i{ z-sSU_i7&#&qf{={B2S7`4%Bik5i;@wr0@h}G$Yfy^4r5^w4=6f=N4MW9<2F}K47+c zVt?w-ihalHj?}uW?d9-fnSbNzbKuCDV>IEIu$CN8llsFoVHG`<7^>V#e8nr zWi+0}*ON9~_ta>Z$_Kw|bfdmO@>OQeSq=dJJQom;AYy@2*2XIEs8cI?6fF z346mA*x&RR<{L~MOjI9wa!EaAZ3l%@|8;VGr2-`qsmC~0g>W6S?q(iWbbr$~_|1#C z>^k>ZXvr}jM;waNea!kAVwaLLq~aEKnpDp*tHqIeO`23CE$f&SV;niNiP|!fa5zc% zoF>UUW?kk;qSI>o3|l`X$$QMYC_~aZ_vm?2Vkb+4AG^+Ja(&0Fp^n_aX>z4D2$S~` zk3`a}kbTVhz_uM?e$TNr$wyjjJ7ZNKExw#%*kND{cK$8DWu#-!G3%F%`?$1ed6aw1 z`l%E4Cy3G32)6Kh?UDh_dO&*#b9?$dj+(H}Jqogr60CV`V+opuxJjR;Vcs$88%`{@ z^IL|7`Rm(NDo>VU1+C2GiY|g?C*;8uT-whl zLyJxMEc0q8Mvb;*QYj}}e8?90#43br4msouejAlMBbK)m<5r_L?%CI~ahJJs@UG&X zbBx!!&)HR65|{m=oTHnCbS`g?;Vl&0#`p>^XMeWx4=?QfIDeCPZ#TxBdyL&%9!(bR zqqmX0^g9UiKIy)$+`a6MQY{pA?#IiW+a}tBk_1$X6oHNHhylq59_pK)tqkc*6z|X zu*;8?i{h~w?g4Hbkoa(n*b9o7zc>r{**=NWeS3KV`3n>IuK0(Vb$X};M?-xI+dq^44#<8I(2WiJ*t?64OW4{Gn> zIm(4vxC^l&O%g85_q1Y0>6LMtn9Jwm1{->`8J>4N3Wsl+=Utz}C3iG`4U6nGvS)aX zAx;ht-z?8DTN->3&#{6OE$lf~;`oeO&oO_>H_dY_k@C&VI#yx{!UkWgt9np zpOGJW%N&@d{C18&OQw5*#dLEUd9+6aP=@6l`8{@B6k567`2yw9m@bEZ+5r6Yl?7FI zC4ULm89D*t<8qWe+w-o>Bg7ARdAtJTIqr|o-CZ!X&GN@L{De-`U5v*czwv3D1i=@j zuKWqAXiyY-kJFs{Ut~volA&;>aTov>Z9H_psu<*T~UA`s2GEqL>S| znV6gX^69}C{XYF|)W6kB~5L%;cmKR)?EfBZL3`Qrx=n>^Q& z-|vq<`7i$Xs)RrO@e|%nB@gvCjk zUx(~_thgWgmh(<2a3clO7Wbl`z2IUR*WG|tp&aeejqbCPW%&t$kathKE&(>|MG}eLgpr5jXbLSD;_Q zX{Dg=7`qrvP)Ym*V?v-28-1P8i?=Wuve6G2t^O8;*!f*qE?j8W=`9ZuR=G!XQJ%PP z-r_tBJ;^)$X6$JH8SPcE7y7GX-Tis(mw<9f*Vn4yG zb876H{g=j`?WZ#CLJq96j#>8}zw9`DccrIPywP1cI&pJxFzMp2^W?|etvH8~KNf5K zXJMsZEL@NE2C?V{{Pr%qiANvUPxv+UZP-sJaP|`}SBO8mYc%XF7IU~34!2l_!+yZW zip%Bf5ZF5tK5y6h4xj771D(a|J0{@whK`r;U_O9ftYZSDdC?8nZ4TaXGjl*nITra|q4?9jHC7$cN6+3TZowq`M6RyR@i;M7aTHJ*|+M3yYg^vLmm)xohG6zgn*Pg}{pb7E=$zjN~yK%;DvY>B^(LPE6S}fYv`R^a*D5ON3 zfjp|l+bS(rhLjuKXQ4H$>+l`y^Jl$VM>{Y6xyR~|MvSD3;m5E11`@SHeRo`KJ&JK~FYRwOQOzn)-)!1zc=3%odnX!SCrjL|Qb%*=_pyURE6Ov9Yt7KT zq5UEe?ZU4=Lcb+AlTv7nsZGx6nqk)6J0m$0>!sQKA)MMYmxbodQm0iyIMl`$! zp)(aKTQ>uzqGbJdi7bpGWlL~3)&!`hnjorC*2p#LtIG8bM$1^T*%n z_I@C)r!lvjZxu4<9;2{`Zsw9(rrciT3d~>$7ubns7nWkTm)wym{74mkqzXT>NQNI- zB*Vky@NhXiTn;}>g&(HE4^!cXsqn*8c(@!ME{BK9;m=gz&s5>hRN>E5;m=gz;c|Gm z93F13w1;hp^OU6Xl%(^Nr1O-d^OPjGED0`4g3Fqmufm_N!k@3gpRdB7ufoIS@NhXi zTn;}%g&(29k5J)9sPH3Hc(@!ME{BK9;Y(HcQWd^bg)dd%OI3Kd93C!*hs)uID>pmk zG97;AAFkvLSMtEmbhunX;4&Zh-Bi|0LEmo363^^@ru&)g&pi9g&*%#eZu#Kbm(RHH zxao@zd1zng{sVpAC@PF2;$!;WrEtwa>qRRG^fkCrw88XE2w94+*-h=jWjx2d3?rUv z+(zTb<&2G|uWu1zYG2^u@e@uAb-&=j==qu-xiLeBY->`#`&j#&RHLaclH z%Vbe0%iUCB^kI%RbBid)8VYOcIZEHGdlYuN&fU|q9HZ^_mrFL5Ti+|-{*AR?Wv3r~ z$&9}5l@^MqHMVJ|cbYY$cq2}4%P*UWO*h%!2TSJm+ht=W#^yK4b4KHR=nt-QKY!?K z4k5qM<-cn^zG$|7;4hlJSsS35pZPsA8mX_x7t&JSKC{oHKo^YWi85njf!*6;&LXiP z3YlTfvHH4Fn&bN~qbU|D(=*jqx=#E$5LtPpZ3&b|fBf+u8SOLieVf}bf7pBL%p5AC zhpq1)=WpL|S+~D%bocSc5AAW|ap5uWhyTZd1_g?(Ag#=A76W=vRA}DJ950Hicl20v_OaK<-+cCq@1b|@ zHR$ANQ9MLnO594jg|z>_yEO5$M@xTc;N*W_8_LD^dUoO@K)9(#M6v%*`w2D0lrD~q z&H~2%rgR^Ib0bCZuv+;VtWfvnAurx?{7x0$5X2Y8O!rJX%>G+o-(DKY8$-Ij&Ao?aQVSAg3(B}0TwC>w$6!EOM7w3J84BCO9GY6z$n-w;L#Wgss z(DRf;!sex*Ae<9oR9c7=`7Z(g0OK1qo{{65USl+NBi6?goUfyKoJ*MSP+V|*(k)SR zx?Re6fpSZf>sM}qUCc?zJqsgj>C#sX$WLP_a%uO6TpCxCYsH$BO9=LvmC&punoN~`m z?zzf6Pr2vAr4pQSG} zRbNOmma+J{>8F29ht_4vaawvNtVAnAbkE|jbI;VtOs3S;%WVwcLxFy}-nr+V`2FLBcir+;RR+=qhbwNhcww)cn8*Yv*9 zX6av-461unCr<%=JU6A1cM( zrn8NLsS%_VB^&2CPp|Ltp~V%OMm#nqUM+IeUiURMuJpZ- zKEu7AdY3+9P`w+LC4WBqw>y68J;KrEXWJZBzCscb@f1oK9u>Brp7yQ#49|Witj9s@ zuw@d-Qt@ZiXK|P;C8NagJ2Fh0!-;>DL`;jcY`Da$yiv(qnS_-zXn3DyUevh_NUZkIuh9c0La z<9A}uJHam7m0eWq*^WJ=i~`$VC}p4wqIKl5h(5zEi}*etmr1*f%Cb2oz8z(i`WCqR zt-q3svf&vCn{79Wc+HLxqll5cP1y;ei2b)CU(0Y-?RQmwh(8Y@Asu=&yD1dx#lMrf>cAl_F$AfiSupJyqch!&cy+Lys4`IU*M!Zq@wHA)9i=75X}np@2JpT zjICATH~&bj^zXxD+UmdV{YTkK|3XTpt^OXZ#>Q#Aax|aVA@>uE2KE?3)vDQ0wQ4rp zISV%&HENGB+&K$39CJn*$@}B4JTWGI7;`{xJ-OMqwIKbuXj=$(qa`5MgVRZ%qjkV9 zw_fCy;QSiSoMG3A@%_U0f<^ZjdP?WcrBgYF(O-*#Unxu!P>m&NS!k6IzO-Z|oo%G| zUs!ZL1pL^2v9S~qL`3m+b1}&JiTi=VnG>w6{nXuo=(JLxaz!8+V7VJlJXWc z-L0UT6A|1mi!@f_o=9XKop}!bIXXUyyS@d>!Z>LbPWDqrF)pYzr&--a!U`8pA3q&yduO!ZHd+&QbC7;d zKTeb{hDFUXE4nIj9e8qx=h%|4N$YgA5AViltg%gEo3)wtr^46^3g^4AdPDslo$5W^ z*3zTead~bB?Qt@U8SlxyfHfwbFp867a3?u*QP7;)M5j#>II*9L|L1_VYZ2~!V%>%E z3#&uBsEwC*o$2itI76Je>s&B3tonf4KSLj2f29~TSbg*M)cp^Qvl500O|fH$w&7$t zrTQgW%aiMOWKBC>iuH6Ta%}VW{dX$aI^jf4gV>W=eGc9nNDl5tZRF7xzHQ?ff|hBo zk%hP1b{nU2FLG2yXJ_m-L}2!5pYX|6C+7yEybMBlQD^YzY>zs}lL{r{%14_iWqL85 zw@(X-P2cJ{t^Z9m<`n;%iY21#NS>{<^UerDR zmTz_Y==9f)Ex)t6=lAR#p1*8S_X3G_U)3}35yBVj*z(AA-G#!~dGC%wOFV+-mV-Nz zk36ueYu1t;pJ83L_@OP^lank85j3l|lRa#sZ=noggOee-L8?>?_w#L_bFUH`(uV z{BpnAaQt+#WP-r_v%n5v{YfFFLa?e%$i-OiW|_FlsoYx_hb~3&^xfX!yf2R3Tjds^ zj?yS+6kIvF!5uX84)}_Mg>!nYaB&bVdrn&^ZqB^+GzJ=8iTrgbt+vYVd6)2r%Kpl> z{I0V6qOkmat^8`L{ATGyl=wvjZ+hH=dY5}3N;jt=*>~VC^v1XUP*(-7fSH&VW#RG2QfZ3EN`(jiX|HK` zQ&CgF+rs6)U<}SBx-J-n{ga;3L-_Ac`0p**qZakX4?XR>uHt2v z?Rid~$DU_>xX>TJ7pEYfc=~jE@yzuEw0gLwLjNyto!f_-4Mp+OoBg>i@LbT`bT#gk zHltrhJN&_jrl8nuRy4UTD2b=2O?|7f&ReVBC=zR_m6HoZNa&X~UTG~L%iPuUx$lTCx8X#MD%A->7h z61^?l(X;*bK36uz;l4zkRdhe*M%*Ft^zSNuC@Fn4rW?Lxm-*x0f119_X3whd zotQ3~>)=Z;nBP-Nu+Du+w{$OsYod4lSrbaX81XIfnV+2-g?JKAFP<0ijE9W3;J%0F zZ+Oga2r&fDXgufRslf9kJhgZl@LYqZ4bNIUx8T{1hh*%7dkBw#qB9mx1kX}DU&qsp z=a+c;@eKZF$xmS>;(ZRD)p+i~^J6?O;~^S7AK`t}H-)$iPcxnbo`>+*^k?z@rslVC z+cob(8t}}(^Hn_G#Pb*)n|=WAf5J2LZXqi1G~!u@$EM$h_y48&590k3&0mbViBr&G zF`nD-?7;I2Jb%P9Xmd)AE$_3s6Ch(2o|Sku;rTuulJOh3@8hWygG7!vg8z2w-7dsP zJQMMR@yx~3hUW%6_u%;no)_`FhUY)=pvQR}?Sy_qvXVWG1p_2Hdi4_wkmxS6^eQkByvgK<_N?R@{DW5WB(nSbY zRnpkHe$kqe=_}W)UA^ww)|G4Ny`_Eis`k~3*0wGY#)K?);x(uo4mGb`w0K1;_PeK| zY^3~PxDO1g7hRvmkn)4!`(OyQuZ*{@UengTGSt3qc+sQ0VQ7$UpIiIo&Nd4QA?;!;RCAr*vp6jC9)Z8DU}2zh{TD4#+Qs!fKvlD5OG&VbSSzjgeR|(1>BaAw>4@=kV)x(eDT`#OG~TyJ$6% zjYM2TiI84zv~6YE8cqnK((4T@S>4L0hf(SEhT2xQtRPjFsHpTLrj z0vBkAT+t9~4o+`u5QYg)d2>T!pfMtHJ)|C&Ck-Wz3dNC)GhrzX8#Pz2i7zP^KGui63hLa)|O(}9xJr4hMo>R>U3)MD6>R5A? zw$Pl}O=b9>$f+n4VzLXBGbrUkQYv(fnYThwDs_dK0)#Y9MSd!!KORu&3OhqsXw?Zy zS1ARmPf)sAQ6`W;p>cq0@0POXg-zFKky7>>B=;vYfezQMkz4m1f{1)N;zir z>8b(YJSZ>ERGJW7>B>_oy)$7 z3eJf}8)MUF*$Tqj5NT{CNO(D#*QkxvVOt6BKuXx+PNl?kUfoKu2x6_Xb&zRth> z!PN{lS{t%kF$bbNQc_M8^#^HDH#FMOPM_Tf@mG|qZi8DZ2Q$@Mh3Y(XDhixzwHmHc z{RdMWjHqZHK$RVcO_i7}xx6`47Zb7@(WOh==Bi*W*`4TI5;r4r8k&Q1qva?ej*T45 zrdH@py`mxwswnxKfLhstl}=^W>wJ2SHpc48ZNo}AS}QIAGD|ahvyh%>2V?4-rdU|@ zowm`M8KW8wmFCXY6Y5}QsJ=l@BYDk0=!#~zT63ikvte$-tT|!a_;FIM5R^Dn24SRZ zDFM6dOW~9v)%9`8Pi3s6xzX6LbXCE6KX<18B!~W4razsTv&Up6grq0nFp#2pEl@7 z!%aK2tRY64DO+bySVy$%DF)IJfM$nsk(DB+;kq5l(aSnTK(hlz6(q7sxKm^a*mfvK zljMYS(q`KMgXR=f*#R=`bZ|~%{^|(GAW+kWLUrms{x3Nhh05vPseDI}C3SjvN`WSg zf9htUb__~&<_<>G`YXe;^@?aiL<>%fMM3qYs!s}3g%p+1Zn4R5Y9N3_oq7x~W3Zkm zYK0m^u@^B=J>zM_vy^NbP!yg486zmHq+mXS7u7}bJYy<#0~$tjXAnpn?yu39DGk+m zz*KiF>(b-7Z>2%a5hnLfllTMeZkn%YVgVO0T1(MGC=cd!8_L5#r>JLt*S8MT4 zB6?mreUe6>O!WM8`ecn>L-c}ldW}Y(Li8c&^eGx016D8$O=kd@vJeKY;5Z|LL$@Ku zoZuLi!J%6bV^46LnZcpkv78M#JcC2GBu1x@F(QLQ+LG!LQ49N1WnM~eKnLa;H}YQU zaggcodSx91TEw!Xmr+i~C5Y#BWgKrlCP+WRi<0Nxcxk^)V74KiITE-BD#s108! z!)xQG6sQcQ4WMMH=5SK3HhiLR66A1cLwE{Da}bIzI=8M)A1tLnDVOQmSc&CIki=jy z#B_?e0w_C9r(7l|A7}|nGQ7jLc{l8__GC4cUb) zCrwuxR>+u7Rn~rarlTqkw!q&Y#(En`Z7wT6uL6Vg0&Sp`Hk6fjuowW8yg=(~8FhUq zdCAKXxU_k=w2_1u^P&}jge-+pqmpWcO{cv@pCXM-%-(xROXYV8tj|Yg1{z@AAaTmx z8(0v%7PTP(LI(+|QOYlI=FUyw%ultG_y_+^^0S}#Z9-l-wKz85WfN0?{LpaV(hD>e z;WWywSbBj*B`P~$>Gd{Vt@@LpU!uhY=}q-NvZs}$8oVk`hJ84RdC3bjf&n@yapoqh zg+T=Sfk*4GzI=>R zF3^+L#zM2BoV1cBNipRYWowZM6RQzdK1Xf$uVfy%{>@Uzt7^@OGe*o<0%UPzoa+_51p zO%zUFWkCUBQD6#EIBj9ifl#iHkW(eRj%t;ia8zI|QR}I{RS};me=eaWORCDPoULi7wjK%A+9?T` za~f(JuWYQ<*CTAm1WPm)xkC6-Hnkz5h37V2rRS0j*=fj1Yq=;5QlnEP;Vmr*(<6b< zOgjyDOr12TCv=iNE@wZXll7%g_7hs8 zuYFKI zJ>4wP|1X#Yi9D5Aww_GWEeuAMG7M9^S{Ox%#CToG zr-i|qlnld^Y%PqUL}I*Bm7|5hDwPbwltEe;MTx|CAuv}9gH=EohAD%!Fp3h1@#0{f z76vPWGK^d{)WRrABqkROwJ=yMlwp`ML<^%Rkr*!`4%Nb-1(ji#a)uU0QIMy+usBQ$ zM5~H2l%$=h1+!@g$Aw|I9!}*sGM{N9^l(mjkc*IodN`*YPtnx)aa40rf6ocT0cgRjux({S%RbR2T6x`^q@?`;Im z&B|zorPmt{GzRF{6~q-YZUf#}lA(`Z$XhsO-rlQ6{(NGX7n}SOmm>L4cIeC|+a8z{0 zIf0j@aHJ5Mt>wz7ekRxeQ7RNAXj2%F%TLX0moQU!f(JmB0m_Of<6HzJ%2C%kC}PG2 zfD%80VddxY!tGxj!&F|7t}6pG?RA^kjN5>hmf^~=jH86rGgSwfqawu-b2w~}IVw{e zjShzmGDlU4qsig0LFTAVam;f#Y>+u7r8us3IBZZZWHocin9o#R$^xJ$Tsp4NC@3E? zsVemg9hv3L1TnROUy&<|9jb(wT4__4I8+HSwaTV0b*K_zYPC&W?ocJf)JZn=D-Kmc za-mA5a|P2Vot1VvE1Nl;D>VwG6RQU@QAo)uDbazL>ZEhEL$%WhMkk$X9jcv9P@Qzf z9jcv9P@QzHcc^wcL3Pr3gG1HQStZkX6VoW21h56FWIAuwD3s1CB6d36;}V7x>0nG& z33ZRVHAPk_r3k92Zo0?aE{Qh6QC2sj;c}0=QzxPAl00a=+~YRtBs5@>geJ^Au0toG z6_X^CR`LiuCYD%7a+}%0}>1(K;9;1crtJg z@@uk8*Y_le(nScTYqHF*f6+-u*YpZ%r_0$;-7Jrx$N{AwH z+J3B)khX@9EFaieaF2UR5>ptFxhydGUmdc-lwi)gpX!2D8f#=4_vj=llPXS5N3SDP zl~X59CO_+t?J{YH=F->akU2E=NoA{<{JIMbe79>9!VqG=`5G&{9_u?PG`AHXMY;ePG`AH=eub{ zq?4LF&XV^eMfw@$%=mK(hK5AtY(28I-{a;hCtxtta$w!jH)+WeX zhi@sN7Jn>p@_Fm#GIU%)@QHlhF0~iVuqcwb1Z_hmc1p46t1UoFfKFc2rL8_oz-+i` zc4!VQnQKQd9L#LEGD;qO_0xvT+J<_ZYYR_r5@u?#SOXQ&og&)oP$@h;rXTB5h>5jl z9HpBRP1~-}z%!*CPPK@%2V3oOr4s=l`}EH{RM0N8I`5zdr5IguUs^x$z$^e#JJ#~d zgWSNTY{P!GmTi=5eL=o4MhIuZbp7x%8GSmAw;-bf^Yq+Qh`ruE7z4fZQ#&%oQyFL- zB~va1^Zu=^A_}msA9-=cCZwxIUTh&W>ROSPRl>SQx=OTpDPuU5N`dgL^VvJJu&RX2$Qz6hgmG^eskDQ&>pR-sMR z)UKnh)fbgfr?YLlFHNP?w(b9*sZM8mwvo;m*p{LlKKq_iFqF2*fbvT>nS!CTEe7@z znzq5fenQi>7uZi|+U5fL2~FEtV85!Z+96(5ifG#n-D_%}M*_S6qw z$#kv4YtiEN_7zz8C|c9DY-Q_`l9uI*R^y6Y(YlpsfUoF!qBO51+M4CG~$gT++Ud?zXx- zGQ9G7Jmp3`R^iHxD+0Cnjn&h8Lp{AOX{g6<>%2z%E~TGk4Or+YH3zr0436~^Y1(!s987|3M0GEU{!-X{0=JBzz zS}5S!JOMA{UK}fzKp9>LsEk!epb9SpOpaAbpaw4lOpR4Z;8MI0aCxj+0)D&@5QvtV8Z%-+@}A#-lS=ebiWlhn)oA_P+Q8L>pbL*+H5&7h3)Zx* zUAL-v(UKPNzymt<=GifDs0!4pWJQNhu*u3n6qYOsNrw{lQ>|JU5czvX3Q z%Zf$In!}OcTHR-eavT@%ptK++0Sob&xq4T30Sn96pD`2EmaMkfX>7q1fwJ zx5h));==>3ak;FWh7n!S2HQ096OOy+OJt(*t|hHfke7|qIDJ-x4&SbAZzfe}UiW~T zg$zhOArQ1~ZHwdc2kvnX4jj(rAZ@~n)-H-cqpuPFcFCUxdl#=;x|H;Fk9)|?3M;_7 zXvvb*&5Ks9LBS^K59D2c9hEGrTU(SqPiQO(mFm|;0$5K&8F7z$Qu1(GZI~2=(s5)s zvHZ~FZw+W5F*Ml4!9DKB4ucIc1FWeeJe6Wlpv@3m(cbdaS?x>Me*bEI1D!kN5amRQ zM9fi?>?t%-ghKzz;d4-L5aqLd(ULhhP~aZ-QXjBqVcxZE*S0oazo>0( z^XfIt?dv$gXC>DOBry!C(N3ap&GOS1B(lR;UYJ&oG=Af4SxeRQo5NvYB=EHVWH zb#^f)Pgf0hk|br4%nZ494+K_xa;({%&FHmJmL#taG_a8y-CE)dz@7fIcu;dTaH zszHVVr5lkjRPXXRG(1ilo2Z@W!5?%GR)-6 zdRM88SXq-<^MJ@O_;LjqL@q$F*2;)g*p5!80O2rIC^i`sRgkJGGAkeu8KzR7+EP4K zb|aE@ZI~&_236IW6%dG&hK1V<4U`S4u&|LqQ8uWm$*h1tq_ioS6|hR#pt>xx0s`SM z)%ZXK#gi(0KqRFivjSEt8&p?jRzM&!OjTwDtX4Lt#^+En;!!rJ#=>(3McJSlDbAoM z8&ub1RzM(9gDII6uv*z*QdwpN1j1n^saxGC8vv1%ip&Z)N!ef$R&~>LBLo$YtJA3} zV8=AA0){dw;H0X|3J651Q=M4>Cn+ONnv_`qfyglU$DO2Ts$xu1Mx0cWSpk8_FjF!s z;3Q?l$z_=p5D15voOZ>Zia!uZ!M;qo29uQ$C!^S8P*g#hT$Nb?fkzwM!HGtJ4dmJ%s;1onC;$bSi{+^b@}QYo zL7qN`2Xk0vz$Lp9uk4I?PBxFqyYdsxAKSom%*M%2cnCxF7|+CPibROkIA_{499V>= zrcG23s8s8SU!SsWAl5mQLT zG}OjbO!(e{O4Bf#;=~k6#WdU|+A+zDKtzQLXnLperR*idI`NV@7$#$%IuvpaYLl-P zw$m=a*btU-!m;V$x`@1GskH{_1l)6-Qy-j(Z-VIULJBnN1F`9iR}ozs7NNL|V(q9ft`u^gwLMbiql|P|C8Ol^B z!)qyp(iRHz@qWLx);@c-&$wywfEX<&wHQcy~+_lIXGWHmR_M07718G5afmSes#$wEnn-lvo!=2(SILMNB&D`VC~o<|;ag zr=3^BU##-VT5>07&iCV!F0$-#!OKcn$B;a(ACyIEt|4Z!oxQ z(`}2h%S{&zqxcT-Mg&{XSC;KzQ|WkX9IHz=?#JSi-jXa&T#ij*tVd>Tv6?Ko40)2|1?06Hc**r z-7&K`qiXX3!0n4UB2Vbya!F{pZ+2OhiY}mPJq^)oai)PiBs&#}#hL^wxA1SasaF@y zn5y3-(lEf%@eG%@^UT|o5`-L|Q?=))<9#JAl#zsKN|CTg;TKQ`OBXWy%_J*t<=^aa zOxV6-*c3oTKaBsfDwdL-Ot=W4;`45Tmn{aFSvMBvg(hVU^(Yst8zk)upQXbz& zzE=L+hm9>d`!j~U=`}8Vfh>;KxHx|6zU+7(aR9!f*AgzvosQ^nCFKf6Sa~e}W}75V zs&GQo2vvBOQ{khl?xQH(w+eSAC7)X5zQBi`MqUoO8FN5iqjcaEyHaFd_H>1;@b6bD zcAMh_D|hm5wrTP3oFwt5Nj6AXMt{^SEd^qjF`;5Ywq*2u%vb8Nt-H_jyxderwce=l-kS@ zw4d!k5Zs;tAEj9ZQeuO49zU+}7VmE9nf{oxPInlUWp7&tOs`dLkC~ox!YTVR^?}`?eWw zACYEBp3;*1QYOKJ;>NF1%u4d>Nmbs+zghOm)qb1T%-r(gL2Rd6#9prj;t!TDuN?V8 zhA*!S)Eby|YV_iQL+zh}YhCHdH!-{Uq9G6}IU#(cq&m8jhs(WK zjzO>kg8cZ!n1-->=jfinT0NIvk%iZ8gRY)ung#$wjzWZajjYBVrx}w85eOZNh2+jl zO?DtCXczlj7i~vcA0DSY&I`fs~kb0bq*&Ko} zw9jtN4|;WJm*+MP%%h;DE?&U9}> zGVXaW)k!DmpE4Zd_nxxSXKq1V69DJ#9p`O#e+b_!VRq)DV6XoP=3dy_e%MbR@_wol z3_4u@;JdQy>-ewJDZVqt@*@R%=}hsF>}ez~RlY`zvOv#$qU8GDX;pMzuIWp2P46i!{$J7*${#zb`EgV_M*DA@ zU)-;NK0+cLtpi%dUVAuOV>YW?z(nO~#S98lc>_VIhs-3vogIGr6!-K&8Iwi1=`0}c zIt!eLL=gR*!ii)!xJ4w|d6P%T-9D>;oD4XAixRhFm8nQ)Ov+N6V>0s(3q>kU(Jf;vI035|@jUzZ0C321cmpQu+y~@?KtC5v{K|WF5j~ zr0vwa`Pq5SRC_0I=dn{06femMw{1Ac<&D1rQkQJ9brwXsNY^grk@CQJkU1JqkUa{N zamah@dO3FJt`1u-!a_RmMUIb`6M(!R0~R zqG7=V%eMh45+)ri;!?t)xXx8A*v{zBOO2j?uu3jt()0$4xdAHQ?&(p9U|E+EhKfW* zC4v${2}4C7+Xz<}UxyeIw6%}h38Qb0od9z(qryLEV3hutZ>to~n*Vn@q zCdbT=0%telLIPjAiMDYlf(j2U1U5GY&g~%Kac@-M*5nbw$#;HJC*0p*h`dEsu*HLK z5h^2VctuL5w}BzfIB{Do#u-B!kF#%WY_s4qtbPMd9&$o!YG-e)=}{35>=^6Qp`4oG!xBdP>}#1RN@5E} zT|oVYlu(^}2RP?PQT>{Q(UJ#S2#PJF3{1CpR#anigfUD0NFIMimokB4^LkFceo3{oymVDCgX1Bgj{|~KOd0ku|2v+SRi2MuB>Pf)N6nqC&tL6dI6R4CvWq-xe>0N( z;2$qzo#L5X?=Z!2F7YiVQPFrB0tW&C)XkAVcLssEK%gfPz@bCepV2nwRNO3EW!;s% z?WYkFiB5h)1W3pA&jCWBb5g6w)pv>v2&wa=WzbJBX~Wft&!X_n@^3wtVSykrLa1}p zpb^xJ>yW6;zl1-ho%dS&^(x_t5gcCVNZ$Q;O#&e1ts!?1XGVYy!}Y@nWU z@-o3Yk<6jR=CeoVsw2l4&T8Jt(umN`iRR+${Ql9o-Ss9`ji9&4L?~2b4zEKt6!~`A z31*qyCB|3S7wG65tM8ShNDD)vv#N-m5+aeUMIO7Mx#nijPg9^gS;rSeeIJ%&c@lS$ z1Va^))2)l{ zZ4+}QOSsNKK|YKrjR+q_toJ9;Fvsv#yBs@~NAmEZ$3uS6V-x!guJT{XzVYrXyXHOc zH0eEfe8mQDgYQY?l4u8amQGZzW*FI~{`t8Bvo|@WgnU>+PZ%o(Kecl3^RhihTHS1r z&aIEDahDToW4+i%o&Y^jYgz^Ene*x`uLHazc^%O4m0!mWltT-dvtuOO%x1kVZtdsYxs41z!S zNhRxFIy7+`u7>-KPclv=!20qUXti`m-(LHd%5$2WL?3UUd1Ua=Vda19GvEgR-p|g0 z$RS*j!%K=j{yFlEBJ){UHrPKsXY4b-0=B0qFl_?Wee*|~2;oIvaw3L6=sFk5SZ`J1 z`PQ0}1>_)zopfSVeCSo>IxcW>IR?S^1%l%$_>*%3LB*)uKGklY3gzl6O@SE`Xi$Zlk-_Nyf8c8j~#BBS0n!$fkY6(d7p`Kqo|5q%R|Hz%OQw;*~HL? zSE*n9iAgyGLfJ9gqSrHH;XLkC_()EYJ&|SAnSDzOCa~>H2m}B`u5%*hLS7{Ip}R4h zoS0r*9^J2syp28^08|$B+{A3tr~JqjP&P!U%_Br;PjhB@k}XSCy4|Ea1hI*QEW;gY zrZSHe@k%u%$;MGF(fwbhBp1=D&xCry;O_P^Mrdj>uHz1-lVZ1VQXFv`163bIS)*=ITkx$wob87lMI=WaODi z7?`s4;*ym*fgFNa*IQqTX@ig5jj?jyZk*d~^pEfMw>AqTNO-V2KyAeV1L$;}BMhzG z`0KNX-UfO4T7C3sgKn%R2!R$A1Z<~)1l3M~XTCgFfQ!4m8h1yzw>P@JjU=$>>Nb+V zqHEho0*kI}BMB_Ju8kzH=&Cl7z@lr~NCJzlXd?+Mx}J?BFx>Ux=M98}lF_wnLPHWI zF<5XDnrL(#o6tm~tJs7lilP@r2Ab&BaOy&6qS5thLKBUyUK5&VbnTkZM58O$ga(Ss z)no$4YAVu1qpQ}0CK_F{CN$CLiZ!8$!h@K$JX}dze6<>+#9r~WYCy$e@s(;o#b)t! zYCy$m@l|R-VMY|1=o&SliFRxLI?YJ0(~`@g-qCsA_osa+D(Zcc{jRJ})(3}s_;zr< zKF2UiHaOf(?rDAkEXT_A-fDPon`F8ER9qx7oR$4#mqT>o4TUtWGjL>lf^W#$w5H4u zw>lVK^~2RcZmB>L_}cv?`XjFl{d>^9B+yaDoz21C2~g!4wi)^I49e=4V0(nk8%_-L zhO4F|%l-Y)Ie3!gdNsOphNMf+nkWZQXAJIDeKhr;uy-Q77Y$UoZ(P@LEr-TYO8VXX zE><2$m+PjAVxY?XHRvPLnu-Yx+jZ+&tqHO|>l;*aDg=rL`~zR$0e_vk1nL~b0NMmO z+|DF_^s3M#!@X5k4)NHH8{V?B^2{-$jNhIes6;?FFFz0%1O)366L*Pcs0C5OaWMycu-Rt&^Jyz zm{3*#B~tT5&Fdw27VU}uB^+~)>7*bbop>JQ>kwN0QrT;)$N=d3_^5=;HjyK&xJ&LP(+P!x zn#Ig|$TO#-3)>WEm-V`F=>BTTxnGV;eeRZ{*ccR6mO__Du?Z-wFoiA;<07D-!X)Wz zqrI607(^zq6BtSNh(eC_+qBbFyiQt@&|XB`fij0f^SiI)tWc}7J@3`yDtsphyxOp zZFxOZ6sl9MAs}`K&Tck@!dkS3!_!98du)7fLrxwAjeL%kM@9pt>XSnn623_T1zirH z?;hs>23q8!#ffovE^%D;8Rr0;fH<1I7zdy^AX~{+>|o|OuWy5i4j!{&j|^@D>3gEf-C;-U@`SX|UW z0*i|}NMLbM2MH`L>L7u|MV%FCmDR3q4@d%wi#kYPaZx7;o#UcTnrPI)6q;yU)JYSK zi#lndaZx8tG%o6-iN-~pG|{-IlO`G$b<#xRqD~rUQq)Nkjf*;IqH$3tO*Ag*q>08w zoix$7s0$4=F6yKy8y9ubMB}1PnrK|qNdrxaI%%SDQ5RZ@I=@+T|I-q;z9}l|qxP*e z4s*uh!cLlKT--?$jSD0AGo;1<8;FBgA7k$!1Fk$8G^ZvuErWz%{*zYXH~uCe8s|)0?;la7}OGAiy=fiHiW&^d?RMT+^Gl32;qs z;wUJ3T6z;#0S@00UqR7t=PY~P96L)s5UP$=6K4U9?5!rw0-9*zETD-d&H|cf;w+$v zCe8wyXyPoOi6+hhnrPxIpou2VLKMT`tmTKxO1SFie^*}h9+SFO9>MYgNSqLzkqzw^3@WffF>MYgNSqO-H+>#(1 zO>gQfRdtqX>MR5#oVYzfIGWznSukg*@^PC2d9`oqELC-uYU(TksI#;mmOuBck+al? zn|d z@h9pKD%EhY|U=TFozRzUEmaw86B=TFo*R)Bb1xhWuc)Ds|% z%A7w@<)(n(Q74%=DmVT_m74;Bqwe-&LgE1U6Lpmp5Im~fh@*1jPt;vjK=7z?BMy7x zC$8KS5IpKM6StlK9@{z#zZL06h_%7oS@0On1(CE$ESL#m1%%Ai`bj3B)ME{x&oan% z9{ZAaMoJ9XeGDDt+R#Mgu|gA#JXUC;k;e*6H1b%XiAEkPG||Xog(ez#tk6Uwj}@9| zgmN-0?Kas~OAb8}l#No00i9A*T z!6T0)4v*zeEyNXcqG8pmQ^?9rsTC>VP*X`-=5lO`H_ zG-;x-N0TNRdo*dHu}7088hbQpqOnJlCK`LR&_EN97J$-;M++c$?9sqAg^5Q4*EGfh z34R?s8#9P&3R7ocdnn<=%^&17m8r9^Jrw!4`GdTs zG<6oXha#Uii#C6FEpGkq{ILy=FMMVmjomN*Lmkx!gOn?IDiXuloeRcDdbF4D(4OZ(>U?B5GpmdSj3>14dU zlw^4_-d;))SmY)ofkjS25?JISB!NW^LK0Zy9wdQ9&Os7b- z@fVtCRQQD^8uk2yCK?rdrSUiF^$AVcsL%^dG%E5!6O9VI&_LtjE;P}ouctJ}MJT!L z+J&e5K~&WJ*laQ$o00r?jm_|4TO~IAQKUqH?j}BPm2@`^`FC|UCyR79-w`Y6yTp^@ z@sy9yW&Dl0n?e(fs|M0UMR5VkGh)_)bu57D{xI=>MV72mU`+e z1SI^pg+(};&eU1z>MZrtSqMltaXX7}G_|R-)YVz)sk0DZI7w?OfZ&O<)Y;vneBvww z1drQX2x@v$XQ`{R)Kh06AmPL@1{-#?C^TXzVPciN?-CnrQ4Sq>0APLYipoEToCX z<9>#90KObked2Ab8xe0M`^I&H`N1m^ce?O=Z%u0M~RT&H`Lhnm7w^O>5G!0N2ze z&H|i;2lj|2G87OzZdo8`_KckcxTZI87T}s*_(pK%gW+p>6K4Ug=}nvkxTY7r5lmz- z98GWHEWkCriL(IL^d`=NqNk-dX<2|fXF<_#*I|A8pT^GOTb5cqaTd_XUbG~^2_d10 zCe9))OD$TNdDn zvk(yZ#96dufqdMu2q5x_vuMi#Hq7WJ4ycIQHFXwkS-?)5MOzl&@u*G!i8mhC0T*XU zTNV^OExoC;_?87DTZ0Al z4WGbE4(Rj;e97#1>&w9mFyrf)V+gEzj2BR_vtGmMft*#YPYzBnl+|Cv2P_&1-Z{We z-bQk#h+KkqPS)_@ouR>6L(UT;I6YAw!(J*^O%ImmVu5x!<`g_NS1@LYjxmJzPs`Pe zS(5U-wcd$bQ$2dlgnQUa<(lgG^IR;@R9~}fJR{fA!=j-N9NOtYbY`N5y;L5jo<`5b zEY6&EIkPrTYY?Yca&TC`X;dHS9T=CZ-p-QyhgM=rn&lfxUizF|I%H_+abfrNPvV0~ zEJEkz(tQcjhwY`$%cb?hO&W}rIQP2O$0oy8S7^C;Pd`;295&}3@h3yv z^qtpL*KRRRF^je<1iL=&3qieF_jfhc2m5!|2E*9;efTlD1xqkFNC(LMS|u z<*{}B8hks2_OPk4vj_ERV`A?ZF3y~&@5Qm2JVGS}4em!File6d32sGEQqbTo6r#MR z89$ibM)M`^p`@U}y(dI*~y#7N{>2u|RpDhy|((MJ!NUC}M%yLixK-qtBVsx}uKW!lI?MmpmyuVFL=)m9}e1IeW_(+FE z+Parw5AM{ihg&HW5c!^P*C!KmZ5J{MMcLW^`I10E&`eSN;PMK6u;8>ui*9Nalk z8=ur@m0?J^It~`@%nvT@aFB#%vj#pi^q2>$ySsRGynG|Vf-{J`Zt~=+iJYg9e7OVl zkye|^%rS`#2PJt-)yD<^261^ygWTVN>7R=X(ts}NarbuSVMyKawNJxv9_qA)lDv*f zSPwd&vxd0ku3)`6NlDxvj63fp(f9^6Mh*!VZNRYfW%R}*zMznlYw@D;DO2d8tC_Q| z3vt)q=8xddT6}83ZxAk_xvdRo8yXzA@?aU(8?TK{-k>tUXgFp__IB&p=gbzAO-ryiqdHo}(@K$YjpMy}$ zyKY17ZT@py>9}?Pvr4W9Hnw-HFYNmXT^`#z(ie96lwKz_DKK78@(fEY z=BU89J78FXF-Zl+F9i%sGiIs4c!OsEkVIov3XHb|3};oOdew$|0){0U6IEdRZosf~ zV-^>T_XP|~IA*56_)x&Glw+<6jC%uyr5ux0V0HhNT>{Q($~EU|7mA zJq5;hJOhBF91~Vx{2*YUN$ENcx7hsrFQMiVuYkMOvn`!+V3^j+uHb1gB?Z;X_pjlB zOQN`bA3vClqwwla{kg)V6|WI5zlGCXB3Dzqm++}Sc(1{|g7yl!=9gcoC`g8ZtwR(( z;|y+yFj{e$6+81wzw2;(4~P6Akw5DZ?=~DXaa>izaL#!@@5C{hcojENVA|q(-m;)1 zQCx;a_`H|AN@3E(QDXqU;BpHDBvEd{0DR#c+=^f{ac-Oke({&zsW@rkyu62uOP<7A zVjQ3x(ekp9*Ej|)bx{HF)82BD%5$#;8IQY+OT-Q!hns%MdHg$FmJ*P6a8W!Mn`JhHuYeX@U+CJ&1vKJLeq6Gz z=XS0Y2#yN4>u!|3&8K}ui=b=*<7_Cx(ogE>ZP`k80-G3-K=i{3Mk7+}gM=!pO%+hY zq$Vpn3=R#fLb+2N244myHP{-5!Hx6I%o+LDixA>qfB&TRV$S`Izd;g=R$Ss*cjng} zj@SnK2QhKN_|E&OZwM|laG43{*l_+$-xQc6L&0nZgfB3ZBxNym0(89vLDF}aE?n=r zJvcSi^+@F6=E<*0R#H{hL16YwU>Z5-hB~N>EW~}4(PE5)$`I<|d%?VrgY3PYa6F{% zVdMj$3f~J(!a2y^tAqn1eGg+G2yNke!EBI&?7c1FbdbJ>F%pEv25^H?c&m*;=wuJp z`+LU*vkrfYPL9dZx9!I~6Pa#3GkGKL$#4#*F^-C3WHQSB z0LIC=@d=p)&K}{F@L;(%*ozzV!ae)~;4(qv0Oi7r_Ml9IjW&=k$;_Kz!X0nqgFzix za4Jl}a(yp}Fi#C(b~k$Q*}-sr&12-yh^P1oEeE-gjJJe3TBh0DzF+!Tx}A1_)wx^= z*KmUJtw6bda8FXU1rR)1YNQ}bE`Fkwc?ATImK%w)W7*@No ze>QK}*Rns<*SqujPytMQ4M_CC_nvahYV%Y5O}19)PV^3|(yKiy$6Tf6S*}v^vA0wC zm4V7warkb9C(dHc~HC=Mblqc1!Pa)s}xC zYydg9k)`Bl~3kgRJM z!kae%T+8ISqJc@^QLG*YwYVWxB;qM^774!GE@LZ<+scCJCa-*53zrDqlmU)=RORUMAnexunsXe(jlN?OkB^D(j9PF@T!n9E|L^(aFRk=e` zB(U<9yki-N**qzkJ_ET+Q{LH{+Ll|-gtIL*E_Z4Q2fJ|NOy^!r;UL8c$MOJEdWmtl z1&!}u3NJA(5apl?5r-ywHep;HOWmJwf9t!UmtxqFAJpEpyLSv7nXYj0BFD=1gqZ!d zmK<~39(`AH)3~sKJ;4h8icpWSP>LSy%H@l{7pUGBRWOyFv|Iwwyu!FHwtdBHU)hqD zOCb6Vu6a$~G22&Q>4ampuVCk4!ZF)d@LAY|W45ncot8@=qQMrcF@3oNq8zI;1CCW7 zTddX$IF<)ntlkVbuHrROmIy+kWtUyG`9WA|9Aj)a!x9+eE+|kl=1)}dDyJF++ungSM(t8D>@3iz^ zcUT7QXz9TMvA%tLw~J;`d)NKt9|q-rbbJc4F>Xjfi*X`37#ljshCi60c0Dy65790b z2yJtJn-TutM^VHL=dE>2oLG;6qw4HjHXIHhXBTvmWucC{*w@Js$CD+S)i<&;VLU9_ z;HkQMN?t3w*90(*ymYF22^@WAU{vN4)=Uj+Xr%eZ#O?tqcZS1B`#A}no6{VDv{XbC zKkMgM9vwhVo|bd|>7SLQh~tS`=YIVAo+oPOmWv&pr$xfKBws3%nEPGKSI)BFzzbc>e2_OD`(j#FIr@&p{J1w(m0>aC%jlAe zk9RoftZVC!F*DMSZ#%AKS!%FAqAcOd2*?yITe5kLWupX9#1x>pOb<&gWJ-~Ypelnk zRuk#)A_nH6R7_-*7lA&4<}zDMW_2VZXfCtWWKM}>1kGi(nM^s75j2T+Q>|!@jvJPBRgtHgU-J`W>}XH_&`@p4IXW(n8p2md0zWr|7flU~4(^P;(UfD# z-8spL*d4vcZtD{3h9uW6EvG2H{&a*mIZ-4wARyY#@tC%tJ`PMC=UO)nd@3#wA|cFy1Wyg*b2`d2wlc5$s586HlfQk zqT!k+Y3!-R-(Xo;XnbpAAX?)Di3>;TVOb+-&7Yr1XL8Z}AwQ^kyTsmGiV`aaXmp+) zp5D*XTfv@T2e~}vx3;u^26;TnFxo}?haF+G)qy;Z`})HOL6wIFhQcf(iAl`9FvCce zN3lUCSQ93R+id&7{33}9e!_ytueeQNSB@_(pm1hlDqIH^vWh|(EdP>(9uwi23X+yL z!9fbm8^}g3O;T3s!$K@uzNJLrs9bnlfrUyS+LhVWE`ztM3Nv`3ZkOtn%Apyc&uB`584t5ZFXn;*vy&A63eMMve@)e^k>Q0d*Xl#N z$HqeA8&dA;i%!v?#L;+lEb|2wx`WDf=^gmeC$yLYbK@SS&YUcV^_jWt%(42E&>R%6 zXOHg0%j3N@=~hasVl;7771CXJ5&hC=;)slR$8=e7(!~46u9yCW?u&MSaYp!x9$Zn* zh`ytX&bl3%46c0Q7n^taf}X52TH;n+^(ZCqI%tuf5_vrfLV3`{;T8<%v>BE~qlvRZ zB4bU7KH&i0U-d^qu!aUU9R%WM{Dp->+HX#J#1q^~Cwg~~9vYgIRq@MS%bL^y%0VrH zfG$7I21PgkvaVMkFE?L-&uOoS3t+MV ztn4ss00Sl)z)p487Qtlu>Kcb(3n%1ckM0=`!|qLBdeX&V*tiJ{+cwdOcNq3;0+Zdj z=Qs@8HG%2g+;bhst+_-cDd**=rbYMVUXY`j8Y~GQsta>e)1!NGFV0a-k?zR7Bu6z( z+>hI_;j$dnRBD)Z=qh)5fj0*j|{Unl|pc?by(jqnb8uy6xD|lcSn8?zrvPuq8(|ZQO3#v0+<| zYTCHhwqwJN9M!aOqix5AYjRZ6#$C1@8=mY??y*JMxW%?(!&7n;^DA9XMB&~14Qwo5 z%e~k*2B&wVLoRzf?_XAuD2KItzhn6AiVM(L9T0T&w_i^b1Q4k;%HQIiRT2ohzprk) zR<7ve4u1xe9p&bFp@@lcrL~43-%%NeT*p&CPdQS=L~hkziyW!W`b579uKt;A@J=NK z712{}+-fLfYbIL0a0@`8h>2k5lPZcqZp!3Ny=MZLP{c&;w2zM~#<*+48uyyTYXK@L zsED5ae))1dgdkhBFwgkIwGb7Gm zV`v}sG}*Jh*b7uiK}GiL5BD1iS!5I6KW9`o!@Ks2>@V3}?@sy~A2t-S3_*@4oxkM?76QI2OLT}DT=0|4h7M^6BD?;DqZR^W z8Lr4)c=&olAm`P)&{v{%tt#UM)CxeZfiAqb;=`>|1)UTe?0s;9$~x?x6?c7G(LR_%{IJ}k6! z3c`T~!$5bozi;gN>~#Ne1qI5riC!{J^Fu{L!098WGvo+@u5mv#ON^L0PY%r<>|EhgVrKp7;1rx@WtoT1!{MROuG<$6tJv++Qq;EF_xFKv7`i#t z^bk2`MuIsG51NueNiijHmK$o?=bm+(=O8<+ZXbSDo`#4F?;pWya@R*tlmbw84&(S| zFq(2unOloTckUj?mZjCc90sUt@f{4i*mBZc&&M;3K`)yeLgj(p$zHv|!-tt;s&91k zR+I&@j;Uyy?JuOGTbUT29M|slb-4Rv5?e#)GqPDxNkOId)*Y5aS(V4>ah!e zWFYm}1waZKy8!OV5;S%J+><3}>;iSoEL@BQhtmzkj7GBx7h?g{y~IQ{qi``6P+hGc zs@a5#v4HAMVxpQ!xF`##UK>MHvxxU%0oMCr2%8J=qAcLK3y{`S$1cE&vlNeAfcIo6 zE{W88TqJx;W#R(7I7{Vq*yBvYd$JVQfse;6t%(cpo-CEu!H<`>^d>IAd$L46aRJ_w zrFiTDyeCU>Nw1!2fcIpnybgxEyrnmB0bZP?@;V^$ z@|NDj1$a-E$R{o!_hfagUI!QWxAWlwyz|E2m_sVQFvpN~_vKhH?YbnL7v#;4f1{4o zN2OR2vz?SNI_o+KYV&X4&sucvT`vJsI<<+g2crNk{JDN=BJ6i6P#&s7JUB!pG*Ac! zGu%R#F<~kDLW4zcK>O(P@j^2-(bwaJM(1rDYY)K;uL9*M!Gr#X0{r~f7*8yPs}%-mr#_kJL%)M| zX=nF$26hi`B*+aq((P^=h|C(m*7XBB?b*9GIbLsn;{7N`huQ;jFVfyl6Wuz@QwqUi zf(K2Dpww6gG#6>q^`fuS{4l45C!wIT9Iu41_Z+FzE>~CaJ_b#S9p`YV*ge6UQv4Qw zq4Ak`pn+aOTZ&5Qd^!#!?F^@Ng5>Rh(*?UqSEQGH@3@I3M^G$?~qz ziEvGXWO-L#bX<#Mc~|d5=szUOqr<%z4+On>1L}Lh4Z8C}V=Pw-JMkpT^$B*!1K&{q z_jMs>0@o3`yo*z}fL-ZSdYzrjY3m`gJd|U$l(S{FD51F%4Av~WCi(}%ijHJ?7Y-x@ zwH(Rvu7T*_W}wvI}KuD9kUR%R{5pp|Io$UG5)%Y*6-u#t0c`P*)0#A~`k` zmOr6^M#nfwA};(5a#HB>?uo%Yn34!uQbVjN1IIa`ItvR951O^jigS4=&9b7+am|(d zZ(=0!KavkI|0{Bq^U}+MOynJ>x<JY3>h8RF0vDM{Y>6{NEru3v55w&tsNW zCiP^d%h8Gc`o!LBwf};g0+N?OtEG9_&m-YMqctG_WXHyPF~RL?YD2)Oj|}V$djJku zXD3A4y3@OO@>5mk9JYNg2v=kF55`{%Qb6$NA_U^t(aE3au($$(V?V6doj7)L@+Ueh zu7KdtRqn*GlaoKu{nQEw9$n{79J@IAgV9(VFE+sv$FAQP2S6Od?V#y1L^;t-)xxnf zW5^xYQ8?JeD!gA zFv7mnlmG-zP1&c3>Pt-tK;%_oS zYRWzsS2?LE`*@~I-bqc_2jeOyHDw=WRFspNvd>J}hdGqkl!AyU``ViFYA(8YQ|1*k z)QmsaqX1QjKiQ*z;HfG3)gH1_Q}Vk##8Xr9%RR(XQ}WwA#8Xr9>pjF%Q}X*g#8Xr9 z3qHhCQxYKF;*~^{lbVtr_EAo1O8JtHgqE68zU3pF)RgiyAK|2?ly5qVDcf&lTK(9_ zl=eAssbH~1DCp`UChi&HPwJHb1W!#lpr#y1O$k8cQ&Zv&Siw_M;@VfiQ&Zv|Siw_M z;_6qyQ&SG8DF;$h5|DJIUO8Z<9Dw115r)WGnp-N^0rScM_+Zdj$~%^BPW4CC=zw|U zK#NxjBBs%&F(nawCpG1u znR2kjl!AyU+pn>`n!5_TDTji#68Db9UI~Dz45g+7Ab4uZAvNVtYDxeipPF(=O*xdB z5`f63rW{gJ4yC39Ao8gxht!lqsVNCax>8dPnJI@_Oi4uFNliIqrW|T9B@ulmHRX_* za;U|Wf`}=H+P0NVZtw7>%rEdk(uPx00-!3xsVM;no|N&=Fu)ResyMj)Aco!rep;f-S$jI^P1nvRK zPWLl_Iabz`;JAO9I2K7s9M(0{#E~~K(p!%WB^{HjAL(FFlwwQ~(>+?Sl~E(B5IPAE_G7xpL=d7Av@Ny+VG$1pBUbsGHl$p8>TV>gA-Q zyolhQ`X~#9){{3u7V62Hsln>RWORDRkn)tvupkq24C{Z)vtZ&{f$}ip4k{m^G1Uw- z$U~v!yCvZ)h+N~S=R|@z5IrX%+1t90P4=?3b)}bZgR9G^(SE-UT%Q>2$9?YMN|%GM zdNVrKhuwzWeGRc$;-Kc$ii5_-Bv~(Sgb%YIgc)jmuih6QE~E$Xy<_Z@3<`+Q9L0BF@M)OnYz_`v=CB;b#ATRr7oRWnJdbIplZYmdlho}y`+Ndwn}nS@n+*WJ{* zCRm!c%15fnz_GO2lqxl-skDmaEB0AGf20v@I&s_t67MSD)gaKCDzvlg?2|&JgOxzl zv9)K_w|j_9cw=a+cR1|IMtB*uhDrqON{+dzMJ0kd)oK>S@3&Shva)x{lf$GjC-^ZT z&`6);&fGu2*7~4zh|M&KoiDi^wS7@n;OsXurQc`t}C6eKiSP511M4_t!^X z+W@zQwtF{2*YjmL!gy;_$W-$5j9HG5H|cnK&MZgBLwA#J>34^WChpFHt=UGSJ3u+L zDZX<0*(}4t0ic|I3G9r|Tc)s*%_KdtN$wHbr|^cBLdv7eF`%{IvM5MrUH^)l+k6b? zM%MB)N#1cpYco8sC#>TQDG%+%cVvP^U8UFQ+wIEqb9q3;np2)-aeg?2E#TqWnb6oo zHCzqXT!fZhAr|0$oeItB=y5WoVGSa5d6*rqu<|fK6z*y3g#YLjp5hIaPGLTWdy<4M z_x0a^54-tptkBjh#-BJsHK5_O%dt1{ppWJlPm|=Uc0xoWWkaxe24c}z*%0MKqh;Zs zu9DwqyljYaq7k!jFl3hBXv}Pga-vbQa4>9^-)P)yh;pKlvv4qUmfvXX>=60ISUFhA zbCA9jkDrx?0kl3uBWMR1FPd*w9tP3+5RIZ8WV~qkKzUr%lc%<2ZR2&3sq? z86uI!3wy$`Bw{5m=wb@TOdT)o3CEI$)x4nD6ONfWUf>fB=11hW#nfEm6Hbe%xymP; z7E^PbPdF{6=1QM%T1_o$eaefL6&z&mwU}Dg`&6jK)Ux8IycSc-nxFDoOs%Va!fb2m zwSAGP^Ho2-9WVPCA_<8X{)A(u#!6peYOei>M2lB*^-nl0rsn#ea9X^YD}cgjF*Vl! zh0|hct^x|D#nfB}6i$n&xe_RxR#VGbpz>NwEvtdbYcaK~2P&_{)UqO|ycSc-nxOJp zOs%Ve!fb2mAM#A3ufX$FLB1U?3mPIB5HAc0$4rftz{J#C8x)BaQ*(7tI4!2;`k-)H zOwAQS;k1~VYlOmSF*R2Sh0|hct`iEU#nfCW6i%zDWvx(oEvDxBp}p5)YFRJT_gYNN zHAH)_#niH9sPDCyT2~E)+1Auw<55*_>U`CZZ^z4qhKNG(!l7_1iC8I2OwF}Jk!UeB zR}Y2LVrs4*3a7=?TtO60i>bMWD4Z5ka}`lIEvDu=qHtPF&6Pyqw3=Gh5|!6tYFSNG zUW=(^JyCfrrj`{&<+Yev))bZ3VrpGg6lPmf-^=sI-qiW3BHxae6%COLh!+-xW2VMR zVq$8pEs8{oskyo+oEB4aeNi|qrsfKxa9T{wHAdmIn3}7M!f7!z*BOP=Vrs553a8c7 zveu})7E{Y=qw-ozE$fZSYcaK~I4ZBj)UxKNycSdIs-rO5n)>&7P~4k3Uv=c$@v@^K zk^%9;qj1dBSZPd5&9z67XfZWcABEFmYOX&Dr^VDVnp)N(mDgfwS&dX)i>YNjQh6<=mK90mwU}DgB$d}vC0+cxqd&N)k^k z%T-C@sa**WZ?USZN(v{nsjNy0C$*@oN(v{nr>sf}C$*-mN(v{nrLIbXRcpU0`Ep*v z;7sY~HSTNfY^rrt(m~~^)>TOdxtTCO8Nmp+zQF4{+LpH)c`HP&WIh`*)w(L_ASe^B zN(v2wwXRC$SXomNtx7t`5*MvXYT{U2TUI3h zyBfmj9k~G@s3RRj-ZlG5TMs816cB0Lr5EgIBLj$pkJ;Y%*bIGraw={!%es8^Ex0E>$1M9`ig0mB3O-eB zzpz%XMP)-a|J1WfI++)vJJGH(;J?@lp&aoOyB*iNsZAUgHol(J4&T6$UgPO`?U09K zy=renbJlJb8V(t|oM!yzUP>i%#80j2`D_M& zQ~d6BeH32~2j@cJcu3xn^U4?HQ@1#-3<0h);e|)-*uw~v&bodK?KW?j#MCWStnJn> z+HfYFbhk~Vf5fGMfN*-0Q_496gi}#YN6sN2oGr>(m2(IPXRC5n=NtmU*`}ORat;CE zY*$V>=Mdj9{IhT-!;SQ9d|#vS1f?14e(H5ZX6w|k#z;HjKuGid-(Ty9P8aZFwVy@eS}&a zcUSk|fK+#BvbRQU_VnW3vhLDUFK$2UE9AWy|pd)d1h~ID}J8UTib@8X~^(* zUvF(Yer7=OcQ<|+&|ds9q#N+dpq`FjhV=~mGOz}I5n9LHSJk>kpg_mnkH-UlpIGZw zpbHNKDzzR3w%~!l_F6@O9e5z{q}mn*o{R?q*VeWwa2*~9^w+j2Fn|XF!?o=SjNpO5 zC~peJ?^AIb8-5;BpBxhUv3P*Kw+>D09_f7=SvzqRCkoqSZ$0)g zxm%lymre9vc4XV;p3U1Y>z`jZwm5s!&C8cPc4pIM-B(||?Fk5T%Vm?zqti>5jm|AC zFCISBoLlDe%>3fQ{NnU7&Lx%}#AWv3g8H9RP&bXv%`RKH%%1ZyK0d{XH|gz3*UibZ)u1xOjMBc}YV3D+#%UwL(aJD+Rw3!GBJI&&Hmx zf^*gPPAtyOFU~H{9&hd+Xdak8d~kVmX%WtLOXtJR_8)2>9(K0>9A~?fV}eQpcN%AJ zenFPK3;*G2IhK3EeHZ2RXB80ISSlTtsJ2K{jOKlLREiY{WmA!;wlFGQ#y2)TERivy zk4j`AS|GZsi$piT=xUSvuJNQq$EZFh(S>M%=the~H_7O*1Ifk4n7$^l1z>^5riw(i zkC9>UA?ac)-;tOcQXrZGMWR_?G^1lY`G| zWi*e;qblsoZz>Yi+g(&!B?B2vPac(G1yc1}MWXsW7u7b2iqZU39+hGRqWb+JQGL)w zwOyiOG$VObiWP|J&x%C#aTnDNiHgzG^QaUn5Y;D&MD+z1)zuOeqj_c?m0|^=`cjdo z{+ElYyG!C?JhORR1{R3y?}|kB&xq_%Qa5OY!HAZ9WC|9D?E6I`!`wyb_{9>N)(?#7 zE+1RrN@G>2NOYJ^FCE`lAKcaL8WhI$28l033ncHnLJ?kt2#-FY<9T;YHV-XK;5H?U z`p=hNrYKk-nr0zoju%pb~h%U<}5~qepZx9 zIRzB^i$ebO^}>qv1d36qx8#b2oC1pdT_MGOQdqG{pcs|*7fWpw;RTdBXH}8f z{V|1=@?J)To{}r&@d8RczK~MAg_ZJNMui%=QXVg$)KDR%o?cif?`2fzWUiFQ3n=xh zLP{Mjtd#dMD)g(lQXVg$)bT<}y{xcO-pi=aALmMWyns@#ETq(1iz$U$U%mHHp|7e^ z5ne#4-zlWjM+z(Dy^IQ#Um{fkl=651r9M_jsjn4M3THKI9Od=OD31y~MwE*20!n?m zkW#C#d98iriO46tQdH=vPN@Jdpwy|Wi&UN$7gDOq%SQSno2bpLqEP@AQ0MYO>TD~f z4l_vAp(-y{bv#%=ohKDiXQG%o%pEO6RORhHcN8q3&fY@m94w}eFFsV|UY|RK)p>Ry zb)H{HodIM{{|IU%4B4s6cSWBNEs#HV7gFfgAAmxrb)XQHIp?LUiBus)3n=uPg%o=4 z15gO6@`>}OJQZSZ$w32mMc@Zzx0km%6y=(GTJYqBKPFV6z(g1sE{&W zD6EX`385mN$dxI)Pvk3wl=*%kWybalNoRy={FA8SkOGDG$AuI*8;9@O*Un?RRS_z2 z{>xe0IHZ6g=XDmTk*_ME$i>*hfc^E@O}1xnKs32rw29yXDpd-pv>hrPzZjKBW9RrJ zHi-;~F&N`j5^KsS5b@Q8BK|3fm`7hEM#i>PV$7ieQC(Xos(wb5y=kSx3ehH1Z2jJY za|+l@{h_n}U)W6j_)}J8@5?e%ds26!&o1LM(u;A_rv>i1{R*r^{P;zs>@+!7`0&Ap zhx`ehE9{5^i?x)G?DpTwvR}mik~{t2Su6XScZ%_Q8 zI=&l+YA@oBG*82Ie+Ypw+=PrH+R8NotRI6l60(eV*kd2^9xF$cthi^p|37Sa#ea2H zhk8HFz2Y%}XXap~bfTv*FuTNdVPO6y39W<)UY>e86vZMuMO+M~OB9a0Pu9SJLN>RVOO9X^??d4DO@^8GtJU`P`L) zd;yM2-K9agWHGECN_Y-gA+VRN6xiRDj;=0E9GO0-x9jp@b!pfB*&|C$gX|f#*PW3V zYq^!>j_*Mz;`@Av%<+CI354e+k2Vf34KxoNNvN!edKMl!HVn^ zQu~9IQd>ixhJXOwPpjq}kvysYxq+8o}yQm=Jtc5e9qx~U&Sk{>=` z`yV(I{_vT<|C}>_(rQVm%s%iNS@x{Az-6U+QYX{1p>IXJQAo-;PVjZpPrkXJ=7dOye!G({VgBkK&BPP3tzws zw@q`rEi&?WcBzajHr#dDf6I4;ChD%rb||jt1M04Cb11IE0_rYrb13d}0_v`Ab0}_Z z1L`hrb13d@1M04Ab0}_Y1L`hqb13d?1M049b0}_X1L`hpb0}z_y>>a3Lwg17vzw_L z+9zngU8?R-e1sk$4A`CO4#h24KnF2xfg4dWhvG}nK!@NkAqpB<{OrTi`x{;M{TF$` z5ar;TPjVZU=OC*^q9cs zfwE`)ie0+WiC6^rz-xez=tR(hYm7@64~@GNJFT!DT}C0zd7%Ps!h(oXcm1(6Oq6KkGaALoDe-m|tAhLMKlc^$awR>^yu(F?(j;JP`zRVr9vv z4nl$Y&C~nmZ_DmRX>9~F-WnlUYu>b!eFTM8m_mUyL>8<0=2G@2j%hU51HvAk92fa7 z=K>CaNZ;&!9dhBfaw^lGZNkcHW2rf}U-ILqv7iRXkJi}oj&hDMKZ`PgD z$Q`K|`2gADtQG%-A@Bjf155PM01fahzAsOeKbF*NgdwLJH#14i#q6cOlV$&k|D{F* zTe@(B)t)Xy%JxzJL(@yQYOd=O#`a8_RKb?UJA#v>>B-WbJnQadtd$?|Z>BmeHkX>q z4crbR8f|@du9at)HW%l5ZH8X$)~YI77?eb^FHbmw?{iUj*dpjEoo!E}h~RjoHweLN z!}rI17@lG8UZ023kWh9?C|M;KqaK(&i2HCF`=*zB(5-#>c@LIu?ZXY4vd!`rr55tEgsDNhW zk;{U(BjBwdd;FM&a4f4lj+$Xh%W6Liob8!`yL|d#cfkd7Z7%YAc+TcOan1(&V`VPo zGryf>KgNIUDmqk4!P10c%H!atvuu6=!`9AsKz%-8h&&vrP70@ed z1y-QEck!5gmOxOFWz4tOUE6|@ERP>SZ%#iEr6B3@$gu_d=%*0{R-oKJKexQtZQpMd zh9SzqmE?XJK{y!q*O%uP>_fKlhR|gi7%F*j1JD`DR>=*rB22P8HoZJ^b2yu!Kza10 zx%tI#K0|?W-?4@1B^0N8M#F%!%bha^Z8Fkjt3*hsPK?|3QEasgC4|b(9iNySM~4`fvv&N#+i{EQ86Drp&-zk0SF!7D)-%uN zAtY3throwm$7@-~*|7U*=k35>TnQ_)3wT=H!S)V;J>1E9$ak_f4RFK4A$0s-DFX!| zXMJ^bRyiOZwTe~rtk%Y}m|)vw11lLi-jy?0A?KXRD`Zr$0Y^+Ej^84w^*N9r^h-|( zhz(K!havjlEANmHH}#Dn00#G7(hVVlAg%~i-*kWB{h@^S*qMdHjb%(1FLpO(mlm;& z4Oa%BrKNUJulOXOpa7<#A(o2F@Me%woUHQ;FkY zV-L|2Kxa5d-&mAdODhi#Y^-pUeJ4hssE+8g9E{=-;BkpY`l<2+=;*Bn4rm{h4*-tL zu_}?(Yk2~6IM3mpa0|d6a$%#Vu{?j%O$VFUyvRGVKd%^vzzTdx0Vy$$`AvC2o`>xj z#;MEWP+eD{zZ6mDFjw(i2O9Azea;7{OIbIO$|V10o5U#EKcT6=A?6OiAm?8Y8vT`} zJKUo8NBK@q18v2D*_-+o4s%&xG5ajh%GdcfyUM4GW9Db#Kc<*mV$n>=mWs_cXKT(4 zh%>G_QF(^GALSNbr&q;!7`%8^7|J;a<)DO;EeC_|gY!4x{l=l@A#@x*xBfxYarhS2 zO6KMpx3QyV-kg)@SNuKMO|F%g_1!4Y0RWM2Bb+g8btyds zTLl_?0{AZg4?r%{rc@uZ??^Lx!B76-;a2ORe^dFUnS^jWdLKXCch?V1&vFrW(}fQrkNYA@{jJltV$n%vOy%+H z4z8(nwJc9|$y!@ix4zsEKIyDk4cuKC|>`R{Sf z|8C2Fk8A#STmE}o^S|5j-{YG9-Io6z*Zl9c{P(!#f4Ako$2I@EE&n~P`QL5%?{Url zZp(ja2OO9~INNlUI^e({!r88?)By(wz50Q# zQtLYy7@vxGy#kb$&tolSE`e{5GtJF`jGx00@bEXeza_4o%0#cMfBT{0L+^PSb_% zQ?Xdi&hYu`Pkp#~|8LN|vjNV&^d?;OgC*}$Lr80sFD~1|yE>0!$n@7}7H6jC7UpkT zYU;SuQ9982it=StrE87g3#CJ@uNl9I-5Jubk`01Gty5NglibUi3pl5+!ohEhLyuXa(U<4wYeD#wm+22HvKe_R@iqB&AT;ursTyuN& zEk!UMIlRy~*xbL=I5<1k%)YJg!t~*#Cbk@BKT-N73|p%6`HRa=PX(c2d4FjhT3u^cJ{{ewK%VF!rN`#6i3l5-XZK-XH=9a*K`@)BlyjD?~3yV#M@yU@skML_bSOm|WsSpc8cECR$L~^q^r56v+Wk>W; z;1l}1&}`nCJ>Q<^Z*68T)#t+tBJ~SOHIFW1BgMYi`K9c2iYy;EIK6ap_GYDQKVZMA zgJQMs@KPmv$9*%mW$z&qLuj7uv7Wxx ze5y`O#TW*i&w(IE@ALa@Zbs!I2x33&#rDBNF$XL&T_&aw#GdQL_D|2mLIfc4JczLP zVo|{f*grsBHKI@c96jW-%}pkWT<#-~#GyY+Y(1ESUh3und9F3!Tu` zLy3$65P5Mfl1h+FCa7ovd?7M{@FPf#l?)m(-8O!LO@M}&qT`0@(B1kytjO4 z!NKwf_@u%((RB?&0(?DFI>lI;2O2}8W0QlmzTU~K1XU4JghB9q5Y#p4tn@ji#t5?h z%F=4tbtNN^#2RpKM+XC4|Cp?cQ+=nM_cf3m7w9bg`JAPf`TAAp8gX%r`v_@SECujq zJwE()ojzTfb?nfmi^!F^eQ>+<>HLQ~R1f_Q)rQ$aY#L{>OHN`(5dP~%3Wxg2`3ar= zc}wXCw@l1V>m)LMK|XPIpOO36-8m6(+53sP$8lKAr11d$(b*;UIv#o&OV36pW03mv zxJlycNmX|8Z^I*Db~+<3T(AE2v;6ZbPb(cjckaD#e(|pRnqQZ> z`9I2~w7w2z;RVo+<9EE2e5Foz#%bvL1koE&s9;8 z@$|;6l=)sRGktJ+@lYrvz{YKq`X@+Xly+<5;51HMNkBQdaXTgc84@?6;}=NeMRt^?^q`L!TKtYq`N+?{!lZl&NZhTO7J z@FGPUoO7I6IM%?5%D+7af|UyxVI~K&(XF#CBei(F*CfZiDrc1fT^?gc<#Ju^k8EmR`amC&-Mk&6E;j~ z`*Q}{BYng=UvvLWHoTIj)um@HEE>QE=!*(gnX|K|^s|%6v+;gn2n!LbX+zpz(EBCQnEf9g9sceyMIEKy_n@+d=E}!AXh53U#T`4Nh5SCySo$e0Ij<|0_`mBVhO(I20Dj7s7g|g1(O`2!-Ov{K4hyhcucI8!@#C_K(2E z2yRJveA?J8Rrf9IuTAF+JZ;2mE8dtR17ki33=bPI*$Q}326YckNE9=V?2wdSig1G+AnxByuT-WRhCH?!|0yyd3h?*11 znv3HRYYPj9_t%<`E|i;M=Fcb@)V1#=Qu$;4&930?dHB6n?ksd4{8`}gd8Qopx8><$lKC~vQX@ots`rGczWYCzYKcM8<3#W%OOmch`Gfe+@*@I|?Df>KTm}Jr{D}CWF(Ucj1DS+pIwb)!Zcq}V@ zgB*S4+yEFdnV6NnPli5&@oF&U4=>A9Vd=YMISS0zfXQvHz32+g--J`OQb&adgkBp7 z;bd(hBxh@12O-wd>}bJq9d3mJ72^%wPdYNIr0%oh*~c97Oh7hTGHN5&*d9 zb-hu6MES2M8ZI+@gHYwi{EIt%g7pWg`ovcNj#eeSy1yEzd(R5$?w>uN>hd8}?NSEn z_1Dc`k0V&w%)i-{l0R+@hB_R174?W=CR2_yFL}DDwc^ z5q8jSmsK#S!sH43dFvV%d(% zPuw~#2MMm#oRE7W{9Qi-ipHWND~eWE65X|;=pIFV33>WT@7})RyC+u?ecp<=Fpe?>zwPD6aMKy?ZsfvLyFjcge>pWj z-G_Va&{TRf);EMQIRCYETA-Rz;~Hvqltr30 zwr_Gny-Ngcckdl;+Z)1t;W@H3GgMiH`v+!)$B<>g6#DHx19GJCD|*a;91Ngoo0pjx zQ2UQ$fMK7!(;3$=X(u(BuC@AtGQzM`TUIG8TP`iLPK@(9`0n#St#x1Ozfli=Ax1#Z zsn_eEnIv=KLZjNM9jvu@0=PG6Qji zz$H4cYNZ*7D+HDy&>22y-tGi@*AQ3+0cZ7rkNVbnDFT8j5LDdR-Wo2H!^>*Q)BrFC zDd!r$epBfGLPwk0V(HxbZ^Yoox2a`yA){^%i8n4zh?=)So!>=k1EuTJN$?g@WX&W^ zju(<@TKlEcJD{Pn%1mG{5)l4PaMYTP_V!I3m`~jGmh3*ND_R96yOkIik!uV|%nH6i z`my2v0IzwetjfyE#?!%`Y5zuTi}f6a2yiR1eEo_rJ|a(1F}q%nFy0H)a1GUU3)z5X z6t@%0w{11#oeShp5n{B}Z;ym(8|yHZ{S7=Phm7m5-}L)m|EAxJ$|^j;tWx`%U^0p3 z(ElXo(W3%%MMxc_&$4{JI@F@wz3!W$miws{ckt5&>;-4NO!{S~#Yp%y0)u~~UkjuP zOj1Os;7)|VbylH-zE_>YpBLi(dgO(!szPrpPeKUD4I6cM_BLO_ZIXi|$@Qmg(^ zQca{^k}?u*B`|nC{i>WY!iW&P<*#ze2+*X~xTH@0M@ijF`lCrbKw$7C`n6`FfiX&! zdYhkKp*Weirqmd(&wdx!jtR`}d(%C2vMXy|Ko2)(KN(4|-Yv9_>Ke!fSfa4!9*|SNu z*oMu~%%>5H;OX>hO~n*7mhj>MhMIe#t#j@`X)oa)MG`^&HnS{Cwei9rndM?!;tr(bK5 zq=$zmB3t(@K(ZU6QB8N5Pw3MoxtO3kKcy8A1sI~*NVi#e1_O}Ms*@p4dVE~m85I-W zygfSVw&*7#*O})Lac!se@RbAxYw1^-Ss))0$;PV)({?IYTX%|Q=$Sn}^!<+-8g0gz z(u{9OGo~tMqVlc6O6EFg$-NXrbq((4g=mA$^&IWeUJR;ello+L&^hh7th$rkUR7IP z5bkicrPCMg#M&*=ihGn5F{|v!gr7(=VuG|CS9*3_iz-Od=x*1IrrDyqZxW*$^bv>! zA6L9o8z5Kt6Prt~qKq{_&E+PK%O6y2poQtqq7vCC8P~*=@)rArA$PnCcCNwD5RQ&a zje75~Dc|Kjfh$*|*69nx>+Ghr(7xq15JhC7T&Wh@HlD1)q8+QrgmqopMPTp}`o++T z>x!}wqHKJTLJS|30XjQB_p)=8oEGlBajC%kt$IkJ6Rb1AR78FIHdXM>IcjDbZFwRq zw>(2m^mOxN`Y5NnQ3!ZPtj12A&n(k}KUem5*XyGUctd7FccD5b#@OzCCdDQv?=B~L zuqgPtO1&Lh2-8E6>}*n!Z^>jCtkaw5r8mD`5HNW@x*5c@-7ixjd0p?!V7k<@LahDp|!R8 zH3T}t4mWie)1%H8z0W7_f*J@kwMsPzuw@hATnC5@4R?9F*|>-`tg1M(B2<)Lop0Hl zpx18%ksO>HXl&c4Q+b7GJJ*5QHmOI>_=e~rAm5NdqH(8_n!U-{G*Skn7G$KOo{i-i{z?X?4XJbr{qw%Iz{tGGoG>{ z(FvM-x|u5xd4{HNcT6;D$yq$vhQ~yd-AkDo^)qn~Y^kq8WyH$Hh;;{1ccGPXM~{~n zCdFPQDEK@2rBBEhQ`lsC?)9eq)OJ{&$qNnhBmZvZ|CO0aGrZO$GRDmjY5i1!f;sf- zEMa%DKw7?DS})&;)Uap$M#K6J-_Gn~Nf_!$TyI3vW-TOCFZ5g{FQPZASwmJKIK3gNn@DcI9~t3mktvLK?=qI2im>CC%cH|bMp zbt4&knbDGdO^n_)SxM9*b-O|8&i@fozmcT8*LpH(qb=){do1fa_-DM)qXIl?_YCsR z5Bq!@vM(ihU+`A?V@)$%Uf$%%Oq!*%Hduoq3ug=h!dX4-f z;MBhM9+1+_QgL*M)_Ihxy#P0Z zla(5GzW|DRnvCy4I%1IoiG5{V2f@RGs%QM%^tEw#gANvr{#853tf_96d zowTXV_2Ii@F6gT+omf_1(;CJGu2~x>G&6(|WNgo-cHdA)q!Yst&2)|_5u>#s9F5Jx zu*?2u8-@qeKfi$oxezjw1{|6&ywgGtrt(2928Q?-TD-0u?+q&94SpLcNQVdF8IJ~6 z@Qk+(pC(UNyw|dxz&~F|UOK*=7Vn&tn^i>)&bEi!vH6NK4kyp&`c||l z^q7rsP3JuOZqn+@{txx%$MR2RC|pC|Yk8Eefreo>+M!d_1x3Q$-yaH5)grWkpmU*te zOr{T=bE!Z&p*)-GAU}f_D&@h~qSJKz_(kB9GPt{RoFJWUmYZ&Fbh?hDOxZa{+Rm9w z-8m1wEYr72jmqubmQlfX|0^o^;J5%dU_jXYxEWm$wuLbJ!9--Ayt0PnSC&*+_EsSC z#@>eCej{#|zcl@WH+JsD#b~<4(#hAi*#Gsn*vUqxl0IBd_c%2_Z3LJOULwq^lUPMU zm62Zd1bj#N+g#szAo!Fnyo(Te;YM~~Z=-aA2k6(b?lZdO8``i#&=#j-{w!+KKfC`r zQ7>xmz!MWaHBrA@W2U*mHz^PwNj2El8|1gm`xlUR_5&D;jGaT73+@iYsLz%eKhb$N znIw<(q-kR{CVh;Qwu)h_4P&uOW>SM;=&$}2hB{x*rh%$^=m7|ZIuN6Nw|qF7h#<0x zBp>snV+?&%NiTOak?7NoxW<_FpL+77i)3j7WFkZIG5VjE^41RH=HYH&f}6+5>HmV> zVZRY{8%V!vkZp~<4?pRLa5?tJI2$I{FSJ{7+A#eY5_pva=vIOKuW1>)EJPr;PKpbUc9~H?85^$o}Of0Ei`M)F7)x*n=Kg~e=)4Sfwrh5m%|PvIKwDU zlSQr;!rCogHDn&73;dny$UZ^WQg*JdvdMZ=%ht3)=zY4P6G*p8A%)1(;9Av=y@E!} zX~z<2%PUZR>|asy(oe(AaAVVkeO-_K4?JN_mYb{5*7$U9_EFKR{ni{0%t&xfR+;r> zCvExGX-R4Nsta8N;V>b2F|RY-2}-wuW0Z5B<2iSK>=)2PAG!KxccCz*@b_2cu4PTl zPH$3D`FFlwEUBm}US3pg;R|_Re**8n=M#8Vlh-rOm1DUW@Q$?7)@T^ru3lOd%uFxL zOixe8NO#lbNbAIk!iigQ(lXO>Cl)rhY?Hh8O`K6Xb7IE)`8jhl(=)OrR!2I+Z4*nI z+S*$?8nNFJo!2(Ewlue5?__LdelAk{3WpElddrfBSpj^3EMN!xfw+K3h))P4Bqa1p zNK8lyBnSEj1_TBM1_cHOh6IKNh6RQPMg&F%Mg>L(#stPDj0>a$#s?+@CI%)2CI_Yj zQUg;1(*n~2GXk>%a{}`M>49J%E07z=OE@~=n1tgK796n8V7`qmM*MK@cah_?ceW1xQ_iEVkbb($pC~e zG(zdkhzTroEkboB(Kn*ZOwu}Of^r0lRgG9Wk8VBkBL4{Fc9@Df?QMpp`{8Fs-R`aq zYf3v%{*)!InVqZQJ9rCQ9<&oyFHT;nwa^E#$P8D@&WJ(hg(GiL9`3t%hdbP8rnlTn z(=OMf5A{J>yDWV)w8~RJ4de-6t%K=Zl870+#jZuLHkr2MoM;Ajt}`MJzc#Az?PQHF zeR$5Olcm~mXxwbHr*yS8>2Mz=X%~6|F4RXg)1t5S?IW7iI`^npUkbtna3SOs0c2$jQWCPthJ56}Ks6CtB~vU5&qi zll75Hni?&CoXIq91T~#8G{i}de@=P@+I47K(+wVun~7a#?$%ur{9T!N$>;~>9YM>-({;sf7f@Tql@#MK4@#}yTEF@$BJ$R zTaEh>eb>=w98v9-8hP{45hl{P-?EmNiL}_IP@~I@W_gp%;GK(&L`Gh0S&3d~bo;na zXHNVDeYT@yC>`|D?Na>JuAs{l?)P8qj?_htxHF>7rH?1Zx~VR>zxI)*T5eJw*`f=W zR-~@>Y=w#TO60EgN}4~5^MZ?XkBz>#`D3rSaC7}1$f8yLYmU6frg=Sw8-`KsmS~*j z`b@sMd82KvN>IJs)}+;6Y{O3N9pf+Tvl-E%{m<*uku;mv!3LS+rm71k{u_+Fn|n^r zzeLN;?xPU3%RGv^-y|cQluqhhX9J<*RpeC#{<^lK=|MStBM!Csy!euohMg&`B`MpV zLhXG*wyoMX>T%<{-Hf=!{=QN32KQlw&U@PI?F7$Pkc_{aZY?@Pr=w;bVH3XjYRfv_ zWVHQMgV4A>2{%bRMi~TDEYZ@;h zXO6J?z2A4Mz5@x-u@_#w8GrwuU1CW}ja_)e{R?gL%xf%bxtBbZA;t>a9_o5@jL!0c z?Xz^NLE8=e>spPEkKB3Qg7Zx9EO6TeZ|Y-}b{^Ut)To{4E^IN1KMAhhN0X{O<%_=S zkQNeRWmy?!@RnvHly-;7XQ8_dc1=fK&Y`}`c?8m-;~li< z@GqUY_O)eAwk%fTDFEovOR1Nm>%h;CZclfDIik;}L(ANIsa#4rBRfzM!J zIfy)jO^u82O%-tq(tn(>^Lk;g5&rjYv=fr(|9#NBxP^*0FrP1npw>yM? zp-6aCUTv2t*h8iHNy&C{vXl6a5u@WeDYNId!anu->u*fILHLs5?O`zHSv117oSA`P zD-^y$HzR0<6ZkaXA>j+TI881BpPMM`g~ESj;i<58aI%Q| z0F=WbZvBoD;kU;QD6|Iv+_^&p7JdL~re+#)gND~Fs0i=;K!_`aU1%pJU-8_I9m0p~ zanqvV07!m9k~Ju|km!G>NMLm6=@24cS&7TtX!M{5>>8AzU3`cNg8ol_78>OL$vZ+q z>=eEoZVc)kA;uxZ5XJD4;r)NMv+!AP67euWTp{9T?)X6Xy$ICsBf`%q31pi`nc92= z{E`9|?sOCHkGG!+g}q~j`g=(DXX5hI53W4)9Q5y08F1)Xd5$bdcA3#sA@uFFNuQ&R z957kf(+}O%y;jpQ8gWJZJ1BnfsV<*n?@WjfPyivS7UDT5zCtSBam7y1k>%l$p{_oZ zy-CWL)zlwH!21Xg{uu>khEQi5L09_?1CWB3J~!%0kvLPt9TJH%=-2jdn|2dOIQdKW z8C!Pq;L;g}OY5(kw|ag}b3DSAF8tSBCw$MU{G24)tFh36_!G_e^bHO#E{%SJ^QYu@ z7YYA|b~2id;UeyR;hXK23=N+`XfH}SaIqM$Soj+n?1TX#u1xqZ5OEEnU!$FvBu4og z6UBg&g?)w@nTD(o`A%|^CK10xB+f#7k?=i{jFZh`;9}A5DKW^u>tqQu^%OGL-+3~{ zwYQks=@A;*ABT2-nM~lPDuMGv67duR{X4!ZqqS0NG79XLxbe$mCeuw2nKa7CB>BQ~ zFxVN&udDU)ik65Vtx<_0ew6S}*<2;;bRmATS@^Dr$Mmnycf8a$L+PvRR$oyeeWo@o z+|~#w9K!BG4}IQ&0|%6fUBGP1Q8A=D74D8I9x)nq2eB#0;r<&o90wo9H2f|PlZyo zvI3te$2LCL1*p#Xj7({pQ6Xrx2Goy+Pds(Bh@UaVwVswlAY>+*`lpUIa9URYd_FP- zF@zC9bN2{&g7PaWh^DU*B(w4<7Kvtv5%R8##6oCV7a_8p=W%Fq5+P{bkr0bRGhPTe zk7^JPp;;t^ToD^W(>VyaDK>=WOb~J)HiYIu5ORNP2u({Mglbt70~&Wn$P2L{G?tE# zU&V&dFf~Fxhz+3uVTAlCHiU*>5po8#$2<>cv=SkgBP8W*VQ)VA=*^p_PZ6TYD|H&r zg2+KrWEK~p5gCX)<5IIk{bYr;CJOM;*=|zNwks~J zDi$I)dLl7eXf6&S_xB<~Gb#{ysTUC%&4p^*fL{G}HWdf0`?C5bNG7>j6mE=2C^MTAyXLgc5ONQ}|6unr>c z_98;-vmnxyT4=o*L=Hj3|CD!sr}bKZ z?~Q_K1rXo|P55NlyQQ@tKHpbkyX#-G-X*%aDz0XD&o&gsj3qG6qOQs_Ou8R;b)-pB$86l=|_+=)I%!~5pb2`K=(&Q9YW2tb3#eKWq+9}b8X$(I*U`BWlVO)S zCOLmsh?$ilah{v>ak3C+$U?Nbea`A=D~dFPx0%mbvE z<&`_F*a5*w;5TyG+nt@KZr$3sb?dfmTX*bq&lo1+X0DUZT}~0uyb}~$g1m}Pnzof6 zP{odI!grEe?liuMm_O<@rm3M*_~9PJZ>#W4Q%>--^u#gB;K7F9M{2`Oo|&|`18Ggc zAYBoLti*sh!X76E9xLp5DZ-z2+;PX>EbN&w^U66$eM zA?!3ECLqpn#|htYuG7(59-t`46X5@8c;q~8D0C;6ACG}ajAtEp{J8Rz<157Q5a}8Y z3*@h_!c{?QW})J3p^{{G4MfOVG%xz_h2Y)_ST(3Y!&v--w5%x>s~OA<`ckiGV(O3Q20AV zzfMSP?OfX_;yUHH77dX=klx3F;BgQP3;z=skdwdbw{5#kpqpiH{U-afRb9#7pUB@Q z%w*~11!((EdThpctgCL_)~!t46I(l#A_o<5x4UZoB6DGm%FBEsFWql)Z9HKdxQZqn8CJ-b`U%AQH|;+8EaKVI0ntpate6G0&BNPM@iRmP?a_ zoCL7T%8=+%dw3E=_L87C97;=;NibXVw?`$5p-+osI}Yx25k_B`HVfde{ywDz&M1zQ!tRVUENf`P~ zN?uB%*dsBqpeIBG5~t~eG00@3geRJ$GE6%_$+%>D0BJxha3baXlTa#<70)ae1N;j? zp9mpSOA#tZN~vZpL0Q_?MEs&hFvTc*d}16g$eXVNO(%k0O!cAs1lhsh`o6 zI4g6%u!ADuR^d+;gZ7EI=S0GOk&KXA(Nv+HVXmgXm}H~>82`uB$ac)^q<$viKNm@v zqQ8F!PVISvful`@V-4~*+X+63@4rvP-MU}+Pv?J56LHUqz@LaT-oH#-CHn0bai`td zC58vZ#N8ropBR-XrtKD4`^2zJF@Cq0vri1qbb?|}Mr4X9yG6!6ffE&LbWlv)ErR>R zxGa&oTNL9Y(>aOrpOS%r-cEahkJ3-@FWsjKBTrD-&X#3sB^iamD|TZf+}6<=@k)m# z!G%xN>wFO?5VLdK8a+^k`QhVK>!U-*BUIL?xoD4yYOfN$Pu%)guEQ>;TlpxFI9&MW zt^)B>SJJtikt=+;u5^o*zL{=Qqec{r{3LgBZeDI)L9U1|jEyY(t8;S^ehmGJF*(AY z8}ploFk#OZemcp^osVC2Jz0#G5$Jc0aZUp6A>!v#vcqPJfsJ$$KSy77^2?~usLL~? z@Lc*GJ6nvXp%Zi%4AW`4TxQ}$xL2x-QfUpJEe6Qw1O2;aOEqaSHr|e}dkq=6(;kUB z4rZD33riq(KuV;E;rYVO6T>Ism*q3Pza|s=4id8qgnu%Xs(+FgoFnYXV&rUL%X8ld zw`l0KCK=@}in4H|@HaOJOm6rwiP}s}m(L#SHN#WSaHOAvbX+keUd4bMk$`>)dewI7 z08ITPPZYjYu6kOYDb;_72+3(;2=ZqnwC@vR_lj9)YNyni7a}lOB&lLKKqoNU-ch@B znefeVRnk%wsq#WNZ4x>uqeteR*_4NDTh&wxh1+o^0=ZgGqtauiB;o%Hg}v`;YW4lw zudyfg7kF~;*NV8*3o%=pCkD(GabwlAgg`1W*^&r%-K76f+&zAXiHtLYoBBGp>J@7?w{KxQSj|@`UV=j#u?~ zpiz(AK2WW!$I!k1MyY!UD32R^#u+7dl$4Y#8arRaj}eKZsl6N|Z>Kn&FZ#=lLr)=# zdW^HEqc?rC+UO~6`Wf^)W`_P=D*`J-T3t6MwtwsBYw-N!)(TqRhpc}AkA%a= z3VW9DuN2d;#%P6@+9v!f#6MjF7L_a#{&8X)?8Q^o#uY0{@XUOa7_Y7|*tb&jqb^DO z3VSfx$`TPjdxeNA6?mw{%BT1*g;*`(H!Ox9j~h@@vZ4fKIctRwrD%1B^arp)1m@2c z32&5$xcOo>?oi1>tVFuA4vL|pMba6R$KuTPk`*gOV1`>)XxTm3{()Lpbmbub20kM% z;_nb~mz0*ADQu8V5%C9wxPBOE7UsgwZyZkG3p2G2I7YoF@pDHUlMYAF@$@!5Lu4dW<0TQy>EfUG2#i(5RMMVgl zXJJg&^N7(~O9;9WLH?OgZCFJw=OE}Nigh#`e8v2+-@Js1 z976`<^flP7R7hT4XUU>GI_8&bm|1d0Nl9MGA}GvriPGv$DEyoh*31{f;hG(y|5%tL z29CjRp6IXsP?g**2BC>Sn?Vf)x>}wZ+K2^eu0lsEZl-Aq?RbKK8xSDU-Bjs~a-gXg zHltpsT{3fKq-5-h(lOFjXK;<)X@pRYAyg70L@x$G=qIQZuBuomdJzCpzwAZo7Tf3> zB^qt2_vsa+`Y68YsT+3-M z8HcZ(bA++8+}N~b17g$2n81pzMZ=FBG5hDjH^CL4*ViHNClZ)E{KOMa#DGCi2;6B$ z27|Nq24~L9o-j-Jf^G!)+9Q08>M4362ylk<xXNVjAB z#v%MT5kNzhMK|?$Ja@oG1jHjOI7P%Ci>3;ADuzmyQkV+~Kyh27=3o$7j$I@YPN0|r zGDZAEnG9DX5=hk)C&o0yKzRoj2{99<#m!c%bP8Ex5LqUO79prO5QGI~L~OL^mn{PA zWDTm<2`CDj&V<7t49|<7ojOddd_~(u-?>13+=Kjx`v^~p$B8&h(jbqi6OY>fI`Qg$ z@pp5DoBke%HMn&@FFxr5J!opEXLZQ8IJ7CFUHC@evV+ z9DU8h|Du(6D70yGWag>ZZkckIPtbXdgwPK?EG zUA!F!tt({;&du30N$-~KBtiQ^U`9g-hZ*vewq6jv`6fjB9|&KDqEIGPPrxsR(8m}J zj=6KRqn`H80oTV-t>eas(f)Qj5lhnhEfy&l1%ydNb)VEXQRy?Ovb~}mg|ut4|DZ3C zva}|2AN@Iif1B=fPS(}}XhODA0UWp(fADwR!F6j79>f{_Tf4S?-N8H7hVW0tUAs0y zV)b+_&nYtg)g7plf2k0ad1uy7hPA$1OtIk=g${E75Tp zC)f$c!$0bYlghD1{+gRIJE_qA$o@yH#L`7{lr4I6QRyN#71|D&np`)~2&27^{d;_g z6vd4|8yw?pAOaP(%AoS)FoTM@1FS=Z_O3%wPahyAq|yS+q4{F+VlgyF#4i#4KZ?=W zG(s~H?G>ias1B&HZdC`q8e-^nHp+C=(i=ihn}Hr+st6QTi(%tr%akJqhvmt8%8T$0 z1g620N(UkHaGIn}{XU;Mi4ztktP)BGowgtW3WY_2@%=4-LUL07q|BteL?GBLY0|=RX+Q@1hWL(8hT&%{NH}wWIBP-D*$Wc(ED+}`NV<4I@}&#<<9(G_xuovo z#`hwZ1br7SNRav_^dYCyotOrr6u$+DV0iw5WT>#LNggiCC6>8NW^#98E^(94ls+Y; z!c^oRR~ayC506qR`b~ z-#6$yOPxzR+daR4f^xobn$Pi?1&R0=>R@Pas-l%vE5Af+y@kdI{bI}S!{-5`jt3|e>iGiM2%hKAm*0_6dEocWFf^#s(i0lP?VHs3K&dB2L;|B77%tW=X9}L?$PDg9Cd-i-(t}JIJ|>J$ zT3d&|I^G&8WysU`u>}jY@Ub)NVaNUaRea)N8k_i zbmOgR&&4h{#z-lH!tLguPG=V?%qaZz`ykxS(E#jC$WUJTeUy{2M<+pax51yDWX?v| zM7j-08R}Wb9+wh?`aBMQdg8MWVF{3-q5qy_&_S>UL55Q4N#;p}y$KoWRr!6yJofk{ zK`?nD{`h@w;y3nqm!JyVpYX@;n;I(sKa2hRk%R>q%xMrG+l=3@Ot+=LlpL zKxSqydbW_BTFaUxWxDt0vmw(3J+ph!b0uUBLuO7dGT)`NHd)qODKilM{wHKAwpvzUFM2+s zv>;Q|i;T~Yz-^XQEM+F+H})6+nLmFOv=$<$r}lX?WG;edlt>wJ?$~1nrG;Y={`q~U zjRw7#Bg>H~l``?v+{YaGj?7|&_gQg7C*mQ#*h zog9G~J2?U~?&1i{c!(n~<8h9_j0(J=?=j4P8EZKL(zOgBuX~>(;QT2^!1>(kOwF0# zd@)DB`AUv}^R*lS=Nnx_`!j7Cp?vHiWLaWXjSrf>Eugwt}_@P*$KrF3()0?(_Sjt`!Lg zWR<|uR&04)TS40R;XZplnj!y2#Rx&>vHlhVZCAi|I!4RsIlNmy_ayCP#4h9)Qlyf)& ze?E#M@aIB~fbfwx5#h;kagrk$-#C)7iz68W`Dc!A9Ldg zdm2kQk};yQ5x=kTdAfUEg=Y}eZy7qzXU(P#yL+VPW(T|Px6mF;>i)h4($rt&2i?2h zckkU@2<-meeH-2sR;j1rUR%wSq~~S^dGA8^y6-%PQa5|u4>E*$-9KeW7LZpMf)1?p zHbcmYKQM%P-Cr;S9au|z!%Ure-GdlH-HovvK@WBsN6_oe;0Q<`!x4}!;Rr}qas;H; za)f%_90BPzj)3$ohET8jdX9keVUB?FuQ@^)eXf}snczH$Bj8-b5pa%h1f0+22srQO z2sr%)@`THCJ z=Vv(r&L43EoCo7^z^l30;GD@3aIWGAIJa{IoUh;rIN!&R9B_V>BjEfcN5DDdLX%Gp zI4|G`IEOg`&Zlz(oNwX?I6uY_aQ-bvz&Y_EGxc0>p3M<(F5?I|H*y4=_i_ZB4{!vW zpXUfTf65VX9&s__1I`mU0?xA-l9!IzCl^6$V9`kFKG|l{{p-R6%ld?k8j%d$9Ztq$ z^kSU*ed`j{S9~bMJLul@vzPVVVG=B$89MJs&kgo4CbQ>W(+Xsmb%~4U=Wg0qMcu#X z*)3}HAZAqqjSO^oNjqm`#ZLxnE1H0kMt+bLpY*q#d))WN!gHBGdUj@d_ajSNz87u9 z`3ym^TURm!#cq9%A;>iA5r&}Ht)DXl#csXH5EQ%hCx)Qdt>o{UeCQt6pCcIu|ae*x;dzHa)#*A*$O?$F;Y}I z*Ur?X^JmN@(UT@Wu7M04&d7?(#Wo~FbZVhj($`76YmM&OndlqZ)gu6z{2$f zwY0P&j7sYvz|(Y)`#UXC1Sp^SgfvpnYCc>J@H^ z<_V>K@d%yzLIjaCKgd@^xN3?W}# z&Jgm|wG1I&4Ksv%brVC#S6diDzPgJe@YQoT0@9arB#3@EM?m^^j)3$%90BP^TtxdJ z?W3bg=R>etjeq>0(s{`(op|_0fD7P?O6NO&(53U_bj#|3oOh&WWM}dFS7<{ecCJay z=zNL1mr5s8-`1WAOLw{m#lHiZcQNEJ5ZdC#D^p~cwVEMR%4=PO^gM-FwC#--D+qKG zL#W&v7?KU7gCSJzoeZIJKb;{|?t2(Q<-V68RPNv82+X*iBQWD8j)3%cIRetRaU>h% z&JmFQ5l2A!h3}ZTLGzx!;0Q?niXrs$_iK)T^Sc}Y=YHQcHPgK3Y>t3)4oARwK1aa$ z0*-+5H#q{%k8%W@f65Sg`b%TIlpr_8fMUeYtvQ(&A?`z&`d0_OM8Cs?T;zz?c}uaDF%@Eo^RFdCYLV!82gq9t`54GM zE)uG(Z>>$uvfgtMJ^J+JP0_j9|7H`R_Gbx0sQoEt2&#p(mLb&sG%*C#!s=v59+1-* zLhaAF459YtDvqFD+|Ciyi$^#D(ob*%r2otjkRHo=gBc(_ks}~In2GN8PN^=>#N_E>Kz`o^XtCnFK3xRyfkmW!=V@M5<&l%DTM z5^ArnZA;C__^W}03CTS9Wo-q?q+-cklYxYRWLd2qvamIBN@_;-78fDg&p}$947m)* zc81&p}w5l5o!;qtsBh{YU@%MLT%lygJxRP z)}6+XTp;H$BoD}5hQOVzix@&}-FG+wGj8Ju%=jTkK>9w8fb=6A0qMs%0@5#X1f*Z# z2uOdz5s>~fL#VAAc!!xAnczH#Bj7xSBj7xiBj9{AN5Hv^Bj9`zN5DDE5pb^O2sk$~ zgxb0-9LYclas-?&;0QQh#1U}5lq2AL1xLWSy35R;AUJQ}2srk0aoGfFt1iBaVRcVUB?FGaLcu=NUpH?Z4s(IRAzt;QSFs z!1*(dfV2N}(^48~4{!vWhjIj*$8!XnCvyaxGZ;c6?b#dw=lL7~=gk}e=Vp$8a~ns% z`D~7W^MxD%=gT+(&bM&{oDVUCM%wS;2sl5$5pe!BN5J`gj)3!@I0DXJaD?*t46`h9 z!FdEnz&Vp6;GD$}8fh=!2sp3d2snp10?wCk1e_n>2sl5&5pezmN5J__j)3!!Gflhl zz0)u60iol4t!#6f)m>gd?~Sz8{5T zSn+b^NRR1dWM*2+qL84qHVVnIu82ait?Q$Z9P4Hm(LG^H-W{lSx-S89DL%_MbWix5 z`&9o|ym?Pl4gCpR)nqcMV6t`8ke& z^Ya`5=cLO_K3Q2fvstg{)+V2|SXz==l20b;mgFb6q7h7fP)p)}K({2PO~v>$ z)0Li^l^#2Wb^z2iy`-O5b=&gm8%?`lmh~P(P!!e&3_(#?A2B2w$R8PkqOktT5EO-F zf7?t8MPUhspeU?FhEUrwm?J2Q5gY;O6pn!OM2>*;RE~i39FBnW(HsHk0*-)mF-Jgp zF+-?rso)4WujB|gpU4q#uH^_gZ{!F#H*y4=+c*Nw9UKAY(>Mao7chj{mTz$coWIQx zaK4)(;QRf0p}Mv0?xnU2sr;IN5J`0j)3zQ4579qaFgj#S>QZ?Bj7xoBj7xa zBj7xRBj7xXBjB9L5pX_=Bj8-X5%LX&P}@?;5pZ6^5pb^I2sm%%2spQM1e{Oh2sod` z5pceMBj9`)N5J`7hR_q@%^U&e{Tu=3+c^TxcW?xpf5Z`Revl*J{1`{T`3a7I^V1vw z=T}@rx5oQr`$Mg9o^4szp>6RF-9Kz|M@mN`5RJBR=oWk7OS;9LW`ugD)MDS4s#|RO zbPm@;lGI|K`Ic_6_fA1e3_0&e&&bW=>q#i=eze#{FGRQ4t1dTv9vN?)!VqMN` z!4Z)DCP#8C>jsYG!ZSGn()V%%q@QL8wb;*d1e`zS2skHSY1&2erxQ5>&gmQh=WLFE z^HPrFVw8^~c^EO{2sk%0gj(!2j)3zy90BJ`IRegq;0QSXjU(V3_?BrY^#+qT0?tD@ zl7}Y+j?BlHCqt;kp2-n#F60O}mvRK0Pv8hRFXsq2hdBbyEgS*oT^s@DzjI_ho@K5w zZKoEylOy1KD@VZj`y2u1LmUC;`#1v54{-#XALj@-KkXvAWuyI?RX_85{5cnO&^vU? z_JG^6;o-Q4IUsM3sfGN}*ilDMzO{QcBk;qgI0Di?#}SbJBS%0waD&N*=7mRd1f zj?pg0%8D})PBQ!;hIh}=4ABTXD^E-*VtC6pHN(Mk(RXG!Pummg&q}Hl$Ytf_6{Mk1 z<{>dGDXtC`GnF zu7_Q_YJhbA6maQb?JYF(KS{{>KpxZ7n&RVmgIV)*0}njx+47y~(e&=@@(Dxb?MGD2&LE6ZPzZG!G^lt9Kq%2yOu zE-Wiw`D-Rq4Ve#Jq`V?i>iNh;v|Y3~)8)Papp%p#y@{o+HPimqN;4YsZVuA?D_8S* zkl=NYqO>y2+FOcTE3~&PVhGjuN`~N;YgIFZ`eP@#h~`WiVJptDo{I?T{U-DSR2y{? zkl3;yADj0x?PIjgD21ZBhukB(+jcC@<)iINVhGtak|AW*Xcy5|(7xNsiYW-^trpRs zoPW%dAL?jd06*~PJKD9 zx^HdnMHhY%BGE1|-5uu=!^0}J%7<%XklPvJY%t^QLabsPhK$~q*tYa0#9zrn=kQaI z@sJv4qhb#se!pNcg!~%FN3id!ue6@u6N0Kh?YT<*3l>Y4vel(ZS;@px2DwPYd7Fti zQzPKAtg5sGyMVp$K-Mh7~_ZU&cy_?XP6KsuQoYHGJJWH1o5W0KaB0_5F8X0FZxvidF)$p$i-Aq#-09h^u{ zsI;lRJ-@D2?S>?g{Gvi{=VYB$8DcdtJ}ZH!eT1}34Ui2?rV)tRk4Vex1ag#fhgCj* zJ`lB=sFt}3h}vI5Bew!kyQC5lDr{@4jBIRs6J5U1Zs{C?%!2i_qpyzj5D>M8twx?B zWE1V~rjb{HsJ&G+@-7gyYmi1h2QsLI_KwhqodAaQs8ue~ABft6RLhJ6(gi-#T$yP= z)E=!Q6Dn#9lND-LWF0GmV!^IaZmeT~(5qwPTx1E!;NM6WS&6F!=uk~|ky=8)Fw;ev zfKhmEp zq`0wcYO2w|%y*IggdoQzxyWcjHqnk*T2Cq=;5@@c<^ieLiYGu9nGa+l(#mp?A|Ps4 zTdn5=AZkxtjhqBT?Z~Q;O(cWV(_B4mK&&w4K3$}XWRO<2i<}4K@Os)=TI;zANEh_X zbCFvp7Oa@*B8PyeJ!f>R2Y{%3MKtmxkmsD|ZX4nliv#k}IcD4PTOco?Td3|1B=ct= zhnb9kFHgU~l);xytaye@0WxH-DU%Ll=|v`TG?3ljFp)(-jyvB(Rsz|_Qm+AW8%wJR z$YqT4sX(SP&F26)$Wp%q$fS$Sv~C9SyK_zC2SA=+$YVfmzR;9;5lDZQ`ny1W$vA%k zCly&cH= z%&s$lOlEra0x4$5)j)!*ly3#Hj`6t*$gvE05XeIec@oHt%=TA+9AbI+HjvG%+&=`w~M1U+}dRl;_F+RJ2+`wec2NLfhp|a%*sdPSbIfu$tNaO_fLtI6DlYxT?YFPFx#(y%zwB@sEA4(qt*r@BUzWa2<72Th^5}xm71GdD4Q+yp0DP7 z4`kFkvr=XQUTuZUADN|(Kn6WBbeMIlXMud^%7n^fBWPkZwu{i!$B;S9Jp6A!_A;4-L1@((G7QLJ z7YS{sZ)nFe_2HLwTBLabWLmm(>4fSV>7lK5yo->`T*&Nm^$?N=2$f8 z2}uXCz(pul0b>2-44oDsCjfcybQ4(%WGa(68OWo1v`naW(`Jf!mX|ulH`0N;>>?Dt z6|v57kx-;H6mAMPT+h-v6EfvpS~JDE2*@hN`FbF=jL-LgsMX-Q1P=qTSgfajs8!`! z=9fTDbNNtO?*TcNA)f&m%^3OzV>E-w3R4 z;0Z25sn0^J>ll&)*Zdo?*XCjq$?!U+|l0B(cX3yi}f&M)GAzAAGG$6av*AjiT2)gK;R(His)G90ikawdoou8 zp)XJ?1fNR_)xfr{7j(H3LM^0Pm!kFDhFJ71X;04sK>l=xi98L2zQpXwybk0lFRjX| zP*tRhBSYzFX|+q0J%a^THl70En7x*9=pDs5x>-PQ&?k*OWCalVII@S-1ECKud&mwT^igAlglcPRDZ|#V5wi;*L*H}uVqFbH z&39{t`+;n}+myKj2z{+rYYx>nwWp`6d0~nb!txsV`8o_W_k)ye6{e;ZuPUv!)Eujn zq3K)jp)cTisXq+OYW`Hpgln2xA>_p(3w{onFWmcSDAdu^&|JG&%~z__=^DGxFiYP? zEczO*!#UK{+yY(nF#7_z?2dS0uBrDmAsJbcLnn>58_FDVSPiyDvE3=ZtS3eJ9)W~M!VfBXXsRhV0dq7eQRrT ztGrqTpV{EawRBY1H%401V~~s(B-2H}rLeuV!M%2dIHmrjwKZ)ma>UcStZ^la3vrj{ zS7rH2Ik2>*xig}SlHyCttE-|U%B#y6!V{>8R#_9JvL;3)A%@C|t&N`j#klfpr>mfs zIIgnTRW`fI@vaKPErw2989H%g=){$w6IX^#Tp2n~h?qKY<>@SGsc&Y5L_krv-OGIf zN}JkUhE?0zScIyUdQZ5j*0@-OXssPBUQ}lUS(Z2?z2d-y99xzlrJ1#!LNyF6@e0(3 z(mIz%T3w{3VlosjA4#3kEx}T1QTR$i+V{*wI!LX$WtVAk=p> zwWGrpuETOf)bU7rsIoY}Xtfn;$EQ0RBKoQ}+|<&%wJkzSa4w?}6*`YJG*Dbq6-i0W zH85qf6jYb3^&2;}d(w?)EU-ULNQ#A;w?tY~v-MTDA>7)Snq!5wHn(mLHG~^mQgf}) zrbxJ5UF2ElQn$9Mi}^Bxwlp^&uhOkhxUi!Y`GpI_&u?sLsBiB;N*Pdqd_=~kr(#d5 zP)$dB`=*XonZIrI+asac#<~m;*xFj(9wAS%WY(y&I$Rf$6)?y7An8$|s*2L8;>?Or zQRNESeq*ymORLnPC`+!Oa?Xp;%7tjDl%>9`PLuN9htTOtea2jt3YJhTuUr;dkzcmF z*jm15BDyNv`DU2#y5~?a)Qw$MxQM{~(#A`#+AQ_eBgjGyAJxr%?t&SF& z2u7ZUw}#s3UVyTJhdQT)%}pr(w)*BKnae8cLol$pbsLJhvmIThn)>E8i~Jn!)!2x^ z5o`6)ym>Z<>R%e-3=g9*NQo~W!05sa$%c! z9$LPv6l-m&^2>-MqAx6miZXpwU0k`ebQuMbDyb<1%Z!UqxS;_+Yi%eahfH*6%WLlf zdrK>GT5HKwrDakCT$~#hB=jjfTc4ta(S)bIM6MwJHq>v_fE6;EM=NCBT&)o9I;sJd zr%hq!cA~D_I|VLvT#0c#8_&m zA`*zLrIuF}S7v*9bJZyYFDtJ`V37hSR(7a*jT=v?F@eJTW$6fZ3{bY3;Y*i$k-;>> z<3O?*O!*1LSdQn46UPk5>pTpavJ~j#2I#2hm;anBC3M$#AK9d*bgBZE~@IXWm;oPsv*C3F*Vn-2H! z4b69b8#N$B7^GJ7HIdf(mQ9h?a6=(IL(~1Lt#P@0zD7$LY28v^tAwjoS7D&Nd^vhb zq}#cLs!2IMabqkl+!W_evqPoRzp8RjO4wCEYMyrW&p zRKwdLfG!brV5;%BOiypPqwCX5?=+~o`;pd~Fy(V*VScC*y>-PRD$ zX!SBzkYmlr7J0s@J`}0jh`gu@Z;7Y@bJ$GXclUw{Js(pD%^Tq>-UYlxiec8IzJ~l; z>T76r^f}I5s5;DQoEu%u?%*JGyEcS78rt17sYfbDo@L+E85a%}ceb~N;niVuah(!t z-mcw9c^igN8&G+WP*td)N_x8U2taPqSQl!DG;M6(L~QB7paZ=dDO(k3FQ{)ZF6 zDy;HE%{3qXYTIB3jA^N_!drt>MX6bfw6r!i>T2WGyiBTjt}J$Bq*8Ze$-&$pS+%3n zsck@9GwFKS1e=I_5>*w!(W{=5Lff00BJ>O#?r1|+AP-dLH$>_v8)?uX6sj(j%|R0i zrKKH7Nu;hFRo1y~jcmkj+;C;pNT3OHuGMfUVz^JXIEOm(k{X%XmTjR88?4ltj{1hW Zv~YWSYdxOCF*4|kg@kKrS|eMm{}1P*IEMfL literal 0 HcmV?d00001 diff --git a/bios.c b/bios.c new file mode 100644 index 0000000..42ffb72 --- /dev/null +++ b/bios.c @@ -0,0 +1,450 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + Bios.c + ************************************************************** + Îñíîâíûå êîììàíäû BIOS * + äëà ðàáîòû ñ RS232 +****************************************************************/ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "RS485.h" +#include "bios_dsp.h" +#include "crc16.h" +#include "spise2p.h" +#include "i2c.h" + +//#include "flash_tools.h" +//#include "spartan_tools.h" +//#include "big_dsp_module.h" + +int flag_DEBUG = false; /* Ôëàã îòëàäî÷íîãî ðåæèìà */ + + +//static unsigned int *RecvPtr; +//static int BS_LoadOK = false; /** Ôëàã óñïåøíîñòè ïðèåìà áëîêà */ + +/**********************************************************/ +/* Ïðîòîòèïû ôóíêöèé, èñïîëüçóåìûõ è îïðåäåëåííûõ â ôàéëå */ +/**********************************************************/ +//static int _getbyte(int *addr, int offs); + +unsigned int read_memory(unsigned long addr) +{ + return (*(volatile int *)(addr)); +} + +void write_memory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)( addr )) = data; +} + + +/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */ +int get_command(RS_DATA *rs_arr) +{ + int cmd; + unsigned int crc, rcrc; + + if(rs_arr->RS_DataReady) // Äàííûå ïî RS ïðèøëè + { + rs_arr->RS_DataReady = false; + cmd = rs_arr->RS_Header[1]; // Ïðî÷èòàëè íîìåð êîìàíäû + + // Ïðîâåðàåì äëèíó êîìàíäû äëà ñ÷èòûâàíèà CRC + if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH)) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return -1; + } + + if(cmd == CMD_LOAD) // Åñëè êîìàíäà çàãðóçêè + { + rs_arr->RS_PrevCmd = cmd; + return cmd; // Íåò ïðîâåðêè crc + } + else // Âñå îñòàëüíûå êîìàíäû + { + // Ñ÷èòûâàåì crc èç ïîñûëêè + crc = (rs_arr->RS_Header[RS_Len[cmd]-1] << 8) | + (rs_arr->RS_Header[RS_Len[cmd]-2]) ; + } + // Ðàññ÷èòûâàåì crc èç ïîñûëêè + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, (RS_Len[cmd]-2) ); + + if(crc == rcrc) // Ïðîâåðàåì crc + { + rs_arr->RS_PrevCmd = cmd; + return cmd; + } + else + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + } } + + return -1; +} + +/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */ +void Answer(RS_DATA *rs_arr,int n) +{ + int crc; + + flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = n; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + + rs_arr->buffer[2] = LOBYTE(crc); + rs_arr->buffer[3] = HIBYTE(crc); + + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 0; + RS_Send(rs_arr,rs_arr->buffer, 6); +} + +/* Âíóòðåííàà ô-öèà */ +static char _getbyte(unsigned int *addr, int32 offs) +{ + unsigned int *address; + unsigned int byte; + + address = addr + offs/2; + byte = *address; + if(offs%2) return LOBYTE(byte); + else return HIBYTE(byte); +} + + +/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/ +void init(RS_DATA *rs_arr) +{ +/* + if(rs_arr->RS_Header[2]==3) + { + if (rs_arr->curr_baud!=57600) + { RS_SetLineSpeed(rs_arr,57600); + rs_arr->curr_baud= 57600; + } } + + if(rs_arr->RS_Header[2]==4) + { + if (rs_arr->curr_baud!=115200) + { RS_SetLineSpeed(rs_arr,115200); + rs_arr->curr_baud= 115200; + } } + + Answer(rs_arr,CMD_INIT); + rs_arr->BS_LoadOK = false; +*/ +} + +/**@name Êîììàíäû +* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë +*/ +//@{ + +/** Èíèöèèðîâàòü çàãðóçêó áëîêà. + Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */ +void initload(RS_DATA *rs_arr) +{ + unsigned long Address; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + rs_arr->RS_Length = rs_arr->RS_Header[9] & 0xFF; + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->RS_Length += 2; + rs_arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + rs_arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + + Answer(rs_arr,CMD_INITLOAD); +} + +/** Çàãðóçêà áëîêà. + Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */ +void load(RS_DATA *rs_arr) +{ + unsigned int rcrc, crc; + + crc = (_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-1) << 8) + + _getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + rs_arr->RS_Header[0] = rs_arr->addr_recive; + +// CNTRL_ADDR; + rs_arr->RS_Header[1]=CMD_LOAD; + + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, 2); + rcrc = get_crc_16b( rcrc, rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + if(rcrc == crc) + { + Answer(rs_arr,CMD_LOAD); + rs_arr->BS_LoadOK = true; + } + else + { + rs_arr->BS_LoadOK = false; + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); +} } + +/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load + @see load */ +void run (RS_DATA *rs_arr) +{ + return; +} + +/** Ïðî÷èòàòü à÷åéêó ïàìàòè */ +void peek(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data, crc; + + flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + + if(Address>=0x20000000) + { + Address&=0xFFFFFFF; + Data = I2CA_ReadData(Address); + } + else + if(Address>=0x10000000) + { + Address&=0xFFFFFFF; + Seeprom_read(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFFF; + Data = read_memory(Address); + } + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_PEEK; + + rs_arr->buffer[2] = LOBYTE(Data); + rs_arr->buffer[3] = HIBYTE(Data); + + rs_arr->buffer[4] = 0;//LOBYTE(CpuTimer2.InterruptCount); + rs_arr->buffer[5] = 0;//HIBYTE(CpuTimer2.InterruptCount); + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + RS_Send(rs_arr,rs_arr->buffer, 10); + +} + +/** Çàïèñàòü â à÷åéêó ïàìàòè */ +void poke(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = (Data<<8) | (rs_arr->RS_Header[7] & 0xFF); + Data = (Data<<8) | (rs_arr->RS_Header[6] & 0xFF); + + if(Address>=0x2000000) + { + Address&=0xFFFFFF; + I2CA_WriteData(Address,Data); + } + else + if(Address>=0x1000000) + { + Address&=0xFFFFFF; + Seeprom_write(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFF; + write_memory(Address,Data); + } + + Answer(rs_arr,CMD_POKE); +} + +/** Ïåðåäàòü áëîê ïàìàòè */ +void upload(RS_DATA *rs_arr) +{ + int32 Address, Length, crc; + + flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà +// stopp=1; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Length = rs_arr->RS_Header[9] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_UPLOAD; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + crc = get_crc_16b( crc, (unsigned int *)Address, Length); + + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó + + rs_arr->buffer[0] = CMD_UPLOAD; + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó + + RS_Wait4OK(rs_arr); + RS_BSend(rs_arr,(unsigned int*)Address, Length); + RS_Wait4OK(rs_arr); + + rs_arr->buffer[0] = LOBYTE(crc); + rs_arr->buffer[1] = HIBYTE(crc); + rs_arr->buffer[2] = 0; + rs_arr->buffer[3] = 0; + RS_Send(rs_arr,rs_arr->buffer, 4+2); + +} + +/** Ïðîøèòü XILINX. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load, + òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè + @see load */ +void xflash(RS_DATA *rs_arr) +{ + return; +} + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void tflash(RS_DATA *rs_arr) +{ +// volatile unsigned long Address1,Address2; +// volatile unsigned long Length, LengthW; +/* + if(!rs_arr->BS_LoadOK) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + run_flash_data(Address1,Address2, LengthW ); + + Answer(rs_arr,CMD_TFLASH); +*/ + return; +} + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void extendbios(RS_DATA *rs_arr) +{ + volatile unsigned long Address1,Address2,Length; + unsigned int code; + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + code=rs_arr->RS_Header[14] & 0xFF; + + switch ( code ) + { + // Ïðîøèâàåì EPROM Èç RAM + case 4: Seeprom_write(Address1,(unsigned int*)Address2,Length); + break; + // ×èòàåì èç EPROM â RAM + case 5: Seeprom_read(Address1,(unsigned int*)Address2,Length); + break; + + default: + return; + } + + Answer(rs_arr,CMD_EXTEND); + return; +} + +//@} diff --git a/bios_dsp.h b/bios_dsp.h new file mode 100644 index 0000000..9ed9601 --- /dev/null +++ b/bios_dsp.h @@ -0,0 +1,120 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/****************************************************************/ +/* Bios_dsp.h */ +/****************************************************************/ + /* Îñíîâíûå êîììàíäû BIOS */ +/****************************************************************/ +#ifndef _BIOS_DSP +#define _BIOS_DSP + +#ifdef __cplusplus + extern "C" { +#endif + +#define BM_PACKED 1 +#define BM_CHAR32 0 + +#define CHIEF 1 +#define SLAVE 0 + +#define ADR_FOR_SPECIAL 0x100 +#define CMD_MODBUS_3 3 +#define ANS_MODBUS_3 4 +#define CMD_MODBUS_15 5 +#define CMD_MODBUS_6 6 +#define ANS_MODBUS_6 7 +#define CMD_MODBUS_16 16 +/* + +CMD_MODBUS_3 = 3, + ANS_MODBUS_3 = 4, + CMD_MODBUS_15 = 5, + CMD_MODBUS_6 = 6, + ANS_MODBUS_6 = 7, + CMD_MODBUS_16 = 16, + */ +enum { + CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH, + CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND, + + CMD_VECTOR=61, + CMD_IMPULSE, + /* ñòàíäàðòíûå êîìàíäû */ + CMD_STD=65, CMD_STD_ANS + }; + +enum {false=0, true}; + + +/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */ +int get_command(RS_DATA *rs_arr); + +/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */ +void Answer(RS_DATA *rs_arr,int n); + +/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/ +void init(RS_DATA *rs_arr); + +/**@name Êîììàíäû +* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë*/ +//@{ + +/** Èíèöèèðîâàòü çàãðóçêó áëîêà. + Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */ +void initload(RS_DATA *rs_arr); + +/** Çàãðóçêà áëîêà. + Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */ +void load(RS_DATA *rs_arr); + +/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load + @see load */ +void run (RS_DATA *rs_arr); + +/** Ïðî÷èòàòü à÷åéêó ïàìàòè */ +void peek(RS_DATA *rs_arr); + +/** Çàïèñàòü â à÷åéêó ïàìàòè */ +void poke(RS_DATA *rs_arr); + +/** Ïåðåäàòü áëîê ïàìàòè */ +void upload(RS_DATA *rs_arr); + +/** Ïðîøèòü XILINX. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load, + òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè + @see load */ +void xflash(RS_DATA *rs_arr); + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void tflash(RS_DATA *rs_arr); + + +/* ðàñøèðåííûå êîìàíäû äëà áèîñà */ +void extendbios(RS_DATA *rs_arr); + + +void write_memory(unsigned long addr, unsigned int data); +unsigned int read_memory(unsigned long addr); + + +//@} + + +#ifdef __cplusplus + } +#endif + +#endif/* _BIOS_DSP */ diff --git a/cc_build_Debug.log b/cc_build_Debug.log new file mode 100644 index 0000000..152a2fb --- /dev/null +++ b/cc_build_Debug.log @@ -0,0 +1,3 @@ +------------------------------ ice.pjt - Debug ------------------------------ +Build Complete, + 0 Errors, 0 Warnings, 0 Remarks. diff --git a/cntrl_adr.c b/cntrl_adr.c new file mode 100644 index 0000000..2f29cdb --- /dev/null +++ b/cntrl_adr.c @@ -0,0 +1,43 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + cntrl_adr.c + **************************************************************** + * Àäðåñ êîíòðîëëåðà * + ****************************************************************/ + +#include "cntrl_adr.h" + +#define ADDR_FOR_ALL_DEF 10 +#define ADDR_ANSWER_DEF 0x33 +#define ADDR_TERMINAL_DEF 11 +#define ADDR_UNIVERSAL_DEF 10 + + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */ +int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè îòâåòà */ +const int ADDR_ANSWER = ADDR_ANSWER_DEF; + +/** Óñòàíîâêà àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */ +const int ADDR_TERMINAL = ADDR_TERMINAL_DEF; + +/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */ +const int CNTRL_ADDR_UNIVERSAL=ADDR_UNIVERSAL_DEF; + +/* Àäðåñ êîíòðîëëåðà */ +int CNTRL_ADDR=1; + +int cntr_addr_c; +int cntr_addr_c_all; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all) +{ + CNTRL_ADDR = cntrl_addr; + ADDR_FOR_ALL = cntrl_addr_for_all; +} + diff --git a/cntrl_adr.h b/cntrl_adr.h new file mode 100644 index 0000000..100021f --- /dev/null +++ b/cntrl_adr.h @@ -0,0 +1,44 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + cntrl_adr.h + **************************************************************** + * Àäðåñ êîíòðîëëåðà * + ****************************************************************/ + +#ifndef _CNTRL_ADR +#define _CNTRL_ADR + +#ifdef __cplusplus + extern "C" { +#endif + +/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */ +extern int ADDR_FOR_ALL; + +/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè îòâåòà */ +extern const int ADDR_ANSWER; + +/** àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */ +extern const int ADDR_TERMINAL; + +/* Àäðåñ êîíòðîëëåðà */ +extern int CNTRL_ADDR; + +/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */ +extern const int CNTRL_ADDR_UNIVERSAL; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all); + + +extern int cntr_addr_c; +extern int cntr_addr_c_all; + +#ifdef __cplusplus + } +#endif + +#endif /* _CNTRL_ADR */ diff --git a/crc16.c b/crc16.c new file mode 100644 index 0000000..a69f55f --- /dev/null +++ b/crc16.c @@ -0,0 +1,221 @@ +#include "crc16.h" +#define MAKE_TABS 0 /* Builds tables below */ +#define FAST_CRC 1 /* If fast CRC should be used */ +#define ONLY_CRC16 1 + +#define Poln 0xA001 + + +#if FAST_CRC & !MAKE_TABS + +#if !ONLY_CRC16 + +static WORD crc_ccitt_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; +#endif + +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; +#endif + + +#if !ONLY_CRC16 + +/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */ +/* are sent MSB to LSB. */ +unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register int i; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ]; +#else + crc ^= (WORD)(*buf++) << 8; + for (i = 0; i < 8; i++) { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } +#endif + } return crc; +} +#endif + + +/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */ +/* sent LSB to MSB. */ +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register unsigned int i; + register unsigned int ch; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; +#else + ch = *buf++; + for (i = 0; i < 8; i++) { + if ((crc ^ ch) & 1) + crc = (crc >> 1) ^ 0xa001; + else + crc >>= 1; + ch >>= 1; + } +#endif + } return (crc & 0xffff); +} + + + +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + +int get_crc16(unsigned int *buf, int size ) +{ + unsigned int crc16,i,j; + + + crc16=0xFFFF; + for(i=0;i>1)^Poln; + else crc16=crc16>>1; + + crc16=crc16^((buf[i]>>8)&0xFF); + for (j=0;j<8;j++) + if(crc16&1) crc16=(crc16>>1)^Poln; + else crc16=crc16>>1; + } + return crc16; +} + +unsigned int get_crc32(unsigned long *num) +{ + volatile unsigned long crc32,key, num_vol; + num_vol = *num; + + int i; + + crc32 = 0xFF000000 | (num_vol >> 8); + + for(i=0;i<32;i++) + { + key = crc32 & 0x80000000; + if(key) key = 0x31000000; // 00110001 + + crc32 = (crc32<<1) ^key; + } + + crc32 = ((crc32 >> 24) & 0x000000FF) | (num_vol & 0xFFFFFF00); + + if (crc32 == num_vol) return 1; + return 0; +} + diff --git a/crc16.h b/crc16.h new file mode 100644 index 0000000..148c7d6 --- /dev/null +++ b/crc16.h @@ -0,0 +1,10 @@ +typedef unsigned short WORD; +typedef unsigned char byte; + + +unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size ); +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ); +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ); +int get_crc16(unsigned int *buf, int size ); + +unsigned int get_crc32(unsigned long *num); diff --git a/create_rs.bat b/create_rs.bat new file mode 100644 index 0000000..eaa0571 --- /dev/null +++ b/create_rs.bat @@ -0,0 +1,5 @@ +set iname=debug\lampa +set oname=bin\lampa + +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2bin %oname%.hex %oname%.bin diff --git a/ecan.c b/ecan.c new file mode 100644 index 0000000..26e58c7 --- /dev/null +++ b/ecan.c @@ -0,0 +1,355 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" // DSP281x Headerfile Include File +#include "peripher.h" // DSP281x Headerfile Include File + +#include "ecan.h" // DSP281x Headerfile Include File +#include "tools.h" // DSP281x Headerfile Include File + +#include "RS485.h" +#include "message.h" + + +// Prototype statements for functions found within this file. +interrupt void CANa_handler(void); +interrupt void CANa_reset_err(void); +interrupt void CANb_handler(void); +interrupt void CANb_reset_err(void); + +// Global variable for this example +Uint32 ErrorCount; +Uint32 MessageReceivedCount; +Uint32 MessageTransivedCount=0; + +Uint32 TestMbox1 = 0; +Uint32 TestMbox2 = 0; +Uint32 TestMbox3 = 0; + +int CanTimeOutErrorTR = 0; + +int wait=0; + +void Init_Can(int Port, int DevNum) +{ + struct ECAN_REGS ECanShadow; + + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + volatile struct MOTO_REGS * ECanMOTORegs; + + long id = 0x801CE000; + + if(DevNum<0)DevNum=0; + if(DevNum>15)DevNum=15; + +// Configure CAN pins using GPIO regs here + EALLOW; + + if(!Port) + { + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + ECanMOTORegs = &ECanaMOTORegs; + + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; + } + else + { + ECanRegs = &ECanbRegs; + ECanMboxes = &ECanbMboxes; + ECanMOTORegs = &ECanbMOTORegs; + + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; + } + +// Configure the eCAN RX and TX pins for eCAN transmissions + ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant + ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant + +// Specify that 8 bits will be sent/received + ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008; + ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008; + ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008; + +// Disable all Mailboxes +// Required before writing the MSGIDs + ECanRegs->CANME.all = 0; + +// çàäàåì àäðåñ 0 àùèêa íà ïåðåäà÷ó + ECanMboxes->MBOX0.MSGID.all = id + DevNum; + +// çàäàåì àäðåñ 1 àùèêa íà ïðèåì + ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum; + +// çàäàåì àäðåñ 2 àùèêa íà ïðèåì + ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1); + +// çàäàåì ðåæèìû ðàáîòû àùèêa 0 íà ïåðåäà÷ó, îñòàëüíûå íà ïðèåì + ECanRegs->CANMD.all = 0xFFFFFFFE; + +// âûáèðàåì òîëüêî 3 àùèêa äëà ðàáîòû, îñòàëüíûå çàïðåùàåì + ECanRegs->CANME.all = 0x00000007; + +// Clear all TAn bits + ECanRegs->CANTA.all = 0xFFFFFFFF; +// Clear all RMPn bits + ECanRegs->CANRMP.all = 0xFFFFFFFF; +// Clear all interrupt flag bits + ECanRegs->CANGIF0.all = 0xFFFFFFFF; + ECanRegs->CANGIF1.all = 0xFFFFFFFF; +// Clear all error and status bits + ECanRegs->CANES.all=0xffffffff; + +// Request permission to change the configuration registers + ECanShadow.CANMC.all = 0; + ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit + ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit + ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes) + ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity + ECanShadow.CANMC.bit.ABO = 1; // Auto bus on + ECanShadow.CANMC.bit.CCR = 1; +// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set.. + +// íàñòðèâàåì ñêîðîñòü CAN + ECanShadow.CANBTC.all = ECanRegs->CANBTC.all; + ECanShadow.CANBTC.bit.BRPREG = 14;//49; // (BRPREG + 1) = 10 feeds a 15 MHz CAN clock + ECanShadow.CANBTC.bit.TSEG2REG = 2; // to the CAN module. (150 / 10 = 15) + ECanShadow.CANBTC.bit.TSEG1REG = 15;//10; // Bit time = 15 + ECanShadow.CANBTC.bit.SJWREG=1; +// 14,2,15 äë¤ äîáðûõ ëþäåé. 49 2 10 for 745 + + ECanRegs->CANBTC.all = ECanShadow.CANBTC.all; + ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0 + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared.. + +// çàäàåì òàéìàóòû äëà îæèäàíèà îòïðàâêè ïîëó÷åíèà ïîñûëêè + ECanMOTORegs->MOTO0 = 550000; + ECanMOTORegs->MOTO1 = 550000; + + ECanRegs->CANTOC.all = 1; + ECanRegs->CANTOS.all = 0; // clear all time-out flags + ECanRegs->CANTSC = 0; // clear time-out counter + + ECanShadow.CANGIM.all = 0; + + ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1 + ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0. + ECanShadow.CANGIM.bit.I0EN = 1; + + ECanShadow.CANGIM.bit.MTOM = 1; + ECanShadow.CANGIM.bit.I1EN = 1; + ECanShadow.CANGIM.bit.GIL = 1; + ECanRegs->CANGIM.all = ECanShadow.CANGIM.all; + + if(!Port) + { + PieVectTable.ECAN0INTA = &CANa_handler; + PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6 + PieVectTable.ECAN1INTA = &CANa_reset_err; + PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6 + } + else + { + PieVectTable.ECAN0INTB = &CANb_handler; + PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6 + PieVectTable.ECAN1INTB = &CANb_reset_err; + PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6 + } + IER |= M_INT9; // Enable CPU INT + + EDIS; + +// çàâåðøèëè íàñòðîéêó CAN àùèêîâ + + MessageReceivedCount = 0; + ErrorCount = 0; + CanTimeOutErrorTR=0; + MessageTransivedCount=0; +} + +void CAN_send(int Port, int data[], int Addr) +{ + unsigned long hiword,loword; + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + + if(!Port) + { + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + } + else + { +#ifdef TUBER + ECanRegs = &ECanbRegs; + ECanMboxes = &ECanbMboxes; +#endif + } + + if(wait) + if(!(ECanRegs->CANTA.all & 1)) + if(!(ECanRegs->CANAA.all & 1)) + return; + + ECanRegs->CANTA.all = 1; + ECanRegs->CANAA.all = 1; + + hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 | + ((((Uint32)data[Addr ]) & 0xffff) ); + loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)| + ((((Uint32)data[Addr+2]) & 0xffff) ); + + ECanMboxes->MBOX0.MDH.all = hiword; + ECanMboxes->MBOX0.MDL.all = loword; + + EALLOW; + ECanRegs->CANTSC = 0; // clear time-out counter + EDIS; + + ECanRegs->CANTRS.all = 1; // çàïóñòèòü ïåðåäà÷ó + + wait=1; + + if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1; + if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1; + if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1; +// led1_toggle(); +} + + +void Handlai(volatile struct MBOX * ECanMbox) +{ + unsigned int adr; + unsigned int bit[3]; + unsigned long hiword,loword; + int Data[3]; + + hiword = ECanMbox->MDH.all; + loword = ECanMbox->MDL.all; + + adr = (hiword >> 16); + + bit[0] = adr & 0x8000; + bit[1] = adr & 0x4000; + bit[2] = adr & 0x2000; + + adr &= 0x1fff; + + Data[0] = (hiword ) & 0xffff; + Data[1] = (loword>>16) & 0xffff; + Data[2] = (loword ) & 0xffff; + + if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++; + if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++; + if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2]; + + if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1; + else + led2_toggle(); +} + +interrupt void CANa_handler(void) +{ + unsigned long mask=1; + int box; + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + box = ECanaRegs.CANGIF0.bit.MIV0; + mask <<= box; + ECanaRegs.CANRMP.all = mask; + + Handlai(&ECanaMboxes.MBOX0 + box); + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void CANa_reset_err(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + ECanaRegs.CANTRR.all = 1; + CanTimeOutErrorTR++; + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void CANb_handler(void) +{ +#ifdef TUBER + unsigned long mask=1; + int box; + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + box = ECanbRegs.CANGIF0.bit.MIV0; + mask <<= box; + ECanbRegs.CANRMP.all = mask; + + Handlai(&ECanbMboxes.MBOX0 + box); + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +#endif +} + +interrupt void CANb_reset_err(void) +{ +#ifdef TUBER + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + ECanbRegs.CANTRR.all = 1; + CanTimeOutErrorTR++; + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +#endif +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/ecan.h b/ecan.h new file mode 100644 index 0000000..b9bd676 --- /dev/null +++ b/ecan.h @@ -0,0 +1,3 @@ +void Init_Can(int Port, int DevNum); +void CAN_send(int Port, int data[], int Addr); +extern int CAN_input_data[]; diff --git a/filter_bat2.c b/filter_bat2.c new file mode 100644 index 0000000..a577836 --- /dev/null +++ b/filter_bat2.c @@ -0,0 +1,19 @@ +#include "filter_bat2.h" + +float filterbat(FILTERBAT *b, float InpVarCurr) +{ + float y; + + y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) + + (b->k_1 * b->u_0) + (b->k_2 * b->u_1); + + b->u_1=b->u_0; + b->u_0=y; + b->i_1=b->i_0; + b->i_0=InpVarCurr; + + return y; +} + + + diff --git a/filter_bat2.h b/filter_bat2.h new file mode 100644 index 0000000..a9ed52d --- /dev/null +++ b/filter_bat2.h @@ -0,0 +1,49 @@ +#ifndef _FILTER_BAT2 +#define _FILTER_BAT2 + +#ifdef __cplusplus + extern "C" { +#endif + +#define K1_FILTER_BATTER2_1HZ 0.0000096 +#define K2_FILTER_BATTER2_1HZ 1.94468056 +#define K3_FILTER_BATTER2_1HZ -0.94471895 + +#define K1_FILTER_BATTER2_3HZ 0.00008766 +#define K2_FILTER_BATTER2_3HZ 1.97347532 +#define K3_FILTER_BATTER2_3HZ -0.97382594 + +#define K1_FILTER_BATTER2_5HZ 0.00024135 +#define K2_FILTER_BATTER2_5HZ 1.95581276 +#define K3_FILTER_BATTER2_5HZ -0.95677816 + +#define K1_FILTER_BATTER2_10HZ 0.00094411 +#define K2_FILTER_BATTER2_10HZ 1.91126422 +#define K3_FILTER_BATTER2_10HZ -0.91504065 + +typedef struct { float k_0; + float k_1; + float k_2; + float i_0; + float i_1; + float i_2; + float u_0; + float u_1; + float u_2; + } FILTERBAT; + + +#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \ + K2_FILTER_BATTER2_5HZ, \ + K3_FILTER_BATTER2_5HZ, \ + 0,0,0,0,0,0} + +float filterbat(FILTERBAT *b, float InpVarCurr); + + +#ifdef __cplusplus + } +#endif + +#endif /* _FILTER_BAT2 */ + diff --git a/i2c.c b/i2c.c new file mode 100644 index 0000000..c39b484 --- /dev/null +++ b/i2c.c @@ -0,0 +1,142 @@ +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "i2c.h" // Device Headerfile and Examples Include File + +void InitI2CGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + +/* Configure SCI pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be I2C functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation + + EDIS; +} + + +void I2CA_Init(void) +{ + InitI2CGpio(); + +// Initialize I2C + I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code + + I2caRegs.I2CMDR.bit.IRS = 0; // IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). + #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) + #endif + #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) + #endif + + I2caRegs.I2CCLKL = 10; // NOTE: must be non zero + I2caRegs.I2CCLKH = 5; // NOTE: must be non zero + + I2caRegs.I2CMDR.all = 0x0000; + + I2caRegs.I2CMDR.bit.MST = 1; + + I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset + // Stop I2C when suspended + return; +} + + +Uint16 I2CA_WriteData(unsigned int Addr, int Data) +{ + +// Wait until the STP bit is cleared from any previous master communication. +// Clearing of this bit by the module is delayed until after the SCD bit is +// set. If this bit is not checked prior to initiating a new message, the +// I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + +// Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + +// Setup number of bytes to send +// MsgBuffer + Address + I2caRegs.I2CCNT = 4; + +// Send start as master transmitter + I2caRegs.I2CMDR.all = 0x6E20; + +// Setup data to send + I2caRegs.I2CDXR = (Addr*2)>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = (Addr*2); + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = Data>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = Data; + while(!I2caRegs.I2CSTR.bit.XRDY); + while(I2caRegs.I2CMDR.bit.STP == 1); + while(I2caRegs.I2CSTR.bit.BB == 1); + + return I2C_SUCCESS; +} + + +int I2CA_ReadData(unsigned int Addr) +{ + WORDE data; + +// Wait until the STP bit is cleared from any previous master communication. +// Clearing of this bit by the module is delayed until after the SCD bit is +// set. If this bit is not checked prior to initiating a new message, the +// I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + +// Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + + I2caRegs.I2CCNT = 2; + I2caRegs.I2CMDR.all = 0x6E20; // Send data to setup EEPROM address 0x6620 + I2caRegs.I2CDXR = (Addr*2)>>8; + while(!I2caRegs.I2CSTR.bit.XRDY); + I2caRegs.I2CDXR = (Addr*2); + while(I2caRegs.I2CMDR.bit.STP == 1); + + I2caRegs.I2CCNT = 2; + I2caRegs.I2CMDR.all = 0x6C20; // Send restart as master receiver + + while(!I2caRegs.I2CSTR.bit.RRDY); + data.byt.byte_1 = I2caRegs.I2CDRR; + while(!I2caRegs.I2CSTR.bit.RRDY); + data.byt.byte_0 = I2caRegs.I2CDRR; + + return data.all; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/i2c.h b/i2c.h new file mode 100644 index 0000000..d358a9e --- /dev/null +++ b/i2c.h @@ -0,0 +1,4 @@ +void I2CA_Init(void); +Uint16 I2CA_WriteData(unsigned int Addr, int Data); +int I2CA_ReadData(unsigned int Addr); + diff --git a/ice.CS_/FILE.CDX b/ice.CS_/FILE.CDX new file mode 100644 index 0000000000000000000000000000000000000000..43d793225769fe50d51aedf071f42f55862c4785 GIT binary patch literal 3072 zcmeH|$x>5c5QV>xfY&G_C?Lob0WnOGc^+;;ZU_iLyW(2U&Lxk~Z${q3jgP<^#8?tx z>6Tl!H~;yodUMX#T}?o@>REoJx}W5YcLFK?piXedoAQ6S%Rcl3{744kA&wZU6ao2; zzkpif>s2K(N{#DgsZfnBqh?esF2vY-V(oDP>CO#k-`CGnyA8QqK9fn4dEAxgcqMSZ z_1~K1H1&V{TOHNq-#G+5+@$%Q;ieb$p=T&S&rue=Krc~08bCReM}z1UdX0wAFd9K` z&?p*1Z_zlKK$B<+O``&Ohi1?$HizD0^XLOsL<`s=TEdpm3RXfNu~oE&t)mTW6K!GJ zXb0Oxd)PiYzz)$7c8pH25S6hCI>oA3gw@a)R>z(?M-RWWJpAm}-ta5G^iO`_=U(?S yuX*HEKlO^2Jv=!+Iy~6l+uhmT+T2)QTP-aw7U$%R&l*?7iAQA;BcOoUAJYOD?J;$!@uDNKcq&s(} z+wHQyI=1`YpTGU-{q1)9dix!puh%#D`R@MaW-|+EWe0x|wZs%ee43xT<8eh-ethr`Wf>IB_%KI;_Op)8N5Z+gZCS^-|&%JUX}5!BZ9G{ZcMF7_rVKs73-cm=0}=IgH?HI z#go0#(iczmiX2zICVNHni@12Q*NPM33gTP_FDj}n(&NcqBl_n#K1dHjSjIKkmxzAh zYqCc$ORLGgtl9Hq54o)3lF8oI>><5#L7+=tlf6as&rf@lTe^d&7)d@;j!gE}*H%;a zHL7FbYqGD<{VJ}>zS`Q?WMA<>w18e}$^})cj9No#quesbx{e-VKbNng*U8=y{US${ z#JPMOy-wY`gG7DG9))u*G_4&Spqu#7F{wAsBh<;h1=WSG$-Y(iGHYm>N2Q?yq13R~ zXkxi3P%d+v?0aZ+vE$TzhgKK7vS*JhJG8p8n(RBGN9VOd?TEgbVU)lJ3i@2#cV_fR z@qSJiZG>}!)nwlrNNCm4xg9;HDWgNeYO?P!JKSowddwk#Q4j3pV$TE;hRyi0vLXfb z2dj%c6UQ7Pa?p>fm{z503NQtWOAs>&tXgHMW5OsgA;(BBC(dD|YpaVrsw{Z*LYRF4 zN$KK+MsqB<$3#|9Aj+#@RV-y{7kixa4ohu@93mLZ?M|GD zHEM)p7keBuPTK?<_Jchf6Y39E7kel^;^Km_O!4evT$4RhSZQ^08avMDCwmO89mhy$ z6G;)#s}M&bcJ&-)u=j?O<8sVeZWyS6$}ZhAD|X~k(REJc6fLP7w8>*J2A5Fd(hP#Z z#n`do4`1tKkHNLHn(QGx?nY#gYCL-=C(=z};6IeZU|*{x@3AA^iy)t{n(P_6cXsp- zytv?&l5mquH{Vsl6?~y%E_yT?^RYNY1r#0n%-)9_A+%IZo$T>8w3nDec+)$g$6H#W ziuOHL^fQzXF)AnJqSR`GDsj6`_83Wf!xqg6B1)0|u0L1Axa1U9RZqt}RVoIy25)*}@!9}FVb==h~siVXx8#nxQzAs5h zd>ZMv1WVJT_VwfUJNVGSVDNJ=7`%YL|Kp#?z&(ia{%ddO3>F0syzq1!c+@KD2v$zP zLoZx#QP>ekcv1_ZxX3&MgMz1CNY^q?A`<5Y#t`TT6g&b#PWO+D+2~pk=(D$imtMHp z_lMzlKJ$-9qw9!@G!^Tx5M@qT`|)W^EsNk1o=#XX60^Jr`I;tWtTA*SNbq%n!$Xjj zpLq&s#R(D)bb`}E%V?cg35^FMh%sA|GLh3F?-UgY`@KDk*=CZKo#`-pX9B0pB=oPv z`219z-gr3Fqj2USB~i?le9ej$gi-A21ZOQK0a>?mVJeKB3C7;qkudw7+B_WTQMmFj z0f3Q+9X)(x)+k*2!syA#HA%CiTZkr;Cw-$hOT>aCvs_3aZ?cAjQM}O!+iL0uL`}FL zIVX#R!7fpEDc069c1zS*#)Yj|{o8)(QyoyXT<^9AfKly=Fmxr#sMa}M7&iju!5}z} z!5L=(+#1RuSZ^GoVYbCGJZu^5A$SME1*1~QCPvY}7IVs#+1MUC5;8mCon8w^Cg)#f zITtyX{0ECW2fO`Mfc~n1CS6MynO4?-TjM?3u%vTjHcagwF7fs*Q9xmqXP5`Ie_9)p09qRg4jZ#;Aa8ow(j3UYZXp%yp^8KGB5 zunXYnp0S)~D`q~-t1!C)1JR`V)BNE0&=O>wYN$mmFs8R*78x&?pII2V1SD!JFc~O- zT1ZwXtqPwuqcJIkfYZpPVR1ZZg1Z+voo`MOK25}9?fcmcPbP;`7iz7-UAgv zB-HU?Fm=n5GOYUFBLDyHftsO%jjtK{3?EiFrf@>R*rCP#Y}0+O zHoN+-Yp-E_ySC{%YDJ8TZux&|(!rwNTIZsTTST8#%OhZhrXhApbuU-tv5v z#YulJ-TlAg|KI!KfBlcv(f)tyP*9lPA>IabZj+MSxlMA%PXCPw{@0^l?E9^(`uCIn z#{YlsivRgP>Vzr2W1TQEFE2O0gW-Sg;X^ux4uxa$a@*|LCZ$c+;rU(L#Gj>>c$QY; zS$c_QnI)d(bo_4y;s1O=>R#>dP5iI^|Gg{z=l`e@+WC%E!tl|<^!}s&|8Lgse?ID4 zf5D2%z~=bl;tHELhfud}y-JlThDwpqVW<^Cy`<16gl3W9;(w3-t9u|?fhQF9>OZh= zZogrX>HOXkBHj4hF@^Eoy*J}Ceg2BSHKAa5QkWi%e`ph#4cxrBZs^gYQI#r{BC|qC zp-sh#RH8Cfs7f`eQ-hk+qBeD?OFin-fQB@pF->SnGn&(amb79AcBD0J*on5Zqdhyb z3%k;Rj_gKfx{^#P>12}4?sR7_deWP|^rJrm8O#udGK}HmF@k&wC}bp~7|j^QGLF3& z&pzzS1SYZ{`*Q%3IFQLqVJZhPje|La>CE6zW-^P}9LC|yVJ=57k0UvXqdA6S5wdbW zBJmG9TCHu#_|Ny!aq?Wi@tnYkoWxn2!{uDX4cyFa+`+v(z#}}$6FkjxyvXak#V35u zSA5G4{7jPy;!FoRvKyV~Oc%P+jU2kugWlvafWZu71cmI)MD}BU4qy@oGMOn%x;jA1e7u!M72$}-O5e3o+oE4Yx0xR^`0l$Bh@pc-wM(AtNW4Zz~aaMesUWr&rytK3}YF`-i&7-_GJPS*^m7>fJq$4WTr5cgP6v_ z9Kv*Fa40jG#cU4aaONuFLKXFzw(Lx2 zx{*p2d$1RM=+6+QGn+Y_$6dU_tB7K`AJO=$`(d||@qevK2(QcY4c_D}-sTL#OUA!% zwGeXU*^mAVU?77S%n*h$jN#-lf_w@nWF(^)%^1cqj=dSrKJ3c`CbA#LRG3!of_1n7PYBEUFuPv1~jA*jcGztn$esVw4@a~up_N$!%noN9qrkfUD%Zl zY2Q$Qgj8O3PEFqU!b&3N`*W}sU_?GdFuc9%G7c$U9yYq*x{xSkuhk(;=gTUf=d+{W#!<__-UF7D^DygPJvc zHuY)54z!^Io#@V<>_rcH(u>~op)a}gqdx-}$RGwYgrN*$IC+d9p8^UQ$tcPY?yVMy z#y?W`(@VyGbj=XP$a5^?*qia}!@f*lBKxsF2QY~PnamWXauCxvm_wM(;mlzkM>C(} zIf+v_oika^gWIQ@|*u zFpZ;`&)F>D3a;iZ?&V1~@;2}BJwH*kwtfID*^zFf(uaNwW*D=W&0!qQ9OiN)$8ZX# zaW3a^CD-r>YgxymtY-sT1-A?@MB}gShs=`kf2?*0kIVB3p5!T>W+TtAiD${LW4}?z zcqTBFgPF}7=5su!a2jWE4lB5rtGSL_xQ(@}<5AYLflWNm8@$bXe8?Ak%}@NwW|Hda zk5QABv|_#U#(}k{dBbgLZNh6&MGRY#F9Cl|9y0a&H z(Sx4!qBni$OD_HB&j1E8h`|hDD8m>|9wW%7fI>!6hH!7SNHqTHe#kBv|50^A7%k5+ zjAa~qGoF3emkCT{KlbMUCUGE>nZi^KVj2f?2-BItq0D3!vpI~znZsO;U>-+u6i0Im z$1cEYI;gFYqES@iMRQDzEW6 zZ}28>@iy=9F7NR^AMha`@iCw9DWCB^_>Qi;k`p(@p=P7P{Oi`vwoF7>ES0~*qZ#x$WR&1g;wTGEOg*pb$>VJF(s zj`r-#F6>GNIp)i9LEBV=LAmVBu?fO zPGupdaXM$Ph%-5hvsuhJEa6<1vW)XMpXFS@3NGX#whC?;UWmqD-4A<}jQ_>re~COV zWhIw!IahEcS8+Aha4pwyJvVS8H*qt!u!>u`joVqx9o)%X+|51Q%YEF>13bt>tl?oE zVJ+);l=W=jF&^g$p5!T>W+TtAiD!9^=Xrq_d5M>Kg;#lv*Lj0Cd5gDshj)38_xXSi z`G}ACgira5&-sEc`HHXkhHv?f@A-ir`H7$Tg_g0HUvz-t?g_x%8ty z0~p941~Y`A3}ZNXj3A!^3K_{LMl*)7jAL)cvk&_+fr;$L{v5z04rDS@n94y+<6sV9 zIx{$wnapA~hjBP_n9EkdEz=7odd>ZX-ep>NtA%Qg3Ss-Ej%sfRkx7T`c+?#kBE!|~ zc+`C)I?&mUHS2YYc9FMd&5NR)tL<2`zB!mk)hz#`{@iGTUWOH;^*ilaG(W0}u!EZ}%f;6zU1WKQ8!7IGS=a|Vkzle0LR#hk+u&SfdfIFIvL&IPRC zLN4NBF5yyEav7I%1y^zvS91;5avj%m12=LLH**WCxRu+uoz>jIo!rIU+{3-x$NfCO zgFM6<9_A6&vW`bt&judjah~8wp5kdX@(i1Jmgjh$7kH7Ec$rstmDhNkH+Yk`c$;^4 zm-l#|GK71pMWXSK)ct-X_}_cuoG=*M|*Z=7j~rs9odaebfybk=|(asq>@HD8Dx@0HaYCh9&~3<_M!(p=|yk) z(3f2L(VqbfWDtWH!cc}WoIJJ)ZW&&P#$VkJ14_n!M1v6WBN@eL#xRy~?9F)g zVP7UNk^R`81DM2tOlAsGIf!W-%ppu?28S|}SLbO2+>| z@qb93Yj~JPSj##dWjz~sjK_I`CwYpe*~l|&;#r>Kd0yZ}UgBk5;Z84j-r{ZE z;a%S2eLmnrKH_6O;Zr{2bH3n9zT#`X;ak4rdw$?Ye&T0-;a7g+cmCi{{$ewsp>~NR zDpHBcRG})>s7?)PQj6Nup)U2PPXij#h{iObDa~k33tG~O9oUi9v|%UO(vJ4*%r5Lo z2RgDFTLrfaFGS<7?uQ{IfVIG-|vd#gpF@mKf5u#)j#F8&wDa|IW25f^g_m$H(}xST7v zlB>9yYq*x{xSkuhk(;=gTUf=d+{W#!<__-UF7D_#U#(}k{dBbgLZNh6&MGRY#F9Cl|9y0a&H(Sx4!qBni$OD_HB&j1E8h`|hD zD8m>|9wW%7fI>zxiqVW=EaTXl@$AFCOkg7Wu|Eeei36F;6sB?z(>Rzzn9d9iWhS#I zL%6qEBpQEpKjfE;|7`I;OrD1`hq)ZVJdWfjj^-GSWj@ETfa5uV6FG^KIfYYM$Z4F; z87$&V&f;tqa}G;5m!&M@JkDo17qEg0xrmFogiBe;Wn9h`T**~j%{5%hbzIL4+{jJb z%q^_qR&L{VR&xh;au;`V5BG8(_wxV`@(^oym`7O4Iv!;`8+eSzd4eZ-il^DgGi>5n zp5u95;6+~IWnSS`UgLG%;7#6QtKgRD1@k{WEm&Blg|}L${`=cIb<{wM6B&4v|Iy%q z=y0|CD~5(Hr-^iS%KvD1ezc2R{uM)`O3}{M_N+N8dRX3`HQ$Oh=w(i(FL@gLGSgrV{r#&Gf&K|Tc(GLlh@W(;E)$KH%*ANFMe6WNdb zIeCvh^T za4HKqjng@UMV!f5oXuj+VF~B5lx3X9`7GxGR&XH~aWR*0DJ!{*%ejIpxr(c~hHJTw z>$!m&xrv*(g;m_jZQRak?%+=D;%>GIZW&&P#$VkJ<4VT=9`V0dp7(J-5AYxlv4)3v zgte^WQP#78$9SA4c#@}hnvFceCZ6Rvp63N#3Ockn9 zjq22(Cbg(d9qLk#`ZS;+jc800n$nEsw4f!e*nu5sO&fNiE$wK}&XghCTP+fezq%jB zmyG`|O+wgJo*n4OZgiqEUFb?Tl1U+zG}6f+lPt2yVR!bRJA1MhJ?KdCE6zW-^P}9LC|yVJ=57k0UvXqdA6Sna^=7;CN2pL{8#lPT^D*avG;|28%e8vpAc@ zoWl~f3T_!*h{j*t5Brvk|GDD7RG!N?kMmj11+3sgF5+S?;Zjy|8JBYfS8^3sa}C#W z9oKUMH*ymfJj5Cv<`LGijz?L~1|H*ap5RHI z;%PSW44ZhC=XjnMc#)TQnOAs~*La;bc$2qyn|FAZ_jsQV_>hnIm{0hW&-k1#_>!;q zns4})@A#e{_>rIZnP2#o-}s$B_>;fbOc}zx)gsaOtNUSM$@qt+AyjCpjiVx!s7w{A zQjO}=peD7bO&#h|kNPyAA&qEE6PnVD=Cq(Ct=NGbX-yk;qAl%c&(7?^u5_RyyU~fx zbfGKVNG63;(nu$ROtQ!(huztO?(E54^q?ob=uIE`l1o4OGk}2%VlYD($}onL#|ZK% zppcP_Vl-nI%Q*ICJo~UO6PU<;?9TyA;y@-dg{d6GG!EtvwhC?;UWmqD-4FYhjQ@1; zpCQjfnaM0>a~Ov+hq)ZVJdWfjj^-GSWj@ETfa5uV6FG^KIfYYM$Z4F;87$&V&f;tq za}G;5m!&M@JkDo17qEg0xrmFogiBe;Wn9h`T**~j%{5%hbzIL4+{jJb%q^_qR&L{V zR&xh;au;`V5BG8(_wxV`@(^oym`7O4Iv!;`8+eSzd4eZ-il^DgGi>5np5u95;6+~I zWnSS`$`J0Y7Kz4xqL(L?jQ?xm|GGTi;7#7*ZQkKs-s62f;6py*V?N&sVeK%@R zpGGvN6&=})PIRUVUFk+LDWsA{IvHfLRdCDng83hFe_?W&7T#*1#)CuHzNw?ecZU!e zc$ELqWasE`wfrlFCQG6No$Xn3bF_=R9cwl{B-**!o;CgEY~psT7ee#QXoFscb))rP z+aIQutp8cfL&#R9a@d_c=+2((MGtz?i{A91FS+!iKLZ%ZAO3%tlnyv!@S%4@vN8@$O|yv;kj z%X@sxCw$6he9jkq$ya>MH+;)?e9sU3$WQ#tFZ{}H{LUZz$zN zYE-8NHK|2y>QI+@)TaTBX+l$)(VP~vq!l}`BdysgxMg@D8h>>^Xr+qJ|E9DEAyuB; z*^|BKK~H+on?CdZXvQ#>aqP`__F-QpFp>S( zp97f0flOu!Q#puf9Lyn1X9kBdlUdB>Fb-!9b2)-}9LZ4}%`qIye2!xQ$8!QFat=#4 zm!&M@JkDo17qEg0xrmFogiBe;Wn9h`T**~j%{5%hbzIL4+{jJb%q^_qR&L{V$`J0Y z7Kz4R-48QL#(%Z=-yzRCxr@8GhkLn?`+0x|d5ASU%p@Fs8ZHt+B*@9{n#@F5@ZF`w`$pYb_g@FidIHQ(?p z-|;;^@FPF*Gr#aFzwtYN@F&e%s*kj!6+5sat!cwfw51*G*_mC~l@4@dH#*UoE_9_E z$)u1<8tG(^Nfz1UuseIORdCDjLNxyBewbM@{@q)Ku%|rtq6afVIG^QQzzQzp zA};0R?oIg7J7+A_yTk7Yi`v4G<_fw4&|!#L^QjAtMA zWdaikAuT1H-!+1K3MgbGqZmz2i=JV3 z%kDv$c1(6!Rz`AWN=}&;4(S=$8QJNX$r)u^JUi1~FUun>JtreAH8U$M693qfMC<-t zVsgq_YLg;A{!#bC+z{#&i+`Hqf4Y5@K_*#b^S*ukf&KX*A90fSo$U2fIF*H*#_62F zBF^M2&So*=Teb=NsL%VdpTGB)9>63HWHO!H8>WkUfp#N>G&0B{hdtPn9`vFQx%_jd zW@Myhrlh5%l`)PXEh8m0J3A{i{ht|a<9TXoMtVk$@NeV&f4(f7J|QcujLT;yr)H#N zWu;-4NXxEUFd5)*%tuoRpBG4~hdmB^^fPnzGjy;DamT1O`x%KS-N7Hn~Q zbhx_Zg);xua*yahr_9T5S+M1uk;7#9>zAYI#7F~M#$asuK!3HcwX>~R-ZE^}+z@Hd z%kW4FidJONqeApfP(}BD9^j=x>eKb==MC!Pjoie|{MDjO*sLB0e^(%hid3R9Rj5ie zs#AlS)S@z{KwsWfw`KnPp~2n&()?*~uxz-~Y$oIcdo$YIH^!t8>W8 zO3q5jNl#6bXYr4ySRpgp)+Fa7C;EED*GP)o_%%}Zk5S%=wg35!{{{BlAp3i;G>;J! zGLlj3uJ5#mv^#sU7d_}nFM895zU0!6{tRFsY2ubHz1qiLqpV%ab&)d1jbUZDNqT2U z4tGiK<{pY~d&$513@FGQQjj|$WkT}^p>TVMLL#cDK&}9RPoIy$}cM?(ibgD-bukkpSmCB zhtRB8{O|M9{r2~RVO4lYx`u~Y8#aY?()C{7AbpI-dD81oNjG}^8R;gT<$15aAiYH# zS4nT>c7Lsw7T@yXe{Ts*YIcIq4DB_>ee6dS4|huDwwI6Onx3APk(rXd?aH4X%PqE? zdQ^O~iv7JMuhebV<+S2?rDi26i1E)$-)22eE%7b4S^5;#E!AMlZq(r@w(%wYOp4t6 zUEL20f`9B`%l-eq^V0WX^rKk)B>h7CzLb8gUVbBe+w*s%@A4k+^8p|75g+qum>52j zo^07uq^Giw(>R?oSj3r}Z37ldi*H=y3&iVNR^t9xVg8VKwT~~Klc0V&-zDRWERUSz z$;t72Ja=VWX%NX54}Q4tT~KfGVR!u)|l zOXR%GvKJZi`&4y5oDf2%V)0+%rE|q&Da$yI^I6UXtl&Z};$kl0QdV*qSBU48(wCHh zm!+@pDzEW|_uiELqFnqc{f*!GgFpF;&4dd27bH=UN>ru_RjEdGYEY9})TRz~sYiVp z(2zzn##bxrV}f`V#L7x`PEO)ND9>WiFJ<8pjYE27!ozhW*I2pE$VpDP<>Id@#2bs) zD(Q)bKGEa<0-2r^LhWMlZ(70ez`klu3tG~O9oUi9v|%UO(vJ4*%q~o=S}z>re#z4~ zr0Rk&U0P5zITT7qGK$fRVJv%BofyVT_pRC{Ops1wKlbMU4y-yeOqSZxEsw~KNli)1 zPR{gSg4$z^f`0jZVs#?ELRLz`U0E#ath7=_^@Z_z9M3r;apMy$Bq^!sSvl$1nTc~A z(Pyj8&P+IR6n`bQVC0a(2}1|w=MT@1mEWwCl$@MMzi`X0EBY%ba^q)pUjyy2rTy<< zPj_@b^-hlbouzFnP7Lj&J6Bv4c9AAm3L(Y4(NjqyoeVO`BAXm`XAiowCwtL@p7f$O zedtRr{pimC1~Q1j3}Gn47|w`F6GOiAwMxn1b!qRycz9EiQ_^y>Gjq~PJpyE=W~Zd2 zBxh{vz#Q2jkw>3i!+Q0Km7O%P&C1A3oOi4lNLT%GGBUINWuM2gRVD|H%Z=q5TR1y; z+YL;lJjR#G+IC~ndt|=jRiEJ_hsBRtu~o9R*$dYG`$>$t9~MToYD@gz5Z^cL*SC0^ zcX+ST%<#VSL;L(A>BoG+r+miee8HD|#n*hpw|vL<{J@X=EPlU8*U0N(=_9P=QJ=A1 zTCH-=P~AQ9YfzI~)TRz~sYiVV_DhcKLen;>>8YvqdC~6umo%~$v$L~P9Ly8eBdhlB z6+ec?mrqTUZ!F{~=37#e(=$q&49YEtZ*pw;%#_3>FtX9{tW5;|%eUI{lA>D9iVzv~ zN9O**>A_4xeAH6rfwKOC@;xuo@7U7sEYtAIC*Bhocv!QjA0PRi@lji%Zof5GN4l)B zV_iz5g)3t((VB}Rot;=KS)Sv12o)Mfy2!moL>uJDN0#xp6GGL=kp^~qB2(%0NY%7v z|MHdc5GvP?H|V}{;zv^G7+Z8v2sMk<{|1#qXsCWQqDkcip{cZU<%yw-v@6|6CWTbe zNGF3#vdCt4>+T_KUO6wckhY{1JFp|IX~Rymr5)|rnO)eGj+JMI-J~k`zqCs{7%r;7q`l_W!UdrUmWe$F$FnYmcAc zNuJ_qHu4Occ$VjQo)>tLm$mP&NPAT28G6d67rp6QWoF2g_M^MM_mrkp$qVVy3^Mtb zfF*cI=WA?Xt_h!HCq2?r(-XGSqlf4BEn3vsodnrNyJ@jJlM{ELL+Cr8#5SZPE>h8O zMtdn)$qD8wqT4n!-m8fng#16z7Du}(k(vH%8Gg6GJU_xxq>UXimSPXYq^f=xq%zGiJQ5FRou#L+|Fw5;7;!1Ztme; z?&E$Q;6WbZ;ffQ(Bhq6k_6)~L=W`qjIGz(Yk&`%?Q#h4{oW|*#!6MG&EY4;z=dgrx zS;{ivowJnejMVJ($ZTR{7j5$q+3Be%{>x5F%}!VdLx>;$bF!5H-G#(ajg{GyEa#1M zSrayF>i^KbL!$AI72TAagzZH<{_1{M68U0V>i>Ca;raH#axP#67jkjMiQy9Ie)?zo zYm*OP5(hGwDNN-crg1QbFr673%1mZ4o5MJqIn3n<=5ZuPaWuzpEb}>z1)SiRaH4ci z$CbULJ?Kd72nL&g3l4W-;fmgmYQSGC~-hS2O~QMIk*UVbPE7)@Yqd+xE0;G+KS* zwKckMMoOY_WwA^Xb?OWHN2Y0tXPcg&4TxqMFDjXdK0Vt04=tMeODR*aO$u_1)cx~H z&i|b!{^#4T%ejCRT*yUS%q3jPN-pDauHZ_pRxYlQRuI=DX+$!m&xrv*(g;m_jZQRak?%+=D;%@HYUhX3j(K0^z<;5Zt zKlYX~^Bav)d_Y%9^PitvR8r&1CoX`|oTC>4WSZPaxbfz1su-_oXAO>%qg78LQdm!&R`K| zau#Q^m~&Xdxh!QF=W#w4m?u~vEv%FmMoLF9nlX%J9D6gKeb|=?#A8}C_mi+UA8pfP z(a$MmdNB-*SLbNP$vKIe^w_~77SiOzr#1!-FDfhX#S_k3h=0Cf8!0jI?M_YHU}*FA zh}QkEB7`Qz;y+RR_p`tD=Kv;gAd{KGR1RVq2XhG1nZcpVWEQhIj5*>pS6a(>qPDaS zb*V>v8qknNG^PnnX-0Ee(2`c{z>c)04Li}6cC=?_c41dK(2?EfL>J?duF~I>-`}Nw z@b6XXpOrN6K|Qj|W3z+CApf4>->(+NXA@J?(p)oUBKYrj{`HSY*70JMQ%cs6_zx{t z5s%LQMCSf3`g`;coxdsDI68zXvm(RCNWVkBvm664Ybu$Gwxh>lo@!ZSxElG)@*V5U zixfl#I@T;_D``!ixg@e?q<%&BP}vR(AyjfIeQ9*f@iSA5Mke9L!y&ky{_PyEa;{K{|q z&L8~AUu-5QvlU39B9*926{=F*aj1rLow?99YvFn%^ECp9NCC#95pqix0TqOC4d5l;%HDk63N@{;}k zryUhH+6T|DiD!9^=Xrq_d5M>Kg;#lv*Lj0Cd5gDshj)38_xZ5m%3je zQb{A73^K_gn;dp$54y7_d(nfQ^rAO?=u0lISEv`>s9-xPEC_E)O9mm~vq&(r($j?} zEphz`LwXey42%yEqif`pauN7|NcXIu=wx1kabM8}Mz$qdQk;1#dTkqNr2gj@#lK9Y zHYw~Ht^481lIQ<_uNuN1&bR+kbyfIP+OKMI=r0|>Kn5|GAq-_0c~xhI5z_CI>V+R% z*Y_ho@iV{hE5GqOfAA-Nv6&!V6-c5|#RZ|Vbfox=61UNeVJzb)@#XVI77iSm8$Z#V zmgADY9GBvkSfu2WXg$p~JD~kd+?^V3XAUnKre`P#*)GK_nOVta(X5kGoP~6TF>$%+ z^Y=vqvE?(<6K!*Jz>txmXqn?qFr(XNXkM=g1M>4m51r6IfB49}3YqC<7P1xOk{i0^ zSv3CYez-b>ipARh@fAYY$G+Z|2^`X_UYPE_1v8l0Y-X4xJ*k;%|D~sJDhoM{(>a5~ zn)M8aOXo0`BbdjL9L3Qb!?DcgI2Ld`Cvd1TI8%9=#cU3*Ix)VCMkRNR)$xl?^Z|-?@8b113u&?yI&J>hmMSGO=_|$t6eOTFk+D{ zi5)f)cGJSBfqioO4C@ygNW_jB35(g5Z|F2Yf+Ev5xA(|mbBnRBn4D-LG%2)<*8OmO zC{h0hi2p$G7{p+PFqB~oCyx>2Q$Qid)T|ed_3x}6S2Hgxkj|}{9FCA4>G@I8h2B3+ zdWPqVq$ha)M5!+nzhuqjxvs{}NOUD+^xH@FhYNX=lT))2&z(h<9+MwG*&53|y|i;~ z(Ha_GHu0Q)B=-_qo?hAjy?EZGRDOBq|6|KD62(5UF@1;jDrenEiu}V5>VCK}vi_Fw z-^u>{-&4e9Xq6C#nWG<09wW%7fI>zxiqVW=EaTXl@$AFCOkg7Wu|Eeei36F;6sB?z z(>Rzzs8A&@BuOh$iON)=D%Ge?4Qf)0+SH*g^{7t+8q$cyG@&WYXif`S>ff|-Y}tVw zX-yk;qAl%c&(7?^u5=(e+2&x8mXT%B&!IoE8@K&XaCQB3=Ck|?WZR3y-pSRSn=rKZ z@G)D?ZkN)x>^mkuHBta76jh{BHYf5quKzLj7jBNu{}h&Q^k81(lgQLj`TLz(o2McJ zk3RAKb7Z5-*5P)XdOOl({rgxK-KS;g`B`&ZWT4YG+98O1Vp+QouHu;!bdk$nzkJXB zkp?yznb^!)8QVD5faV<^p>Xa-`*(owa9&uCWY<&Mcv#;Ip3~pu@-LkEZ&Okj(@a4FLjSZ zum6k`mD?hVZfXBN(C&YzUHpiT`GimTjL-RkFZqgZTp#kS^m}df57Hm`iJ$p}U-^yS z`GdbKzgb$LYMYRx4XsEeDpQ53RHHgIjVWtM>sYp~v>x?oKtuWs=^sCj8gGF!6ZYp~ zz3As(v9Z4b{YsBq~yg%2c5$)u>Jl zYEp~Z)S)i*s80hL(ul@1p()L1P77MniVv&R3m-{8<`X{UGd|}FzT_*u<{Q4{JHF=! ze&i>9<`;hDH-6_2{v^?U+SYp`a^sD&-;8EumEjHmk+FI7h*dN+PcWR1erWVK6))WX zb_IX&Ez9jw-ujRfc8JyeJ4;^w@r?Ly66I>f~UOqwDcAI zs8^-0@j7qtmiOM4-e|6Aik1_Zl{MbgzN&-$leT_ham$58f(`*1K57Dcip2r=J;xfunM_&Uu@I z?k#1!w5$33LZs*?f~kJ_rL&rz_~0h~D#ex$C_^Pm3XMWg_rtxxOz@WYFBaEx#O2&( zd10ya-ezsWebNV-Ee;P#&lAt{r5AXAh4doNFP2`yrL5#Ku4uL(Tq)gZ_x}3}(Vd=^ z?2^lLgZqD9CiZGUVXwlG@fIK@x`v;AB$`7lmUT)gzt9RHZ*;sG#j;LMNlSd-EnW=$ z{wTqQ7v^nMR?-qx(&C$)QreKQ-|)Pm0v?~e%qZpX621Ok-S=bf66gP}7XNF+?Yd^G z!u8T8{aeIORX6v?MxJ34&+;74^8zpO5-;-#uksqZ)yNB-YB(NLPY!Q-{uXcZ4)5|F z@ACm4@(~~N37_&ApVLJ?UFCD1e8QH=JeTpC^-oJr7^dj1%*k>Coh-L)Nf4vRTSZ+o zxAjR+@jHQpg)!DjyVy38cXDzm`#ki|>s8cAi)WuxO3NPI^rBYIAZ8nneg%bndyg$v zz+zP?L3xk<{#V@(4~DQyvHE|%ct2o&KggQu3&O+F?lqFbp7#A-^q?ob=uIE`l1o4O zGk}2%VlYD($}onL#|ZK%ppcP_Vl-nI%Q*ICd5xLj0_m64+k~%d&)0mzw|vL<{J@X= z#LxV~ul&aE{J}PM-alUMT{1*vIcZQKM;mQeQA$|}eR~zv(pZT}OG(&ihz37az|#_+ zR#LFaStpY8`XhBetSQ<5ORf<@ihcc;dbT;T&-`71Bq~yg%2c5$)u>JlYEp~Zq^Ymz z(zWtgC!a@I&tuBeTsW(S*6i0Im7ixnqlGd%! zCe)MGrvVLVL}QxJlx8%i1ubdC4(v##b|FjJM*ZJO+Lm^-XJ>X{S2~bm+1;h{Eqk1F z0k-(>y%KG8{g{5sxB9ogid743^uH}p?6sn!fApt6ewSTJZ=qP;rTm)1XY?sLu*5Sj zt-BD(JbIhC?6guYEZ>f@621OM-4E+a#{YQnKf!)Jk&`%?Q#h4{oW|*#!6MG&EY4;z z=dgrxS;{ib;}YfPQt4&N&*jo9Yb*{|Nw2BVGh8dZj_bLB8@Y*_xrJ5S%5B`vYVP1p z?&5Cl;a=`nW*(3}$V05bw^U~0XUJj~>*j3x$_S^Sqb|9rFL^Zt2#%2_L-^FQi-cr3URz?Sjf!{YyleYTc$ zJj!}D@EA|nzfVe^;%PSW44ZhC=cr-~QPtR?y6Z)1NIx@w__;ZQFZhzL&Fy|8ZP+4& zMv?o;mH9ESLWLaHW@Kc#flt|1itNPrWKL!&tK>T~AD>i?PogA_XRNE>ymgwRbSX7- zz`%mMKJg2PQ(~*QV_TxH5Gg9rA{Z~Q39kX`pEq#$gmRVfq|hc>_rnt<>;F#9|F(7h zw;k=-nO)eGjx`sA-K343$8RESN;8_%f|j&mN6WRAzNOuMTX}egcX^NZ`G61kSex*P z^c8KutJ2qNEQsupNXTM$^T_f8%*ZR-dK45**Tol4PZ))0zLA@Rq-45v=eF{UzCO@} zWwC>H?Dx7ZNlCPPG-sD2B>N$9;zLZ~n0UUirA-AU$Tym8T8_J#q@^XkQ_#TFKK=UT zm(1I(UlQaU9sjHQZr)a6{Qrjf|EIY9B_5jz;#h$sDpHBcRG})>s7?)P)tnh>OJ~&V z84i`sWEQhIjJmG-s3&b;xrWlue9q@S;|spzE57C%zU4c<=Lde|Cw?Xr6c&Xi7EZVI zNbpr-1u7n%QpW#z1w}u*iRYZ?IANYHa-DdF>xt5H5>EcawyszKbZgH72nL&g3l4W-;fm zgmYQSGHRKdtnK)da8DP#Iee=IIxF!teeoaMyR5@S7j77x_^twxkBPPC3Rbj6Z}TRD zMO#$7xRi1|lK7XiPDJnjrS6AKCENeHj@|X_vw`;AAn9O+FwC)hxO9Z~^QDEJkCYCm zQZEd&uLm)h;kE09yxNu{p8^UQ$tXrMhOvxeZ^p9^`!a!v?8p8bz$9#GpWX#U7er{m zlU<>isPVLdD`?_(he#>)3VMsjk38vVei)pcQOX4B&|Z0eU&!aaps`gF9?+xVj4zp* zsA)C}J+x1La{NFMTf^M~qFcC){|$+i-dKr=c1W@k&vH2b(=J-~!*kB}7VG~VSUZHt z_V*N~auCxvm_wM(3=U-`pVVv3nR z{gs&k@*2n>hSZ)JhD!hS%f`NAH2$UCpRHfNzx&(H_Nfw5Cs87s}t051~b)NSC$z$2y<+dSswe{#MeOKL=gpc>RiX31i*&QjQL0 zj?|>5!uCX__M}MF92zUWgt?|OyI0>F9b46>HkGGBEDp4@yzR$Us&|hviQ#r z5}*DN|H5(>$LRfE)cx>U$@!nQ`giS{O${qWheTOw0Ku7wy@9<`iJ)(AU zm?u4|_JVM<^jOd5OOIm#$8!QFauO$Vs&yAi6YRR;Z$-aoYK}|qT{Dt6l3V6-ik2_K zWI;6N{hZmrqg7i5m6jCa0%nB&X(-a z@Fs8ZHt+B*@9{n#@F5@ZF`w`$pYb_g@FidIHQ(?p-|;;^@FPF*Ga-!1?Nd0RuvhOP zxfL?qiP}$$5;YXX&MWx02qFc+yxzYBC-z#gGVb5A*!FVX$s3qEu;1SeT&%<-zGx^Z zjE~m+@J`9`-!J0-tMB$3zw-xw@)w&4b<78nL`5o5nJQGJ8r7*mO=?k_I@F~e^=Uvu z8qt_0G^H8MX+cX`u>(8Onl|i2TiVf{o!Nz5=|D$zqZ6I!LRY$xObV%_kxmAgWRXn{ zyR!$~*^|BKK~H+on?CdvKamMKh*v3Uhqr6E$4swIsW&zUB5O>4!`*~*?;E`{^Tz<6TDx6ispbS zN%Q?)yFmYNc!i!JPui$ro6y+r0-IKRCp43`sJI}sl(u3A{`EV@UW}ZfkA3s_O|Q3k zAw#5gl=eHvfy46$7LJXy)A568e1&cO5-^fy><2}DOP*jWV{hg6jsMuXY`;M&*~2ZR zw^*P*7e4`!p5-2JrQC!vFIr+^M}Sz5rL@bDlS2Ctsr%uB5E>MVe{0cE%PKCd7Q!;u z#-GReTu^O6SRtKTtzI}nI*%hcilaG(W0}u!Eck!yooAF)Mc1I~H26I9YL=X%F!Aw#VL=eTCz?>5bqF~Mm6#)@ZX5a2c;d_0%)ipn6)(mSs zY`FKFy64ocU2)egVYu8gLgY-j=QfeI3$ujT!X3gK;Z9+$Fi*Hkm@nKdEbvRzy(0fp z3&pn-e|tIFt$CGGsDEzdsJNqjWi7P)R#^#X)w)e{sY5HP%4J2lY|llxl4Sa?ct_8_O5Q;fEOUSA^Wy07pN<|R ziqnGP)X_ihcgnm-gW{w^vBy$g!2fQ4T&cK!akyG+>&oLk$Tq(6rml(}pv;SmE_QbQ zc`Ye-%KXm?Rc>GZq(+wa?5(78wS{KN5~!+TQ_7O986TR(RvGAs_M0B%MBJwBkDOfG@{A+}@ z!q37w;TK`O@T;&v_)Yj-*eEC&gBpS<*l~$+M0#;|dElPq^+v^9dfUnef16FaOFi@7 zGNa=2{=NG2uL#jso_fp5&x+YXMU{@vrH8)1{vTC(^Gdx%H!D|dt7tCd=@0nhl$*b6 z6lLqbV*BdbE%oom;<+e!9SV^U3yF{lnUD(wp_))#s3Fu8Y6*2jPjy8eEP5I!a*%L{ zaHw#YaJX=UaHLQolnMw(2}cXZ2*(P?OFAcrJW0|yS>!3gslsW(U}1=Gx^RYYrf`;U zws4Mcu5g}kzHp(WGgM@`o+K`scu`B8QN`GJQ`q0KQ+Hdmtzyeav3@Q;pjWmQRZ+k; zxfYbC+`fuconp%6#jsVS=eQONZ?WY5GrK6$zu3N7xuyPZ7yZwYJew`tA!UEx5;XdJh;X%psheSRix_eaQW5VOYLSd2cgz%*Bl<>6hjPR`RobbHx zg7Bj7vZV8h$e$&hbs~Qe)(gK18-(A4--V5Wl5wdan1UtPf+M(spOh5yNAgmpip1Tf z7#T-CsN~P4eZ_K?ki-hC!nLF5<)elNeg7|a%7s&WOO1i69@-7ilAro?;AXF2o3pIqA zLM@@TP)DdMY$eo_Jl{s-eX=%uztrUq2oDMm%X;r4BIn3@@SP&(3iE`!g!#ff^8Esl zl_;n9RWW1Qc95epWCEoUzs&MfT9&sK<=40RZv($SesQz3s|fpFe2|J!WyQl(8Ifl5 zQdq@Gw33r0il>?WQD`e)UMlK;_p%wlKW?a^l$Ys$rM$$d;=BK;{{vH*)sp#%gN1>@ zAmI?zx?u+m2d0ZEZxdqOL~^Q_UyH3Kvj`; z6%!0)@xR3O)#@$#|96Z2r=s<{9BvP_j_?M0#?l*NBic;#tlmsRM+@>9j1vie`@ezkr}|L?10 ztbVoF*f?RlFhQ6oTq8^pCJWaJ*NZLQAoBCHzWPG!_)Fm{;cMX=;XA40SBm^W`U*da zTqXP@tQOV?Kg;*)M1Cms$44SRk@}>}I%IWJCUsg@?r^_Z!(VZI<5#AM+3-5`p-WU12T=#;=7loIE zmxWh^SB2MvH{`m-BCV{svNIWz39jG?K_+{HM6MV8|0>sP5aen8m?EptRu!iyZ4nJQqAe?T?%XWdD*B3>+W$@EyV8-4?)PW? zRB=NU1-H!qOKe~LuGB7@wg10~{(mp(LiA&ZeqzyGA~F>+Ar}flHKDptL#Qd#5^4)| zgu233!ZK;w-;p|ExzrUaM7|bvSFekFLs%@lDJ+rimWuqZ7WP+P6mzlMHMYub-=>~? zd6h3mBmGr+e}497$}&d(^W(q#SO48N^%XX`=~j_=d0(NT{8bsgxU4qZR13BI%P08b zL(%^~w4Ad3pV)q}_TSw9j~xD=|LC`e-Xh?3`5oeV z^FJ@F_76n+gyA; zTNw4NmO?9`wa`XrE3^~Z3muK_s*}ilWZi#Xk$cMj_Y&Dl{@+_G4I8_Ge-7NLW zxBQj8wH#Pe9+8o1MDKq}!wes*)k1EuFO@sgPcu|$at=go6GX0C~E8CDrV1Lg4 zOcQ&ZE;cqpxJ8&LHg}uI%O$?s7?ERzE9JARM2-{t94~T$Fj1H!`+6sfyiPv9UgQnJ zjl#`x{S=X#e*3RvnSGQ6yORB`e|5oTpZ&2$R}mfSzZzY|J)5UpMWz0y!$5i3ZK`Ue zr2tn1m#?Y=@<-2d)Ag0Rbd`68%X6gi&aJ%VfJ6R>|5pCoav05K8TJ?dEQ|jywy#`6 zZNC0HOY}cmbajU?N0=+Rno`~SWd42|VOwE4p}x>SXeewiG!k|Y8Vm9oGHR??p=;4x z{BqmNzRSurTGV~}w&Eusizt=P_(;3gQ)0!HS2E?d$iBY6$hyrwDyCkpP8nKk_W57^ z^N*Nr75e`>E0-0@tZHFF^#8{KV1-RoRT|6Uzl!ZE-`L{(=N)DJr-|hCPC`?mnXJR? zB67F5yJ{}7h0s!HCA1dW2yKOSLVKZu&{60lbQZb@U4`zFP7je6OFF|uULp(^MhKS* zBZbR^QNn29a$$@xR=7gAQn*SOC+UnA`Bypo-#;tUQ^h<(RUx-Ft1_M3mRjgsG-q6}008_mRxm0_3NS+S%0ZC3Y9U#a_5yk-A?qS*g6VqcSl$-=e5b;9++4Z@AWO~TE>6k)0`O_(ms5N;Lw zoGJ1(vGdnOz9B3Y-W1*vmIzCQw}oZGJHorda$$w=p76f#p``PX$WJ7lPepzvd@g(; zd?|b-d@XztQ5W%eh_{XRtc*moeEnjU(jt`l?&jeRoe2)E055yWy&oo9iuC? zX@$08xwwidy3GD7mWr!z6(}n!oBS5aZ)sg=^oQb_|4y>GQS_f~S^uvQ{co3aSM_E6 zwt>)4*j{KP>>xB2b`+WjI|)sNorPw?F2b%t^Q1(z5ZOx7X)Usi&{k+Cv==%E9feLp zXQ7MGRp=&k7kUUih2D}*ACb>R_0{t-NAQC1;y;}$_#dmZtt*eYy{W8}Zx^m&iAMdg zO4~wq3`@RO(WIBv9~GBYH4#zag;24aD=o|>!~IKHtY!L^)lU*HuIRQsG^c?U!Z#_Z7+G$7GHEaghs!MZy!plfu)oM*ob+kHmldW9h?vB77=* zCVVb@A$%!(C44P>BYZ2Yl=!jVi%jbFQ)yk9OA>OST3v|+BJwX^tCA1PtfP2nj4ZfS z)kK$f=_ItYTrE{;r8Bz4bSpZ4mCrrO)^Z5|P%-IReuu<=sp5$%+z_hT04P%?6>F7c z%T}!`pHr0I9Ju9DK~>>x2Z6g?@?i6NMRCD?)^xPmA6LLh8Y zx4YU_>xB2b`+WjHS6Z8mdM&d9bqfc|JEYcNqPE3e)m_|Q?Nng z8}k3fBHt9=5|#+^*mCCEp8HkUMwu67n<|dc-CUpTE76X8)xVGKQ{hceuFsb3D!=2; zGAM3kmCxzOk+qwK=$p!65$jVE3Wi>`IuvnS>>rI8XiVY*8|DeqF zi)VlwZ~SThOGW>0OI|M%-VxpvmJ2I{_v;K(ABe0x8~^{e|GRSF&$26P3za51@E_ZS zQcl^}uc-fj-g-#4akVnS@_MIiWwT;_y~@^AdhstRBUZ%{D;Dvm2~}B*D^<6;GE((# z-nGsWC3BOT?)>}tDqj2_D5F}XdH;XwmoiS6SM>baxbfdc8eR0SV^l2u*Si}&{nzW_ zYyb6#%Kz6Tr^f%Wg`<4bSJeK-jsNzfsd@i8Uuyjyn=k*bJXo<2FW3IYjbBRpuT+-h zw*CLx_Wwr;fT^aI>0fOtV*vTrCjA>~u&IVvYKX0dIBJNihInd-uZ9F_NT`NHYDla~ z5=E-W)ZknVDX1aU)R5|GNDVclrW#U94XG_>1gjx+)sU^!kge5_dTPivYRI-~$abo< zzM_Gmp<;VQBgGDi#)=&kO%yvRnksfyG*j%N*j2HcqPe1lqNSphqP3!pqOGExqP?Pn zqNAddqO+olqN}2tqPwDpqNk#lqPL=tqOW3i#U6@16?-Z6R_vqLSFxXBe?>pV0gC<# ztr(ylk)D3&VTRxDGzqj*=b zT(Ls&p5lGQ2Z|3BA1OXoe4_YN@tNXt#TSY%6<;a7R(zxQR`H!;rQ&H2Xlj)1Y|zYL7lU05b~8$w8?-QJY0%1`wLu$$wg&AC+8cB*=xET%ptC_2gRTbM z47wYr#*G#=EYp9{_8V@g{~kt3PlH|ty$$*p^flPsU=M>m4fZnF+h8AqeGT?A*x#U^ z!2t&S4Ya`kg98l?GC0^^pur%6LktczILzR1gCh)%G$=7BHNfB~gQE?OF*w%XID_L2 zPB1vp;3R{S4NfsQ)!;OP!3IMNPB%Ei;7o(F49+$<$KYI}^gM&}4K6Ua&|s*+MFtle z3^TaIV7S2ugG&uY8eC>D%3!p?E93WN6y z-Z%Kb;6sCtME^~jENWb)f3bblsJth*ss8`iDEY+TQ-jY8J~#Nn;7fzA48At_#^76n z?+jKNd~fiB!H)*3jMASBRvWA_SZnaJ!8(Iq4AvX`YOulJH-p~|HpQ+nQ`= zQs1P3NkfzEO&Xc(VA9xRN0TNdJDD^!+1aF-$u1_ln(SuM+@ys`OOsY6txejPv^8mG z(%z(lNk@}TCY?>Xm~=JiX42iHhe=P9UM9Uw`k3@J+1+FhlRZuLGTGZ?ACrAe_A}Yv zq@T$FCjCvc$pDiBO%5_S*kqu|Ad^E(4mCN<OGl`X6DITxv4XrAdUxxwT{lbcL#Hko2F)nuBy36ubaGKve@KJlebKkm@GAU z+hm!^J0|a%EH_zU@}9~2CLfr5X!4QC$0nbcrJtI7X7aho7bahtd}Z>r$u}n7ntW%n z(&T%SA54BUS!ME*$!e1|CTmT8Hd$x#i^+PEUrjcc{ATjI$wtwMg<)Y@SQfU0W8qqO z7QRJb5n4pDQ`RDpJy#Z)MQ%~BsAf^!qJ~9Hi&_@7E$Ud*wb;sHYm0go+gNOCv7JSI ziv|`AEw;Br|GO?~R;GWkebr>k`oED?vV%oqiybYRSnOoc)M96gW){0x>}s)_MRSW5 z7A-AWS+urjW6{>4oke?#4i+6PI$3nK=wi{;qMJo`iyjs|EqYn>w&-Kg*J5{zJuLRL z*vn#Xi+wEiwb;*Me~W$=2UzsC&=vzM4zxJP;$W+Epv54ILo5!pILzX3iz6(Kv?#GC zwZP&ii=!=$u{hS^IE&*gPOv!9;v|ccEl#mG)#5aZ!4^X-PPaJ2;!KOPEY7w#$KqUz z^DNG{xWFpC&|;{?MHUxZ470ezVz|W!i%Ts=T3lu^%3`#|ZE=sq0*iYs?z6bx;sJ{XEgrIX*y0h3M=c(+c-&&4 z#UhI*ES|J@%HnC!e~adeb~WWZ?4s?frov|Zzh|tHXDyzyc;4a#ix(|kvUu6z6^mCb zUbA@J;th+%7H?X-WwFF!sm0qC%Piipc-LaN#R`k}EZ(>Hz~V!Tk1Rg6_{8ER@Lsb*8%riM*Tn_4!tZR*(6 zwb{yMYnysD+t_Stvz<+Sn+7%wZML^*WV3@!W1Agqn%L}Q)6`~Xn`Sn<*z9Vvn@w|@ z7B($yTG_O=X=BsYrkzcDn+`S|Z93U>w&`Ni)ux+GcbgtIJ#Bi~^tS0^)7NHqn>}py zwAssMZ<~E=_O;p1W`CQ0HV4@Bx6w8OY!0+J$mU?1fi{C|4zW4Z<}jPXZH}-x(x$|w z)CQZQY>u`$#^zX?MJ>woFSf6mZK?m`?2_YcPOv%A<|LbwZBDT{)#fyt!8Su|PPaM3 z=1iNjY|geh$L3s{^K8zyxxnT^o1r!r*<5Th%;plC;Wi^|F0~nHbD7O3o6$Cx+l;Xp zYjcIol{Qz|Tx~PXX1vV=n~65p*i5pSY;bvD=A++cH~%}q8p+f1>UYBSAdy3Gum zTWoH%nQ3#I&Fwa`Y-ZcsVKc|(PMf(l^K9<2nQwEq%{?{?Z0@zW&*pxc2W%d+dC2Br zn@4OOwRz0uahrvbNj6W|JZbZk&C@o|*gR|VoXzt#FW9_j^ODWWHm}&cYV(@S>o#xL zEVg;m<}I5gHcM^ZwpnKLj?KF^%WYQJyl3;i%?CCg+I(d5vCStopW1w8^SR9zHecF& zW%ISoH#Xned}p)L=6jnTY<{#^W%HBGYMV7SYi)kES!eT$&3c<(Z8q5aX7jtvMjPc| zIG7HWgYDorxDK9!?`+b4(e`)UQvZQd5;{ZN#xVu&u*(4)q-xI5c$F-l37h4i1eSc64asu#-bmhn*doIqc%FtHW*% z%^g}ev~+0Y(AuGmLtBS-4(%N}ICOOAhcg_`bU4f5Y=?6k z&UHA?;e3Y+94>Si>Tr?6#SX(9E^!#{Fv8(dhmj7KIgD}`?Qprn7>BVAS2$ehaFxT= z4&xlgJ4|qx=x~k0B!|fk*E(G1aJ|C~4mUd7i;=T$(;^!9p*XQF}1r5{IP@Z#yh=c*o&ghvg0{9Nu$y-{Av?4;?;o_}JkShff_obNJlh3x_Wq zzH<25;Twl<9lmo|>F~Y74-P*%taA9tVYR~=hqVqrJFIi~#bLd}uMQg=eslQUVWWd` zF`^l|Cyvb)P3E_=G{<+8WS zK5m))PcOIqmWC?s|JXGC+t)4G&t-p?el7>N^moxN16&StImqQ;mw_&WTn=$L)a5Xj z!(EPWInt%XrPKwNqg;-5ImYE!m*ZTHcR9i3M3<9XPIfuP>`T;npyWwOh)F4wtS?{b67jV?F2-0U*NWva_Gm+3AuTyAl> z)n%s3Z7#RF%yOCSa)-+tmpfhNy3BLA%VoaH-7fdIEO5EkgF0Z@1;j-A} zO_#S^mbff+dD~@~%R4Ubx-55D;qso#`z{~2eCYC#%f~LCxTT-EeCG1G%NH(Rx_ssG zwaYgy-@1I~O8>uQvHchQ7j3`wmik}mmVEE>gUgRDt6Y9^S?#jMWv$E4F6&%=aar&3 ztIGzL-&}ro*(gbR7#^mF=;6`RqnAf-k3JrK zJ$Col!(&g6y*&2z*vDgEkNrIM_vq(wfJc81?J>aPK#zkw4)z%6G05W(k3&5U^Elk& z2#+H@N<2zE@HoojXpdt&j`cXs<9Lq~JWljD$>U^?Q#?-fIL%|Q#}JRxJJYM&B!(*|>n;vg@Eb&b*@%Yr^ zGmpT_;?vcqn@@M2 z9zH#NdinJB>EqMaXLp}HeD?I&%V%$&eSG%y+0SQxpME|E`1JSDJ_CFX^f}1qV4s0L zgM1G0In?JcpTm8Q@Hx__#HZ8;pQC(^_BqDqSfAs3j`umi=R}{Ad`|W`#phI?(|iW| z4DmVL=M0}Sea`Yr&-OXT=Ukuje9rf|z~@4rp*|P+T2sUU?LM=7X8YXXGsovnpSeEseD3m@?{l}$Jw6M3?)ACP=YF3D zd>-_9$me07M|>XjdCcc=pM^e)e4g-m(&s6kr+uFBdDiDSpXYsE@OjbaC7+jlUh#R= z=QW?#i~4V~sCAkC#r9RlE$4sU@Jkl^yy^3n&k~=dK5zRh^LfYTU7zJXD}3JbdEe&) zpAUUL^7+{36Q56gKJ)q9=L?@NeZKPf+UFaeZ+*V=S?Tk=&ksI7`mFN#$!E3C8lSa3 zKl`ln`Ne0w&#yike17x!-DjgbX@C)wngLdT9pD7G0bYO~5Cnt)Q9vA!1f&63KpvD9 z0;&a652z7PGoV&L?SMJ~bpy5v*gBwIz%~Kf25c8lKcGQC!+`Ar8U^eS&^TbnfF=Pu z1vCxVIiOj=w{GphZB-fK~ym1KI?%4QLn8KA=ND$AC@&oddcAbPebh&^@3> zK+k|)0lfqI1oREqJz$T3Jp=X%*gIgKfPDk@3)nxPU%&wY{R4EsfPe!74hlFpU|_(Y zfI|Wf4LB^|@PH!%jtnRXC=DRssDPsbjtMw6;JAR}15OAyG2o-ctXk2PJ0&oEdOdz}W%k1e_aiUcmVQ7X(}wFf`zzfQti$1zZv^ zJYYn?r2!)YE(;hHFghr`JYY<~*nlent_-*;;Oc;J0pkNE1WXLLCSX#)HUiz{dff1biCsS-|H3Uj%#^@KwOq0pA3C8}MDg%7E_!ehBz6U{%0R0jmSn1gs7C zIbdDDF9GWVeht_V@LRy|0UJe)Ax4N9VujctPKX=gh4>*sNEi}@#34yY8j^+NA%&1? zA*w_BMeWSu{GZsqY|!0e{8v3JsS#2$q*h4nkUAlCL$(UpI;396HX+-FY!^~Lq(Ml- zknKYnh3pX0IAq6=CLue8G!5A~q*=%=A-jg`7ScSVMM%q#Rw1oJ+Jv+XX&2Hyq(ex@ zkWL|;L%M`?4e1urJ)}oS&yZdry+ith^bOfPWRH+NL-q>UJ7k}beM9yO**~OT$N?e! zLv+Z1kOM;w3OP7rV9215LqZM>IV|MxkRw8l3@HgI4I$*HkfTG62{|_8xRB#RP6#Le363C*<6a^Fq!Kxgg}ikf9+Lg z+z@hO$W0+PhfE2X8Zs?pddQ5BTS9IPnHh3h$n7DsLS~2D5i%#_&XBnw^Fr_x9 zRUtoxtPWWdvNq)BkaZ!ygsczwHDp7`Zy~>jY?RU;VMLe_R)ihlM7R-NgdY(^gb`6h z9Fat%5m`hYQHZD(Q9YtYM9qj=5w#=gMAVJgDq`!1dJ)@1Y#Xs%ME!^c5e*}@k7yLJ zLqy|<9V41V>=e;7V&{lv5xYd}8nIhM^N1D^EhAb*w2o*K(Ke!8MEi&i5gj8sMRbnn z645m(?H18JqDMr}h+YxBBl<-2jo3Y6kBB`Z_KMg$VxNe8Ble5fKcZj60TKNpbi{y& z10z(YjurYZ+J4V1`+o;TB?m_gj2IMgNW`HLheaG7aYV$C5hW3&5kwpnadgBn5ywUx z7jb;V2@xkooD^|##3>P{Mw}KgIATb|=@Dl{oEdReRC;#AIT7bZoELF^#03!-MhuO( zDB|LXVG)-^438KQacRWJh|3~IMU0NPJYr15*oZ44u8g=U;_8TT5#u8!L`;mhCSp>= zB5seE6)`*Fj)*xCcSg*O zm=|$Z#Qcc6BkqY<5OHtBeG&IZJP`3<#6uAeM?4boXvAX?k4G$wSQPO@#FG(EMLZqx zOvJMh&qX{R@j}Fl5ido&9PvuTs}Zk7ydLpJ#NvoIBi@Qw60tPm?TBR&??k*Cu{>f$ z#Cs9%M|=?RVZ=ufA4hx=@oB_o5uZnV5%FcjR}o)Fd=v3)#CH)ZBfgLLA>zk~RS`c$ ztd3X{u~zi2Ixp%}R{x9bOTdOL>i?gkl64WkM68eaHDW`=ZxO#oY?S+Aj2JVjrbsTor%rglu7n7T1r#cUl@FJ_yVZDY2J zsUOoIreVzXF^yt&h-n>Sf9W|x>)-i2j+Qzht zX&=)erejQ}n9ea>V!Fn3i|HQIBc^9eubAF3ePa5?>>jg6%$_lO#q1rkPt3kC`^D@Z z(=XAu*@NoDp+o%vmvK$D9*$Zp?Wx=f_+Sb79QTn2TaA zju{qnNzCw=5iys>jEuP~W>n1Rn9F0v#Egx(BIe4Nt75K>85c7?W(DX zm^)(T#M~J(H)dYUT`}`x?vA-9WpiE z^Fz#!F{@&Jidh}ACT4BS&oS#_eu-Hh^J~n8nBQW4kJ%Wb5{v{h!Ah_boCG()OYjqd zgfJmWh!c{8G$BjK6AB5{5~?TENT``mE1`BmorJmxTP19rP%mMdgl!YHOQ@gFAfaKx z_6dy=c1UQPuwz1#gq;$aChVNhEMb>~T@!XoXr9m_p=Cm=gw_dd651xTOK6|aA)#YZ zrvK^Xw!g=g`tOvKbWZ4!&^4i3LidCo2|W{fCG<|{lh8L|_k=wX_Dt9-Vef=}6825l zFJb?LehCL8^iR+U0}>8QI4I%Zgn!xN53I5MFmp)`SnqY{ozI40rP zgyRy9PdFjr#DtR)PEI%_;nalF5(Xy>NjN>>jD$0j(z6oIPD;;7I5*+Eg!2vC)}NIPr`zPdlT+UxIf{6ga;EIN_aTok%UJR9!q#UVWB80;faJN6P`+V zI^mgwXA_=Fcs}8UgclQDN_aWpm4sIlUQ2jADSabhal)GkZzU{ASeo#5!m@;S65dT% zE^6)CrD*@6|Dx^hwPpLiA}M(<;r)aU5x6F- zzD@WpVP(Si2|pzKn6N70r-aoBYZBHb{G6~Z;g^K<3BM+6Ncb(`_k@iJD#b`KQ>+v_ z#Yu5fyc9nrNC{J-lsF|xNmH_vJf)CQEv0%&jg*=xwNh%Q)JdtEvQ^5~DfLpeN!d1K zyOjDV4N@AWY@gC7Wrvi;DLbY#N!cl-Y0Azi%~Ezr*)?Uil;$ZdQd*|8N@<r3a=QlyY#&z?4BLhol^ua#+gYDMzFnnNpHcnnKD^DMzOqlX7gz zaVf{AoRD&2%1J3Fr<{^HiKDVL-SPZ^PNY0Aiy%Th+Aj83^cWlYN0lq*uMOt~uM z>XdOQ<5MQ2OiZ~ZWm3xIlxtJ2OSwMfhLjsqZc4d1WlGA_lxZo`Q)Z;xl5%Ux%#_?nzmYa&O9gDfg#5kn&*4Ln#lZJd*Ng%3~>y zrz}ial=4K%lPOQ7Je~4P%CjlYrTw2z^$V$fG1V`n`sGx=lImAe{aUJDPxTwAUYzPT zQ~g$|m!x`Ws^3oavQ)p5>UUGUJk={w{a&iyPxS|>{xH=arTXJkf0F7?Q~g=0KTq`+ zss1w6U#0r%RDYA|Z&UqUs#m7^`&9ps>K{|RD%C%wdUdMTqrt?e}GF>gx z)iYfq(={_)E7P?zT_@9ZGrd)&x6X9EOmCBwsvg4@buZJu*uL6tOZ(q8E7>lienx|g zh8f#uG|Jc^qjAQL8BH>F%4nLgb4Ig_T{3pf*e#=ZMvIJ=8Lcu}XSB&^o6#<#eMX0j zjv1XYI%jmr=$g?jqkBe=jGh_2GJ0q9$>^K0d&V9aduHsFv3JHk8T)4Jm$83Fzl;Mi z`e*2j0T~Bo9F%cz#=wk08HZ#XnsHdh;TcC{9GOv)QJO)P9FuWu#&H?PXPl66 zV#Y}sCuf|J^*=S!r)7F@riWzu^h}?T=`%BZR;JI+^f{S6H`C{3`ut2^km(CEJv7r7 zW%}Yw56ko=nI4|$5t+U;(<3u|S*Ay2dUU2Q&-9o~kInQInZ7d9S7rL@OpnX-_)Jg8 z^u$bGlj%vBo}B4xGksmAug~-inZ7a8H)ZEz0y0nSL_UPi6Y)Oh1$9XEXg=rk~IB z3z>c~(=TQE1Ouv)qcQd^_(*u;bt{dih`&>85^$xjioa-HP-6YpL<+^FEcg}UQTc@Q=ekX<+vd7muG{CjL#{jKx>K$@=ekR-yXLxEuDj>DN3MJ3x>v4y=ekd> z`{sK0T$7uxPOi_*^?A8IKi3!J`odff z&GkjOzBt#za(zjzhv#}kt}o5?$Xs8R>ruHLo$JeUJto&gxxP8qQ*u2u*VA%6J=ZgGeM_!y&GpP& z-VP!rDVJJ-u{{Z6jm&GqtJugLX#xqd&_ALRPOTz{17 zk8}M=u0PH7XSx17*I(rN%Upkz>#uYDO|HMq^>?{mnd|R!{X?#Q%=M~V|CH<1xn7g& zwYmN|*XwfqORm@F`qx}<$n|fz{yolbu`f^JyQ+ZS}Bg5IH^8yEDB1>K~ecPi+n1-)}YH!J8}3VPRq-mRdU z7j%n)ZduT+3c7Vcw<+kh1>LTo+ZS|)g6>$*oeH{hL3b(Wt_9t#pt~1zkAm)5(7g(} zcR}|l=)MKLdqM9}(0dm2UIo2(LGM%0`xf+m1-*Yk_bccF3c7zm>w+Fo&<7UuK?Qwq zK@TkGK?QwCK_6PshZXeU1${(8A6d{P1zlRu6!cLAeRM$|Q_#m2^l=4!d_kX3&?gr3 zNdH z#YQYFY(#9VRk5(JTd`ZQTkqG*&hF0mWoOa*{_B4H@bUCBXLimtXRgn6T_@*^rl)mL zS~JqRIIT<4x-_lJ(z-mYnQ2{-pMUzkwN+vMuS_>wmDbg1U6axQ&$ zOzWn!Zcb}bY2BXI9ckT})?I1coz^{R%}eXvwC+pm{%p{| z(t0SZhtql_t@&v^n$}}!J)YJRX+4?Ng0!AW>*=(fN$c6Po=a zJgqO%`ZBGr()v2BZ_-+v*0*VWm)7@b{gBp=Y5kPe&uRUV)~{*(me%iS{gKw6Y5kSf z-&C8el&un5rM5cR>TIivt**AZ+3IeqhplC7Eo*BzTg%((X{(p5v@P3~W6QPW+45}# zwnAHxt=Lv#YXw^?+FHrh%C>sjTE*6?wpO#Xx~(;At!Zm5TWi}|$JV;G*0Z&~tqp8# zXlo-|Wwy#~RoJSuRb{K%R*kJ%TXnYTZEb986I+|w+RWDGw))uWYpb8F{&rsfr|(tHIW2TaC74YmBY2wzjghwXJcs zwy`zd*0#2`v$egg3AQHMnq+ITEn{m3TRYm?$<`EGJKNgD)~>d8v$eaeJ#6i1YcE@S z+uFz0zP9$WwZE+cY#nIpAX^99I>gqYwhps(xUC~>9ck+*TSwcPYU>zV$J#p1*73GZ zuyvxXlWd)A>l9n3+B(hF>9)?Wb*8PeY)!Luwykq)oonknTj$%lz}AJfrrWy6)(l%0 z+q%TorM51!b-AsXwyv;srLC)MU2W?cTeECkYwJ2&*W0?m){VAqvURhq*|u)6HOJPi zw&vQp&DQOpole+j_v(gSMJ%J!I=)TaVb9Z|hN8kJ)Z`pd= z);qS|wYA9Bd$!)U^+A6A>HF6B!u)?|H+*F4V_Tot`qb8Ewm!G@g{?1beP!!wTi@7P zZ0lQF-`V=!)(^IRwDps%pKbkO>sMR9+4|kqAGZFq^_Q)`c|%7jMt>$QTM{77*)6rUv)^@axqjepv=V*OL8#vm~(MFES9F;q&a8&82%2BnW z8b`H`>KxTO+St)1jy83)nWN1e^>NhKQ9noh9Sv|a(9s}AgB=ZVG}O^BM_V}B($R27 zBOHx%G|EwfqtT8U9m&xcM`Imr{KL(PT%)(GHGw zbhMMBDUNn_w2Px%9qs05cSn0T+SAcqj`nu6kE4AZ?dNEJM+Z1M(9uDT4t8{iqeC4X z=IC%oM>smt(NT_$b~M$|F^-OPbeyB(o#y_}UEa9rlj}aWOIb~;atfgN-{n?n1*>Vz zmdR9KE47lm9wiZDggY ztftocaCTd0rE09E)_dW0-`7gjSxv1s817+Psg3ieZ?{sLT1}g@l)ubaE48`Rv}x<~ zPZm|uHofe0E7d=5dby3Q)Ih7LPs{6o*%fBFh5)tEPJ_qS4G@~1zrQd{LsJI7n8aoP9EZvQj( zTN4WV{|QdRiH=Tkbh4vU9G&XuG)Jd9I>XVKj?Qv4&C%J8&T(|Eqw^e{@8|+Y7do2m z=psim99`__5=WOhy3En#j%GT#!qJtEu5xs>qiY<^a&)bu>l|J0=mtkOI=acx&5mX} zy2a5PN4Gkf>*zK|w>!GS(VdR&a&)(&dmPPkbg!fP9Nq8e0Y?uyYI5|DqlXgTGzs{yVCx*Ftau&W`ihPoQ& zY719ex*G0kgsYLRM!9NmHQH69E4douYOJfRTy5=YoU3hIjd!)JtLHt>MU2&T%GOe99QSMI?vVlt}bwOp{wbxE^;-))y1wZadoMy%UoUVYNo3zTwUqv zDpyy#y2jNkSJ%3_&eip}s~FTU^a?b*rnnu5NR6yQ@1~-RbHsS9iO* z$JIPn_qw{z)%~s>aP^?8CRY!+df3$?uI9UX)YW78`KRw&rZE4HyA4mcdeYSbS5LWm z+SN0zo^|z{tA(zfclCm+7hS#N>Sb52xO&yqYpz~*^@giAUA^V%ZCCHOde_w=SMRxc z-_-}MK6LewtB+lM;_6dZpSk+n)fcY5boG_1uU&oPYO$+tU47^3dsjcW`q9--u6}m) zi>qH<{pRX-SAV$r)74+D{^oOdN_i^rRO+ddr_P?bcuU*qNkNSt?a3{r&TS;Akt9x3*)0&>v z^0c<6bv&)>X+2Ntd)mO$hMqR^ROYGNQ-!BWPgS0(J=J)s^;GAn-qXgOHu1Enr_DTV z?x~NbzMlGd>hEcQr-7aZc^d3#h^L{RhI!h;)0Uowdm7HF4>h56sb zYuMG(Zk~4cw1=lXJ?-UbZ%_Mp+Sk*5p7!^2fTsgJ9pvd?PltFq)YD;}4)=6~rz1Tb z<>_coQ#~Ey=~z$4c{<+H37$^$bdsl&J)Pp|R8OaQI^EM5p3d}imZxc+&h~VUr*l1> z=jnV;7kIkR({xW4d79zrVo#TNy42HUo-X$^)6*56uJm-3r>i|(<7t+sYdu}(>3UB$ zc)HQkO`dM{G~3fHp5}PE)ze&0w|TnV(;c4f^mLb}yFK0GX`ZKhJ>BQ&eoqg0deBpo zr-wW}?CB9t^F2N4=`l}_dwRmtlb#lMddkz&o}Tgatf%KZE%fxfrx!fE=;H$1)R=`BxhdwR#yyPg(#de77Qo<8vOp{I{LeeCHIPoH}F%+u$dzVP&= zr>{JH?dcm&i#>ho={rx~d-}oCkDh+=^s}d5JpJnFH&4HN`oq(op8oRmH%a!D@>Sxi z)K@28oqcuj)zw!wKQI6EeQQc#{=54PJ$x)qSnuYfWEk`C8l8I=(w)M50 zukC$J@HNrbBwv$#8DBg2+R@iezNYxv+1D<Yi*FL`X^|ha` z{e2za>p))z`8wFwA-)dvb(pWieI4QJNMA?!I@;G%U&r`5*4J^qj`wwfuM>TpvxA z%YDuCb%n1heO=}2YG2p*n&s}Un6Jlu zJ>ly~UkiLazTWipman&c zz2oa$UyFRb=j(l6ANcyv*GIlS_VtOcPknvn>vLaU`1;bIswzR1&B(P^Unh19b`1HBh%e-2?Rq zv`nC711%S5`9M7b^$L^@WCwBrxq-YuexM*w7$^!92TB615NO3fD+O9PQ13vi1X?xF zYJpY{v__yc1FaQk?Lg}US~t*ofz}VSL7)u-Z4{_1PL}- zjRS2GXwyKO1=>7NpFn*B^$XNL(11V#0}To^IM9$lLjw&9v_+8D|LObIZiVN6w+tGF z2O1G*WS~)j8Ul?D)EG#C#snH0XsbY52O1Y>n?U0OZ5wF2K-&kJ5NKkcNr5H@GJ$po zv}2&10!<0DbD&)U?HXveK)VOpBha3K_6oFjpnU@E8)&~k`v*E8(1C#t3UqLwLjoNd z=&(SC2Rb6qk%5j1babGpfsP4uY@p);9Utg~Kqm$|DbUG*P6>2spwj}K9_WlfX9hYe z(6m5j2RbLvxq;3Lbbg=<0$mtrdZ3E}%?NaHpi2T>8tAe>mj{{|=!!sB2D&QH)q$=F zG%L`xfvyX5eV`ix-5BVmKsN`P9q5)oa{}EOXl|g}0^J_yjzD(?x+~D#f$j-3FVMY# z?hAB(pa%jy7^o@GLxCO+^hlujfgTO?SfIxPJrU^1Knnsr73k?e&jfll&~t$n26{fw z3xQq?^irUg1HBUH)j+QWdOgq^f!+-CR-m^7y%Xr&K#Kys7wG*!9|Za^&_{tj4)jT& zPXm1x=<{Im7lE<*x19f>?^}Bm=Ksr};j2Jj2l^(^;y~X9`YzD-fqn?|W1yb`{T%3* zVDhhl`7JQN2j-8!{27?P0`oTohb9%8lF*cfrc-D-ho(ztx`w7(Xu5}{M`)G_&9b3c zE;P%Bre|n+g(e*uJ2Xyc+|YQT@k0}YCJap!nm9B`XjTZ#ilJF4G%JUucW71#&8neU zEi|i#W{uFS8Je|1vvz3K3C+5pSuZr}hh~G&Y#5r2LQ@u+^3YU-rZO~Dp{Wi{O=xOE zQx}^0&}0&F-PuBQ$%4X0Oof9h!YYvu|kj3(fwaIUqC# zhUTEq92}ZMLUU+n4hzlUp*bQnM~3F8&>S6_si8S0G{=VKxX>IQniE2EVrWhZ&B>uT zB{Zjo=Csh99vW*vQ-99?&CK?FYp=rb|BP_bnV~r=G}A(Jc4*EC&AFjDFErW z7@DTgJQSLTL-R;z=7;9d&^#8J$3yc(Xr2tsg3vq_nx{kaOxXBrsOLg03@1MynioRz zVrX6p&C8*AB{Z*w=C#ng9-22o^JZw?3eDT0c_%dQhGtP{-V4q9q4^**ABN_m(0m-4 zPeSu)Xg&+g=b`x`G+&11tI&KMnr}k0I5gje=DW~*ADSOR^J8d!3eC@<`6V>JhUT}> z{2rP=Li1;6{tC_C)Ouu6ktvBxX=FM@rgLPvM5b$Gx<#gYWO_tqnaC^~H7*xv`A9t@ z^@@~^WJhu$xskj`exx8$7%7SrM@k~C5NX9oD@9s4QtwEsL|Qe{YLQltv__;gBdrx_ z?MUlHS~t>q(d6|bF8&!bb>P&d0onZ1_pN;j^S?nfX~W2D6q&Nflt-o_GL@03icEE6 zY9dn`nYzf-M`q*5Y!aDGBePj#Hjf(nMCu!=Kz>BePp%c8|;+k=ZjcdqrmN$m|oDeIv79WcH8D0g*W{ zG6zNG;K&>jnL{IUSY!^5%n^|}GBQU+=IF>wjm$BTIW{uKMdtX(oDi84BXd$@PL9ke zkvTOor$y%U$ea6J*YMtUup{CZ^Gh|HUjc`Gt+N9LWV@!d#^BE1*s{YW1~`Y_T*kv@*} zNu*CBeHQ8SNMA(yGSXMkVVRT8T-R;O5N0^o>ow*z}LhfY=O-&7jx}j?IwR42{jO*lZD-En_o0HX~v)GB%@P(-51{v1yEr zVlyT-V`H;bY_^WgxY%qHoAI&PHa6SEX8YJoh|R>=K(@W3yXqc8|>-ywTKQQ-@A%8j`vHYo_m82Nd@IJ>yAx#f^K%+9%e&vG$9#f2;#y z9T@ANSO>>CB-Wv^4vTeotRrF_8SAKc^3k!G8k=Kcb8Kvmi_P(|IUzPD#^$8hoE)1| zVsmP2PK(Xyu{k3)XU68N*i4Jf*|9k%Hs{9Xyx5!{n+sxdVQi+y=Azilh|R^Zxg<81 z#^$ovTppX5apM)Su8eh6tgB;P6KhtiYhzs(>-tzX#JVxoO|fo{H9OWVvF60OHP+l% zx5c_W)*Z3#jCEJ6yJOuGYhJ8-W8D|){#XyhdN5W~tcT*s569+_*vya3qp^7`Hjl^V ziP$_Dn+36XDmG8YjnBk-Hr8{o7RGu$)(f#-jP+8imt(yW>(yAV#d;oA2YsA7cF&>!(;h$NDAKud#lM^?R&8V*MHGuULP_vJ#~dl_V-n)G1NtL|qbf zP1G$>_e4DsEt9b2KXt^^;ZwJq+O$Q9by;)YKd5l~Z`q__xkSq+>Y1olqI4oVk(0Ct4-Zs)<%hw0fd760MnNtwd`lS|`!EiPlTB zexeN$ZJ21IL}iJ}lgSl{sZ2~&VyY8UlbG7X)Fq}qF&igllf-PAn9UNid1Cq`rf*{U zC8mGUI3Ur$M1v9yPBbLZ&_u%$ZINipM8gw}NHj9hs6-8kMki`aq(oy9jZL&wqOB8+ zOSDa*@rkxgv|Xa@6HQ1oG0~(%lM|UlJ0#jM(N2k`B-%OAE{S$cv|FOx6YY^`&qRAA z+B?xciS|vjU!wgJ9gyh2LkwsiUTjY#PD#A1Br5`ME4|`m+0O^_a(YN(F2JdOw^Rn6HjVDf z4}WFP{b%yu)O!BWUBgOkmv_F*2YKqm= zzh&8jFRauqR?~o%>F{(bwVTy6sAW1@-%9OaH4SNrS`FCzPTro zWvtYGR`%m$pGkQC1DJ08JLg{y%DwjgLVgW2uk|z8&(DA6{P6gH)ZZcbv;E)W|DV)A zi8ZkK`j4XufB!49H&9|Vm6oCtI-?7^q8qxS2bRII)--E5;_~Rp<6guxY&dY?!AF1) z5n?3ZN|VwR!4)Q@D>Hv@;wo4btAQ&?O4k5akd&?kt{f>{2V5~y%2gtzTp3cz)gYx6 z;Hr;OuJkD7>W)&b=qTkXj#94NDCKI6(*EG8j8d+|C>?@f*b-c6Q91%#VNp5?Tv<^% z8jTRRlA@IAsQmXSZ@pk;>1S=dW@hPU>D}_L_z%f0vA`0Gi+GM8+f$pj|5|?kZ!E9o zijmT-F%H{+5utQFju&k}+z92UL^Wzrk4>-{`k)^MU=X<4#o`K=(rw8vYnIaO!5XD> zB3P4@PKLn_V9imw6If%E?#%01Q6HHieqpre>;wN zJn>B8*|-wd;6}{GT-bNvPm=%+!W)tLKL$hykv@~X2+{?j&`-l(lg`o$DO?U{8@cew@ zV?6&j@d-SMr+EHp;2RkZ*6x|R85Rn)dOTDO%|S=H|FocpED%JSOU$_jpcHE&t+A7;wRy{4kwR1X-+ zkHphB%bS<4`Slew?JZwx{_EQsb>92b78@2ytT5a6trJt$ih23Jg@v9&es0BW9;xDwVUx~lrcl-esvH7P_a|tT`L%qB@Kl>fLxL|0gD*h{~nKo6PU4QVS z@R_%1_g`+1Xnt{3@fCbqsgLxsXLLbVbVGOaz%p1C%VBx+L@%Ua!+{GA0dE-+Bg9Cs0#?LI zSQ)*s3RcBxSRHF%O{|-mYOP0H9~)ppY($H!CvJ*9=#N1diY+k`qcH~CViG39U$EvLv>^S|%j`pg(BbwpbkMO$6#JpX*KkCi&At&F_&S@y?eb1k~v zm1}cpe0N}KVHqv!)2i(6%yzhmK`}2`sbdSvU_Fz!?&xr}L>Zr3spAXF_}96y{;*Of zww6);AKD&6>h4zRvV~=dUou$&MfTznNz}h(%$#N-q;8GVn6JU18^V?!oe7u zn#orP*)J=o;U#$(a7sW9FCv3qXxC8!^XTeJ9Jmp zS5{P(m38nV$eGWU`Ay+$lc``xF0Uvr@31*$lA9^NqQ1Va;~m3>#(@)uG>#hEkejEj zy4?-dTvcz?uTj|-^8t$fNcez;vHXhjpj@|aUZmp1_s;$MFYTkm3bJFrHLY;{zX|yt zo|@kvIxRV=9gT zHPYUuY_77F6!H>O(P1{N-1bj4p>=f~B`3diRV-nIEnJ?4#-aJe*H?DbFIyI!)Rz_6 zh|IkU+lK{BtAn+F+x}m9dCN~}FMUTTu^O#R-?z?5v1)7E|L1UkbsV`m9w*>LoP?8c z3QomoI2~u;Oq_*jI2-5ST%3pVaRDyGbX;pWt(Rg>SGJ-=eVPEXCA+SogN}|NqddO4#em^nL5Rl(lwV{@>)Ow^;sn zQoU2}5*IK|KSg{R&)``+hlO|^FW^PIgqQIOUQ6{&y-s|OapHaA2lx;l;bVMCnV%8A zNcBp6NnDEB$-X4hohr&WtX5W2)xl8R(64dKuz|T%L3Wnv4!YCCK_kXCucw>eqPn7J z@6IesZB7T^4D+dilqFub4C@_C!z zqpWxhl~@z9ec!sEaQ*)^`Tve~{ylm50YBm={ET1lD}KZ8_yd39FZ>Owg#87SpcI|Z z8C}p7-OwF9und;Pa#$Wc(FVqJ8NIOzR>f*q9cy4stcA5v zhk9&{ahQg)aSqPKc{m>z;6hBtMVNt$aS1NPWw;zOaRsi#Rk#}0U>2^$b+{fk;6~hp zn=u==U=D7D)j_V8)JIzTe`T(@({$9*Lu!gPU(WFi&h~w4dW!QlZR7vk63e=c<+&Yq z;7;6yyKxWZ;a=Q_`|$uCL=zsu!*~Sq@hBd{<9Gs3Vga7Q(|88Y;yEnD^LPO-;w8L{ zSMVxc!|QkhZ{jVyjd$=a7U4a-j}uB}S|<`u!pS(aq%3t9@i-ihQ*bKIz?nD;hx3{v zh)3cm9F3_s2FK!`^eyZ0U+_&HsOBJK5v^ z^nL4+6la3k^1luFAJ6CA7TaNaOu$4;!ekiifE}?DreJ66f?cs2cE=vr6MJEA?1O!= zANI!qI1mTnU>t(ea5{#UG+85vBQXl)CB0J>#A?)_7VD6+b&2a?eQbaYu@TD9$lpaQ zsOAnP>N9Drudl5rtFJ37)`e>8T3=Y({!we*t@vN_7pM7c+1GC^x%eWq<-fJ<)K^w5 zUE9g*|68Y${~Jsr89@A2YjySH5N9N8dG|y7o?x`26_|{ea z60|mNNt4rSazbdu28g;lvX+vsF z;)c}iM#M6dqXLzvLN#hoi#pU}V{C#=u^Bc;AM`~(^v3`U#2|cMGROLXcJL#9!q4~x zzv4Iijz91x{=(m|m@kDAbmB;HXX5fKXHR1DXB;@F|JWe|I3%9i1E{MiuVpMPvJal! zw`hJ@(XDgK8Z~lEFqY|z8uWoL? z8a94V^9RnoRayH3SoZiIec!sWaQi<^4cgRW*U~vwH)3}zLme+m98$W_8cH07EwCkq zV+2NG6dEuZjS$A*L$=30B5xn#6MTx#@HxJ~m-q@_V{yr1>sz8rK0W5O8XAXa@pZArrg2Ys;Y{Ls@h`dX>N*n4XcA= zKqLD7v&EKIw|AO5TXtLi+uD2E+m+WA8>33B&9Z&py1MZAUqJpt>OCgs32_Cih?O}K z+?%*{=`?E`aT|=sw%88aV*(~(5+=i72keNQFaPtNBXMmg~Rn>ttCE zQYZ8AI9|c)cn=@qC;W;(VRdHwMOSzTu{PF2JvPPmn1o|+Jg&iYxEXVB2kyq}cng2R z>caj#R>c}v9~+?pwb%rkV*rL=IQGPTI1m@$F1&`<@dn<+TX-Aq;9V@jdw3sZoj4!C zXR1IYs!)v@)S?dc*ch8&Q*4IK(Fc9e5B)I!12G7LF$6;~3|nAJ495tJ#3)$SfPN$U z^=lr!E34~kYO8B1J7{99`Tq~CH#`2*_pR#+um2iN{u^1IH##k}-Xy+-xA6|%#Ui}l zsaNU);zzvZW8x?H6rbU9e1R|V6~4wdSd4G+9lpm8_z^#MvQobgn<(oc;=_0ZkMbUm z5excIreSkXznt^_mF;iLWoH@EFL$*??)4SL217n_W}Q)9Raa3~Ro&4kok42OQttIN z<;8b-@`|o0eyq^yKW0F#=(6(4`nsC>;w_*p|IKYD^G+O)EH5uFt1iAwneD%gvVGsW zDaDmQZTtV-I$KtE`d|+%gJrQCmPb$YLK-$4xbQpoP6fpEJ6ov@h#O)fl%X6Is6-X2 zQG;64VPodqgcx;RY{kR`D_}*egq6`7t6){EhSjkK*2G#^r*p5=y2OIEk~fjfKvh{? z1y}l27u%<|tX!ihuc)hF{a#U9bp4xOZjmEEEJ@3i8O;k(U33dGTWZVu7wy>v`5!WD za9OVLG|$W~PhK7T??d+gIrnePOIfYu;6=QIm+>m&`)kBLT^3n= zDW@O$V<6=YA`Zr;Jl>4h?!p%QVe3(i139B!#-XmNvf@X%Gxe2wVexCOENdXAcDETb zsHNcY;?Eo;9;HZS&w+?d{+eEwhXY5r#-Q*`r{D)k+mk#1}2wA0}&E4$BjoyN=+y8lz(`A=l(zJjYpD(WgLI=UDnH`dnI(E`|HD4x~k zHp?DaIal)*yQH&uOQgBYme+SMh85(0#6XToY>oQBhJ2F}D;n1-`)4$j4SI3E|_LQKa+n1PFNDY?6hIJxs8%dpPg0Xt$R zOu^3B1-oK5?2bLKC-%bL*a!P!KkSbKa3BuC!8inm;xHVJBXA^+!qJ$DW7%dnj<^}y z9h(!|R{gnkbdh5xG@0xGP*YP^QBPB8|0qkQaSdxdR#a6{Rl~X8B1d#`1?L)7S@G6d zxPBP%@0xn{_#b`Wx;@2}KyBN9ec1l%OMUc1e+5jr%2KNnGc~@1f7yIxyI+w@`7`sioJ4Q#tJOuXAImGW*gk;rjzl&WTUBJZ$QD}N z+*CTa;H|L#w_ILczEll3+yCkN)}4jN|4tzPCz6Mga57H8sW=U%;|!dMvoH;3;~boe z^Kd>cz=fEOi!cKh;}Tqo%Wyen;tE`et8g`D(GIR9raCXQN{FTC%yV6cmvmZWUCOq^ zWw;zOaRsi#Rk#}0U>2^$b+{fk;6~hpn=u==U=D7@Tv&q}nn(29YPy5(6J)d0yuVn} z!J49RP|HqT?)B||mn72wvnAJ+v9D57Ui1W{RoMSWHMG1<^RUDb?@V#+{mZWZ>HF5* zDXUXn|G$m>|J$jLJ8&oN!rizB^KdWjXW#q*;;oF~bIHqXxE*)0FLxL55b|^=e?JU| z;|Lsyqi{5);usu@<8VAqz==2sC*u^Hiqmj9&cK;C3)65m&cV4j59i|oT!@QUz8S>K zXU|k;b4u$wIQ(jj$PLulUFfoow!ZT6R95`bqG6+2GSi$^E*NMpD}@W((V^&q{@?iT z8gSR1D7VlAwVb+9hh!v^fPY)D*krZUNIK1j!DfF-}A_1Q7GgL)N}m337$RmBe} zG&k5>3#{*;=)(Mu$PHjEM}UeRx?t(p|L5GlwIEeEj*MVW=wIw&Syq?Ltkg~aDC6I4 zi&$3aaaL;fKg#%b>ofLuH@CP>xp(egc`f@yBQ%8ddA6r6&AOk@vbvR;TUf@w>{sl& z&$am0T)}cQGPL}Qfrv6@SgAV;%b*$kn^s2|8(OKmTU+5jAC&NI?#$S4J&>|i$m{>V z(f@y^-T#5V=!<_7uV8 zI!trewKm&X^9%at<7}(S4(QeObw&Hy|BU}dj{;}Q%^iuZD!yk?(8k96b2Fp(Zb^3h zXY99{3XlK3&Gz3r)akoeg!k}1KEQ|g2p{7Ue2UNTIljP`_zGX+8!X1R_zvIW2mFYi z@H2kFulNnW;}85rPX8u;TDr*kjQzyV@ddubSNIy=U@^YMclaJZ;79y~pYaQR#c%i> zf8bC2g}-6Zu2U#MDLSDux}Yn%)AoB1|C#od>1?~oHWCihw>-Jz*qHlD3SZ-@sH>^$ z;NqrC!BzDY^)>b79hCcz@nKZ%v_x}j=d#42Z&YFp&Gvok;llm@`F!F>sh`L2IG(_h zSb(SSG@ik;cn%BkJYK+ycnL4#6}*bq@H*bWn|KRv;~l(^sJ+(et z*#8?_@}E0^Rs7p2CDx#9-?!!$9{=mg@xN|-&hF@eWw0!k!}92fUP!}+0~a2A1PBo! z#zExqVB#S-6o=t(9DyTo6pqGJ9D`$V9FE5cI1wk|WSoLiaT-p?88{PXVH(cHIXD;R z;d~6`{f7~^z?QhX%N*+-;ym1o`*1%Vz=LSQLwFdEU_PkuQDa7BR=<25v#heFtd4QN zH496AkjZ)O*mHS@9XVS><^XQ?Epi8Niyzv~%+i+sY%^<~nW1B88fNzTZ~DIV81mNt zkCOk#_{@*v2|S4fcnVMB89a;Uun^DV1-yut@G@S(tGKYsLTftlBFwI$Vz%a3gNQ&6tf_FbB6{E^fo^xC3|MgDzZWNc;|e!s<$!#&QS{ zV;!uE^{_rRz=qfeN!OXy3d9vb4L3BWr@XSdmYu`$q9^gF(>naie`?pR_q4I0*REoUxa#lL;oeB33M+76Dpw0xVt`PF5$@E{oVHR~TgDmX z+G4M?28?OB!Ywxg=PZiN(3=0cf8RPwtbWaX|LK$!<>h}F^1m!~x;*vXlh_Ms*l^&& zgO9MQm5PXEU8h+a6E{PD48kZhVm!9Tj@TKyV=wHFgKz>)#_2c<=ix$Jg3EC=uEkBb z1$SW{9>$}13eVytyo$H62p{7!e2s7M1AfMD_!BF3TAi>fyFB z{zJdwxC+1NH@~2ae>)UWMt3XqSX&vzn?ZgP%6r^xH7oT*-gM!^?ERk@`>khF)-rkh ze;1m?uJn)Hut(S4sXdA6y3iU!9E+{6HO65ZY|9w19dQEV#YEyHOoqV@*r{u;)D+_H ztV{nO{?fG}^(!%NX)-OPy1c%unlt)kdC&jj;eZhh{U#1=Y}mTxYtl7UoJXnSJDC4? zVe4eJ36@v#by5B+KJ;pEW9}erMe_``#c$q`S9EPl-mKcr^ z7>NdQI-0mQIo*f2FZRO$w1oqSfARd^M2oRBg%Xsa6FQ>{x}qDpqX(A3vRDqwqbGVH z4I2(zc<>P*M1&X#RzOQFE_ED~X;9R;QZ4PNNE^(SnwOyBSBdcIf&E#jw_KK$$!YPd zFh{m!WwtIWxy-TX>OXIMpl`IkPj=I^vb?6M=muyBNBuH=-+Ccst&`XPpCkVZ$=&mK z0WacZ^7;z#G5Yx9#3%417T{_A_6+eg#)#L6Z{SV5g?ISdyTp5$?>^%FcmNNg2@heZ z^VE>rz2zW!=8CcoZ^V+R$L3L`s=9bJQs=q8-!cjn-JokuQS(bHIxM<%o!-3MoY*b? ziSrh_YN@yX>j#Y)Fg$mZDfgL+Uu9rf+55lI_pO&we3z;1{Qo25e?EDcL(Xm`&c$uG z9e3bP+)ZBZA%0Fj|AP1>zQQ+*3yX>G@%;P55AY#A!Y9o0DY5vcZ|ARhmD15*Yc&jL z?FqT6So$hw*S?)4$UQx@k#F+nHqvsXcW?|Sv*^vK@95%R%WA#xT=UIqs;W9z@3)Qr zgT~N3+TN=8WeeHQQeq|9zHhyfvO4GGznuJ6kf%yip&B))MIGv~3Ax;q_#k8tPxC+Qhr^4uIX z#nl__i-`Je`>`kCJ zQTxB|T<}cmAe}3_-R$J%%3JIXy1&)7?cZE>b^DvE*}^kLH*fvbbo2?Wy!?-E9rRje z?x3}oSh6yGpPRk#zHQ_G!Q}rCa&;&U!{ImrN8%_Pjj1>W$Kp5~j}yu9NyOE=O|{lw zJ8Vs?g|)E`*2Q{Q9~)ppY=knDqXLzvLN#hoi#pU}V{C#=u^Bc;AM`~(^v3`U#2^gD z5DdjIY=JE?93wCiqtJlSXoN5ZW3d&s#yD()@z@sIVS7x#L`=eD80>%@u@k1Cqjhku zH5G)m{MUAHU6ECg|JHR!F8?(hZS!Q#|1Ti-pQrN5$=k=uEJ$v!Dz;a~zUr?Qclzy} z`&VB7?>DG9Q+5ggR?y(#XS=?_Zw-~+4>zg+O+CBz17%r&kB~5hw z)JnaOSH_s^8YfdmZiUm~DvITpWpRh&w&fTzKC^F`Uq(m65oOF~i@UXq|I&`A(cA@R=irug~_Q0Ol3wvW9?2G-dKMufw-KJT`5Rb<+ zoQvtW7+2tG%*7pe1drh*yo&emA^yVOu)4F&*lniuF^@mNr}zw?;|qL=ukba#!D4)i z@9;f-z>oL|KjRntir?@%{=lC&kM}sAcmXa%yOlMXga54qY*h`XRyjFaG>d~q56Yb` z;PxN2wan8|Y>oQBhJ2F}D;SW;c&Ki8J4%F3#0ZsgKI&(HMD=B$>rdtdRE^4r$uxjE{VVu!AI zG3txn^nqgqgW7goa&wdyZ8fd=FK=m}ZJ(sPgYArL{^|SNpsgVPXOsVPsN>hVu|H3I z18?Fjyp4D8E*9baZhQ}vcqe(ki+DHg!93iH`*1%Vz=LSQLwFeTyDhdJB|c8xpCCSo z1$YWi;~6}Q=dcjZ;|08kmRz(KTecLd>-jQgO>J!ln?lW7^4Ztcb$HI*YTZ`MjRPHh zNh4c&^B_>wQAcgv1!;bLb@4A1T6y^&lx_2Q>F?ms5&QoeXZybOVah7a>;Es4|5vEv zOUUV^#LI9wX5vcv`BlVJ_i0uMV{|Dxp))kkL+6C<~_>7etooZ0XH)Ay~93$OpL=uX8@KUJtk z4Qf$`dTfkMuqigf=IDdI=!gCofPolcz=fEOi!cKh;}Tqo%Wyen;tE`et8g{0!7N;h>u^18 zz>T;GH)A$#!5rL*xws9t;||=3yKpz|!942oLE^)B91HL!zQmtcz6aw4*1`JN2o6QMc4F8Okvyj-{HRA|IS~+w|+By-}<^R|1XmNm-q}X;}yJ$*YG;tz`8va zTkBB=Z*^a2z0LGHco&QC9^S_X_z)lAV|;>7@fkkH7ubMuHl&<;Dd#?>@5cjZ>fSr` z5OLEU3$4xg`{w8aKEc42`=ap0$U0W*mE}c0cV=bC_x-trc4Y@Yq|kQTo!slIDvKRF z%NE?c2o)XNR)S-xxsyM+R#5DFVwoi6mCZe)|2J&~&$N#J)&IV^v5%QO_iz1?YHLTW z+mYE_@7!9e_>Kn;|wmeJ8BfBu|pk2A+^-e@Z$(}w<2{y%Rk@*j_~_y1zuZ!Ip|{_ESr zvidRJ_QwDW#2^gD5DdjIY=JE?93wCiqtJlSXoN5ZW3d&s#yD()@z@sAd-O_OMEt6I zll3*@{x?{RZ}AcO{I!M>@`(0c(U;NJBg@bgvH|J`p@BW3`0ZVoMzn+7*T)@@Q-bU}-zl#6RKC;(; zvhL?*-v#&oS%&;COPwr-O6s(V_y~16pE`XMkKqZ{(N7Y$XB|C(zfZ&@OoqV@*bzHn z3UZu^0BnKG+xgVSgNe191=z#vwQqhv9G>fs1K7mk?X3`kyhgGGz_T zHb7-Z$I@GS7e5(N!3`bjiyt(|uBMw;>3pN_pYNMLowsd~+XN`OPnWm;@92vHZO8vJ z`S0Jdp|O;0xFqw#ne=_@hr;iF^(6njsM9oTIB?;?M}QFj4}13k9YqyCdi-V*YAB&6 zp+$OUchjlaGzg@TgkFLQ2nYyB2L%CX(gmb9=>j56L`0;CG!f}tI*2rBQr~xGceA@d zW@nP~f9JgO{_FX8H_Oc3+4>^|0wXaBqcH|wU@XRAJSJcwCSfwZ#1u@$G&siO_4jGP zSL&V16U7cOqL#j%*=v8>!lDd762j&vtVxS0Sbgcgowr0lqMXoxJ%JpB= zeeuZo`oFove;(^=LC$SrA?c!=2DineOLJZj%Se}F1-`*btio!1i#7NTYq1XNu>l+L zJvQM7Y{nL1{}bs}{ETh*1>3O$JFyG9@hkRVFZ1jp-H!t}h~IGtf8a12)~9>{IO~%k zeU#z!LRF9LQ3jM7EYqe|JA{&|)M_PfOZ#F9RXKbw$JE*ksh=&5NobaK(YiHX)m?k1 z_{)XZ{!PXZ7dsEi^M9%P;)xqi0=1w2Jx=^ju^!LjDsJFEJcp+z`_;&Yf+!9@R6u3a zLT$X`IbW0_EsZiLi*hKBik^OMl}HPD-W7#Oi@+N`@I_G+LkXrUNqUa9;XL1c0e|5l zF5xn+z#-nRy^Y~fO3F@%d?y7XssyUvO)0NCqlvNiHw*;3s2r~Wj-7*j-abdq!4Jo?Qsv)A6I#oyHd?$_p%|5UF3qwb5R&i%h@#Q!?$ z^#t|(B@`^Yg&E_S{XlWpTJSaVjZ($-#`bxIe*C&op-w#@4F zT3KdmAyhvHlx#b7VJ))(s{Iyw{3$zfaaX>`@)H7FT=XJ|dP?0FFP)G7+#>$}5SQDy zgS)tg`}h|R@DPvi7*Ft&e%Le8D#W-dv8{&cFu({C{1Jda1R)q92t^IlL>(Nk~Qt8lwrCq8XZ_1zMsNTB8k8(H8IGJ-m;0 zXb%dZYS~OHq)u-v+aRK%v;i(pFgnCAP<;$4;S_(J^+-AX!?hnGmwo>~BmGE@GjQ+5 zZTqsweNpFak;~3EdCV3(TQ2SQkVk~hP8oSj6K?mN@`y=D)zt?e501M$u;&qEtyelW zBjj;K@Ra1V-y-LsJ2pB07H&`Md1Ro}3E|mZxIJ|$iH?6L$Ny>j5Z`M(aHLVQ43 z?}$$5j1SQTUC|5O*uH;6+8sU66Ca~D^|v4CKzxeNFdQQ>2IDXtv#=B^@Ez9U2W-I( z?8ZJE#1S0FDV)V+T*DpQhkGuzJ17EQR7N$_ML3et1RtO?2I5mpz+`-lCHNkju@47v z9vAU19wA$9wr41c5~vOnA`p#+h(`~wQdO_LcZ`GmJ>`V)O1SSTkjvWxxC7MwPwBi% zD`Ocb9}-V}lG}bE$sb=}`WC7->3->h!U7pNI>xjNClq@(7CDBJyl_gMr?eN;li`70r^YJ3^M+x!=O+ ztKa-X&fPk#i{_SjotB(Y8s5y#=@W;%)$hia=ZZ{vZPC>`70i(q{|uBiW&AJdzVMJl zDTnxfPW>N2920WS7m1XEMo2<3QqUMp&=k$k94*iitg0@ab|y41&=eHR4Jhh4)1R~!L~G_Q@8*b$2v4@%V$R(=JmXM(1Q*BnM>b0` zDZM{iopMz&iF_rc?u)FF)A(Oki2qgAUA^3EM19tO3>qLdx0hQSX+*C1B9itn3el*C z`iMaTG(;@o5RU{Tq7jmilIwzKO!_bF%LBgWAs*o|p5Q+`#WOs|3%tZD2u_6^IGNOMv@(gS6arX_=I9;+0jD?*DANmDb5! z)NHu~SPG-R(bYCR+_KEpHpbO8-1hie%Dw%YD4pppz2zU2`cK^#Ii0uveTjcR)?a@N zz#!KDC!|YR|I0|1V+Fp!O02?ae2X>s4r{Rv>#+eFv59vpWey18iUlr6bg_+bj=#S0uEd|ZFY-v@9f$h=nD{?o{r-oic!uYA zftPp%!FIq665Qc|EXa!NxrJK}QqSBML@v_Y$b-D_LO$e20Te_b6h;wv!w0@7Mn1(! zH?aNRNZbECHeoZ{{2%3QfvcCiB7;JC)Plj}V$^SPvTduaGq~(#%9)!C4CEQ$&;3^F zi(-9dxNUL`ca^10sw@7su_JhF2*cgEIE=<3bNvU`eu!cY`~Ml}M+%X}65u zi&!oo(b&OfUv-$=6}9J~Y|oTDw06zNUqHwQLnM#a^3YeW$fJ*tvc8r_ zwB^v8#4UwBC(r$hb!##4xu)UQ=ojc>6A zYpHkZNN3Y;n?pJm^DrL^un=Ek5f)+h`nD5HT>`HUCfVnZsgblaq^uA6UW-@~xZ66&H~FXwJ4 zwMG}cinQYkmLM{Y`|H2U`EPstla&f$|0X&y&Xd0Jm(u^I?u&xX{r@nw|7OPZ z=&XBy)*hX!i-2u=7M96_)Gu&#*gnXmGTgF_QFcr@gXy9GDE&X`z9{V6|36Lq&#?Z^ z;v6op{{JGq#QMKXdIeW;4cBo4H}N-a;UC<_9o)q|+{Xj*c}QB4exV=zx_3|trBMcD zQ4Zx%0TodRl~Dy%Q4I$Ag+|gh3iMk(kYj2cbSKnRU9$F`tX(gL(0ogN_K%d(V(Dn{ z%sBh!Z+mCkv#?CAezw?JTC6#{x*pSB|K<4G_A|7VcloHFT=#{yByu^l|Nb2R4PgBS zA_&0Yy&dU`9A1iBA;iuk_pZu&wwFd$FJX!vWHtI99in^k;0tFW8Qq z{QEA_Ub!cV-puc~CSB~hIZkSOF9*oFDRgzo&FihM%OiXCyj`7SWoc~Ne`}MjK31SS zy}T{59Q|=MT-XJ95~VK(MqF6LoA7GNR1#$t{;E+Ork`;h2I zIv}^7+d$G!`1@1R!5D(iFcibUYP4VcVG3oiPJ=N-^&E+^)-6*S)UViexSr3Jvs(RE zG7c~W8cd-s9>^pTW1`Fv4Q-c}Se9D-2@tmW@3NrSYK23pT>nYk7bPU8@jr$W|Ib;6 zBU$gGNXO7#e?dAH<1ii*FcFh58B>^cD(Ny}vYd1UzQIbY!fJerHTVu|u@3980UPl> zHsJ?s#*f&7pRg4_V;g?KA=-#PNR#q#UIGq3%lcNm^?q}DK5@9F%V-H07wo)sO65a` z5@S-2l88<_W^4(n`ms5OjEydiF5BZz+0j|zmHmHqcSRM)eP&BP(s9RIeH1ZyRd}8h zQl8h^B7OaD_IK+D$?LT|^li_`2z z{)UXiCO5}JyzO~ppg6O0mn=HB^TIMwsA_00bfk!3aSpYM>@+!O!~gH&Vt@n?yyV zq^6j|W24-H81B-=NQ087skHr~l=J>y?L0!%A@8~fgBjt7KqR6Nje4k$7&Jgb#3Byy zNI)VQAtld5(TX$`9q}Q0qBlOpXBdIe7>`Mqi8)w;<@gqBu>(7?3%k)c&wSB@v?-dQ zIa;74TIca{YeU*L&js-=>3et|?a&@Vqz$;tskR^^n`qSwi+^zrxKj7aNFuvK{qI2hKVaQ-%H!wOnY2qD;ntP38$LpJ z^uWjbdoR)zc@BwhNLOMNR$~qS_8sZmJa@%B()n0`h4>nauoz33ZW*cV=gI3gIFx5; z`iHpa(%3GO4GJ;_LH$Yzd$yr24vR!bQ-zeRpLH?R!z^bU=+E6HJOWg`JXjCTSqqQ) zzPUpwQ@>!%pzv9NyiZP zFG$B?941iLCXx>2^I@dJ@i|83F}RH)?L%4UOWF_pF#rQG2%o@K1~jC}))-k=z4}!+ z4l(jqJy)O9EWELGSKXSi>Hz<8zSh#`>Zl$Mv$h_aRZ6SBi(4}sa#p?ipXzIU`OEQ- zj<#KwZdojY`aw_S`R~+yQNeltZ!qy6LOj+H$MvKeuo2&56Mn#E{D>|130v_qw&53S z$FH>che-d#8Jx#OT){2e!6W>KSCI0ujfN+Rq8P5ywqN7luHy!7;&1#zS-VYomv;Rg z>3#eQ%8qTY-2kr9;Z7L!Oa7IeZOfEKSEu}v6YUK;`*I8`}Dbia}A#XjuE0UX5d_=D*VliJsUyzG`W8|dQ67q)^< z+aK&7Vp2a~Ba=Ximaa{Tx=H~uYGUY^%T zng@B|g?z}50w{<=D2yWTh7WvEJnuwNg0v+3@D56$G|HeX%Aq_epdu=vGOC~|s-Zdz z$jDeKma1oM3|tQD?a*@YR1bR@e%rgWL7l8o4OQI?IpoY0W^c>S{#jc6m*bzdm9hQ? z^`i`A!ufyB{fk=m{r`;YN3fq+OGqW0+ajHP5%Op+BtPdolzXA%%Al=BNFK|CRLVII zrA<`&bDH`J(Nk~Qt8lwrCq8XZ_1zMsNTB8k8(H8IGJ-m;0Xpau~03Fc@o$(>M zpet=pH`0&L9X-$!AEOs~qYwI`ANpee24WCC!KWCEA@~eKF$}};IYwY4MqxC@;0uh! zIE)8_u#*1}4#3MY$6a0s?_-CN(DDkK6ivZ{NKPCRp z$on~7;3Zx`cyW9U65Qc|EXay%$c`My2~XrgZsb8;cp)G1qW}t`5DKFRyx{|16h$!< zM+uaKAKpPJltvkpMLCp51yn>OR7Mq4MKx510Y;eMj{pQB2*C(JC~BZ4YN0mjpf18- zMmQo6i6}&)9_k|o4bTv=h(kOQkcdV|LNZd&7){U=&Cnbz&=RfC8f}n@ws;rs;eE72 zrsFTy{UGP~x97H?4&?m-I-(Og<3n^oS9HTi=#C!fiI33>z0n7K(GUGG00S`ypWssr z#t?jlp%{kY_#7iJ5~DC0WAFvWVjRX}0w!V-CgV#?!BkAcSD20&n2A}KjX9W$d6#*bWT*eh##Wh^V4cx@vxP^ak8+ULQ_i!Ko;sGAw5gy|S{=-u|!*jgAOT2=} zM>_=x?(jesWJNY)M-JqKCvqV-@*pp~kPrD$00mJ9g;50F@PRLiq8N&!1WLjW@1PV) zqYTQT9Ll2tDxwl9qYA2`8mhwpBTVo|00I$&V1ytPHIV7}%XPnobNp-OW0!!uYoiY8 zA`E7PBLb0#LNw~3K4Q=S4H1ht#3KQTXoMsrBL$7o1WnNl&Cvoa(F(262B~O^ckv$H zM?17f2Yi5z=!DMr5M9s}-S82*qX&B8WAs9A^g&GMiVqeGc-pFv_vbkMjND}E#Ad@ zcpvT19v$!jI-(Og<3n^oS9HTi=#C!fiI33>z0n7K(GUGG00ZG?eYv;*{jDWHiNDnauoz3Q6w9z2EAS0gVii{7Tdcu%Sc`R7j}6#}@39F#U^9Ni z7W{;*_!-;q3$|kic48NH<5%p#Z`g}{*pCA^h~IGtf8a3w#1S0DF&xJUoWv=d#u=Q& zIh@A@{Dq6Sgv+>stH^Zx<+>l~9RF*?|2lc!z)k#(TlfdJaR+yC5BKpe9^fG!;W3`z zKRm@VJjV;X#4CsbZ2KU=9UjPntjLD!$bp>jL@wk;9^{1=@*zJ8pdbpNFp9t%KJZ0R z6hm>8KuP%F9h5?8ltEdPLwQs{MN~p%R6$i#Lvy5tA?(Ut$WTVj8}}bj-j^%))HU!CcJ4 zd@R61e2qm|j3ro#Wmt|C_y#Mn3ajxg*5Es=#X79V25iLl*n}Uj89!nRG97=p?$>vY z|4+n!D|!EnZTJP-u>(7?3%l_v_TV?{#XjuE0UX5dID|iN7=Pjjj^Y@O;{;CP6i(v| z&f*--;{yJ|MO?yVT)|ab!*$%iP5g~p_y@Of2X}D~_wg?t;2|F2F`nQ*JjF9S#|yl~ zD~N)$Q;^^e4`e}BWJ7l3Ku&lf7jh#H^1=)GkRJt55QR_}Mc@q|_@XF^p*TvQB>eCW zN})8$pe)LvJTe`Bx$ZY`j(>%MLR2L0N~nw~sETT+4g-uZ!5;w#L=b`zf>6{zP1Hhd z)InW@!HjT3AQDlCMm^L=3>u&zViAXUBp?xukc4EUpfQ@DDVm`ae@ z-oyK7hxX`z56}^v&>0`13%a5kK0&(Ug(WJ=!<^nj{z8nLHGopVlal_GYrKr z49Djffsq)6(HMg-Fc#x59uqJTlQ0>Xj=x;@+!u?0V2D}Kf{ z{DSS+ft}ce-S`!I@Ei7GANJz_4&rwl!XG${KXC*{aSX?C0w-|_r*Q^naSrEk0e|5l zF5xn+;3}@+I&R=5{>Cl*gWI@+ySRt@_!kfG5RdQ}Pw*d};u)Uf1u_$VW&fXZ|Du&7 zGM7*OfkLX2**vZaDJ+wD6lf%*@XY41MM#mE%%fm=Aw_34kI6!+pV>TK2&sWc@1^Yj z$!&k4bNzow{eMN-5{20IL4rFxkOf(h4cU(Nk~Qt8lwrCq8XZ_1zMsNTB8k8(H8IG zJ-m;0Xpau~03G3Hefekf{IA^hCppKzQz0QbllO<{g0AR>kI)@G&=Vh{7kZ-)`l28D zV*mzX5I(`D7>ptK3_~#t!|^#rU?fIiG{)cyjKw&N#{^8oBuvJan1ZR8hOaOkGcXgg zFdK6)7xOS53$PGhV-Xf(36^3RmSY9J!Ah*cYJ7_|_zr8a4(qW28}U6h;RkHSkJy5r zuoXXJ8-Brd?7&X!!fyPEJ@^fKu@C!k00;3q4&e_R#-GS^{N=iz;vD}Y#Q!LHAH#8+ zz)76KX`I1XoWprsz+bqCOSp_HxQc7IjvKg%zi|uy;5P2yF7Dwz{>1}4#3MY$6a0s# zc!uYAftPp%QJ8iL65Qc|EXay%$c`My2~XrgZsb8;cp)G1qW}t`5DKFRyx{|16h$!< zM+uaKAKpPJltvkpMLCp51yn>OR7Mq4MKx510Y;eMj{pQB2*C(JC~BZ4YN0mjAk*=e z>wXjG_}48gL>PIS5snB%A_~!{hx&*?12jY|;t-DnB%%?Lkc<>GMiVqeGc-pFv_vbk zMjND}E#Ad@cpvT19v$!jI-(Og<3n^oS9HTi=#C!fiI33>z0n7K(GUGG00S`ypWssr z#t?jlp%{kY_#7iJ5~DC0WAFvWVjRX}0w!V-CgV#?!BkAcSD20&n2A}KjX9W$d61#TtBvwOEJs*no}r9-Ht3HseQZ z!B5zVpRo!*QIzNu0uIoWWU~ z!+Bi5U$}@%xQr{fifg!z8@P$TaSQ+8Htygq?%_WE#RELVBRs|v{D-G_hUa*Jmv{wH zgmwxN+~I*N$ck*pjvUAdPvk;wFHw-o<-( zAMMZ{9q<7aA|_!nzQhzv#WZ|{>6n3;n1$Jx zgSnW8`B;F3_!^6_7)!7e%di|P@C{aC6;|V0tig9!i*;C!4cLh9u?at5Gk(Mt{DiIe z8Qbs+wqpl&Vi$JfSM0%W*o%GGj{`V}-*E_k;4uEg5gf%a9LEWq#3`J{8JxvAoW}+H zg^Rd^%eaE8xQ6Sv0eQbJGx1mU|2g+Bx=ESLr%*>B#b-8;KZTT-$vg@(hCotg^H?sV zluYJPq@a+RWHyh%LTZ-TJZ=c7g8EyjNwZ;!u8b&QmBvQeHh@H}lpC}l(7nPrRCwD;qeZN+4IQoJrh;zd1PR}T8R8ycTp>oc@*T>O>8Ff zC_?;Or57|IiMp0;|9g_t^Z#zr{{Kz;a;wNh@ek>3+`(Pk!+rdV2Y84_c#J1ZFL~3a zL3Vf|5AwkerQwet)I~U=P#2PJhw+$z$(V}in1zK{jAi%+tMMH+ z;slXi>{>IklxCQNRCUk-OO*~&d(tKAQyLixfr6||z1N6!r0cN(-+PC-Z6bAEez{pO za>r*70|W%C+#MHgj&Io19Amvv+&YKRkp7)|4jD80mh+d||B5z8q{K9ddNXHZdeI}_ zWH)P>2{5Jq{g&@YO>7!#o7&%$?qb*$C@uaW))K1x3Tpv%(TGaIM+oY^=-@p5$2Q{s z3+sJ5c3>xVVK;uoMB+4w^h@u%VhZVI?``5o(x1EyZd*yG@$X-e&fwo?lFsJuIizzj z5Az{-=$ARAak6!+t6)aw3iRiuXWQ?3ORD@bWx@bssH+u|*wi-Sl64OM^ulBPCdcTj zK6fQ0@r~Fs0Q6gy*D+)3LKt0bO%f7q<<$~G&EtRjheXGklj~b zq3(;0&iDT_PIOyAnw2`6jWmZh_XCsW;_uv~dHLImG=^A< zM8Lyw%a%j`KO|arg_1;hrS6N)lmUnKzX9=Y zNGxL!Ph1m78xiLu(iHw~Oq!p+3y>B>ArwXtc*6(2D2iezjuI$|cPLk-NXvK&x3Z+= zP#zUf5tUFGRZtbxP#p#sWzLZ|sFiSszz2n@_9qh~VjJ3vtff>@W>r?alDDO72L`It zezJ%&Cq~5EMgXj+MGlFl^a-EgIbPr;UP18hZs3MLHxE)}H9H0? zNHth&Ic%E^LjaHTG%*Z^N~A2qY0_5+WFY837rO+pv1y$=>m2G2>~zXJRBh`e{H-O| zk}nIRvdqfLuud4HTDt7i)&|K#S$PUBZvw!8kSWs?1WuKf_7+V}tcZT(1P$OLVBIzo7N z6H;4;WrpvEgKKKKq*HR_{$Dwz?H4^Ik=3F7zefGPPMx}e zoA?{IaGU=99nzQV_q`$&)KND`aEAx7AS<#VJ96L&b@o4|e@1)%ob(U=K1}*2j^HSc z;W$p>L$z2`pQW8Q1<_6`$aG3_CFW9 zh53kELHM8;Dxwl{`^*=4Nb|xA`F(hnGih<33!(&RN%-L%ltO8gL0ObTc~n3lpEaT| zX%TqCmwbwnR`!`Fs*qMiHB^TXs@wOs2TG}H^1~$!JVi-;{`k0V?5A_j)255*_#33Hd z&>St$5($*IMAAk`LNZd&7){U=Z~bvL#K-7`-spqA=!gCofPol%)~6r#vIJWJj}-eEX3DXgvD5brC5gLSb=Y_605Kp z-(n5E!&LE_S}trgMBl{SPsiXkR(v|a-5=yU{^wode~)#1AOGS39^w%m;|c!5Q#`|S zyueGmg7BqZ2np`+Ko(?0He^Q*Yy&dU`9A15Q!*6qaNxb1`W^b@A_9RHRK8Q+TE&>C%!ine$c@8Ny4 zLwj_<2k3}S=!_511zq7syxt)#h0-X4vM7i0sDO&7gvzLbs;K5`aH~#gK&bB_QG>K5 z{C&gR0!RZ9gkXfA8|C36((dR1*1yK8?O3Y<10}g{z-Z2a2F3z+{3oaPuBULCJS0eC z&F0IM2g)*Xt-rh^mOs>HPm6yBN}CYu|8wn!7;E4EXFtNa+hpGbVT@I$pY!G)-sgqX zUD%ezMR)tn*_BUxstc*7J&!;+5c)c4LijWlQZIWRt`_^POX9OzNPW`s$jIh}<+vlH ze)c>v6dT_bLKj z0T_ru_ynI)_Xd*=!DkqXVVH!;_!3hv71Qt)reg+XVism&4(4JWhSP3*PC5c3F$$wG z247$-#$h}rU?S$T91BPn;%h9zVl2T@EW>iFz&BWlRalL0u?F8^E!JT@Hee$%umeB= z=8@uoMvhNw>woA}K?U^9Ni7W{;*_!-;q z3+sD3=??6~F6_py*n{7&7yGcEX%CPd#P2wSKX4d-;s}o77>?rvPT~|!;|$J{$2rpT zxPZTK5tncoS8x^Aa2+>r6My3t{=seB!Cl!^u+;q#&f|aoOZ*?OULN8R9^(oA!&5xNbG(30QI6f9D2kytN}weC@D56$G|HeX z%Aq_epdu=vGOC~|s-Zdzcu70(itiD;cY_3XcpwY1A{(+J2Xev_xsV%qkQZLahx{mj zf+&Q-C<1R7iw+ScQhx*>5J3n=2trWmL#lY|`4WyStf8 zfjm)=j*nBM(*MI2e;21r-%w+yqn9ch+n2UM*J)d*|-nwA_!yo?NX_+(7AZslq4(lf^{u$c- z*HG&ID_)Mze_2TUza}<|uoz3Q6w8R)a?)?H2H#-?b?qC{l~{$$IF^ zcKE}0qmYJ(v^+AjEWY=JG&C)bjBGuHC~6kcaC;sZXtBv-gpfwq^T@?fmvBIr9}sCHo0G1s(XvW_37`(FKoecEiHMs3}K5RHeG3KZFLG458f2;q+m;f9Tvl*4YE&VsGv$301qA!*R(115H6je}C261stZ= zxi_eDS5S_>zT=Hb{Hgn5y2Q?{{rI1ek5Z`nO^I^@>VF{b4IV-mJ^Vxs4}+)){VyXq z=y=IrsND*bx;>!Fe4lhFi{TDeVO#dO@!*3K1AQ-!TKf-(l>dazR3ghP42I6a(@)&b>BqCZ zy~L_K2C=}?@68_?ldNxzM8qcPnIT+mnDo4KE{>23zMhxP>GhSDm}q?k#%$IZe$M~X z|EKPYMe>;d`}ThytKqBMUSfXkFtGp&F+I0I%)m^{g33#0wbNPabXE(UZLYq_^#xR4 zI3pVB%Uzhm6Lc0|A+i(oSFgl+&i}FZpl|n`t6Z)LX|g=0wcn|AkB=))LWDGh7R#vf zHwxiVQ%KX~wodnN^)Lx(x;&@e&6Mzn71B)R)IFo{;CId@GI|?EAv`&PJXe?_8tSY~ zLgbz$*k9A~QtCf#zgQxP;tutHc5Wf&P{-$D9`4Ww__e5?7$f|Iue+Zp=I&zuKQ+0& zIWnQC>k!E!DR5(y>j|wtr%`I6_KBG%LD$rBuUE@@OPfY#gR8Ur=wnT9+rzE;Z@84u z!_8m5+}gzLGU-pQ++Zm;L>wsz@K?F<-kcoOC|P^oAwpl%Dpu6h4cO2Ct2iY#CfyWCVmo!#B;GmZ0G$h-oN1eUfv(z{Y%~} zFO8dUr5FSRaO!*`M~;(*7BKNsnfW@aV+ZT zj-}=Fji#Vqyw>m&fBOH_eX&v!xg6^MVb;r0;(J_# ziGtn+@tAGEM7OpgAnzLSlyb3_y1&5|d+SPd_}wOzW4TVh+!&N@TM%b%7LgF&MC(s+ zGn$NnoTW0Uj|7q$qrK7KZd9c!rSBK0|CnJsUEIVjPfeCyV&oN=$%LCE|d# zHAt@|O8uwqi`5cQwYUEj84_-E4nOxoZU*sySU)D#Czzrjf8VCFIPmAWt1$ajL;<1dJR5jQ_~H@Atxn>42z z_i&JUl9nRPMOvCPH)$EtJfvkw^OBY$m6*?m)Ma6Cm_TFmDl{L|(YQ_GK$pW(sJzv> zfErtC<%EjL*QNcF*8BwV=ce?=u_>B6FUt5&)P1p5z7yOYe|O^VOZ+^DV^Pv9q{T?H zk`^b;Mp}Y2J84PM9Hf4v`Dh=mi^Q}=S9{}FWkU_dbTal#6u%EYk+4p19Ro;pMg9 zumJwSs#kG3Er7r3Fm@?Pv6?GC%Rv24Rz@YTZG#M|quT=TxW z5bniIpy|MN5OFO5z=aTP9h@@sFM~N7Y!audtGqmojEB5{+1tU?FgyY zFy=fbq_rfjUrPUvwqI=G{y&HIe*lMtBYeZSIy8(u#39@z7)D9)b1&=`Cd#|DrQHbQ zdLcjep`@-}jgupzV$IDphBw6=9;^Krj2w(qOP@y>jl;t&*k}xuuO)f&__PvqOXn;k z)a5FSONi9bop%fN=RPkj*9Yj>|6s*NCq*^VxZ;?avXUBM*50|5@BhoAwEbeUbNq*M z{ZErTVPXem;2_6*+7jnZ#M`r|pL;8@Mx?ThXLKX?mK+DjRWwn&%ioMtq(;%l2XmF8rP7vEJdn0KDlXBlIt%gLTo2APNz&PVj^Rs zQYnhs)`B@QlK!8bmQ6YSOWhY+oR9yt=Ih%K(}}(YafRc4M|}+9n9mT#d1xz+ke1O< z?=8Q8|H~^qIgwy$io5o_#!-8&sgW`D>S@oI6|O6yso~92v_(@{e~sg*0!hi{ zSS^K7j(@7HifNgF`p^C!bzf|SL;Jsk`oGk-yI9V3p2xYya}n*pV*Xx68sO_CCa|^m zn)<#H>+mCXU?2X(8Qg%znwC~nV$DgK_jZ+;lIu6rQ0;B`YcB=#=OVNh0ugJD({VH> zIYGyI(Xq^C!XFdgM8|SVqN`H(#Wv^hzwWTc9umJA?9+uI8nH;i37o^<2MHn1f$%1vxzY+^eDydSeED!Y&-gMLfn!WXVFm0~JvNZ7>u|uo@e2 z3NKMQEBPV>k@y&Q@e-cd{M@}!6A?&6OSDH9^uh>?!&J<{Vywa@?7)5;#W`HV9X!M{ z49)K6J_$3h5bLlLM{yC`I99d?mAHnYDh%*P5JE8>voIHna2nU}6uCV8-1DOZDxyCI z<8yq08DRUbb<1X}57hq#mb$-P9tqUG|G$jW0&B^0Gj?J>j^Z?~;4VCJu|81+VMswo z48lY#!Y1s;1w26Z+ui3ym6rC5VMa2A*F4<1A0 zrChEh9u4I5)UPJmWX#%1?z7T@DEUZD*81=YZ+ zh|#s;m_c9JWrpT@dMZq>b8>2wu8WZP2I9~DpIrA3I`9AW%1WJPy}Uv$_HBGn3z2Aq zR_K7P=#7yWk7<~TC0LCguoDMx4CiqjcQK58qRE(vudyDxa15953;RmHp)&1GH5d_q zVAQ}2%*H${#u;44GvsFfqyS2y5(Z!hMqn&vVma2~N9@7@9K#u0#XV$UpT!4NVMb$g z!Y7!7#rOdS@E0B;2m3I^VMG+-Fc70K6-&^D{guw>g&`P)iI|OL_zs704wrEoPvFM> zO-^{QPm&W}D1|@}f8AwRzUou1`{I!E{-4=fhe3f#y;ekDLt?Ezt_Cq3fmjoT!qk#%{TF3G{7dbR2CV zf6Zs+m1WU4b%x^4{vUN;9F{~WhxWe>AEioRJQ^-cyo>knKH8x@I>7Zy-_08Onmc_> zoxV=7zKeP_UqYa)FwNHyC{t_P{j`RH`ft#DRe>^(eAka$_r($C=YM^`M;)awk&ilC ziTYX-zWm*Zv?yt3(qg0^k`^cJLRx~fD``p6Zls#8(-F$+|Bo82ueIR*OUug9_J2A4 z`g$eG{y%kJ9CNP!AMsIlDNOW0PkfAC=#4(;3)e4w%ksai#hYtXUu!}9jrv*)Nfc7* zzBuK4|93y)pP#y4nR;9c1$bYDv^EOzzA9-Q6ykj~(z+uvv_uOq^3_HWB1-OuFs>uWKT<3C*cBW_CUkL%ro zXVj;ALfVsoeuofQs|jguhUWAR6w-cqPJ_;sFQnE&I;hO4udQJ}se_OX$#WX@ZC{y_ zqd13^IrX)M%-L5+N8~wm)(_?k7t*nGONrw@DA)hf_KP#l&wuveqX_D3By~3m(Wr;| zh{0YTFR{<3yJJ>P@53Wwv>wE5m>iiZ4>+ZH2Aw5b=W5qkGW2y?^&QUTgr4sDudnOM z{y+VH+J13P5``W5|BH*VH_5sF;YIxz7s!jV{ap9YaiCmTc*i~AC9|Y={9oVcd!0AX z>%Adb_wBHW+(H+ny$HmmM$|Va`D<^c<5Trr(bZ7b^x?4_!E_4>Hu;Ad0@W`uIY+jiaMAU&W>T-sIHS1a5NGe%L!vK3nCqs?`5z7@4AH zauJ>sQ?GtXypBu2M}3j&zPRjs|Hm9Y3L>r}ICeK%3KN06 zAIbY!ybs|0DBjQHy+7|q^FBOlm>5H9CjEjmjC3q%UD9!+N*rDMPv5?dzHYs~UYovt zrM^DB_HBi{y7V0`kS{INcgRq={+qflt~zi3llbU!>Ugr0$nfCAo^%w3ay{TMG-CUZ zJh(L~Nz)#RCBG2WMHH#^ z&GB5Rttmt6H7h};5Tns(2sEj!r?iV!{JBgdIFRRpsZJeXjyLPuWl-Wz-50kckF|SR`H~1PvZsPukGVvd=&&m6pq}G=;o*^M2Ms86tsb2q5&#Y?~!Ld{Y zx_Bmntyo#hpiy<*>b!1S&sLSSVktJkYMtCD;yK5EEPLWQ zcHJ5OXP=NxiSPvN_bA(nOqP;DI%Dav=o$Wn*`-%PIw$m9MsNAntkFWcpv1y&N4*g&)Qam^1c@D^JPsG6|%5h;BU*zQbz*}Av{nsK>aa< zwkm20F)>twN%dje8E7Z0%b+@5vTYG8(*~MUS_wT{U&~6c{VugD5p4@#nUKUv63kV|D*2{u zr7i26|Eo?Mr>j3>xwOyKO~c!b4;Wyw#vkTMwRZbW2Pz{zvO!I?bJ@$2BaSx#Fwz3O+>M<;ruo6np7V2Qr9 zx29hEZPB+*obEtl@|SRDq5h>%2IdT6hxyILw0}bUsfxB`u@spAqgtDx#Gkq^o;Z*H zw1N0%+JauZ@5}ovlncGD6n(p<%Gy`(EmG0yMKmQ`x5gPychHZJtz;^DG#2s0q%Ux0YcUMo&Ql;p_T>XxS#XC zz4n*&S1^=^DI~~WCH~B(?LeOG3zUTj2sMQUg&NhD!B(eDh9DEi-VCaXk%1MVWNQlb zS8da6C5wZk!AeMNzvC^b9DiN)fjqd;hiiXC9(UzPLrk3Y7=@;td76dFLb_$?ch*nU zv5QAxsw1S^)*g$VGQ^w(g>+Y*Q)jo6ISUEtzC5SgO6vO3tVM+MK%P_QMvU*wBBV#k zoN~*oy$NL9t`X7`WzHmBg^TZW7t+(Wl#e$*Qrdsoej(gBn`^)S=Q3yPuDNsUhx#7I z*dKLi`$K#f^VfHXSj98Ai)ZtDGcy;TBf$8pDtk(iQQARH0I08GxqK!i+cp5!-B#7+MTtLc zzmVLW#{a%d`(GlPL0l#NB}uQ7`jOrwy+z;esjL29s+n7@J=7Q1;a_7TwcilUZ2Iou z)^|ErXXd(2{pnqDU8f4={l7$`zEz`K|3Tds9`4GM0B!gGHO?l)q-d22Z{b?d{gi>dl!>qSTcXbArAx!VaYRX=cj; z=?GJaXI<}nnN_Mf^ha=J4TfW80cPW|^H zz8=}Q2aGfeX@1h5x#njZ*Z(BAdx?VXJPXv_Pc(wlOXnt0?_CZek?wm^Op4Z<@9XO; zlk%P5I%;Y&M%;+gaZpKLXGGtsjEHKYXJ}G_rnLXmeUZz#|Chu^$;34UgNb=5whp(s z?*BU1fOX{@P=EKfP9cBe4?Tr2H9V@G=Ajof4~8f&QoNo>5_p{zTF*c=^5W?1>get3 zh=}_7N|zje+JEZ4@N##0{^tNb>gGN~JoNDsowAr$eLsIH% z?~DZMn>;|@(TnBUjWk6Ydh7qg0(8Onz%k;qD>iR#NXK zAzNM!cT&Ifwa4-jyEhW<*_l(0jGji3Ir|IuoXnZ1vo7&FTMBos>(}s7+JD-9k>B0v z`A@AV7MIz#`wN#4OI?r8-c}^g|4&3CXnyHvlyt0L9s9<5M#R(^Bz?E@@QfH;H7v5R z=3b5*4a!QezP3n-KW#sqIj8a8l8ApYF-}2a#AOc?(ewqba^K%YH!pG4O>6wEN27uR z0)kB3m84c^V$I3PF?!mAn4}0@XVQdx{FRG^taosvf8O7=l=_-d9rtPKxc*Q_r-ArW ze4FUF*+JRUB)SHJA=L2pYXDO?1(=k|LDE>)LyIRxnHk~BjR*Mz1P5?u zklGnQ9zPWvV33D^S3gF};D)JjQQD7;#%n#;q11m%4YHhNP-91 zi{3(9@-~PYJm{7dX>3olWJ z&Y@X^iEw#bH^zjoMf!i(dk^rqitGLV$h)#F8{4vRk!_0Tgu1(0HLAKStg=>dqe%1) zrgvjX=*9F7riPB`9Zc_FdM6Gcga9Fg5JCv$|C!mMy|(sh&i=CBKM>vLIeKTW?%X?f z-Z^Jx&Ye;z^JF7%UCyrut_7|miwu>09d0%(v4*PS6niuG(miwBuWr>WqSe$A>tcgG z$8@yRb=S}ARD4?Mj!j`>700_<{%7in?;yN>M)%p!)ieKl4Om=T7D_3+mceg1yjOr5 z@;e09f^}fM%#jALgx^u{OngIqA8p;8Egi0J(#fpd4(INp*?__E&K;eKG9&F>n&w*D zRClH%R$s5E*xd9-YAIm4g^2C?pXk1<6ksKoUjN_vkhlSSZVs<}`3r>k8v*}~-#4GN z`M$*;_yh9YkcBdszCkdPFMtJU9jUR!rbcsdVkT8-n06(j$}`tU-Ba568rj|0-qsak zeteV>pB1!6`!1+5MddV(Ieqf&ebh`<(Vkvk+v&cYpW(kN=5FeY{b&7Gbe{>{GAWJ! zHvGTsL*~f#*#F((eLGnodw@Go4)y|f#5U{=zRP;x_uwD=X;M}1D=rgi?P{rUogByL z*cK+!xhgczYEydc*s#TEo&0XQtg)-hzB{#3hkp^~3w^V_v;Sqid1$}?M?&F9q=d~zyHUhltn9g@6|_$jvixwB#Qqh-g{8=*6}pp-6*8pVS8?ht{xNQ-j~1_ z(_&Hf9@rQCEeVV@F_mphoZQV47@uw>-B-(6M*>AQW~ZtmqhWQX1STbzaiu&?)6k&V zUahvRrA4PdJo6_BtkehBeVrPL*8lXA+!4rnr}-<)%Hdh4_rGu)fn)$kz1#w?Vp* z9%Nf&J7jyLzoQ&~giCc==6GGH<8@KT>q;E2i#T2vcD$~sEfjLRR52gd*b3cRT9$w6 zeirtT^!;CVfd3ugcPGaD?F{aM>`HhyaCc-6WKYE9__=ctab=>?kuldo5dLpJIKe-K ztHLp=UR;sz27oeaul}vz!WMrZKt zmBXc-YW@G{K8w8J@9Xvd?8~WtFu&&n{C;=g@w*$m2e}t{2zeNBJrtj#=!d$bI{D-h z&BZDvRYXqLEkvdADz>qj-xSv`Bk->r{$cq?_a)-}{=bMUegux6M4m#P#_#hC_#*NW zvKVnbeub4y@^M&%7=(fTF3jWy)-~{ML@SmROT2 zL!3W4#NXQ4dM7fejTKroOMtTVFI(riu03V=cl>&mA`Snap|An}U%dB7@4>ZQ%KA^+ zOJMchm=V{eG%@#-z?!`=OI^DO#5_m>YnzzeDwEC|Px_|>)*+^PD3%2Fk-&N;=5*x- z8$wkX*ucgNtLz}jT`U2xHmZYR#2!nrLu*F!jdOs~dMmRC|)5-ACV{F-iw zF*)W+R=Dt6;mr=-NhRGUP~VDo*u|c>7oh+Cv)!8*&d*Mj73U1FIM`3##Or$yJg+=}Q^H7@*S0^QCI?m-6>up&UT_u&<*#T-M!L?fgZr zy;kx0)I2XQ%tyRv8LLBNT;U?p-PGaK4o>zQ`reF_*`WOydRy&<&EpVy7>QN5Sq!tU ztZ8?i6=hpIhg{C z5v#3MeB)LvLMy6OXr-1NMr&)EIy;^9&bI&1ec3D^E2ruIE`0ypl`(#&7SQ%%Key8g z*z*BAnlWK}7xl=#MRQ~>=l(TeL8gpJp3f^QEs4<6_gxc*i@REz+iIPxw!O3cEE;B1 z9*d&#WiyDD|jj<@mM^-Rvxu zhG}WjsIzjrRZ$f#-rANg9ALJXvtVW_Bl--~cC>Vx5|)g>I>>!q*L%{||LDHd1Y~lW z{)f^3!En4hbN*HU|HOR%KM(GazaXC>Lpe8&{|#Y`$XKxVj?0AHruEur-SyMD8N=XO zfHduCjjJf)ng9~bg8S|bIi~+l>8~N-$-lPgy78Z#6yG{cGs^Oh?n_;O@teKvzv+`i zuE5v(6zhGw!u+q52#=byL?+Mkn=!Ks(pXBW^QLSi&;0fHM-_* zU3IN$uN1yI)Kqu5j|Pml5GyJxGZ;Se(u%DY9Nit|E3RD_?rRpHL1h%?ixFIQ?3c{M z|C8`E#2daYU3XrgM*?NG-Kp#Bk=O$yP$9Kcpt}A6UYz?Run{p^5-mp82Bye_e@S2y zVXTs}l|o;*N&=gin5K$S)M&&UD|{z2%*5@PtNr6W&yzrn)S(VK{ejbJ3DotLGoO&v ze{8>O;hq1n1;t`2bAD^k^Co0C;r)ihEr-a($^pwHgcTRy$n6DmOx7q3p-D$PJvEN$vHWBErP=%a zZ#np{gXe~!3#4)AJgEn(7~@@wTsgUr>Y~uF;B?g2blF9Boz0SQ-X(W23spEgqrq(S z<({>wkJXe2$Ar80>|O8JU0vHbz1!UfP*(%{j;W1jt8M?G`_k$i|7WIzE+1GRm(k8U z7@yzli6I$8J8wGvfKdfK@+jwD;P;n##d13S!Tv~^Uf(f+5q7~utjGeEB>aOO_ZtJyjYTQ|4$KvJ;m|(^5%z0gx zRJG&~@c0-DpA~@Z_z!fSg$+7Z{JxO({=&&WMC6 z$|~61$ImfkX^l_Q^xZDWGp^px2T)f(y{Wdow$;7UX!%F?rQJLK?`HUKhvU`Z_!ju? zAiM_Qg@ii^uSxh;!Wj-ln^iM9BvpLEK1!e|J{k`~>fsfBb1)Qdu5n4E9$xA9@H!Tm zsGZ{c(F5{q{g3Xm&<|g6di(!fObc8Kj&FnG>G1s{_WuZM|5pTvqX z-Iv*vfi(SJu|Q-p{H}nk4A;frYRD?cs>m9gTNBj0epK`7zcg-3ehx2JXG&N^Q+%!e zhp|7hTL4dkw$siSu@@yUMN;j~e)T(9QpH3IY(Y$I&p@Q$bO|&|qOMask%^A0NuV_m zGj1h&)8ik?yHyzd%*rLoN{ot^8{5B) zcl<{w{FlIQ6luhNIV>OI%hdcE-S6@C|99flE&;~-VfA(n z^hg(FU?wt)a^Sd;5RJBy0=+Tf*^H$kxa< zNH@}h#6}d#+~HOBz2kop$`UOp4VRZhOZ__NCa-i;Wi;d9-8)R~t_OENfqSRkU2mN4 zY51Q>@pe}<+y6)RQD)EhkE7`SwT)oCe>gsDcuc;}E0)IPisgF70o}-$z#9;sqhrcc zcOR740h2y=^Zu)2DqZpx#hPBawZ$+#ihG-+SvOvy-1~0(XD;@tNk99VDQv5`x749l z#{b9)hjBIZ9~VaqJN^&d7Yu&7|Myt_w;}%DgORWD7Robui)04h1O7N@u^fh7_~T%F zgF_ccXvh+-6qi{OW(A(QdbVn*@96fsKIZ#h^E7kRvlfHXg?^8U--^HJjZ4zRI(YlN zqjADIq>U%q?*L}Zu zFRx&M6f*w%K5(<)^X1K9i{$|Dz!CFh@rcFJIdXpTHvM5oZIfGi%z8)tUKwkuH(NV2 z_j_SWZB2($aq`XnyD#eCFaCM(Q0`}{wd z!W94Y)9RhxJFfqxvA2iU|Nj)r0`56#fqcvO-o?!ESZ?BCxo|S;z8B1qzfLR;e3KWG zf95d{9LaFF)~>E~Yqu%du9aq2M_oPN`CM9sGa1j(wuMW%<3-!MV*Qs-Qw2A;lz>?s zZsm9eNwixY%x+?|L1ufA;=d#2sBhN)!`L4=9RH8;9+hc2z4$015}0jbD!X{ZoG*c` zY>U-2_FZ{3WsOD10^7vvy7>HX$2KP`N6nQ$4_0z&x2}Q0SezRquwAcxtv8jKlhF_c z%97w-W?U^H-l|Rs>=ch_%f72ZVY$DSz%C}M`aK4*>Zh^&EcP#B((HfnAle4#`i+Bn z#0IsX9oDsm0s2f^2n-w}QYd>y%#@WbF6$g+uY zeKS{6;o4w!Ep^U2*SYr8OzXw9kEZZB+EQk>q3gC4O8@3>5UqY=`(;jm`M$mVzw6+C z5nR2ATsmlu+zCF9Tn3MKfiEBn2;U99h+Izi9`GgP3c~k-i;*h{-v_>oT+e+T0pCJy z;QXWD+lVO-u1rv`xpr<``+-0E!Z)ME^_AoNQ@CQTFK_i9-Isk?rYw#BJK+C0xcLyd z85{5f_#Sf0poQ`z_&yTAH+U=mdz$d?k=w8d&wxvi+X+7l{sCDC?@xgrAoYP_*zSxk zt;p!6{ukjkr6bnlsw~cfwcMxH&~|lxdaSv*w!MF?Gwc*0Zg|NM~0QW5M4cRzlCeh%j`4%CGqnt<-*qMr3z zo!%~$LahrZ&4*H2+RvmbuS=)2)NkAe339FJ5^1+7DJ^40FZ&DljpQ)b*UiNL<7pF@ zWn3#Let)a~M)wa6$Qo(--_7`+ijni=L3rMF)DkIY+}{I)dk9x@{vpEK5q3KA!qM{5 z65hdQDO%^!;@ZUO9g0&D&YTI(k2PNn+)HTcjeYhgbbhq^8=GdORV91x)CizZ=CN9X zq|oZV92$_(Y5cFmXX|$d$K))&@x23{3BJd?zjMI%2hWqU!M8bo2Doxjl`J8AKH=Yk z=Yh+Vi)G)z#hq%bk5vsw?S`9U@u~7`vUlX>V>b+rmk}?CW)ds zqFn;}+D`|)R?@%JCjXmvzXbNTF-=8Kld!M-S8F1pwv)htHfD`V@$rx`|Lb5AlMM!W zsIvl5^Iax^Lz7AOMLYik+b{Es$xdtkQ~$4rU0)X+zXBZ}j*c%t$Lpx`*XR6toWGLu z%W?j4&O0YAciLT|Qf~HZ3YV5J6(LfQF@t^vFBMU}l(($(zGCL~kL4fRFGqX%uZRB) z;CX#`z6zd4!1ERG+yMU@a()BOU(NZEoWJtt!GEbLtCE?+lA1qf{-dgwGW?gMY(?@F z!xfoFF4^|K(fwls?Bmp{|Bdh;g69q4`5Jg01B$I(GG`-~E|rXOzl+^lNvSlj`%8H!5{>wJ7wT)7y`1y_mGk6Nd233$E8f$3GoXC_m;g7nnJK{{~;pE0ovrGU$F-H$b|jE2N8{ z=o{EqZEBp-X{d2-DmJ!HAH?{d3uy0cN_+3S5j}EN-a;uKC3$P0?<>Ro#c&^>O?V;KWH_7)Ztl8-y53W& zy_C^+LQv)#2Y^-!Nin&V^9e}<)4UxA_s47Fo_WI@1s8hU#V8CYHFbl&9>m}_J9 zwmX-)B*V|VDs9 z?=34y(?Tz*FN*9r%RjbX&i4BM&!PUWg!i@JeHD1W6yEdU{bG2pg7+Wb{anh%MqHEe z=Jp@SR769WT3I>Bh~z^{eAd-)e5{$Qujq8BbX@1%Nxf9xi&T@_hX0aoTVfpF&ien* zeK|M4PSCynpSAh^w<^3}2JeI6{StVuhW8)g{XBTz7~X$F*;tKh7I4i{Wk8h+Iv+C*TDHtaDG0V zZvy8l4y}?41)smnlQU)UQndH=)2Y2%)6K*@r^>v8<$2A;PHl#SOE9_Nvw!EA4q5z@ zKqOG;+=)PR)-T(6^T6ION^ZVM6n7lcJwSR`P4*=m82~QjvlJ^Na90^~fS(&MnVG)_z z_vT*NI7Z`lj+ADumTf8%=_sj)vLaro?%+;OB z@*?#eooz9d|H|@@?#mV4@t;fZ|Br|BNBP$G1YD0Jd^dO>{O?A1cgjFNN2FD?6lHg~ zL*==mn6tf*CA7?^m2VT7pg&St845?D(aaT-xmx!KUoj{jlokKBg;r?>au)D$!CG~#<wO7aOw4YjCc)|M61cRFw^;U+)qiZiTosT=TKj(w z>i?b4@m+>4lpTlm$j;yn;Pyl3$gZ6KJXpBw&H6p#^aUsVF3Od96)TBr7V&l*fZJvE zu5cV9?08FNIoB!fN?9psS6N-#{=@dmHD3Gw0@K1~3g3BTp{zJKBr6PNZV&CiS7`@c zAR&2?|36VwoX%BWVLQQRMz!e`s#~Gny zR9?6;Tv=IK#$LsJWn1!GXMJm3O_Tcu5cM;)pQ9}Q=)PR*UH|)L`hT|;Es`mefhIPH ze1$gu6O*fCAAUbsR48}h*1orBK{BEJqOFs{6_N6?ijt5|b)Bdm6IX^q8RuTqRJTr5 z6fCOs&Th8Ha<15fulkB5Oxn%fBZ}N_?$CYvPS3w^##Tl{d`6wgm!&c?(-P3O|Bvp= z^O8yl6jlV_xXUnK!E<Z_l#_-04N^2VK-7ry{2n&7q%C zjhS+Lv5w|?hk11N?akmTv-x|%XjJ&NmCZ`|ZgWYwcgGY}i<8|S`>9jS;w)`l?7G)R z^_%3#HQToy^ome>=`$0KK6u`QAXgYNs^uah3?D3 zfDBFJ|0(MK2a4v&!_@OHG1vD|_&y)*FM|70#{Z296bA}eANpM6Wa^0EsN%pEgR7*H zz2HtC+WS3-=2?R~0qyllljkWo89$39@;+H`66MTyfo@@OX+_5KgqW`ONcats4V{w8 zL?ZiuWV+*qkXo;gYvQLG+B##ZMiKlMSlySqyx)IcrhR|*@M2jE_btr(tzRxAk5LA$ zz}{a?xp37G7(_dmt6ez~t)o#J!CiH1 zhUwa%@jRxZ&)6S%69137d(QgLpG)8hNo#jHD^1Z861YkllI{4o*D6`r`}7d-OW!Mj zYlMa5l#NVwj{isk*J35BJEoW!;m)lVo_U%Cu9t>3ZOul^y(Dm>z)Zc)7UIQWo$H&W zp`%l&N<8y%2`uzcq4a;j|Elm$13bC^o5q2h$68F$toJBuh_5-7#p>2GvtAczH#=G_ zn;CV7Tc2aE=P*4NGl%mSi*;JoUc3ca^M70BB&Gew+JEYPxhEhiq}Bh|Qvcsjv`|{H z{SDaux2Xr7WK7soqeAjD@(kj4L}Sjb6LXsq-Q^M8<&8|;(8ZY1q-+E#{Vp?=6+ygq zOuA1peq`vi6`o2m8qU}>viwu`%Y6Zvn8yFJaQz${KaaeCyf~^@UIG^*FC(uY8IMw3 zX8)|pN?2J^Ds=B!uDiTUcR2-JnfI1|bYC9u^8YIQzXr#zBXf~A;QvkVE#z(F9VFwS zOvBHL|A>-*9YK=Y;?js~P?sRfKe{gudFOw<3;*xI@%zY;$UOKz3OO1%200e#^H3IW zQKnavWlNNWOIs6(F1vHie?*y|mVb0#7J1iy`7Qh(H>yyMhvyTJ6OogUlaW)9Q;}s3 zW#N|pwX&jYwusgiNn=<`f#o0Fmq)$)p9cS@!|{CN4CGAYEaYtD9OPWe#xh4#X*;#r zFi>EY$#UwVYPFj$n#W4u0cnhA z?FcbXmB2&NsIK9Nd9DN&Nn@$DuoIJ2oF0|NGCilGu9d*!o|2L2ht+>(TKWkQ^VQ>-h z2=XZM7_!Wv?0f#~`tn-)Qu%W$FO3yi3M~KVzAO&Nx@rF3$Kn48I9|jUut$O+X<;pp zF|tVJG57BfSs+KTE{Nh#j7i8VHER}y8BgJV|MuFj>mv7NyjXcfX?aOSneYBw44*YS zi}791@hc|jbWejwbqlZMcx(Ie+IC7~rM69E$A6;x@{0HS|Dim8E*u}k_}?Sp`(U^~ z0`?D-CGzg1DtT_wLb;A{Vg5%)TXS`1ljE+!d6gBRXh}3ulJWC~eOOa#tjlFRo_Nag zO3EriWhLdMJ~yqcZR&LU(4M$kh5x8S$Fbd#yj#d8ZM;Rddl_pqCAhs7ZA)rV#?=QB z#994E_vJP3`0sZZ|M%>q`7$}bP(~xAto`$DL7}WSEGC~b4sb)TpCkUwsXqOCX zQhgfbIZ4g%S;rxs8pFSCH8RUTx-V~d*Z+Hn@xQ+tRwWM?%#lY6=E(!YLbBDc9=UKB zdjfI(dVXt;madtaTy0VfzOp5)l9^qs6zE@WQmgdEiw^6*`n*J4wVPE)+#+7yqooz4 z>{I5urdP78$FGh04MfxJE8G~Xu4Q(qb)tdGnS7lD77O_sNeonTtk*<_Z76|POiZN- zBNC~`={@xkGR{yd6@}AfJm!kiVqT{z<>z|?yc$PX~5xnio)}K5MHIuJCWZB&>>UQ${QNYzmt$>6(d3l}=Y7+PD6B-WaP*)fEXP ziu#++LCo?px-TDk*Z;W>{-1#7r;z6gie-~w?EhF$C7Xh;7sR9id;@F*-vp56GzhmGZz-gc@3#u$t<)_BBu%Mx)98_p7F4tVF zaT$vHRy<^NBRh|Wqnfl>{?UE;*vtQi@ZS!9e}u;l@FTDj{1ey(ehf|r{|wFmKLKZg ze*tHKFH#;h2QB|9Gw|zYNkxz42kuq#^349cfsWO8+b9)JVY-2`M8br+9CGbhy^!D@D z>OZz$zVPb*_vrr~=_Igs^bPk0^T0XaAaEZr0PYJ0!Tmt{cvT@* ze>E%D4{@?!aHy9od0Ed7Ff!c|6BN*0FTFkMd0z^MDPS~5_lpw89WJG0X!L85j+K42|N{yS3kc* zUCJFxDuPtD)9_!eYS~!+(S7;G%m1s?|8?+J43DRQtAMA2tAg{v)xa~r)xk5tHNdmL zHNmsNwZL=0IRC#yUCJFxDuPtD)9|mVidg?;gw=idHXuc5{r}hCzaIXs!=AqeUJt$w zZps=!Hx%^98-!osTfpVWv&eJ9=EbS*<8Q=yMctX~wBf!rkMnJ9nwn!RiU^(bW;z@l zX-%z~?aTOFQ0;zm765H_zuNGxvbFG!p-1=SyMPQ&mFhRv7f z(e3-;{24IqFfV30fvnk9Qd(J7URoK={NbeAyjbGu_=ny|W#;iAtu0ON+>wM}UgG1i z@3!s9PsjE1-;sy!hqb-FN4_2ulFEt2G9|RTlcL@Y0_#I>p#twz<0Kk z_V>rye{4T1d3n}<8CoPVoVDK08&oXe!Ns!aV7~RR{^MV$|35)i7+NS_4C%>y`-E{# zE<^A86}r8)wL!HkqHE0@PhPd^^0sExkUIwd%xF`sxvjiBF^DEy&Y;q8h5u-%cv(qg zeK;Pa%y;;L9shytmq9^UG0pz}o&6s^XOHhWLyKjfp&{9SXqD_YbdKyvcyDB1#P^6z zQRRAr^Qy4+skvJhzO!AkGCT{uJJ&}fyt_vCnk?t3DvVRCCdEDRiCqTD{CTqNe{^4h zK^d9G|6W5y&Y^DqVgf!u*8D9)*Y98r*xM)1lRJ@vXcrvA+MfpwXH6JzjY)+|6^B{c z1u>gl=S?IYG-HY~g8Q(0_lmu%vA%n{`+D+ps+*=emlzCx^Hk@n$(AYYaIY$ncK=6o zUj_#ykjDSSe0Hv2-p4p>{*CngHihHMCRfSDlNZS4%=@`?@)B79UNZShLq}r6k5ZrU z_cPj?I_pgh=<-6z`;}H?9`V%9I?As1OC_+>cLEq1%Bqs?4MF#wnaQL`ZMCMOD8g1= zE}3QS9Y2~v+8EaUqx&*6DC?y09~v&Q;qV>_53iEQ@Q_5o$>7GrW3u+}IkN8XdC7-5 zpzV@{ODZdw2*89apBTxyD^eZ}u|rCw&$77fGZmTB(4fkhneB>uOI^F_a>Z_<5%ow#; z)*acC#$?1vvEvbvdjv*(`uwP3hhw(lG*Ub~UKlBjOx}!^`V_F>xEz_3@!hZw13~2dB_hmV+{l9}g|4cY8L+{^#_xJJrlu{0c zV-rSFF81gAdi>^S)66%*lVH3vA=Y^>k5>AvdL4hYbh1iIeJ6J%^C`}3sjus&rOvTv zrKciM3L-A{D}HU%uesi#*^Pt>EWS-u)GyEA-}Fwa-Brihe{^38gP!@{73lwHxE>4F zCGflfeE%C8@I7Uro!_&D$KqMz_P4H%owGW+JDRJf_wV!RuI5sd-_cp(DI)&W`%*=u zJagm1Ow>@Qk#y*kz@z>Cb7PlEvyV^J+W%OGW40xUqoL2(A1MyfdNlp;#Pggw?(9+a zg#>;y?M`KXj|RuSrrR+^-A$lfx`qS?nYymJySGu9Y%%(@K$*pLiRtH9E7?9X-c539 zmEa3mSAv60Osij-k};B)LrqMjo#dJ8NpP5n*-b-Np+Cf&CBfyA1pA_`|FQitCMZMF z>i=f+zlyrQ6&p~4?l&M)hR>Hq&NU%hAbWByanyCSw9M*u_2_og)|pb~kc;i@b==nF z($?zQscu&~-;&)oyQ`bsZYomK)zOX2>aK5h*teC}a<*{IZR}m;bXQwe+H2fz9smA= z?U%7Z8Jouc=J3B8{BDi(AlnXKC^IMv+hO;28NNt%9==3&1p7M7emUK(B)ZM7E6V!& z?fn%2)5Wuy>RVJg8o5^|JvWyafsk93^kUo!om`{)6tOPX1&F)5yPQ^~QmWEA<^E`A7GqDCn90(*^&Vz;hd%PlNw$!0zD-WJ_=>Y(XtJoB!Lx zJd@&IT{p{DPwlmxF-(K`K*iPlmeolA_cJ%e+>iptVHJ)_EvBjJs?%a>H0PorGZoj0 z-2*M*ItlsqR&Dz)nPj(|!~Pdo-Iqy0StU*X>*0SoyzdIfF}U8Ha3}h{%HTqo#(of| z3@x;D`u?eJa!f_?F3sI4FHK#420VG+B(mv?Z=IC94xCl*XliU66{B5>WG73jTSglF z@93&!_chnV+wcGAzN`?G(P{jjI8@}8p~Znk$jivLdByTC_We2x-q&Lv$UluJlq2)z z$ZDe&$>3#t|Kv$acWrfZZ7{DQQc0H;Pm9ebpFeErSP>3YmX%fdeJeDYh7kiXP;iDTUuK3!ex=N zlG0MXdD`E7{Yh?bpb8#qjzB1~3Wr_2Z z5$7wz&R6>Nc$Ug5=X<)Vmm%LMj^@KChJGacN336@Ti21t)3B$oLS%+^r?37F-%)~N zY|Pd+MZHWW4)2iQSR0dmv7+fo%-IqgFHP!p3ErwxBv>R(>RJtN)nExuk|Z5~ne{=M|p@4NA(D5c@3uG$NjICZF1@Ul>(zcHkC zUrAq^m!2K&$#t)%EdMB>dwpg3NB3pzpsbnJ{_BMQF6#eT1q)<$!9v**+zQ+poQcdp zwy|x$^mob>cCL?HGo`}GC(OQr5w{DYZkI(uZr7E$T^4psopY<%@ZVBf)8XC-`m6U4&aVp57Lbsgbnz5LM*SmV2SKR9ne&72J<@>e3#aDLg7j( z`}*F?u(GDul=^mhm(6XpQ~SB!|5kxY@n7Rww5R~o??5>I z$Ao#Z3%u{fx!sXHkX?~w4%ZAPVy*kNHSU)xT38*m8V6OPRQi5^k7q}-t1_6&so$dI z>|$NkS7A37Oh>&st7}}o8W{d#33bdXi$*ILFI?g4Gqn60-QU3L|KAh+-y44SLgv8# z-zF@Qec=BE#(wXQ-G8Y_@(##k|4UqJECzy9lvRYwD>Jqj!me#UGc3Qsj4UxXtnANG z+Bw_3KtWNW0Z{JO0+CrA3Nxs9yrMuG{ySotLT&j+_stq<kiNw~CO^ zz@&avWSrYJh6k&Obak^K`?Q32x`JV;sekkp&}=wh z;^&1+OQNBQNJ%7NUH=_wJ~k4&bbfBqsL2dbsN*RSe?5FJaZcfu4!W?>$={z@edX3B*C?9 zOsal`3Feu*N^l(;GhM&@pBDdb!2uFn&&GtAxW#iakBnBTl;8%$?9}c_Eu#*WpkF!Z zO}G92hwT?uun48;{~@D94n>a-$&1N~qZY_vgbyXW65+!MuQI5r_a=@Z9-%mND~cz- z9+j44G$nuZvmkRIvuOr}pFL>S? zd%i03ediF~hw#40YW&`h-@b<`-BM-|}x1 zbEBZFkf#6p!~X$reIW9{5cYi^RwcKBTl4+zesCe;cQ{W#kKZJwnn5Y;rb$%W*5x*n zLN%s<&z`Db1+{KzNaj_gPA`-jK*7Iq1E@iK^*6dNn*=2@YL@|GT#qB|Jg$OAHCmwl;r)M-+z>O>;g7N zJ_5Z*H$!IK60CSH_nW#GHIwYTaJ0O%q%0gM$<(c9pjuZ)y&c)*@K%nm#QsbQoiJk_ z9iE+_0sfOZ=a?F6|IvM^@{a%7hxy;5h8Ob5v{3G0-tWDWi)Hb|VtIMu9Jva)dg6k_ zGkqZ3?Y5pMi>QYjFIB8i+Sc67t}AXSFfY-n>63GP2cs?AsUd=UpUfnOLp_(Hsa3iC zS6u(meWCxgMw!j-{o-@w#%y z>&hIjD|Ngs>Udp=<8@|NBMLqG6mg7U?LWFNOd4H1jsJ!4e=8i{2FJG}cOZ8ncOiEp z_aOK3f0v`gH8H;y8eHGkRWBm0dXeHk?5ZJl{U1|T%ryQVdJig#M*CqE2}Vs!UAKc` zGipBxmYJB!t^#w;7D}+f#7x$8j_pex%KWd5Y)qO85%-1#F+Y;vCX&kEkSlc}6R(!w zX1y`PikP=Zu&Otvvl{WtdnH)oqMBTT|L+dw|GmZfPg(9X|0LrnvfHEVEjtn;o7Js9 z&3av=@3Wp!H<%0892=8@%}y5B4_kv{+L zarl1%exF31LfR)5N(b%#PNbRt)lLlMHB2mKm4IcBk}0!&Ymt8bJvH3j(9~>Z)YVj* zsdtg?aL7N3V_zqgQuq2I9;Mqj$Tf#+?*F$-Xo~+b*P?32|DgNA_sD{@_Foemx4?NF zJU7Dg7Dy|<>-jx}@Kodre!oI_NFA-rmNnDPTyv{>s`JRE_%llV%Ypnqmb?;e!OL-a zBHHvUt2+Iq(Dwh$a21A(O-kc`zarNEFAB*4$brZ~$ic`V$f3yG$$tLdy0#gL@7tnt z<(W@annSgaxBU>Vxx3DtXNK8p4yC1SjvRp;R!}Hy z6ALAVzE49A9NfoiG*`DMAFs>~<<9JQpq1&7rrN1>Z3>T@bfGwkqqAPMrmOQ;{CE=J zzqNj*W-Nr|-@F2mR!!6YgWz}G;3_!^IT|?zITraXavX9z(*L1TY@J@~)cWV+qt~gl zuKc2ay4&ObW1t_pFVnsL-xJ{fL^wWpa7a!9Pex8bPDM^bPDlDZ1}IuKi~bB4;6oP!7%p&p{3)d>GQtp<~|+K+_z$a;{S&Wu30$ zNXL)Pg2I19XGN|5$28b?!~d7`9+$dyVDU6PCc!DPY`e3+mN+pRB)El4t=4uLi1~^H zn}xbg+00}_)m#a-va*A=nZoj@2TG6~aM3RvBg8yjg6$?|M5z!m_;d+&nwZ*%GWakF zPIuBKtN+-3*(xZL)Aavv^#2HSd@gb%vJbL1vKRV)E^;^HL4A&nPCj!gmN{TOG`5Y1 zMoXCGRp~p?%RJQdSKNgDU>tD;6rSn0N+G~!#{&8m#F7{c+3%X}C6t!-E3V$8XaB;HrK0m%Q${vYM#es)k; zDUw~7l6e!~|D!zO7sc|A?#oVI|6dbdcG}qUY1+s_c_J?)yN;SCF~W}%-i7cHj0-!F zJpm49|A!O6rKqQkWDq9ez%%d4YqG&7F7fhxk;+xavQe{fIv?*!s zn4!z{`1mh$Uv}~C|MNHOKdZmXuGsbt^nE(|J`LSJh<5+^%me#sWJnqbXFO&$wRE*~ z*R(e^PBHF4#PqAoYhw{@=eN3~CMq3qs6E7XtgtO~s zQm;35y0oYhi@%zNfI|d#Ctz(`>vVTlS4*{7-nO%IN>{&2>!yfd{10Qls;`~Q~TTx?a`wz5P&X?deiMmc##EQ0*V2?Db8zwA|x|{^Jlja%P zYK;NZCrEGyG*fF3$=gN=?j$WWT18?rr>7;jONwE?fc5`i`(>}7tevL+&G>&>23JWd zGGj37{vxxG*~pg2R*37Na$l+3z$!I;C%-E8>R z4dJ!?qx-V2m;W8%eTv$@MXjR73@E=iG zQ0xCg_htW}tdyqz)8M}yt~-!Uqzjpjtbh;Trh*>XmpOhb7WG#KYBc+u*>3=jWy-8^ zrP@qQ=cZR_sM1NVVqaABTl=q~Ki>aC_vJwE{O_9?7O)>2zn&M9eMZFOhY7{<(}XJd z9@%O{vHWd#m3+mz;J%0T=Tx$7Q(1YqJmh;RedD-C$F3J$5sLaxtw4qnpr zP<=0u=Bdup9&G|xqTMd)&Z5|%vS`GAWo$YC?g@{tq@htHYyZ)GIoLb?Z%gL?egwyV zhT{c+Lb*IpEY}A@aszTBaubsI(3#~N4~kP&D9V-}Sx~3Ef84i_DCXrp-yq^;#iJEr z-}Pi@vDdci+AZimijMBfp~jX&Of>@bG`iE1^;)$@jb}B$bHED$OFiO z$d#0XjE7SF|Cbn2(xc4Dmb!>mJIwqq#{S4@LECx=D@)wqtt7aIjTupoUbIfztJz{TZ#m3lHh^Fj40od zn0HF>U}CBtDS;~`cxXoTO#g?q|JZ(+=UxBpA@u)Y^!zIH{A%PHYC+hhj`Q+=HvFFh z$LAvFA?G6(AV*RTE(9+^G9Jout}Nxs()IIVNay|0)-NsfI`3bCe{^3?@Y?@*@P8Cs zAB`M?9ErTKqDjQX2jvO++P!1l?w}A1i13$ix zaX)=?u2}W3TeD6=V>qNUHn!Oxj(grp{GBh!fgSOSLzxx{voGAhzFVD6B|ecqib3gi z3&5u7^>zIZr*2{6KZYYF1|v8`fd4|P`*Moc{_infWKa0r3!e7|=Yacw`-1y{`-2C7 z2Z9HICyr-c5ar@9!Y6PpnbW1R8*{iqgcUIu?lUA(TDD^V$oQ;{v*0C z^S$f;9}fRVz~x-HJQAD-9t9o^9s?c={uVqAJRZCN{!fDclL?=~xl_SD%RsL9*R=|M z#r(5ehJt@P|BJCdvH<^2owobV?53#_oGY|DmAyW^8z)O}9x=6kBVwKpev@uVW;3<8o-_j?o z{m1spnO^&UKKg$edVD&1JRdv*JQF+%JR3X*JQq9;I`fvHi_RHB`{x609%i!@^_*{ToPWTG&O7JT1YVaEHci_G7e?9!) zK=?+^-2|riUOJE~{&n`}SImD@&p)~^=X&|S8UAm9$A$2DD|ioh8*)40JHR`^yTH4_ zXW;)n_`jd<1DtyhT$=XO?_BY(>sbGa`7hP;kM7I)Uj83~|A*mm5qv%ZJ_Lu)kvd%k=!C`*NX|{}1yvas zaO#kUiq<^+Q`Q&O^fGPxAKjNLy!L)5Uy2g6G*X_a%6~iD~ppwUgoaZzXu4jR`Zln9Pv7 z*v6z!uZlTgxCAfFsDkPLu=9Jr;eU~odvi2qx*8Lm;d$Pe|>n|0B$z~Ltq%J z03%2V;V4)NmVxD96Z~%k{~Hrdr`!`(@ju|y(etmXhb{l;zFhC+e-rrM6dpH&+s(l$ zuo|oZYr!dC9a2xY0c-?k!T%QUKb5eD^YkAo{s){odj55-Da${)FE@JmZ-)OCcx;8+ zHZTTG1KYt4uoLV8XM)p_8H9I*|Jm@rCE;|+Jz*9915O=1|GGA@aMWr9>2Ce?&3(M--!fRGSx@{;A6S$M`RZM)&0oum5j1^nZ8sdJpt^PjD}AZ*UH{ z54bP5AGkkw0C*sH5O^YG;84oIVTAiC2Ri?cj@nFq7G2DZC3uaENnNLlIaPw!+L%~LUCb>dc)g9ObR5a( z&m?%GiD{V8J@a4*-fUxPJx3D`lina#@RQ(E;M?&3Ec`!5cxl>Gzg7GX z`2Y0$XW{=t_hpfn|L5WV1$cZBZeIcygD-=xfUknDfvD~G zbU?-bfd5a=e-{2fbYC9z`v2a8|M%hX1GxP?xCHzI_#ya5@FVa~;K$&f!B4>N@c;b> zU(nDoJxjBm_FMDWT~$~#o*ji_N8#5|xOEhhx|HpIt^W`I54tZ;24zIr{Lk+>{R3S7 zh=1=VP~bFg3}b)502l=G!NK4Va3cP{VPmRfIN{|uHv&u}U2^F5)pZgzrR10B|D*e- zC@@gO_#ejp$Q#!G6H$*eIaz{tSRaMjb99je@3Jw~o}(Kic#n;#_8i?W!TW4Xwdd$L z2|i$Bsy#>VO7I~YQ|mbzGgN|$OiW#u4o=66kl>>p^~?0b_W!Z{EaZ+SxOe^cqA?;P z(c@9*aUnPw90M*7js?eoBBFD{yW_aGB@j&g|=)1iyCur>to7-|~;` zmuJ2FuLS=q!{gfUS&XbgcvWyUaCLAEa7}P6uoC{)f&X<0ugAId!T&@4bxwj`JO7wr zHUH?oJn!Xy1Nh$%9z*aM1}ne_QbITimV#wqIoJgM8^Qm^gg4>brr`e}|2ikZubqD? zQ#JqSzP#w=e>3>s93HFSvl^@cYr!dC9a2xY0c-?k!T%QUKb3GZ=UTx3L;iJ6f?qrT zG>O#wqx-Vh%YQ5Ux4~l!KBs~0UBtPiyTbo$_}`N7R-D@!{6FMh=Op;G z^H0N8$Nwm+`|^r+{Kq!%-wlsF@VPCx9k@NX1Gpo&6Sy*n7KGSKlqT8!??J6`|K;qZS1T+W5dBf)v#QQ*n~AASto7nOPR#81f5V0R`1*g;{qml-{y!i4 ze;RiDbnN(i@C@)w@GS6b@Eq`5@I3H3Z2yJW{)-4-%(+XzWgeb8`#<3SOJ#Pvtmx{0 z+JDsj@`0ECOX2@Ac)S)q7a*4tz5=`wyb8P;yaxOocrW~45C1n1zL9e`fvF@V1G(dW z!2g%bV`D3_@&BRwvc${(&G3HzaS43>0sIjB zBlr>cC-7tN&)_HEzw!Tl3;&-I{)}^}Pe}Ky$;rAy{;52V}#(#kUFbL*@gTW!-MED=JJmbFzFUPqNpr;Vzj{gDw zUn-+p8cVYA|1tJUzBm3q(|gbmg^%hI3BHqPcPeAvB*FI*Ef!_W2PODHqOMcMd_jUs zOiaE1?|lh=NKB(&%4dEi!H-N#wf}E<#(#ZmVyZny%a4%YC#h257qH`hu>JCd*ZvnR z&-gF&coceE2#yBFfXjnp!ExYta02)nbbk`MKbi0foLdoG=9!vI(|Oni{6DG8j+Yg+ z{|DPIUwZjp3I11x$FfjpSn&4VsCH$`g|LYQ7k8|sTsU#%>x#NGp z|C7vPV=J=p|DgNwm6!hw;D1AS48dm@tNXh#z~{E$cHs8l4&aX9PT( z@KWx@#*OCeDDnLOzbI&}X+bpIm47jy0saG7UnGHt;Bla_sonc|7EqW1q_`(==q|4ZTjGI+ce zJ{KUD6TSkx61)n$8oUPl9e6MNUl0E`5WbOfH-Tv{5D(^#{{jC`DzmW_+4z6ZeF=K` zzZw2-fyagLc`JAicpGv%;XA-P!Mnh_!DrzAKKQ?%@B^HC5KJX08OR;~1OA_69vl77 z#{Yxv%V01655fP#@VE#*9|0c)9|NBTA4i@b{3Q4k_%{4M3;)j%ex7qLfT<)U1G(dW z!2grXW5a(o{vUK-hI;vb5&mC-$HnmZGWZJkD)<`sI`|g&2J$B1zrg=H@c%C1_c-@H zm`YMIkURbd{6EP&HvDJf|3UX3%SN}hU|G&cJ7jXJF@JsOT;8);3 zz^}o7g5QAu0t?16{)aN~AHqY&_M}pj3goT;4ETRincUJ?nvMSl-Iv0A@A^;h{{vk9 z2){pp0;hRn8UF(Yz#y0p4hDyS6XAc@SjPVlUXF7kz*MqKAb0!^_N;i27bM?|b23&^8S{O~A52W6 zU&@%DN&Zk1Q|F zd->l0{x^ij5PXKg3NV6{5RQVSU>R5rHo^Z!@V_zPO*pqHm`YMIkURbd{6EP&Hg!cd z{vUK-ioE=92LGGGV-gEe3+I0dXj>IpZ1jo>W!-va)p5^m;P3z$k$GLSp|2mC+D zJU0Ai6kbQZkS` z{s;U&$vigvXXF1t_hkjI|7RQc?}o=7_}muU4%{Bx0o)PX3EUan1w3Rd{s;U&sf>pIZ2Uir{gH_A|Cru`hA6s?D@uN0 zqTQ*CxxVC&Nwip$F*n8an5gTNFFDu%@C@)w@GS6b@Eq`5@I3H3bpJwh z|02Q{bM6vwnP+M;ZNUGNmVG+^k0~o^{|~lb*7Wj!Dg0jskJrNI0_1YSSAbW7SAkc9 z*MPqR?}h*C;r|B0H*)SKFzp56!QAmb;QvWwHnt)g{|~w^YkT>>8UAm9$A$2DD|ioh z8*)40JHR`^yTH4_XW;)n_`jd<1DtyhOeHB9$Q}O!{-0zXo4O(!{|~w^>v;Kp2>u_2 z$3^h@2>2-Y82B{!IPwJHC&8z{x8eU;_3;e$W|L+ohk8|&XsU#%>x#NGp|C7vP z!+$pZA9P?3 zj{foi|4%BP;XfPy54tZQul|1y|9^$cFW~fV;FsXv!LPu7fM0|E1iu0Q1s05B{10W| zKZJ*l>q(_3706uy81Vn3GP$L(JRAQHx-U_$|L1%7{{b$4gx{Y)fz!NkjQ;@xU=Yj) z2ZKYviSR#c9OHioFUPqNU@BQAkURbd{6DFThW~8*KaBm6I^+K_y$20Z_DWA#spY=>kwf|=v<9{|V zG1dN`aU&!@lqwZ|0qg(4_Dh-9{uhm7{119O3Oz0aM}uR)<-xJwIB+~T0sIZRKMCER zOn3#(tq3mjOiiW@_@k&XWc-ItBL{BHpN8^U7jJY*c>f8c*N!n<=Wm7KId4(T88|D^I6{DSn#*tap3Xb1@M0o{GUwt6waLr zrjlg>x#NGp|C7pS_|L}w!`L60Zu~!{_n;w4WZa69A5FA7l`+?s{IW!gMHzEb$*)M% zb;_76lE0COsrLVj+gkEBA*RtU|C`+rWA{F+p$@C#V~54K;X zcKWx@#*OCeDDnLOzbI&}X+bpIm47jy0saG7UnGHt;Bla_rt z|BopvYX1+mU$*e_e<}Q529MXm=K|z%!dHM-f>(i8gV%t+1Mh|Z>*4$26D&$fd40%$EL2x#{YxvORJavhv5HVcw7XZkARPYkAY8vk0VbIeiD2N zd>j6sh5zRWKhL=rz*Lfwf!y&w;QvYHvEe@({|~w^F)#lw!v9O~xEMZP244YR1z!VS z2j2qUK;9($7x;e%{@*419_QW%Q%On&a>xIG|0kKphW~8*Kj^-+d;LEj!2j>zaS43> z0sIjBBlr>cC-7tN&)_HEzw!Tk3;&-I{)}^}&r`CkeCSBA&6;jw{@85D(^# z{{jC`DzmW_+4z6Zec8s#{|4~CAv}iQGYnRM5u}806f6bHz;dt&{x^dEjR|kUxlO@T zl9GYk@ju}IN#?PsE3)zbp!?F}<$p8y-y9yR;IkU60c*i2U>#CVxB+YgXTkp#@IRGs zGv`{sRFaZ`-0?r)|4HVt;XfPy54tbgdHHXJ|2BAx!RIuv9qa%*!7gwnI31ZmcvtwJ z4gXsb-imWugQ+AX1G(dW!2grXW5d7N|1;9+zU<)j|7-*Q-SF50pWA}lf!l*SfIEUa zfjfh{nE$f^#CD7~-<_|OeH|gQy@>OnbmufR>u&!m-~X#p?f)sTx-UEB%c^PXfA4`w z*b_eYLiR@HAp0QuBKslxBmEzhD&}>HtTX$%MuM(MsoQ{9=dRE>w_2K-!#e#LB=C>! z3xuchzdff8fa3#^gOG!fLy$v}!;r&~{*M8Umdzs_KRV+E|GEN0@`l>6KM-na54Hbi z{ECu4GtutURPii0y1wMkPPAB*F*lX`trB&eGG>e9Z)0Mr{XgTkmV8>a=$DQW_SIti z&vrJZ&KeSPf63p$#Ej_lh?s{<{!Ysly*|&t|67>p?+yRi?KJ->F|*sF?0aHnx4QL6 zVrI84QZX^Jn^6}bW_Dw->WG=07jJsj{O{5y+e@Fc_Mf_+ie6SstN)MS)Ld-*4z%lz z1m__;65a{f8QBH#J(NXOS3ircf)-s3Ex9z&y6RtaHpAEoT`S7+ZyI}Z@@1to{&(fn zZg9M5elb%+LedETQ;;TP3uG$df9UdDmo2(VE|+xb?kz3K+CxXbu@yS{#qy8t)3BFS z()c$+LR#Rs6=_3a$mW!TX<$3jf%JR)d}z|8M5%SUEY}%Eon35cY6~nQ4Y2Q`#p4pU1tJ*u^j36(OFUWkLa?|@{jJ*(UZw(`fpsq z)$m+{)FO3AJ<@>uII39I8XfbaU&VZDr_PEhjiOFHMW>&lQ_vhYT;RV%mzRTNjMaTQ z_@4IP#L+AXKe{+DdGtJ40bCJW30xU023G-B1y=)C2iE}C1c!h_!Gh6qWEkjINHk+Y zV$H6uq%!AAOP#ND{|4*+?e+g-?>xZUtgiomWJi)S>^KyNV>86wRLhG}@RDN_4q3Uj0NS8Ia6_4aqQFM48M_QbyM z;r|)_?F%9PANr5()7X<0^7!8v{(lXJo1o8|BAbxS$QEQPvJDwSwj(Da*G8^`T$ggN z9&&x;2FMZ0fcaVRn)b>fi-RtEw(QBW|9bn6H~cd~$=+g^_#b1xVon6Yxk4V#w z;@yRm-65T)Ldq%P-OWiERyyb6O^SDhlQN=mGbnT3--ve)QaV~@71Xe{}TNT zqQ@a*7#TrEk+sM=WIeJ0*@*ldcKJwmrhN7sY=m*X;qQce|sa8 zvH#e9Ik3?GPs9Hp9BvJl+aR|^ZioCWa(m9O9MgJo|qD{2vIHe}l_|kOw0V zK^}@c47n3>XXGxFgI$rkA$Ld4K>i-N2Xas3$mKxsl0RDtOJ~LKuNnbt>VI@!4lCq; zFZllh{Ot{oe?;zs{1b9tAV=oj-k$&eHWezb z_W!%7$nvjfhZ_FTeL14g{+|o~|ANQ!;PHIq1;`_iM=L-2Kjg7EaX3s$0CnI z9*;Z$IWqtJkK!GFwiLF(FT+1$IP49k;UC?XqYC}M6XE|PI6N6H|A{;Wc`EWg^!_IF z{$|c^p*-A*oQu2-c{}nBW&kKG zrZfJFv0pOViT@B6q4i+zbQ5XVO1%5$Qrc@ZMFT_Pota6goZm)q^d6W?srgiyu%~zr z%A{1zlbLXicn`^?RFp`*^91o8mPrXSnk<@dmw1oJrBo;k&%9Q=N4crr(El0z$M(yy zh5COT`hPt-d;_|CBl2zNdI7utBIhqbz{|+_$XAfBBL9PY4f#6q4dk21p@%Hw#GW?$ z99w#-3RS0}qN>R1e}lEbp#2BY*nT;_u>OCGpYMmq2jKBR%D_X&hmnsU=OG_OK8Ac8 z`2_MwUh?DLB5839r*_GP2^k1w~_B4-$lNM zd>{D%@CV-7o|@vP>Cx4g6tS<>7_sMgaB2IPiDcq`=)Rod zmF4pIpHL~XOeOvNmGtu?mqRX(oQSMKPC`~AYmh4-S46Ia{1Lquq^ELFN{|Z_0_O+K z3;t{@6vo2g9|vC1$!PQ+-Ivq6GCq(0QurSQe_nX>A^pfQa((0m$PJOdLgx*_?N|dyh*9^ zC~-_y7Vn9flqxTYlqKRl*`!3j6!j}9BjPNV$f1PctbAR;jY6a;kXG_^J9W z^lxMTvHfzcSALOK|M#Q+1L*KHba^`RH^?oJTOzkYrjdilW@HPp6+6&|j3L{RlaU?B zg*;SKJT)2ib5)TmD~g;j_8;3X=M}F1(Fy;X!QT{k>_T=Udyu`zIC67j0(l^Ie=qF* zA2{EevhYXbKFB{I7vNs;UW($b(nnP%%~DraIQBo9*4S^O|LDG4;AJH6k3Wu=O*dWE z=Nq*z{Qnsa_k+v7AooZ96*&`m0CF4Tw#e-$2fsybkK6&dBl361osc^t7bpWuL_1kg z5EbKzHQ@pUM+$rC@UL3{%IH73FBcW^zYF~D3V*x7 z9|vAxF^vAB`*K;K|Mz$Jp9O#afX8Ez$03hL-ih8{gWg}u`E`_q>ybAgZ$#dNycu~5 z@>b*m+%ExReixUm&`q3JT(Rv8|B4>7O#Bz!mpO&)|GDsg8ywyamv;Ixnb--wqLF*?Eifd{-1(B--IUl z3cLR`=ig8kzD0hA{2uuO@<*ghm?0jAqz z$j^~qAiqQwmI2M1{cI{Sd8a6ZrmkpAE6O7N|2U)ja#P{{FJ%;o^;zqsx4Kf|)j`<} zd0aL9ex*UV4f!DWu%t;oDT&LSHNirf+byRnWm6?$lSg?%wGEMILqoK-@Ky`_m2T-w zC3BZIhU*r%px}p??oE2zTKbZjB+;O19{H5!h%SL@{R?OO&s5d>IPo9We?|A@7O$+C zr~i+7C>FkeT<>d=+kJ7l1KbJj0(XOZfZd^rxU0HyRbxa{U4^P_SLL|s&XVd?-CVkR zd*X@CsfrS8_(%6;u2GQZ zG5*IZ-fOZcHSGeP`K5TTqpoXH`k5j%cZ&B0Qeq`ldL`n!N4z(gl*$Db#rKGKZ!syA zOY@2EY4Of=QYLkZ#M_=M-rL<3BKyBa|FQjYuUFR1tN+hJ|Ifz8p99VX{{rWM^T7q+ zLSTQW^hs6YskBMOxk`^z^^nT7P*HEnipq={{;~aXe_{Q95&ZuX8-Fo8Uji-#mw|tS zIpA_&ef&&PepadYQI(a9tx#2UhJSQl9xQDCT><}B!tqt$6w1NX$ZNow zd}V#7(ox;A?kbj4>c1G>P)GlDn?;n!7^D00Fl8Xm{+|K=XTtGpa4lG=qEasO3`+0# zIkG}UTrTFkn{!Vn5)Fl-k!XF?tvIARlZjDo7v%k4i|vI@n%whigN=E&Sm0Fi`~*St zX3aZfJ<-~_#zX?L^nxE$>M5$4)9Amd`Xv4X|LDHVD;)o^=U9yxSGlp+WiPgxgirx=n_Yx2{|==??Kc^o}o5uLw;^B&GC zN-7B)2Al`lA1IZoV5Hl+dM9i0DrX6zwGD1>rLhEyW{KQm(wgTFXf089s<&H{XW95K zx-U<7Wy3uFN0*3qn19%B6^pcIS(x?^c{zBT@Z#s|=NbsDYdPCII*v8TrV zqx~ZcOjYsjm_X^6u}$*D7{&qC1V%0bJ-Tuz$sUcNrtz=1 ze@}Dk6vgFyR3g=z)TB^V>Z&?jRh=9Dbq==^|6%NpyhZ%Si8QEQjxutgc<(kT!^-FS z7~OKONvTXIzSG5fzjQl(T8lBKL#E%|31#LO`@cOXSjl#cRyl>-TQA;+C8J-Og5g+L z@y^SnRGC0hjuP)<($lO}CE{Gyi1&$+bu;gON(4s_+b_=*_WwUSN#xZ@%=_?E%BtgM z$|m&xJ~JsGukhQJHI>o^E<^thu5QY^n{%pgKDfGDRmZX?O_#JBvq5YphvG@~P1Aiiw z@;3h7?xiziM(Ir1L*N|W{}6AG=Z$bEl`Gz=sj+xw*R*tNqSd~mE7sH8(q% z{R12ejswSo6Tpe!BvAa&RVJ#cPPy@p&h%>hJ`s)Q$Kofd>O-eWz42C+_m}nm(S4a; z*#GA&334bp{!e&51)K^_1E+&Cz?q=vp{v;cHz?AXI$dEAhkunTni>Ct?#ru%`#;X+ zr?cSrY;YLm;2h++;Bd~507nA%Lr1Y-!oM#3o8cebm)8pG|D*WnXgEFw zoQYqYdhMZL)mU6d963F@Hx@=oFWuQdE`4cDvD z?yE=le-BPz%;nEW;vbQY~ z?_+qed6LyXx^I;}MaG!t>zc;|aN1Q}S3HCG4`YAi8?VrMXwf!is}C0MGsf>wWSaRh zmQ(gVXHx3wIKn9>iT4F3r8eXw-ZRDfl9N(r4tQVhk>Z^%z3Q4xWa1CveN}qZ_E4ni z2JyZoy)@~SrA(@8#ruZI`wHgulm_H?rEz(qBq+11nI>8l zkUeXfWbc|l>5S^YNViWk+ct7DcSv`|6j83pFex!RcQsokaLP)eug7`&9y>c=;(yqF`M@isdGY^g@IO#7C?9x&^09|G-J_WUgnZvK zLq7D(mbW}jQZbr-q0w_32BUV`pAI*KBbIHNo?g3qW(p7^LBqj@x`tp~T`2R*!v8gM zO|n-OnQM}rX_C3P);+Xr#-c9#i3|Li()9t`GU+@g-c0OrnkL^2|LDGaat3C!ylKo{ewK$bE`uW zC^JPW6baVXHZ<1Oxdj_?Gr~gkkw|@r@!%uBizb?ud4bGL>l)pRO5qDM)VU}?*ObT$9X(-_zjqBIJ#5{2+L1RHZyJDj@qXJ}60l zP~H(!_Ook?tD5>YJ2zQykMdZyA4L3bi}wRknz~M9u5nbo zACWSlt+Azy^?yDQqhAhvnuFcyKO?2XjK%`emPw2E3yD+Kb*dy%{-SulvV2GQ-wFPY z@tL`Jp-@_}K#G{1=J(5_tW9fH>@jN z8+9ed_Y3u)qzxOMjIbspWv|YmH zGlO9_d-0PjX>f_%aZ}s=IpyS;%#%}-nB?qpIJ{YUp@ zj88my{9g|LSHkbr;977!xDgx&PK5t`s0S{m9*~sfaA_VlHP)I^xZU~r8FsBDe_Ex6 z+>Ey-KQ%eIBp5+Q|JxH9Q)v8ubYI5#3g-VMD;N?qajx7B&vz5++iCnfNmMk+qvZkF zn(GM@=bN9)|;*wWS2s*1meYW7&RET%JM*Hc#)tdG`3Twcf%iq_Xg z>O#R8#J4G3C%b1gF zf1djwfm~4y!g@4ZA8~OZ9YSv{*Q(gEO%|6=Ty z1c?82#+2=LB2Db#_Jfmh$nUhZKIL~i%??uL6oGfPX)Ex|{g|5Sq{P?JSY1+HBfe24 zWqU&7wUF}Pj)%-MmHI`T^K$W(WtqvYU20_l8UGa%-x#O!QmIEGlO~Ff4m^v)=s&h! zmH~PCzbAjqAkP03<2|-ytmm}qLHP~A-s#8zbc@+tc%n+D_^*(Y-?|ywSjK1 z_jff5YS|V`zB?SYe+8!7X_gY}SNJ~;dz$_#E~l(0hS50>F#KctWm%t0%;SHm2iK0V z-4V(_iZNiD;{!x%nxvHSa9~YP{s!J>ZIBU;WNWkCgu6`op4foKGi>Ya*L-HIb*gHW zj#Q^+y122nk;X_Eo*Q#KqqgCJ85DD>w?s|v+u^HW8-dC{y zxRdFypI0AhR%E7xCFi5gn8g?*nxwp znEzYVB!_^J4^7ZSbn9|Sf1AB^cHU4kON7gl)}5`{&rimB+U(6s67Ni7jwsCudp_fd z-c+KwM={jd@Q?0GwNF;cN6V1yOjq9eD; zdGTDOl)2VzsGYPn$92P*TXfc6WblycRKlljV z51=d@L|J%|^B2Hp{Qts_7-N@Ig||yN*j0IXW*B885@o5t#_&i!hWVB(r`c;=qlq!) z2=z8?^`g?E&0AC5I?XWpkM7H=K3O}D|104C>N56rf#X@ocb87_0gznzu}PjWiGA_FWl?OzLGLjlWzmuXMg03K&HSnxX*x4+JH>4 zjT-Y3bYJ8W{dbhEz#=gfVnIR*et~Gleo2_N=gDiIaPX_?BnLZbIptkn%L~RmtY9)Ke;rq+{(n@l|J- zQJF(hekQ&ZWOKFpkn(f!tyIABNPigp$M(zWzJm4N?x0xQjs5=;{ePm2y&pN>2c173 z9EKfui{D2)m?qh+sfaX*d-1*Wv$DI6n(pe=ha?+mwMf z`1@Vto8TRwIFc%*>24lSsEX>=V%3k5`?5~ez4I#!w^>L-wN}=u*EQyzw-BkC|F(G? z)l<1$X8%8QU)C<{|NSHU&qT-TSo>@9l0fM}Ai^BrF65s)94v;C-P?GUC3LIcOy3=F7Q6(h>x-T0Rw*Nk*Ti~;?P4fNNxcmTq1Troz9#8^4=l^UE z)ffNwR~icC*T%*Zt+8g+?dks+ZFFCPK3OGC|G$9$FX8wr@HO}bd<(t<{&7Jm8)w14 z!YWdhT6Ax&8OJ5cg|t*gcL`dF(&1lG!I9~Pe{^4>h2#GxFnnMc^!yiKS+E>f9*l{}}_Ja_koCVw$SZyXv)7nXa;jDjkCV7Ucq<&iEh3{z#ioOzT0_a3|96miSgR zDRoUeQobX;)x~%$DqbkFGsU+iDV3EYrLpWi@vSWhwPV6sD7@{uq>MGI*yEXFiN&n% zq-;@9Ny>3$;@i-qRFy?1H-5_Dh{lR?D;hAJBxCK>7})9aY~s^nGFBferfO(tpBnt{BH-xzXjWaY4AQB{03|R zwggs(sx_i>{%lvB%D$({Mr-DBaDP>%tF&45*6`mNQW+@2Ke{g)74p9o{HNh~5bTWJ z?}GdT1-_}BTahJSQlHZHXPe}eyg;dobg z-wo^zW`N&=J;0v8;?PW>kR@m%U6qP1IX)}=w}n*iZum#{Ws^exe=qnyAHBZ-o-d~y zTmh~GSAna+HNf&%LTuwwX(QI zs%(+Ts(UY1uS@4~EzSm!!@sKfM}>+1F!o2L`kdOMHKb!f#%&|Ms7a~&E@Bj0im%Sp zSRtK(ka7Enufe3$)d4(nPw{Q!q>O1M?KpOB95cr@c2X+qG*aFuzD-O@6LrL*J5R!js9c%+2~i+%+vo8x`j*8@ln7FeBf*J{u}Tu_zu_|D);Z_CjCz{ zRaLW?vZB&p!#}oPHuK5qdHjEm{r>@ue{^_e?T4|<10RQ6j&iU(mDi%a&WSMmqx+I5Z2vz1{}03SPVnrf4j5C;+RvQVaJ~}fmyQh#zhaTI-tKs_)%d9F zeasiLG+u;v4+mWr7Rd3RyE@|fvAU_C1+NjYwxjHV>1z%9+IBW$m+Hx{=?WG+0n#*ChJ=3L^qh- z)b7M6I&}TcG%8u6ro*JvwGl|UjQBQlQfi0COF7Z1E|XH{k?_nN#MeVgZC%FrpG(CT zN9l)|30iT<`ro^XFJV&Vbj41yD5;g=OD&+63;V(7Kek_{7uNru^OMILkbkoF&wkZ| zo>QuuJbyuc%irHs&yw%K`-}s(J=)W{rEJ&_ZnD(|pLQd!c}-Tu@5MKYP42XsZpKDZ zwJZbMz_Kn2e4~34JC`!DkeWBv$@)>f-QD;@7^#-NqsEx?xGUE)9Q5fhp-;`pzQ z=A^38+M-+~EY5~=s%6Fghuj7D*U?Y?&p@T-ny;ncIqQhLcj+N+RXX;@iVXsr0W& z$(*yjBoWuzMMe%0t=d}>$(D3pNwm-{R^@&}eEV3Hf)ZiGEVf_v_ep7<{(px4&t`nj z$udK3rycO*s6gp7_JcYStc_iG9h`)1I0rli{sZ0yiE)9_gV`JUSa1&5t|Cyn8`vBC z4IBY32Csn6!9S|F4>%uO3T_0Sg07*{OmWr0urDf>!xsuPSC_by8tvgJ~82Q`;1m^EPJu54tZ0`dA5axc=X` zLgd%H?BxaGUTZklv61~b(EKfK@a8SbIQqDl!;5g zRbV~JMh|?~!0~N7%g=KrIpBV2@E7m`cn6H)zGd8ZH1{ojCt2hcd9s_*rr$F`yS2_g}+)uP-qNWCi3J#D3mm9!Sx{6AdwPxiJ_W zIW&^FhqITaef&Zbc~+JCS4oYLjQw_he@Fs-V3Dt;xt{WB>;X_e8cU|;l^CZ+0uyziK= z#CM=c8BuA8NX2OJ9b{70D)YC39nualDI0X3DHR)t?=VuPTZ~>4c|iB>MsSgajkanYi9 z`z|v7M-|~c^WUcZPu(xa7S8|kvj2BA`+twFnIX#{mqjiQe4H;=GfQ5k4p?#Fdw(zV zxtiHl+`xJhs}AN>+Vvrr*Gf+5jCb}}P1doVDahJ+UComlTRKygw$qslY8j^2O*eMR zN^7^G2F=EQsQcx3pLp~9e}Vt?sNdJGnIog%yaK$!{O>ob=gaDxzgs<1CQu&C;moX@ zVmIkJW5gO7Bd#kXICs_g0+Nl3hZZtjGxL)CtLh-aOtel_6kGPdoT|ut%g^iViKSD$ z&Zgnc)X`!E4E}jzyNR=zTrv8O?#qdV`#)B~|7taHc?Z7Nsu`4z=;K?vX12UvEuQg| zi*L~XS1Au89=g1CR(?qL_StHX?jv&*=g3>3CgZV~joReyRM$A-cXz>x(GR*(#@P8JZJ`GkIJ40q8p923P-t#>2Ir;?7 zB|fkwbA;9aXY<=L;2g@xv&btLBb+b)by=NN!1vP_0`8YHBPUZ%#CKCoM~>Zlo<9 zZL>x*oe%DBo>J83%g>m^fOY_oiT|Sea(1Ercg1LtJJI8ss-Rpsx=HTh{7Q6t3v@n> z?k`UqxDQ)!75{fP|Cj$31?SF^6qfl(x{hXRedB6fDKjg8MT4QbP-7%GvIFP5eRkEY z%*Ek4*HyP#TQ#ptt3s0>ExJ!kwstn_9$?~sjQx@;ocNz=Q4}Ymq-I6&&C2>YhQD z)*PQ#U<)GkZtokmH*}6280E=Yqo_;!?vy9G_{Nw|BdaJ^L!G{d4o zV%>fAWybK2?#m^G{{MCGzdw3^09@aM9f(jCu7mR};JlXKZs2??H~w>(P#bI*v5Z(} z!Xo5-XyiK8`mw6KPwA{tzB#OSv2jE7f7Tv0x?OAdSJ^pZ|IvN9tWf`d3IEr?@pL%8 z1OC^kX_C#x1!NoA{9lf#l#hr5*d3bM$lS55Q`MlNU9G&nYf883r7XK@ve`jj4J|xR z)@i64xfo`y&*@1d@_(Qw@Shr>)Y_X!qyOl>%qi^u3(^0x6`T)(UEsWx`Cj|h%#?Kch8jaR5D5x=WgN6LtpXf~4v6Q`Au)%GeZl}-H&ML;@ ziQaBSL%6jsVfUWdk4&rjbaktFCS&2a-B;#vyhO$u-IuF;G9l0ZJEDxA8Gm~#m@Cr(Q0cDTbgXT%WtMhy zDlSety(w1N!?-W|K87AT-Fy4&qps;xyer+>+|z6kf{3Xawe*==+;f;0a|Y3j{gOL< zj`v98LDLaKT;yc&o$aJlHtk4xwfN3;QYM^=)3KVPJlQ(VwRu3w!^L-ACZ%KROm&_! zqi!Ci$oOgEyTD0ltYk}JN*70klv|1KBJ$U&_!Q*usE@>V2`RNklE~cA;=9Zl2azN$ zt9$yGbkwg+6~$9+0Ex{|%0xE3eS!d!EGQ)AFDk z&2J%odzIf9pJq9n#d!-)hz)fjp=dZXa)pP}V?RbROd(Lvl1w#QRxG@%_S3Tc#r1B% z3dN^w9#VdrQ&v*b6fpzi|6%*(y2AZ`&gbI~k)T`%--p8Sexn2O@x(duS7Zghk7jnL z{o!F79~_*KTVdH-^~KXHcx_E)s;y;mr(*P%r#93WtP4hh?t_mKQ#;v5xz}oxnDgSj zQxlfHg>!XJO5v_jPbBU016#3qIISw+#{YA4{{|nPz;OTX+l>D>s%B6Qs}awd$PZZu zd{=niUOtj1tDB^YH9$N33)J=2BUPN7=xFP2R?Sz<44m_X>LStlXf4qe=Pn~2jK{94 zYpf5|hDW43%{aqE7iG?F$@HPYYwiWPuQ_3Dkm#9=M1$<>6b+8>AziUH`ehhZWT6(U z!sw__BH;`J%nb$0y>;WljFRd9L-*yT!u21z{UV#e?-!FQWoPPvCgOiL(FS;$F`v&c zF6fV?0f}+$VUGBGe7}N&hucrhpB{5`K5ZS!8%V`sJx&bGB0rqB(rx-A+A&3{jcFL% zU~N^hIjYjABr4USQYlmaqx*78;ry=`$=%f$>$N-Md$wU5z&o_}pMvXq(fdc4oA(^J z)ldH~C_Hql?OG4?H4o`+wU32m612rs8;^7=?=P{KuEFJ)npo1Z+p?><_>j+n%ujCC z@A%OLzq$Wm_(%6;u8$$V!}k9c^#4k@z0V(%$Kd*Ta2tPL1LlIO!I{(tC$T<+%c1BI zQ!aI&YwE-`H8kT2G+C%C!uFv|ldZbXOrjvVPc`-*-Iv>aGBJ<;ztSv>dIE9+^M8+G ze216$x1X0ZNvgb3&c`NPGS-G7vSc-Ed7avWT^RqZsuH=H zu{|rmdl&V6Cv!e3$2ZBi@j-cyKEV&^8+e1hK)XXXtjDkwWdqoT+E9@l@3Lft8^g8i z7wf(|rgor?!cAu=(&Y41n}Ciu-E--LbrY1lu&gW`CX#XeC=(Q&u|M(@@gJx4plZwW zNXFt^MM~p$(sZ+J>5-Bdb=QdFu{5iE91(wq_^y*=C!V9q(_}`|eDU2Nj+NAzc%FHc z_-=AiI@OfU_?#rZTVSR&5zYp=?93tSKbQJe|G%$c?XQ}-G6T5@{k|Q@KI(+Y zU`PDH-IyEdexzHIHnSHJQ!Q<>({-Be?`$i+GbmeYPD^(;CyQGg6aBNhX|AWa(Jj7j z-*KJm2M;#74(hP)x^{epA!W?HY(s;ac`@yObYJEbj{n&h{&%I1|5r5u&+jM$JAs|S zMm3e5U69Sl6lEYuSs3w1v~{-GO-SzR?w)4VF+MbOATq+hid1K7an5r&9|}fC7*5mK zV-sM^EMZ%$@V3R;oBO&_Mf~_7zDDSWwAo=N%YV8pF*U1txx2FX%0g)}`j76*V?N@2 z!~WlI;C~wPeK!Z)@H`cs`_cDaWSrlogPx-LZyuR4ZhEmyl1|G&8o^(yY1aLeKD#R$ z?1IUu_C%=8>Qcs<*gZLE0`*0+MiQGBzsAYy9RGZ}Wo{b&(S3QsMXy!TCt4MEbrNiD-!JG~?s(R!hN7eY+2My-cd^#3?$11f_zz=$c~gfJ|o`&~wE4UmQCq(}?>&!MWC)8QQ#AR;n zl$HKObKHJFqOt$jetDtL|9^U{$babj|D7i;yLslx?x1RPTvi%ATUH0_f*=_2uw4-| zYV~1ay~3(((P`^$Ztbw8*XpKLH*1aeIcwb{f;OL>QVb+9L?jcFb5Z6@2@e&Si}zec?1)eGCDZNAowil6_56M^L?^@p8a2i@n832_t&n*_E)gym#0Z)c;?FQ!DqfE@r@0b5@-95WpiZccE*g^ z=!i*SrJt6YK&UiSXb)N!X+{bvvq8PWgkAJwD3_h}-%xaPUtTR7|6hjvudA+)ez%)?GWmAk^T7OPb{SlDK?_{0g}#V}8E$#U+aT3Tbz! z#$WZST0Ch@FRrfeBs2xNy-PFZO0%Z0a{q6qyxRoahnX|+UvyvIC>;Ou9{le~`+o1z zLD`G8{vW_`B>{PleNnC%&A2eu0NR@ik^gh}4f4*?tvy}d@qnvS^JW!W7*{DB}w)x{Q^?@z82qnankjwDl}5E=J=~Hqcw)?95+sUuQ{A5 z)rpj>%Jjx?DRMb8^*^>>-YabXuY?w?jE+~(1_&Tm0jq-5!0KQPFydif2+S@1hZIz4 zEtK2VI%P$(T>!an_{a9k2Zimt_!m7GriBOFThMM=M9Gj8bR zlzOK$|5}EW^e8ny)f`sVrG|fWUq155GI{m?GVuQkI9?Vk2R^3F_bl^&o@30RXi0bf_ntNxzE*uPn!;w&(U8nNU)g#Vj zbn-gY!t!s5&vfiR{G^+-S5|MMgKx4?4@{?{btvqsr0S*vW0{F1V;Vc85>2kt{< zaha-dXjN?)k?FBSujR+2oPiW^+ZZrC#x^s2C{#|S7C$oGEosZ!7V;l;Tl}3zXZy{v z{4Wf=>Ixx zGTK~?YprPPT6fZC-lVg;JJ!}|J?p~hj<)P_bMCKd{SyVYDt(z3XBL)aA#|=!wUC8V zHBP3f{~g``$|uX`@m~x7k1^+S8E-)9ysYu<4NAW!AdQ}&Y)oIkuRRN^|DAWRoJ;Lo znmJ7OZKN?0WTA?l~!x5qFLCgZOrxGuo<%K$*{le`}+a z$sZH{L-*yo!uU_CMA`3ly=FZR@Gok0W9EQ)|AGsqU8E0s8`_VUr<-*6)!iE6INQ1R4Ji+s_O~ zY0u-opI=sFZvQ@v``nH(p!J@BG=M&E2r+;Q6nnpME0+V4Yd6?Fa}Q+&Es6z#%>!&Z zadKZ|HQgY0u_HS=6RByb{$9tiw<5|DY7DVXdR;W=>iawQPO%eRQdI$95Hq^JNtxW7 z$N%|^|Ne3k{k-V;*OLb2Gvrs;f~ER!1{9?+L@m>plTfTLu&r59T_R? zyZz;6Xjw*`JazTq2=Np5iKys513lngM)}eA;r9PO@c(MZ&zAX&^?aRnfZ+G-Kz-n; z4$AM4n<2ZZXULRdWg?tb_`LQel-+zonmb#}3Cb_pam7nJ>9kf!QMov`A6hfdeX9aV zF!J;}nkvuXd85bW{!C6LE|H}!u9^?WCF|MlKVxqR;is;sXr-=)RQsWtBYs@A0xE036>3?gtNm z2f>Y$gNKk0gQADxJ=7%Wii@(FM%PQDi_+^N^tyIcs<&0SKe6E--IpGd$k{ zZUu9}ZQyqBH2%QI$K=U`MhaJJtgm;8yeRw8bn26exB>i;8X|Gnr9$V=$@o7jQ3z}w&* z@Gf`{6ghN?u{h15&LrwoPF0GO>MTj!-Le0@UCFd20ATpX_RBJb_5b^rg%9BPL+}xJ znR4(k@)PhW_zV<1boKv|!;?>dWwt?#r@;{C^JrU%>H~;4APo_y)|U z9DIxX4ir5WrzYvj))K^#jvt*7h5xY5kQ)BceOcaLu>R*O@c$}Y{|CGVUI%Z0b$pdF z&BL59`hiC{H0Fm}B$Rb{TsOc)l+tOEh zrtsWCfBz39%>OE-|A#r@VfcTmG%y1Fg+JR(bRAA(JA@~f!g^}7eZOvYu?qWoU_Z=G0;|zERH#Rgh4FAtU&xUT!=!o!$I+snFiYGd<1BNp9Z;TXK0K(`$ zx-Zp!SvAl9dz)VUPfDrl!Drxe@CEo1d96I(FZ(u~%j?$^Wk|P~IItvQ_+6e&8_#a|F zOzNfen6%%vBTK&bJ@HpKDZ|Q46Ypo@uXIvIbQX~v)xQ(}GUC*AO4m_5)5X86kW0Gq zz_*sZCI01|lVw_rJ_dW2Is2k5 z(oXZUS*L2z_9(l;Sr=)MR=2)$k=I3f%9$mlQ!BE{nNjyvF3bL_q!+L6#~-DwOj>)p zyLiCbq$KX!d zdv_rp#{YW+%yaxemqX{~=xP9+@z&j29dccwx~`}zbd9Kt|Bvq{YZvPS1GB;Yi1iPAT9&th0B9e{^5gFSP&n!2hdo{2y>H`hFj{ zA3Oja1P=kXL&yA59dy;HsIm)CXF}m$SG=(QV~p<0hW>*6zc+*2DH13hH8vnMw9~%u z#pU@?%>SnSAMylbeg%62GADe2Bi0?a+Nva%aGR9($5ekX#Ods{hlWB<{83HxQaJpNCD|BLAF+XWq;0k#E)V+W4#v-Sh?!OvxG z_(G4|d}T8~Gg9X|U0oEJY#yfV9hz>xH%#VZ`kSYy6e!WAGhWI)jigVvpkivE9Tgf- ztgC4FNB5=9FKg!Ue?C7|GS~Ykc>cS8P$t0n@yL_>Gh`XgPaBE<1qww$fryT@Izu*@ zZY90kO!`b&t94)cx!^sD?9UW~CynVfophmaw7xM~S7bY%+yv&_)$aX;%GDfF)6uBx z`t6xaaos!3WID0ml_0yF_%E#ooxe$>ah~{BcT$FRo(d_S5&xPdrP5cF(pSX4wv$qu zP)Z*X|GJKqR5~dPkKJAT>yy&aFHOlHCC}VYGR$PwR%1mI=B^jBjm*e9SJ-_wH65iW zD7?j#h?J*^e}s)~exjd7|FQkjP}u%Elb@DF|1Uw$|Bc>Ppz{ZFei-Lla=sP+SNu>e zjG$Qm!8|)p?bs{S{dKZAm{q&Fh3|%wyM=BI#X>XWHqP0(e<77ctc7L`O75L0D<)gA zg>2--b28s*_{a9M*iS+HZxFMvHEX`4;dvXdI)h)=C~1;4!ON@#+$Vv|4MzC4OE*1V z;<2eZlUt{1c12Wntq=3B8%NjEo2DD1XR@X9(9tS}z$>4$p`y8@qjRqjy6yhHKs3Z#Xvmqx-UnU&iI}f22p` zmvB6jF<`5YpDk~eH^~8GMfev4>6LpiQ8_X@QUmq|%{n(7sFf&HOZ2)Wuq-77f! ztLnv!{-gUW_9mV@{trR_*M;Nv;rLMaUXSw+I6sW@^*MjKs!0yP4`9-erY0j#*&I*N zW**9>;QwJ^(X|_LuTbZ@zKOE1==wTxuMll?FRu>&^{PT^=KrJn(&m?{JpSk4|J}xV zkB@;q_5qqYDIon|b`@L2^7kW?X2?u%z@*v61T5^IkY$g4XKyfQd1;I77y-&zJkG#^ zX8QzFBP?UBYWC|Y2JK`%N|egGfP%i1t*4md%h-Q(Upo8+`~Mv{3HuMX2Z4jZA>dGO z7&sgpF=>_@iL^Rw3qr`Y7&KZImj=u0>MgIUv%Id>^17(ybrH+!re+E~3S~c<21RG= zp9~QHna+k9_L~hD>dUqgf1PCgPOHK&bWxx98zkeg=&F$NkHx={Nf|M=Zpbf5bMA4FBl9^c0T&nhpPF!SC7N9Iypzfj+>Rul>k6{_j%OfBU*TP@MiL%DxoU zrhn$~y1rrE(1|Rpd`Pl}qnx>-mJvg=uT;(G3O3 ztpLW3ST5P_bYBy@RLop*3erMwRRW8i&5cwZ6T|16c#=nIs_ zz(7fp90>{!U86;p&%MfR1hnh2E#5NK6`QKt&%2}9p;A$@`rD?&6u}jUD>5vVW;tqq=u@ z*2SaWuRhXH?-mwKvzlyg!t&OgsaRWc%6{00VsTcJDT$W8cGZ%kU79@(`%w_h>TlWc zKj^+pEsXy>M5(Jl@5AW*D(L<5*n`rsmEtA#^H~*pfK&}Glyc`s)Bo5|$86{bTXKwe znfZ@wZ)oP~NUfW3BSzWWqg%((p2zH44uo0CsIx~gU~q}5wfg&7l%H(se{^4_7mojV znPovE_;*oazQ3lQZxgU7Xadck1=t;`u(&FCts3g8iq)y=0acJrb!UlnsBSI;tu5Lu zjGXzOjQx?F{KJt3>jpb9iW9`&F`Tm2w&_F4GsVA|WIYx|9Y-vN8I@hq-{uUaQzewD zF7fw>v68xsl@cN16Lw~Vd_MHlZ|T4#$mWkqG^ z@c%{|+b>)BC79>`*WebeFpmEIaqRyD)&gsTb-=n{MgC8FsNPIdZD?u@O{JlEVU1ze z*dEP&9b1vmZ8U25NB3pWFYD#;zY_ef495Ym3Ro4a237~_fek4GiX$^pFWAr+ZHPA1 zyN!Xd#C2ew%4VochRR~742Gs?>z2hZ{A)^hM*q=$*``qc2eJRZgy$e= zgzJsKufWFO*I*N%Jv86_vr1=kS7R%T{_EyQ82v~0WjnvDo2UOF^gj&u5fBBnpbpf7 z2CylxKXQX_vj(8n)pz(=rSmgZrOl51w`gjujQ*qhvVGzFuNL^&%$y`e-BGuxq9p{&SUWCP`h$-P?BJ zKaBm6{rs8MgD#*VE%y`hPY$egb-bA~*@04E_mD0jC1R@n7Ha(pWd$q!~@C$9w-IqQ5vVI=_FTnqcaQqT@6y6^LkAo+`li(?!IhMv~%95eens$@J ze@sw{ZK>U-0IRgw@UN|JR8KZO5};P_+k33wge-vDodx4_## zbu1wf(xp$QHE-zE2!SIjn%RYtv-#hUCE*!rHJ_TP;26icLl9lQA4}f*b2Q~CB z8MU-xSO*`Msim_j-B4tfURI?uS4Z6E7pqiSrOk$aRaI;FNB3pl!uJ2V#Q)cWWkvBq(B_@5lo)U}3xbYJ!_)c-Z$e@!@E z3#<)(3Br_tU9kbJoVRnXI5N5vVh`)OXe8*KFzfM#Ly?9cUa$L79l9mJ&1>Xt9BgoX zkKAhngQ#otG{{hDOJTR6$f5$Qc zit{@-zngRS!{}OFV{JGbj6~f#A(-i!sXsH9N9&7N2#rbPCG*}ST5LU>pT3E!)~jdq zCX~_D-tKsFk0M+=(AqVnvq$p~!#}oP4lLaN>t@D(&SJdpEnq5Z{j4A}MZKA%+Cr18F;B9MLG zI`@i6RRmP;tD<$d$kw`d<~jVUmjB7{kM6UuU%~n>T@@m$!1HbJ{9AbLhWAzZ`*!}` zp1*tedo}(R)mQ5ry&;zVFIVYNy|2zm%)M{8Sp09XX@SGP&dD_TkM6UuZ^8V(JJA0f z;JI{Cle}LwQ$DJiB@^I#S=M~nxQexZMl&8{^!%*;=L8F=BvM7}PdjVcCY@!fCEV z`J@EKPF;$#QjN7`a9&m8qUDRqZ1^-L}hk zW~mrJ-Bg)QI^sW!{gG3g_)j972{hO?+eOCSE&lyYxwAFW*;keF$>N`BQihe=B1~cx zp94+GsBzG8*0GrP$@)LriT@yzvR=o8Oj=F+hnSQZ{cS}GyfmkFUJzky@qmFuTXSowbE>@!FztVAKa2azDtYa{W3d0v66g7JOhEpDt$&yEAMpEx zdcXr-g#V&PHs9;R4fXZ4EROGzK+!T#IOWXbRs?IA`mJy_`Iu=v^taeIXr)_KvP7&m zH_v74fNqZyk{SNdeL2xDlk)hVkN)3FT|bw2-(yt)c^o_NDCnscxu&{Fb_63HX;!+h zFSW6x{k6$gEzFsl>DMjO$$2R51Lb`*O0MouG!- z|4s7K$`HH*>%Fv0s+47sFCnj}sgz080r|8#-|tT(qYbKdXRJBdm$0`|(%qa=g<7Sn zcXB$_>n#0YS-2+0QZ3V%Po7&+q^?*eM0;mfDn>K1Ib}(yv*b@#y1C8TU|>Fblj*i( z-0~Ap4y|sW|LpyX?mK(HKAy+_Z8aiy)XbM#Yi7&M;KrIc(oz!`QRSE7|6mK^WGoy{ zccjx+8NE3n4qVP~Z7>p~VjJnplXS!kUFNbDcx$iIe9hdhK00!AAV_3z6y_#eX~vf349W<)`95QPOEG)PW9ZrY+tL3;-DxH|y#9xB zjna0fcYBdmw-_+};)^mbVy8v!QQvQo+hWHoa+y12v6n3Zz3lz%@V}^faoS>k$Dbdt zxN^WFrG|Tl|3%yv-M=cKwS>z3bH1kZeJN{OWW6|Jab?K=*nLZ6SHnLWI^qis`~O%4 z{tlFuI(xtZFYp0Y2`w!Hqrn(37K{VspaP5sm0$u`2K)jn3zh@RgNdLDOaj%Q2CM*9 z1S^4+K>(}*Rt2kp)xjEIO|TYN8>|D?1?z$J!3JPM@JkQ`ArJ-;5CyfM4%CAN&AP2lN6)NSAI75+Dgufc>&c z8Ansv4+g+AFdh5`Yyq|eTY)qf1Y3h`z_wsJ@LRAw*a7Saeg}2}JA+-ou3%A$uEW2a zjSp~MA^*E^v)#Gp4Dfrf2iOzr1^xi`27d(mfIoqK!Jol?;4ff*@K-Ps8~_dke**`B zgTW!-P;eMH92^0T1V@3R!75iXI2IfSjt3`z6TwN~WbjXL3OE&<22KZOfHT2t za27ZloCD4U{{rWM^T7q+LU0kd7+eA_1($(;gE`=Ga0R#$Tm`NM*MMumb>Mn%1Go{~ z1a1bmfLp;_a2vQC+yU+ccY(XXJ>Xt&AGjYp03HMnfrr5(U>yaC<>Z-KYLJK$aL9(W&o z06qjCfser_;8XA!_#Auzz64)^ufaFqTkswD9{d1)1mX#ldO!&%1*3o$_<$djfze)rgGw*~ECYT4mIcd!<-tTy1tx)NPyw@*b`d|aFA^0T-f)EIU2#A7OPzUNk184*rfnR}*!LPw4U{lZpnn4R_1#KV( z+QDQ1W$MG|Ke{g$74qNVq3e-*ZU&}+F3=5nKre`c%|QYrK??MNsh}SWfN5Yl_zl;!fOyZpcQ?mEoM`rQ}*BQ-;JHzEQe(xpg? zG?HR~ieez$A>G~G-QC^Y-6A3&0s_iqVW=EaMo@1ST?x$xLA?)0oZ-W-^P}%waC`n9l+hvWUejVJXX4 z&I*D^9AWvJeJ}Ls@%}#^|5wU?m7c3v!&=s{o(*hd6Pww>R<^O79qeQmyV=8D_OYJ> z9OMv(Il@tnahwyJ@7(1c z_xXbd{K-T9;t`K|!c(5{H_v%N5XHVk6rvK1=)@p|P+}5`*u)_&@rX|X5|W6-Bq1ru zNKOh;l8V%%AuZ`hPX;m)iTGvSC~WqFMd9<$6eS2=)iX1%k%iaEN;b0d203_>oV-OY za+8O=2b@+&n`GilYOFcg0bH1QHU-A_V_?mC{mhWiD_cWq0O=wCpn$v=ow4ya_XiGcV z(}9lsKqorWg|2j?J3Z)0FM895zVxF%0~p94BAvh450-?_f3WO3}*x*8O3PE zFqUzQX95$M#AK#0m1#_81~Zw(Z00bRdCX@43t7Zsmavp%EN2BPS;cDBu$FbKX9FAA z#Addzm2GTi2RqrtZuYR3eeCA|2RX!Hj&PJ?9OnclImKztaF%nN=K>eG#E)F&C$8`_ zSNVl&T;~SAa+BY<#cl5JJ9oLqeg5D9fAWyOc*J9#@RUgBZ}x)~;q!kc|G)Ko&WnF~ zN43Whg{VX$Ixz?#l$gXKHgSkcJmQmpgd`#{Nk~dEl9Pgzq#`wGNJ~1>^Ur@7$;7K< z<~6eLI$6m^cHSTdZ<3R@$VG1Qke7VqrvL>hL}7~XHt$fBcPU13N>Gwgl%@>tQI_{9 zM|mnxkxEpi3RU@lYE-8NHK|2yKBNvG@iCw9DRrsGXMD~V)aOgSq5)s?4Ux$|@cf^D zzV{RCa36@w(I^O+7MZ#rI2U+<^T-^pc;?Wo$P@;ztO!EpM5;1M#vo)~)!O8`&2`|rxA^5LQ|U2oEEgC6|HGQTiVf{ z4s_%PI?r62tnz(58um>~>h7{eLCNJcT5F^pv#;I&HLPVF>)F6YHnEv4Y-JnU*}+bB zv70^YWgq)Fz(Edim?IqJ7{@umNg@>ZON+wtxAzBY!smZVx6^u_;VkDk&jl`Wi66Pl zPh8<=uJQ}lxXulJv57-m;t`(&BqR}uNkUSRk(?ByBo(PiLt4_2o(yCp6R(n)*T}-_WF;Hf zd4n9hNlxA(7rDtpUh}4POIlw^< zahM|<fMK19pm-&e+{LEE;;TqSu!LQupH*Rs8JN(XF?s1<# zc)*`L<4qK(jLSpH@|*c3khw9$hgou28*Kt?k0Dw%nWEWA!uvXPxP$ibWB z^$tANeUjK?+frBD~Ez6y;rtQJfN#q!gto!+VtFeacau3RI*Lm8n8iKA;-a zsX>hT$$^9A+!lCNmM*L=gbd`CmRrxA^5LQ|U2oEEgC6|HGQ zTiVf{4s_%PI?B|?F}v?wfpvma~;pMO93_t$d(0~y3%hA@<2 z3}*x*8O3PEFqUzQX95$M#AK#0m1#_81~Zw(Z00bRdCX@43t7Zsmavp%EN2BPS;cDB zu$FbKX9FAA#Addzm2GTi2RqrtZuYR3eeCA|2RX!Hj&PJ?9OnclImKztaF%nN=K>eG z#E)F&C$8`_SNVl&T;~SAa+BY<#cl5JJ9oLqeg5D9fAWx*qK(jLSpH@|*cLwjzvTZ& z&&NFBDbM(u=e!{B8i215g{VX$Ixz?#l$gXKHgSkcJmQmpgd`#{Nk~dEl9Pgzq#`wG zNJ~1>lYxw6;#D&98d-RqtYjlQZ;*pG$;n&fA~$)+OFr^bfPxg_pVvAp!rQzQ4BUKjB_%JM$tC{G0{Qi;k`p(-Cxjq22(Cbg)|ht%OCKIRiXr7rdOjL-Rk z`a~%3mllQPzeWDL!sq{Gj3D?*&jx(WH+;)?G~|04(U>MQr5Vj>K}%ZEnl`kh9qs8r zM}D9ao#{eXy3w5;^rRQP=|f-o(VqbfWDtWH!cc}WoDqy<6r&l#SjI7)2~1=XlbOO) zrZJrv%w!g`nZsP>F`or2WD$#5!cvy8oE5BO6{}gpTGp|i4Qyl+o7uuvwy~WZ>|__a z*~4D;v7ZARs$eKu1Mo$xj ztczS_-ymc|vL$krM}m-T5vmNE|82706Mp`Wn*U?&Q^z^MNltN^ zGo0ld=efW|F7YFm`H3t1%vFBj8rQkOuiWG}ZgHDC{LWqOai2eUz@I$iFCOujCp_gD zfAgFd1R)-mh(c7N5uF%>5K2s95t}%~B_8ofKtd9cm?R`68OcdON>Y)UG^8aR>B&Gw zGVv;zd5tW*PFAv!oj1tAo8;sza*>-n@uC@lY7^4}Le z|99O~OwZz!pd_UzO&Q*!Ebmi}@>HNAm8eV=s`3HVs7?)PQj6MrNF6@nV?NQax- z_?$1O&zF2f1HR@PzU4a_@;!}cOcR>YjOMhUC9P;p8`{#2_H>{lKhTNJbfGKV=uQuM z(u>~op)dXD&j1E8h`|hDD8m@e2u3oB(Trg%;~38bCNhc1Okpb1n9dAlGK<;FVJ`D{ zDcT5~hUIVeg9G97pYNsxdM;!Ui&?@_ma&`_tYj6dS;Jb^v7QZVWD}d&!dAAiogM6C z7rWWRUiPt{103WKhdIJgj&Yn5oa7XzIm21bah?lY3)LV>@uC@g=o9~=swe+qvsNU3KkQj>TwNFfSSgtvKzqP$Bnic^A;l%h0cc#pEYPdUm{fr?b3 zGF7O`2UMdvHK<7~YV#p=_=u1BgionUJwD@ezMwu|@)ZsEns4})?`X*PG@>z0Xi77h z(}I??qBU)3OFP=rfsVKqU(`-?rVCx^Mt6GfQnV2|4a?u`2S>u^-&6j*^z2O^`qGd7 z3}7IG7|alcGK}GjU?ig$%^1cqj`2)jB9oZR6s9tb>C9jzvzW~s<}#1@EMOsvSj-ZZ zvW(@dU?r5K2s95t}%~B_8ofKtd9cm?R`6 z8OcdON>Y)UG^8aR>B&GwGVv;zd5tW*PFAv!oj1tAo8;sza*>-nLRCJX8r7*mO=?k_52?dPe9R|&N?l%x zHbSRi`J4UVMELyc#SDVa^!%JJsLz*tMFYO(8@}Z`8uC4jXiO8D(v0S`pe3znO&i+M zj`nn*BR|lI&UB$G-RMpadeV#D^r0{P=+6KKGKj$pVJO2G&Im>_iqVW=EaMo@1ST?x z$xLA?)0oZ-W-^P}%waC`n9l+hvWUejVJXX4&I(qtiq))PE$dj%1~#&Z&1_*S+t|(y zcCw4z>|rna*iVE4e`!%z{$@Wo6F&a~@;|8OAr5ndqa5QnCpgI|PIHE{oZ~zfxX2}b zNkn3jkd$O3Cj}`{WT<1;?z3+nSFU(tZC`G#-#j)r_sBO23$rZl5DEoezATGNKMw4*&8=*SOrqBC9S zN;kUGgP!!FH+|?!Kl(F(fed0WLm0|1hBJbZjAArn7|S@uGl7XrVlq>h$~2}kgPBAq z@Rt^athbYc)fC^3me zY~m1?c*G|G2}#6D(MISrEPt~fTne9m;@CluM9-uoBRMHZNh(s4hP0$3JsHSICSD~o zuaSk<$x1e|^9DJ1lbpOoE^?EHyyPQ41t>@%3R8r)d55CBOEHR5f|8V?G-Y^?vb;|@ z%2R=gRH8CfsLBUaqdGOHNiAygA$9nOkNJd8sY^XR<8!{CK40<`4fvXG_?GWz$oDj& zF->SnGn&(amb9WZZD>n7+S7rK{6Hr<6QRIgS`?PQ*$*y<&%cZOyXx7E?)0E1z35FJ z`qGd73}7IG7|alcGK}GjU?ig$%^1cqj`2)jB9oZR6s9tb>C9jzvzW~s<}#1@EMOsv zSj-ZZvW(@dU?rg5|8*KAR&oJ zOcIikjO3&sC8=&Ku<5O>*)UxyVf(@{*7I6rdo5 zC`=LF<{gUiF2yKL2})9m(v;yn%JM$tC{G0{Qi;k`!F6_{en2&}a>$Rs8+g{e$qIy0EbEM_x@xy)le3s}e^7PEw-V?7(#$R;+k zg{^F3J3H9PE?$Z@LZ@N*oBiNg`22Uve~+Gf*~fkkaF9bB<_JeQ#&J$?l2e@K3}-pV zc`k5~OZ>=Xe&Py0bCqAX#&vG+D>wO#TioUjzjK#++~*G-@Fx%Xi$^@>2~T;(-#q69 zL0tP1QHV-3q7#DhgSD9ihlqdXO;NF^#$g{pi&HL6pCn$)5;A5w>p_?S=ll)BX8Gd|}F z>hmRE(SWb{hHv?fhI~&W8qudtsvx5q$=ao2|_MMuF@5WV zR2eq^_Ws~j`1zk|{-?Q5O=ku(nZ<18Fqe7EX8{XY#A24Plw~Yu1uI#_YSyrpb*yIt z8`;EWwy>3LY-a~M*~M=5u$O)8=Ku#e#9@wblw%y{1SdJgY0hw#bDZY_7rDfbT;?aP z@H1EWg=<{r2ETHX-?+tX?(jQzxyOC}-~oT~kiU4uW1jGoXZ+1`UJ%6dxI`495{>A@ zAcRn25{uZxAubUL{G~-<`P=)0JK^(>7cU6n>zROrBqA|MNJ=u2lY*3_A~k79OFGh% zfsAD0RWkD$S$LhSWFtFokb^hL$y?+iH+jfQKJrt5f)t`KMR=QcD9XDOqc|lfNhwNG zhW9AT`;?eG#E)F&C$8`_SNVl&Tqi<-zqBYUf3qLl51;=H`Twft zO@8ARx4Fab+~pqk`GW`i$wU6)5s!JoQ=aiR&v`)*-yTO4q7seh#2|!FViJqk#33&6 zh))6%l8D44At}j7P6|?ziqxbbE$K*41~QU~SINw4WZ`wPl8x-VK@Q#|CvTC9+~grI z`N&TJ3Q~x|6ya^&p(yWCjN+7_B&8@#8Q!BT?^BNQRG=c2s7w{A@&VPTP7Pj)HbSRi z`J4UVLHPV@#t(v8de-Jc>hKXC^9i3)mwJ50=X^nZzT_(!@HOA?E#J|Q?`cG1n$VPH zG^YhEX+>+=(3W zW(;E)$9N_%kx5Ku3R9WJbY?J-EM^HyS;lf!u##1*W({ju$9guf zkxgu73tNd$;4du-%irt=55wobP5#^U+`&$Ev70^YWgq)Fz(Edim?IqJ7{@umNltN^ zGo0ld=efW|F7YFm`H3t1%vFBj8rQkOuiWG}ZgHDC{LWqOai2eUz@I$iFCOujCp_gD zfAgFd1PSa*L?J5Ch)xVb2qh-5h)o>g5|8*KAR&oJOcIikjO3&sC8=&Ku<5O>**5v=KTD%irt=kHY8wR)QeNrDtyPke7VqrvL>hL}7~X zHt$fBcPU13N>Gwgl%@>tQI_{9M|mnxkxEpi3RU@lYE-8NHK|2yKBNvG@iCw9DRrsG zXMD~V)aOgSq5)s?4d3z|4f&o%G^PnnX-0Ee(2`cPrVVXrM|(QZkss(pXS&dpZgi&y zJ?TYn`p}nt^k)DA8N^_QFqB~oX9Ob|#c0MbmT`@uC@g=oA3O`6{{;C@)N>M( znZi`2F`XIAWEQiT!(8Sup9L&r5sO*EQkJot6|7_xt69TZ*0G)qY-AIg*}_(~v7H_4 zWEZ>H!(R5Wp937^5QjO!QI2t(6P)A}r#Zt}&T*a#T;viza+#mF!p~gg7p`%g8~n;m ze&ZImxx??=g9rS{L;m6sk9opVp7A%&c|nlSzC;wF5{>A@AcRm}iZ+6$zW?*j zbARIaH4;a>xIxIxNYn*Ey!JuJt;khg4?^xlsxp3!Amnc3Dz^q9_ajxAAZHNrAaa%C zgOG=js!SLfgglB+W!U`N`-A7<=Ran`Ac*BY6`MH3B_8ofKtd9cm?R`68OcdON>Y)U zG^8aR>B&GwGVv;zd5tW*PFAv!oj1tAo8;sza*>-nLRCJX8r7*mO=?k_52?dPe9R|&N?q#l8K3h7_4$&o zXu#Ke!?%1#L%ydGjcGztn$esVw4@ag3jC!-VfowpgCI2c&)5HKE&n!pwxu2I=|D$* zpc9?xLRY%cogVb07rp62U;5FX0SsgigBik5hB2HGjARs}8N*n{F`fxbWD=8^!c?X) zof*tz7PFbdT;?&K1uSF{i&?@_ma&`_tYj6dS;Jb^v7QZVWD}d&!dAAiogM6C7rWWR zUiPt{103WKhdIJgj&Yn5oa7XzIm21bah?lY3U<2pC^m7Dy=EpBs%-?_^@?(+u^_>+hH#Umc`gr_{?Z=UmlAd$y7q7ap6L?;Fz zgc6fj#3l}LiAQ`AkdQ(3)1u02I zYSNIFbfhN(8Og+}Wac%p@H$z^MuY-?X;E1IWTwNFfSSgtvKzqP$Bnic^A;l%h0cc#pEYPdUm{fr?b3GF7O`2UMdvHK<7~YV#p= z_=u1BgionUJwD@ezMwu|@)ZsEns4})?`X*PG@>z0Xi77h(}I??qBU)3OFP=rfsXt@ zCpy!Gu5_b2J?Kdlxi$tYfmHbSRi`J4S9R`~o!%YTfX zV;RSICNPmnOlAsGnZ|TxFq2u#W)5?i$9xvBkVPzJ2}@bVa#paCRjg(WYgxy7Hn5RR zY-S5v*~WHuu#;WvW)FMW$9@iQkV72i2uC@_aZYfOQ=H}uXF11tE^v`c{K#c~;tD@= zm0!5Vb#Cx0H~EcQ+~y9ybC-ME=MNt6ClC3HM?B^UPkF}QJm&>L68jQSh)RS4e`!%z z{$@Xj7e4=JNrE7{o-qg^l$gXKHgSkcJmQmpgd`#{Nk~dEl9Pgzq#`wGNJ~1>lYxw6 z;#D&98d-RqtYjlQZ;*pG$;n&fA~$)+OFr^bfPxgFFhzKqcPPrc6r(sLC`lAexMVb=|We!(VZUjq!+#ELtpyQp8*VH5Q7=QP=+y_5sYLMqZz|k z#xb4=Ok@(1nZi`2F`XIAWEQiT!(8Sup9L&r5sO*EQkJot6|7_xt69TZ*0G)qY-AIg z*}_(~v7H_4WEZ>H!(R5Wp937^5QjO!QI2t(6P)A}r#Zt}&T*a#TqFW<|I3oF{O$cg zqVV}&lK+o-UgjsR@H1EWg=<{r2ETHX-?+tX?(jQzxyOC}-~oT~kiU4uW1jGoXZ+1` zUJxYp7)KPM5{>A@AcRn25{uZxAujQVPXZE>h{PlzDalAq3R04a)TALT=}1ooGLnf` z$;@kH;dQc-jqJQZ4&EduZ;^}K<7uh=f6h&YxP{mdN#0;O>AZhTiM2TcCeFO z>}C&p*~fkkaF9bB<_JeQ#&J$?l2e@K3}-pVc`k5~OZ>=Xe&Py0bCqAX#&vG+D>wO# zTioUjzjK#++~*G-@Fx%Xi$^@>2~T;(-#q69K{ERiQHV-3q7#D<1~r=l@!=AjqQU>trPx z*?EH;yh%>pA{V*ILtgTcp8^!55QQni+q^?j-lZ7DDM3j}QJONmM_Jyd9ObD%MJiF5 zDpchIs!^R9)T9=*`H(t%#K(NXr_`k$pYb_gP@gaPiUxemH+;)?G~|04(U>MQr5Vj> zK}%ZEnl`kh9qs8rM}D9ao#{eXy3w5;^rRQP=|f-o(VqbfWDtWH!cZa*_rEL&%irt= zslw+!O#Z|59KlFNF`6-qWgO#~z(gi7nJG+V8q=A+l@UG8z8KX|~OJmfDP@t7w(BonWanb*j|>trPx*?EH;yh%>pA{V*ILtgTcp8^!55QQni+q^?j z-lZ7DDM3j}QJONmM_Jyd9ObD%MJiF5DpchIs!^R9)T9=*`H(t%#K(NXr_`k$pYb_g zP@gaPiUxemH+;)?G$aCX|I3oF{LOxlA$FOZVKTk#CNR~MW^@VLDj$}iF(0{hXfB#7KJP1wk@0Y1a-Y^JF6}ieYL1>x? zRff&Ky+6nle*Vvz|8wqB=efW|F7YFm`H3t1%vFBj8rQkOuiWG}ZgHDC{LWqOai2eU zz@I$iFCOujCp_gDfAgFd1Svc&5rwEkBRVk%A(WWJA~tb|OFZI}fP^F>F-b^DGLn;m zl%ygxX-G>t(vyLVWa3pa^BP%rovdUdJ8zJKH_6Fchdi1^&{au>9@)LFVxJzvnJnR?qh-M|mnxkxEpi3RU@lYE-8NHK|2y zKBNvG@iCw9DRrsGXMD~V)aOgSq5)s?4d3z|4f&o%G^PnnX-0Ee(2`cPrVVXrM|(QZ zkss(pXS&dpZgi&yJ?TYn`p}nt^k)DA8N^_QFqB~oX9Ob|#c0MbmT`<{0u!0UWTr5c zX-sDZGnvI~<}jCe%x3`$S;S(Nu#{!I6m5h~!}2%#L6-3OFPHxcJy)`d)vRGH>sZeQ zHnNG$Y+)(3)1u02IYSNIFbfhOjfxomUEPt~fWDTExhLk~& zQO``gN@iXo3$K%vY-HyRa_}ZOd5c`+CJ%YZM}7)WkU|uu2ygQaMR}KE6sH6wDMe|@ z@E&D(pK_F^0u`x5WvWn>52!|UYEY9})aFC#@DU&L37=AzdVI#`d_jG_<8Jy=RZ*XgY+EC5QZ|0;f!D;qZrK?#xjoaOkg6Dn9LNWGL7lXU?#Je%^c=3 zkNGTMA&Xed5|*-z<*Z;Ot60q%*0PTEY+xgs*vuBTvW@NRU?;oS%^vo$kNq6rAcr{2 z5sq?<s%}#1($#D!*`z>)ha1Zt@$qxXm4Y=PviS&mTPC zPag6Yk9bUk0)J^ySpH@|$PqsOC-Q%)=QIB1IWGuO+2e>pRH6}`7=#c?Okxq6IK(9$ z@ku~J5|NlBBqbTiNkK|dk(xB5B^~L>Kt?k0Dw%nWEWA!uvXPxP$ibWB^$t zANeUjK?+frBD~Ez6y;rtQJfN#q!gto!+VtFeacau3RI*Lm8n8iKA;-asX>hT$$^9A+!lCNmMOVLK?G%SC!ALI<5|JT0o_(sof`HqHsPa_)Bgr+p3 zIW1^OD_YZrwzQ)?9q7mpbfPm|=t?)b(}SM$qBni$OF#NEfPoBRFhdy1ForXNk&I$A zV;IXg#xsG5Oky%qn94M!GlQATVm5P_%RJ_@fQ2k#F-us=GM2M~m8@blYgo%V*0X_) zY+^H8*vdAxvxA-NVmEu(%RcsVfP)<3Fh@AbF^&_Vz+YMvmcQ8#@`ca;g#1tHd5Y7V z;VkDk&jl`Wi66PlPh8<=uJQ}lxXulJthbYc)fC^3meY~m1?c*G|G2}wj^l8}^SBqs$aNkwYXkd}0$Cj%MD z#H(cHHL~zJS;00k*TVT$lJ?@*L?DMoQ#iZ+6$vj69~ zKZS_Ik)lixnjsQ(L6Blu5Sl4cl_}E)p_wCBIUoql61mF9L1@-URitQI_{9M|mnxkxEpi3RU@lYE-8NHK|2yKBNvG@iCw9DRrsGXMD~V)aOgS zq5)s?4d3z|4f&o%G^PnnX-0Ee(2`cPrVVXrM|(QZkss(pXS&dpZgi&yJ?TYn`p}nt z^k)DA8N^_QFqB~oX9Ob|#c0MbmT`<{0u!0UWTr5cX-sDZGnvI~<}jCe%x3`$iBRA# zEs7G@Cp`B5vj;r)|M)?%Vo74eh_*=ni}hT>QkJot6|7_xt69TZ*0G)qY-AIg*}_(~ zv7H_4WEZ>H!(R5Wp937^5QjO!QI2t(6P)A}r#Zt}&T*cXKD_@q{VzWQo)7Eae!?CD z{>!!hx*+w!AT-~<-W-8jQlAe(3q)Yu|1A0M{S3Sk1bO~HVvFTwpx{% zRsVNEp2CF+{uhs;RchAwuiu#(H8uhAGuUD~3^&0g`)~QkE|6J!!PHGiYSe0cDpNXQpWC<>gXqr!yG_aJWh$4B_Da6o_P)Zo^8FXPnNMe` kTS1ILL5&i*3r6fM{YL`P(gq_{U%V z=U@Ie)%??+{{ycl{Qvml)w)0Z>CeYEfB#p9?Z2PD{-6IHug9aGZ+bf4A9|dA1HIq! z?DChN%LLJj6n_SK^4rVlu9DNQ3!RPyJ*nK~>H>P@U;pKFE~smHx%<%&Jp_6^=hE>DN@xr%Rq){`$C15WPt8%frw5WTD#nDmKjsi zgQ?zs0==vJ_4d$L1juio)j46X>m=E?=tSLtD${JT3FLtG}{@9)H57W+ zm|4L6XD$ALW*Tz*F~VHt+uQ;~IM8zwy`OF_L}K%L!>g zJRXZpN6$STSAS)~x~<2nZO-v1HoERCuj=tMLXt|`~?q*@+-EKSFg zsOTg5_wjTI)sw`(paSGK&`d9nCv_&m;kr+Q-q7<;s9Kj5G}QDI=qVhw^c{aZA3mPN z>lu12s_7g<1;}rxX7Y3NM784&MCU=Y#VZ#CM1ETb55QR90L`t{2Gb^ zlMJ0aA)vxij)CYY(6bkzCr=2DmpDd*@Nb~Ef?5!-Kl=f0r1kLW_zcvfj#n=O0@0JH zp0aA@as2ss_Zm%r{HoCD6i3SGWVQCNh6_Ybfj+9j7NHmp0rG3;`6p1T{L|5+J`g&Od36S4Ft8>ok99XBi2coAyt8=`jJl!ml0_4}wa%r6G(l|Y=B?8e?pw&6H z{io*_OC$ugBeeOMi5z4 zj=v&^dYq7lKqH7}&p24qsk3LOK8knLA`yLYICuv02^v?``6xj=96n5?Lp93ud{i?I zS$lt?8W}#v1#z@C{{&6HW@30aO^f?{!WAyR#Myp{)7e8e5IqHYwpC@PWc>MZiy;ug zzk$XDnTg@`7;!d44~Cwzjz6EJx3L>~6d=EW#>soOkM(x?ifWv^XPdX%C#o8mXPgVF z+qqUKp7W)mdI~ff3uikQ4)|MDa{3MQp7C1qEE|Fec`&r*66cUQelQ$?X7Y3P9>?KS zb>GtsG_$qn#zTqo9+?W?GL=53mgf&`mC-)m;xj!*A$^kJKud;idV6?!-7?kppefz? z7N6-kGoGvGw;!N57ql)p+qr<@Fds8Z7+*2fdz=gB=(2|g(af+wOAmWOzzjx$c%D`~ zhL&^TZ0Ew^X_-7v&V@iD2Id`YaQ8w>%*n5ym!C+}#Tt|aw~XFp z+F}ee(sc2*HlAG@0-Ji#4fJm2Tw>L0ek+834W$d!C9$+D^CgHES6$dZtHL(T$LyG) zr-d26fkylkykr$VL8I0# zE`K_Cs9mPXSEyEn&9GAzTG?cp+FBm?i|y-)-d2Tgp6Tu@e9PLJ5SH=RBW71bre9b1 zRu#69WGbQYa>-J9PxW3RVS9*sMO5c-B~!g$qnkW|I9)z0kpe9lwmm#u?V`BE{Ov3J zs0w@Oi(kYXcGbl%Q^oCP@wcTr-8>_?EG^yTQ5?3VJKe3}E=x;yDNA=T!|)Zj!b?ks z!u7P_VoOJ8l%Q&1e%)3EwcBb-cY2twv(Hx0YgxLhE!`;!=DM_WcoE#f1aL8MJm*VI z$5W`ra9nNaPEYf7_Ocnu-n80!^_=pY4dd%1l7U98T`fXq0-Q$mu3290D}2mc;%cLI zdVVpNxZ;X-g}u08O)1k%=+ur;t}ufnP|3kL-pK2;Y7g|8&aqKr{j9d`Nb*lZ&sAX? zwe#6+z4}QX2{eN)vvwASDXkZW`$zuT-u!LJy!kdXjqmRrkW+!AZx1SZY5f6 z{Pp~FKh66|hCYtzR~ru2mtTngqu3O^{S!g7HJR8{hU03(arue(yHXRB5Hq?;&M-qSvk+pE~RE%KJA#P5T2^E)r*VE(=s_n5(iprvRm%*w56H-U54I% zJYK_Agy{=Gyv1DIJmF{Zyst2f)2L3vDgK`?Q+9Aq~;$e1j7ym~<}L#x8p z)=0m{>olt{o0$2!S)Ti2IbFa$powa!@S7XR%ve+f$ZtMc754b9aS0MW@eh$ zYUEHgNaOnmdnd7h5v-@>Nl79wTBgZR*YgTf%$-W0#df2MrnmO8S+KCM` zL;dbuV&)#whwqhxkZCMa7H?gyJI9D1sN0QoglcAd;j zFD|gO8bo)y$^;IyI>$!smM!-Cv>Xle84i2Lj_7%{RkZSJX!+Lep77riR(7}f6FATk zfAa>bYX=j%a)mH zWcXoA$99f5mYBl{S_`x65+n1P8_b7j&8FH4s=3G0+W%o2HdCz%d!!+KuJCeU_9%0e zc&NwGrtz^{m_1lDN|`=vnI4Hke%KIA6|Tb=4ZHqd)_utW%to+^78FbBWG!I9<`tIu+3p1X=$=FPgGkC zc@q4i)K>OTG}ND7A#hGw zEfOHV`pffLf+%fG?CE67-$65%@DtFTx)A~n@ z&0^PU=v7{d*HeX$tW{qxDWzr+2DamCDC;j2_fY5AZGC7YkS;>Qd7_$-H%h5lIL$`g zd8rjvUqGm)LMd4YS!tbF6QNqexNv|Ou!2%&S~l^ zA1a(}ugaD{=(Pvk-ZU50>Kw1GPWBM+y&e66+Eqo$1IgU!WJBd_PBq z9cpnR0%NM_3@z>NB^A+fp(@oeLrWui(RjLPjW*Aq!X~!(%wcKJ!zm|Qr+OE(w7=wl zLrjuMs4lexYesjD=MpC`j4Cz8)K=CphKkpRlc&Z&cf3x8v!tPvWd3Zc%FAVipH*Q` z8_uPNy}aC4cr)dyF!pNvnNz}2;i$x4nd}Oqd(=XbAgRJ9y6jg#{#DRaI2!cK(X&@! zX2#=5;6M}JM=6c81fTJ8HC~T3MM?r2ww5HrQ(m_pBl~LnB(O@Rv zIVCZAyYZrymZdvJ(jlPoXSRJ)_}8bRYWE~i^~gB^R=?u-SD;zHvOrPqpK<(8nDL^Z z(Gu*Zjz4qUMirR8P|#?JWT9bO{foA80KtNziQ$2BA3GTe@lZ`3y~=L#DXOZVCBwGD zoaj)qLvB0;nph5GQiG0^3o?42pbi%RDoMYbtl>UE9l!)sY$ed>i_RhP*c=wG5AaT3 z`9KwCW1x~IBK7t73F-hUhO5|0Z1oovCLknKRsQlJEnPZ?7y(0VN{L_oLi|~l1gi2J zl-ucsG`XnW3o1FF{aTa2ILC`^;pp-QvVIXTUZCHkVR zSc^baOA^?81NEE^w}5&CFPFZuuP-OVRdJ?>rYgBQz$Ja<12m~*u-{Th$LohdXR1jh z15|8fg7FR2NK;OlvwZym$^k>S)gd&v{l9^hG}!@-Bjp=tNt0L2cw4`Kat_iJ_No~d z$v4oFCd)ig+uuM-n%qE~3*SIXnzCx1me~=i2;$YJsR@UYG~pqT`3Yt`71YPSfl8X< zmza& zDoiAyp;`LofY2vsNmDI-JrDW>Eori~z`UxTK0!;GyiY)ItD5}*N~D9^YL7YIoAGi& zmPoK~9;j+b#GA~|gpEkB=^Ciy;8XslKsgd-s8&2IeZR3eY*+;4=O@*Ap=CNGtNenXWkse?crQqR)& z1Bc1RQcy_~$vJ*6P2`^|sHBMqmoK2FNK?|QoO7UWsvxC_S(h{0+3E$&o>%cM!8D;zhNj$yb+(hwPN-MsvOy{AX`nU{F2K2W`uG?^6Z zJazFWXi1YD+LuqBpHa0f7Cmh8)ccbB5+A4%?`sZw4agS67b0;hY4Q~9LX9VK<3*&2 z4Kq`<zr^_-Pdj9Y+@=b zLBWyY<=rP}r0L?#Y#b@SA35yh6;(|~uY~eX#7W~=2AL=A>Nrm-vxPG$;r56M^CVvateqU7hT+(D;`1Scgt&OHY$nk~L$H^Hb6T0nOrHx*9s8KtC~SgMalUhbs1pxFvC!|+h5 zi-~kpD+c!it-a=~cX4rC}WbbZS;RHNWO1y~+l9wwE zUn_!)%$|c47~Sy|Vgz?pS1tHUc0x%jW2nTL0?P{Hfs;ri2$AGk8tQB)rBAn~q8ja= zgfn+}G^ewCYd|F@ zGt_578Kmk563g#sxxU4wL}&w5KU8Q`(&9~2lWz^E`hgyETkYkZp*|B@T7{SdeI+%W zpcMv|gDNNF^HuUVC9p~7a7f(!>N(|>r+p$fQ;oSwnj3N)egP%#mu1*aCS2hXtckc{ zMcBA;Rz#lNnUTp)Q0FM={htr%@{4LFdROT(@+I$kGsFWW7}Z15rupz`Q^vx=N;Od1 zh)?t3Kw~(rUIP+`w(gujt6y!vX~b@*y=yC6a)rI%X3FJ$3h4C|Ha)6eZNRzRMMHOw zWan^vf&*4XRkf_G*bmTL_r?T5(#O$;FQ{^!#%;9$C;I1$wvzfHP?;B2mwNnE;Sxm6 zvrt`jDXyX0eFUOPx}Z^zIpXizij%9L5=5eZ^!SNtcJs+JB&ta=`U#qTy=6jBtED~G zB0-9TR9LfiB*qi+Ju=cn*A&!jA`Q)i881SWxw<*5x7*#hU$BW%ftpQ|eM=qmQLbVt zHhGYu;Z*lv<_Z^^JXtxi;+`-Ql$Zlo*fSU^^97qo2N9@vL-uVwPQ=qzj9Q?oC6ii> z`cKeelOyHXlK+BDWKlF#dlXPjs=x=TG&N9>ice=kmLRe_5vX{>-2WS@#U`zHS#f-D z-;D3m3&keSu9$_Z0#l9CIRpW^!q%W4&o-DU%0E!E>BDV@p^CFTP}TC7dg{(MK0Ymgq&|;HjvMg5o6(Rf^DD`!P?QY>x0ddR_JruOqQb|X@NYqjO_shKJTbx#1uZstkaFYi}mP= z>LC@r6`M3`KcMTrU{f;fR|;z;@L#l*QwF1MK-EB299mSWp8l;0b5ip4`p9h!qrhp- z|N91t(Mo(en(=VClIkvme+yb|b@@snY=|BL z<-EEp?8OatQ>)oR__v_m2gh1yc85dni_WP73duo6PEt$fepV5xbwD8*rjvh|gKs-t z7c_H!QWA_75$_+W60z~Og2rc>L}FwD9$&%c?HFb#AwL?Wlv3Tcdy8H~W^-B4_$87v zjI76|x}Q}9TBi(>Gpy`&QiSc>N}jM(*yEcmh)`Xz>5kr%G&vmjaPl6<@$T)GiE56z zQ%b8b4xX4zdlQnjCPxZT_p4Km@N!w^pf3Z zYAY9xgn))R@fYI}s>=!|c_pEbQVqGWmzRTKgJ|YW#CF?{=pLbS_Iwo(2icHTKANF^ z_s$CIvK_6r(2`-Ba^e8|ZJYXuP368xN-x5B%wgN>8Co)I(@Z!|s4h87@;Y~po(NJ> z6y$tSW7tH7kU%xm*?}|F{W`0l#U@)iqJP|0+pwvvwa0PyjECqSQ+2rD3@tX<8^RW6 zs4m%bFE-ic)G?;}egToT)<#8cmmtZTsY=0(`j#M;;mDO~9Ak1@mxhDvMd=)k+ye;) zOm%5ENH$hbDVTH4gidz>rmc0A?3&9Puic@5p~P!Hx;fegQVahTuGfnVud9%;-3^;M0$gNGN~2veYgzG$byWjK;tiy2&?;@wO&;_t|b1Gifkx-=Z*&I*U68V($alQl`& ztchwFj^xoIt-7?%bTvWRT85);G`mM6M1N*e9sf@DFfvnEn(Wb^DxBQN=w30Cqj=+y zm*XQd)!J82axId%TM+ki)U-8;a7lot-X|W>72fZ56f}twk|+>`C@Zac`nRCurFy-F zs+x74Qyad4mfznWIiS`2JukTiI8>7hl5IDQuk%ATgqLFb3@sU!2tieP5MP1D{{&6W zdrFzZITkg!8B*ce98c^Qt3mgxt;s|+nOWFjQ{6ZxX*S6Y3}g%k+4!SOZC<#x!Gb7} zd;={u*}M>@WwoZ^JVTi@duWQS2O>W6Qav`cwT?tTR7;?;(z7?l9L9HVst$fR5G*P- zP06(i8a5^Holt49$!Ex?wvzWNRBc{}>Jpo#qNER~TF5!d)u4N_C1_@HW|RIrbGTHvy)i(g8#u8k!Jar= zDm;0)@WEP|mMWaprfP(@b5#96ESU$LbmLs%QsGalaAL{K0I8Zc&|;J0o0!v@O&Yl~ zv{ZPKYq7etG%Z#5vs8HUXc0nSHc77DP>o;0ZUHQv1~_hu-AXocRzXURbUGjr=CJkp zAY0JV65`E)U^UGVZGGknXW4N2ai9+o+5^hVg_hti7Jr^4b7aU1bRqr}cfay%E#dGZ z&J0Mzc5US^wmCejZp4L~s@Sq`E5*$wo>e!3)dE#jW~vtda=R0(W~k(9rg|ziNe&L2 z%@0&nnW&ze=Lf2)TO#jysoCEI&A~3>p(JwzzYV_fQoNg?Rbek1NZmSU0bN!&+MiOc zu&+~P-(lIW(f*WD-3Wd&RjHbp!_of9sC6LtEl^cuYAbl(S z?cW9Uju}ujYl{~QonM~{T3W)E>H6t}u^AY1MRF5$Au)ox0UpYs8ZQ@6$sCb{>Zf4F zQ$Zae2~-UvluM7Fp!SpiRV|4T`~u1ZeF#Er2@>chW`Cf{#4u3z>wJr(KasYwdJ9yf z2+aF^g^95@G^w8mxzkrnO%J9@j);P~b8gl(Lio3!&KpA9yE^mJHS`7b)-5}y8g!hn zR0T{;4}r3CI|d|B2_joHU$iyRH$X*-s{!;C5%aGKQQSM+JgZ0OFg+Tghk|CjCPXeL zTg{I$0H zt14V<@?3(gBT2_6Xt7BX2rmEjT>b+Tf3Df&83zu%FW8jm8%{WzO}XLv6V;L?Pgb_Q zr3o`$giVRQfvRdrnCTa6O7zVsnTSd7th!IcLp9MiKqUuvFU%%n^=qPUfQl4%(C8}@ zwx|}H%p3fkU$BY9z3x{{mJVEO`~{m()`nX8*pXM=KUA3d2C4?K;7~t(f;y~(NPUqa zbHBdw30iFOY>kU)H0S#SEjC$$a(#`o`6p2Ajo7jm-g{6=5{*uUr5b3(7i{8A3sbc&V?J<6oFW7_^OKrt}qY8h@d?qci z`ELR>n@F|)+X`=fj6lsM_HMs`Mw&9GWDiqypT1y0+}5X|YH7OI;q?hxZ1OCey*7R2 z0~9Wqs%PQcE%XJOY8K9nV9?;gp)c4}v+%5UAM=&>uDHIxCE%(GtAT_Ms{)4Tp`gVk z&%)VG)mMb@Z=f{`&n@t5r+&evnuVWSOSV(LU{lS)lhKat)Gwro%N^XWmV-yG_;nlg zP;D(Xc^1x2>=$gRS-5wd4jc*nf=x9GcX-hO4f_R~$U)?`dKS(m?iXyTS@_AbJGOei zkfxf2=M)k9zhAJaX5lB#pC1WMQJ?rXol~>$lV{<$hreJ`V&IWOl_&Ia&8A^eC|=T( z;gZvquBaaDVLai_9RxU%X;OEYD_-t|BhYMnQA$061{i?(h-X3LM@({`1Y`o;byGpB z!m9d~xZbT$oa@}yBoly?EF&W^(4CPE)m%mfRF;w0OSg4D{0dqX_RN%&TOJd8Efr{X z%t%it4xb%TK3`2x(BiP?&m1wc%y{BB_*BrUu-Hm+XdSUU5x^|ozJ3GEWn`2RhuM-J z9OI>0F;PY3nwfS%9^5&*!Z{qtm>X&esMtP1lMx`6c1yx!=zflBHgQc_Dy+Bcm`OSEJ*ml=YBm-L!X1Am zoq`4(H!F{q6O@UeIwy&EYdx%oyOJYEKR}cUfW1B7~|d?Bk?BmldupzU0xn zI$Z+kNmnYI=-E)UZw=S7#NY86VwSprk5+|knhAo`AfA$<21=?Zw^eHJfa6Ewm27#U z_xdepRoM2G1B+5?e$odDS~4tB2jV9!5*qYxpxGUaqm3)zxI&fyj6}IJ^ z+Io-8$$bF#9|4%HjxURDsOE|mN{Pc9^4alKz?LTNj&+5_RyHam&U{a7pDLU{c1lUX zz&p3qmUDscAPM{^|!30q+2!SsW(H(i~1QJUq2y5b?d8T)DzqsH8gQVp4eYMwbB9NZePL1&5f) zyilf@>(YNO5=^c_)%K8hd?`~;gVfqo7*CNaEQNHyK_(7Qdn|#nZb&J~9DYPSikN>3 znvuf+p;3T)*UVvQWMKm>bLF!Tha_O;oaVA~%3NiG`C->Gi#5r~ARDU5LPIHa4ncqB zuno}+_1YS!qz~VkzM>}jH&hdi&izDrmGs61qKaT0sESaGEN7t&!t} z)bnbE;fm@ZRC5+7X?70WqUnCMNtmeSZZDu>)6+*fcquuVpqwX=Zc4s2A`|r$)ziPJ zFtH&Pf5(Opt>=E#$Q8DrHPpS3;yz1%Z>jysv6hiz?N4~&@0BSBaZ+Jv|1BoL3P!;+ zbA=x@)U_G{stPciC1L}cwmuUsbg{N(vtc*XM6;D?Ldqd9dW66U@s*dWe#O`5wlZyh zeVl-Duhr+wXEJ1DJ~M}%=Ae)@*lM84EOr9rvyOBrK< z?ii+j^Owv_J!>Z^qXGdauw+v$RtQZJo34^cyf-^l6RM0ViL29>u~^ed6`(6EK{!%D z%_birK2TxcdAC@+_6%2^~zjk=M5(&P22^Fedx)QaP(6$em_7u;7% zHW4jgHfdr=ERANGK$mQ~6q|JH2!FoxASuw6Y^r60FMc8nM>YiLl1)j}Nhz@@8P<8Z zlqT{5xvkRvMDRpr>@}N44wpLwI_gF=Ph{9$vl&`!lA;GHHHCw4$tF%;o2q&Q25X%I zbjc?6`~x+ce4Z8Pl1=zM43#g8kR$OG=jBqGN`+so!Z{!y8%7E(N$=}7ypJmw0vdD# zx(?=Wa(Bt5gp^ZCgO1I?@s-@7DcYf0v+%2C;oH?ep}JzztyDNEuSRp?$e`<1Y`W#5 zL`q4T*!TPW^b!$v=j4)Rl$k0_Mk=*($6-xcXezwa{`eZxRz*5+>dF%WeC4YOm#gX~y^VGC%+yKD z^#L&ir+b3-Z}Jq8ZcQzuz>>pUf}ufola1IiwGHV2x*9pmnF~6Y$?m9BC>PVLM$WC~ z{#@WQ1cn3lrYe�NFsuCQ#xriKGu_G``kiKY=%-|I`ZlqH*Tn=qv`a@aC3Rhfjj z!e|w#q1;i9Z(&zW0c)a1OVd^x4xBo>E-9$ytX!a=p~l^~UhmpU2cjp9B#JwGAI~Ob z?Jq!n3(7M0^&Y4jI3-ni2ffFOOuUjx5G|_5{cos}jl@)CuD0Zr>&1%MgquE4le(t@ zAE*|aq>!L$cg!A1ZsOM~^jEPda`4d3%7iTFqu3-Pc{t=G_=FABN3kiU^s%3OBY zHp#w1b?+8?3oSOq3O}{t2t-dswb&%nd^q?TdI9nqX!2fi$(5yv6?Y2%`c%+jldL*a zrNV!OZT~80vB_&X)`L5ppHCFD*yQn@D-Z+GQ$dSOUiq=m@u(L>zlP!+wfHms#^0I2 zdn5>=--1TL#G$s$rB!tQThO!>*X}6C{POpmgIgjMwg~k#nro^R^OHvywCD^(Jg0Z-;afUg1%mSnV$=T!A}xhtD%H{i4FzPOOwd zELK$asowev#jCBJ=Wv6;H_(JyB+C=&>eud@@lmLjNH}nZ1mhB{4;8M!og|220`mo% zDsboSEk0IPU$nIXcZft#zuvyEbQ}tZNN8e+{)wsGH#VJ9fjfy2BFma8ut$hIgF+2 zrV5vbz_$<_P^MPQj(Z6}aQW(P#o`bD&FUB7nrr@&w{& zz5-oJQ#rJ~%0A@IMxZi(`_3U3m#H!})}OQBp7U~v!IcqvitR+w3-tPRzq033Q1wF&LqS!o z5DU$w+yX)=^+O`*Pd=zB+WHiKiC-cqy%L5=0kvYHT8@;5En_0MfT|TUG`h(SaBdTp zRR^k8Owfw?;c&(HGds*uYg|)5Ue3_yriUj4>^@XotgO zK62f(O~%4ZZ51HDftC-3%K%3SoHm0w#1t;2sWJlKc{Nme73fl$E(xJY&M=&DJ6i85 zoHUZ$1FU{PCe7i=ePa%n`{p6{&4KNfK-G#tIBZHP8K`PhGv^F+DNW_Rahg~zA`aF4 z?qsOeuCHrJKGRU$$Ke#Tbd%jT2(~M1dp)(a!i65PQ3oc;hVK0$p;}u85Bp&7O9ncg z)UyRG-K0It?IPkpm(o<>LJvDq*b6h%_Ihe-WdyLbI54XZRAXX>#?mhak ztFG?B;4iry{_+_#2G6U-b=`ZD4{MtL$7hN|uL)YjUlc-SvN++3(?Ow7<& zx}==v4r4*5Q-l@?vYolDTp2pPjG7Eot=Ln2{zRIR`HXc_pet!2Ct6WeKM>(!sO|Mc z74L;QC;8F1Juy(VVunVVo^}i1TMu+4O_ekag`|F9p%B}^MCLB`sda7_8cX3=QQ1uhg)hwL+Z(5B| zN~8MnDVcyfr}F$*uE++a^&>`Fv%jgrb=-xxvGHeuq{jG*eHWv`rX+}?l=^|2B?m2D zsueTUk|w)*xW>%=YI{9FlUJIgHR=bFYnd6g*E6(qlX$Zo74Vp_y`G^K9H>e+5t%eN z#!HQf30i>wM5~QIZ#OT#9y!LLR?N`M!gIkbNtgyLpi61ute=}D-W&)o8nl3_6*E=K z&?#x@$o(^D@lvgrpcO-4-W&)Va)oWLXK3jrudRs@GKX!iXJ|>2c(Xb5hDdM(X0T!) zt^N6nEgjG52l8Qz7V=VKVn>y~SekfNKM?3M9(k!TF+(j)lu|!%7vNwMFBj6poZ0gx zp4AUm2b1tpt(d4LpJ}Gv2a;KvO}5uF)Y1f0qZ)-}HrZa!P)k!TFgS3*wAmzH4`g*t z&iVmWKM-7V&CRBjFC0oGO?C?qU}83{eBqp1^DLZaNfWUoW|N#7bA@y5 zCQwNeNAY%QML>4U%mr>|8>N6sn#c}1z7iLWz=6gWPAT;Rp&o9l?e)MG)X}X#EltyP z;iB0U&LLKy8YCPjGMiQlZi-ju*nkuMFzPLA}{#h-!`AZoN8*l>oM>Q#+R!meA-bX2S&QsOorCKpVYpC0R zle*O+W(WBM&4QbAm>TMYz*{4(7Tgr~G=yjM0}0|R!>a{1#cQbBfRp9T(xfo7QQsOl zImAjXX^k|FF{#2yuD5S1A>bZ#1Rab&v$d*GNyxS6y?!l-?2Q#v{Xph3iA0j?%~T^z z1RaQ~&jR6jQY$8C7TlE5P{&4!O+IcjkYN)`##C6Uf#h16H}O5SVx}5ts$_Uqje4MJ z#RScQn_V(Xlj93{saDL;NK@h~?p~|_)tH!}ktX65#-G_?Gn=$*8GkA^u^Q1JAt2CD zi$A-40=<4C5?OFF8?`jqx1C#q^nrqwG- zYayny^U&GeaXyBp?=5D)V~G zJ!<-Z1(DE`RM-n{oWdFtPG$238fmhRm4Ht<3)mD|NfTSmMOFRq^cgdtYQ-R16^=BW zyh6drWj5JfPtaO$b9!U^nMeq;Nz>c8t+n9hD}rVkLK+%@UcaeuEx6edH&p8uw5sg& z_*x;AXmNHrZa!(2^!ExN%0BO;T_JnL)?qd-~N2Zl?a0 zCfnY!!*#XpMQFbIm}ENZt#MIWDYd({qYW$gf{hc6$azr9oqkxXN z2Wur6JznlUQqa;(5+PPpTDJgQ>Lw-h4oD#8pg*P9oth%#Cu?CiX1G<~ux~-c-El>}2 zZzutk!kVdOsN-oE72b}Hza9yHSQ(CORcxvfT-N6re?V8##5$&+8tSat^S#wjXA)dc zNfWtdhaf<8HPo4*1S&%VQ5j^?H?5=zBUn&L6YJ+uO`t1jLiZGOuoYi~mf1j8Lme3n zR0bTVMm<@jmeK@SGgB%bKZgu_u5%p{5f#pLtp$}d5qUqF4Rk3@+2N*?rO9#OXD($G zy&-Crvs!RFEfw+3QW!v&(o_p>r=>zTMGNRsn#j^>Hpzekm0AJ1l%`s6+qH!p%8w5l zm(o-VZf*x1oH#lh7U)u%YQgQ9ERHAD9q3Y;YQb%3#yur9MYz&ZnzF-9snHKW)xtzN zsduA4YQgPXRSa|~GoVXpx|ME{0SBtd405=XrtEN2YV^Yv0za6;%cV5cf}1-@N9QDN z73fl$xDnK9NCq7HsKqwxe36>WF#MODlaO*sxpS`4aJ*c0PD08l<<800E%8dJ?DiB6C!`$c zXdv;^TB7iBHPlIMWi3He(~AI5H5;wA>KsyA6;wl=*`nmcu5DG@6=s=JP~ zw_p)g(nOp=pfcbnAe!YUWJdwssR*_;c$L&{NGYj6j(|VbsLSr zrb(KZduSxuNY5NbTLvm=VzDsz%J)Xq-#|;6WWaI7s{%lm(v%CPIcg|ridy02XvIu5 zA?1{kG(l@HhnJ%jZ=fYjGT@wblx_gJl&0i^q0}IC#L}8gUWE^`>DPpmGnJ5Tg6mSI z#G$FGuit`ZQtNDBZ1BmJ^SzaBB2QTQRR)|jvnJ#~m(rAwa;7mJ+wIOlREO(AT(( z&9Zb`&R=T@&7axC(j(tnN>eSkovDmfL-?pliEjPHW}87OX+o{;dQ-rza4onm@|bhC zQd%KkgW%h7oet<5esTSPM$_7xoIM}?UG}VIJmzMzz z17xpfX{w=lmB;)DZ``l4*KeRDONEIgyYwzjY)>?2|Uyw^6;xBtWLu|D6YUe6V-1-H}40aZUib*Y=~B~8+0 zTSB`rz=1BMsTSN-xV_t<4}@y% za66R^SCL7>;aVH?-#{ZxJ_)yNUCX{Y&D|SlES>jjfqLXP&D|SlES+O;NeG~M3mNHG z^Cl7wxL@g#*QbHj%ax@gqe+#rG-YQ6!BSPncO}EbCl^%nCKT5A3U0}zG}R7wlHn0} zKfVHVwWj03gHYAlnnk{6Yjz*0+7XE)!iIq6O(Z@`g;%->&vmG3t#BmHRKtmEd7`&x zQ|)m3k}IwX)5zi2*Gf0B{aRE9-+@Xa0bR|T7$bpdZOxX9s>vdFDNQxwaJD_5(ltPr z(v%hFxARrKv*79hQynUNiojzZaj=ueHPN+f0FK*$#9mO|`?#C{@>y(fIWU zbhP3P)f!)#ED;YT0MMm0CA|v1_R$Ya>g7@6wE2nyraeegiFE zI4bm2g1t5y4xb?xxS)|H-`%%u(@7BTD*6T*OXnXr#&G`$*1*p&KZ$l&129bH(rL<3Qz&WSefKo45|z zb42G`V;e!@oQmox6^?p`fOHchT_eW{*55#*o18R_5G7d}?r2|GI`(|hIa*t9+plJm z^u!F@>XagHIl`s4*tpZf`jos0uG$p+XrDW-z z3AIQ%w3%v2lZ-02w#bI?y`?mjFP!_$UteY=q1hKRvZXYYFWl0{-N2p@_!!m9;qrxJ z8b$RIHpyPUftECB4al~-0#naPhc>Y3obrV`^bx3*o}SG@|y~mFWjb__-GmUbJC$rZLQ!l?l*t^ncP}hqXAvbo5+b4Euon# zRQI#scNH#QIJbF=suLk_8`V;pD)`Lle~EdBf|0!z-LR>A;aq9-`a4j~Z=t%HH!*8) zzuNJ#-T$l^OwyqZvZlISD3nrTR0Gv)iIAg}G%?{Q=;#N+(!I{%iX^r2^;=YCi@F!>00ubLaPHE8!ADVL){$P2~&spogl~8T8$1-o%Yfsj!SHCq^`d z0=m>q6?|q-5!Z2~t+Lm1zm_kYNu}EA_(B#uOKB=!_(N;!?Gg~PY3U2+vhJugt*sgA z5@%I2zv-Ovg>(D1D(uZJD!i1Y@`ZEzwxPB;NryHFhbkk@&C(#{ppIUqqIxQ5=_V~7 zS-@!Tn9CEF(p0{1FVIg%uOQAo9XeC3(_TqDhrnUP?c_C9wZQs5#iN_Zg7*45kz87PQ(&c=2zV(1k|r)>-1>0kyIYpRF5RBmq(hr3 zT)uFwy?p%{In*4Dh}Wewl`otvJ42;cf$p?a+FHKwr)IL87nE8{^xxdp@`Zcnbi1Q` z^d`{JiZ{@BFQ4*-lfFhR1iF+aE}j{)8%kL>d95y5`Au8P7yguMYr84S;xBtGa6wC& zw6-S7TBDw;bC=RY?(-0kZsN$ut~W)qhkE(KS@6C}un($<7Lm-Wc@xJPqle`SC+V@) zR6uw1)7GRKrOwbB+|tCeq={(p0ify&Y2q)QH}O3BfgMSyHC`@s6Myk6oM%}&!q<1qkt}7rQryzS zvvd=&)n?OvLZXpFENV%U*4CU-7PBd^l&1K?DJ5y*=H?w=-&Hu{3#g=t_+?jE_FCYo za7mNa)`Zlni&4lsh6Ng5IHfF2-cRM_QkvomrIKFU7 zNjDJ=XhD>{eglnea^^FxbM?3F@0y^M`HZtumL~gqc)60M%6vvCNfQ#L9&;wAH&mmW zocW9;q88j3pIr~9DTxcGl%$EcISHbd-ZRzs!huSf2!7L;;L`%Vev4{!lQW-fH@8Zf zaPF<3i3?{IAZcQX=nBhT>jR-0UpP=n6PK)-!?M?JpwUgvd`6B62^Qa5=_W2+)l?dD zJo8364+#J@7XShB{;q`W!bkv=fOKFNPoKlu1 zJ2H5=)J^e)Q_9lh)eSFK^Cs?L44do=zkABVxz43-iZ7f}(oMwSSej(7XAUPW9H^v; z@0m@~jc=f(o9qiGI>yo@dp$$r3ul=jX<~xmK_}h#28z4y^%kgf6Gsbn%n`7b4J>oQ zVa@J1B`odB_mwz6!}1e&A1JBArrna?O?X>x!SFIT#WU0QS4na>C+QCoqobkpYbRj08PW zjzC8%rnXk*GtMbnn(U0{z4M6}pr1=fiNE5pvufKBxnT!5z2KueSKg=nY3i3^YSWbZbU@DJ5xQKgqgD_Ij>x zeBnSPO+bw6+GSF6PktN}5QoUC_~L7~t{hldyAz%NLIMdHsFkojTh`?cYEn zO-^zKtEIR}8?urnQk|y4T3Z8E7Xw}CCX!tibVw7q>a@@Tx{@aHk`#3G0~w9vJ^{MY zO=PSKRMVF2QV)$+_T9vw*Kb53Ia0{4JX8ZT)y2FVtlt*i*E5^S z7w#lyj6N}&Bs5EDDqpyhoB`G92Ix|nk|TvumZr?YIf|;PzJAlz@`XFe8Ja$BjQkoJMPATc8q*mnR zQku#aPN3PVRwS&{;vVQyn#vc>hOMCV@#~S~MoVcbUpUbxhH4rBbSX{c3n$b-(5rL< z(4}s|$0PH?7Vry-ecgLXUw_#CZ)su=(+Y;|!B+|FmYU5O@|84g+gj><)-8hi@Dk9` zir1fhq3XyyN=Y|u$Ej6x|Cmr73aYl#(>D_#XgLkd5|; zZv7?mreqLc!5`>KH}Tc5NxWg2r3v)*chP(O7FEYLQA)ZA_sXt?fd^W?aFQUsN)TwI zc?({_m2M)jSt_iN22_hmpex0JINl9a*q8GH-SN7hnT21pwkCzI0P|&|ftD}a?jDAOjihs$&1@=P zcy32zWj2}()ul8gE}T-5rY+m_iwZB7x~Y8O7p<+gWYPnGa4w}OIZ`Mk-GqU)A(FkG z+giSGQkjj;$+aPTZ>gKg7k-gZ-9q#RfMkG6X-Zr;r6f&T?}$yZ19OGT7mmYA6^4vS_l>+Pi#+JiBC6`^*D_3E zvw~Wh92p4Jl{67}7^v3PEY@UI(N`;JV&Af$mL}4bys8IurJGo*6x7lb7o?YHYH`|H zzHm}%z5Y)6UkxI3=}MYNY!<3oTeEt!_&cZBOtpOB_&`OK6a%kEsIGJqXFZClEFBX~ zvq|=Prdq!6t7^HW#2w7e^~-OdB~4meBf_#=n_&^?^&1YCFWfeYm9oSc=u(=>7k<^+ z8mQKfjDw{#F;zE5G=C;xt33qHX{KtY!sQFEbfUh(8>%baL}Ig0)$(ym04v>emA#&+ zmM@&lW3RshwTHmbdT*eKZ%U*-PUf9%5U}QmBr2;4OPUyJ<1xMmfy1Wqg7gmQK`zPP`V~RJeTMq)L1J zeM=N-HffIf23opFYwIoBr)?1r>CVd+cVlpHCPk~CpxtYBoXXR3({C-y~_j(EgDi22n; z(lw;eUP@E>!YzGxqE!K)OKB=!xMOg)40s-NOJ6uTBGRO_HBc?vnc%GEO(Zsx_NA09 zom1+GIr)tsmM@&3zE=rc=kgx%y`?l&T(~FvK;=JTslL=r!~mKjS}NnkR|Qg0J*C36 z;C2uqUVN=H_{LHtcTl8MPp<1Td>C3i6W}2?vq|Eh!f|mA|%x~Gq zG?#E3~6S(@K!c>0Arm{JAi4d!NEysW^rKy&KcbONC z4%(#w$JEN#Z#Z0@T9X2*xjbIJr8Je{aB?kn-BeAWOE%S-&Uv&*?qjuP@2RSt3YWXp z(-xr8zIY&)Y%1;V3|U*+o>5JpEA7w8*@(Yp?LejBNMXM+SEO_(sLT}!bVfCSuI%d; z7An1IcMlVyz2X*=Y7q)DRMnYVVic`&ocl`PaJYP?Ietp|lR%dhuI)^3rZXheB`imW z!knqr>dLL&vYUA1$cDaw)_Aq{Cx?kEyj)$8+A3`F>WaK2X8Uq=MQST|jx$=pVX;Zo z%&$322&}1kn`}!KB0(gXRbbmw{UsXF8LfcYrQvL3`anT_a2YT9=m!+|Ui<`XsdFdfOUN-a5>;7g35HkLr1C(m5lLnxdaqx73O7wwSH$nW{t8rr zK!KH7V`PS^mKn@Awd4W15`R)#6?EtlpyDvll^$kp6={+^-g2t!%thLpwpI}E!{&;7 z6z-g*tfOOdE> zA*ZEcou_8wv|5S;9z%_4ySBDe7GH3QsfdwKzXDx~L@kk= zmTJp`;E}UjB0VZx$Z4szlm}9#4{7ANbI9OqHfe=ITg71k@|%7wBbj506_4lzzrcZ3 zxDXjzUw>!&Nv4(!xS`D7K(pYsF5{HGo%g;Q`wcV!9!^UI)%|9dfUOZLT*zsuwp04% zoh+@uX=_FDW;=yrl7TM8|B;0hkFQT}83_hdwDKFOWnc3Vat4aoW`)27t??@R%EpQ| zF}cTSDgI?&Nj{|tb0&H`It$fAl~h#L62A6ti{_D$bQY>N(0B+)J|(JCRFis zQQCt=&Oqje=?hoh;`YXjHfpL;=-GlF*Q)NR%HjzH<(4TO{<6 znQHkFnevPVas{BY|5FQyH_&2}dxYpdeZ@(gW@z~lpSDrkEpwv+UIx8^7Mm>dT%Tq^ zT>25W6C3V*EgH8o--As=&@7ZGf3Y8tXEl%%WP?q-93Rb4Zs;&xintKdlUhXEN%c_;HU$cqnYeCH>Z?O@zIT)r71R7@` zrOYPZ>B7sEG#wKKNhyneRYgG*Z>ScVG}5+X#iQ;7lP=kmvxAf}o9sT_;!s6z&!%|v zC}lQ1v{<+2m+9TAY5( zQ2|PsO=GL9L|uloi!d`$y#QnnxH~TNt!stIv#nsWK-h(DJ3>>veQF-sr@=Fy?Ndt9#Hl#5Nn1-Zn@WXq&DHDggqdn( zNWAlsO>vM>%536JF;!S&=nd6klT|n;l0E2_DjauqIBXS8(7xFuhRswo6`PoFxWWk>U^8EAa;v8bZ?`*0ToZ3h_Oe|y1&o7?So3HJXN}<$ zl@?kQSWWaeoRtcD*+7W4Ofz~q6t^c2b<)Qa)Pm?UV^H1ADgw>PHlijq(Ib?1%+Ywc z8ad36LRB))F=a&!16@t@SgRCN6Fq`zWh9-XLM^TeM}|E`+YU#YON`;lN8)s;j%f-8pFA2?dG$ax|F8u zB2h}qhTKWa%cV3W%NwOEO}$^nh0G`TlMq?T9!^$n5b}B8osyGO>xUnYK&^2ntNY;5BNltDV^KOImOrC zfojwPT}jiHtV3GDSz~}oa)GX-X*_#X-d+d>Xwnj{T!;=Ya-0fBZrAwVB3>N z4kscDDrw5urYjS-B{b4hhnd-0c>#cqCw-u(Mw&cr*^b&v5IN5+(CatQat1nU3`gUY zp^n32E8VmmCU)m|O@}kwY?p^nw2NwVle5M^RqGa_fmgbTqZ6SjQrlU6vq|=PrdobP zXN>`>sWDWS(p1YqXN}St=}VBT&tjt{hcURrj5flWml;G89kK;^k7BlI4w3qaQfnADNN87PIOv zB~5auZ5atH{%Z9MtwpG_#sJj}f~m$*Hzms(rDW+g1N)-F%cV5sWE-VMKWxbi1}$DL zr73$?S7(hOt$;KVFPG9(>sQwjsAj=Hm(rBmzbU186H|YWe`%?i!wI0|?2@I)XYF~p zl%{NZQOeTf^WwZ*N>eR;nN`1PwbfTveY)T}(v*{J5Rj$gn69Ns_Ihq>VnaCTI{E>s z8l}8kN>fg@QOeSE)y$BWOKGZAv$MuPRU8Alk|ttwG&HV+zlcpf&&JD@G?6~0pw>;< zyYj~7#3mG?m;(Vzlee)1$gewRvuTpKqyQs%-%gpmgC;hFST#$NZ5P5~!ug z(KG_&x1iBY&Kg5Tg8jni9kkr7&Kd($zU@Ht6sn26%PAbJY47TnlI{oOIGd~ZM0O|=%>3{yijN`dZpT~w=cwBSA*oHqpMuGN9of*ZyT zs%&fwS|};E;`PUZR_EA&vpeCDD08W{6f~1sr;<4k2Q!!h)!oP~Xbp9Vqyw%pNt0)b0v9wY9Ea2RJFYUfVhW*gQ`l>AKWNrY zTlceI(X64qEp1Ie_Vtj2Q}~#7!!H#s`^w~hd>ltks-jkmzZJBkNy_&?D>QPZLj!@< zQq{Zv2UdgTu-3zBZ9z+#WZn+=F-8lMk>Cxqq{*g~tsr-Sx@m@HtCK4tBu$tcvq^*g z4YVq(rSD-&SMn;#_m&(kue3jMV3j>aJyV(GcqK)F#ow!3{Eq5k)ziP>a2ZKF>Z1Tl zW%sKLm#_sb4r_cL5HVMHZ@2=zXWHOwxtenfTT$O}3mf)f%rh zrMVH|dY!z|=0bU;9Y}vjzHXq)3MUmRrCeeA8F;C=$-cssnFZ;Wq~p_&AbKS`keU0F zgu>$Q%q#~I#_nhdSkgqqo0aKJ>(>JzwV}Eiua%jFkvZf5sKtNI%pwkxnZ??lYq>_f zSedEWsp)vKAl_>I>dY*MBrc#TV*3ouc=i3x2TpFgT1)#{nOR60B}pe|p{)9xnI#{M zea*y>Ii)!)Z;Tq9w$}R9yNL&8i~07hhXbwk>&^C+)Hl*iQ)-NYX1v~PU%7TL(3SWT z1Q}^k0}o93G}KAcp;o?rL$zGXNy5TfT}IM5SM-5`7KddS4~ZPY@w60)oE@Z;>PCQt z`_;?KK{iy&Kb%Y|ymY@VSCW{Vu*t4qwkM>*r;|FNS|O^w=Hw8UB43ttP8Cj$6iR9S zO4^!TZ;HRIB`QSKIZ_U#;ewf|Mh`nj$^mBYs+ljOtrenr^DZsv({{c27U~%U3r|^f zLg2rlT3W*P@XERS(E0T#6|R+}Z-GBx8P`-TXPlk2q|1~aVDUH5lBV#6Y{3PUf+1LL0ElXlK3)~^=mef3&;}!-#~Uau=DXNApa_8RakGKsxD!+x~yJP1L&<=(wshT?8uLO>M3CCTF3+ePbKuAgQ^+Wh9+b1*k-V#G+ad zOjL2VTIJeE=4t@Z%5OTS+^r6`$IGSlC{&jm&e_51U9~(Anx)yAgL6bTRG;1@1*-AI z{UJNuAYiMtT1k?TW|TnrTm1KXXGJwKOhy_*Re`Hh(}=F2kMh)#kw#F=$?FlQS~31s z&=^Ua1%f(S6{uPQ< z{tp28t~4elXzheLfz6?U&mPlGs0T*vggSxEf$vF6a3RnjH&ZQX@=ho@_;xJ}JZ!3+ z(1(|*Y?I4F;H)+R7c|TKhfOK*O`3*G(F6r8Y4ZAYzPeR3ORbUGCgQIroJQ%K{gf|M zYbTUsHsj+g{oSu#)Q-Ouw4}+CV4OyQ?s#2LXGUR~CEbLQ*vZhlw$@IlPfX!&^0L8M zZ3GV0a`HNm7SE4uj>pg&sB;kEGL>$^0slpX%gOuD1meJcl0`yQpQ%>p@k2%xsO;s{ z{^>W+%!kQ5HvXQ#IiPCA_*>Xi>(_?__rM;DW(m_oGf?jJOeskdbIzR#Rdrj2YZEnT zZdj_1uaHArt(YoYp~p#c!=}j44O~*a>n2y22pvzQljdgLoPJYbQif@$K|m^(>7C{h z&dn}xQBCJOHPSYhhDOeu`$ihEa^K)6pC0WSHGB3_h!ckP${e#8b^xL=FnDu#TC^HFYI`o3gaes-E7tIcJ9oDXqF1+s(Muu0vaSF@G#ZA zeGk>L>Rdmp3TMl}5p1Gc(CQqo70Asj!4ks11+C7pE1CmPn&>@k>Ib->)j5uW!e`@= zV^cptD{9%vdJZJ^b-&uw&(PAt>P$S4TB4BIanM&|Q{iN^qm(;miUt?3`?W%&>?$LG z%)anB&yP(?MJ?M}08Lxts(w*Ug_HIXLnG-UbMS6}&lP6V*ULekheA3KXFjUMONrP( zizsueR;OA`uI4P;_ED!@y%VuG^k>$-Va zj!Q*#4}WH;r3nHWE-ZqF!r-M^F+)AnDJ5yz(z3ovvaPOGOi-e#Oh9Zsu!5JG8i4%h z`+T%I$7^-`SEEZPu16Q-1!#S(3F2``tOlM6732~e|06gs}b%VpL zqDSJMeo^((7pMjalj@xexxV%zQoK6Hwx3MEW`Gt;0*7k0sqsaqSxH^Y%jL*PCM8OV ztxw-3%u9{`iA@Q3rj!Ji)1NWrkbJd zb00K9_Ko1Qm60S}X)b7HFifEgO zN1c;XLA+cJ^<>ATl!iJ@l~ucY!q=OjX#QW`ms8US7{J15J0N@?Wq5kqb2N3+AGEc2N@yL0UM;pMV(h;*<> zXqk_GQ{6vtIQ!}lkRB$>Rlc{>!*Sko1>xuiw4f&Byc{19{j~MrZE8vl-fYSBcD*TJ zOH&RfZxsb)(as5{5k4DoW+Ih75JQc`QA z6iQWAom1JsfVy*h2OBS!os%tjV!JhRa1cnEoZmvN)~6_5oug$w>B41dDX{DuLS8hg zPqO{Y5@g^-E5AiGdf4$5n{&l%S}yZXwaj-mFrYFQY#!`-I8<5Yhk%E=_j6KFJry+5 zOW%0EMKWr-I-PJ1G;!f1B30*b?#fUt(PpYiIRaE8C+P-xx$K;z9HEp(4yk9%0IdSv zP_^R`XQxNbH*(Z)o ztTAoXS{C<=PNH6|TR7RXWK*`ODJ9cPE)R29CS<0XG#o%RURiPtmCVbPAfB^L zO(_W?=jkMfbB3(Zs#|5q;@K4@LE@`|yj*ES^g;SnJ;D-D6#%;AaCxPj3=62nAFhJk z%vjyPU!ua#nzpdKlps=Iw0h=n*&L_2qE{tDK$n7;Ffgt?lab6tz`R@vVyz^dDvF7; zlxePCo-3RiJ1J#Be1sY5fEikb!?~(R2yLrA=c=+ul;Lo$DpuYyKPcp7zt(clX{kum zrjbAl!*b-5;qXQzP}w)2OF=BdLF%;^FSxK!(?y^=!xaW5;S^Z_G?ySZfW=?dWae-J zvVe~AEY(xtrQz5DGzTr98m~E?#yPSjn`&X^GpV>SQei#K6;4zY1k5I9M&ad>P0!4S zNdqMgdn(OM??ZJ=R4erprOc*mXfgd1Xna?KNV+Gp3B@g{zVw_EC@VH`)+#W{9I78$${)pU5Wpe9Z>!1{7txktPzRe6uo_0%kjw>>hV{)b*GU6Plc0O zkwbr~Ff*=QZ@z_Ag|#k%bNlUychIC(Wc4V+fs^$Ms!6Q~RF-b`_q?TABB2Iuci?cWLqR>MKI{x1cq0w8cOov9($Yl%qRttDL+f65AUo6RpnSv`L_v4zkW4F9Xq2 zQ7txU61?Rgv%(NWzXdHe*%izJ_6rUZyzL5m#=#otiwc7bRHU}Kv?{p&O@)bu4OD{5 z)bxvfB@J|-QZQ_6d?AS3-50173>zEYPz{^7+HEw9-41O+>50>`oYJ)xZ{mDllPF zVSML-O2M$jpf3IdEs@Y1am#4;d-30Lp_cq+_xsiF3mv!Cb7#S zGjx7^Dyk(CnqG2D*intY;`moVOC;>Qz>TkFe}Wd9T%O$vjrtEzG_KpKnJE?iLL(AB zRZz3ZtEGu(wUtS5s7ek9_#7`kLW@ndQ8@d*=p2q%g{s)f4!{@UUz1vr{Ehl?Q`|Su zVv{{JIQyl|r^ZGkNIT~W+n>ymOU(WREjD?4vm5Zmc;(br9dXu)YkTO*_kj(>0$Ml7Q7Mr}xz%Tg)n@F=0s_M+#*)|dFwicVTQNhXaFXsNF z6bV(uev#zx8)>TfurGZD`i;5b9#Xf}a}R=w)x}d|!(pNY0u`HZu7APdd$Gy$VJ^D( zf@;l&k;zd#rY2tu^_mYmzc^VLzZrB%)`Pc4(uW5BV&o8vZ8mv6j2r(8@#jcppyCZ) z@h{rS;Xy+kK#A{MU-{6lT=*WSIuqadcsU_U{JF_IP_xOgCLf{2Chbmar{uqBYq80* zJ6zkpZ!5g^OE$pqw@|Iv5O&7|CC26T2vn_@q47$4M|{gwHDnT~q;rPG z$%~I)R1>6xUw*utpmhW!3FV0W99=@3pIR|POPcJn+4h27C4nxbiTvUz<$g%clV5Ag zzrx|#r}N#o}fmXyP-9Ns~-P9I;ZQ_b-K}(u!RN19=TlZUh1ubcE1Bsh61MFNJWCN`& zKF-?u&(V7t^mB!iu7UK3>IdBZLvne!l%|UK^qt2foYF!I=&qYm;fnaYdGeFA>bK+| zbYor*{H3HxyMwIhG&i7tS}{XQH+crb>dK0G?$sIC|zV=f6GZ>;fS` zdsj^Xd(b755(K1%2wbp8>|JH4aBVCmX1?MPnWcx~_GBmraXjc8gh+BNOUJLcU!f6y z=b~fTpe`njrdlyRQdA@UcgL+%c%K7@L_W~klg$1Pfi**N@$G96PgL=&O43O^IR1?C zm-c65iQenCs79IIZJN2_aA#=(5423PcTSnWhfPbSXTU4V=@1CNu zY>>hb!oLNL_}^`sNjRmElN^Kt9B7&5yG?U0ab?=JV^~2;niL1aRN6y*$}?2Zk|vvG zf-c;zOVi9kG8{H<$Z6!ZN+XL;p~}TC8tTcE#!Yp*77EydE|<98?snsW95Ttvl``eh zf>c<#Y|B+;sBE6-rozNGNSFAyI8ghxh461dqfGB&D_NryiGVTj1mlG+Xi1Z*4pjal zOwLj_m1&L(1Yezp`qDJBM=M$o(5TLZdc0ifri#At0bkOpNBozjnM^gIYSYY>N16~g z@1|HBHkE1SF#q^F$-3OHOVdos-=eC1AX$lJcxjqRe;B9~5^1hvxv=y*eUS>6X?9cx z3C<-QK-G%Tn1Yrx*)(6QeSxYKGqj}1rkUYn4ohFm98M-+<|?ug+@xbRsnu_w3A7>9 zY5biyoZToDu!njwDM3}`FWKZt=EH$@eefB%b9}Pqz@<5=a55jx&;%$y6u(Gbt`C0y zd^DYtREQh_OMzAA5I&p=d+&;4SLz%u<;AG9HJOx{BC2!PG?Bf2Xg>Z1nxURlh`HjE z@2!S9IT5SE>Ky#pQj_FR5WUxLDqJC|Nu15yTH`CsY1NAHg@R@pl2nM~<k{B+Z;TobaO;I2=wUC8%nsb1#$XE@J*IXi1Y*19^K~ zVI8v&Hqbg^=|wAv#H6NJ<}9U&nB5RiKcKI^sBrT8LqO$mA6c4~R=x5g#$1xpO8{O< z#71M&*0So!kI2S~sV=ShqpUhtu8c3^ThKi0v9#)B2#Fwi!M(+#y}m+@MTyu{;j-$< zkBIZqLw&j6M&X94r0+m0EQm|1{wS-S{D^oc%%-JPC%H(d+Nx*OO6sZQP%o>V{D@5N zSz2{YHK(l_2xJ4(@{X$mcJuL2CHI8| z$5tJmtpsZbLVgNb(j++`k(dp~lpoPhwm4kjnHRmHCxZftFQIenhgQyTYQ8&jnN)}B%Boj>L{j#t zADC1dy0q$K_|pIfszE|RbWPk+)A5uFSK@@^N8}1)DbuGIrf(Fqq{&vDIjTisY1N6d zi}-7vb>Q4dplZcb;X3Y;{D{mJ%_fbZxx(cBce7-V4@~*o*_xxyQ1S~IY6DIRYYU=w zvED#4M@%Y2CSQSSZZfqsw+fUldtBs5;pI}ADjgCzg~peeELoYV>T`uF9a2&uKD@<_ z3wEiS>ZA;3?M2laKtM+~y`fstWCKpZW@`xz`Wc!ehZL9Ka0bS0m4bT%E$wg9jH6ao z-PuxRXl@l?<8*Z9f!vjbYD~U?mPWJ#9D8gTwwHTgGw5p7oa6(T&LKlsT2*BS3m+Q$EFI$D@`fYjrqIV zYV$WkJ=B3}kf7KHb9lL|aJD)lQ2Pz63fsjns7_BGdTPDu7EU+Jp=)&ViR{+kMD&&deW?%9Y+W5@T>}N9x@f({}$A1YoO*$?&{hj z*@u3;`u`a_vjodg9Exrwme7?k=KeR;-dHLU8MHR>4_&2s+wdfFu9LpOUPf5FL zmI$=Z>p%;`R~*m@n8$0zXc6dQj-k5SvhJjC#*u%3VfV87nSqh zP$lI>!$gTHQRUL_GerL#D5aDPl_nzl#y*-5{#(!*CfOcb_a=kD2>%F_%B7}iSwq^a5+OkFO~%HL4^2qWeg1*LB`xQWYjLscE*T*$`caD9fM zo=lQi=EF2pztUjp5*ca{&W(cN4k7$EP?GclRV&H7-+>k*%FE^+Gf%Op=|`wyx0tFO zDN1}k%i;gHyDv~Jmp@LT5Uuk_T^OX>2ee>d+0A4+zu^xNa~9pbX{6)O_(a;aQ6g)4!l%A&!%4CEQRQWuA_I zM$=0AlWL(UzJnH3OGHXpY(PsQy7Ji@C4!zAkqoso*nSCxQ=Ykr+Y}3`_urTMFw$i+ zB4?cfwcN%Y)?f!Se+A0!qes{l55){L*muyPYTKW^u#I{BsL63F$xz)GVS>_ba18i& z|Ga5%2~+NKoG*U3gvf%78S)2B8md~PUBj0f?7bCxO_kz+1(hsgJLg#< zj>B2%t26b-oozeNa8pb)F0tHzmhGSVXe4;-K*LQrFU!Rk&n!V&X!`2-6z4Q0rfxj49bkVet8?r+++~lHZKov(^+M7iOL!`m>P^d2SEMQQt1vNM2{^f;&+Jw*4_J6xQ=+GsErmjaJ)W}5C*OX)z@Ff*V!tL0%^q5PXA4V@k`9ZK0SgDBknLnKMEQpnGz*L zmel|u{I{SrIkulU&$F@AD`x6!g1Xt!#QY;vD`rY`W4^$i%m&qDq>#WVKHw1Fvn}zF zj1;b}6d!z(&)^oGex$+4NCBz_a|&Q%gp-j1RHVrK*H=z7Yd?p3z7>lGs+C4+lz!eo zb3qrUm^3ydd|p$XEXwPiO@5pEe9P8C^i7Edyq=^7_CM#FY}NQHXK^{!YObLRNO=`aDIDfZ?QxU zc9OgM#Ap&CucX{*^aJS0u=(%B3XX)ESoZ+~*`OAWYz<_O5Qum0gm;2kBIV(vgS zHXM)9`n#j*^#xSiMA+cD!PIPWUx{r^8h`H!I?j*650On=u`6hd)awRQy``vXGRdu0 z18$&|-I_{Dlv-A|@1T)Qz6y`KM!nr}2Msq-8tHhETP$xPKOQEMPsB~!9wul^s2i%} z>;^g+7iUlnSddw-<3^)ECpVFDw6R{t{WyWnVI^&E!!jjBFHj}F5W92?bZN0HWm3mo z(u?2XCiK-c`_Gqny(UNJKB$c@pN<#AVv~MRt;w;&&3)x_ut}~x(GN5SJ9*1e#Rofi zcv^l1t;unAD=FHOv4BcoEe+1ynY?A5_j&bYfT^EyJfjRjO^)413X{#R@Pd1BKnhw* z-QihEF3fQqB@X_jTu>iy=Pl2}-y7H04bBk|>LzF&s5G7zPV%DurIxyrMY%85BYd_N z3tHS{hnp=)57XHmFKBU-9d7Panr)}hgL*MXD^PAypPk_?%>&tbb0z*ey5qkJTHIuZ zyWEg3^;#b(Xf1U++~ZQ2<5g-IoahJ2*�y%WZ19oTfxHyTRpfr)W|tcSH4(o66zN zz8;s2dhFD6(M^NP;pQ0M{C8X~_f-?{0$SYU*f~{mW;6N5WXTuM;wJABbJpKu=WXwa ztpC7Z~BDyZgx%Q&Ua2xQLhtyIHJRY~c8 z@*oh%>cs*rhdY&&xKUFAX04~Ner?r*)1z?3cjO-88b zEzsg7vCv3SH6un}FVNy9X-1$DW>7s1SQ=aoH=&=|wm+^=MHQZtSS@IAlf&+Kz8)s) zYkk%Wqa5y3QmRbD<R2iFwzw9DhAb1o*W|A)t9kSvnr77w5im z{3lSS+b35V4pT2yXk=3YrSIMx2YRLHu&s)!xrxy`hyYbDR;uBq6iv#-rijKX*+liE zP?ZlzSvoNS&?|1@JbXbl4_x;qZu*gTH`|*mwmb>dEX-} z4~4>i8XQWV%zqX*&|GZFTO!4_*K9iv)r+OU6h<*s`_>%IxAd31ctN$eN$w+g;c`~i z8ZB-xg_2B_`VRBcM9t(~rAE@Z!Nl4Ns(D~1R?+JVh4k;fEH#scu zR>#SGPJ0=qDu;w|rFr=Doy0s;FO~-9I#u2hH&Ln3!zAPD1=Vm<${~@+?jC6&tk9H0 z;^dyW$>{_|1|2w2QT> zUMvkxkwf0nJg`sbVM>7fz^Yfg{-veHZ`n=c0i2qto|bB^a!44>TGdGK*#I7DO)L$r zSa`}IQRQm(5U6^wLZj(Y4hdIX>)$n6)a3M)Qw(`a9i(8aB;s;BF3^gFCzXn6mEs`# zRrHR(1&wSLt6F10#^m(pM{?i=-{qzG;rjBpA8b&!CypR(7i=_m=)va6y!^6{n ziT(K(B=^xOewz`w-fV5^@uZ+O2=J8kJ~va$5#!;72wH?I6i$zE5#QK%r>J~b3Hj{^%v8BPO8pT`c7JDr7D?HSU ztx#KQyd_3Vp&=fs7b~;Q!u|h2+cuSMRZpR!~ z9;z2B)KY@CG!NqA!*Y*yyT`t;CV~)kjkPwR4;tx$yUM&EpAdPN0NqF;w<1Y z_KCm~$TT;3kAa8k#X>a^c;3=HB-}XyqZ6}2i<@i^5K}QXT^R(Un5U+M-@U@m%?lA?aJIKz|(JWz2HI>ch_tn&(5++^L)BC?e5j`=c7iNF&?);#dj z!*msa=bhpvncfs7)vC`&G(~A}BJjK=*_50FqSjZkiHsLd4k=vo(?oVPOx!moddFW= zCF7-_;wIv^8m82PnqMerxamJ@b;7e6rqqL4pozd!#!uWtwR&;WlKUB||9L+LsJMxw z3w`C^j`CjxjiyW0D9(vV=Xe)O-zaFf=|6k)Kfauo9fK47Kofzl!yA-BopO+e>cuil ziNN!gRyCOxQdgw^sHw-_q8i!spFMg)Ym-)vjOqh{CIZh}<|dMAk5_qk$xZAvNreAr zkDfi$JX9|x*`iw9;q8=ve>jjz!JS$D}K$Ub4llAoqjciJpD`I;dCav6wENChO~!YH^bz@WkT$y)!pwm=b|!t4Z@fB9Mp4`g)=I8QGLF>;%+2Owt2u zUlW0cs$>(PG7po6VudCG&kmTliTh+dOxD*+gA;)VD%n)R*;~gis1`SAY~Bc9d6=xP z7pjTCbGM1O=`U#?$D2GlIquBty*3Y%_4NuZZqiD7BT{5; zvc6uRiNIGLISz-1N%CSMi~WC!o9wGo^xwl|eZ5jG*(62tMqO(UllAoiO#~jzsCnRO zY7dk3^$IQ7BoAd2W%Mwq>1$sJyyUGpHb5i7t*_5iNi#E)lV$UtiIHfSQeA9?hMTy% z(ojtaTP#`=D>U5nM^WrIq6QkK<)E4c3>j)^upREdf5lk2FnbaWOR%Or52^M?g@M^u z0rEFg6M=`od>?~HJjBB*O~(aD)!-?cu!y97*a4q&C%U1U2t04iu>oqI&bQvafQFl# zzKiW8hj;9|3v~P~s^KPbLg#^4c=V2U+m{ZKdOKwU8 zp0~_RM2!z3JiO$lMBvc_<|Z6SL9MTs24jOtB61Vz@y|E`YCGS%*EpZe3#U3W>>!rcTMh7Zx;>@|Z$@+SM{`IcU zkE_-o!X>8E!~Bg{OBfxfxGBXjd3ec938V9txC!C!2498Ic|BotYOfvb!tp#?5HA`` zc{WcD8JB{RFLeB*TFlktyqCkx8EQj4uig|AT@Mopnra&aJUI>q3Xs2nmc#AZ?Bf8` z{7Nn`5xAgP>fCU9{QD>?E%tv`O27-KYt=x&lS6Gqy?XvzRHHb2niHp8T9wqW(?+q8c;ACu;~Oh@FXxOcqBfkV|MmlMJSPJ1dA{x08|u!uZ4stR0=aH(d3 z1;?ieo=B?#y^{WPH4WDLoSjnJN%^}ne%>pf{VoR?sb(kC-rd^Q(y#BO(6T75h^S%yJl6 zb9@-tB!TfS#qnQ7HSF(dVAunazGUNG%_}GU(qJnNhECk%y))4d)f{7jfY_hRCHM8x zr=z4-sA^dMV-3y0!GE3$VWnE()(=a6qUe$mAM(~-Kx>#}-4R;1Fm=+!3N6RXb-75} z(YTVye8v83gr=|Jc|x{gKcH7q;-j`RKV~ke{UjFx&90XpE;&ATQ8#NasI#Pvd zexaZVqgN%;>|NQ<677Q4OH1vGGU%>Hsi1TJWdA8JL-f5#wpgBNw>VJdZ%+hDNt zJWPwT5@?*2PdO`Z6i%4jM5N3tb~Gsst}VXYXf(wC@gh+5Vs@sW#Z9vA-tg5uOpB&- zgGE&4Q=iXZNlw8a}in3LcZ&E{dw#CUyK zA95R$Cr8{YaH!T6AD70>fB(Vof` zq*OtRo8-v7jZ10{YGf0r7n6LT#8W*?S}s7L4L;4V z8~jzOnc`C#MO&JT#1%JDRo#@>@sqk>>V^N!{}OIOVCbJ+LjkCIp?`B zA|snd*>(w-FKzL?aZ=zkn*x@AA;&($Bx`D1l_f^Rzz=Nv(tmT(FtW*~{@#d+&mQu^ ziGHAH7k5iD0#!+ge<}V;HHU1-5z;*Hy-ACQm)ulad|xuXIh!xd1@uZbQ7k^gq%A(q z=G$vt3r=}n%acsOsmcs?N`QKuVX8QyFOcVez0AcQYo8a;$fgvWA{^>rSFcxSZSj%i zKmVN&sC%?Hq4}5MCT){(tltK~T5u}R;wFV4-|#^thnK5F(w^GlOTj62M-rYUE3{;j1C<=G5A>3oYK!kn{wuXx z*G#2*LA}Ea)k|)wm}v@5aY|k+u@;;XH;uyh5(p_cMTk&?y|mbUt%6fOSej}uwZM;` zJX9~{zZEpHDFvr+xMjkv1*hELa=24)iujb~mBSVPwmDQQ`^Lv(xW`Op`_EFJv7psp zrDoKjb2#$K(Bm=+D~{BbVw61Wa$D5wP%YJ*+EPS{q?)}?_yQVXn%YtyNo1$2lt9Pd zP(_t$Rj0Pp$6bLqPfn?3*FfSjGR5(^OXb8@MK!|IQ8A#(^Z|Os{`f-SVX+WL-4&|( zx1Zy`LbX(LYD*CpF*iv{=_3V=p~qQ;`R~LrJg;&LUqFkS9Ax_Rb|MuFBy}b>RLg62 zITlWi%i;%m$^MlXORk3+?5Hr%%k^4bvr}%k7R(U>GuztN@|wS`g=vaMSj+DPG+r|$ zDAi!%Tzd8VH^Wq3GgS!%jaE-7srhe#me*`od0a+jCYK%%^@7H0_QnQKdk{kSZ$XRw z6VwDfBVMBzSKtV#ap0|l)HTfgRlt{=|Z2((bG5te3rV{Xidm->~Hs~#rL2vCjd z52qb3sFIFR&?y?Y?@E3P(5v;z8M1cVmyZW^vK)Y&B-1>_L2j2E1mRkOO*|hRNRD(JA zWT+X3M9*g^L=Cn7N;UT#sH<5M0rC5`n^xLsFhQwM_0n|U^A1Wt%}{AZb{o8O7i_2! z&k9uRPXh7D9?cgD8mk$HbG|{^<_^>qYS>KF`xFe<&ybtHLKTD94VJM)EZkqYgBCa0 zesNM+cc8^h)~{^J>_Ed!t{=mGj;#8%#~$I)RrNJho+xoE zc3!XrOR!lf(Xt z`)c3%zf=plgJ!)tFBPgXxfWzot$FoUFUOuX`bwU)8!Tgqy{oe)7wQ>dLcxJb`V*A4 z`U&XxRnV;06r3Vhu>-C3>gAGcuQN@IAK4NVnM#B0TPLyL7FrFqZ_PcaT7L_+s8)l$ zT-Y&tmQ9@BPlG)poD|p?COkh+j(uy+^Jt!K8jKHSsH{b@|ITK6zL35`G*ESrLpfUY z!OUL;t-d-I&Pkn(26IV8sA@*or`wQ-#JU63u#%##uiP~_eokstQA2z7m1D~D%lbz8 zT4D6msv>?hM-1qx=>?6S^Vh!m`-ekSsY11kF!hS3K=|=lL-sf%OnImoTcG8ur{ENO z9CLDjo(3!pE?=DscjlMLt)4%B{+>;~K#|)X5&dF0n>#eH{wvwXM~j=($~P{Cxt54& zPh4M@b|cfsNe?L{rC|y*u{9ri0;&dJU!3Tx!TgK+%5TrZowG8j^16LGew%SzQ;dh_ z$qCd>C~wWDBhx4^oHT73jIBO7JtiNSM(1=L&kY-_$8TPDT!P;c4P>O`d#6QTP)`m} zbqfQ2%6J~0jIV+^my5U5E%IXZGc7&ME4H1(==|2?&UZ&$7vrlf7Zy^5hhYDSRZlp^8A5g9B9E zA~F0#OF&d}sCwl9)r^pk=y^S_+(2_u1`ExT+l<4hC({Z&xQ zVW8rd7INbiB+%^d|@!?W!? zyquhDj#E!g(i)@I!?b91H#k}ys3wO~`W}E~b3D)zYYr}uS7Y{FyfB9;u zk9z{uEvKM!Ri7K+hU$l@R>3IKsp-ZReqSu{1bwf8O%s{D?bvcr`g3c1mCEDsv9n!*1Vy zp&F-=ER^{^$t>pKwcwQdnu1fKoc8=O$CR~Rm&DwRaISm+s(E<#6jPF0EVeW_+338b zrA{iBsY*&sWK=V^i)WZLBjaKivxHUsN|jRA$3v)U9&Rtw_An(IogG1O69;@HU|hy> zZE&u904i?c)Nj6h$xWQ?@$6fxV-cMIqFELUamoyn_tn`}H&v_pWtfuk_LrFD{AV1q z$sIfti>=U_9B&!CJGmODSZsyXQkN=!$xe_sxfs<}NmrPUMcA4gk{m&qDcFO~+ERwwg){&Uj6fT|ZO z)KO&K(maqYcLGctf6~{~l?JMnL#~P0->QD0n$uo?xovR%Gv`yyh*tG0G$z-7lG|@w z`QTx)s$Ze8hyQcVI)_Z>Y|<3&|O%BITJxpg!TU31s1yIT159&~*iU0mGv}#q2DD!-a+g&D|uOw z4U@AFsck1!KmRQarXGZ59|KxYSE&%K{0+3+eAlWX(N60HV^QmWp;~T!@)t=Va9^$J zS7_XP*Q$c*SzWwra7~VNKZ#489C>#Fr?2Jaa~0(LcdX0FSX_)D7F!ye>lt}VlS8)L z{0a{*C+9s%(gklww6oI14Ny~$ziDvJAyYb1i-hB+T15Zi_^*OSN#ZQb7df42K9L^K zHwqdhnd{9dkmY%`s-M_EyIc0?Id?LlqLse|O@J&Ft%#z_TH`{?z{anF*2=N&=O|#H zmy=U&zTHPcrm{#PYehR$lW50VnjFsGNpUz-_5xayW8F`%!jp5(UoNUKFH_O#lY<8!S<7zRO&3sYbph z6|y$C-2CJma3;-ty>#;#$_P{I{?FvdikSaqn99v}nJaSiE@GW zBgUbwr&x%yP^WQCyX&J7YgB=mZ&X|o{TtZ$RnVFoJ$?J~C37_8a&l7WsU^CTN+(&u?g zlfyX@DGsN!uMMW+M&8mq&&grS?W~FnlG@4?C+iJwm{3x&+b1*MkHXUpkso+ zKMI&B)L^R=C=BY?$S?Y3I)&^%cpJGJfc@h`A zUajg^s>My3%(q;R$oDSg@K14*lQqVO_E)ljgn0#kLlQl_lxwwgNj6la<^DxE3EStPv`^FKkQx5|# zXcWhXZOW8|q)Pe~H;wvG5<^ZyBj>>efvby&Zm5ouR>xEB`co?@ZF-Uo0+wtdJXBP* zNQlaLgfHFvkDOPBs=7s)7>}?F646bA%gxWhGLEdc7ZPwUpwa57R7P&M#F~#Ozkt@{ zs4Z`t-4i2nWKy8xuU;Z;ttQ7FJ?CRQOwxJ!KtbcIaQ*Q7chccKOj`6WpjqlEa>mAr zhv`zQQ-CY;D)mMhjDtpNYB+Tfg5=X|fYDLY_1l*=`-8Kw%} zr#>37Xb;n+R!1+T!E%);xZ`MucPG~dr)V09`g1aYN+R)4y;vHYl9{|EksF1~!%J?e z;C)J~{WUvN0Z{61p-LeF**PB$-jip3(yHodFZD8gU2lyW6tvW!s$Q&Ai<_*#xkb}W zk%?ZWz&89UV5CNw39X%LwNVs2ZD*LwCH%!^_Djt%G-ZZ$j zgvEr0&x;UzcKmb?qZ{WmV;IGV_vHgf{h$^63Q}lIw1Ka@|AOw&I_u=O;X@^>S8}s$R#)Bs5@`X4gyuAl!r2=CfW4067BeT z{4=N1oCxqKYjJIGMc`c^j)WMST$Xw(v?B11odcCqiNL&+O}PV#ws1lJaRST(Ao>Cq)#4`YumM##hNfJ}rYaD}EX`Jq z!u6WhwLqL$vWXxQIL5|oIr9LD<+==hrkmumJIQu6%7lU)2Zd!Y{$G(MfTKe=c^ z27v(iThORx*MftpBpg&PxhWS-{ACyC_&Ax;S_wS7KpdwcWCoC4d^tIlE%zmddmQ1OeFb{C)XU-i zlC}UUClKi6+y&y;l99~+%MO@8XR4J0?_mWhlLzP}H`V623&agO z&x|d7E!t^tZH~J@+$hrTVUoUn0gc_{0&(QgMyyF+zkt?K7bzr@b~Y)!bIDC9V8by< zEp<}f=6d1bY2~`Fqd=U@1{a89kj^}$=9Y_81>zteZXz33!{j{{fs1MshrKasLtE#p z1>&Sq*ax&gaDg~-kT+x#`+!zg-%{W_lY7T$(kpJFbX-AaTY$=10(vEz*jETtQU$NU zW=N{W&2h>wrS=UM^2%44`t1fL?MFvmdCqsglpE2i6AX0ufFy&w0R+w0HF_Gw200vdLxS z#)SmtCe82*Xk?Si$gxW&MxZHIvWa?f>8pMLl^mpE^(8k^U)Zuq%LOTM)--Bv%ck1l z#veW2U@I)5L%kL_i>`LKT}JLdTxB=K0rH6r6e%F}@-3GNsxm`FD}M`G+$0vFZoTy@ z0q?-ZuYwjg$+za%i9|AcLYK0sV&UKNt$`}q&q?DhOfl3=zs^U98dsruSK4s`)M1k7mGPA7>u2?wN0I08yMj-XB z>?Ug3r@`{A$E_vOoZe1-LA7L)d~2XmdQiROriz98Km*6VWZrRM=p{F?t87M;U&Q%( zN8qWftEL`*Gp`j3x0emn5qL68E}j zNwSP1ZnC{8FLTLF6$|&p6hN(-f26NPH&iPY?xRIOWe^CEzXdIBl1)kFRv90EF&F|H zzY1F1B;T65m>h$l#LWeC)O!(2Q0e4&i{pIeVakJCLc>ku+!(6J3$=Q#xCx7{s7f{= z8e}(_B}LnPerg1bj&^ZqrU6f}C^opA} z%vexqI<(aUaGr5~dF^W@pSkz|XCrNLkvSyL@i)U%XUtq6Zk%@WFvF5HT8(b;nq-Y=iN}`3vl?0PZZmN`Wl3)#$SOIz^n@9%D zNJ}I)_NVeTIMGC)|dnO3g5frrb<2|aYcP~ z7V=**JVJ5&N`pz5kY;j?K^`gY|1azWjcjuCgqyPJdsniFozwJHW(zeArORpXrEIEL zxVKX{2#WEZjfn-A$_f8r@_?7H#f<*X6H7-R3CW(E!iadnPbNhrqb6dv|{0|1vgGC z&)NLzo10%ii<>kf0EgRwbya3>F?uSIwA@c0+Wrty2OYM}BY1<2omikk*> zu4*FH)8rWsPrWXvxM{pK=Yf6DDKN&v*RqL!aV&iNp7X%T_?eeI9=?`M<6p#0(1!F1g9E@bQ+oi3|_-Rr*>?k$H729H@M2YS7H!-gr2B@d8@h zBrAY|1XKDC=p{Ef7Czn*H?iAx49<9X$xV)h^Ok&TDjrOcJRV+h6ZgA%eaW}}!vLG= zMJ#-Lw75z7c$l0XVd?92m>dh|Gtxdlr;-{EFS*IF@bQ+oiL}iV4~b^WCda}DRI&-T z`S{9sc*#wUg^#z)O^QbH@FEsI{-tD-d}|Vo&Yb(I!OjaGpOI|BzB~qJJiO#4=Y@~A z%uNIae(8*dm)zu7IB&@a{xhVhpck?5@p^HSV&S7qwW&&9tG8Knj)jlUNH&o_8LF4E z$+2*t@~tVVF_+qSc*#wUg^#zyO@zWtRr-2uuw&r^DsG}4h5IUf{Q_E=PQEqmohBFV zzV!71<=?zsk-o>jQw3zI+5x?iO)1qj-V!(YiqY|K_TmNAXgUP9s4Bl`K(Dxo%-b|r zzV)9!+K2}#eZ5k3EPT8**Ei6)bjQOhO$WynRdbV07!T+bH>Fe?Z^^f&SjwE@@$ib9 zNCKQj;CM^iG(rUG+xf5ApPafhSiUu%o0j4D-j!@ZF%?v@i39!;;a8>F_^4yyyd@6>=yZ(6!z)ck21$lV z+JdCb+4cdw*EPT8rZsIie(SY&r zr1LVuj)jl6<~&dae#*h|@RFMx3mDJKpSsKHgVS2!z6vZQgtjGsC;W`1zGw#9ry*bxJkY>(5a=z_b$1~ zvGDPhxQWCC50muu3#zfg34tH~{)aPh2Y2v2>FX8hSonC$+~i{s0_1Nd$9drcDsG|* zhm>TBuuXJ9OE$@ArKHmIAo!m2wde-wSonBL+=OX<8dm{ZHaRbRKqZ?vlj;$cz81Ks zmTZ!5Jv6gNSo(T_rrsKgS-v&UImP4Qm267AweglT9ruK4gt5Lv@A&Hm<49VpNrFYUyF7c>{$4KN;Z8epgkU5a+71>yd~e7 zieh#LkyD~~9wx`a2h`k@qDueb_^&kBvG4&EH<1P=>HkOiTHh#Wag%&&jy6oYh3`pU zuTaOr$6Jz3oOe6*P{3}m^TG#Ivgwom{k}XNUUHLT;o~iHlTJvChnL*sSU7LVw}#Sm z$Hv1;ZgMPqyk%}u&A{>SQZ_jjKHf4nDTQS`yyPaw!g))+HJx@aP$r*;IP>aQ_<)L= zxIe@rEPX9(K}$Btw`SLG3dixiOWEYS@bQ*p6DM^{Rr-3R>R32X`PR(RTtwsHrEGFu z_;_p119Lgm#dvthP0kA+Z;6{YUgVfbpuhb1N0r}Rj z)pU5r_b$1~wb930;wF+PJi^k~BAa=wSh(w>!M8R;TUM_aNh<)F1n?E%ArkgL5rK@TMrA)+$4Q1vIQ+}l5Y*vq2+h! z>le`CrpZ@aJf-+BvnPGMLMs;T%4aBA*|!4ZZyH>&a92JX7mAsiq^|`oXvrq|){E$mO9>~RjnBvo0eRRh{aKB4|{~;YX(95Ond(0pp z1rBs-n(^>t@`WlXtos2M`S1!^!Nr-Nn6gWnOR=s+dzeTks#|}4XC6)!3 z4mWX+G}sO|y|7q2tB_E2E(hI`0>_k*7o3LbS3yg0NP)A}HoY5y)@My?XeytLx2FAy z6*L{*@$hPdsdnbR5>h-`1=R7T)HItdE~;6tu118JmG4~!w230rTjF8Tz>Wsc;7k3A z)GX*^SIjp1IWCI2j4-!a2P)A3)LQ*Rn)3y;hDly7YGb-6GzuOH>Vx{w%lrguW+qP?K%H0wb?!&H%^k4sHQj3*7YrlVrBR^oD>Wmuw|P*(%v z>jN#?ss( zTJu^#URUp8uBX!D+wu{GO@mA45M@$>i~TR%K@J#ZnCuSvFa%W3u6L-GJ4k>^RF#=K zpjV0mE2OAS>xw-YOGNFktE)9kwTUXTWn9{0GlUXaM*aRsgUhFL9W5Lb@8|ensXkE9 zNPmtv9{-L9;1)xfm9{lG93D`$``$6gSEvEXHM+ zv~<~~yxh)AnXB>EY#T0@&CAcrOd~WzQS~tCDBdVNb*0s*Vil+YpE!3m^p>2X^tJXR z)k^xRbBcrNY|1)Jy=>K@diHd*;g*8OnXXEIo#svCR{Np zr5A{P*^4JiUr?=T!rap$5g>mZb|B5hdrk6Cc+F?b0@1I6*5pLJAUl3vg(VcyT%qM6 zDKU?il;scf-1JaooIJ16Id4?fos1<~`CHJM9Jxs2{#O~vpHf5u7qob8a^D-!yl{4r z>R(jBgKmX|Zg#i}8smplr`am35I6YjA{Dd*j9jEQat;pepefQ}YhPU)db}kTBD28r zDjoI$Dz!bJlGdYc&hM+^p?Wc~X>g?radvP1GwA`IY=tyes-@{tmTJ@-5mkjWUqDMX z*&AZ_U(U*>LYgn2#Z5{V;?`Nmn+O#Pbo@lQhU!;A!%f;v zWYMX>#rWP8Hxc!=j!0Q5j`4{R6;csV)Zp(=K03bZ-_pXI6w|POoxQ7qhMNeU&u_El z#E46+s)B}_T&wDhZEa1?Qmd+-spy4Lh zs(NDw+AN`v<_oIfCWWGjvtUDM*e4YsYjOzUdLHb)u_G^8V~BpF!IduLIwNl*GuBiu zxv6|Q*Qx^Q6q==0Rj5*hTq4)Cs_5%^sj0bd)z?ZFN^&XLX9rI*V+v^sTvUsjy#2^d zY@k=N>8sp9*Q#PW-&Vp>t1470U5K5H*(xrQGS%qo;~xuJ+~n;?HaP;F#?;!^N*7{} zK~%-`43qWs{I^goPcmhx&{n1zeSL1QkIoJP;y&W7fnIV`r3c!IFN*795 zDmKFmwZ2}VC7Tqzd}9~O%gOqBg=z@ttD=|i>D(tD4==f?qL(R4g)QwxcaC0Waw=UY zWvR%VIBA;MTK*KYxJl8=H$;b}zxDOfS0A0FTk>DI|JBX`yF#HjeuZiUd3<*#RL}d` zffuwioxR*j@B2E-i-MLgwQ4R|r#x4aHI#x=)^sj7^~RRP!MUS4uNZrR3mTS4Z7H@G zB*I-vN@N3NVEvZ8Ty97aBl`IH3uuPPRioYr_DjD~8%m(#Z&A%KDIJixV}IoLMf!Tq zsSUK0l`AxX2eT(@Y{C}XQAa?&ts}^Ja9^zwR;o2jcHan;y1|#y zpK3>8L6oRa(RfP&0q4qM&2oKdaHW-`d=ZuY-C(<1E3~-DBAj5Pm-?j$ z|0a zbaE$^`8C+V%wM5OKCGeh7Y)t@?|0A~ipj0gXseS%$`^|2S5Z|fokACce-$*z*lZ`x z7l?MAgqe{wOyk_q?{kL9isO^>E_wOiU!gkkEDe<*oSagUh>eVWKxIxMNK$K&YA$8?gC({NjCbqh6qX z9~G3svcHcQCLP8g1nF)sUnpp_x{~}yFwlqMeBqG35ooEa)F2`*=B6y_%KfXfO)3q| zPt$m*tEIY7QH>mSbs>U*w!)RatoGIjm%2(JA&^G{Ab*w@p<3$d$AL=Hhb4!X5MGTMI143PLi-Lc`dSH;DaKXN%b!JEnQEyk*ZFzl*pqC; zpYuXUUu)w&C4HzRV3s&9`anxvxtu6e9lr4$8R~37qpo~)B~YI+dz?e_v&U7w^i9Sl(6Y@?gLOddW={3`|`f&Q3{$bGwn6di+g;D;UT%JM%40 z07`^&mCYrzxGBLv<+ae)vjtUDi<|72aRS4GF*(Mh1Fc|S>hf^P#(lN7Ho*lg*<^jl zv5Zi?KrEXUpUxjGC7HTB9I5aKFTub-6AYv);^p?I>MvAXE zd?WSVVr>ZqhHA+sr81Ie>az`G(|BHfe`JJ9zosq^`M9R)&AX++b#_q22iR>;VO#oY zA8~~iH(3jlRp=33f`RU9r7|i*bmWrGU0kRxo@AiKP4*-S@_M~`^KNM{C7fk(q%IH1 zT;?Y0>l1YBf(y!T%>!vwbA)+#XrBp;70$nyoA@nmBK>BnD;^$Ae+9KE&0EqDq@>JV z@bE%5@h|2kd`ejyoJyF6o*m5>RFgu(Tarzj9G^>_hw8;LOgTHqTUyoJ$391xhw8-& zH8=5=bOfPg50l-?1)2m(+zib_GWmI^UaU}a6K`oAI9f2diHGXN3N<(Jmga%;0UlxN z>jj$VB}o$ECQbpEs`d2>EpF1;!8bDhJxmU1uF&EpW#0f*8raBqo|qL{+~f>RlKjmQ zOW<>^SJL+!s^Yii0jK%+N%@Jmmj_viHU7n#j^COGbfnqe(a@#AuA?^yn46qIhCQM+ zu|SELn1B;)-hH$OsCuzNi<_nafh6Dx``88IUUE}T zRPdJO0dLU5WPQC*^_?<_ekmQw7AK>HN$R}u)bcPNsJ|mEpFm+Bia6x)SH+UTC&N$ zH97c}b=KD_w7AK>HG5Z{9P8@^n#5S7nz)I*D|3_e^$IQ7WZ#lIquWZ#;i zQ647i>lIquWZ#-peh-uN^#aZ55g$KiCkTo4`zDNNeZ4}9o9tVYXKqHczFwilP4=zH z#}_vdjhvV>l%t7WIjPG-;71ZsXJ(A|Ql~&qK_#2m9}@eclZ^WPQP6Nx>hh4OFa1ht z;uSQpa1@=n$x$vIYE8^9glb~pyd{f+TctfrI_odm1r0Z)E)R;%!*mr3hf=sHX=CKz zi-*~t6}{tcs3sOZ?$w=dkt!XidNKd4py4LIBB*!F`QFj%`7b3*$ui5l+P9{wS~;p( z^#Yn$ID1{12XgQ|!b`f4xO>!s)A}Ml>jo=@hVQ8t^WW0f#KOJ9#-c;){Jx1nWPQCr z6AQ=o(L9iD@4i}JuTUQW0qS{BWtRDR|4D-r3kRxsAVXXu)~Mg#cG-voYnzHviC)#d z%zi{OHgGeeYJzkcBYm(b#+Ye_eW8UfJt#3PE;7W1hm~q z7Ioe_o{l3RXNy0SLv@rE{C&@}m_G^||3XP&V?yh1e&jEJ=`6|79v{_qNo^mo}D5@Y8S zkMCUy)70hRLiU4&VE-izYm($ox{|$SpqdAEkq-8Us{P@m!P#r(EzJWPW`Um8P*GK~ z)*v8mV&$HC_^QF#YsP>uH@UPT57mpM!KqWrTjnN?0sOv6Q|u3~(BdY?u9*?{)&B4q zNIUmUK-@&FW$~n`=|@3}n;g5QO0y@&{_sMz_L>zb8bRKC z+xmKi#?VtL)qqY}LoY5>bCn1p6fR-<;j|JSp13*fNg5b$X)>{Wj-OCn(!k6HrJ7Sn zh@vYprM1VR0geb~HzP~kT9^Y09^p&Zmx@9KRfDOiVyb5wHGSpysT*%C{BctZub{PF zt%VsoQ(dCcrc_aBXwAXEA_`Q!SXhGmDbItoF!5n&E|08!q`@iIzRb z$PK8K?g}jd;{Y^Ot~@!H`jw+YVMOa!uA$cmF9l%TSLzrU%BG0=>SMxO198O?EHCr0 zYZ|=~sMS~I$MUDBropO!$K-H9-0#cmKP{nUvBYPEmL<2}-Z%kb=n`5ERMySdFq820 z`cFIkD-BMXHBgCg3OC63@y*S`7Bm9p(_Svs7Yse?_dqMO{ApGCCGUz}ENRy6E1sXc zA+0oqNxt`hsu#1xMKuCO2L=apu6m%Ct}mrJ!V>d?V{*=%t3fJLn(9euuvO`oil7au zSL>DPNd?t3xM4E}MW^u>AxPPHpugbxtuR7sRgO^=jPfjYv z@|GK{v$jC3IVb%zxZ=Y)&;V7=&i}qSpqJ}4r-FFvkSaiR5%_>!j&Mrw@s=B`RDGax z0z6!4aQUwaMnF~RwF7z@>w@aD<1Mv~Biv?e2aT6u$`xopHT&FPf6(H4_DmOO#fPHSv{7u>8%O-C`JEIMzsQuWv)e5vU;N?cG4=6A9nm6tnro^Xy+7|5eZ!dSBLuR02MU(0rkw;o;OE;s$$}#=*>A1&tg|4I+}! zPYXO>a5R-8tafRt2GJryUqUlEDNOW6joaUsN0Np_hZ>xJ2{)xMQA)J|mFQTZQIaW4 z^p>Q;uO&6gRCC2B^)tjx$DO)Df*EHmnWHEKV^Qrau!e0RLhg(j)?hb@^AuGFXq1$)kJ>2tY0~?czj!}tiJ^< ziRk<$_QH-SVVJCR7pj%tB>Dujb>Yr{suwFXaS68A=RcE&bLwGQoCagkdG@V^$rw?C zznA0&yIQa8ss(C)vjVB9RxFJPQcI@8sfU3VH0$--)*T1M%>K(Js=JZ{yOf>O*l@+@L6xSQ zmtUyXCThwdamA=7XUQKn)l!lvheT?Ksh*`&sFo-BZBLRKWTtBMH%F?VkrHIn=$~UH zXia*E1N};Hfzn8Va>Uo~o_-Xx3Fv+HDZJ>;Dx{!l5%Z9pPW_L6Fiu*0p?)iooYZPYZFatt03>%(^m(|-y6{#QY(!PbXd#doYf=Jm{1 z1+5Xb4_K#ysM7Q=>4IiE|Kj*BL#f&15&p3g%08WVm?};Gq6-=)R0)@3 zpU#Ry2i1%(Xx1w?$;=m0zKmS)lco(6LqoIw`b&AIfIBBCA< zJE5cy91qh@|H?3x6RH}6W1nvBlSB1VN&cj8J#T4j*b|WmXFZ$X?~hQeaH~?}pc>UI zFTnUf%ahbWl>wdhEe*c(Bq_X<5wDsJjv8=B8u$>UwV>M zc1nY@C#l#L!{kJuWpaLEhWuC`!eTNjJhJ+c5iTY9VsK4!!zrGPH(*h^?qBVs?3EUE?svo!dxBna~m zPx8ao*EN)VOE)-Gqqww967CMF>y|kG<0=&7^ga*MU#tcVQ>sRhA$nSBA?^_-u|H57 zhJ^Wcpt=c>2HTT-kLC)w`Kzdgn^HB3Ys7Y_hMQ#FA;Ob4dPDV3xG7bm5bGOMDRbiy zw!i7iv=^GSa;O?rP%RhANN!NYeKS?7QYsbhK#QB~Z?f0511)ZHCNKLfa(R~CW?s2O z&J8vxcHpjU2??0LOkto}F39y~*+gPsL1oF}!RRY@4K8l-rYAP)230n{-C(<_6bjT7 z-%#Z^S)f|qf0M0x2Q6-r|B6uCX>cw{=Cs+IOisq1({(~T^GZ>FH(0JJ=C!#anE9)q z)nJk0u$4`y8|Zh9up}r)70xD4z7VS4#S+r5#~Jc?CuI8mdiCqS%gY2QzZr37~U*kF%4H>y_8d68xT0g5#;@xIoBjn0Vb% z!e?Blg|{5jeFbI9e-0DSDF%t6KMPY{x0K-b-S5lJs-?4d(VyQln=N%MR)eV;1<{Z~K7M)LoDoIU&PHw`Fe71+FG+Epv zS9KiYc(h>@$6xJmvif!dq6|CGZ(OEyWra=XP24@bXJ zu6W9(QCsWLg5mYzCV9DBQoSQgoqRHiBu`S9wBnAif_{Z1sHJX}5aYgcQ0CF7CEKyM zNy~)|gDq%rlh!u^afkgW1?&bZK1|A=kDIBB{+qu3EpAeLnDEuJ-9%Z0;wHt1M+9<1 z!2At2*;W2P!alDY>NmNsI+FRufeKsI?xTLVuhefU=+ty%@^AE&`b`C$+(ZigPJ_vY z*5oK}h6+Kth*+(xziBY`V4zbreUKUWEd9rBTA=g&aiBtOK+!vXhN{&C&ZFGNaaqJ{ zz=Dhj9|pInDn3m5wBz^-wy1`iICOoyNVL@+{|&TMvr9EGt@_G>wZy}d-xh2^wIx2Fnh|o8uGv3ST{yvJ(8yenz*vY@gE?2_2AlgB_Um~yRgMA$s#da^ zDBH_tmj*E{Wb4;gLc4 z+bkL^Uwzc%Js#dRn9RRG%}qK{aSyFwvOuB^!Ui{yg%zrLpA*JAeXU`V1v5&uiJg}w zXI>#{sy_EYPQu3Ikkt{WhKYJ>YWp448YUS()LZiu-$84b6qjJfY^$#|Ox_*fyza)z z;hGiqRdy5GUOv)s(_rrU3)I7O=Qen~VwVM~$>dbT#t5?$6R6(zp}3{FEnv7^!cYq& z4#lbM3pm^aGEfaGMWgid4qC$`Ywe9QE*lb&!t|l)VM@`5JE}EI-t#9utgqZbGfc!c z=8O1c8tiK*5d}B6tATAWBKAf>H6xrOd6p75bp=%iNtV;ky9Q^NbnIyy#ghZQAS3;; zr9;($7m6Nh#1^c%iTF@K#X>G~wE&BUFDI$lntq>OQ-1 zC~m8-HB3HZ#xaU#IXo_&GF8Q!II?wPUP{0a3n-|DiTjj~?=6GWBb-aCFbp*|997t0 ze*#2lu-@lr!Luzv8Qegfw9ladamUi+%qv|rRU1p34^X%7pfya>tmoj#j)39hP*L?T zsW$pTvqzZSj5OH8ghTiO_4}y$TEjHm78Xlt;SCWj@+=QmZGEkp=6hKace)Wd}FzmS^` zLba^$)V(8XdV>*38V*%;kl>0|!a}^L7B|@nC(HTx-U94-C6CoqZH2oy!7a3`@YK=c z*x|+qmlYn7PyX^oU&{(lc$V$a>n(XRVp-uz^W?CjiuK(0wT8*9q!!*rUqO0=ysD_CgT($jDD8TjA(PamUiztQ_(kJ;LUBsuk@(C59Mn$CJqn-WaAbrBz^=$w|ib zO@rY>H`rDH<$*UE{9S#O*}@*~%@&`ziM+T_os$XlCJijmnpc@<6hGK-%-Hh}RYj%Q zMc(ivDQj8KIU{2O`sl?nzAYuJUYJ)Uva?^U{nQm3ZmQ7oyNp_(X6FSPD5K;NmQhRU zwdLv^wEC)~CZI~4SdfWcQZTZpdR{-3H+l=ryxOH=pMJxq8yB6cuda^Cf#nVJlJwz% zdR}!2&f4Dem6DkSbziBi`U3U)$df}tMxYW%Bo=IFb(&kyX@!qlxnz(p#6y)sJRT+q zU!XU+(pq$+ffQ7Ib-Db7X0bmNHUpK7NVR;egcX|xmyM_jJ>zC}2MZQ#L94IwP{_HM zO<925U=kiZOmZKAdXr@V7uD*k!mZSaoi8lFrdo!cYjTn=vavfjjv~0hA_a6~(QyvD zpq|&eY&o+;S!G%5tyy<4zpa9J>R(Aj?4*!E(}zogcN&au;l65EIZ(6_G$M#rQ1ft(uHR9uzS@GpZISPN1Fij6 zGD40QscOEF2tYD!8Z3Pb)M4=(svkAN3R#Y#sd;0&^vwA{tw2Qj_NE#tHEW#xa#S!^EMcb@#G3v@^Nmj&ZR zIw}!wXu8VLqrk;6pg?z|e_1e&o{)nqOY>%Os2J(o*yabqh8Mo)vaodQ(G%tAC44B2=E)x1(Eabu}d z>(#>~SvC&XZ^)*yV7$`)qr&@!2(PRvACI9>;Ewb!3&w?TN8!O|1D*hX`l{WDasTDU zqALr=)p02VJioWjO-)XvM!7mJ&>iVt77X?J4=R*zo2&Aks@jGemQ4wCBUJTO7L04? z{`bSy$_s+Ok0K>1zsWUpM+LlRubFUGCdU>G**6O}b^W(6oocf6TSWs02!*QShf`hafOh=_w~@Z@jKj0kdDz&eLq!x-ZOSmflb!EIcx-Y1{`&|DyRUb(s-)FNDBMs*0J(^E z!)@TQr-Ewb`1ZuLy%DAqv@59ls{3E>q19JgFq{B+7HdQ0xUZ7i)kQ+peNEZrxD@09I$t*zim4#?cPFXO{V4<9&xZ@UD zeU&*1bVK^1`m4dSgY59_NJKm&_f`7@oF3be{$;_qc-|;w^Q`GON?%mxypmKRm*;Mn zY;mw&#kk|l+Ox?uknXFjJD}$po1q?VDhr0%7{?oIgeqtoh<+8c`YLS!RBaa^e+ydk zDhmelT|60xeg#TU+I>|r%cz|4Y)fEV71Vv*$wnV0qNw_`37ftf(GbEO1)UxW&wgwvL!aQsmXRPsMo75OHnK9ZyH<{40V@}SN>3F=vjnQ&ni^4#V~dZH=t#~ z*z+8zA+rJ1()lwDu4I-UX$$Pq9Ud+V#)s%Y?nuN+W^tM3QCn+6tiep4SG|ujxMBNK zL%5)t*FSe9_>PyzZXnzfs-D-KQwC)A2dZ7C`#O52S{958Edbq!5C2p$i%$`;C9{zm zg1cD_c3-J1zw*)XB-~WVEG{8E>eoEm!#`!gxUMwN4O5znnbTmIXz<}iGz3qzpwoaD zl?tD|X3i57RNTZZAREI}n=w3G2$u!py3(95lfYO%5NM^9xTXr_n>IF4sc)VJD+B^m2Kg=3>Z@X` zd`>@ap*63zU_MeCW5K4cXcx1D_PRJ}FIBrBYhKHOag6oPZGA*7x=|WAR5hLM z&tCK2N@lT%#;j`d>~3Dmf}xD=yD|*oSQBdY#LmfGMw=`UgQj)Hue`}3DdG*h~rJ@xMO$)9Zy7+NPstG_^o+m zb8voT{Xju2{eem%?v%~pb#Kb>TYaU-+oQF{>z-GByRREMhm?ov>s$zLWKL+e@2;=0 zVEBytdRIktsw-ZvzRED9#^H0g6=?NU0dNY4Ja1FKb8=2go!_2U-DIZ^90xYzhu`U9=L%50&Y<8yqN3I^3z$+A%ja)XCs!SET+>qaUguUB8? zE3p6jEd7C2U*+46Lk3e{uCtRxmt+>|sd`>5Fm9nWueM+q;0-B}WEQAuy^S2j&$^g}-%r`;Jy!`L4K$BK7DsmieaS`jzqRXZX&?y>#iaY+L zIR2}s)(Fc8{xhx=TtUZ^f_kF@s_H9o`Hhtm3x;y_>MLh#cA(y<7?tjiHnDZBpKG(z z;8-v~HLuLghA|OVDOXp-$CMRnsGo)brU0-9t0Ciut zbWYMrfO=kWCRTdK6OS+nFCHco{PC~obSb^{0|m{za$wfb=QG?~=^P$r??}*%im^a5 zuN?6;^!Yp;t*yS!UQ-Bo<8U(2>Z_vIK(&bOhN&zV?)g!JeQnS!wEC+3pFf1ko_QGM zl6lo+0@WhAqnc!vcMdAf1{3&sHZMs%DXQu#R{gW48wd8ZUO5XVs(f&5>hUCuSQZTP zBxp**EMF*S&8y8PDs+;bdN~zDh@Nh-t%=#b8A_^5?i+5)v-Bs) zzNpR-hD|nHq_J~rM%1PZ2KI(lXXCP-hp{f*SDD@zojZ%JEEuwIMfFo|z)CjrnoXIUA;si--U;RPnpX*5?6wWtpJajb zRm)|Ve9smPshtINUpETZQ+CW7Q2h41ZfrpDdi7N-G;EnU#djl2kjwL`v=U4MCC=SK ztFJm6jMkM7xrJ6=wRHsaIo0BQWPGK;;^9%&Vx@OHF*glGC#VbF&<8Eu^#cWUX!+gg z_Cx1AYdXY1QJo?msOIU8YMCMOv)-tXr$uxN&E$~RF-L+;o~deYp_v?V9R$TmTtV|6 zC1BWmPhaJ{R%@B6q3p(FNz$rwr($3_RE#bP-LpDC!5^S{=Rddt#hLjk#kGV;S zv4|b9^Ie0pDf7-&i!DhGok2uj#911n7okN&vc`8Yb>p*ZH zhqbfv&idP6#N>ux7iwO8@#5Om7pP`yHW)FvAy9Q+xhVJr!QV$2;q0sc z^}K#QpKN0W?;H0b zk)e~xf&J9rAF0~AzE*I-i9Ss0h6u;LtOiR-a-rt4@iW5yQj#ulOSaI4@q?f*sJMyy zxt_TR(NIuv6Q6rtujBr9H&_t@YPyKA?nXGrU05&TCbBd(SR%=yK*dem3$xMJa=2Z9 zl^=?{-ZePqUum!Am0D8IBAlYD87BFF9247FujS^uiYm~J_%K;pMRiUlE#HVYQ8~4s z?(4=eVT%7&U*(}N02;Bo5iU31H=_gHVgK5wc$X|Akfhy%TdLJpyZN@mR%E0a>p+yRJK3CiUT78uzi?(_`iv+ahRV)N_!_B91YDQQa6_gN`F>^OewNZi0*D!5l z8X@OPNy;x8^`_=L-BOK`bSYGzk~KF_%AdNgb~DBzeimyVwc9{#)7e+5T0F~PHXnseNEaXKBbi87pVX%X!hoKi8^JK^xzVkoXp?wbA~#Uk|bSE z!}Pu(CAbl{pyDQuB0VqlkDMMsAxlY;-t=slQbsFOLEfGI*7=zDfn8+d6;Nf!fKa|Qyz+uCHA6AH2LK$b= zO|30}y9Sq=Z@GPct+jc$;{L9ai6t#B_?Bw1gx&nD9D*^x?yFb`l_y8*j%vC2t}KfB z6HnekBTPRW_a{KUA=b*xCo%OP^8US%8TdZ3O59h+{l7O(Q~)g=wwq5Ve1j1y?$0&N zYVgK|dQh!-mDBqE{j=fb4|CXkRV;2)8+>-SF<%QRIgEj^1Fd;=+@B=Kjd?9M-`s~O zv*B@IG^fFm+watu*l2L2AGpFSP%+jW4_ENsdzdk%R%9&G;c#ejoaq2`W2skpP;75c z&c-zeydF=|%~_i7BdDIUMAA zUUXIC6N_I`f+JPW7EIOn1S%y-&ciWdYgcPtD|qklES9b!>MJ%QTw(N284&N(m)K}< zh0%R-73c;Jf97lheujpLvlY)S5;es$Ia;JxOZ=$RZ*3!AVw@*PgQt!HD*N`9YV}nH0e+!^dw0-^`@2vlP}xDZ(75?7)X7a7 zN=~_j#*^ek!|^824L5(Vu!l)IF*vmfQQT3j;5}}(sNzblpyNs8a0TyOZIeLlY|0C~ zp;c{jc<7>vLHq*s`>3E%k}k3aRfQJ!7a&~THlnjLqU%&*)*D|k;_ zU{WQm@>#1_$xPw`b4IXVl$&)+HQe+i2?}&$see@%-TUw#R1w~2aD~x{fvT^z4elCT z4mUM01$9-_TWA)Y>t2%bu;GNFm%MT~Ga{-Rb@Yhq#?ZsPGjzi;{VIdNRu8)QC|rMZLmZc1imqlNYc)Ft++oyn>oVNS9vyS zzsexsXpNv$4q3i=bk3+q>jvw90%5)lTcYY-a;jcR5`i_1 z)VscxoBt(QMnF+ft6OL+7~jatHr<9%%YmizRlE5>)%H886}{|eswnogh_J{>y}?yJv1lT$2de$&_Q3f@zV@^};IM$o7#P!cJXlptT?+0UVH zZ#7ulL?*(sR%ccNl^FaO2@`8Ck0+KA9L@?uG`Xx-9jT^hzcKX;z^6K zZlT2z+Qb1WxBU)U27%A=bII3+SgSIU1eE9c1}e|+mTL7?77yi;H(Vr6aAtB8?g6T3 z&Y1VEY}Z?b!#ZRcBP@vwH-*zDNY9V9<94VFFzx*?msD-pn90op5`ylZe71O%wn z*KgVKx6taVj^=k0O zmB3?5B2?AE53cff*6QCCymxUQph_pWo16;Xe``;KyZw~waSJUepTjr48A);w6_*&nx)pRhvEultqjp z{O3hiRT;-t%s~pM7;B}SzSh3FQ!|iik~O!`L_^rc5ml#7+(N6bHVE)3pV#YHb7l$6 z2wS2GQQT22gTVC^fr_1Pq19JOP_A8@ix2iI-cjS4szFf&> zUh60x6&jB>$?n_Or~9cy09R!Ms=eb|s?}E;1QgMKHZO@?WSDFakQe(b{i(!QP+4o# z>D=I^a`Rnx523c30N7x%sXNhXErG;;zAE5IDyA!Oa*O!n6zmn=L@K?{-VI=2ZfT zWP*)tFAm~lUX>yTbVprPBEXMgtREDKm;&Rj!4)Ck8iM0Zpqk=aX!X^$1ob6079B|Q zu(u4bDxS>{aw-Zc#et^X=xZec*nPwc(O}>7l|${ON?>FT6P1Xc^(*xs3o2pC+|0J$ zQjKh~7#v3U^P=M@eNmO-FrTbMqjRYL80h@J)UHkDhtxL zUQ*+5BeXo6EB96LS^8}b`* z#J_bc!Y3So%H_GGT8cya1en(w5xpuSnHVcj1xD_umhs~u_b3+RU1@V5dft_nwXp|am@8(e*ruK-j( zuc0HmM-Arplx5tKD_8aw>b?SVjJVO)oT%V4Q#JvWmcHw2svnH3rsGXUPQmy)DD9oX6zFUv zQ28ylP#ZrZAxcy?w!L`W!j#`rm~uD$^OiiXTQ>1~8nuK16=l9_a3Vj%nB3Qm>V3ai zTOKBPC}hY!yA43AuUanTKx(jW8(e*rB@6V~Z6Ir_=2ej&a&)y9bw@RkA3o!G)pA;q zb{lxT`YLU~(ZT0H3ef7S962t;es&vv&rW%AWc&bq4nYDf9+sC)C{Pk^?W~L+pe386 zqkul2sNjHC2^j6?5cZd)c}F#oA3h^t%8tRK>&xple)uf`!{*?l?a%9)eTsW2EC2^f zbKN%Bh8{U`l1)_bcr^5Qy@aXaQ`n_SoV%l%$Pcf(uNxU;yk33PRuJB+Ji}Y6)mKSS zpwDgtGN}40sX~lvvfE0u7M(qMCPxPU=T1fnuUB7f{QTL-ya!r+RpjUMkGBBU7H8$e z_`y~(596$_pyNqFi-%?1aZ30(LI9kLH^Qx)bgxCH2;e6tCO5dLj2|wp7uAitHKtzs#g-9xq-_pH2ey6WVjO8=(t~j)|p*YHd@nwVLvS=mT zQZ2=y@a#Z73)7(^rC(jV5~xl`-%uTw=?3b)ZiHJ&&yTg{b6V6ndCtB8n!b|df3%M? zd0O>%4W_GZu;Nps{5)@GqH(IPHhu`LJ&SP81Qb>AFkvY&V?ie=m}$cb=T5|eN|GO6b=R~Tn%G3wC5lE>TpX0d6 z(Y{Yq{RTHB=ZD;CDM=0xY%Ds2gk_Uh2&&Ip22d&iBS-F&bfFCalT2PdBLVZhQCy3I zEhS)V{OlAu0b0UTCon$AOP|8=jwQa?ad*-I9@yQ7!^_6tsXLUtUefQN@xCv5D~RgF)=_!2NbRBv7B9Z#&Tn3_Qx?;5?$`=#tpl?UVZhp z*G{36ac^oGY~zQ_#Alr|qBriV_~4Utq31=1SyoW@b!R)1h)F>`uiQ}iVsL*SWnRnp zA$mCH6{)kqO|;j2^|lxG`$k`D+skJmF#Vr1jX3HQ0poh6<6_5+zEjlx zP;xDft^w7mzv(Mk4+WjZ5|uRMd*4E%IBa_WeNK4hXm0xIumE*dHr$4xH{4elKR{(w z-!-@*KkON3m^h%ff{rH^FodOx>eLorqzgS;FoY}%>UpK&)HBsGethj8HD%QH^#f^e zPJ3}USbZIL<*lG|Un^*YD|!4YR5t=-!}Rv#NHbD@a$}#as;F|Vcq)!@67N~(pw^4( z9M&)P*q?2G4#XF9Y73y+i&_UOBV5K046R`zon-|bPXevTk4aI%XCruDWncN}zJAGE zTxl28>Z>&4xaoO=C6e%*y)Mo=ZnzC>aAkyL-2s&%xNC4leq8pIqQ@I<168z&s^@iQ zJ9C^7HxG*xb&(X^xNC43KfW6Ji}3BUQOgw=MOE|4MN%6Arh-N;`wCSBM(!HSD7mka z+Z;p{cicj&!IEX;4C}Kg&FQS7Dq%|c@U!b%wOeVV799b)4IV}eyRY&UC|m&|?ryCV^6 z+lw^+Nfni_ArVs#hP`yn>$t~n9iZch#oF-8G_NlEO0k9wiCAS{p{l-;^YhG2WK9e6KD*)eW!wM%GwV=}KIK@pfwjz(NjT(f{ zb`#r=Mb&-X3AYXt(S5b?L+0@Y``5M?yIpGVPPml~qoV4*qIK69J)UGz>FTb7GFj?ayQVq$ z)&2?B_Y((}WI?51NEf)^O@iaf=r<%8LIB|bC|#4>(-k_N|1%i(p!YlXc&74}+1qXr*c89(%n8jMTt zOmDlB9O6Ew}SL_N4Q3m-Xw3MkmKScNj;$Oy( z%lWd795@#~E8*GYe1Q%EP~^o$5H-EwZ5lWiKFjli&~Lp$9uoH&`~Xb0|;^Cf~5W`YT>x)eUyoi(`EUyq43*E)c#0O|_R)qfC9c z3g5&aPFJOisdu(D{RQYC>dW!6;nkiWYQNpv{#Cjds+uGz;C3(mU*-96QU6s7?|#my z(!~^LGq014VqfL?Az4#0{H2A~)!>xp$EAxuDNHmFiSqn>Dd8FDVA()gXa>i|57mY4 z=bW$d{7}Yt=M^J-@X?j=#^kF5`OH z;NsPuAI?Z0d~{{}Fqf-`e+J&ms(MV3!JSv;=)D8Z?ai`*^+CEx#t+beBL&x8LHEIA zsvj&H*2XrEtBfC@lF4(6ZJAQeu%PCZ@WmOl-6?1mW-geFJ)%|c`2~i4yEEB`DpIT( z26oeTCGJoGc_V^tB5i(2H4XljL+uNn&i%weRBj>r9HY6Q`^*S*U^i8nX57iU%KySId2csy4r!=L`2ro- zP3shTDO0li)lC+xb3dntE9`~YZs@>nVpBj-HLnwQYn5pxs=b>ntXec*UNyLkAE)oK zf|1wi5?bRb27#(v$|baTmGQ$`Y2a@CPNhOJZp14)MehxQRY}ILvUj2yEZy`vID3RrtEEhB!H_OA_;Qx~KNwwj2 zOxZqmuZOElGwDs5IM|DE@AxFpYN}3>U=^-~)^T)c#aSGJq%J67gbFhY(cqSgi@)dpi(ec34?AzzgU{&P@_iwAOJ-@=7P%5 zBVFj;&|~pdQ1d$3D289PpyqYrZe8wS^QtXdU+i)ih<}B>@J8(8O1jX!9X zmM!WotHJgQUP5E&dGp4KKi#i$_(UR2n%;oQ&2~w(l&M4r^)gsC;8_Y)t;T>35}wzY z<`#d+0Y=DR+3-`w59gcjJv=#}i$dGQtHNF^Rb*9PbyFEXRL&OFNjUST!d{eYHgvFT zVAEZ?NxpN6Txq_%Y_NGH-&qDc$(*;-6^~mtajk_J37oeR2akK=;9AO*bfH@X!{eSf zxR!z;>F-wjaiZI(wL|^oYgNQJchGi6MlFwflH^*-l$5*MIfut>{BSMZM7q%JoWtYA ztCTOt0!lfao1F&7^FuPalP*&G!kn08O9N?&@dH#cO!Q(PO$mFgT?3m0P&Pyp z{FO+=X#`Zd2}kXK*Tk+?&3REBr1$Z7DHzGY7lnxi;veG&l`jQDAau}8@%$vYl)%n? z0E)*;H))yiMVxx??5iHmmM!*WNSPA5y*1z;+c@@_j%)KeIE;+PJxOw{iGwiGK>QQ- z0xCUBQo=wF$M~VXzIa8K4#c0?%Dme1vwV=}zTNIbt;O@Rs`~GOh?{F5O$mDeHLtI_ zJku_!CBrs;h`{Y%{S_3gW?tpmB6xT2A)pXq>0wQ(K=qbOs-;Y&K`HZdAE#ReQW~tq z4IxA6)hntoe%3Jr+ml~kKH>TjS`&wont*C&=_S<04^*X_2r=G&bpI0e`oK0&g9isp z^SF&#uFdP}yS5)Kq0V-aJ zV%>jq|H}ArndUV%duLx#&A3vsc^@3YboU<}@gmEx%QUYj^1V^}FF8LPFJWG(4t;Lw zcE?)cUz|ojrJL4aoC9bSj5jopi>~?d{DM$T;tqQu+~C1RF&@vv@o#@2A~A5c0%F@bO2wii7UT8i~hQ$mv@E{DNKR~C#9xLvs>0~MaI z*E*PG8w;SaNUjDai90}dURO5mKqSieA$lOH19$5>$0Z`6BneIsmzVjf!3lfu8uL1E zxAJ%ly?^qakdmWM_k!wc89$znF(ovITtdUEU0Xo)C0s&d{8$Z=?<`NwB{X{22_Zl= z{aiuIf}!s6_T)DUi2E;xLv}o_uQDKj4(z5X(~L6TKNl>nf!*|)*cF9HcflpmX<#=k z14g>(RZb?LQW#g=R2B>+oA++QGQPK)UK94B!Qz#4q5F@n$~3b%QoQ~fY!u`1;#D36 zQs9+`cExKMKi-lFRA$8`G#&z1OIW#K_bR-~G_P}s)Wd^tCXW}d3VV@-Cbq8{T*i+L z2%z^{K%iQ@%G*gYn-(9JRHK_-Ac&3oh$2 z&6ii*lr3AUO2yvb*TF_H9*?0%$!0+(?pAV7(qQQ_oap)zE*o6DYMHU}8}BU`qNSlK z;|Hh&>xyc^UYv4eUWuZfLE9ahm#<~~ko~g#m4Lk5Z08pgw0MI zdr`7k4W77Lt4uS>+`KZ2o#}0NGB_3XvJp&0>cO&MIYZ2=jUUp5?xl&sM+G&nloGse za2Y>u>Q)ko?-QOmovp@IVXyBuyz%!`E9^z*Y|jJT`|$}rJzTLXpH%hzHt{#TmFI_C zDpB>mj5FDy8V`ZXG~*u|I2Yb3cJ(F`4XFIRS5(XRp+c1!JaM zRp&^PJU^61A1oX2H5OD8M^1jb;B0yz*T~RI1kIOV;!D#_~2`ygj`JuYdV9qJy=S^k{ z`y&S4OO7}9;GoRJt0(x223MKp57)K*X3Dv@V92s8sxoRhWbyu^t1`_{mGQHV06aH! zyW@|J!`VVra==~?8E)qn6f}C6vT)mzKnD&oO2HLXDO1vg2E3N%2gNO_-ZFXB;4*$( zrkSr*Neq|Jc)2*DNK~DKe+i9;fOB{RB_-_)+U}%>Q>=#yeBza*^u746MBa_SKcF(; zCx?;oc=5Wo<%LDQQk~AtPJ@&1%xlCeMS1V%9Llh#!S?)6U1%T@<@uqA_TIxp7t7F7)nJ9hWCTvE*>=@kme zvIDzmnZxE)^D)qY-L&da1ZrLP%=xS4b+A#4$BS1RKV;wRZ@KCwkZ!P2Zob)O zaKA94c2_~o>%`q!Wtu73XI>}aOm>GARmm{fq629{HJMjM#J|6&;CAky?M^ge89(fc z*!~JsKG5?E3R(t%x)rEgPZv-!f8AirJ5e1RySYxaEvRO7qT}}}9HXJ2nj|rj@4E^A zTR~+Itl-s|%k7T4iO^V}ni(1Ef!%}+T2S#y;?BMJll4$g^Ez?2R+(me@#b}~QH;ln zR~tY0H10n-qE2bB5_i~lDR1PtpVPw?_VO{<->i}D&5$b7%!$0_brR0R+nEO2_`zHo zNK@tf*c>HqM{Hm5TE>q(ML@M|zl3JaaS#Wn7Ft)(vS6_IwT%hXv zXX0+9USu`cybd;sL8y3@%4ci_?$#>P%xlc67tmMTRADd9sZ}@Gn7M=&uX4|_?RXH* zT<5iFlEhags+1)@)7$Pu!IbgiGR>^5&0IJo}nRa+hu^wb{pQG09?7>G@u`9~yZbX3U`@5oA#t%pE z2|B3D#eSvYRTB;RMc&9us-;Zj6(b#MuxzL@&3u36m9sp~^tL{ z4BGCbn{q%G4K}Y-gB?Jln{X+Zs=kEt3qrMGSGL+oZdGLS5*h`=DKw%w*(g?JnmIFP zXD}58&O}{bVjcaS!BOlAs3Ik2Y$GiUchUK-ogch#~YXjBva|w+B@7h*O>Vsv& zI?2Kxox-2X9vFy3g}o@*ytR+a7cjGt~2gFuyaan;~5eq5#*vq>w6OK6R&KGIcL@qUTK9GnKreg--S8Bm(J zpi(fT3k?)Zd44Fmt-+aW6r<*KQI&!rIC#I#SphT4uslEHvCA~R>fthedkl+3#zFY`ES|shRR62gl6LKb~cV{mi2WBje_w`bD)E$Z6_dSKU;eAGUMugEKjd?4!ywbFE2| zJe>PE=c_zFlx!ANvSZFo-R@Y1Q%4JFvhnlASy=;UCJrh-i7MwB+(XOwahYax|G<&* zRh}O_;G*gSe9pAPYvug7O!F%KGmxeVdr`7kR5?}VOmDjrs>q?GNlqiEO0S+@P|zqC z*J!|HB!zJa&BWpS3cSOEs4wYLX|P0yK+wRsu!?n$x+I}bl_Yd zI8aojOxGF1XL{S6^l*88n5DPBa@d=!>hlWxAHdr>WgFn2= z^8<9?y<`V-pz{2zV%Gblch%rBe%Q^dZkmKM*{)qwWx#Ww?BJs-<=?khTA1Hg6J~MR1_O% zMD|G)Rr5M=w^o^EYpEA%xeqiVv9VBK|QW?!I|E6$9k9z1qGEsu>7|JXe=1&E^p8O;1<09a@GpT zyec&V=)i7TDd2%hnNsKH{-dKbb3wJb!a;Da!q*1=P?a)WM8inH{CsPo zp^TrtgiC0Rt9&*<<&L?8*0?I1^20$=18IV&dDY?us3!O;s+IHOLJP!X_V=BU@tKkZ zRaB*$Foy>dM_DlB>ugjgSvau5ziZ1D=`V&3?56K3*5fkG%zgvA>APZA)Lj@ko}@U``{oL$yQyD+rya80--z7A>+VMga zf`KEY$}|%k^tggO)7$R2!K5g-o19)mwFbFk&MzovbkmQ+UL@Y%PaJR>s+!6<@IlJ) zifV1y`cY;QPzly0Gztbk_Vy(Hwt>6#r?zZScUjQMMlrm|;Z-W1nxO-C>pF`_pE~|d zQJriQqpEX3&FjS7T4kDv7n@fnFkkg>g}v~LslgL>Yn5rHilce`kZo{DwRqJ6ow6Ys zr%R}2Cd#`=aDggPas{oh7YakX+G}+Qt#K8D6m(VK;SyTB%J!iC>%eD9Rp*F=9Hl@9 znMSPq0(I;PeKAllwPlOt&E8Fvb-#}`RGDTDmXlGt;$G(t+U`U*RqP7mTT~|-#nygZ ze{>@C^D}X`VuTjdyiPWXVbc}VyiVM$Ri>E&c;-Ml*Ng$Xl|rpo#GvGKF2O`qv)chca> z`QZ!S{`#}#s{yohlgv?|gG?jRk;3cl0-+e-#NWi|7j&CA7IYBxtuoEz@N5jO5`_28 z1=4&xNpigp6GfNr15i9}-Nf}KeNY{^TY22Pa&2A*8^w6s%9LyKI&inH?LX?_IGO+Z zZ?I8}$BWn9^8>E~cPr51bvJ$%RLl0WI7)_r7O(q93UuIZB?qf`-Ho3Gy?3MlEnfGq z7f>9|=caCV(%=|ByvE~-pL+l;UiYvURB`kTpf=z+sA?m%pt4BLFGzzEy8^l?Q>0{& z-pAvfIJn+gxu8;0msG7_fNqA~l14(*uV3-HdwzfpHi`i)UiZZfQ1)n?`*ypd!C$_{^zc5t zEvPKb^9u@EyzVPcpg0oGpd(d?dR%woXF+ASonH{D@%(&Jvib2OPzQi7p~dT-^Ru7| zV_iav*Zp~*_Tyhc<1`{`Q*+Kgc4M4D+nw;5*cDJI7@{Ks1ryH?P)!^ZCfb)gXWB)z z6wL1VS#^5voeS(6EoHiUeil^mnJcO>e!Tq@sLLB&LQ9$MUm8$yEzY3rPIyhivwi0a zDiiAbf0V;!lojn8bkLL%d^f1+h26Ik4KR`XM?B_l=^~mc_#+3=<@mF|tX72d~ z=9S0%y{b&}g5En)$TqeC&$W5|(u)6*YQ|M%nxRSv`V89cRD+Ax-N^(L*Uvo^)g;|S zI_%^51(mbl{DM$T)-sw#lOzRWZx<^(UJc$ofb{fWqZm7`tHFD44(Pz$x;ATv*FAA( zK?imdiTwpNuLE~0REt+zFjR@Tm*M4=^Wf}DDjGa+w|-WcX09cOl=!^Yi2us?p=9$e z5>!jMbwNU@c-=oz8q7J-XF1yLsA-=ofy}(x_@QpeK$@~&o!6MxK{%7gYg}#oV8Co_ zKWTL}xOm;?D0t;4wUwU%N%Ks9l^58SORz=~H}FeL5_#6Mv# zUSnPd?p7YpN>XK->0$4qI?Gg~sf-^=R_-D}V&LGTOX3cWqW$w@L7?>7E2?GuVBU%9 zz}*U^;&pd{z^kP5Ow{2_pfyR__{kZkXKcDDIX^hD&8tspyo8oPVB_bVy?AHPcBiP; zoMYqX9phvGje?QS2AjeKkk2nL)#V_NGF3QbK?imd(|19oV9+}E9~~_#s3s0J4ByW= znCb=9su@4Z{YSU#0rP4Lh7^K(@u#YDLCx#H-AbB4@oM9T9fUkf!AP zu)W>9`h3W%Zc33upqg{=yxv=Dd|heqJ~MJu%OJgv-FHzis&2BN3Z7jxxQri_X$CrR zw^AFn8mx(fIzRU&7p0j4wej;gaksuE?Da{><_Bvuc(757$D>Rs*(~V9-TInJg}lbR zBE;vu-R?x0ChWytN3A43C+^l)K5)yhji1j?tILJL4%sFNJupWK%3REZVR(2hw zn;iDyP`rBso~q6Tl`)dt3+MOw@ewDz5Q>Di7_d!Daktwt!dmES^Ezo$y*= zFD>L2bl@StPorkiceP)E6>lHJwLd@@5O%^FuUZkU40u7s7~CiZx!~!x20|xY!ri1lqn^f1)aEC*~69w z+w(&e$$JBSwb#7b^FzAO{haew#*fN0(@mdBO+1T}I)tOTi&uMos3bNJ#4>)giwLTd zaOScu&8s~>-`|5}1Iws_dR+0#pSj%bgx3mtsf-;B{uy`(@E8_V=_ax;2VYLbuHGEG zB6Dw`V9N9JX3r0%#QmJ}R-PY~Y34*3&0$aaD&16`A2u&O9$nBu0P3xbpErAc*q^qI z(>2waI2`t33)DdT%k%SQ&(GvAGOAJ3#9_}531I{AFVBz80j8U%nfZjx$F1~m89yr1 zyr2W`B|)kPqCG!k0S^SRj34D{LUj_(#GMuI+H&xi{&0#N+ zh$g&753`B%L26OG&orXqNE8fpmp3S}ph2AOy*xkfdsYW$hx&-5GshN*D$`60b_Iho z{61HDEs#7oY+Y4@siJ?Tx7`WVGJf9ogl8IzM|%Lx#6ihsQGFjc@88Sw^DfU1?vTN< zVL1piai~l)4Q9L7eS^#MBL;y|I%NPYUgh~&%d30w#}!Zw_PA2y^PXxMKiYsqgD2rk z_7{e#JU@@Qc|f&zmGQ%;bD!|cE~(;GIX^%LfyMW78ez;lS_!XCh&(qtGMq|XlQFC(7{GA9?vBCzIW?_4(ujk zDAiyI;tETh`*ypN9T$Q*3 zbfOW<_)*bedU)b)tuoD@95116nuIgoE9^zd<{iqC?%oWkGR;ucxDw4AXv8vp_!2}F zDSk38k6Rg>GJYu8Z0LQ4Hbt>w!4R<$ba3n@(3;hES2WoggNii74 zsSo>%`q!Wtw@7j34}% z_aZ@mRD)#@kbQG+hE$nmRy^jFGfy6DKl#UkxE7M;)yB{3#NAqDnxSf5C*e%$928aY zireg7nyO4QriXatM6-K?U_}hftHNH(g1cXFJWl)EWC*I#P58U+jUTEj6jdo0Tq*-z zvt^5A(cW|pS|8X=oIDV!d$j}@ow!?xv=&s#l;!LFB9zk11(j|>HErW`DTrmk$g@j> z2OGuk@D#7R23^qm`Vv5kR~tVpy$2#uVK3_CZ^A*+^8M}+T*xtgut*HOuP*_#cvaYI zRaP7bVi`Xw(@Zx_!kN_Y&A2M;^^XI21|MA+KlqP!URm7@q^ZJQRP7X0`Gt@F|NbXx zt-@XugEVvyG9U~dUKP9IsM~=RzIw?DX5X@fH89vHM$|rrp2{=>ow!>+Dt4uX9MHi= zF{qYqvhhQmpTV31(!46{wesKwb54c5lu1Z~C+^mdY}q0)NfQT_<3Ri??De6r*T46P zyLClw&8v-{_iyd-{4Ip*e-T8x3`x{i*y|q_)b_qJvY|Ce+W5gF8Yt5Wdy#bTpt4p- zd$X>nuFqAxs!a1^admIOuu-L;nk1Kn@r2;xmb>Y(kz;En^)oc*U}4Wciv zL3-aK3s_XOWeeya>ibAEHB<^FN9jEN^y{DSTCppAF7)tZqu9zg^WfO{Nrm-a1Rwti z)e3v*um-43Hj0r~QdG_B#NAqDnyIOxNpdN>b5plF)!^b)VK0{IgJr{K89yr146mGb zcu%#$UZk)*o(DQ{w|_59+Vk`EeP3S!N|`vm?D^ps?t77-0#{Kruhj6l@8L3j zRHm81nS?V}SlztZ^FuAlduggN&7UgMj4NE5QlGRsB2hU%)BxK>0tftn*K!(ZFqiLs z;2^_y5ndg;B3)>}Yk7WDI})l2v0w69#*fN0uZY2*z67P2(_qK0IRE&5&LQ)#pqunT z^<&^%_$tp2YDI&CUH^p5$E}QOd46=PE>vCq{``VK%k#s`C8{pseF-gI?fD^HXzW+%m5A{7^n^>#;M@teUCkR#1&A zHP8mqR5?FN;96Tu2lXXT)}d;r5vQdLCXN*Ap^Bp>4rhH_@>+>IUrOBhMFq) zc913xVr_$Ns@Ro|a;KY^i=MRgaVz3q`_;ep%^N^n>-_wJf|elKf}tAT{fdKUGB^%< zk;^jB!)5%aOfwCpMAo^f+nqGHj2|Yc$6pt8VElYl;*QER|6}jg{V{&nvEh}H%^Ov6 zZw9O8D$|U8yDL+m11}dwgL_y8KMj5zpYSeHf?uQGlJ`VKVWa$cIM zj31x_1D=|M1>I+LcIOOcy6;Nd`Bvf%(80bd@{>bV#d_E&H<;$C0v)XBsGu9FGJcr+1}ePDG<&JM${Gxo`FO&L>OM(wEYd)Q6I3p! zd7UKMVbTRE%+gmQFR@h7F_8fPD`SS$zxRr4& z<3~GJflji~Iq5h(tgsizi3%^{heMCmO_T7*LV8>k_JZmly^nKv3o1R#{?vgUuGp0h z&7qs*Dt^+ehhV*eOf>_26AJOBFr08KL z44}oUa(;jgv_Dmy(_pm)=%88&rI`a&>uh!wyiTI|oSsxrDHtbE zKj|xR1*Irc>MpB?*;Dca^|)2g7(YKscwP$ee(Adw^yXDzFQ5aH3+uI@;+1_C_p^GH zX~qFBUfC=$fflcO40Dyf8myX^@7}!H_@PA5_9Z;&=Jardy(rnd4-UHk?x*G|(@gZh zylS`QHPzx(VXs$`>IW*kj2}*VP=l38e@V5%Uid%^9qf|lu!Qum!d}#E7Lo*ub<^!6$>SbZuFb2; zYCIvWZsKwC%JtSaBxq~1@io-r3e>!^2l5H(ajU2nulD?`WX^kN$}|)0Gq2>g51_@X z!d?^*xvwq+CC@orOE-Od+~GKfST8j`^d^VVoDPS*B)1;*FGU#R7*E0?Da}I&(?rTXku3c_N8F( z3l2WIcz%FNnQ}V!U~uC30V)NvY~3eqJ@jzakEEe!;-L1;02<@R87#|-c<;RD@lvMt z{E)+NJHG-gWopk4hdvJmCt)uR#1^ld;yi%zrSFmpRC<`qsKNXi;|Hk5l}$ktXz^;# z560R+nqvHrCSqO(DKw9)67y=$&!plG&>B}8KkKyLdqGUj53i97GuQ)V8mAFZ>839> zklj*Uo5aN{Telz2|HFH8Z*n2585~847xcbdKF~}YO5g%Y^6`CxkwZ7wu`A+96KL_O z{pvV01|}C7k4063Gbvz$jwoIo_QENBFA`OznPcVk(XGhGeK(cygUzpT)&96Acx(SE z(+pMfN{aRq)ZC0mR|k5Z zQ@gSUtHJu{@QUA093=J!YU2mL=LDKrU9oA3V-Je-leU&wot+<#Zh6$z9t=*3^$<9f zG9}G)d&^}HCw2vN`$(ZWsPe|+QKsw=P=g0m%7GTIwqU42vx)O{gR{EQfg?2dePD7` znPxKm%&YcfUs5gON5|?yl{L~6)Z%56Z%$6;zyIsKmy{~EX^)JPGxZa!o#v*tyNhWp$be}kY-WS8;@zPEE;^rR~;(gXK z&{C$dUnC?{?W zpy8Fgj>q#0dcWI?Pp)_seRh8jY{V+l%xgTZUjrWu=eUR#Q1d!Co{`6kR~bK)YP`=} zU{zAQD(ppN$NMcHK%<+8*s6yo%Rz#k;Z<9WhtwrmmMyWgNd&C@6t!gG6r zv0?7#SHe_9b)O_Dgu1u=i8Mz1Q>l;^?1mn@`tLJ7dAxX4*bC_W9_~j*`Tmu1ZC*bH zb`vp)@TxN^NCUVphXkeQVSM)LVQS($>7mE1bW<5W_^}PW4^xvdU*oE<7xv3Qg;$wo zUgL2cY*66w;#FZU>Vytd_-k^0zFemHjRH3J6UR#T_qZzT1@u1Z3#HP-3VQ(^ERiV9 zTvVk@S4ztLxUT&!+i0>sVZVAKYxCZMVaZrfDVWzm0wt76nJRWgCD!{Li$F^^DdCx5 z{{7wtGVF_2g}s38-i;@H74c8li`SS}4D2VU$E|`EuiCPeTCh*>1ub5c@CHNrsnbR zDmNb0Rdm|uRS#obS^P1V9*-{QV2QLQaD8;jnglvXcwXV+f@D0$1O_}^I<_{ z{7{|uUQ3W?Q&3GDOu7?jbQ9W4-Sj?KHLoq)?k0JDsG4)XW0CZc;#HoXRh0OC>6=fJ zZHn^z03EEF`ADk4=2iQso{UfiXASJuIqcr@xPIMlJLK`=Rbj8Ux9`EKxym&28jmX* zbe^>JajP0!yejNPU7~@FxQsRPYU2lY(EXf)zr3K5VQP$SJ@%y4X>f(T$ZFd9nxv}x zTrNuOW#S-3Tu^)_CSS~@#8Yhs~Fe>TH~s)7ts66 zKz5MUoMWfahn(?Gx;Z@zt5z_IUGeozG-7#v-t77L7}Rh2dMo3{WtypJai2g5w3Mkm zKLi`@dzjM9=2aP@RBq*9q$fS}TM#MURZuC@4;5*7f_D$2aSJMC`axXw3F=5Syt+&? zKIy@#`Mo?pmMiqzVAcFy#*fQ110AfI-^=qu?&E_SdiZCsYOXTPeDpF1K9v3Tq_5J$ z<@sTY^G?-AH(x_*Ty6ZU6J?*E9=D2WjjM8gFq`f(1J?;K5eYkuu(5(kFr~Lu%GU$YAti^!6D-Egy5lvvtJ#kR+4Pm z91KobFiI|^!P?~ZgmieVu-Ci7ULTf&k(b&+-IXyxRD|U2(rKqrzWgSjBoUD(;Ig(a8Gf z6!rpozn>0h3<4b?%x*fF6_?#q77TTl)x(4RbZGg^>SPTYI>-#HGR?e3%9LY52R+P` zvyUbL@lE>Rb+Dg~$4i;2SPz|azoP&n)!Ik4Yyp)r zrEbDta8R2b991f$@Y5hO@S|c^)LoV|sjk4||G)q7Oh;+vqAK0Qxk&f(>ql8Ilx!B& zLE-u@62L>%VK0_+gTX1|hot$P>d$|J1@}jVy;$7{sw}DBJ@ojW9{Q>>&0LFD;)?fE zGmD|{>aZ8RG?1n;e&kVDm5T=pZjQb#s^;}=klg)I#*fQ1v$z{9xIZfFrQ9zXEOYU) zhxz6#{tkN)e!bVj7`_FSGUafidp*p;ub`SZeg^yLs0vgH#>S78^ChnpyZUhKie=6~ zB+B?v43i!n?5Cr_#jCb#0UelJtW?uY3VR_CgJjVv(@a&kec}Lmzn_lBOAjmT#iD&8 z5-HQnYxZ#^Gvt0h-8$(qyejMkbhk(@$F+Q3qUTj#r-%kg$##P1- z&_N>m+MVK$PB}k7C)&TlULOj3EkDO#;;7gai~C29t_*^~s+rQvZm{xZ7Ia{8tn;+2Ht`&qrpG*ijUyiWGhEibxxRoDyv)nL_J zWtyRCUMKtMIIy{>npds(pY&C_sf-_052HLJQ|A-Zp@%WT&8xy*INS!AfmC%asPr%? zviGYi$^{ox%9K>f`}vgwwLsJtD4<(z`O|pY7d$^oN^0DGqp6sW?JDLV7c11yeiALm0w}O%92k2lw9gfw4O2Lo> zKj^0N{HXK{yiWGhQH`jmN;i=iJD4QtCG#rJ4*~PRembf;7gW5GE;pDY%k!fZ3J0D{ z_S3P!u&A0>CE{F3(-L9vs!%UfC;RE}KNr-zPWIEWt+Ak*B*`YYUp2Gqub}2t=Nw(~ z3ajST#t*@(?dCPKcvZqPyEq0>-{mk5Rq0^@_4j%hmu#SlU9n~!XhhPM3n~SJ$6?UJ z<@s@$W-8wd%#fA(XkO*{A;>e>V@Bdypz{1IU&a0W%A&lW;uY&>0*wK$lORbvCj0t{ zG(2v3ro+QuR5fv+h$qnERh}P$Sc7N-YoSoJ@qL6DdcSuo{ZX(L_w+i1sYT_W? zbZ7ATnB2W-Jnn*uTub_vN$`Z=-R@N#VcMbz2%B(eRRrlW~uJBUqC@xg)5_*BgHP( z>h2~=pShd#xjar@JCWOO$YK7)CsI@`xE~kk^Sc%TTH?Qly?8wpQXfQEjUN5eriw#P znRz_r@AXH=RdDmr*9CnqsHM+E(14nYjoE@KUb@<5z0G0rZm>S$4fzr%+vLsG-eG)n zuE>FN(_9>>lHm}jbQxp4HIt?s-A6^0Y8`5umsEr#x6WBmb8(`oGuC*@OJxev`F+Pk zzfh%6WuDSFu#G7<#l@+c*m<(`!=mbOAa=VydHN};ktWqzriU@t9vI$t%={0O>~6Qs zODdM??xy3$(t^I%Q<5h3UFoa8Xz*J})BZvl%-ODP@PX@4#fj_&TOqA;!2~@zUJI&| zj_DCstYlO820b;GWBl~Ja*#z)6@wgLVL~NCWlklQ0vjNfw5ylm1-gG;n)&a$Eo_IWcIsKcI(p|hgb5A z-NT;La2rU${CE!A!38Zrw9As2+0yjqbVXU)Q1x`hHY0O%+-_5UiGumD5sZ0lE<6#P z8q5)Ec}gFNeQON%{^uv%RO{EAJ>v8&vj4A!iea|Y}-QWTM*zk(&nvS5PM%@RVj@EZtkXiO1c; zT&suiqwJF;%f+o1&1|T$j@o;er?w7zc_C)7YYA@t*|dIAKhQm6_48t;aZYTLh?cU zOtc!z*|=`7mq;Hj=E3`F`edmvQw>_d%7UbjygEL72l^lGid>Mlym!{rP&{E;f{lZaeEU!d_`I-B6-B?%+k)JMF(q@a-|xdj$f*)%}^(*F1<(@maAR}S5S$f_yz*Y`@f zr9kbdq?+~CuRxE(lm=5HNTW{?_njXyTsDokpwjCnUdgHmRBfZ|rJF-39TB{b<{fZvG+B)m@ zkhSFod(p_0V_rS|ovD`iI~~w^kiqfvcZ6bZ$Z50=@7({4p>>$w_CN6BZlWrq8?35~ z1P66V!s#)qtDq5o&cYK_*G~ibm-thrFI2r~#1|;>S7L)(9IES(hR1E%=AbL8NjP!gUCoXnyQH?aE+!@Xa>0t^en&9Ii(0DJ&-qi%ot_A5PIn<3WXrw6z z-11FG+z0_0b)*_;!tcI6MR8~e_9=xYRBI7Rc_Tv=;$z#RxY++z(2^!6zJFuZKb~a7 zyfQsQOPZWt;kwcbDlX2@k|z5&@flf8Jn5dGD=}1U^G-O5_qm%q>7Jn_O`e6nX|dn; zr!=u+H&i#lMG)mYhu1$Bp~Mxeo08;@;yw(?-dcV#IEm9iK!QWu!My$zr{nQzuxDZ7 z4w`e+izXYYwFu?Nk^O;nq~PNcUXNO;pe6pEg^4=^DlYcd7PQ3Qi%{YYfvVe2&{~A5 zQsK+XI^0hUKK6B}CQe78`%MlOG~M*))Vz*=v`BbrW_Owg=g+Abdm|#@shLpJfy13q ze$rsCGZ+U)^9Upytl+26(wknYvf1%4Bu}BvmV>IkYBoC_zL#fEWX|1We=f((d2l>m z@96OQQ@Y7ZRowVirk=0QP&;|ac~C1!$*VsXY4Hyg`*8ZJ7jm_z()3iG!kj+ne#IDF2U|GJiHWF-e|sgW1UVcnb~oe0^&0 zyK1ejr*>V&xE>b^JC2_;xK_=|IUs@TONo2D?@#f^J?d`K1P;`zD*}a~xUNE#z3!GK zd69wIYxNuV8(QM837id!cBIHM_A5fQre@cT2dW4+9?D&?g)L|t+HYF=;_gxd1juhe z>!Z`smpnTqYk!kB9@x4Hw3faqhW7$=pRO3}Bcd%Ht|WDaoQX z2vn=itq#>%zfxyzdjM8<#Z7~cB3aPP>RQ{w>#JQ9rlyNPYo=3eIiMd(5huiQnBNOp z3Py`ipq_ISVHeR14m-Uq!(wnz^~%r?U6?9HgL~Ko(HT}{8j+a%mkMV`aG+XA0<{dw zN)gd&aIGYjBSeFhuE&KZq8*$DS4>i++JMG@Kkck5XdK$?aopaFclMZa=Jr;Dlku5y zEXxNgRIiPc{p9X{lIISOauIzN7;pNZpRP=!?^C_mK3!t0-N4yHtUSZg{CA5lKyx2lUh;T4ymKTXd$9AbR142`TF zuE3(}Q7~J1#UIRm6<#Z__^z30)fzttecn*e5=41cfgWwNXV3~PD(Xx|x#!D3bmbI* z6}Ptx+p|g<%;8fL5JB7qpU;uFLZA{?0v`wC;|cVG>>5E;4GjNqoO{9SSM|6SM*rA= zp>@v7#mQ3zjS9!o6pc)hrMfJEa3$!LlmGoL$K=%0!s?O%w+WS(_>S3?Juxdl~ z&jwdaGDRhp&7}t0k$R$9F-g_sqQUax)8OO6EDf%OS$5T<61Qe9=${Sd^Rf(UVa8Wy zqgEf*-dvKk{CF+QK0F_?c}gpCRor?8&BBZ$wDo{?`0M}mTU2A2s<;;2B$W)W$Awv- zwJ;;WVt+f9sb)IP)h?1;7Bma9Y_?*pauE8!3mWbJp-GY*6}!;WV8=LjbU~v`C6a41 z#_o6odel;Zvis8m<>ebIq})6-y`ZAC2uQ&Y?9)UR|PF;(){{@lC>aep{ExF z$}xIwn?0+T(t%p*Y~X^%AfV*c{%Ugm+~8x*PeDtX>{;cTvkV_|egduKV7A5+>#{W2 zk-E32pfR~r=8EKQZN#SA?MOXCOPVw_1Kn-J1wAa0ifT!drsfywCTJ?868}!_M3uyM zcjj)RB8ZWW-#Gpksy`)7o|-we$Kz^8>X~XulNabDWNL6!z{=E3m1G&4(yCQO59^E= z19DN&NE3-O`xBU4>ZViK*@8xzKD|^W5Sj+dz}R0KX!%UFubKwCfD{Ej{?bkB)OZaJ z#i!ih-6ji*zACDbCMl#v)zb8N^qCek(xie@Kx2lG!()Pvi$Kd~nglLq%l<|kp*1-2 znL^dRwa?@FwWvm#ayBkO6V2)>C1v`7uEV$AYW)gTPkM&vqM+4atzTbWby&)J zpET@_Eoe!T2a`aF6wIgR>k|}rh@W!Mld_iw@l$i_d!Z7ClkO@960wo}ddvH8+?yo7T($TQx zRW93813l0$Xma4?1EQPQ+4-cchXz-=5NCPp&oghh1G1>y{urv+)=!Gi*2-l{?-~v+ zj&c=fO_Egh6;)Y=Ku?pT1+gYcIZB~QiO9!W7F12yUt3g5hCNBvB9v-AJLUwfMX2@$ zLse=8s&e1z1))kH#Nz7p<~kwo@#umchAGfW+^J$cDl`OC?%Oj}a$rq0D@n=$imIo- z9a~iE%kfH*bQ(9<)87eND@kgE?0;q{XFcrc?+mRk$Md02orTxaO46)&l3Gt`^eKpO zP~1C7e!?q-d)-Z0N&aWHgHeOs3!G{jsJ@(+lW!|;h=_6oOrX}ol-AC}zpo1F{pF+s zT5z&P`;Fs&hO&9kROJHU?=g+9ppm9JO5n?Dv@2-DpWRM+P^H)O|N5;4XK=Ltj^~I$ z)YHE%1FcE&+mqx=vHc6je+pW>Mue)W%muV~jTNB6L`U3js?klgxM6~Of_mIagKN)9 zouZfW3#T^}GzK^6sCqEf40Ol81(iRQZ`89emHrQtl#$iL9BV7_PsJT-#}0U1=ZimH zxio{GXP3c1Bsj$}P^ktM&1O4I-LAsxn`YHTRSe<_)LV|o;+4b!Q{B}L5d-|_C(M4s zHY?U^zE`hbd1?Zc3xEcDYDUQa=5_nadb~b5#a|(M^lhd2&hlD;2=iJKxb2`|_N(2t zfNBn{;yQ!5cfbhjHsFIKSxV503u1?u6c~PL1$y;@KF3PGGR5>zGjoF~nl|sx{1ubcc1Nx$RU!XZb z;hW5Nz5C<=*B^RtD!=L5nY>KRn>4{imeL!%sMeg5k5o>Z1@$*^g631Nl0KXb@_6vy z_o=|TsWQ3PZu-flQ_2z>diaJ4DnG&^;7?sA0Ir*dZ>XS|B!7~$8&g_2y&I$a8)%hl z(AGWvt|baoV;LuZh&#oDLbYd$ zgX9KV&?r-~{QZPyY2VRBL8DCj9N?&ALG&AFYVz{ATA98aeOm%DIGcztAUTkLYYR?x z37 zn(ctLtAf_|nyFa_l^${Yzn~>eH8me+n!F>>nwo#IqCaIxJcX7tWol;IZ65x8Ra7%I zt2`l(UKEE8w5H~&YMvm=Z<744pe0S2nkjvF!t6H+TGA8-wU&5-FQ}!7nc0Tk$p?~m z2+HHyYKogQQ?uL#LHMemmL{OqO}Nzj?BSxImL{O?n;%Cu55V;B8XA3cTwAMXm;4F% z3u4a08Bn!z)=8yOzKX(nm__{eUXlPXm>SbakXsQMEKd zRi6u9bg_MGuVt9WOPai-A|H3qV4`_$u%D+U?*v-X#|&XzN}61%@x*D1 z1QOu}?<;sbwNAr4W7ESamrwXd-TF_5Jf4x&!zq^!)Y7EX<4fo|iuLgT-)s58@8=vI zFKMzBfJ0k?b)p+yQ}dqJSei~zoV=l+B~AM(VEMu?+;aQ;in(9XWXB78SO+4J1Almp zbkoWbN)vxyrNKGv5U8a|A->mXz3p}kUPJAHCzoqLHK+Fc{AUk56$u8PdQR;DDrtI6S&a)`Sp&Jj@xW_G#R=G- zdd?kWHKKn=c3pTZng1FoQv zrqplpW{eZCx`|zPMb*+o)wCz5$E`GYwfJ#sok+Z0;cmJ(DXyT=O{w36*Wg};S*jOR zOVg({+^O9~HPWO_uggDnZ%X47h;B-iCsL!-V;5AjYUVW>OcJux_A6-YCIYtmgE+_s z-9!g_aO?|r5#bZf7Kt2xjNe0_3-zWn#3yiiIEUZ>Ro}3O{9YsCx=({miewhO<$@}O zHO;I0hJ-A2_7$|G$-Z!2C$_JkB~4cOBqs%AvtJpeBnU#JUg5R4bBjoar)2+v)@QJdAeY5_GFs1XKwP*p@qz=oe^yA7))0=O&F?bC3}tUbrS`r zOjR3I*4`=`sVA1rD+Q+tsu4lgO{hkiQgCV=oqQs9>|xx)p=wgpTE6clTz3VPZsPQ` z0o5FBhw&v5V%P74YG%3=oMMBo8gODcJxqHg64{f+S(F;$D`=!C1*eFtPN30EF-NKC zqA%fsDwCQUY+pEAZ3iL|UpT&dOOy9_o``1IfDKwyrJL9)-tig9JCDr1MYRW%o$-~(N& zg~tQzU9rp)9K7!)G9?4`NBUJ;>yCs&wHzsL)@A1d0rG-C%R`Wb+YiH1&uWI%F~wS6*Pmx$=!O8EMQ$8 ze-*%{k;SV;Vr{%SLiGPYOZ(SRvzg$9@NYpgHCHJKrKuQ@i+#0652wBa*KXx$OY&2w zqrO1hP1(B}%zjl=9g-)m=-EO?AfABe=oQ~1-r_d6KnBJ#dIZvTZ zwV>##dDSu1LHMc~?92tA=2b-^49G>G$(3HQV?Dun6^~2$(aX#IZw0M!P3TtXdJAeU zHf%ww!Cpyn#^Pp606oq=fhJd)r!0s*0*#v%u_M(_@2KD@x9!TcY>_}((>C`o=`VY) zoPN^aY}n;AM;l9cGEbQOMnN^d(IauYbA-wOs?CNADqhj0?y=)5LX}f9Jo5(=_( z9HH7Q{qs(mXP_pRYxv~93^L7g*t=qRZ*>O z@`9Vpz&~|UL93f$t)XH~=5SHa>ZVw0I(G8_TmKC-yS=bv-AyW(d<`vWN==i~_OQI8 zs8%<{T4NJT9{zn*(CVgGYaHnK8<77Mw7MzQS{?Bl&~_Cl^+BbZbOaNRP><{g(fNixW9p?tSm3V3g-9&MbK&2(F9G^wiy9_9dBnCh6 zXjdD5T^2NRPRgr%avsENq>+KEG_~%twbVBus*+A{e zWDXtQTU2#iaXrEsd>8-K0SDnID93LX>TyX0%3WbB=s`FN`tuC>-$eXzN?9Zns8}gK zl8$4GN|}CXsY=_Fw10W3dm4<-BvkhvAvhTm>PXh6{Rdn3EYIcbv^VmIdy9< zO+K@Yn}2o_!7(>@S2es{wm9jD)r zQ7|NsXm#5rdjpl;N4m&lNBg?iH@l@O` zTEOp*_fL8lL6c(rj7LERMq|!YOC&Ots&2<>in-XZMYTjC2_Z7zfyTRXgyx_Lp0Y@| z${RQT?BTEaa^tbpcI`<0~FO+>u9!{$CAFjH8RX z{GE>&C#FusOdLUD-=|vWRkEUgntWK-DKwidEtW|uJpd-&2S3+fLG4j@wnQi#5Os6 zrEYJ1IhC}pb46L1rI24R`&D>_Ra3P=K#dgJw?}M2tD9^#{7V6;BeEJy&^1)mtqiL! zub|aUwm7KqIgsJXT+o7lWuqUbix3a5m~?KijTI{G55~3f5x;D~;D8_Wa3wv&KeY}{ zNE3fwRfDUWZ2YWkKEDC^U!WBnuZlZ(f%5S0tAdtDI0u)6slnh>DkG)Wb^;_!NyGgn z$^VLK@oKw?QWt}6qWq`Fb+=JT0#4fW1yyn$0#z$HfKQiK(CQ|C-xTQ|h(zseNUV!| zBZY(q(ry0@L`#Hf0u|YjOv>xuUyh+E z{X`<6Vej$p0$F~rs;rV6f3;u{8ygRxKhsAauSEz#!aA=-$c=C@k+7f$0by4{q27%XzAgo zLD%^Lnh|?|3t9>$A$%PS167-FC#sd-R0ZYYs;+ua8#Yu^MiK&+d7VnPs2)DQg4V=g zlZ!1C?%|_I2AVRG6nd~Uu`lA$Jg6RpqoBo>?I!B6nQG!gM_yeddlB$B=#;B<({gfz zvai?#;=EI)5zwQmNrUk$1?nEwe)R=)Q%+QU@ET9KZP}NxJzxKt>MHNBsZcf~+YBMo z=rEeW7BoFvTc|JUUKTXsPmk&47m4fzjWkta-p6rB^iJj+X^FMLS3O)?fhwRB&~_DQ z1)!>G)TjMNM`Tg0oF5%s$A<;;gwU{ z1GQQ!J1C&-s-UiCif7y7deXjmK|$r)LJ)0ByqrGpr_kax!Ld{MuxHT9zF~)go}dnu zE|0(a>_Q`Je~yk!TMu8PT1adCl!J_dZzfR_yzgxnMK#O(pIQTE4mlt>fa`IG23M{$ zY50CF3d6Vdi-KlqCS6<4{qwS2cl=w>#7jvt)&t~o>hkzo&{!~J#_BnoFuFYc7Bm)2 zRmhS-aK!QdK+A$5Nl%ZeUby~WzXh#s+D%=a%X#Sq+Aa%P-L&83k+)+EKW`{#byMt| z+LsZ~iE4FIj30%mk2wAxs;SFGB@1^`9i(srsRS{Da||65Q=(}GHwQr|*vF+>*yl{77= z*6N(%>LC_Hzk#~=2T-r=Sq)C0@`W#`o?l0Hipue~s7jg^RN5b7N^dzLIhN#cYdtPQ zkLwse7v%;6b=LBNx?8g;^@6H%eiqcN#LIia>^F+4?BNBqL4dz?0F^zwpc+>WyqZ9( zn_@TVjKwFU(_m*BK{a;MYrgs;x}aJ%EU3FFJ4=tq8do0*xuEW*i()-RRj#T9bvIqq z3ooc#RY0BJ#0h|Iz_G>qu&u|nqheiKnqDpx%rIGgLR758rzZW}$v7q^MkJy4%H|?Xn zpfOS}pe0R?NxtaZ!6T0Uhbmc<<~1r`=iOaH<-Mevq6Tw3>Iqy_mGQNpRt?HDIstz* zxW+ZEr8*_xhz`{+?QMW+?54O+kI3pK&Y*EO#cn!znev9Bs#Wu%YF zDObkN_F?e2LwxJnpL&i+3c3Aimz(u?$#5oBQoc`^Gqhwl$!AF?IK82$)~B8nwXgKp z5nE6#xM{qtH4fE~;dVs61nPw61@%huD(S&J>=UsU)XMj2tsbZjnpjYcD>+K{4aWBI z_nMk2lpCBt6^!y z431AHgsLnUc2p!hc>#?c{-<5?Y`dC_>s!nai6mtcUY+Z4Bw8ZjeOEMC(;KN=M-O=3 z5MJ5L>~4}lz;Ra>J-mr1l-DkY3Y8oJ1^GbSt9AwOP;wn zW~iW9as1n-lLd`gaU@$%rO?oV-IiI<3%kj@x)kbynpfoyA4&56P<6V{f?6YNOy0;x{1wD`?iQ|NN1X7%N>9%zhQ9 zqexJ-Hw5c)>+E&Y-M(Q9s-VnzN)1NYZ4>;ud1!h;6{lNIZJqZpO#L|}K6Iq&JQ$#! zBvBKAswpR4oy@YJY8$ndJ$gq~;|4P|+6o7}znKNMprq^VH;+`&;00CNm|rykr>5B% znr@<$nW(Ck1+ERxVJE21_F7M=ZKxd$4#$u0m@`!Imj!h~TahHC^)%9Q?;J^m!*Fe>j6VoCXTR?O@rU7n>1a$AVMD31Orac>ZZL+1`c>_ z0EB8Lq9c^4)Pv(W2X~OE?yji~$G>SXDRqHr2q{pPn}2o_`{n$UmxF9XbvGSTJwg?) zcc422Gb>T~NhV2~^K>aJbrj1+4~qQlmhmdh7z~M1Ym3ujk2w z8w`%cbwSliHr?tiS5!+RcCJ?-^uik=L8LUYRW6;g(|G4oIFZ|LL?p>g)?BRcj2jyOngo!MJj?PoQcg zdy}`DCz}1ek~|)$NO4@opI?qOKANenrNSveDYj2^>+#GvZ&_VkRAet`d~4W2qEWfe zx~1QO7O$B~D>q9J{RZkH5r{;l(mF^@5d9W3Dx9xWf7g7i|JQFpRU~3j6|bDH?za@` zaaqv#B~k{2ngn{w5&04*YSSWN$0t^W1nUY~4fg!X_djSb$E}&F*I*8}oM@7(mB&?v zgKl!)P&4h%PrabkV0$kyU?$MGs@}YO!$!Ure^P$TD{5-zjgRhra47g*P(4pkM!n_K zQRbCXJp=U~7m7ehC7+>MP*Bg*!SSkR%J#7nX1}o;%`8Fx#q&cAYdwFlPqLtKF321O zf00&F(0G27T)LpU2TiT0-#}s2d?#Ra+G-wbK@(T6dZwB=gYZ>B|J7C^I&kO%JUZHxFC~`lG=8dP;30Lsgx9!7CQh_Syy2^Q>tHy2;xP7gW0GRW*%X|2qZ1 z++eNYi%`Oy8+GSK-HkThin27U=OAej9s4Q5>=12@|gDF!xZFgxcA-Az9HO`J1% zB6p(t9`{Yoi@iE|Dh(z$5UTE`Ix+W1y`b@ieAqwCAsza3kH}0{n4qC*BN$iGfY(|z zr>^bWMR}Dp*e53=O|~hiH9ZgsS3dyiNfJlSy+N>MW(%Sn&}3~6sD8#;Q#b|p%|&Kl zc&+(0ehju*3}pB-#*eCpL6t)!P6K)pM9L>wnmjdM9UqkjSANrn-94O8H28A9N`^f( zbJoD$g6PltEA#8G3YdTECPNAOdR&vFL`VJEO@U^0RizavKs z%kawuuWs;bX7$f3^Di=ai|UX4!+HsAtQ?+WivukWJjI#y906Ee9)An^QB*anlgR$} zoMT?!;tT)uTAfM94fvZX4kr&z)Wc?zX{ztNq&L&om(*?Ao$z}+fShuDear{42DX{7Wm-GG@ zCeAzdh&LZy*%H;tj|*#UV`V{;@>V4-FHR`(@|2SLQERp($SVAsS5qYrVqOy*ClNH< z{k{rSS9qrJwk4>N;UWGFq=&bcuE%2!QxQGS{Y}+SS9s<%j;k+IFK_vM6{;*t%xkUa z%Od%Wd~rGi6*j$ot@C!Sd~4h1wHg_(bd|BYIM_5)+28I4#|-)O3gXaQde~G6Tn1`| zq{N*Q@E0^5_$t&{Ti1{1qFTIq`S^Nq8k4iU$nEstRH05Hc}Hsce?haR>jU_*ElCjl z7BtRBg0=dLr5VD)ju0teu*vvaA6Q^ucAF970J|8A>PHS6~=?*{wEDCzeMF% zkj&MO_w}y(7FG4@y4Leo%lv}I=L^;3Wacfb^ ztp4SkIx6rDy6L?J$B90K82_9&LiHmWF}c;G3l4g?LIz(pLx>X&y6Gbt@ymV;5w4UG#nnh^Jc5tBIK$^-7!H>UF;Z#0d zp6G^ZMH^C;kqGynhF(Fly2|v%`FMkIEn9*!C)8l}MV(r@-w4&RB~l*|=^P9WMVmZ0 z&LLob!a#<f+SA>mx#-uI-{Y4A_YueK#PXl5|3wRtLK0C2kxx~Vo#CFhD#>-?4n~ zL7tf0ZxpZbhJ0HN*o|^8h~GZM^_6Xe=Jg_U8>(!Nkqi?&+Z)Ad@LmwV+4c~qrmGK~ zpzws@P%W3nway;gOHFG!Km~Xz}WFz>kX)iUK7= v)7@k___)|7S98h|V(sZ%W3mJ`(~ zl2?)wpZ)7^|9YO^eAD0b5QwX8ZIFru0zdSxyQjNndcN1c{L2^L{mZ}n%P;8v|9t%) z;eiWe<$JTkKTgg@`{T2{CkHEu*#O-8)wj>Td-3XdF9!Dd>+9?EB>-3O<9E-#e)&B8 zxdq&O^5WII{#MW9{xsP55BiQ@EaAU$i{ip=MB?Xhr^W%=BL}c;ivW;OK_fK)aGy_Mgg$6CyT@V{_`Jc zuwM1DqYfR4VSmp`XhlC_pCx!7wFi>{Hxo}b0tFJTe)sa(pU?Iudruy=MF8+V)DIx~ zBzggG=gsqH-=6*T`CnhZ`OlRL{q3F2?cvVWV25D<{Pu@eZ(scR)$?!J6A}7z|HaGK zul`KI{Oy~@NP7u)|NiF1yXPs#_Mi_0D0bM)7?qLz+n(oxP2WCy_sr0-6@PyI?(Cb_ zfBoyTSKkIJ)=k_1z{*FU&!@Aq{n32X`^}rTXV2bbG>3BT1qs(juipOs`5P~NyN~*3 zUjY1ytuUxm{BN26Rog#KfEn&H((vp5eD~awY;AiIP;9(?_w3z^Z+hSS<=LB_0|#Hh zFTcS!Fx_y_d;Q&aZv!VJeE8zki+5i9=C&DUs|5h}*$SXi8-gGU&-?=kH}T__ub)K& zvC**NQ%?a@Ee%`I5Wl(As3O6N^N5F0knq8qA6|JsZ4bBcxqkt0kF6k7&Hz^O`{&R9 zCyChY@9u7HZEQtV(oh&z1CnwY?{^vtdI%eF?yA zM-c;i(NgWb(c_s;LJaKL#S$pqk3{!36D0t+lhL8S*)ydowPGs~AX>52+alTYVhNFQ z-4bG8&sLe16{!dS?&hr6>h)O*04~E1M<=6P)Egxop!eT#r=6jYL?6Df?^G0@ zLfZ`IAoIZJ+1`}feShIli#~x4|iz3CnycMJsk$69Rb#OGAJ!i5lLDdC3X`NPbR#>aFOa5Uh|$6E&a%XV&RtlIeJjl04i1BtPaq zRaO)!?&kwWB25$tR-F7kJ8c1AtRO)0<60{^C?qQc(nJv`$&=dQn$?E`# z09`~CDL&1Qg+!Vt;l~2_c5X)z1wis+{u2_4C5R)ci$WL+i8N7!b%3iUU(F|vGt(LX zT%!yi`8oZmvVv!vE(#&LCDKF zD@@oQpFTO7wG-T%d1wI1@0DXwr1*K>3W+q)0!nfTn$0ueL|+2HIuHN@(P(EOOf?oo z3L(2CQV>V4SjjV5Pqspel|)35KmelOnzt$|oF7CAVJsxlL<_d!XDjlG6MzrX;f{p> zaPhlmFW=_2jHBFOWkD<<+MCPNOtHZ3;+oxE%#y&0#djCi?CxTLVv*g&HM_f5pjc#g@oLyN zY>x;WwfOGhd+`C7lmrxuAEvn$9X?7KIP4cc*!0n8-)`-Vj*jTaSYx9RR($L>i&7vR z(#{TG<3mWG%|oJ~#lzFdG-Y5bK50+{AdbXF`_2u);SW$;XNvh`dVKhJl$rrRlOhK8 znnwYG+~^%7++d0)j}O0`OlK(v0MQmGncDy=Tm=d5#V$_A8vr^Q^^VR82m?l+`4<4! z_)Fu#Q~>-D+^56YXOQxe6``Xb8(Uku+x^W!bjZm6B7Fmj|Cf&?HN|}H zXpK~JBsH*{efOH|e)&>+bn@z%bED92UU$hGfI(F#S&ZsC_PBpGxFMk!)t^`iA+XxP z9h6Gnfub1ppXMnV(Vq$qe}keJw6`KZIH&JVtq@2kX4b#9lnio0MG9&)-+|(TW-v8^ zniJu{tFaWjz_mIKCz_5iqg^7!ZvkkC($^3az6+;q7afI$WTtEaDD ziVJH1ycGb_d^}oT4?9W#y#LLcZ_d8?=Eb{rI3X=D1%Qw3IT%k*ru)4H_)q?vHi8K+ zNVtk$^|vze=}Q1U^0E!8AsB$W+$}mqS1t^<~hCO3bAytv{+J{boL z8pdMryl@oaxhRY01ufOaXFt5%pB!b*4u%!}?C1#C+oY4DkF1$D4(W8b5l)uvZ*6bU z2H@6u*gA)V>%8c-sPtT506w4-eg-?k;g5Wlc5*-(0DmS)6G-3C3xJDn-u~^|er6mT z;P&@FeEsspHxGLDTvf(Dh|VOrP3BP-)Ta}R=Ccd^o#AGGW4LRJ5GXFsCSRP5M>BEu zzn4%r`~%FtY=w&A_6XTaOSUxv7 zWD+f)gOr;FU(!P5Y7Uszxw^*F;&d={)GCTNHxna^x!HG2R-?>6dL3-8sdaGpCF#Jf z-Vmk~wjz_88;)FMrpwKiiSQdF2)Sw8tfR2GrlxRsHbh17eq##BVAEZGah^4du_CvIktzJ_AFW}$ z5-_u|hRMs3{lr#WMUAGjmqzpUiDnG=IEjaVcl}%k153C|tHBZdY&MNoF?3ZReh4d| z!=O?Ji+@l){;AVp@pV+uOw-cR!M`Ny*njXttAL;dCOkVDfFi{?mnczVUZl9!98H(L zW;mhbXJP3sjyjv1{SPE8p1i0qmK^Cj>~C)m2mNgmEKE^qK<;I&u;~j4MT*FioW2bu zAmQh}0TETry2yM833QOsbLvCf< zrNcmzyE+}tnY>XORW$Q{;s-iBV1kMrVTMHhFZ|F85hXgbTf*XbftYmUAu(t(5X4Zj z*qGnXTjA$5*#bvV)FB>=D07UKQ1VlsIHD~bYCyso;(2{NSBQ-t(j6^>k9M>^CQptZ z%_ek$HqD>Bi)jL4ux0OU(4hjm+UStWT>2%H%<9np2k4N?+%6pk{{S6?Hc9luaH%?c z(i%;d-;C{9Dpz8CX(e{Pv4{(Zk>G+-Gn|O1OaZA-g_C#T1Ap=4KIEM<8z2wk9;uki7wL5IqvdtX|* zFQP-`N~|xf#1_$^awXQ6R$}MVAub?Bf(uH`aAGtw1*Ae1NLcO)WFsmd8}<%zaRj#C zvkvE2ffzH-RY1|5X&1=qIO7_vQP;+)egKE#4TZqQIRS z_a06UvLuj@deYrQ8Uc2kN3!HkCtSz8qk-~eD_a+i0Afa*CF0ZQWC(f+PIL8KCkGaJ=DAL4ncz>k$ zCIum#3Bo&i(wq(OqC$SyHDC%C;Z8v^XcJnT4)*IPne<0u;?cB z5&VI&t;TTE&%n@#Io{WU4#lWWPh~ez9bL#)q`*#2tb>m^&E_KeAv)e23vxkOkOMOp zk4eOXBM(8@H^=Omq7;+S@opywOQxujk)q-Y6h$54v52D9XbB17c(+rbWs9hR30gEk zxZI`{u=pJ)e&L!RUr_n#9O7{&$agTX1iHn<7_-I94X|HzTMDZ~cIuXO;C*$gL+7?O ztSIV$=N;H{2HLKGgnw)KAv(nXYS=&X-cad4*ZYT~w5b-5@LyXxG>%e23;#h|k7^xS z1JbR79}uTQW>l(mXl)^O>%c8j><8bt1b^4@k zV%jJvT7ej@w4xQV1qy^{B}FSD3lxaJN{Y;$b>~>%QqxL`%*g?r6gVxok|J~LzmozB zp-PI(k=jlQY^+sMWDdl3QeZWyqQFJRCNDAvS|K5`Kk4xFZRu63Lp%Swb)*)Q(-lFy&sK&ysNZaE8 zF_4g575l{pt&ls1M5V(;%FWq4GxIwg{N|xwnVYQ+%>1)CP+c#b4%{Ag=#XAQ&UiAxx+u#U1lT3ZQ7X!jRUO9v(F zpDDZfTcrbb)wmJ!Eqm07K|-|6(r(xQSbQ}IOGq{rlxN3>(KgkjRmZ?LgOm*tu7M#n}p*>x6kA+*2 zE>nm0bkVJYTe2=whx4v!m#M>f7ro2W;k>KjW$JL=W%J@XMC-|R+l<^?d|ka%CEJy> zTS@K0d#OscOKrE3evx1&kK8|yuv8`6wYXc!&UK>Ich>+O_>sJ=w12-AZZ~ z|BEa6i~Jgf9#X4W#K4Mw3kN{Yu^57cOLU{J>GMCoZ7(M2OQx_l>ipa5m-Hmhm(Qbv zF1+IESphc2l7ArK3L%bPym|BbO@;)3?M{kxi3dU>&Tuis`1>E`FaG-cO}k1OD?YW3 z8lOIyA0E?Pu)iElXFdO`MC0TuTJ1Q5^umeiw4kf#@ z$Qe*{)avZyK-%G83Ad6q3V3gZ%2BHa(@Ez36=5t=3gGJ~*ir3yKTzZxHFPIqgoMl7>v-31yMAfU|`g@|AmrmiUaQ_9mNfoI4c+0nF9*9|KM;97yyeO_x}j8 zagcntI~)wx*Td~?Njy`Oj{D!RCC@3@IN%QnMGDRf(t$1nY%2i?cg&7nUR3~A=k$yK zDgOaTqZ;@J?$JsBT%VuXA_g4>yE{AXTlx}!mDBtkHt8z^NaKOEaO3_RRv$N}#d7*M3R>2+`c5h(#3 z+$lF6#|cCZi*zNJ@PdTJ3kU}5k&hUvAcJVjk||0B`*EgNJRV9E*Db(#p`iqHxNGAfD~Od` zJRTss5f7VTW(9>h9;}j?cqmca^Z@6HouCACu<_twE*==gexOj1VwR)YpUY}1jZ1FHqd^Jv~Lutf7Hhf#h$%&9WgO(ZO5Oqjv=b=xd!0vAqV-x884@oF*M4gwe!a7v}{{@Ec~A2!Ia`U%h+&=FJb^ zzZ<{);nlmQCII*o190$>=B_5b$=Lo&rNet<4)%2pUmZXC-%SlnX88jgW)CQaw<%kn z=yWifNr$hV%$~O%MFt6p4l%sN*#1DJLkKwxmI*mOT9D8Rxy+!px!os_@P2da&wXY7 z1)#X~_d#>dt~p$g@DuFpz3(<2*E74;&|x5KCO7k@A;q|W{|gCM{FhA&J-|KW%Ps=E zWZj-JD7+Q@rC7mISUvNf2E|}06f7m7@Q#wU#8r+8?O`MyZyRGVSY#~3opDfnFnjmx zjo%Yb4j=%q;hy2u1b+VOaQpx+{vFNLzoVY*ceD%p-$O6QV=;U8`g_+5dqH`&;9%bfOk|5*ycGr{$1P+LBh?( zFHNEK0}p_AR0h~$pygYGfg`Fp+)3m%tY{2(Ka$Sr)-l{oiX?Jnia|ud>DEEw2knCZBnm6kr*LUbQ_USBthG>1CA1cwqr2TpiL;6c63m5*pX5+@}jTJ z3kPfuNhU8E6ay`V14a}!t}+yj)az?g&jKR`6Ia>PYfucd6c!j!7$dS2cl_}@dXVx6 zCkGzVO~GwLf#LqtmBBoa5M3`wxI!1#_lJ<{D^vIhQ_yPJtgFoNpW>@{6u2l8ueLX zMZhZ5YllZilZW&~YptUqyn+TwUU@Q`O#4{^W5uV5 z6&|l3uuC=kWKc=L_&SQ3)PqWlucN3*Jy6u89*@OlrK1>MXT??}1>@@|wks(ZUq`W1 zNx}F!irq>I#;Yl=aw@IoIgp!ajS6@T2P7B@A-zQk#@A5@=`B*I(;E`5;SM)aH3uM_ zk|Mmq3`a4jq;Pm8#g(r}zAzL#U!;}R;}rz9(&8t=P>2-jpB@-kHkJnScioMK0 zNE9Bgr+`*96dtdoxVBFW<45`BKgJ?$VIsVO0}?C+MS5lfQl?;h9R=0SDhkHeQBduy zqF{U-1=Y?f3dYw_Q0=UuV7!vzy~6<-v3{;Zad!VASq;YcG6w?2QVc373|>d^{%mY2 z?KtBq=#Z{y8~7pzB!Ge|X9Y#Tt10T{3u`rdR!tG=zhc&NR@YIm6}d{-H5QDov!a56 zt*)S$j7N{xDKm0Wo3o;U*I9v|U_+{g!sGQ6utMu7XGNu>pj8cp$E&R1EwB7+VOAiy zEidhC5p8+pXA7A^J6l8)`Po9I(9RYSMSixBDYUaiL{YOXk2Ox+w)~}|FAp+hoN6$= zkb3D6F^ez85({7nmyVuPQW$&%#e1iR6FPB}j^2DZ*-r{>c4Ce3Wght9GS0A-JO#kd zleydB%i`fGNcfOO@9go(oQ@gnx0nD(w;vOHfe8|BL`TZMJfj1s?r=JN$2#2498$MH zKngEV6i;1FFFWE>m)+BSA>q#cKRTzj;=v9UGS9fXrzFMfGE%0C2zehmpJ z1>@a?i8=~s)jYw3CUgVH&!xu>nfEMmyS<}ki4uA}|AZcs7pWB%AMPz*j3`j_D=C1lptyWI-kY7$Bb0N4 z0YCW5E9`JPJo`%JC?1QlVANQ@b6=ag`RUxMQDt&lRS4p{u(ZHwcREcg~&+-{dKxkRyQglT!i`J~3C( zbjiv4h(CpdOXH)_Z1(sh7f@_wnim#tu2hADTl~r4emo(qyNlTXxO_UA&gXwP&0diY zKpM0T&m1a>+p!KVo}3bp;2xG5<7_-R7@?#WB+1zV!c9jW27Bo56vPyz zD`D@rGx0HI*5m$SSQUjItSFwm5|D7;L{yim-l+B)NVwvoF%we&BzKSWaK60B|J4?5 zK7j<}Ca=)QirIz1`p(wQ`sTo%bPIrq>ciH0mqh@O+>bOew`booRQQidhl^8Ms^v8> zGfsM)8sicr^vjI9=<>v_9~9@=t^H z!GCD2Kq2)3LwD0?L=3EO4_u3J2@LiKFGyHJ)e`EcS&=3yF@v{P{6oSmeB$b;RncD? z4Zso#X^G-?1n_=xNSJ!QwiaDgiTXA?=bQd5J!U1db@Ff&lQDizrjG169ww?T~LNA}d@S-P&>&FMz_u z0}8E+2afE}iv)jD&%eydLi!P=_9G9x&iuZufwJ*331k;}0jfN^SukItd2YbK}J7z|3o` z!`WbGIBYjl05o?n46tXUv5@ZnBoyt&7Jyq$$)L+d&s`;!NNCr5LBgORVdd~3cS(X# z9uj_INAsIE&;R`5EuGy@*C*JU`u*_g?TbIZdj2hrPxeSo#$rfVIh-tsVj@wj;)K1- zw9Ohp2Y&?zfW2pL|N8kad*8f#^G%QbJpSdcGn&UALBcAIx~eDuv=ncjzpJ5`Oy}Z_ z51LjGFt%cU@1fQTEyaGIU@O!VYm?E@(TQ+_7g*tMqi2BD4)aHGC^-FBC;NxuP3}P9 z>jQv}fZnor0M;h6`N?T=-6nm`ucnd=bTar4osw(EI6td-d75KjD|~hvU~m1$_4RdE zhgeDeqMg`Y$)*HKY)Ej|tp*9g#vA}m2}2{n^-)1WyF3XxPP?8%W2{fAfbRAp1oI^sC7XXp~@$(1XEvpbqErK`qGxb^(9n?AVH`v zZ3$dod~vX@zKDpDf)X)#Gm6PR2c@qLhJqzXLD`bPLFubQBtZ(wmIMT4s1A_?DJWYK z5R{=hL=vQ+Y)L>+M&*H%m;E3GWlI8rGAa)&;Ulx?$0f99*zj%C8c4Y7#v%pMcSZ+V zm-nTxhJ=sa{pa`3zkU84FW?!BpV}7y7wN-c*H~P45?;Q3^=F6~y5$G`+DX{z^5mU{ z1Se+8R2fKEGe=+KO8c>s(CA0ZudFQ{|9A??P5?e>QLv)mhz%BKJcZ;40Dh6D@I2Nd z9Tb=NZbyO{pt$8I%x#e@+)4z%ND#CHz`L5&`u6n?U(>zaSx&clh655-XY zb8~xXI$ZnNO32>StMKG?yW8v&dpj&A*-=;hH#X&CDUeV+*6cR4y`b%#=7x5WV(owZ z@a)?&q0T`Ef0w+*oMnFXAgr)s)uZ=~h}s!$WUHLfL8x;D9r{bsA&e$z85zKDp+h>F z4Hy7LSFe!M@@oV7H6)~?NfbT$4Sho|9YyKBtk?Z0zWvMVH}9H9tyL7kQQPgPg@ljH zVF@3S4HN(u_eO{F+;K%`=4Wp9Z%OL$Pl1zPp!g~0?w$1z)jPKDbvg(!ZAMe9QT20o zmkvMG+})+aPc?UU>F`s{-Ca8TRC9Ni4nNi0-KE1%HFtOE(7A&l=H^cI`k_mQ&OH!O zhux*>Fp}mZ6fseU(Nc8~AJWsQL-eSg?&-kySzTi>K9?WHOZ9_v-ca|tdVi@pNHcS{ z4$*UTmM|9LBX&CDA$rixf;xmn4n<5V3p%t`gE0&MzZ!H)f>;Uw)oXjwL|EHP6hGzK zo}NkU*Y-{ynE6w#?Yngl)Was&`5qE{h3VEoSO*n!7*_T;k`5uN3DLB{ ztVq+SZor^qIjU=W9HJ0<92Z5gqR?UO>;HWByuM>Kzw%GoiKRB)H%4=Nx1Wz{mL{z3 z<b3G@eaNJp~)1E4&bq_8wAGDX_45=D=GW32(l-x}bxmW!38-lGFWmW6Yc|MHjhyGI65B+nkANosOKlIPFe&{cC{m?(x`k}wn^+W$$>xceQ z*AM-3tsnYJT|ac5StRGhQr8dtbFClxOI<(o&$WK&FLnLUKiB%9ztr_Z|6J>b{!-Tu z{d27!`b%9u^v|_^=r48s&_CDup}*AiL;qashyGI65B+nkANosMKfFh0vxMD&WUB%z z5cl}qcoV_H0J!GAF*^$WOS}P~xZ~}vbN7O1pTci>t0;bg9q(utrH{?Q)-K9Vu;Z=N zL0AUClZ)?oD|HZ-K?NO@JKjnigk?}chYj7XyHW>X8C1|=bE!HA+b9Jcww9`cuna2b zu)QQ5;wslqH_f3#yUIl{0LoRabOfYb<@$Yp2t-Bk6C42vQN6vfo~?5K_#+@n9jdDw zYd+8&g;DBIUFBGZ;gWQSqMAmFf;4_*qdJDELT-f=?mQCIifW?phk{fTYkz9+@1a8&P2mWL(Lvb4fP@YmXbWR0Iz*#MS|*l2hjxvMU@BLy{Qb?h zb)$)u82yN~(NUC+>(N0sdmM|e&}iO1NktJks=eZb1UlLE#p_qSWQ}G$3c$sqll&cS zfB~SFo{1V(dp-UwfZ_`h*1j4a{r)g}<2FNa$6Xs`fIWIFHosUZBwU&OVMa1ep3E~t z2EZ+Q-vjoe2lMX@#o7_wJnrcCnV%B~60XM*4A}nM0@fbYNHE|;0$pfN2T^4m{1aUb z@bj0y?tT6_pQKC&fPek@=dh07z5Mn6z5e3?y?!0t41rz!=&+k&*SXpNTNE+JzyEuG zt4YKZM<;uKkj`BO;CGI~06+gbtoY_H&)$#)!I-}r$*}?KEo((Lg?H4WLjW5T4UT{R z_nkHmC@$i6!j#4FFmP5d(D=z3(e%+^qs_n)m_nGD+Z2Ni3O5W5XL&1xQq2_o*ouA! zMaE4gFW8E%gYv(PDb^blX}mV{H@N{T?9E&Fv01I;0Ki}0ZLXbUpuY!9BBAYYLBc?i z(2fd0!cdaXZngvo8EbW zlqBfJf+WyAe`vnM>z~y==ZDAbA_YgKojY|0p-2G`ugqI3N&x;*YkNDKpl~bm{{z?d zE~q)GtsfRx+ke1w)^Paa+5YjUaUWoEb9*#BkiNBmE2k4Y^)vr05lFc2j)2(5e0aQj z4hM^p{sRd&j!*U{=8+BkO}f9t&h8)_v;g3o&nmL_(o#`eI{6Z2=1;nTg!JC>7H_U{ z)lnGF=qW6|g5t{f5g7q@wpS=T-05I>yyj|MmQWn5ODB&fvq!>nfU=%6_zE+x(o<*V zhmW6}Jejra1ckps+{R?UYwT2w=Ed0`9*=WwCVG=uNnSAC(W@vf;V1dTGZbk|T6~2k zFXR4rv%^1T4S|yB^9~%IIaF4xag1dNj1}p_tqk6JN=0$g7Z5sMEUh4raNpkb$m7~D z44d$RgvFl}aGlBVoB*TZPIyj$@k8-cw413F{ya2N5K0y)O!D$`0@_MI!d-K8GOsH8 zVfsWkZfJFAJxS!rV;A&B$=gWA>B&)};BQ2=diBxhXx`3il5Z)}2d)9{IiO^b;>zsg zV2%e7=6E0>t&<+_d7zB+(&=Ez`@uA`^OvpF9=~)Q#z)hPzjJ;tIuL$&I&hWCd%*-u zuF4VKXrOX6Q{;`5DZG&?inYmfDlzbArd7`1ts7Mob|rRjl)Le=JXnNZ_F!c-kUi-& zP?^btMc&Coq)b8hig>s-r>6qV4kpvtyuE;clK%P&yMBo93SX+syu9}W^ce++9}?1; z*WpZBBjcTJMom{mk@SNf&}+S zrWogz5N_%snDByx#n%tF966Q{gPo23_RhL}*s2-L;`+gz4(9~X-KuAP2>~UG6nJp%c^&d-sh*;Rh=Yd#40+uwmaNNAePV4hiQSZu6`$ zNT4T~?mc;!#`SuieFebk!E_?DVMd2^T@AbsW);P~rVcKqj1rLWnQdX3I9JY$t^^Za zkg#|}(F6FLqr!mqw}U5(g)}@()d`AX3Q86!qQQz{$|?Z~KR1Q6OI5*1_!ttdjUV-0 z9c!(n07w@(5#EnFgyml>!O2I|^-V)(Cxxxny_{NNAYt*a|72kue%_Yg1Gj7jtoW6U z>b4*k*$1$!=jp?XTr1$&PBDDq}nfikzbc z52EFwkLq&|mXB&LVda8;yrJYTlM>_wspLSy;w9+5%PA&DN*Nor;(N>+zh?f+I+RL~ zf5fLd+XhDDI7xVx-tFV8v%~UgVAK5CaLTINa81(IN_; z7lz6mo$KLEhwMngN8?9lWZlfwy`AW(FYKsGcFQiS29)$mHKRkc!`HL#yEK7>q7J4$ z@Ql+|0}}qtO=_{rd4eL_dZ9AqHBsqsElRzX5|HrgoDP22trGlqP79R|AIzrXGi%L! za@te_5`5=Q*B%e2$9t(fdl2ivV24W>tI$Xy9dp(ljfP~LnOon)9z+=Ytdz}s#;D*r1 z6&W2`@HTJ!iAsm};fJTw(Wy2b8u*wl`(C93=O*i*j0dm7^5P-#Ln}48nEUx6#Dj4g z!Lz0}K2-VPeGG8TSTyhrzT6)w9q8mntAlbZn)n=V{FzFJ$PcQq@G2mUW48Qzl@2!% zV|$Z_XQTc7X}Z$_3BPpp0X1qkFcU@-pQq$v?&rI@vR5~>M zVD^%Hl`8td;AIuqisBk3_#xqk;7&gj`JIHK4mS~GHSv(aFYE`%jK%yhXmij z?<7?EAsLTcJT&}J91m4Ye(3E=_?;D^ABy}=LeUS`?c(2ckvs9~A6DG8eO9(f0N|26 zve_6#@Z$wQ(j7zxLVNZ-Lxul9!ga!#7G-l|V=&m*-sbHQ^9um3_+w!iEdcmeSLIB1 z;Ng(k^M4tE?f`!?sFnn}O@<3ewt{04 zqNRvxNuZ0^eNaLN_QUa4lP~A33uTR?8h$Xqo;^V`^5pSUD}jN%zKcrez}bEL6~4(| z@Eb1IB~Myl&)pOk?6Nxn_SS!N zQ9&r_1qmOVd^tIwoA8}Y9=8}+$@_sK1`>mIk@JDMwk2yslcEXK8Nm|Xx4+C8!GL?t ziU!ac0YA`5eH5{1?lZS<1i;_9F#>uG0Wg<{k{@%oJp{lHw~;`=$cX@aXfN>0dJ2Fr z+~&$o2lRRnMt(uU2aY1=DFDK7TM7e=G?fWV>b-}fR!*~YUIfKmHx@C_nE=2w{vxL# zeF;Dq3s5B*0`ML#*i`8d0~Y#PUqd;9=eGW0HVmvxm^_gv_fNrh9Wm9cTq&o zNzz)8S-cnq!BNp;khB!Jg<_W#(Nm7J6uFgT7e(|CBP~U4so6ylJ)=lVkz0#)QACd* z(o#sz88R`MZZ{oIq9+V#DWt~;Nfglogj5u(lzL)%vxHW5M-Ng{Q;6v;P=xeWQ;6v; zP=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeW zQ;6v;P=xf>QVc4ydk`jXHAQ8159+gfP?_C>`s^N5X7`{zy9broJ*dy_L1lIi>a%-L zncai>>>gBR_n}Wp)qhvwK*X-NX9q9#&@eurj-Ehwgx`lTX?MlpuG3 zM!>aTW?h&4FC^$rJf<^9nosAj@*v@+A*TbC7y7$9+v{7Ko9nKF;kAA70?%9SP?_(A zqEn7l6t>499mr3q5|D7;o=3|Jc~z}RxqsME$NOSH0i~u8rwf51Oc!bjak>yF!gQgg5T^@)B1{)*3URs+D8h81rVytKfg(&7Y6@|> z5GcZQp{5Y03xOg`7itP|x)3PBbfKeIJ>IYE^$72`a*({m>;{FH-Yg+)CkbCqA*Q!L z5zFy=5EUFL1lL5dc6`wWp?L!y%I%bcISG%5=CWp=X$*oMP+v9 zdc6`wWp?L!y%I%bcISG%5=CWp=X$*oMP+v9dc6WgWv{oN>-9<$mD!!^^|~my*E4|7 z!?^YURW9!JBtg06#e4<{OX~IZaf z0%k_No+L;16I-!5pU%W)k7t}@sRn#wsfN*{4^6Y@v>e)#BOn13RS^YzJw?@gK@`o^ zpvsD>`GP2#t3ee-)qFt|&DEfaqH4Y%isouiMNu_h5Jht}sG_KvFNmVK8dOnK%@;(` zTn(xys^$x#Xs!l}6c_0yVzYnms*5Wp;;VPft;q-J#jjQ&eVm zX!i6JmDwGdJv~Kbc86w9O(8aWETO$J56zyQqB6Tfv!|lC6RjWU=9jjUvh4vRxO+cF zxD-}sVHWT8Zdh_Od%L?^gPrZo=H(T|Uhj4|u18BK?uA0L2Q!NlIJStNavw=k6*Lr#i zX*Q53{8~>>ABr+1Bt?~_4E|dY#>qiwVs|r znhhihzt+=HP@greY~=_aw{peQV+tv~QDNHM;xrt$13*V1rME=k(_2p=rME=k(_2p= zrME=k(_2p=rME=k(_2p=rME=k(_2p=rME=k(_2p=rME=k(_2p=rME=k(_2kZ*~(3u zt(+?L#N&2?70p&oM^TyG%~noFQJLM%R!&DzncdA+PDfFh-OW}`M^TyG%~noFQJLM% zR!&DzncdA+PDfFh-OW}`MN!$xO`ENpj-qnzZnkno3LK51MF@8XE2jAf?EwmiyQ^x1 zOJRhPUXZYOE9b1><95U0&c@bo*I%a26s3E^Hd;AjZL^gtQaDGM<93M>&>`^<`abw$Gjc+NWc*-U?~9kSP3GP){Mv77~SD3+gGP*+Qc5Ye7AQG+Rg%el4h{kY)>s!mkDO6w+)V zQTVl>oAU*P=xeW zQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v;P=xeWQ;6v; zP=xf>Qi!b{CvQ8uL#wCGZn4#qDC)Dj?sB~OD71QdD=M=)w0e4q%IprUo}QvIyF;s| zr>M;C(CX<+D-o}x0lL#wBz5L-Q#(9Z7A>gg#e=kCzz=_t5`F_SwT zwM*IqRJpjyE1&WZ~Y6>yE1&WZ~Y6>yE1&WZ~Y6>yE1&WZ~Y6>yE1&WZ~Y6>yE1&WZ~T8g?> zZZyiYa;5C9YvqWdKD+B$Iije~?z%gx5Ji1<*WFo#DC)Dj?#?PiQJ>v)cUB>a`s}W| zvkFnvXLsG5RfwWKyX)?(LKOAcUDwKuMwwQwl-+fARw0VY>_#hRby%@|QfLoQ<)T(j z)Rkbu3lf&o$`LsZh0*Dk{eFLa^Zc!xwIb8XbyC=c7PoROC17S~+>HSoEPeEa#MPhvgha)nbpNH3LRPQMK43isp2nqNrNz5k+%4P*GGZ_K2c69jGX( z7JEd|oDNhJRf|2MXif(zimJsPQ8cFm6-Cuzk0_ecfr_GPu}2im>7Yn)k$xifa>&i} z^hn0L^aemjA*HuO;nQ1BA*HuO;nQ1BA*HuO;nQ1BA*HuO;nQ1BA*HuO;nQ1BA*HuO z;nQ1BA*HuO;nQ1BA*HuO;nQ1BA*HuO;nQ19A@*_tMd;=96qVT>dO1BsWp;;NPES#p z-JzG$Q&eVm=;ibjmDwG7IXy*Xc86Y0Pf?lOp_kKBRAzVR<@6Ml*&TX0HHFyAK|*Hk z4!xY7qB6TfFQ=lw_5QS|uxDTh;!l2kx;o zjzS73)*;>4CzbqS&;WQW3KY_GAyN3npq@gSE+h)S7}Qfp(}hIg7lV2VX}XXo{9;f~ zAx#$&gm610dW3KHdL6096jFL4 z{o7O0Q8;b~fT?mN3MsuM3ZLG33MsuM3ZLG33MsuM3ZLG33MsuM3ZLG33MsuM3ZLG3 z3MsuM3ZLG33MsuM3ZLG33MsuM3ZLF;ippN^DA(&1QcpZ?Cs>i|^-2_#*`4e4N)(mZ zo$K{V6qVVX>-9<$mD!!^^-2_#*`4e4N)(mZo$K{V6qVVX>-9<$mD!!^^$HY~z1~r- z*DFy}&fU3QuYvd4LRS@@jsS?m3?)3yYf|KwuB&<#kDv#?C-Yo{hg7d&0*E34)_-DR43MruS zYuba{alI0SG+js(ele)GLYgil3cncCQ%KW=MBx{MdJ1W}kSP3OP){LE7ZQbE4C*PQ z=|ZCLi$OhwG+js(ele)0kfsZX!Y>AO6c;JG>v}!lU3w#Vxde5k9#cr^4GFDYk0|_B zj-EnFZ;8UEx1K^uZ;8UEx1K^uZ;8UEx1K^uZ;8UEx1K^uZ;8UEx1K^uZ;8UEx1K^u zZ;8UEx1K^uZ;8UEx0<4^*E=}P^m?W2uIu%PqCUIDb2J4Gg^fmD!!? z^@Gg^fmD!!?^@J1QASlLBf)HJtD_(J=8J#deX0N@gRODDPJ zO9%k>+7!S);Eqv6vHIri-@a`<@t#EE#S#(<;2*fdv?_{~(ea_gz!d3|uL10+z0lW_>NGMXQ%;v`u zLpEp$?->lBWW~y8@1%-?@U;}9J;aCuXGgQJ%e&A zPAeTn_*#nbxNSTvwK{t;JC)4H zQ2<{_QJPrOogAK6`?e0MtUxihb<$0Gp-@6Xbis~TPhDMY{|gDrne~VqlU{$lPxsiP zry)0P6<)k$dUWpvYeks!;_Q|wtfP3+YbgOU!>lK&+V+qC1QIUKXOo8mF!+zd8vxR! zn!`VUGXTIEW^Zn%J)`B;uDd;hr|4Hw0RLb^OR+K=RnB^&WY#NMu{Qf3PX!x{AMPXz zPJ_2gPL-oBB9&?yF~&czJ&KBAZEt#7Wre{%Fv}Pf1zSBoOC>cF-!QoOEp`;fiEM7p6ydWocU+DKYb_VMkTidRJFhxZ>>8uD91QLoAE~+u) zEhQk~WB<$rQB}!H^f@H_tYf{&fE!6(#OqB4z>0}|yq#SHAk0-f0&O?a7N+}3mOEEjHvx4xI6vYCPR$5a) z`sU1Hmlxd;HF+xfDH~Cfr@;u_So~}vF4RooqLj~?_pZ{7#Y`l~J8BjPl#W^*PvykOSpj^V6|@48W^SWontFuy47#!S*eTg|Nx251fF1&VXd-PYNVprhzo(+X3PS(>XT_&H+M%n-HKPDqH>w4yr*CcGeF z@t{S(fIN=c4LcM(7R8{AE`4%Vgs6p*MG7}qji_}>Ktfp4imD1u!pH2WX=Tt7z8$pm zVKZnqqUGXpg0@VtaL{&AAZQ&R1g*6bo{WOl;d~$B+#wGJkHxc>FU7SQ09T&8c=c{L z=n<|h2>?VC$fKa$@=rQvii$?eS4k(c#nU6wKp1dHNVgvu?^aSe zipgmm1>@@|_D3$^z@O2cU zQ5^;2>nI)`*HJLOj$%GOsmcq+*HIkL>nIpsN5QRnM|KPAD6_;+1?}Cqh*7O=R53{S zG(5>vEOrDFUXZZ(IttSPlk=QpR2*zaJx*~QbthwmpOc_uk;0c^vyf^k0STY@y+Kh` z!AbZS5>^k_Cy#~EWRN&WcrT_lvNbK*HN&ex^~ra6DwW05GK}QcANRaR2V<6x>^iZN4?&|L!lD!xMcqW35!px z==DI(^XkU>&S0~@v1!|Gj)&sJ8f{QGEBw655{eYglV)B`lz^F`*ArFEy2yM83F!62 z?PdVdVh((+*X!F}&uFp3G>hw^ZvcdMab ze4Q2O-D)TpUq^x7t%ic}brk5`YA6_AN3pD4PtI=J>lpyeNsTIouy6Kyc|imdUXZZ( zlw_uZgMMR98bo!nI3+cEJ!6HRlb~dg!Y58+PO?fsLZjEqt137NA4397NypN@otZb2 z0s_1XC{tl*?xqi$Gtzo=pa&FE%t{o#e&{Kr^`=DOuQAnANGmmo!e3*mr;x5flPLT( zrg{qLDm010Ut_AL$X`NYL$1BZIri6>>M5kF&?GDTHKuwB=_)jd!e3*mr;x5flPLT( zraFp?NIfaNxdgSdyLkyYYE)--Gli7i5`|B12B;{c^p+@mdh02q^p+@mdh02q^p+@m zdh02q^p+@mdh02q^p+@mdh02q^p+@mdh02q^p+@mdh02q^p+@mdaEg_E+MBxZeBvJ z%I>O5$U#w`-Bp*6gQ7mW#mD>zW6`{XT<56D>~3B{uA`{T?&c-rI*Q8dZeBvJqo~a8 z<|X7hipuP6UP7*;sLbx>CFClKs!PZzFPfK->nJMc?&c-rMGCYqq!@Pxq1ChP0a7p8 zesnnB5xOpdV8RO$7Vq`2Hwbdxe%#y`Y;5fgw%j%3Oi^*FiL=7DdS)$GqHvxxtzM!8 zbO_szqN;+E@G&G%BUX27Xy7xwp1rAC-zw?u4ecnTfD+cU$*rM{9|{!GVo;*+(**-m z6w+c)qVS7BJ%uz~NECiCsHc#o3yH!n2K5xubRkjr#h{)-nl2;?zZle0NYjNx;TMB? z3Te8KDEwkjM?sBP-L0V+@6sE|Tg(flkkXqawA#t!*3dc%DZM2MpWb>ar1X|3e0u9C zr1X|3e0u9Cr1X|3e0u9Cr1X|3e0u9Cr1X|3e0u9Cr1X|3e0u9Cr1X|3e0r-XDto=; z*3hcdtL*iTa=l*1+>HWK+3OL$x<*y@dPliluVh7KcISG%5=CWp=X$*oMP+v9dc6`w zWp?L!y%I%bcISG%5=CWp=X$*YMP;v-+!|Vy-Qpu%g&LLX^*XFDy`BM3uh(o3K+)*+ z1VIE7UXZY?UeDZbxxclwGuYi3y33Myp;bJt7oBQC<%~PqT(8$b;Reg}dWjM+Gw$^S zIf9e$F(j;>oQ|c9|LlSjcvoosf|EY9$MuYo8~x~HS5QccL5ad|4eBYR#h^strwcuW zv>22q{9;f~Ax#$&g5cSHPr+imOK%3yepF|6Gli7i5`|B1J%yCs5`|B1J%yCs5`|B1 zJ%yCs5`|B1J%yCs5`|B1J%yCs5`|B1J%yCs5`|B1J%yCs5`|B1J%yCs5`|B1HAPjg zM~U1%u2;w%&^yQ_LVP}FDlpfbDLyy;@gv%B5vl_@H- zyWQ)RDJrwO-RqSpDzm%Y>lG=gdOecXKCV}$sGPgoyS;fDWP86Xi%=qR$~= zIp_S(4^LdPXS7_mw><;J+Wf17Cy#|&f&h?SsABMT#mNBjLnlS?qM?++UNjW0eLzf> zDY{mJISQID!u>#s6gaop>);36x)Oef&TaNM7Z=Xs1QTA6uy|e|CYd}W#^&yheGoHK zl=31vx7l0a69W>86yB3&6NE#~D**}N+-6Z#!AbZS5|)z}(^g*C+h~JgZCaTZ2A||b zC&hB|qD--HUUX6*FFYXRg>fZ38Rdn?`Md}>E+=H}1qsW^3nmYFv9-P(oyuO^8;tV8 zThYpkP736O0|Y-=C17UA3kUOVa;oM$WIuz1)%i)?-XQR9^T2OV(1&(!kZv2hJsj?A zM0Yd=g|q-+3F%4Tz}Hhqn+FnwZ!h##NNFKa`1V3iA+;A0h2K2TQ%LQFMBz6N^b}Hi zAyN3v13iV*UPu&v^FU7_wHFeF-#pM$NbQA0;WrO-6c>?7HG6}Mce#i9z;kz3b~A;P z-Yg+G4+IoGz4a7QdP@{Oz4a7QdP@{Oz4a7QdP@{Oz4a7QdP@{Oz4a7QdP@{Oz4a7Q zdP@{Oz4a7QdP@{Oz4a7QdP@{Oz10*|dxMmE?Y%+zP@cPy-Bo*ojIS;rReOV=sL$@I zy+KgaXLr@!ASmjydr+C(?Y%+bEev;McDMHi%M_K_-QF84Q&eVmdvCBzQJLNCy}=?y z)!raUYwrz~DJtjg_TFG81-JG#anfvz9ASxP=yPfuu^n%&<2os+w_-`v?-K5t~ViL1Do;%k_HpM*l|1 z;rcMT5FQj#KuHvSF&M3B3l!2~P@?eDg`PrM3`!J!y3kWdi$RIPPZxR$X}XXo{9;f~ zAx#$&g%k_FCD=M=)*XxxiDziJ+>y;=fvpd)8l_)B+JJ;)#C@Ql%*XxxiDziJ+ z>lG*}d%an%*DFy}&fU3QuYhn{IF=st!>)F_ z?q1UI1bjXIVcWUQPaxs?grNAzjLEkLo9;o$^rhEfU%0KZpu@h`VZX`P{!6998az3j z<&}Vh&su&UxKo1Owt3@EDs-6E=`amCOk>9OdzB7|hq?4rH%Rz-+YckJ!l=#K{6ww8 zs7{BG*I~3A9S{%Ge`y=~f^{-yGR(LuQ1I3%=VlI~X>bT~>`n}6$dIH>c( zLGZ)Dviv|#a<3T+``~vJDSF$qJN--L2dS; z-RWN{KX7i=>0lq`10CpX%G&%}rNbqXgvT*t0|F9$(W=$%=?zc<@0+a6zf?NF4|M11 ztO}eL?Xj>ox;82-BR8!d@@rDj4}51+>j$?*-*kZeOYH}`g-(qh>>YQY0=>;r`wuI0 zsG2Wut*Kkg9WHCWpi_=({9w;eh9BsyH#z%8 zlhL6tDXIK$!}mBV?Is5j?%8Mbcw7tv;OgY7`SI-G;r>}BfdTl$6>~h}uD{g_cy}&& zDPYi68;ZTd`Rqb}d$T{-qRSWfcTF80wc{3mk0l)**=O5#slf42)Zy}MzRyawH8AmT zKheSAAM`t`xYZ0+6m?h`NvlozH6)}@`60a9TQmR#h1hiq6vxryb#+!8?n{k*o`Ud| zR^SBe5K(kkJ`O1;8J&O~a7`GYq!%PCzEOh%;)a}NI?FwD51eF*(uE0k!vnU06>h5r z5{eWd9!Ll0C#M7?gcGnuRV6Rc=WNCPkx=R_APri=Kd`5v8wvM}qsH^8yNw19=f)29 zwU}Z$7j`EE3c@!dsz|Z;hPN7g-IMP zgZoF!;?@^~ohYg=JvtOsFqxH1?iO!UfRaTDuCz`E7qLzWNQjOd96Owy6&#FE(hCwU z?)_mt=}NscyBY5u3LRU4FJ>2p>$}4ZxpiJ@gf4+NOLBWpd;YVr;zT>em(~U&16IR?0MNIMr$b=Up{A5M!ku73o zxYoC9Zvh>aRm3_dOjKKd^QBV)Iy8!yAV_c{eGCa)VQLPkBOtchx%ucUPN}|oz@De5 zIWYi|w(2QrPHzCkW<5pCNgANosG@Mg&7O3_?Od4|ZpOJv;ym6x+{-FrkD?;BKD1YN zpQnh~pv@GqE{dumWT!!F)M8Nd+{_#5CGQN; z{L$mzb`Y4cc>j3sz*6UNK%h~WR<+d8(EnlE!{;5 zbTN90uK7Zwz-Ek|qHER@DKMgXimtg^q`-Evo}z07B2r-Otf%NYsZXSETVA@n=sKxS zq`>5oI3BGerv%BAUfR}!WSA`Bj{&(x3-Ig!9+W0{z5ZyYM`}r7qrTiJm{N&_O6M-8%UF-VQA)bP#G#w+?Pr=}@62CWRu^t%JR*NS6vVItW#) zTL-@b(4j@eSO{gVTZeGQs;oqX4niI5*1LZk-&Q zr%n!*TPFwSsgr}{)=B9qk8+z|!` z>zFYh;o{NgICnx1{|tciC@tgN5jOy^AB7M3l%0)@;pSFB|AB<%?6N{h94fLZhQ$d}l#W(MR~0#H!;xx8z@ef}3Kw#GAUah762ca!C@1eD z{uB~0+|qs(M^yVXa!b|2FFT}ritF|Vbk&g=YIh6=2&aP-)MXutRR|O+9fXF~DB0UEF`Wm$((q15Xj70R*>r9!FKK`NAG z9ZH2#uY*)5%Q}<_rCtZAP?mKl6-u=Z(#~JGPKFhBZUIA|>2)}Fog6H!PD(p}3O_8Z zPD(p}3LTbKC#9V~g$_%rlhV$gLWiZ*NonU#p~KSZq_p#=&|ztHQrh`b=&-apDee3z zbXZ!Qly?5gIuy76)OAwY`BUhylsb9CZ4UU2plEjhR=Df+9Imm60KmoLleu^kOaK~J zkS+>nXZcq&W&-U-cAS3(g#c zFP|!kHRPt$ctb*Z>9oO{}KD(t}PIOd#c1x|ANKv2NQYR)-)MvNUXo(c{*)8=^B1L_6OKp-! zQJ>vX7bH^DXSdYkNEE)c0YEo*OFfK8Q8jnp^xeTqyFCDfyDHh^+AzBu$^8QfXkkvI zqp$#E)=?+^*ed{V)QM?fw%3PS>pS$sMbG9bgeu6(q#T9wlV3-bDTFF0Qg|)(RtRex zk-}BM3M+&)j!5CEUP}lgbu`@HTx_d0{Ao^oE2?mvrK9(^Ekqq_;@n(z}8}NNkTAanT(&kdNzIj=eL=2hXMG_^B>&&Pr(v06g=EtXT$>w9dyIZ5)$!F0uT4sOBik| zBcXwkJltO|I^0e`LJ$r2*BHBuv-HF5B_t$%xB*yfxV?l7#fST|Q@SVD@W(Ss*VD7+ zMGny6&ab|G{@sgL&wB}wWdT690zU1Zp5$*c0l-~%{-nLEz~ar71pv@RBIEf{-#+Se zFc@yH4+cAS@-`In>2x;FcR^VSgRi0(oenCk0KSTXwaPEWWGn0=m6VPeoenFl0KVRe z{Ay3O!akEtZN)~V6~Nb9k#84eE9_(6)K(nrPabDxO;bQJc>#Qd6_-z^li7H5l)VQn zl=L@7u&L+pe6LNF6;}?XlgZia-;B>aBY0@cz$+5&zX4CjtBt!4TW5_4|o&VUR>@CBp53Ob~+etZto7( z*SGDCH2_y;^OMuFr_<4?GA2E~GA288xHz4RroyubIHJ<)^%(Cwpfi(h6i-h*B3qSa zdc32_dDwrZ(&62A%(XZb1y32B9KcveA0aRom)Ih###D+owPD~!i4Z#36tPa!qq zXX1wr={2MVZ~d$?^D>rKqtmC^n1O`UlMb)<N5x*VhsRV{2v@WY}C>IR(w3`;=+YgN3l>L)ln=|NOcqo71AQb;)S$G z;fmNlu#l>C_y-o!q7I7}(jo=b2bX%jj{4j~Zo0dg1e~j*9!4nX1qq86(wl}nDo%ZW zw91sA(u&mG0ykI@>ZqwvB?{}wxQ+%TV5YsRNtYbSOY}J;T;wKKD5U^23MpL^#CRu^ z0ld*oI@04a?4sEp?q&)k@9Cpio&yrngYpJ%IaCy@*aOcK7&C9gs~~=C+^Op>?0iwO z0u)lIW-~Js?wpKAb zI3y%b@C^HNbhr+?iZ-@{e=2kkB0|!EyGEl!h>ffkS{<+wtMG$cxRDNco2B+2s&u%> z#V4-K9NWc;E@B5j9 zz`y~}am3tEl1Hrs{3LmKiowDZEFlq(KRv~8VG5SeMX|9k1xx6n*j$)`C3I12Elj}@ z1d8aOJniV}4$3o-6z=K&U8wg5%xA%(@*?Z{!yGe$D^+@#eu|wqLrJBudPj8%IVEjj9s)06z#fPM&y z#-=(IbHaxb%2tfN2&K9|+*#jR-`sW69sn!Z<5X6!90lQPDaNBGRaOwboaEzTv|_K`ioHrJ_G+zIMM01Tg99d0Kpw=Ib*mInw*!FcM-p?OaI3+9Yr$;%<^JKI zrL%n{Bg`tup5!W?6@1f>bNw(XZV%lhgDjzVdV@PE7pw^N!{la(!g|uwk5mbmX;*_? za&jKBpFzUfXgr@CjPkw$AYJ?$yv;rUXf$WEt8CjOtEIbC9)OE<6^z8den@A3#=B`* zMPaPitF&UT+6sX|v|_K$is{k*cvf)|m%&$A!3)T|pR!h%1!uH$FAn#eC?0%zZ`**t zXu9P=gmdZbV1$xhkg$a1fhCX9duu)3BQ0jPTOLGKg!G1zl)Ri5B8Bs0oZemuNU+O; zE;*8y=yOO|rEn5*+W;B|#A$f|yq{Sifku-)OVWF57#4e=kkW#6$WXY%GddJ0id|A# zqfF5D&8C*hio3CyK5DIbYtJ)IdCE2 z=6*N=VpNQV2!J&@*IqbsU}G{_4j+p~uodaC1B*8tDl5*L7v}s(6~(RK zNjKWTm5|^L!Umij?f@f{^n!%N^WugfkFsJjoOi(#rMz%UwP1zM3KI`S3L6hx%WYN! zC7{DSb0%tDRRC7Ud*jYCi&}-0@NRv<5p{F^M+$0tqA6$Q)|OkCGXNCQHVgwY6n+~< zPa$nTNEH5TdObzwnMD~Z{Mqz+3gK=+!o0aR-mD)B;ch`9#a10fu|A{=Z!>S&V?l_? zVnkg$p{og{sD*@-g7MA_J%tpt5`~XiJ%tpt5`~XiJ%tpt5`~XiJ%tpt5`~XiJ%tpt z5`~Xi9R-50X1E#e)~qUuTcJ++NzE5ZNN|%{z`04y!w4n4AYloUnjsI9+V+lH>Y4gb z>`>gK7OY4owGxF*|7cQ+lz^FbQp?L>Kg|Cq_8+DcCkrjYyRkH8k`8`<(yrw;-S#9) zSegG(>^}sG(0{n;pqrw&Cze(@#N-3pf9NPECY=sGCcT}_m~=Q7lO84oBz?ZLm;`x< z$u0k|)#{jZRjhM{I0pOg|VsvRF4Hlo?YR(MU+@+JOHaA>Qva4yK zC2X?Ts7}J3@NQBxfHK9&OgJ6a4tKiqPxwj-c2rj>&h_0i^O{p6;D@3WwzP-aOn3=fw@9WSkc6vc~G^z*!N}f&->VVLjPM3$Fys^h*>lq^d40 z?CIQodjNz>*l=t4VPBwFM%Z^#EG6u_DJbk6z=eHqWi#v@&XvpH@t+{zfq=N$Z)`MlxJW;#y1at%Zfy=F%M`p*Cv+H)kZVZ$?ko)z#iiNF zcqDlW64K)r7H>SIqFBREBu_y?+FuyF^^}SNR_s+;0eqzudzDrYzQ&4MA>@30@G%EJ zxYc05x%%K?gpyv6u!IdOLyr0|+}YUK=x=SibLA^ngTaclK9neI;&6RvDFHL>YA`Pc z0MrNZgf{@vm^Aq4$l#61{M24FU{s*HJJavX%TbKGuBFXT5Wa@uoRhmfSOg`DR&afg zJOv54`ruCu)Kf^Fk|?~V)D(M_Rse4XLr+m@#a^8i6!tdcR&4G?F$X2xy~I7P4KwkX z{VyaeULUSAc_DNIyH3AuY8jaY@+j;Vn6s?4?abgl}sc#n82(mu=L&1R2|g0!NW|9_EP z5JEyqVe!!>Nzn@W$^Mi1A8IIoub?<*39<)rRgSt9%=8iCM+*{MW(Ay^vpmcVUFKg% zSi)-1kVlynu3O@mRL@z#iZruI6gH|!2k)n#1kALVm6rp+rOEz7=^SvjB8^Fl4~_Y) zN7M1+1AE_9n_B*`JyTHPRZ&>HNnc1PQmj3i;_CTq)Uy@oR*%6)dxJ%aV%Vn?ymjnO zPEuKMJMyF-Pv=TVa3^U*I2ZR0Mkwh835$pQO-ml)o*udED4C+v1i6zmA}d1NLqd_l z4OSHQK?z8(Cuwx4>Qv7B3kjFzdvt4@N7HOb0g%o(7H`A>aF0JZdo;y;r-HZWoD%vH zfQt;s66Ciy7;gv+ph$5)(ZNNPQNoFm{)Lk6QFVzR8+Ii*ke~}Wx`QXJb=sOh!pAZB z!|BPBQ@4%^XT7w4={|vk)xSJ@`JLct9t$_2#7s11J^aoIlK)+flApxnY^EEop~6n+ z@C&o6){>)h7bL9FHS!}N>e*50hLyov*FeHueA0^g;Re?T09FC$8jHqlS8=Tz;Vpp) z`y$1?rVieXtORuU%q_5Fz41ohU&#?H>phCjoxMI3#=o-9SR z+m4Qy^g+$Ty||JeN8~oBE9``sJrmWboC`WJkU*7|))Yd_0g&9$)ZY!O$L}JyXWv4? zjfpMuGq0DQ71@)d1KmofMhAQ6A<}`~Wr?E?wK~wG)}h0{y3=KaLPENbfQYv7R;vTu zYO6zsbYmYwFm*gy3h7XjII&Lm>nKVm2BcOnzKQ~+Sd3cuA-N^8fn%kCib=n8Z25mx zo-EetUo`_J&CzDwk+Ghgg^Diy^VU2Ho)5+)@`NbdB@aQ3wMp=Zm#sn9_% zw5&t0crhJt&2c_Cp+gdK;fnd5d7I~UpQ`+D$zJ%JRRR)z(F{2YccTIQ9bfKWl@1sA z>d~wQrhp{#g}>Oe$M15y@n>2crW2u~dZv#?Yg`o^(5mRrH+EHDylJ)>J5i1|Il$s|EhFYGnY2xm4JjKdBc?uoKBxtfrB$e5Ln;KUb^A?2yq(HR+eyjsgoa?a;4T|o^ zIuOOV9_!Gc=zgpNQJm|s4h@Q~$2#2IpPdeNhQlAvI4bui2Z!_=ZTol!#KUL5`u6#E zFJ3+G3BXJkMIS-JwfWxJ_~Z#aaP>+1snG!3aTF1-xBg?ena}(Fi~WBH+G;a*Du zfFuK_ascq5m+<7YB?EwuTM`VAWQ0qg2$z3B!WE*xgXaI3d-6R1w;~DyB;l^i0dSQh z>>tiXdq)`&0NjowSfKY4n+Y8zkMjZ;5bI!o)=4DYOPD`S)fya zt#A@(f2F-ckdpu)NeE|PBIH=P+>k;-9C9&`q`0Ucl=OlGI%Gxx^JV@nH2~a*Tn%9G z5`7s-$oFa)2?OsW=oLxG-vA~fVZ%GAA)%eu_}Wl3tT1`q+Ud>JmLTDy$PZ6W8#Wk< zYvb`5ZF(vKCIWhI!py7oi|jrq06u5~Fen1Rhmq*kvxouk0h0h59wl7<1qtudFOT+x zA_IUgqzxbuAR+;{LSN|Wg9myy842&v7e4LNA_EFvA7Y?$6#(yzzBqe)az^)SJv?bu zh=zn1=+pqVnvAl$;sD%q0poyBa09?W-jQJeKkfd}g z698YM5}@}5VdR&k7+DGmjAXYop=bcTvt;@74J42sXgGC#U|?{gm2i#D`V-2iq44n# z0lhb&!&Q7Ct3EWxdO_jqWCZkD01zZ( zroFrbp7uf`_8y6*<>L6!=<&lsLmB}|363h(VKP^C2NAGg#Z~)7xjP6z5@0g}I=pAT zcyfj#{^^JS;FrxYkYsRVM-uk65)6a03r_@qGLA1Z+OT>Opjw$?Y%p`PuO1qMzY#V{?6Xw;uskzL*Ik zWpzl81QFg{Q)HvMOmSFAaad3B|55j*%aJ5UnxK?)o^|l3lQ+R;cTcgWXBKe+D49Pv zGcg1*Q2}HX*p%LstSXS5GR4f=tSmM;KlZuyMfMf;IaWV4Q*$$ORd-V$gd!ajRt6%} z_4`asFEjUW-*ZCj`5|_l5W8N8JI4={4O;ewXlglA93Lpe@-iE6xzXvqeg3&U3}~pY zZHBxcgeGTnx-a+DO&lHvAZm{y`Gn90ap(NZy3dYoD3%wHMngR|e{9Djdxj!;L1-Jr z?N86G>&(I^Y6!^3JF_%~-beXl(M<)4_=g?j`8c^;CC2ln{|6e{E&``Z*v+3dd?4WX zfk>n{jZXn$OOF1COdd5Nig2&o^m7`J9EC`MLmZNwgakCiM~w)AMpd^Ff69jX+<4GB zBp^`71<5Ce3NA<00oP3Nt$>4}w$o4D7~)C){0`$=5G3z}xc%w=$*Er24W}jfgaMKt zjE&;Z)MQh0qXNIpeg<6PJoN{7Imz*1M+WT;!`pDVkkal$o^ zB6%;w@u3fboRX_**;?ek^c4%mgHfr38Ud$ZsbzxtMU1 zSo9w4A85FFwtqi@BZJPDo3q)@Bt0vYBWpC<%Wo&MQKV$g8b%=`1#z;kNnn`qx06Fu zH4DYhpyBqDv*D}$>f#Q0xoIMg;=@n(ce`{SS#HO>KQhGrz7GQO;YaR75E@1yuDJlo zAK^DPid*}3pA}}a%Jw8*Cb7{`e3WyzC0-Xz2|J`NXu#qmX1t)`=5g_Xkjw%j{R)mD z#(qq+*hoEj> z_t-ehI=V?-0xve+qoerrpnpLCY3CQ)p(;rv?}hmMLb+sM0D|Pb5NG?oM}(8SAHp|^ zv;Av~!nd15t-F5|=Hfu@K+g8N6>Sh0^{5*!2FK&#I!oGOy*Uo?#Obso@0<(HQR>AH z6dMS=y0G%^)TD22%2Cw(OA<>3DP=Keko#bCaF0-lz2QqrBiucG49V!45aB zI1LaFeHG{IVO4R)A#Pl8#vyK8amFETTya_;Zdh?zAZ}Q3S|Dy%amFETTye%BZd`H3 zA#Pl8Mj>uqaYiBDPf1J)PL{=xC*@~oNlx}CvSg>#n(*0rD$ctMj)Jq;nJ*U0?fg-X z3^BF{l3S*yQDg;&bM+`hup}3pJ_&G$w@lZmLg4w)5r}nEoKc9ISDaCZn^&Ash?`fO z5r}nEoDqn1RGblrbyS>Th_zIlVF;=?QGo9I#_2rEV#sn`#jzEUnDK&!o3C-G91u7v z&en8$Yiqugoo1jiM0>@Fqfjc&Fht1qTygp&z#&x}O%DX<+~VPpR&8Vy^@$$Hr&TdD z;A|A`bH+6%uvkpx+CqjnIzDwlK;8+lProzvi~{mrh{sL{l6OLUdT`}7Yw>~{E z5!h*a+m8nw0t>WEw~fILQ*A#U9cLI#9(DK0+2Lo_!)2hM-uVym(Ns+k*W7K+P92UK z3g^2eaBjsUk|GBrv-8~|SBoJ^jTbcBJj>B83X|;eT=(dSwk(&O@0L+?c@88;A;gkd zp6f_JLwCL#2r5;>Ncb2U?(vBp!=)flY~0bEZlgSokNZ)FWGP^uOFh_3Kj2`9`#9wI z(XsjyPe2q-8zCUy4#A^1-Mv&Zp*0GUX9Ons-q>;?!!rF&9NLhets^%tWKp5`=mMd9p(vg5+Hg zcR&67z#IlfQFkCgK4L&%)M)`>4#R-xhS3CZFJ4+{hF*2g!|Y1Tjrd-yrv2N*;Vxw$ zy0So}z#diIvnYroXKjSH8glnp6Nh{8IuMlvG}LzJuEp4hhjxhlca0pvS>|RA-AU0bIWQXA^)q8dbt0l6-_>KG;IUqKvIngZvOZHfrd8^KfU_qTDOlQ zr{-pPBWX}T62!G`A6GyO-9GO9?oMQvyQgO->2_tH1P!2 z>1WC|BLvcqOmo4F?B}{~hcC`fPL$s#DH>RCW0L($_5S|Zlcy`=CtA>uemX6J8_WN` zTyBNCkVD}6_~K~w>C?&P=IO)gXWS4-KN&6sH~2!0Qp2KE0}F2OI7$sp4vGdRhct?J z&URN9^b7DQ-RG`%lL(MZcRk7l>F1S)NAx8Gat*y3RahEuql&{rMZ>f%E0zY_Zi8?C zTymJUj)DZC0lOTvhQ?7$XFLjA1yO5g9L1CtGQht!Qsj7@18zUODhEauXMMc zDERU2Z^FF?|MK*^Zx61%e)iXmkJJCYe)-~$8(+Qrj(!FGn~mL#f2Ii9-2CsGC%@VF zKS-wdR-)uL8~<%%CyFfaFM(z+aQIouFb_^1@9mzPtsY-IzWCi)k!iAH%D2$)>of{U zL48f-QTbocaPRoV^VhpyeOdbo%R%7BSAThZ_3FjOpI<)zY9k7Nj6X0S2z>A0bQhmL zfA;nB|6Tt`90I@0H59^04@p@sX!s!=wf}Ik`_)&k_FumE!}CApY$0$_K@`G-^7XUV z&%eIfh`%uXXHxg{;Og7g|3afuzB+&T-K#IJvIzskyMe>rcdx#E-6H{k-}X6V!XHQM zFTN!s{maJl7q6)Y`S#V9Uwr%e>Kpm{tE+GM?+lt0hZi6|2ple6J$v!(AFe7}K;TiI zLn$mYURN|;S2XzV9t}Xmx%m9mvu}E4V1M{O`y4u9!Kab`M@8X30)=QNGDRW4f0LfmD zn|9G8_?T~S=!ae=Eckzu(3^JARFmw7UM4Ig|1*VNuS4OvFhXzY4ZWEs^fKXfhThB* zdbzMn=Ndw9<_Wz@SZLfd^k$yW%Y+60ZxVVlPv~XBLh?UT==JXhI8gOw-q4$SLN60u zXXwp6p_dEGbgm)v=AO{2goVaULvQX0y-Zl}|0ba~_k><1EF}Lkge<)d=8I;I?qB6@UkQ)H zfaHA~b-4fRMWLI%zzYIDsUaXduA7e!8r~F$X9@-&eyTw{YsG+ucLd_WH_u*7s4$V(2xxEMLh)i5(28BzGzWT2eXDWiZ48)VBr=RkQ9&l zMj3?ZQQx#^#~@gPO!qg+AXq?~ZWeBW!6?K~-%Jz?2x!wCgj+BQh^YsHh20P{4+IOl zA?6+k7Is4{JP<7GhFE$aShy7;#05Q5tvxPCxJ5g{B8v+;N*RO^7g4wgrgK_4sy!}5 zxCNttXpakmxJF#iQSEUd!tPPD#|1%LBQEHu_P7vX_bA%qf*`ID7j$hWVHmdHVIs zm&!1D5S_3C;``kw`qKf34Sf`ilMW3T#CGpDjsp-7ZWswP@G2>ocQUOpAkbSSWy0ea zHN?^b0bw`9bkhOB!hVRk2Li%wh?!?DShx+M3q56-gvruFuXULO4V}{}%OnWsanZU= zsvtaZ@x`^`;tNk)1mU*1=tA#{i6bt8up7b?7hhZ}F20yL;vxvUN8yQ!FC1~fh4t+D z)&A>OU-w!mxLmKWM&a=h(80WX_#x^A9rfAOm#;7Chra;g@9TPz3y6tI69_cCc}dqZ{sC#G z)=ytTplIEbaFhP1fom2YIq5HI0ny8onefM>SDHdY2Qllf)oh3$+y=psb@p{X(-S-! zYT8T1Uw@s>t$h9Um#?~ONWcDH&tH7?{LlH&K=K35_UY`y{?{+R{9ox51O)!62T=(R zP75^r@bCr72)WeND>zkBPv7w^30*>3>xR(C{c0~`i{B0qG(i6`Xj7emBH!l?u4L3F|nh&T7Y{nL{d@WlQgcoY)6 z@f>dwZ^Hn|H_xwLAM8CiKGc4S3W0yf9VQ7&Y<=~`AD>^n(wzn7V+cgn(bvzu{dZ#& zMV3p#ZDR-!_fD_=wEyy(zbXJh;Fy295v7FuKZhSV;9P%75An0Z7hjbhoq5Iv0&)%|PF7DG_Of5l@PqsqqL=}MVOIW7iQCGsdTk2B2e7%8eiyN(M#3Pfm_68c> zB*D|?uU@@;)sauK5ZKfq&YzrIJUu;LtsdjSmH{y6Nk`)iG<`6?i^AKW@1`0!Fa{wg4}AKW@1j9=SA!(B?>XaAws)ew3; zL!F;KJ^TD*BOKT#UVH+GdnBpMLXd+%_hYc=QTqhJ6C95$RMvk$!&?Vee?I)vcRC6L z{!2ZIgTv3B9-h(}rPtSDyB%_Xku91rB!;!k~_$f5JiR(Tr5D5Ib z9>wAQ?xTQ_4z*FB;cb>X{o>_cuKE!Ufu5ll;&kuv<>C28cCZcu4ezkj$?mCUEeQN$ zJqnV|1`&_c0b*PPB9AZ56%2J0rzD$U;7=T?gFwUg1mdv+;&BPVhuRQ4-Cro`aR@k! zOgA5@s}~JC-Cx{fy5qq*3`p{He{t>UmLqk5Y`VXYIjd?$!*r)Zb&xdOkh|t|r$cRs zHxKEwtyU{=h(6tCpG#oKp}Km}zz|xk5P`l&6%a<95Kxe0h?&c23kW_`6!!m35cBIp z@S%Ox@=1bNTpxlD6@~qO6U6fR5PWD~wR{pF_MZ*j?xR25bbF_iqr#!0u>Ws@@Oe}L z(d1Dy3ZF+65KSIM5I&D8AeuaiAbcKGKs0$2LHInXfN1h4TruHt+Tyk@MlUPA6+8-8 zOk5wL!K2>64lVY9H572@HUAIJjvwO*?A%HpvhUj&Jr~7;7F-djDjzbuY6gZ4R40cjHiZlAT|M6G$DE_H76z(*0d=PBa z9c&B(5O2p*g(?OFdeeP&e3B)DJOpj$+mh@uS?5x85jCiBbF_CemE45{omZ z{R0hcw+g2dXV1R=x~~HoJ``~31_XO1565PR`uen74+P{9z@i9#lkOGX1d&{hI3zm> z326A)cQ2m5e6b-28r7Ut^&T455*K?}Tr9Td^T~7(p8=dh+$b*EAZ`>FZ4ft#i(v?g zi%x*%yD%jz*~LXCSBX_qoc{?8Yl({h&dwGnF6Z$%fDF+d7u_i8xEO|@xJUxYPC^14 zQd}f4F_TE;hN<5}!yT*!)M7zjLZG{uL}qeF9wfpV7(xw- z0f>noLJf)mh^Ze!4T=GXnIEEm-v-h@05SJN^naf|46*P-^nZst46*b>Y-xpiz))L$ zh;1jtwjW~039;jXxQl3=7~zfRuJ5`WjK}-nAAPxv4gP0JKLE0gv&IB^utP;rhTuhw_WLhVX z1_);YnbrxU0m7L;rgZ{ofN&;|X`MhCAe;$gS|^YO2xoLp{n0&jM)%Yo-BV|DPyNw7 zbw>BpAKf!&bkF?JJ#$9)%oW`zNx|j1l9bXtvRqb@OxLsuQdk6Wy_h)@$gD~rd*v!= zIg5{-%ORWzWL71R76@konNo@dfp8{}S(QLqAe;$gRwa-Y2xkJBRSBd8 z!kIv3RRU>%m^%~5yh5T5BKf0IB z=w7;_8zm{Y9F?Rx-B%^abj^m6v~(trWtBkoWtFtOm~PLv={ZgUno82rnLw6R0%?J8 zCXi*7Kw2Q231nF%kQNAM0$ElGqy@s6K$cYkX@J;rCXlTvfwVw46UbJTKw2Q231q8E zAT1Ei1hQ2nkQNAMbZ_~id&?Q!TmI5A#UTr#Kxru>SaHW|73#4 zchU=PPZtL44?-ZigFqMEDRQdlHWe|P`X6Yx`Bh%;@o8$l#A|13d%3lh^_x7*TVq#w zz29BK89LW=i5C$B$x(=KiAA{du}1OHzv8%`s^^xl~1QB$+_(iW>d4n zAO!5d0^~1Ygc*s_4vL<&*?~6Xaw9L|C4X@?9sUq^_7pn|Ly#SUK(fPTN20KUre}S2 zD2?1bgxu>7aoMTaVGsg#sQjTLQQAS#voyi1xbeh(qUOU7dMzO;%1lb`7B!9?A z6n4<`tj`XGk>{J&j*D0oG&>AJzz(H9WF$&ED0(1p&5K>*rZ_ar+SFv8n}knnau7~yR~NO(ISjPN!gB)lCEMtGYL65b97BfL!r z3Ga4@Yg~yMDysv+8QpXxsvE)?-E<|Y8^RggbS0`A!WrFkC8`_38QpXxsvE)?-E<|Y z8^RggbS0`A!WrFkC8`_38QpXxsu$uKSE9NhoY75JqB-fb3% zoa}Xo7#0%73mUF_C2BE>y#zj;Os3mA^PR11XD>iF69`?2>V|M85V{i84dF~6bS0`A z!kIwmN>n$5Gl9^RsBQ>n0--BW-4M`rYlk15YFhPD^cAL&giDgMBNb1=%&j=y%5*9Ow`rprVf5V+-ttPXCyQ7sS3B}|g5 z#f;?(K2A%RYg{JUjRI$agyb7Llj(eOz8x1ZIfOHT&}E`-2xkJJ%S7D}&ICf2iMk=2 z34|^abwfB42wf)Xg}BCLqHYLh0-?)9-4ME)#V_INJldOw` zrfWFe5YFhPYdGBy&giCVINcD==%#Bp-4M>`rfWDI5O;7*rs1>dDRq|T+gHX;Y_yNU zHJs9D-Ksk+^m5&;6_Q*nhPKamLBo2k;RH!srNzzQ)@Hid58Gk%n!OME+w$GjNg#=9 zI0qrfk|Gf8l#zgj?ix--&wA`Y9JnQi9q7tQx^e4lJ6*)d5M$S}c6La;eQAeL2>i+{ z4v_NCF(Xn}ud_(W`_ji5V|wXiGtK@5`Z^=tl6)r)G;7 zd<-!bdOu1jC>w?N6g1G4hr=W^k948mc=@0;v^x$uR5 zXNNV0KRBpn(8Is8!y3bX&lmpEcw#oz7XEv_@XtA{G5qzJ2t`fn#HPRB{x^=qR+roN zxm@@?3K^P@(_%jR%)>z+C^Yn{UiisK%@t?g=W^1*gT>lhj-Ev8sW>@@^|;)R z(UEqoT58R?SHoQVGV5tOxw56p9H4p&4P4xJFVuq5P~3MfDxKAzoy$>65T3a8#%!^( z+*<6+`FxUaI6u5D2RgC>t^RD{fTnl<RZm6NfiR)5YTl z4^9ph643DX(qN?KKWntYkp*h`M-vC~2c%Ag04alpe&y{r;K&lQ{;QdT&mZz^zczo^ z^Z7&0fsd@mp8wrs2l9tKpFiXr*5(h$YYu?rhkc(v z-C|59h# zZbygmefR^%R=VS#(7>BTPvs$yLT(W*q9`~_Z@>Y^-hji~JeEhN#|j0`_Wv|yhj6S; zfi<+-VWyC1oeLbRlkm;O{01Cw>^e9sZomP@u7kt!1{`qgIyh|IfCG-b0f)B`7bj<@ z3WLxE{ko2etQ(Xgb$oo<^2-^LaOiMj-}fg!q)-!fJr{etH-rp1WHf75zhYO1Ff?U{!pJPit?ZEsUT?hh@g+pSNrkK2%D4H&i2+k zo_~bE^-A+6lkQ~GD8!F)4)pu0f&@5-Pv&x!7)e<#XjsFkA_2#lqDYbMbQwSyV(e6r zJa17H^`EyW-&hdIl68=?*4D})<0;dAt3LB*j*j`&I18?C&bDL0eL6Hr4s`3K8RcA`^IKe zobKZ61D#4G`GgR1)Yx?2+TA_3rh+xp5G3z}7`-c6?NK;~^2rVj5ihv?sMB)jMXydN zO57S6g!QdC6(!~AL3 zW*X9?+lW7fhV|sA^9#vQf#hNXl z{V7}z6HiOPC*k&k5Vv;qXL~2F?xn#4xy22MG(xN+(+-Z}_T~Ahv2CZ-ZYB4 ztMj8LCq@qf4fS47kdGiu5P!F~XI3OO^?Oy5v$vPV&^QTg+1jmJb(k|MeG8E!Mu6=HES`=1sIV!AWE(Xc0u!>wQMpD)b8rD-- z0iG4s#b#`2d6=HUDx>HZ)NH65$!C*C4MUt?*x{`~kh~Y-c;)M9N!|-_aN-*U$vYwbZgpx- z1)I7~gR9dHp=~by?sC@$ak=Y-xOK6*G%>X4CixDd&1p~1^+XQ8*C0sV3vqsN<{Aab zJ0Y&wD!R=Y_)pfo|C z>PZsos$NW#(2!LdC3nGveEXd-XMe&l%nbh z32^ADo~g$$5dIW z(0NoOfl*{0C34B5ge!>|FKAegM**BYYPvPwoXzLyhUE<5@F*EY-=hX0#FD|IDiYw( zd6cQgFcLn7hPxM+M@PqwB}|YHKj2^un9ZZ3i_7Rzf#qyFw48vr&xag7Qp+m@eq43t zBF{+*0;3Rb@ga1A;Y7K72^xN?L9l$vwje#W zSI#6BTHh9 zC|}3sz%Y5Tj06)3N|nR_p(L>Z2p)wei2*`MVgnG@%rMzD?5ID43==t|3=^Favsq*q zgRAWm(6FuyL*SfYW;;9dkl)!d>jp=+n~Dq*N16o82>c894=l` zNkBvO^9lmyYn>##=}-fnKW^eMTC?g6?cVP{`eKS{|P3dhhPP`u)sDp#Cp=@yo)h}>Z-JHYwG#D;w z)SmRJ8aVtUUa2l}ir9c5pyB@U^vh?ft3Q6LO(+CDHZE=yNE&QVpaMa|N5wUZ2Zu+; zj}Fh}B1Z`PLcO>#395>_524{rusK|<9&1?$0zVRnB)GBpmm_*X4+J>$=nA%{Cy&oB zYE=;URj#2FBvtg#!NK3-L&Nuhjgz~zdistz{5*%~1cUl1q=sH;6njt3pVI$-SHtv1 zQ3?{wB!70If&~p|o1fAtho_GoK3Xh6{ zVF0Zj#c_euqhSD|hzk)67^D6aJnDNGKYNpc0f?XF9+d?AD^NiaZ! zYspEA`2qyb1=V5&AaE$=A_@k85r1Xa1VOvk8Z}wL*6uJBP#pC{IZ3ui&cvKMFkdR0ue@88YrUC-# z#}RN|5!}djn}a_b?jIh1)<0p~XeGV6^-ACuAbt(@YRd5i&oCEiAr@OQT`sC<{ zE+0NW{@0ERI20+U65NpIHfP2y-zGy*Sw276?T@o(C=rx#Lf~CkaQA@D^pa21Y9LU! zTp=i9Eoqg1K?Bz;YOzkwAB6THFN_ciFW27ZM>tA@GkHL?;;Zo2>>k@bW<{$>bi< zf-9B=2o%c)MUXMfjtm-p-m_$Y$i_la)(aZ`t2WGxENcoxl)*wnaQkS<)gk%Ks#^g- z;O{kvC>S&kWjkoVnZe|fScv80gTO!N5K%CI*Z~F&oWw3xPr5=yAIb{?MG}Kxo_HX@ z3-hDhlXFc41m4R@vS5}6A%MLg6!pAJ(8u8gfgk1?NHC|sae=*JTCJ)ISl|b_hDVPx z0;C=gyp%h5a(YV3liyubLxDiCz0e5;O%QnV^xHq4zkc@mJ8hqZHB@Kik~|&E98fnY z9Nw62F6NW1`Od66y%7Z7Isf|EpRabm`s&ryw>=a<)E8;w@<17WLBlAAw;p}>r^kQT z`|Ing9)m!#z80mEC-qGb-#@+j)5}+Xefa#3|BkVivkDDAuPs@~4-c}D!}kJ*lb8R| zr@*85naUx`k5Oo|13YT)yFdKlsxkpne5cF35#phF1-1_H&b=dK`vt-75|=%i1M|a5zjDh2}7W5O5e4 zNOsCdfJ5gniXI58Bg0&l8D_EQc26RN&tV?+9cBdLeL4#qvYZ$qBLNP{VMH!YS|&zP z)(aZe;V=O2GR#7*?*=SGG&_upqVF&x5bv>}vJ8`x00(gxRSyK#kzp=lbW7wcyG}hq z_#8&bFe4Cfm@30`B)}nam@>n3VkBj~pkX}@6T)_}q_bCamFTrIjEq)um_Z0QOw2HS z5*TLZFp3_Y%}eWQIyxExbq@pibWtJ%-akLvmlP97ET?H(BSQG@gVDQ##3;nw%fr*N z3*%-R;86cuH^|3vG>zi^<@xU(?bC_gvh63`^n!+ZeIfD;(gbk_PfM_V4F?VN^-(PU zN$eP#AZ|Z!PB-M8(~avbH6w|kYLDu!&y1EFo$lM`kB?jskav&bhQII{9|f*X@fZs7 zpUCNzrs@8mi_Kea)WHc2@(7+zt|x|RGhWbe^F;by07vPK6sx{^^g`1QVsGD#BFm&8 zISLUci%V~h1T@4)@aR+_aC_x+d&u{FGM2N*VU~Ke2;obly}SMJFoz)StnAw!aF(l6 z5X;LjKynn~{>qt1MV?WbAnvT3iInAgiFC+Nw|DoB^^HNY0Z7(a4)S6r78o_uor6o` zR|yfKo(q;2j3z@}@18}{4>m#Er7M2TpA|zxU7CY@oQx)jJFEZs#4I_`P#cQnUDJK* z#y^A~oo>$6!R1n}PVtXXXxOr)Rs5)SrlhL*0>zJP)I36!%u2)9K+yQ*|KF&@)t!?{4ilI*NO% zqm>UL$bZ76v1t@{S7#4*)zd&U0%)jHP>_$a(FE~+@`qb*^c(^jWW}1~`eGzyy`bUd z!TT$MLEzq{vt~v4tY%$SHEX_A*6!Pv&YA`JvSy7z+`n|zERpYO))>USOJ~iB z@>%eXLpW>JWv^z9LEOD`)~q0(*Q_y!_mhAGZ{`qr@FuxfH!?9bY{Q3Z3SI{9B4Rer zu3=?})|!<@(F@)&i1$Q5?39xLhgh>jOiFv83V}7$EK*)%(D_!k-3*B6_U#2FxP4x; z#vz1_8I{q9$&ilK_X#?ep3fr66$o=qz2+Nq?3v2-F=2{=nKYXG7KdFh?X`)U5Z+QpcJ2pYwd4O#CjgSG;RtKtt{JK|YS76=Kf`0eKI^9oV+Il$W@Nmue`;=c)L;vAMWjL6Jn* zWT^KO2T5X^okKu_^ifGJ=DJKw2Ce)H4L1+ocNx6PpqpD=?6Oxkul>^~vSiO1Mj^sv z<*}QQz%XMUrBj8#?UgflAus-tg11Vbauz2<_w^hm??5ojL5MpmXMSM$IzJ3T&`z%} zKLq(Ic*h`o`C)aYr+SFv8n}knnau7~yR~NO(6ve9&e4TW{3q9vWob z-O2UDNXmLa!_7-Goiam7LhmjVyWX84TG!p(D6-lN4Wke-aI)Gwog@;_5ZB#0RS2Lo z?-{YHHd-v-%MW{bX{HCNk!F4+2qSh)2#H-5;9-tJ7_njPOQm zDy5m^>(V?9VT88{A>j>y(dZ7NFv8n}knnau7~yR~NO(ISjPN!gB)lCEMtGYL65dS^ zT$+PFNNMiUJv8K{+437M4eEcOVNIoZFDuQnNq0*ChVYc;Fbb_S4?#q)&PsDe0vxi^ z+}8tvyO(G%9Kjppv*7)JKMAFIvbnu8-=>=*NPo~lID(fI=E2(t;Rs%a$b+{L!V$a- zkq2)hgd=zvA`jk12uJWTL>|125Jqi=Kh))bA*41#pb^5T%_fA@W(R~(n@tF*%?=2o zHk%Mqo0}l+v2Bgo3=Q?A%TYdrw+BKGZyO?pw+BKGZyO?pw+BKGZyO?pw+BKGZyO?p zw+BKGZyO?pcN4^i>>-@(>88k4x`&3J#h;;day>DUvR=?|^U_RLH_56wQrzAuR*R!2 zyyR?kH;Sq>k3z&G#-+JO0>k`CxY%`ws%0hm92&TGTkC2FXqk2|Z@iggY@meXLavAH zAoSp74k|>ic8^2o!EHnIYWFyV9^5uWuXc|^=)rA6^lJAwgdW^BM6Y&_LpW=9T35qi z8a>KcyVJVb0pYCOXOO0 zT6IGE%(KZnyIh4KT9?(RtYH*d?H+=NNi5XvnglpxwcFBT7zrOk1FolCojFdKv3$NI z{vO?NB(A!d;%p~Alro37bV6LFM;U|UD8%ifb8`?p%>ISPtAxM;EfD4)42W(JZ4me9 ze#^MCtU4R8L!D`(e78y(9mTzaOD9B-cR;*J9)f#xtK(p&t$weU~n2R)M^@TiaY*Iw4rz1#$2A;PB+BF%FQd!#~Ogkfu?r;ljePZ2!Ip z;8BXGn|VC|Nx9NY<-aQpsP^`y)U;RWZCV2(ED;5LYCbQ2)!@2A!OO@fYAGL8$y=d4hUn}%^Eb1k}Y!w zgt6>4A!N(k0bwk=O$gaCcR(1+ZWBVb%-bMvB6#1}GG`5S4-@2Lcq4d6qdPzt;SCKc zgoL*P!U%5@Lc-etVT88{A>r+SFv8n}knnau7~yR~NO(6veAuO8JV=l$UrP7TAnWc< zt|vxP)(aYLUYhw-GC%DwVNc~OF1vm6o_RNltT=<@C`1gLyf|+s63`IW-2ox%BRVO| zNcbEYP`eMDwfjJ}%)11_Pcg%@j(IYdJNb`>7{Ul{)}SQw0|{;igb~~(gao$(!U%2? zLW0`?VFb4cA;Il{FoN5Jkl=PeIBWMozjlv$l(Tjp^lSGhgtK-Z^lSGhgtK-Z^lSGJ z1Pbecvv!kwUAxC2jPOQ=QEKaoaM$LjPN!gB)lCEMtGYL65b97BfL!r32z64 z5#A<*gm)7J*X}S`sdlGy4-I+kwkDOtj2ASlsdgWPh4p-UMo*`i%eH=~dal|XMxoX2 zA&BVJp?23KFwCrWTY3y5;bUmv^WE0M8v=Fc;S9ij5#9Vr+%*p*mlL@%po4HkH!Ccn zyA8q--K?;P?luTVbhE-Dy4xTe(aj2r=x&2>L^mreqPq>kDBh+=N%4jNpDL1V7TcqY z;%!1m@peEM#oL6C;_ZMiinj?N#k&cD&lFn=Z)m8uVR>?;czYo9@U|ghczYo9@U|gh zczYo9@U|ghczYo9@U|ghczYo9@U|ghcsD`t`R)*#RJ*I-ga)bILurD_vw zUd+a_xl{Z?yt#IFqo`~57(`5BMeR-`FwE?HcibZAQ8kQ&kD-BUx3%zwfL6QH!W#li zQaY?9-TGyVE;N@b?mGxQxS4|r(W~9#5PERi5WU(x4xtCP4biLJ;}Cjq+Yr6lJr1D< zw++#&-Qy6>+MO2O4v%uy?zHfBKsal6T6jAkoV7bGyqh4nc3TT?XwYhRT6lXP^zgPJ z>e@ZzQE?P{c-s(l?QVe3!`p_aYj*>L9^N)YUAr3~^zgPJ>e@X7!L>UGQ0=bLJs|Sh zZ7Cu#;{^?Cs@-uh8z?T)SzOL?uG$?&q1Emoh*%aw?XF2+m|5+%^cY6M$IyTc?L+6D z`JpVkSp#nl(8H|pjL$fk%T2ifb%M}iJ8)3;%nzk>J0SGfwjrc+J0SGfwjrc+J0SGf zwjrc+J0SGfwjrc+J0OhG%^I}nmSwjC!YJJ)ge$RMhT8x?6C9FoK&kD9QXt zg4+RM1h)wx!R>%Bg4=|U;C4V5!EHiFa62H3;5H#7xE&DA+I`fo-J>4mtldZb+C2*4 ztldZb+C2*4tldZb+C2n;s(0k9-6UVv?r{hsyb=CN?LO+C?;eLR!rO$9@P+^<(s2kQ zyiEuRZwG`C-X?^Ew*$fmZxceoy9t78cd%rt-6`EeLteWri<6k~f`&EK?xRo;x8}30 zohAKW5E)|ZGIIHSH!5@(g;u+VAfn5K+Fg?Xhpcv6dW5p_FEsF;xwY_yKplG6=T8f7 z2=L~BbXbw(Le4I95RT|(2r1qU2uE}?L=oNmN$f!EQ8=QT6&BIm2H}WqR#-%L8-yde zSz!^~Z4gHBHa$v;w`01E;%!1m@peEM#oL6C;_ZMiinj?N#k&cDcblz+H#BH_=4s*W zfzZR-hKS+qfzZR-hKS+qfzZR-hKS+qfzZR-hKS+qfzZR-hKS+a1i^deY295VN@$SU zJ(MO$%y>b=8ftd{=XLisT}d}x%qMaOeO`bxue-ZZ)U|sIB9_HayK52{X0~S@*WI<0 zVI%$+8n|{_3vUQ$wL2}mA;2W1!wT@T^b79}LJw}Xqzcii-Qy5?aN7{Q+C2`T2e%E; ztKH)edT`qiz1lqvp$E4O(W~9#5YF127Tykza@Ov&@OD5rYj;|BJ0P63J1xAMAh>p0 z3vX!9YIj*ew6nc2u5OwWtfY8I+hNx?I1B4#lHbh;!8zA)Xwjt`; zJp{qEI|$IayGr+f$ZNNyh{TK+G_0w1$Hi!w+SK3 zZU=->x=jdKcDF%b&-{UN&z$7zJ@cXH4iH9oBg534Ia8AGhQMe72@pnjn-CJ-4hSQ> zO$Z5Z2ZRycCWM5y1HuSz6GFnf34-^`gFmF&ozgutNbSaMv*kA=X1t(b4YfOfW8FR7 z+@zJ{Y&uIfUttK(o_QEWUAxC1qE~b6?vVh8Y|s1wZ}0b{3>)#s(16tsM1Gg4+RM1h)wx!R>%Bg4=|U;C4V5!EHiFa62H3;5H#7xE&DA z+WoL!yGK3BS-T(hYxgLGvvxo1*X~gWXYGF2uiZlssCo~bwVUMY+C2_ogf}vbQoA4a z&v%bQ7~yR~NO(hl6X`gF5#A<*gtr622yYWY!rK91gtrMH;oStmwL4hyR#zBfx`&3m zc3T!FG2;adYpUH3i-Nd$y*+bO=r9Vcb`L>Bmn&*_B7tFMwcFBT7zrOk1Mitz3vUS2 zp@)6`wD5)iZw|x`E7oqh86JIsR|nyUZibNJ?SODZH$xQB&7TwL^mreqPq>kDBh+=N%3|}w^6)J2r1qU2%~tL5K_Dy5JvGfA*6UWLGW&~ zweW@pZO=R{ygd+lc-s&$ygd+lc-s&$ygd+lc-s&$ygd+lc-s&$ygd+lc-s&$yqh3+ z&s^5sb-ITJsog_q0+m63LBkqqcL3*g_hh!cNf&T$ZVMnow643mQPj123?i1rP`hgq z;E?T^$8~otC5*Lyq2Ug3aIL#pJ~rlIA%;;%hZW(|Gd>f99^3jpEg+x=jcv-3|z&bej-T zx*ZTk={6yxbhkmEGk2}KgM7a3rcVZ=J3tuWjqq2R|7zXc24RG^2_fMP0ZybtIVz08 z2yYWY!rK91gtrMH;q8Dh!rO$9@NR+UMuLqlG>EsK+w@q&h%*Y5X%N1=94 z=mDgg%XznD&Vl1P-yKF#)$UOUe$W^%sOj87O#;J=kNDK7Lg4o0@uLg%*%tIA1nP%$ zKwc_y5I8+LqR-;_>_DPe``>x>?VrCgVwW}4xtiq#gE@>r++I0H0eL}ijKW9{tf5Xp z7zL$=uv^qLiVw44ruh_8LW8({CMVM_VkBj~pyB3j|9%9|{oZ#g;1A_TV<~W=MJXE(~*j z@B9o0(R~j>+)U+mgNcI`HwK4^aFBhi0V<6gE`4?&@xX!J41mY4nmM@aaJh>++Nvc(0mf&YzDj;vqA{H z_fN;-f^=DCFgOG=;J9^hxb)cp;%o=JStAFJ9SAzu0dLmC;m-N$fh#T`9^wM;##l7@ zBy+F~p~VFu$GE_|wQ#t7>hlMPvl;Maj6rK$kS@y%T3kR}IE-4Mkpr%OSnV1Or7{;R z&LsHVm?hf$0jlNa(tsop6>m%43pjdz{i1axWya}*24j_=CA{cCzo539iY@< z2Nq8p)?^1n@u6=n_=j9P7l-Sa3vf8{ao`KmnZwa~IKa3LJFs|~i#6E+N*#7!@x)J9*lO3ScVFwmZ9M)uqvHd7* zCuj2e`M>cjG?k>gVdp`gZ)o^sS@pV&ijDAgc*2`F@V48~iuHZr@Z|Z6*OTQ2Z&(R% z6T}DIN-gcfq%90+_^E9546Nt`vHveLymk8J7vFyKY<2a=Z~NASz`tDm<@MF87aMHfv)nPqFhQAbpyAHpBhuZUNInPx z^;R&;%SJ5(KBD89TDV>4bZ3Xo?N8!wydZFo1U@4X6$ApQ;f!t{z*_ z{DK5D{6d~XI>430j2ATAe4qA1A;}xHf#T*gUewPJW0w|uq>LhM)I!53M4Bw(knAKR zpy6j>^K^)+VI+JE4R>fG|1Z{}mq}Jxj^%TY!YGap)6>$UL&e|YC5WL!T01QuS(Jg_KqIyoAX;1z+azM$deY4C$c zGRuOK;zk*xXKCehRW{m`1=(pwA!M@hESN}Om_JQv5Oz|jswN5_Lc^NU;8B$Zxh9hO z1ab2;I0|v|G&l-z^E5aLaq~1d3UTu^I0|v|G&l-z^E5aFv8FUQ1i@)A3Up~OMh*fe zPlJ}C5XstqpsTpjCu(F^9k($AF2xi6v92oy05#4OvMNxzw3U zvWsa|`3D--Q<4DAC22lgY)*HkbGed?A;vZ+vd&ya(Jx7Z5aM#7Gp|U1LsybaJ&J+k zBWS>W6gI5P{it7w)22lL?{5*Mjd-Z2)BXhn_M^gn9UVm1l7(^1W?bJPa5wmaN`a%h z+Kvw5yzL&|YRKJZO&nkcTHWa33k@4RJH*8h%zz_1K;>OKha(?{(1|byI#NOIK5FN1 zXk0SWVu#_YMcO$W`8X7ISQm%GmEPyH*g@{P(b+$L=dpu}Lt%$?aX4J*%~*>aq%!2A z@7{at;Nno&VO<;!S9-_TVh1T5-PrSY9y_==6n0n_hr^ZL*0$I|R(1L4yZ0VDxHuGc zSQm%GmEL=|*kO2s(PIY}hr$l);&8aq7YHqOkUibb2l96wJGeL$c32mO!;z8f83LO67^!PJW&IH}U>o)+5Bp+w@8s}}<#KatzMO>wCmirApmq+O zbPcHd-OOR;;?PMenDs}^9Of<#opcST{N2o9;o{IqE1301%^a344xMxjsQlf`Vavs# zlU6Y6kD57byEt^xHK6i$Glv})hfZ3-tUqevfRZ%XG)O>0`Vo4{QJr*+*#EnoLznu> zq^xu3r2CllC+!@%)YrnHldci_f46h!QeO*)PP&g-f6~O^E^fXtseAUQ3L4%kYF3a= zNKFuTE(oIPObQL}77#3*zUTH}wCdeE*uB_2d942u1tilC6WFVxw16~?;@;}w@i`5o zoTaFu4-utZ5O)txpI8WNhjK20v>>z@>h|TM(_?iAqz9w;VKEnwP5?n*d@hbpP7WXJ z+Gi)rxrow&(li%$o=|&JwbP=2M^SndOQ-MK48;)bP78=^t=v8eBl3(fI z$hME0AntN7RjcJ3qRdf2TE1@!y#Qf^H%KZF-By@m6h?R(5M6jTLEJk({B&Yvb7&~j zV3Zb1HA75Y5Rmpk@DCfG>RGBkiYV=ZxWhe#QIh~s<|vjHfX0%<5XNjPnHCV;Y&SaX z?!mq_6|A9j+8~{V(KOxMM;Vc)i~@aBwoBCnaqsip-yT}S=udZ)mSHqOynT4~`RU~8 z#lLDW(2#D+%&l4`4VZR_sS6@X`ygg6h$!uYn7bgNv=3t8f{4;Sh@}f6N;gB?<6jv+ z)vI^kX`?jMUd%#*ZZ6bvza>VaTsFT~6R!O~uc zxeJ1&y$}l*1WS7%mM#dEc0jPx&RlUp(gDB|7qh3HxFBg4#G8lvyJwSjLy5G*Pz>RS z3xe>+1s&vw3z7DY!Vwn);g1VC$PpJJ?Hz?9E(qdUaWQwr1xdS{mP2puiVKo7gesMA|hMbdV!1MA`wthFZAR7bNX6RD{rXLG;?ac$#)Wnre51(04&Bh_nmhfzWqB zEQquV;(_q=QH$%u#ljUAB<-5+H_y+GS6IPmcglku%04PdJDe5}7cPh(?SQy@irYyW zH`>D}%H?E`4*Kc8P1Ak%6hml-U}-M|MxjkaB&m#I*9&1ygbu;dJ_wHPrK?_$v|u#N zMTGG5QA=lB+&iGD*ng;RtAS*>9~Gs2qX-A-8!Z+@+GuGrRDfvRkBZXQ8AWTo2oTPC z5e{mt7g72;qiC%c0pc3sjrY?x-t_Ok>$hNDGB59YQB1CIkVCJ@+ebk%h`=NGgw;YA3tJ*EnVH{0!0SK7%x<6BpaAxFBiQbf>w{yw;wJ=(WDNXohh2QE3!fpJR_=&oSM}qnaUj z6fOwb19`M*v{L<1Bx%nma1hQ{warD6_CjD3ZHAIjxDAC-v_r78V-)w1*ysu>wUNSH zl=VWS143J8E)Z%XWkN_J1%c6vGz3Czq)Z4Y7%m94V3-inNVy=?M#_Ycg|`brZKO;H zX{1~bYQZoeq>*w#s0$1eLJEchV&aMmlJ>{N`E8wEy_IYX%K zWI{-qbwQ}^WI~8Lxgb<`G9kpBTo9@|nGlj@TOmSWox0+Jq)9zqO&)dYr?a23fMj;ZWAhg;`M}Ee(C`lZZ!R6>KjAC^h!60|e!R`*d~-s#@18F6!uq}4gM-!a!O7v%)5iz(t+Juv z7veAxqL7#SX$8v4f15bGdGh%2+1_stA6e^*^xLS&A<2*8gHjuZv)$G4#qZiVB>DAm zxEpk;vmL^}nu{PG2{aA!{`m!&`uO5p1A&J6cI6_^AWab0eEw!^D4QTY%)I*68ee?V>JnIh)=E@ zqG}ikA49{P)ukRZB9QjwV(_xO1PwIsY+js9!c8#aY|f*p7~;YS!SX(c^OM8FGc73M zFzZpUybI#)#U-wZ)G;v3`Z*v$K4LT(>U#J3%ge#&T--bV96unvP=^7My^<8(#{Jnn^5k+EGh>grF0*PgyMbJxI!36LUGqViF$K zAVX~4Jc)4v0m&?j&GU|Q^hUn&SciNRDT`s4qY%lGc@`5A&=BvMC* z=5KT$AnLLx^6YOAh$N?Z5}R$sbq)mHT3zn_)^KWuNI$Mjc~ayXoSHR^a=2c8ko92G zFz-?BJw3blU2}ej^1b|ETk_7uO_=izw;cr7EOLF*EB*38ve_fAZ zBzz1F*Ncm~ZmurR<74R~$(^{p2#C8YXY~*A(QBarb{K^CyECJ?po4js>57_|Va^UE zD5AhP#A7GKV?V@^6XM7Xac6J!+XKCW(Gv*Ei>;dGg1TZ~j$(Ni#650%9=C4}MEL;H zGz#RX9Z`5&Ml_?;o#zv;xrA<=H8Q|(4)j8H4Ua>2%L~q3wPvDLqPtM zyc-M-GXQ}dt)n9&QGr8m`4Hqgr)`8VvWN*GSp)*35I-s`nF1r25*lQGvXGO&h!!U? z;{^>jkBi`wn2RhhX0e%Lh_TxJqqz53j6wnf8b%>HOXh(QNkBt$TrOwn?pF+Pv^q445^Jayq>z_f9%6G8;{5TERgu)_hP)5r znmui_RFk3L4`NAd+83sThHPI>v|h-A0J70a zR0N+Kg%FqHsHjO`nBBgdN!79veGUz@-E?$xtlw#a1^U}fkpCnsS)l>5d31DfnFq$^ zBK~X`0<>zTLtLxoAkU851o0L_(8b9oN}mG_^{Tm(PtieA)~ksFEoq7Nz};Qynib^( zfhGu^taBp)K!Y|}=NF#IdWTpYA3eTQckcl4^D2qu^5eE_8s>fWD2Ky{e7nQkr9)O8 zO9uHkz@|~4sHM1&G$(<S7!Lu|s&8yyMmdjS|X%s2V zf#fJeN+5Zf6B5wSb;TxClCoaVK+9@mExl=lKpi+iz85&FBFjw{*~Z;{KE&a)B40V} z00iv~a)xQna-IBmWCo84b1}eymXp3L7v%#1n0gd~C(9F?fKamBz$ob40kWK$u7sc{U##*MeXabb4{O%|uYiUc_1Y0%JP z7zrOk!#(8BgA;vI90K)pNBOWn0D(Y~?ybuYI*%mfd^H5Fx6YCay_z6y?H_2rydZFT zK|}f(THN9w`7UCbAnxw&9jI|B5Ouu>@)4y8;uamE*CS&TB<~zW2)#I2x5TgGY=LAE zdd8$;#QF;w))jgL-i6-IPVNuB4kV633B3V`LIDMj#FlLkG+f5xHXn)dz__ZuZ!;=b`QQXc96qe)>cpzPu>}D=;ClE7i|huT+O%PzaLi*lj-RcGcdXGY4C6?1bD+nF6@CwrX(=~gju401f1zO=OSuS+r5rssd$HVFOr)YPMDs36Hi~K~ zHv*9+i05+<+dpUv%*rmygs~iYiZ!i2cC;j2(cumhnfU9$hB$#L8Urk zDBLvF`e_uCtbYKWC8-`5Z{5t6?c}EWaT! z;{^?C$}j}pg)Kc@SP&UvY-yiom^cb0!wf-)C9@3EkpPD*!&rKRvhpu9T(fp(mw|!g z`NesjKsI;sR_z@+$8+@LBb)G3J#a=1?+rQ*XZ;86dLRpc2T z0^`Gs!KlJ$!_4K^G|ct12ZNSG@QQ#0Z<=omGYejki!q+WNXmLa!+L@j;9c-e=f$}s zPkSJv=m+m0gg8tVyd4P)vkP8Rk7XtL92%|}yfHYT0VHvPiZ5=8JcCm*%CIr}8LF~aCvAoPTTgx*AE3$vMpp2$geEMg>Oy`W(| zp$G6T^d<}05of3Mgr1C|A9{ljV#zG@IuaOW7kZ{1%S!Y)G+A$r*Ej)^9jXK+0Q2Kc?mL`mn z-bUXt{%MNM_ec{Ll+-+A6$Kj7g+rRXAaMWun`>S;6g6&$0(BgK_<&Yk6ME>|`HD{Z zZ*EUEcb0ScZ6zD(7tde3zIyfQyKi1^{Q2ecuQrnW$N2L%s^ad$1VN8+%ODmr=}{n{ zL9l!?#7C43c26EZC_t8raH0kf8`UT>`34YZ_-J+U_#DgBd>qSZ*rU)OGWkY`59vDB z8ezVbEgybajiQrpK;YSY@6qXTF@pI*Zle>LoS#(?QNBe#8Ho*bd~$O5VE3eeS;i~w zHA7|c4KUE~0Y9?41enNOa3N58RFZE12%}&KdahjNwDWDb+}(m;c^^a-dfP*Bfl;u$ z526aai8L|RD14#EhN9;!W`miLWLmH5V-34Dlg{(q@UVJ&>b1`4$Y23=s4<)oi{Oi|Dlw zsM8=ru)GhV4DaPM+ka3Yn!_6;KRQ4B6wmD_hCvsT(pMqF)FmmCZy1I^Ogo4vExIT3 z>BO#j1R?T`5Fg-KbTSnIV75IJ7fHSWAZA(|B2y6|7SW;9=uYy@5Fds|*~h7fcACa) zu6a}^-+}=RAMm5>ON8PMb#+Nf@+}CVu*OH(7a)^Zl)$0(s7$^A1R8#tJ<7g-nQzK2 zB}rK?X!wV!f2b6W@JJluv+fHH)9ku?ivk-;_a`|?MuMUl7}RSf#{Zp#$)c#RMIp1>y84+B6G~#x5Yjjqo&xLcVPj zbVzteV*xSed+iwzoqQ9-hv8w@rT(FvoKAjJe>C-n;nCP7MBMS>xu};goqRh4KN`D$ zSV;2$L-in%d^-fX`P~v?s59qLuzV}TN8!1_vWSUMv9vetGWiA!*daoYr}L6ELd2_b zAW(Pa0fOay5R^M}h`8{!Az0oALAf)Bh-b2G2$uIj@b(WS!C20(D;EFoqys{<+In<2D%F||sPjG`@v6r(67V>ZE3&@hya)WGD&Ar%-gART)rIx!_>j)92l;UvX!t43-qS~qFX)`XK{=Y4oG2kF>je$<&R(T( zga$OckLwu<@JTv*$^P*3s(%pq5#5nBAb!z3%JK83bUDLgdZ^&P9)}^jHKtVuLXTQ!j2M*777REUOIs|FI>kP{CD zhk2_864XbrXw^W1x`t(|1`^zmv&h9Lwpulipl-?SRt+SmYuIVkK!O`ZKw>uU!BI91 z6%hDg?olLIkVqOVr|fAUL0yC8lsyf#Qzj0UQ}#5}PMI`VPTA7{r_9|tX|SBKrvXl> zYOtKLrvXk`Yq;}ZV$DPd-tWt7vfzeX;K5GK(M=kxndoW2OqAztK$0|AGttw4nJ5yB zaIj{grvWojIJIc7W}>G7Gf@P$Xs~9YrvWojBwEp6rUw?t<^t(K9fg@5Y7Iya<@v-g z7t>aMfMDTIVVHLwOk4c{f~qB_t^NQ()soXze}JHB$!V)UKv1`2t3OQP4_aJITm1oo zYFtcP{Q-iihFPmWKv4CES*t%lP@Riet3NJJc9?J#fk2MDSeX5Q)#5Y#oa`orAH5A#-kfS{UT z=B@q!LDe7Tt^NQ(Rl}myA0Vju!=lw6AgKDoqSYTDsE?x69~STjtpi!K`U3=Y4XysL zfIp}lTK!>R`NN{sA0Vi5Sho5D1l7n|w)z7ERexBv`U3>jnzd~82MDUQd)ev_5LDx0 z+3F7v)a}sf4@=7*maYB(LDe6&TKxfnYL?q-^#=&5v$@sk4-nKfwEDvq{6Xs`U3>jx!7*?2MDTm*lzU)21oct0`oqNXhe@kHKv3t<>JJmk zA11B-06~?5y+K*c1#eImTbvM}{9tcT)*9ds#a6FqXw47(4NB3_>JPj@Su~WQq17LF zgRfu-k>bDIE6#2Kkx=+ZxnBy;&jwgy<`C5=W_lc32yw~ z8y{~>HvY%|*w`HV_^zfKW;5j;)YH zqDv&F9+EahMG_DyNj-KHlE|fr7ao!}L`4!1DoMTQC?rvI63L~9qzzG#0HS`RdmMah|r)tn}X znq*OOpy3XuApMp_+{^vHMRZdq+4YtG6yL+q9d2RFZbnTaiS%Oe7tB_4KI?QIQ0MO44q6E0W0LiKL^i zo<6l9Dw2RGNpjOm3AC-R4uT!a_P%-uqNuzPBC$-ho4#o4tAk)ivc0b!f~ZOAeKl!N z>j6elH2*;`BRN)cayyt1HOZpn7CP0?zR7#|lf1{Y$$MBw-h+g^M|qL=$l~%I$x_~DeKi5+$cXn&EXU@v zHAz8^4r3X8^{ln8X2C9hIQr@#h@xHuh?I%DzIxW$SF>P8axBMXJFBFx zPi=^bBp_6hY6j9sBKQ+YM_)aAYC}{c0ilw#o8F=uoS{4JNILpzKC;axjlOy|(DYU$ zuiIA-K~$DB`s&$0(_4|eZeKkFQIRzIYD%DOeRUA*=DWSG9)c(;Z-hurnc4&TqOGqE zf*r~BzIq6vCaL$;q`_=@i@rJtW+caIPHqPiq9$3CoLqxiav)HXEJ{v$Uroa^A!?FE z$;nBo^*|$8l$`dynn;=uHOZpnYKDzM8(tv9rFKzRA%C`s#UWU(JGD{&4iwLl8y12oNa~bBn^8>hspVngu(O zV>vGCtA`*el0}lsNvavB-)POR-B(tP%WuuAdMtkIdy}MzIxu;SF@nj4bBIe z-lB(L!H%S(uO5P^rn^XT`E;upNV6n@KUvbzSI=AfY8KQj+1OXluiaPkk!?O{^wsm$ zzM2I)OFH(ehajryHu~y$YhTTR9ZAQ2^$P2f`&4OKM<|Ne&q>+S|Cz4}1u9$8cqOv3)RG(BckVX>0pGZ3T>P2f`&4N0~ z#=d%S?Y^3iZ1YK@uU@qF)hyUq($QBBK~&Ri^wo>jzM2I)l8(N52%;is^wpF=+xqGt z*s*NytA`+p${Qh4hXgs4dt zB`4RQmK+GwBvB7i4r=eKX?P|?O|mFCIZ3tTXe5i0)81DTNfV+b2?*6E)q0?jEJ{xM zel?LaA!?FE$;mCLmK=>_QF7Y*Y9eVu)Fc5>Sd#ndg;EOCzIqY+YJwz1p$87_o4kiV z$$LzjyoYtMYQpOJYWgEb&iZQlCdbbDYWgNeALy%>t$j5McA@F$ ztA`+pdJ!PfTy>4svbC>f!H(ouj>{UYA&81(k>qlcY6j{zTFYzq)qJGlxQMKZWRc`@ zl4=IhNWzspHwrDMiRlFNILrJ zWouu}f;!2@zIu7>zM7A0^GTzxUbgntEZAAn(N_;aRMTzr)yvktngu(Oj=p*bq9SSZ z)s#Tn`syIqv25?Fhaif|8zEBUr1pTmXzQzkU`MjOuO5P^N$PzyX)v4KqGb(&8OgDl zliR_Bs7V$jC)c2s90=4TQ4dlMYVWIQcqT+mvM4z@Nwwr?B#V;M-d7Vz6QU*w2-PRm zlB1CYKDzM8(tv9rFKzRA%C`s%IL zzM2KQ&~)_GLl8y12oPzmx<+fOwXbHuj^tR5%lhgeh>B#9)eNMOge#{^?C7hvTKj4i>_Rgqsb(OJB)mM4boA9*t$j5M>Lk?+q>)7M zCz6i7daJdsW?Y^3iZ1YK@uik3yt68wKq@%AMf~W$==&QF{`)U^KNILrJ zA&82k(N|LfZR@LpV8^n(uO5OZDsO~H**vue^hH}=9Rxd)?S1tSL`_oft4V{|^cF2^ z5X?x9)tuZ8CPYoLC^@+Xwd6pcCW(5Ga!`9;O~W%GYLZ3C$w{guM{5EaQH$>k)~4AgJ5wy)h+ z^O1_;*wI&SxAxU6*o9_JQq4dbNqBi8>FBGsTl;Dj)Jdut zNF#~hPb3|E^>%At&4N0~#=d&{+I=-2+2)f*U%lPhSF>PeNk?Bj1W^T!(N}M`_SG!d zk#zLcLl6~7qpzj}+SXSG!H#8nUp)j-RNe@YvN>`T-?W6jXzQzkU`MjOuO5P^N$Pzy zX)v4KqGb(&8OgDlliR_Bs7V$jC)c2s90=4TQ4dlMYVWIQcqT+mvM4z@Nwwr?B#V;M z-d7Vz6QU*w2-PRmlB1C zp!U_;WHw8?u|N8W>kyzlzzP$=Z{uCFGnuCJy)a^$S9rf+iW ztgohTa`b_|dZ)FoX2C8r9ewo>L{TpSM4GFv(b{S4t68ukIhNzHzIq6vB3UH4oTQq8 z`i<7kwfky5QgK{FRzu7VIqP=&Oeys=zV& z>YdiUngu(Oj=p*bq9SSZ)s#Tn`syIqv25?Fhaif|8zE9QM~>pYn!af3tAk)ivc0b! zf~ZOAeKlz?o8F>j4T2fTv6_?H!Gx$u79}Uwpq3m6)Fe?4QVweGt7&*9L`||NIXOwS zXk(p|G$Cq|MPr?7p#0oM5{W#K9Br(dAZn6D zV+{>&^D`DGfohF41d2urnHCi$u^elxn;?EtJoh0&r1>rrZ~w0XLhHOCuu(&xG^SCE zb>2-7y-@(-dZW-PiaLt2XpOYy#V9O@-YANq)wh26Ndcji9CZ{$RU7Nwn;?3lD5_e? zx&K!Iq17aH6h+w^YwnvMdZQ@HUY~dQNdci1Ep-${T^#HFn;?3lDC%O#x&K!Ip;a|? z6h+}2TOKq)^hQw>&OYz*6F}SznYLdFAPRy1ugp<#{Scem(CpJ6h{yB?+&cXM??`{Z z$mtJoO@E-6raw@$(jVPILh^k2DqBk6yMjcvn80@hjchrA?}*57XAL`q*4=pUBm~M1 zgax}??pR+8K$LYeK%`urlhpDk&t^>$ChH2$uoZ$oh#gFbnj|1pl3FHKNfw#dvA&qt zOPHEuk%@CllHc@WLz`|mShA#JeKFBD?g3Gg1cYiyEsv^}Eb^#heKFBD?lqD{9?dOD zQPyTj`cXkC=?v>^#y&0;7S_v^#y%b@bIiJ`1wbD zW5G~m-3$*(O2yr=z8HWg>t=vR6$uU@1M08x`HQgu#JOOr}h zJat|e)C5tJEHZJfLCb-vHPbxWGfe{D(Rt3=YVzAzrZ2}9MEG}af!(=nl;CVAcU#Q;Q2 z(pX;@Psh|qUUz*l08x`P))$mO+twFBu$%Ap^~C^0S-T@d%H}kigD+SztS{)uw)I62 z>_*YPz8HY$jpCZ?3xa4{Uj)Hy6eCruFq8$+8%0sH1}B2PEFiS127z*wM592-Ng1Sl zeG!iAwIG1#jiRV(u2E=ZPaQ>3_S)AMGztr%Hwr*pFD|GSsfOy!MNt>q*B3Mj3!*oQ zqAt4TLMxo=Toi?~eSJZrupoM)0EBBU!urB^&L~Dvt}o;{qZ1-UP_ci{pEOF}z^&6a z@Q(BcjGX=e*YroWzToQCeS_kV#Pan8Q7Aa%>kIm>V3Dsc=(~c4XMI7BR#JRcX_Hv6 z%O8&Q#Q;QEHv>ePZA?~JUl>mbg+SSXcppUC1W}VLQgyC@Ca4$vswFX#DHA)+UlAXH0gSx_YjKTjkb>kH#Sq#DU0(dL%alAKBsexFD>))&TuNHvmxP%WwDFqI_o zLL%u{Ul!z0`yB0VBKQ)-(Lk(HjGe;JQo zMrK7-byAeq?wCSG4qCJOM>Wa!7dX^DK&smVfe(vuLFloJDcbnsgS{Rn0t$;;QDK{NpTIDF$azT-7{h!IS^SkD=08 zl#~DTW2j4*!Vrv;^8Dvev4^^~?4jNv8&t`%L0)AeoBZcLiVC%C@{gpnNL3EXC;!+- zP|$sai+u8r$il~z$v=Mo$v0&Ufr_XJlmAYN@}kBm1hmvxJo#_@lqm(2(}StMmg-7T zn`}(}8$V@gnJh>=Ve;QeQJXACoS&veL1W6wKV>RcqzRM%#;>K4huUNT+T5fCInyNd zdoej-^56KiRLdl#F#Dv%Fw-P)K}=4V{5O6r)iPONGOtPJ{5O8e)G|4D^502On`}(}0Z`xMp98g1`X~RL6y>!$rjU_?*6jXK zP4eU)M_Sh;3Mi+|9H?jEpZs@H49;Ta!M|*C@xz5$$uxsprVS4 z)})HEu4?946jwF>#UAQ& zvWI$yY)~c326>f@Z1SJ~ax2ub$v={2lYeX#9`eaQ_7yJj$v^fLKBi3m@gr5n;5Ozk zAy9|Kgvoy=MR`%<6mq$s#^T9;irQqs(Okh|m|2t5k^-0slmEs~ zx{`<5B&9HG(xRYgvY_CE$$#S~T`iN8!ZeBQJh`O-`8nZ?zXM)ip^eOp_MF zOq0X~F*#xK-}p&at0oIf=6%vR`JeieuC5eyO*SU~jo(|P6!qwyJNfUVs7*E||Bc^U zwM@>P{C85+CL5D~0Ms}6=Rob0{>gtQMS1OxDP-iJHM@UQlRWvyk=8Yd0?Nrh2kKe) zC;y!kgR`JZ^1QR~P5$A9t|$Ts|C4_{asW!IsKHqj7p-nXU}w=5)>X}Hi{h&0pZw!2 zS}6u+QC!s~orQJTGtZ*9?D;4EIEz+_!C4fSy-8D6WhC`wN_fbyYJ{6jwF> z??dsnf&9Iw0sk-5U7ZnF!}GKC@*T9LO@H6 z#gqTWkHS(wIX#&AyR)towaJ2`xq`(oV>USTcV}HGYLf*fa|H`grb+7Oaz&aj`EUI0 zEP1F+78J})T97kM7Lc1T`EUI0tYwl?n0?a1q-nCiAAn)$$#UwZz)AN`A@%nyTo~;^TxS* z{_D5cLw!#6P}9i<)qre}SJ}uW|M_p=LM@y8BWX7I$5!DXpZsHA;Ub^>V_)IJH~GJK z`(yePvqdN#IKPoEcS?cT*dF^fpfL1CQ|NbSO9~|vHC9xx=wOOo?1bXuL8Y^SJ9QVP?gHMUKY)T6}Y=(IXF*-lZJq!gw}iw>sAf)1n8 z>fB^IMP-swm?q6>bx2VS93p|#yH`z{6nJlK& zxq>y-W0REv&%-u0ZXD3XhWK!fAZDB)?GFLp|ZV=Q5m9Kz^F>gI}S;1iiTm!~VdZ8*6yTJ1qxlr}cxho1!{R z8>CQZQ?4>eO(Y}B57KUm%A^faD6}b8nWVlWCjB7orl?HXAcaDka+OKy)MC;P(r${% zqzzIiv?*7aq|qiO{UGh8s7%@*g+iNhl}VzUm>m6DHNjvvMPjF}g1*9koNKqD$qAVaqxerpTara#>IFQ?- z0O?ePAxNRnuIju$aG>^wkrjRMnnjb|Zi>7$V+zxx52R3-2~s|?aY3m}+8~9352PHZ zHR%UwH$`RA1}PMLAmu z(grCMfG=OK<~a;N`cV$j#)poEAPpZn3WHr{q{uEHWhV?(lm(jT+|AXPE{B(3JN}ua-jAHKS;YN^8OH0m?qo(A*VeQs6WWn-#=~UBYkbb zUG4_{QkSFa1r&TB{NX=4HR5Ts!NcNhf%Qe+p9qD;dk z%ud;rlm(=CT|kPmfE49ENO{eMWAMhs9Yc^#RTwe~3Op!NqpNV_TW){H4klRl6_ zVJ1lVNMBpnAcaD^)8@42K&?st^M`JVswR0{)U=0!52PHZCjB7orl?HXAccYtq#URw z{UGh8s7%@*g@O;H9H=J!Anm58OxhrYLi^%gDe#qdW8*-k2L#f_Vz?nl!(uqZXSen! z3rJBGkfKbzGe8w(0V&D?Qj`UxDEC3i?|(T4Z+xR{2-2wvLq zF@(grCMd?4jOHR%UwH$`RA1}PNU*Ud_SFKQbb*9(v~78VRa8Wt9O zOv?&nMvAh46lDP^$^uf91*9koNKqD$qTC1Rj`tZU2Xb2!xAs#NhKz!O52PHZ{lO2? zZi>7$V+zxx52R3-2~s}N0n(VlH0c8=6sRA`^9Mgj`ADBh8>CS1fs_N)q#vZ+6jgKE zAcaDE_~*3eKsD)~Hg{80CYdlb?V;cUDF>=aKS;YNDw8%yq0qi0RSJB)*x2}}0O^j= z+vwJR@UHz1ziW?-0#cL(q$mqWQ5KM*EFeW$K#H<}6y-ihcfBCxKyHfyq*E1!!ygJh zkaD2*2R}%=De~5gDNK_-kV0W5Ncl*k*VHR0VhYow52R3-2~s}NXVL~K6nr4%Ky7Y6 zNV_Sj=C(l!1s_N`P)+(l+D%cJv_T4mHluRdbD)~^Pn)|bDwB-Cn)Xm=)4oz*6mM+o z6d>I-dYcK-T?Q#K3P@2FkfJOgMOi?KvVat20V&D?Qk1(OU3nLp#z1WgH^llWvYJdO z27I6$E{MfIHR*n%r=OxSNv&a;bU}<#&4XAx(&$zdX;TW*qzhuCK%GmbtZs?N|Vlhxnx*^t2Q8l*-F;Z|rEC#AcH^llWDw8I}NTCg}jI=ROO}eM7{S=i+=43@$ zQULdS9fklI)<@+FO;_H9rmOHnWgo|k;Q=X?6KScONK55JS}G^fQaO>9%89g8?voY^ zsC=i%f!r4Plyx;#VL1Gu-~%ZKYJc#9w3{OD4>5&l(g#u~%mgVP>F9DXg=x|UQYg#> zDIe)GX@e9BK9F*tHn$(7-4s=G+aQI452PHZCjB7orl?HXAccYtq#URw{UGh8s7%@* zg+lv=v{E4E4HlZNybDcNywEffi9yQQr7R%D>jF}g1*9koNKqD$qTB~57Et*>%7NS# z1xTkV42M4y+EtxjSUFJpgMZrGO_8@|OktYzffNceLCQxu7!^~PCVe1QYiR9%7JRq57KUm%A^faDEL6ifojqZ(r${%qzzIiw5Lgx z0&y;YG+$`C@-8%8@j}xTGSbwR-m<5%%t+aZye=Tc>jF}g1*9koNKx*C6bq<)Amu=A zivpxm6^6qf3Op!NqpNV_TW){H4klkNVH(;f=cALOptKW*kC9gK=8Op`v4LSZII z`ADBh8>CS1fs_NaCjB7orl^|R1}PMLAmuAjRtfQj`UxDEC2%1ynwe zav--w0n(`o!{HAFA4oY+`-2~(-4uCi#uTPWA4s7v6Qq2kgHbVsX|mmEbJ|0JI<3&& z{kHy!kMx=3aZx`sgMtsF9H=J!Anm58n%f2`6nr4%KsD(HX*We>(grCMd?4jOHR%Uw zH$`RA1}PNU7xzkmue{Yl)0KCj>53PcQWq7FqAVaqSwM<1_09lQlm(dk)m*_P-<6O;I&B58j&gQ1F421J$G-q}>#iNgJe4@PU*A)ubP! z-4vBc8>CQZUpFfSzNl3TO;_H9rYl}(xQYf^Ce@=T2RFnQ`b2mk0k_l7O9tu8?a-f>@gS4BX zGHHVp3hhf$rNGyVYN6@MyU=vS3r$zZC?G{yK#H<}6lDP^$^uf91*9koNKx*C6bq<) zAmu=Aivpxm6^6qf3Op!NqpNV_TW){H4klRl6_VJ1lVNC%^03e%(yq)?a%Qa;jW z(grCMd?4jOZEinEyD6&Xwm}L7A4oY+P5MFFO;MS&K?;R7qjK7Fpqlhgo4YA0lZ?Td z_E2ckzEWTmR|`#7-i4+sUTC^PMgb|x0#cL(q$mqWQ5KM*EFeW$K#Fn~q-(5?azQKx zYFoG=)=!buWJ)pM1MP4@EC#Ac_ZvO^6qQM84b!9xVw7qg#Nv_T5KAdclP-vn0(CBV zi0Xz|Jkn>-f4QpJ4N@rhK+1t?(ht&Z zipr!7QYf_Na+LxxZ?MpG?OkZP=7pw_Na39(Dho(a7LcMWAVpa~in4$dWdSM5eUM@S zl@FvG$Zb)8bgIH|_(P#x)%k^$1GPW+r_J3Id27ZLrb!=2p)eDqe58X>F@pf!%bK4+=f)At|s3!d&?WU+q+8~9352PHZCjB7orl?HX zAcaDEnp7ze=LQQ+*WQJuYhGx&M#gmSPh|lqJ7K`0EFeW$K#H<}6lDP^%6*Vx0hJG= z9LQ}^fOM+DaQH*P2T~5y{@@2`H$~o>F@#iNgJe4XkXkb1-|lD3r*MFg{Es>Xi8mFK#H<}6lDP^%G5gpR8ba?qAVaqSwM<% zAEa17`q0k;#Iqf-6o7?}6ST{x0+&p+|+C#wyQVvv;evo!kR3>eZLcs@84pftV zkakm4CT);Hp?%$~6!@Z6Ei_$w7n-hlq3IeK1*9koNKqD$qAVaqSwM=ifD~l`Daw72 zVgZ#8q#Vd?QGj%+!f^OQ!3R0ne$VVd-T6bdsz z%18Q4+8~9352PHZ&Fu$iH$~OlHb|k+9{xG)IZ#ddr_J3Il}RQ{O?xQ#K+1t?(ht&Z zipr!7QYf@9NtFU$FRF#6YwtqSH7_(>Bcp&6WdSM50#cL(q$mqWQ5KM*EFeX>4^k|k z@`02Cxh)EiPE{BVe<=7s%7NM+{2=Y7$Xhd}FirYE3Wb><(grCM+KkF+&w*;vKW*-&s7x{j zYuZDhP5VlLQCuxFU3(Xru6d#98W{zoC<{nY7LcMWAVpa~in4$dWdSM5U65{KeUuAg zF;LsW4Y7WTtR_>60Uv0G3t}-)O}gLc>8GenQfrtdT@a&G^B@+F9EVs+VVZP7j1;JI z$wO2(#Nv@YlP1JS!3D7xs3zSI>!+xi+k_Y?xF8k-)ubC@{S=i+6Jn&$hFC`07^o)Q zQ`UZp$|Q5LA}uMn=5jHR-;K%_nr?a*nr`w!(NU5AiOXWmbDksuXIgysiiL_Ks zq@{A7v{*ppJ53Jcw#cWfn^P5r!ygJhkaD2*2R}%=Df0dhQ@gS4BXGHHVp3Opqli9 zw40(bX@e9B?YUf~K+GE~G~M(rG~MKdrjbbDohB*^NKqD$qAVaqSwM=ifD~l`Daw72 zVgZ#8q#Vd?QGj%+!f^OQp zd?4jOZi@n>Qx%589|}H@a-jAHKS;YN^45$gOq1>YkkcLt)F0%o**|UOBOQ#2DNK_- zkV0W5Ncl*gNgJe4@PU*AwI=-_?WU-j+Xg8Vd?4jOHR%UwH$`RA1}PMLAmukV=8rHdtu7>0M~L$qP+4kx@X3vVat28kymipIu2=K#JD|q$mqWQSO5j z3#fb`pJ4N@qyFYc8BUwNyArkmb{rklLbl)9*Z6lDP^$^uf9sdombqAVaqSwM=i zfE49ENU?y*2T~5?wkSY4Rbe>%q2L242Wo%tgS49>Z_Sv(H0c8=6lQ{yk9069rZ7$V zKnjJKAmt-{CT);Hp*^y4+H;^bxBnfnZi=e8dGOY>hk_5J9H=J!Anm58OxhrYf)At| zs3!d&?WU+q+8~8O`?^^v@I|d!Xu9cLXu8P@O*fHIK#H<}6lDP^$^uf91*9koNKqD$ zqTB~57Et*>%7NS#1xTkV42M4yd?4jO?GJvCc2nf78B>@heISLxOpx-C4o1Zkrb!=2 zp)eDqe5B8$4N@rhK+1vI+0M~L$qP+4kx@X3vVat20V&D?Qj`UxC<{nY7LcOc z2Pqa%`9R8n+!h5$rz#AGKNNf*pqli9w40(bX@e9BZARs^=Rh^-pEh?> zR3;gNHSM9$rhTQrD6SToZh9A*Zt_CYO=J|1qAVaqSwM=ifD~l`Dary;lm(E5Q|6pOqviQ1sB9(pqg|;te>K4ZWCgp;DT5TRFiIq^;1+PO^A^~8)6x0 zW1yOJPg(mZDwE8~inOHQn#;vNem5##Xu9QHXu8DQYiR9%7JRq57KUm%A^faDEL6i zfojqZ(r${%qzzIiwC8e_0x@r}&~(eY&~%FznnogpcbcdyAVpa~in4$dWdSM50#cL( zq$u}6iUm|Yka8fmMFG;O3d7+Kg?3fv7gi3`{@|ZBcT?o88B>@heISLxOpx-C4o1Zk zrb!=2p)eDqe5B8$4N@rhK+1vI+@ zgS4BXGHHVp3hil9r9hk;EHvHnE;QZZg{E7`nC|_lEFfhk3|N!}q$mqWQ5KM*EFeX> z4^k|k@`02Cxh)EiPE{BVe<=7s%7NM+{2=Y7$Xhd}Fip1mLr!}rP=AoSX8*LAk9069 zrZ7$VKnjJKAmt-{CT);H!3RCS1fs_N) zq#vZ+6qQLEq)=$jKq>`d+hC#TmUp4)7B4j2LPh~8$^uf9X=H|5es(2g0V!S=kfJOg zMY#`BETHm%lmodf3Xo1!7!H3Z_&~~m+8_KN?WV|EGo~<2`alYWnIPpO9gK=8Oq1@gS4BXGHHVp z3Opqli9w40(bX@e9B?dxWxz!$Y@q3M=)q3IScG~Gf*0V&D?Qj`UxC<{nY7LcMW zAVpa~igF*MSU}|iDF<>}6d;|dFdY6+@PU*AwLkbl+D(zSW=vt4^nnx#GeOEnIv5pG zm?nK7g~Cjb@{vB1Hb|l111Se;bNfNsO;I(s4N@qyhks6c4pfu=X>&J4Ws(U~(;f;w zkaD1!^n`q2L242WoTsLE24GHMb2?DEL6ifojqZ(r${%qzzIiv>BDto&(jS zf7;wlQJG{6*0hI0oA#9gqqtgVy5(JHy2T4kw~$dlin4$dWdSM50#cL(q$mqWQ5KM* z+y&`2)nTB(;WV(giU}H4kF($Z?3J z6sAcR#7KcUmpnvuLo6QYGigGM6kHICfojqXv3`oGxlM?Xf(v3XP))ia)=yEHG$BR` zZHQ&0je%;?J!S2us7x{^E7FpJYc3Z9`Q4~|q3O1Fq3Jd+G)+SEfRxIKv{X){rE(%I zl@n>HoJdRML|Q8MNs9$kzSHDDZi{@%x;<54IQ*gD11Se;fAE8}n=aKS;YNDw8%y zq2L242dYUwNV_R2lQu}9(4Nax3dFp@Lep*ULep(tXc~zW-f5z;fD~l`Dary;lm(%{Yu+VhdyU=u-7n*J(W4iaJvVfGGFkn#@kfJOgMOi?K zvVaujK1i{E$_G*o|3jK>b1Pn*Gye zKGMOcn8Gya11S_{f|QT+nY2L)1s_N`P;1f;(r${Xxowa_!3RsVgW`dNDbTBHW zFio~QZBBbAP^T5zyBC^n^N~K2JTB^oW>D~flmpeIAEezBRdd@Qg@O;H9H=J!Anm58 zOxhrYf)At|s3!d&?WU+q+8~8O`{G_H@Rhe(Xu9oPXu8b{O{t3tNKqD$qAVaqnR;h{ zD#`*d?4jOZi@n>Qx%589|}H@a-jAHKS;YN^45$gOp`v4LSZII z`A7$&VhYow52R3-2~s}NXVL~K6xt&zr#%O1bNk;B>!zrhn+I=Adnouo%7JRq57KUm z%A^faDEL6ifojqZ(r${%qzzIiw6B|$0$0ne$VVd-T6bdsz%18Q4+8~9352PHZ&Fu$iH$~OlHb|k+9{xG)IZ#ddr_J3Il}RQ{ zO?xQ#K+1t?(ht&Zipr!7QYf@9NtFU$FRF#6+unty+q}?p8yN+pC<{nY7LcMWAVpa~ zin4$dWdSM5eUM@Sl@FvG$Zb)8bgIH|_(Q=5QV!Jq;0I|pMc$e*g=x|UQYg#>DIe)z zR7_!-^nnx#GeOEn`b^p&g@O;H9H`Ch2WdA&)!a5nq2L242dYUwNV_R2lQu}9&}LLl zdk$2S{%LbJMP-sPSkoQ~ZQ54~jN)pc>9%*F={7Gk-9|}#}HU_Fm_ms7tqB6;xtVl}=uDM(c6r15zp{(o#8* zmdc5=R8FL&aw0926KSd3CoL9G`A(Aqxh?W3>&{e#;qZro52PHZ{lO2?Zi>7=#1y7U zA4s7v6Qq2kgHbVsY0?K$D9i*YAL%n`gA@urkaD0lw;!b46jgKEAccYtq#URw{UGh8 zs7%@*g@O;H9H=J!Anm58OxhrYLVGS(DG>7p3r%;t3r%-;p=l&ic&CZV0#cL(q$mqW zQ5KM*EFeW$K#Fo7q*y@Z11Se`TNEIjsxTb>P-s_meqrT6?GOHGb2mlanlXiG(g#u~ z%mgVP>0ne$VVd-T6bdsz%18Q4+8~9352PHZ&Fu$iH$~OlHb|l111SfpNk2%tDJqjT zNTJ{ZDF>=aKS;YNDw8%yq0pWtRSLwp!9vp=??TfZUTC_5jOpH=$^ue$!hl6tK#H<} z6lDP^$^uf9`yj;vDj!HWklUgF=~RW`@P~pAq#UUI!4J}Iio7*r3e#k}KjgHB0`&*E zYxYl@`A7$&VhYow52R3-2~s}NXVL~K6nr4%K&?qXNV_Sj=C(l!1s_N`P)+(l+D%cJ zv_T35A4oY+P5MFFO;MS&K?;TT45U&Zwhb1V?sylP?(jm>9b^=cqAVaqnMP)~h!Zg|Lv^njeK%G`-?_OxS!$@ zgS4BXGHHVp3Opqli9w40(bX@e9B?TdS*z*pXCq3Moyq3I4UG^H*oAVpa~in4$d zW$K*)swfLcQ5KM*EFeX>4^k|k@`02Cxh)EiPE{BVe<=7s%7NM+{2=Y7$Xhd}FirYE z3Wb><=a zKS;YNDw8%yq2L242dYUwNV_R2lQu}9(7tX~3Vczk7MkvO7n<(yLem{&6p*4UAVpa~ zin4$dWdSM50#cL(q$u}6iUm|Yka8fmMFG;O3d7+K1s_N`Q2T=)q}>#GYsM6&Ngqg| zFcYMFq=Qj0g=x|UQYg#>DIe)GX@e9BK9F*tHn$(7-4s=G+aQHPd-&(H=Rh^-pEh?> zR3@1)HSM9`11SfpNk2%tDJqjTNTJZaBvlH0y{HzN?sylP?(jm>9b^=cqAVaqSwM=i zfD~l`Dary;lm(+8C%N-BZ?nipnH&vLY=hxaM*(kl&5U7n<&R7n<(!LenHf4@jw; zNK55JS}G^fQaO>9%89g8PNb!BpR`y&@gS4BXGHHVp3hlXEr9jLZEHvHqE;QZcg{F~6;hiQb3rJBG zkfJOgMOi?KvVat20V&FTkYWLq52PH(ZBc-9s={#iL!n*O`Gu7OwLkc$&D|7vYsM6& zNgqg|FcYMFq=Qj0g=x|UQYg#>DIe)GX@e9BK9F*tHn$(7-4s=G+aQI452PHZCjB7o zrl?HXAccYtq#URw{UGh8s7%@*g+hCpR4EYW1`ADhy$elud7HysC*#hKyHfyq*E1!!ygJhkaD2*2R}%=De~5gDNK{?{*coi z3e+FuuGv3r<|7@9iYZK!K9E9TCP?{6pGg~}Q1F421GOgoAnm58n%f2`6nr4%KsD(H zX*We>(grCMd?4jOHR%UwH$`RA1}PNUGmuJw*fv;by6atNy2}eqcac#*in4$dWg3~` zmY-coSwM={1*9koNKx*C6bq<)Amu=Aivpxm6^6qf3Op!NqpNV_TW){H4klRl6_ zVJ1lVNC%^03e#k})8@2?0(DxUy?deQE+6SL$>XAaXa)rzNI6hV`a#-FQ8l*>QYiR9 z%7JRq57KUm%A^faDEL6ifojqZ(r${%qzzIiv@hq4}Oq#Q{=4~Q@gS4BX zGHHVp3T;N^wC6xI>7O=tQ&c7ygEj4;(58K*z$mU3n(lfRn(p#K(_Lf~kfJOgMOi?K zvVat20V&D?Qj`UxD0e}+hxJh|h{Zr{3pd32DYBYODF%F?9WIE)KsD)pqo<#uGD)pr znsh;oQq6-{JaQajDTQg$1u;^f&Ls~~-4KgM`b?S-BLx@4VxXFIL#&^oYHkx^q~L;B z3{;bDi1kxcCQXQuLK|WkX=9+8bWd6PDJql9$%?e3;F`#wuu+VhRyU=ux7n(*Qg?E~$ zEFeW$K#H<}6lDP^$^uf91*9nVL5c-bK9F)Cw?zTcsS3m44~2GB=NDEE)c)X~Hg{9x ztr=68CVe1q#iNgJe4@PU*A)ubP!-4vBc8>CQZ&p;{#V%uP$>7I9?=^igM-9ttJDary; zlxbv!TYh#WWdSK(7m%VXAVs+kQY@hIfs_NeEeeoMRTvI`DEL6if!ZJZAnm5eTQjCG zP5M9zg_$7bBOQ#2DNK{?PMgyn3e;(Z_U?tIdwitNB#(>wp&1l>Amu=aKS;YNDw8%yq2L242dYUwNV_R2lQu}9(7w1=3Vh|Q7MkvP7n<(zLR0FZ z0#cL(q$mqWQKsG*po+496lDP^$^uf9`yj;vDj!HWklUgF=~RW`@P~pAq#UUI!4J}I zio7*r3e%(yq)?a%Qa;kbsF=bu=>sVgW`dND^qI6l3WfH_%4yGm+T8wk#JVY}=H|g$ z(;f;wkaD1!^n@gS4BXGHHVp3hnD=rN9@pYN6?#ccJMXFErgl zMgb|x0#cL(q$mqWQ5KM*EFeW$K#Fo7q*y@Z11Se`TNEIjsxTb>Q1F421GPW+LE24` zw`NRXn)HDb3Nt~-f4Q7I9?=^igM-9ttJ zDary;lm(QYiR9%7JRq z57KUm%A^faD6|=s)1Cv>q<`AnO;MR-4A!)VLYwxL0;9NEXu9WJXu8J>P4|#dK#H<} z6lDP^$^uf91*9koNKqD$qTB}QrQ07bH?Tm;q}WS;_jiBy+kbp;`j@jur&y4c0<|$l zDMkvTDc&8B>@ho0KaqNl>8Xkxo1MPET&KnW8pHDNK`1%GD;R+lWa&NO5}2 z6tzi8VVZ1Gt~N>CSxovt3X{zgwMj~0nru?8Hc7)wO!`3zlg$*hNlIawY*MZ^Nt6?l zevrasGevEZQkW*2bGcf9rkAqPR6yEVX-WYFNO`5{as#Fnq}WKa*04uGiaj)pn2^|@ z?kXG9Eo6hLUp8=>21v1j$_G*o_+T2S~v}R0Unru?8 zHc8DRoz@Rh#lXA65>ds=)4^o(Hrl?I) z3e#kha6^nK6+uo`nhHo; zD@_L=<&~z(4Jau{v7sQ1IT(uApkX8%)LmtRx`k{|^~(lM(*P+}Q29X0f!r1aNT(_c zs~QSEkaD2*2R}%ADT@9OQ zDIe(oX-r|7YXOdEwCVe19s+l0=BYh@qkV3%+QV!Ib^n=aKS+BiYLhldq0qdz*9v^)jVn!wlL4fym8Jub@=DX?22v_Wv7sQv zhJq9u)I%Ah*ievSLqUoS1t~UckYWXu52PH(ZBc-9s={z&LBR)74%GhO2Wc-w(V8)Z zY0?K$D9i*YAL$tWF@c%8Yo+M`q`cB}xq*}l zQfw$lv7sQvhJq9u3Q}w+NU@CS1fs_Nax&0vRrKp?R1}PMp!@r^E71}Roh`9R8n+!h5$rz#AGKNNf* zpqli9w3nhbX@e9BO-2>8=Rh^-pEmbW)Fv5&HSM9$qA zQYuKXp&-SEf)pDHQfw$lv7sQvhJq9uCP7nQ;Go}Xom}8F;Gpq z-{|S4s7+E+m?m8iqg3-C7LOc^CnL5d9pDK-?O*ievS!v-m@$#RSf4&=5dKsr@nIQ*f| ztm@*z%7NM+{L|)MilQ}R3e%(yq)?a%Qa;kx7B)zs-~%ZKYEAlQq`ee%P1+!Zf)At| zs3!d&?WL$q+8~9352PHZCjB7orKnBXAccYtq#URw{UGh7s7=}+g+g z-i4;ixX^TolydJ+8wyf36A_CI1t~TZq}Wi9VnacS4I89bIOUsob0D`x0n(`oLq` zq2L242dYUwNP8*j=C(l!1s_N`P)+(l+DlQJv_T35A4oY+P5MFFOHrG&K?;TD45U`z z>A}XvjeMc$(!0=f85f!^ky1g54FxGSXmIjPKReS61u6C@NU@@gS3~TZf+Z-Q1F421J$G-q`efiNgJe4@PU*A)ubP!y%e=c z8>CQZUfgR1zVcQJO_$z^E71}PR! z`9R8n+!h5$rz#AGKNNf*@gS3~THfe(t3Opqli9w3nhb zX@e9B&Ff~Zz!$Y@q3P1Q&~zCWnl6!2L5d9pDK-?O*ievSLqUoS1t~TZq}Z@QiiJ}? zka8fmMFG;O3d7+K1s_N`Q2T=)q`eeHYsM6&Ngqg|FcYMFq=Qj0g=x|UQYg#>DIe)G zX@e9BK9F*tHn$(7y%cqG+aQHPbNCmu=Rh^-pEmbW)FzoQHSM9`11SfpNk2$?DQc58 zNTJZYB-ILhy{HzNF1-s)mvN!#5-Am=*ievSLqUoS1t~TZq}Wi9VnacS4I89bIOPK= z2Xb2!Af2i(9R5)7fs_NaKlnk~OHs6DOktYzffNceLCQxu7!^~PCVe1^CnL5d9pDK<=yuCOl31+f^Y zZQ+JkH$`5PDaC*fw8I6l7^o)QZ}fCi)F!DZOp`8%QL1?mi${(_ETu3_x*$dh)UV_r zsvBbQNS{d)Vx-`LSPWE?ZisbL)Xi-|j1*iDi-Bs=4Y6*D+N23FQfNXfCv6N=lkO>N zH$`odIa!gG6kKz;7|3ty=L=0&-i4;CxX?5yg{PymA*7`ZAuVkPX=y`9OB+I3+7Qyx zhD};5obsI}2Xb5FQ`Xf~h2ijrf)At|sQtkY(q4+9Kg1NKNgqg|FcYMFq=Qj0g=x|U zQYg#>DIe)GX@e9BK9F*tHn$(7y%cqG+aQI452PHZCjB7orKnBXAccYtq#URw{UGh7 zs7=}+g+g;KS1Spqli9w3nhbX@e9BK9F*tn)HLTm!dXl zgA@wQX;Q5~kQ*#CU3nLpuHr(|6;jH*KW!*T*-S(%HWZ}TP>^CnL5d9pDK>17V&Rkz zq#Vd?QGj%+!f^OQ!3RsVgW`dNDbTBHWFikc)Z9#h| zP^T5zyBC_S_(-2g9vAgPGbs2#%7JRq57J(Wy18wTLcs@84pftVkoHp4CT);H!3RCn``q0k&z1?@Rdo7?}6ST9B0+&p+|+C#wyQVvv;evtN3)Fy3^Lcs@8 z4pftVkoHp4CT);Hp?Te`75Ji7Ei_$u7n-i(LemveDoC-RAjO7)6dMXsY$!;vp&-SE zf)pDzNU?Cr2T~5?wkSY4Rbe>%q2L242Wo%tgS3~TXw8_yH0c8=6lQ{yk9069rZ7$V zKnjJKAmt-{CT);H!3R1}PMLAmu=9Za+wSDeC67K?(&QNI6hV`a#-DQJb_u3WX-43fgm^n)FYb zdnsy@jKP}rP-xP=R$vrY3r$zvg{G^x&~$~A3Q}w+NU@Dz767c$*Y%JUn^&S2=!fopOZ$Q3z4_ z@qC)^9GyP-@$CNT^~c{PiS-7(EkJ*y@J>+Bs6rwHTt9nCy)9E%ZEuC+a|MkWDEuOH zg@;lHo9n%Jc=Yfuau#xfFdW#S%_&9Q+#LS_cS=`VgihOA zH)wU*)d!L0t`t|YfrIOMIdVwhH)-b38DQa*&3{PYkJ!*G1pToTD?NQlTR6S}e#bphUdJ+?Knz2V|SgIz8vMMOO zMhc^o-nzMY`kVKtTXzOMYG?Igd(>EpD_MZlR5FqGs4Om3RSHYBV*K|7^{ALU>rp#9 zv7Q3u+&wBgi>gPBrMRpCT2IMD)}u5`swqVo^&>Bl!YDwjOVTo4^g=ycq1&+i!;Jz` zyYU8sQe3?E5zTV`{Mo*7)u4c1R+Aiwk23@@Y!*mi)Wd~q*Y^)TYuqoALOml*@xg*C z#l@Se{cEip)@e%oi#yGWNBcLM=V^J6_!sA4<|HSZ+mE*9#iP47Csnn?zu?pCEnT(- z&N}7y^(eH?w9`!SDUCT`(u-~nA5H1i@XYZq&ckcB_dhzi+o%aTi(gj&$>JR@T=l>n z8a2`M;I0Xmhf4?h*FI}hLqPGbs(R3PM>Y6h9y~Ovq3OY04L%R==2slKFvd#`)#Pu} z-9hKdlt#huzohW|Gt$e+WHy1=-itRmA;s8?^ons7GJzn4(G&vG;wC4WAcbGYdz@HL zmepbX$Sb69>EP~{x0ek-P{5#1O8mq=xhy6aI~#fn6FjUYdf@mM>tQ|71INEu51SJ` zaQut)ur<*G$G=z)+Y>!-{0sB&!sgYzZohx+?xdk7@h|K&>2h#)($JIm7wcit(1V8; zKJ=hDY3ND(i>-%ALk}Ka_|Svqq@gGAFR&i|?O@utkoXttVbZvOhZlTFiqj+ph)k2> zg_ADL8bn0w%z%dOqLt?l@pSx7N$n#5;eO_SOw;xs7)pq@$- z$h9?Y5W#R{kSQ`hZ=CDxb)S{&+gqYnwq){ zDby2hjUTJ#q%hj$Ui!j`b7<&M2$vH(BC)YWha-XbO7sF?x{xBql;d zrF(ygOV=d{OXp<#H&oPfzf1czo6IiEn_ERqj`pZ`24^Ati5WGTBGzQlpTq>6<}c-4 zTGXd))u^EKQmCj~cW+PXQHW3PfACpc#w+>;$mV*zxx~Y$`0gX6xcG0MU&C^i>mU8u zNEFVZ>a-I7L3+n2Ikx^w3ZouId$skvdReSJ7(31LUtY&G>A*Ng7$lSRz~T6KC2*a^ zmCOT1PFdHaklu{W;_5I&wf;!q`BD5%Odh%;TijZu6>%ZO*qk;kZ^+Ig{WH>FJ-@-V`ucyu|U`-V|^d3j3ekh%AmKw_d=T(LDBC zDXwH5q(^N<6Qq!OR2G+dR0=~>>yH#(K#z*a^B%R8FDx8Iaq3aoSyVl0EJbRpqDLhY zbege8^>kXbgx5)7lu`A?JzRN{C@H)vYZ_q_D+ePW*5Ue20ko*Ewcsvzkh>(gu+Tb0 zsKu2)DVzOYmxs|QYt2bI&DGbt{}FP!Qk>^SCg#wzPE*&UEVyW&UV7E%ftMw?J?JWi z1s78``@b#^uf}&_OcSK=_vy-;&rCPCz4=`cJ3GHR#e=~QOv^37N;_`5w zId4{j)gSb-u;8MZT3&Q{2;IK-j=43ui^cGxqdPXYoupaS;YK7@wd9j?%L=~J4AW-2 zrbAW#rs{HGiXQ>9f0(5+i!Kl6j`ol26~E9Vg}0K2xKxwkC7mk;CVTsz-D@Nvg?FkH z93PXoQiKlE`%)vT!xVQYqaEgzFRy=kV9mdSkI8X~klgDuB?u|Jx0BgfRFnU)6sfV`LF*}*AP;f! z-_x<{D7;Dv=K$gjd+^&3qj=FIg}0EMW^S1Gb4zZnVvohnl)|2d#en*XYwfLvPUgDd4pmx2_$1a(r~_;Nb3nA`~E>QqKazcOq|W z{15CN`6Gp&#Ut-s`)v5m90mL)eGt9~oNrga)$M2 zhQNpO2cO-&d3PWVZTwM+`bLc7vwOX_Z``?iFTMv8=gsM{J}aD~8O5LxLIMu3-a7nX z89P3C7)|kxc#tl$DJDqaSFyuLTmq(sMMKtqNa6W!#NG4gI$jah_zM;F+$$*F3MTUovnQyY*kRIH3_A?%>7?MA zEIN#upwmnp#?+yJbJ%m#8~*i^UW%6NnR47@goEvh0zpJlQ{vB2~vn_n^OkMYNL|qWm32(gVE?z6i|P@ zTjD=Ri(*Ks^%oRi4|6mco8@&!QPw&fuam;)C8>rO&3V%5r=al5=l1ZcN+I>z&86ow z=q&y|%^zk}2Pr&%uYNB(i_lwkS3BFg>y7Y@10ls&uTJ;fnNZQOVYBl`DMmfyjm14b zciB-7yC}u);yg-gdT_EG8B(~U7l`4&pn&?KrtzME5fpCdF>zqK4aAcf~27r)HUBI_&5rOx?c#T)+#9>xZa%xSCBluLpk ztS?cD=Qmk2cRsXS=SdzGab#sDF`>Fh;ld$q+38|199K;H`klcPA7)CV@ZOD&u6_1t zc0GyxEnJ-`;Q41_qbV-jz4r0Jl(R_j6VIaeWY3<7WjA7@XYtFjCUxkhi4H2W{TKQ} z8oZq*=_@?{;C)xmBI}DAJK+%|nH*hUnVx8=PjJ%7TvTpCavbo#v~UFVpwWnl?zGTFV;4xwiSx zo)edcOFCyC+8~90Nly=Aa~IR+g&u7?ad~(xn`jM8kiz?whjOB^$PTw$xIA1G%nuxJ zYyMN^A!qhN4z}{sYc3C1AJwKgDg0yQA<>YBA0OLt;Ph}=$ENT_1}Ay=b%I!UJI5Zw zeGjk2ug*R^{r2ggvMI&J=}*s2pFCRp`1s+;v$Kb%>ATU3^>d3%rN~DLuj0#+O?ir> zfPZPENbejkq5#DY|489HBJTcY<9kyn;Ga4v@D3Se!0|(IeuWe+hHnUOoCgK`p^-w{ za3K=IM5ORGeGB(j`1((3Aq)_)siFdrk z!aeHp*tmG*tD~F$Zsn)W9?qiflN8VO=uHu3m}aN9Q-t{ZeVoy=xbW4A$G?@uYOECR zZ>%t{UR(N&ilVbvr)QV0{%|F4te0OZDMkuu0d^i&g;BFL{z$=hE4N-P+Fw_ml4JVv z5`H9QZ*Pt7D~~Bdim_X{^gd1!${r1He|RVDX{C_#J(lANgLu*4p)lvbjY^bddTf9nSKwmd; zPG?aMy%^6k7*|Dw9@SfcSr0wBUTl7_)TCxI{`h7{8K{zY8mWg-#68h@nl z{MU=il3Z!N-pd+m^kH&(^e0031%phErqKS7T`-afQi$*SO9sPgqmt-lQaDG?G|cW4 z1M1OD@iHMMg}1+=m-36nI(_>?O0oZE^W$GQICvPOK>WlM)CqfMVZr=^WxSPioy9wP znyJU?d6GhUUr*y=kJT_b;l>{+_&P0qbgMbZd5e>4H^8mEBn&CWCOPTbe)KHT!)oY| z!f1-vAF>{snIMI@R?W6b0hhk|b0y&t~Y0bm&Nm zw~5j>=t2Hb0)u>GSr}Q%7knOi z%VJy}MyJii=#Evr`g%2~s^e{xby*^l)r0-~8oo#yRweUm{?qKuNQ?K>;%TNgxPFEyYf9~^$%|mi7dMY?-ucWpRZK$KKA>YB+h|D$@&#afzJfd&jGg^tL_gR zpWU(Y{YCna#}FDX3#R4t6G^aYy1;?_p|st)H= zEq%XSxcu;0=>q$iwQPc*BnqpS)_uaUxw7#E-2zFD`@W_B}( zuU@%@-{bZVJ&rGi-bjiUF)l_@yohlzlH$r&8ldAMRwXr-j0=sE;gf1SHSX}gr0^of z1t-_ewz-$S1t(mZM{i+dTqlN8g;#0RE*oDVMFETI z7Dk3(m~P@ok+TY<5FXrxYZ%UhzMzFJDO(#G^2Ln7!)mq%9BHMN*ZdyVvpwKQ$!8V( z9yVutz>!vJdCl)(Yqkd*Dfz5|-^2E74>;0FEwA}K?9BFnBPE|zaCtb-!@qq&sVClo zfdwCFW!BeR9xgB+>~H%cg?c`j;zJ&PiWPp1-a64%3X1oqn6)xFJtGOUcR-A4-#&?; zP|u1(6UCG8rFf6(RzRAroROqdQEBmW5mx~>RGRq@DZKvG%}39k{P6uV>pqAAmW_pE zMM_*6R3*<9Qs9>iPmce3^60_C(Qy3#GB6In`3e1I*TlRED4>(rGqC=9zWTC z{KKPXr99Op1-wbm%JGOt<7iL(qkwmApFVwh^6ly2>HX8QA5R|?S`_fBs9?n;hvSa|&i&`fnb8x%{t)mg zDNqo5rfN@ZI~R zY`zszU|bwOJ$>{*Q^*Z#F!`?u8zHJn@!;gy$=CnE>8?F^@MMsTQoQ*I;pyZI88(;e z)y`gC*A(!_kRnE5q?OB$Z+~>>tHtjRaDLRM1{s3M%Q@C!p51kPPEIMFAA|2!803@L zUdtzXo*#pB7J{{O78}`3v2hj>KSn6-lXMmt)>4z~geOu|QN~$h@ncCy;evEpY}9`t z#dCMs3pfkzw6#9ADaG@5TDo2wpFR5ihiAvs$xEP9ieJTRcc4HK`!&BsVOZ0bNa3Bo zoIS*~`J0nxn0;()Z{h=08+++}6$<#j|MKwh$+LxoUA=Mh*1dznkFMQY{QjFiE_moxV3I55()?j{+`#y3BSV`|5c4$-l?ypn!i# z3TEJ9<4+s(*ZN>Sr&#q^^FWfF zC4N+|5a*3XMXig9(z6)UC<0?e?e55e$TCl(qFN~i6-6mfQ9J9+ovn3oxs*JOiYild zDvDBsirQK4uC~%T9g(L(qoTIF6@@^qD7unZEs;_T&cBty3Z#nK+S*;>`xpxMX`@k5 zWr|Kk(OHCw!ncI&?3y2IrxaI=5w($OiUQu3PCMvPO9XOFq1&bpg(m;}UrsSNe>#$f zcbUQrq?%eTSKHYaLgq<0#c)IwDgGd5VFq$dEw?r{H@1xyrxY*$?buv25UfzZo9VF| zBNO47OA2`HzvFwsw|2L7H@7ziNn#3XHp?<*3i;|t#CTH-5G^*%6!|drr8t{bQ3w|Y z-m^G6o>Wl?pOIoxMV%c_uc#lURTRP}pT!T;DhlB;D~dm)6LkKKWMs z+@d+aDBz+@YRWlQI9Uq#r)U55{po|#zod^N=1L1WID{MjkiyTdAKZwSf6RlbG!*bK zA*cvk{C`6L1Kof8bbvy7b@Ax{U*YAAKQ4;@{qKg!i!#lt3{pIqeE!+s&-d@#zJ2^H zJ}tPhas1%yNs)+B$ajHOfs2jLZ;_4uA1P!hmfjR0a8`XOHfs zx1u<3v7FARmA9fea85<7ycNZPvr>35xSEZ@l^25?IO{CD7+lT9;L3|Z4xDusUJR~g zV{qlgAP3Gli?z2$ap0VxxAyiZ4xE+3+oRUpqhBS%i&PlQ5#UKaH z=}}u=407PC6y8p|#TcB?+*{sG%Yn1b!rP;^cm^`(EWABxi)SD+QfzyB6bH`fwAj;5G8$R|U@Lv}5;rnt~@eGcd@v zaP0@$nqum`o*X%LuU7@mnW~N5>uHMF*Nd@xJxMY7UQdtoUN0u!>uCxv2IIZnj2<<1 zucuyScUr!Mb9CBxuQ%r`ycgDZuQwyb*u9=q)Z}|TJ<{8wCg1C63U7~^e6Ob|ycgEV z_j)&v?%Zs5ghV6I1wv_%y-E5%4#Xo?UxE5%4#Xo{($TaO%>-P&6>iC!O8b} zn!=00c&|6-EW8+u_j)r@jNR+W=}vxMPmlEWsQA8~f5NFLygh32`+AaM>|U=5oN%wF zM|v?B-`AT_QDgUd;$`x^o*wDFUQE8%(-d9|PQKUE6y8o7-`ATl^v3S>)XVG{2;aiB zZznZH=z4QH?byAZq=@%=Gdk_q`+AyU_JwuqeLYPv`~HG&;T&xd@Acdj^;%e(`SIOr z*KZyc^0YP+D=`1t<+PSH3tU{S7IeP9pbKKyW9yclTw z;fI^Wi{Xm=;fGtri{Tpj;fLGBi{YyG;fFi#|6y@;p*DFGeE8vF_x(k=hdVF!>{WZ> ztQUKh8}%;kE3|7_?-IRbEf`mQ;iy$D7*}i2u39k8#%R~7$`xl(v};}O3e~uvU7PhT zzImfvTlFr!>7rfR^{!B{L2&2&#s9FE?$VOo)T2IX^r)BqPt~I+FzZn~SIFCxFYQ&2 z;)`+Bqxd?D$f8g16%VhXQ)oZsixghnEnZE%cdzU~@nS$VQ@34&IPI$2EN7qd zqg|-aqDw~D(XP6;#s^ZgtL|O#K@xVYYljgEvn_nt z!(Vm{hrjL;!PJFx7hf}|#pCeTU7-TQkc`7$cMXQW?ivh#-8C5gy30NM!yzBv9UuN# zVAi8#_)F@1`0Ib*St^>uB9IJk6|wn7~Kx=XrU z!l~|(ev*d2>>3V#-KG7c?yke(uSbc)!SKKP`K^1d;hzOAu7-_b`0FdF0?{t|VmAEs z#ccTNi`nqk7qj87FJ{AEUo3{dzAWt!d8&J)8Df3Pp5gGaV**FAaa$H5~rB zO9a#K*InB2;_%m9(yZy~ue%1rUv~|LzwR0gf8FIC{^1bM@XrFX9wozHQs={8U(ANT zyjTo>eKjBc@@g^s_0`mSdHCz=+6r;_>n?4DIQ(^&bh|YCb(i#$H2h`PaQN#k?I(42 z9S(mzN*oS`e|Rs+bM?;x7gyySDE`g3qOFLd1{<=$=H4T5= zH5mT7YcTwE*I@YTF8A;chj@m67MS%Y8UB(wAO8AcHvHwqV)*N;`S6!li{Y=YrryiL zUtiZ&h{IoZX)DCxue+q%rQxr;q@SeWFS~}rUw3Igsk`fN`0G*Pa4`JCg9*>@&jJ@$ z<#C1#e|;rYAcnubm<@k@F&qB+VmAEs#ccTNi`nqk7mMMqFH1Yb;jeq78Df3Pp5gG< zUD66^`0FmwOT%Aw4Trz(62Ub5b(eO$IQ(^&G;13Ex@$1}b=P3{>#o7@*In-69}e*h z|12=;Q8N4`bw2#{#ccS?i^cHQSM%X7uNK2!UroK2hrhnAtq_O5?$TC>!(Vqvw@brc zcS%1Fp#NX8Q;PJEJ*Jy>$m|sLRKA!scf%P2@ltP{^O5kGSr~E6bM8W#z z0aIZ`3fVWJM}=>{b$UP`Da2onp%kLv^ziMs!NWdRswg}>`R@Ct!M1}z|X_D zkf`(n#4JMruN}kX@x438w-0U)&V~ZsN{>LZKt3G*QotJ|aQE8B2gmq<_`~WuCMaN$ z6v{yAx%k>I{E3`ZAcfcE$Xf@4pTM91`Syl95DBO$Ez$BdQW)*DZ)IP4Ht4&gFxqJ^ z=L&V-C52axo}D~teQjbm&GcnH(k}wt!eQkpSzEy*zCvVoV}-BI-dX40MHu3PhZ|>) z&a9zN5giZVFe_{Mn$N?v2l%$qL2qQGj)!nqna|qtdDuUDa=-Cg>!BXxSB9l6!q?%^ zQC8CGHJ69*4KuCQB8BW5W`ePw8Bto`;L3Kj$tl_l3l;UV*zKV< zq#-F>0wa%~Jq{GB60pfX3P2?A>QC=4eoq(q-@ktqhyN)w{U84D{{Q^RRCt5FZb%1^ud^LXYZ1`SXV+w?$N#WezPX1PX<0D>;e-vVj+Cz#3MJC9EuRMo^DeohK`P$m#kB!zDto;@1OASgwy5Q1uj zOHuy8$^GgS5E)K0^MIiIcn-Mm4Bx?vui!L}=YTMeN*4#;t1~ zFAycKW(5j(8Iz=;{TQSQh{_I>A_cq_3@(qio}La*gaUpZu3=e}9F777TnhWPzOw{E zz#FO%qH=){aFG>E0d9*-0a1kjE8y$DkMG;xZyf^O3#iw=qxTiJpHk&@C*Ki zJ_#!%f&#v)_~|hL+h`FA2;)M6zFut(JcOO!pH$y}#iv^;P>`kY;OtTVEJ8g<)Yt3y zt92m!LZ2^r>hZfLU$1txM}!pjzyINw z#>SK7@!8WS$43XB9f=_dpero;w0woW5#RY}hHPafXKudS{2HrIR0?RdY7 zec?3!o~t^BU5#5O={tVUzOgS>bU6Mf#cvH)DP8m1cf-+1;rUPVo$$@ikH3F*CTF^_ zOy5^dCf^KKJ&h`^eH3sd?4!nd{N$%yRnR+fy!m z|KwB}kQCmL-yzVGlzTJ^;O}+UsE~$E_>YT&!^1m=NH2m2ul`8k^8Ls7)riLrkFQy3ix$s%_2%pqcAM8d4UvO zzxnb@aaeBbmJ>A|Ss`F=d%cZs>(#Huk20bV19s{=?J8h*nZDpV`JjN;Zoc#q3+zcZ zNc+R+&OGc6zF2vx!Y~IZT+-eq^ea4E(SWPm6#>P^u^*Dcm3yb(VZN8zDpeT+fC7FM z8Y_>IE-~I#p&l;Zef*zwhP`zhpOoU4Aw?E7B|}JY0S|$$9esXi{^}#8_<6cZN`ZJy z{wUz}0%Ed@3lwlg5tJZCuW%huz$Hbb-4^etLcnct{UL>)l^EpQ>0b(XR}}<^R-nm;SXZIy#kv_>~UWW2|a!fRPqs1oq#e*O+~?jD{#4z!V*{z63!9#|0< z>8SKGo*ZlcOA7Ddfz^6*4`1BAy|eyrva!2OFrffEG&{2%@&-u?__gUF9OW?K^6>JP zPX@P{AwT^?3iiVy9OZDp3ZwP#GJdV4)f62MIO@fDIClq+?OP_O9)4xE1s&xv;cAOl zKEVxA%LFOd{UIFXFyZoWexGI_)|)u7KV&~koxKaeM~$19;K6zuXxsySo)$sfKbMDd zN6#LAKfOQDQR5Drmg7)w|0LBM>$Nm>fvR~A6nJW8JjrjgTX_3qg7lUUb%Jh z?EYUHF52}Fj(Sn`@XF0^A3dHvHp5Xb%)>|j_5De!HQMzMj(SlZ!h?Oes#PsY9|xqL8*JQc{p=r4e~DA!GqSJdD< z$%9hP(4l~H^gfQ!(%2P;-hgtVw4h@{VDq1l;jt{zHxZ)ZcL|GA+-0aucO2I4c7 z@zGRJ_~_Qn&pz!a$nVN&;6fg*k-`N$muwu*jU{K10vGsg-t=@WC|tkRSCFgmLjRdb8jdSJ&e&uidOx{e*ybQ%x3uQH4_A zo#LO)zWd?3<8Pjvef!tyszCwoC51AOB`Dxkyg_q(ukm|D6d*Mj0~foSe@f5Hg2||0 z->Q*GaPHqRYOQgZPVhV9*u$^d?e1wyCo`BRIa z@Wq{5_pmb2bV&iC5Cav|(Zj{NcfLG0JYMfwO-c&VCna#9x9k)U6;>;!0snkONB#ylbf{TADNWaWQD_{c)1E86!6NOyZ3JH zTL!R`0)!7C5Z}2F4vqg%!076xce7=pgGElHFuHQ!y{Ir)KtS*QlLD_C2=8GHPlW=K z2Y#dU_w-iHaR|r0pzwNl>91$U^iFTBkt@*iem*`1mkJLbPf&=#Nnvy)$(vbCh6N?M z`hm~l94?2}u%ry(G;;-tEq>paPV>UQ>M+)7u%Li@MC%OcEJH;V3J4B6(m$kdF?5*D;-!3bw8W-b^tYgj4r*!ZXl1%wZ1WI@^S++i|>;UvOP zkUOZLL;<4^d()&>bV3TF5DN?H2J{*zbRd=~Wc11uUZJ%*trfRq^4+4jLo}A&e!UmE z3+#8hT7SL4 z`V{bs@RoWOC5K~YP&hjI@w8T0Zt+A%6|$&W;oYE)rDSJVnjJ1P8CH@ zS+T%^*6XjcDL02u!1>R@dN}hWLQM|e;0PZ0u#~F#UzdkhsA^ktHBxvhJ=p&UkE0Gk zJ(dp#Mo%-OFmJLT-$`HO|{*(L14Z!rqCLhKfuk)|pLj#jz9{zgP z$T(~@h_i@7+Ec zo(Bc|bGoqVyZ55B(1ROiLkgoeLGQ%dsN!BI-Tjcl=snKcg#zE|B!SQ$MsGlp2lGCJ zJY=^ILt;}vemgn152+M}KyE8U8dJdN)cv=y9*h}$n!rP*^%p#tbIsT_DB$^Lq?fG} z35)#{-U;XE`s(Lj^Z#0Q=P(#Kp(eu}N*0x`8>WEQvb&d#LKamkyq@2C)Do0}7eD7w znFIyAQQm`<8WiweIEyk$G$`QJyVv$V?LG09cVS{6j?q6-xELON-o0jg$1cx;})s%>ntd6@a6(l5PgS>OMwFGHy18Ec>1?v`u^ilg%mhw3)#o!GB3iwSL{=>k<=HLcYv}2)8 zF?jgaN)ZDWJ92Ng{^L*8a>ptaDTEaC z(atA%BV-vg>q~E{)&+$1s>TByiTJMHXiu3f|Noxf)1^izr1qTij>})g>u*nOzPM$u4AFH(k zC-qBgVqmJK-7LMAPh2q|2+ zPoGk-GgNI61Fa1D*u+e6@KdWpRViYil|mnzG*fiGE=+qAr9hySLLZwLDbBSB$MMN7mq^6u%%38dQD<1O>eH?dh}Q(5qhB+uhh)Z?3kq z2U5Tr;Z7|@W$#4&|J7X!QyfQ<4#$EdkkG?6*2A~**z4N`R^EVNc+Bpy7d%GN+#+CS z24jWeVgjK76Gp&+WXpTL-*vY_dOgBnMurs37%Z;P5?l$s^ZDQG>3dAXSb z@I^#I(`Zix0iy>P?wW0~JduTbr1;B-gq5a31QPdNpBx+<4ZMsjEb!PX0RJA5u+x-l zfT6OEl1V$!stOEu&Id<>z1RKMr$@AbidRzsV9L)&aWNhvRY_4&YA}pQ^%Mr20hl3m zL3z0b!}Yv+3ON8UQwwsG!vVk;rns$a_j*sa{kBL!y9ZEG%BL{ANM(2-DdiIkS4m=ha2)3V;I7k2Y|!7*V+)f2aQ*!7pM(D1 ztCz7ElmL8^1uYM2OutFLPrW@8lB}^$W0;aGa(MyuZQ5TfB z-{~&f+4!KoFt^a0F;kQ|7gWX4Tt(fp$i+JWD5hJVU?7Q=h{P=4;^PuFK2c)X_LStJ zf%-ZwVdE1eR$>zKcrJ=d*!UEQdrqtjWtpI|fJ0e=?=cSQg2fGqJXS!H<|*&xQSPoAnMIoySZqxnWGH(9`$0${#b7LpCgC;7rSpXn^ch^s^KH^ti+jY zPS2x)fDLP&CxHqbiI|{nsYkR?B~2ouX^w}le=@;-PJOf`F$al;B5~UaP;kEz6i7 zp&k2CAgwtm%?TLpIw{vTyFJ!1?aN{b1ww;piViTKRm>{6?K#|$uz>U;({5{Zb7QSG zMH0~qA|nCAEt-4KU!hI<`zwP3+BG=mr*8o0NU;l~0k4FeU{QkB1Cq1!3|UwED*u!HVcZ9XYu&xW&fp+Abimo1 zl-Z9zoE*_J{?VY8O%Up?w&{X;(ydKp6t;2l9TL}n^FecVdWIGO&V`jC1M-^R$sv;f z5Z~S*PbF&c&mK$yzlEt*;T#^kVr$tU68Zd-2?lM0Z--%ekXOa!qsVKJ220yI6DtIqU zJSOv01>)K1BpdK(AJqp57~-3rnN*oj$w!h6xGreRk(a?^J&3_jkH(~?`Zm0s>V&%^M8GHe|^{Ve3q~ z4RqUl2S1=Tqhyw1_%+FfJ5&}RL%a8Tek`_#z@RI7_;J@qTj1!|BpcASe@xYNlOC&s zfB?fisVBt-K|?c1VswR?YP4){Gq!da4C5k!R)K=SPe+mjYFgM8d3Z1knhQwS;0sBZ z8|&(E;3>yZnS_FqC2nPgb-zD64R-y2gl-;d zA2eCH5lJ@O;g@v$xO>PwCA9R|HU$j7mw?gs1KZ#yD=;O=h8w>bDt-zA!-u-=BJ!{V zz%?pO%sIA=SBn7nB3QwpObAh=Rebmb43*n zAcLq1)nTnLdvXR6bX_!p5;;C)h=e5Uv7r8P4XvzUTjTZi5-< zv5m;H>7o3NcYl!D4U>HI7+Br4m?CU{f09cZ)KLJj>eN_8tviA0?zh(V#^kuc( z`(|bP@zR9c*wE;jocO8eauESz1KRdGbk}UeT3WE-Kg5O{i1*t4_#JfPgYq035@Guln0Of^xUM6+-xZTJC+R|Fnh-ynUQxDE-hhLcid(3IB7qIPhz$TZd+6^JfyY12#{G>u$BXt@>7ft@CvaX&3_=M)@tq zh`$I801t$LlVkS}O~EAP|AAqI?wBtN6xa{<0|`k%shMG`gN-~_V~<%3_^sDW5`5Kt z-xv>xTl#{nI$jgzIs*W|CFbI*gupPgw->%0&{$xyc@+;o1d?;kCm8N`2ZPhIlULbW zqv6Hu%nD< z5+<8KlQ?)l1%P$O2B6-j30&OfEnt};V#5q=wg`{G2J1ay8OoZZ0>Hmn7et>HqS5pK zac0A=jX)S4U@%QJpJu{3QJXTQ75dQ_`CALy-#e!Uix@GzDDOKDwdD+KFmL$@XiQ!K z@Fez*u&aA5-!ylbsv(T=uP%A|| z#WrM#cKC(sqS0K?kXzu8vr!@UBO0_t1&A7K>ecxHjVfhwkdRz-?4WKoO(*~`Z%Y7m z5e1IP2X2j_zG^nDIZ9z6WM^Q*<*Ohk?D?HS8ukg3a$rLk_MmZ{Q6Ba;`+bSnr~STL z(Xyj-Lt_VM`Qb*l)!OP%<0#PIodGj#!42jHj_fyl{p2ald5EMp47vbZfwgIkB`|y>jz-k? zciL+=pieuc*jB;@ooeC(>Ef8CZK(-Ta)9AONx4H_Xn7g{ z=mO6G2o0LiQX=5xVyCm#_7u3Vf?Nm?3Y8P2V5B-~hxT4hlrTU@%vWTBjZ}%wTDOxV zAwWpb%>Pn9xe_~_LxqI_}`sXLCMqDYLW3)b_Jy&%J(S*zmbL>q$hd zDG(xbl(`BF8ni3h-RJ#h%U%090sx(HClU%|PnGf0Z;qpSk2^E-UX=~N-~3z%kQ5fD zf5r{et~UPq*ZIkxt7~Aj3=*iL`0^*}Mb88_@-Gn^04y;=d3d{*?-ZOS6t(vSz6OtLb0{w>Ld5j5+u zCekklP=FzvK*cslGFB@7FUbZBcoljI4Ecap1O~t;M=Baok!%3)Wia5SO!;F+VK%^U z)jX0!_~}Og?#sxa+9HoJ8Gzye`&;t62I!P~fMICQ@7J&}0O(M%6O)t*H~=aohWSw% z@W=rM4LLkcO-unk$$cj@mp1bB=dq;OQ1Y%+&V^?K;P2apE9P9$^w_&@)?Nwz4k_CI(6d^G)tW;$~p!9;CpQoc`3PTEFrPg4>QK^X&j zd>l7PI4ax!E${(OBb#|kjIu|sV5Sw6xyJ$cgVb`C!)VTR-nE>i0%3T7L0iS}pkG%2 z@Fly@rUc6EUMRjm0tvq=h)V!<5eaQiA{YLZ4hi#OYdaT=s_G=pd00Q>@D zC}U#78M>QMLe>Eret|KR;lH<@>s`*0=dZ9qqZ&Znj%Yq#t$*$N!B5zW%g=x^=(3{> zSOXJ}ZPVDhM7J-kf5V0=lybXhfD-`iG-IG6U`38{dSAeRT&$h^7@0FnKLTLq0zgNk za;!)sHfV>JBu4@0NQ5huV!1dy8>E#*2CQv$S{Ez}N|{y`40Hri%Yss-l|=@0MAFKF zQl^zf26QBn%3@??eIxDNmja}>{An*12h5M((Ka`S#Y^GLyGSyWRl#v&fZ@7X3ygX& zj5+|!rX@MbApzhMG`#x%JUJdL&`{OfY-4({K3mUxoHOL8fZiKHYtDPD{-BjWBFtV@|^WfQQT=sC*#W%&OIvM1dt> zxYpa;T&I;sp&RK(0CdT426VUppzXrclg^L$0{~MNIV$kvZQqkN4HzCo9fgxsSp*Xp zM#M+4d;)NJPu`#+oT1rM*q10!fkacDvn=4mWX+!-)!TgXWWANok*Y6o^#TS+)Ket{ zSS`_5%q2$HxRd?;APb}q8+2}x03-a}mNmyKv!9aE0R~9a`-u_^tdJ1FXn&0nCHDWyBg)AJBI?ds zcdNemwogxT|JhpYxz#=Zy1}&%geL&F+osySU0+45MR&Y9-Sg;WW!VOD0GNBXg_0YZ zFpN{`W!g58CnaU+b+Qf^KIYn9QO@mxZFs=H@pKs;0T445ruF6sv4R5<^=+DqHZxyy ziSqj=W~!lE-)vC=5&K31hWnfp58RFkbBmav0Kk{va6lowO-f0u0}P{_njK~Rl6?iB z(owhE{JB*+7%uOJn@$#8h4G?wQkaW>dWgjf___fR=WalYmEjU zhd!96mmxQ4@OjZ`=K^3JtAXOp_YO_DXIm)(aFbSk3c>tLL#Lt8Po}tUqPPiU(t8EV zHsD?ILNT}CPQwG>Hitb>5e@(z>I|zH%;7X!-DjC^U~lQ&*(=0%$BD)%D(y;aQUYD81^DOJm+09f<3HZ1GVj6*KClTDFBA{jtX}I zW+MxRijH_|U@*{7(E`0zd!|Y6!=^vogC%0iG6e=eT!K;olqNBtO{av?|16fERLK&< zSd~zu0SR3Js$*(Mkr|Vei($NCu1rGLPO1by-5{Bt>B!$nHeej5usFexkK;sO0E}uC z6v+wz;Sj1a)iiCyeshW?dadsGJw?uu17J*A#SCVP!7?G3_NAh){TgMBK-WBljDmUjRc5wFE) z0ML#*0baz@?8z&K=ZDA92R)*P#Gl0v48-!23HnDLOG`CX{rP7-_m!T7_rX9C$Gh=o zBm>Y1bqus5K3`(mf?_0U9FQ13|8LssX*>|UL^Tsao*7vHlWU_CU>KsZD#|7ML8pll(564c zh6iA{Z{>oxG!rw@Wc@>lk%z|>HnPOf-bwi_NsT0+WhDI-8VN2ja)CFQL@r8 zXa&MRFQ1i9QegNrk0>K1`COcnT__1vbbw*DIOLd7^Z7_F9D7M67=~Y+yez82I3^__ za3S54%@?s05+nP&XZ<1>0EAX>@;5CMrBh-+krd}*x8(8$U_7fgfKz&@Eer#$mq-q9 z%3+9ICWe6mCW#>yfMBQ$IdO$kwzLswmbrrJPcj9G+q5$Eh^hs1JuTLqI0N9JA5lmU zcuXk$PcT$gVjpMb#vIA69;RR1Jp?TsNJwb{7ud!&4Bi%v3!2gt8weK=7#sF?UnIo? zZ~+BuxU+wBa$?@oj=F1c)~*u(_{?`TCkVK#yxU*FFuYHfRawY=mbn@@CDwSUxOUkO zSN6|}eF+;R_!wtt;30B~lFCJ9+n#?1!zix%A{hXLRdI46t02myz;Na0WqB^dQH-%cGS?($w5(3FhD|%a4MkAF-D#o%uE+>0Psmxn#3?O?Q;MyM6YWrNN>XaVa7l> zO`jYNCYvP{t&`1IMazI;`X%Y=22QOMPjNO&Dq6>eSVe1WpkI<~04{1nWwTl8C^VCE GhW`ieLpU)2 literal 0 HcmV?d00001 diff --git a/ice.paf2 b/ice.paf2 new file mode 100644 index 0000000000000000000000000000000000000000..7bccbda31af336ebfadcbc35909fc2656382de15 GIT binary patch literal 21979 zcmeHNO>kS)6*dV8Nu2*5pg@c4LV$pTEGNNnAYe za>VM}XT|%iM7(bx?b=SPc(yz!4OgX{naY`K*ScB~FyqdpbIw8{9*@VI1t-#SV_4u- z%8}@d=gF^cy91GEAybTeHc@C9^*&o$=|?2$cKt6yAnp`TtVw!>qMLV0*N)v5Jrju* zv;O%+VoxMGTk37e!9hs%N;|)`c0+zaTDh$?n(s@*)2XS+#6W-lf|YYJS*PTu-8nm7 z$vQVG&h`ogZ%&hz?X^-P!^cNOaJF}R=;-K(bz~wnGA`vpR^EIhI-ihGj?U)2Oxf}) z#iCa#KQ&vd^d~kXD}LE43|HK|*tjv}7l&QXSH;!i?%X-2^kUSGL>X1P%u1MxB2Vft0M!_h8o!*e&&3z|XQjpYNL1oE-&-pCiGg_B3RK7P?o98sk8f+q zjY}fC{{}=gqIx5eLhim1Q6Zy}gXv^)s$9vso;BYe>rW>!*`*h<8MhW)>HXJn&4@>> zJyw686;Gs#;+4!9$4{4CahUg++Lg-L1;$_64s5tyYt=UUOxg4DbuFugQps3uOKohV zoOy&yZd1<{dwl>#5aEO;46wujH29m!0gGUmADjoxE^tn051Ir)14!%86KR zecn4`l|8HA6k@rx1t;TIN+McvzAs&toa%fmx31`v++xlt#d3EXo!ULHN2&stvVKvj z?2_HLH46LGHZ`Q_gIrk}r=<9gXGgtk)JYR@Rwy z=YY;#wQ6Vbe4$={Z>@eb@6BZLVo}*EUnrtYUDQ}2S#Pqj)?_Fv9o}9mCX1D0Zb9a* zkjq92l~}IcDs^NimfKWoHIf7}4P^mOD~r7i<>#FS`e+fT)y0p&3srzIogT4=f#KGg zzDd_fieExiCuG~9OPR9WhGJ2Qbs19^{Hlz)o|7`&&FYbPa!lM`DT>srY*M2BS# znCbV#>_T?$;xm*`>I=fb>Vja+d2@&fG}};}P%%2ZnX?6YotdOYiLT8{Ql(s6ouBHBI33kFs&kN( zgW1)t&at28+?Z$#>c(ZM9@lg$X084vo9I*8?&jJw&Uf+V8r7GTf#w=qKYKRWrG}~X zKy%6(Mu)b*J=WMfw6&-sAI#e!FBzHZ13mY6lk#Pm4(9w8_=9D=S^I+(B-*4g)%B$X zZdqNL<_^}Trn!Tat6A>qy4EZt!KxQ)5)!p0hQ@+10yt0ST4+#RPn)$qSZ$kT##-F0 zDV+6l&0?e0@xCUZtgrH`gZ0;LZDVNbn?$vdw0AY?R`aLtRZ6zgIEd{K3?^2!jA#5p za}DZa-X3f;hCvdxW|0-&4nb}(j?rZ=KKX?eHOzfnLS$!P?{75Jpsk@fcMDBg%2;X= zb?zzz^-yRVY^#QzT|FzPq;_OzSfK6TtYL?y5+zn$98@D^(KCh}z3$Yv`1wm6MQS^k zhC`DrCl%ST*tN40a@8G*T|Y6|4QCd0e6nk&BwHPcY}q4s-KJjT|D>)3QTLYQk>b(I zxHd%j6``+Gd6ZF)hxsrMc*8umD}JPxmAqA|ZnaiNop&r!w??a5EBSlng>Jlf-cxe# zlRWBv8nPR8)GgV7$JBSy*>{v-8~cSa9@atj@W-D{1eNlm>t~H|R&4;c2)21%rOXH=cIuzhKahv4p4H`oCe&k8z8q z-TJ?2(2uzSPrLPh%baf8uYL4kp6EQ^l#{p{+Xnrc zI;8&{gZ|AO(tpXIe@ln-ziiOIwL|*9YS6!}L;7Da=-=KU{lA(!wCMh0M~C!(&Cvfl zJEZ?rgZ{fZr2jR8{<}M*|8;}@FZ`GF-_s%eZy5TIa}u6*?|Yq#HCTXFjd%q4HE_~W4=Nx%QQ(bL0{Ui|aQ z6G=(wmrs6hWjZBg_y_pk?05rPo}Gy|&desfM}$Vc%j%9rs)D-D>plhYHvjU+hoR@w z*Dj4diwb#AhHX4+(+-@mP4FU83}kVhxG!O@vezD;*QCL<9LT~9Q@$@L$_kw0$bj# z5pUe7neaZ+A-o49UU9Z*b)Hx*`%qxaJ4ND-yF?T2&;1|wgP+I#9~kp4mAK;$)r31f zx{>d48~39RoQj;h73UXV%e!OZh&y8w-jf}|d)Momuyh0u?1D|aW2T+BTQ=GGywJ$k z&bYulcq_&Qu;raPal~D^3GbsF!uz*t-hBagHUD`3%Jh_^ygzC7-emU&Z%!POcHD0* zm-PtP^BV*Gfo}^Ye;gMY`Pv!(pX}Q_4n6dPWCOjhjo&0_2fjs^>^-5{fw!IZUi|x( zleiP*y-ln87w}I@`!uYuu z``7dfQs3-&UT)(UKH#@1;*D=qCcnHWH1f66FSvh(9^OMsHqZ;(_-%`J;G34o-n425 z-gerHbpZF`yhrD~Ebj}$>jTF-1Aa3l-uPB(^2_NC`Q_&yj-KujUGztITyefOjjvY66a99x zk0bbo-c9?Y8-pg<$@zH<9|Jfqf~YMQ||s&NXqZMI9vQp-3Q{V0U92(!TkYg_&)}|Y2cn6 z`w^u0#tc6E9|HHl)Pw(3;C>RaQ1_U;xIbH|%J)l(dn$Zu0zD!x?osef66GFwagK)$ zlzZjHIhi`JpT)TiIzY$&J>VP2MEOB^5&QUdh%#Q-%)VgF*8BO4M#KLX&`*4i9+DUP zLh2coJoY2#3uLn2v@@S!{~BwcSRb`6_A6MI8X-tjkc)6{S(GD{Z0Sl zKNX<&$P0fno_Zw@e-n558$JO){mpm@<9tkb5dZ8aZJ_Pglj;3BF1)1So`&scC))Ex z9eJ^r(B-_O(XhYJX}GsxJKU{62k5vX!8oIQ#t>+FU9GMBk4Be^`v}r-X8^f~i(z>Y ztL)2v@)7$=AK-3*;~aKio&XPG8BdSA@ELv5D|z^gKB3Pz2I(`#0DZ<7fDY(nUvU1^ z`}v|q!*it<>1^+8eo~MIYUwh|IjYR0ApfUXc%L(D~t2|BT5ETNwmql_ikb5LHk#eWP<{$^Xo z8QP9%ZK+qP0;~>&XkodGN6O{;1G(c`Tl`Nb+?KJ=wz^G6w6^%xi?$f!#A37Lp@VHX zPB@N;6?mSLm)I;Oi)|^3Z7EB~c|wzg|0aa{L|)3;F8r_o@1)ii-`REFKd;efqwf2q zaE@wiai6EljV(cYdmQU>t=>qQOoR4K|x-u-`;OUr57$AoW;5zf3gr(L_UkO*G(Zq5*3Y4Y-?V@PUa2f0$_S Vjfr+RM8mj-?+{z-<=v>t{{}hUB@qAs literal 0 HcmV?d00001 diff --git a/ice.pjt b/ice.pjt new file mode 100644 index 0000000..14a6688 --- /dev/null +++ b/ice.pjt @@ -0,0 +1,71 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectDir="F:\ICE\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="ADC.c" +Source="bios.c" +Source="cntrl_adr.c" +Source="crc16.c" +Source="ecan.c" +Source="filter_bat2.c" +Source="i2c.c" +Source="isolatio.c" +Source="log_to_mem.c" +Source="main.c" +Source="measure.c" +Source="message.c" +Source="peripher.c" +Source="RS485.c" +Source="spise2p.c" +Source="tools.c" +Source="v120\DSP2833x_common\source\DSP2833x_Adc.c" +Source="v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="v120\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="v120\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c" +Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c" +Source="v120\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="v120\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="v120\DSP2833x_common\source\DSP2833x_Xintf.c" +Source="v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="F28335.cmd" +Source="v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Debug" Settings] +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.hex -i +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.bin -b + +["Compiler" Settings: "Debug"] +Options=-g -pdsw225 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\v120\DSP2833x_headers\include" -i"$(Proj_dir)\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28 + +["Linker" Settings: "Debug"] +Options=-c -e_c_int00 -m".\Debug\ice.map" -o".\bin\ice.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-c -m".\Release\UKSS745.1TMS320F28335.map" -o".\Release\UKSS745.1TMS320F28335.out" -w -x + +["F28335.cmd" Settings: "Debug"] +LinkOrder=1 + +["F28335.cmd" Settings: "Release"] +LinkOrder=1 + +["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + +["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/ice.sbl b/ice.sbl new file mode 100644 index 0000000000000000000000000000000000000000..d753984cb0a614d3ed0490a40bc87448e9e28618 GIT binary patch literal 13745 zcmeHOYm6jS6~1>_d84o^0>bJ5!h%TK_3Y{ki!(d3JB&bfc4vfz9UOXlYG)eyMR(8c zERbkWVsL|+@J|!{ArH&7N6X#)NP(pKTt|N@~J*+`uocR#^0wApAsV7pbzyQnSbY+ zE8&KBrc&P|cFt1jb>d@ZD|N#;O1(q;{d1Mtd!ADNC4TzDO5ObtrOr5CsUHy^xIn3` zTap!a02~zkMdVc3ZrSA9`l_NfWky4e5l{)Vdk|l0@T&W8$Rce;3dXb)w zUZ&I+wkdV#CzSdH@sUp|wS7XVSBM|HoN%vD>U$*nC_UdIp1V@1pAc`O#{50;)KyA7 zOMJoAO8txE8uYAeSL$cPS6!pj*NFc}e9N^;Jx{##(@Nb>eBgA_K~L*Csw?p=pCKIL z)2S`0*DK``zeF;xpP|%!1$y^cva_hv<0ShM@q?C9ZxA1|mAaB-b~t1Y@!PIaU!wm< zryruf-=yzvQTg9e`Af*Y`-x8wUqjf(h~FXJL-NlN-$T0Zq&glazL4tp5b+;~_fS30 zBa9n~XG!OC#OGh7RG0X5;vH8j^{wqn{grr;>iPol#Z=b^iQgceqz=knNXJ zJvWGdO+0%pjSK46;}=ldP(Qv*yr25)ZR(d7s14pAo2;{y`W^9c>c`9Rp8Bgref2Bq ztE1FU|DgVUTzVeS_NaEvlD8?e|M+_cO?rA5%O0eX~-SRR5F7loghiurm!?MGhL`kI6z^@OFC_d{*Q$K2PpUgNt*^>#{OyZ+jIN{ z(maFs9iG}5C|{Gfz=YqBG{9XmPGjF|H}e-7wDGLucX(=-a1Yj6-K16!1t=ViBm(XW z8h5cB%`mn$osqymr!JUp8uQX!;`zqESfM*fa6?5X%2p1PFM5my89z=v0ql+v+gN`HFT z3ivym5PL#?ho=spqf@o~qz;e;HoUAP;P)j>aB$zAdHx1@_OSd8PhF0&W7{DMTtr1l zG4`4%hXNY|f<3d8*FllMYj(A;#w|_$F><(YWRi5rH#1Yyg*B`A&~mt&KLMFz0>8sk zTNWWl1$ekal*70bC8HxbV^O?Fs7QYz(!jGz(iUd%VaqNq%`D8@f#Yl}S6huntGU!| zt#_(n@_K5en)Cd^sk74SS=Nl>pZk9A?_)K?i1r?o4>7 zvR?1aE$mCe18{j&E?`y0=21Y6Rg&#Yi`B?ptllJP3l2DKb8eH&gok%E))RvP%3BBt znlbpKh{g(J3j>(fnG#rAaOtC4TdRg?Yk9LHLC3N-LNr$S$uDliF&dtSSHu!n+lUdP zT6^16Vk!`MPbLw^FcomdF3MId6BJhM*bPY1HX=^i&fFo^s4TC9hic8Ro0tn=-abm; zjJYGB8rza1m$nI!#n@{|(snkQ<&Lvm)0JjoFCclVDwrpR(@{UNtYI}^B zMwW^dBOrN0E+NOVl<9EJ@pA#I;>}!=bUj2Qm^e zV{m?tMR>+eMKi>9Sc$U%N!lJgn(f-CG}?9P5`fAlM-nw-Y+maokj73$vYQBw&oLyj zwzH8e4}7-XI#{XCcUrwx?`T`v4Rk*3lISDborN}bApO}S!Qu=CXCRWaogdqVm*;&Y zw^ur~%E5X_YYDMdn1&3$#d@Y=&)1qWg2TVSXWtd4 zve3bIVNyrN@^KXyxA>HZ%g}>*;BH5fcC*ng&u6A8GuQ3h8XgYoVzUPwe5WUMy>_#aF$a8qt=T)2#Bd;PpXlGEOTM_aWSmYK~?OcAdCD6(@J@{o=GHx&w;lvbK zWJnXWn{%Z7$|Q?yp+7jsgWut)J$TjG`MEvIJ?!F>^%zQU_KPe*iln&l+{boZ8}|>T zWV|bB58m*;N|Uajs<^A%OpMzWPIQr_HudG!Ob~glo8#L`pd(8KSt*jV2j4X)1!ORU zIdw-0Qw12`^WR+jd5n%4bH0l#pgnk;dTVvL*II6bjilRAf-{3;2~r`&jaT~fy*I^c z3Y6lU8d*wv@D`$A-03L6*+;TOS`YPkAoXBwao&zBr9I5?Mx{11$C2BFye3Jcp)Y8> z)EwVWLdXX~?u;bu7tOR;qC>6KPNgxiyGG}6ON-$~r8_a#?2>;du6M#@a6p_>#H2Wylx2-?%^mE;o)bkl!%7y>K0FVXiiZWnIRQ=tb;S>WEt(l+r-7%@tqyvn(TDMh)lPtvY z@a~*tnUXJICilXwSV%&avrnZgncf#PCFhwtlSqip;_OW+uS=N2J-F$lxddA-5QL#gYg%s+B2~s|OCuNpVg=eiw0Ci4~t;NHPxZA{k@} zBjZ?-4k%6)mgv9ty8tNX#D8e!JZY(U)2UHw0$XaigZ_uJtmS(h(40GUm4;eQ43}zA z=?}W0O@I*@6I3Io99~S44qP+y{?~bV-3+yy1~1iaIt4mSfMbEkC15(h4|C={-ZNq5 z#7@`*zUA!M$KOzfGv@gno;pA*kBh}l4f34XFXg2UnscS?kKYpStY9QE@{y@7Ne2OX zVtRU^x4u$qEgyCY&it)Y{U!ENbv5#*IkO3v{ObaViDn)P&;-Hy6E7o~A)*rf3p??v z1W7s|w;K6}vC!E|0Tw@mz>gp#4JQ9sm?przUQ7tOuok}ukfh7eekKJyQquyEf2<(^ zu~8Wv&6JB*eC0PY41nMd3-OB&NxDocmZ)9he?MryzIjl4Oeq4a8r)v!~Xy=Wi0Ce literal 0 HcmV?d00001 diff --git a/isolatio.c b/isolatio.c new file mode 100644 index 0000000..ae46038 --- /dev/null +++ b/isolatio.c @@ -0,0 +1,148 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "filter_bat2.h" +#include "measure.h" +#include "message.h" +#include "package.h" +#include "peripher.h" +#include "crc16.h" +#include "isolatio.h" +#include // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!! + +OPTOCANAL opt[2]; + +void DCLK(int i, int x) +{ + x=!x; + + if(i) + { + if(x) GpioDataRegs.GPASET.bit.GPIO26=1; + else GpioDataRegs.GPACLEAR.bit.GPIO26=1; + } + else + { + if(x) GpioDataRegs.GPBSET.bit.GPIO32=1; + else GpioDataRegs.GPBCLEAR.bit.GPIO32=1; +} } + +int DIN(int i) +{ + if(i) return !GpioDataRegs.GPBDAT.bit.GPIO52; + else return !GpioDataRegs.GPADAT.bit.GPIO23; +} + +void BLIN(int i) +{ + if(i) GpioDataRegs.GPBTOGGLE.bit.GPIO53=1; + else GpioDataRegs.GPATOGGLE.bit.GPIO24=1; +} + +interrupt void cpu_timer1_isr_ISOL(void) +{ + ERROR error; + float Riso=0,kff=1; + static float fRiso[2]; + static int ist[2] = {1,1}; + long numb=0; + int i; + static unsigned int count_ready=0; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + ServiceDog(); + + if(++count_ready >= period_ready) + { + count_ready=0; + + if((!sig.bit.Error)|(cTestLamp)) toggle_READY(); + else set_READY(); + } + + for(i=0;i<2;i++) + { + if(sens_error[i].bit.Bypas) + { + sens_error[i].all = 0; + sens_error[i].bit.Bypas = 1; + Modbus[i+DATASTART].all = 0; + continue; + } + + if(opt[i].Wait) + { + opt[i].Wait--; + opt[i].bit = 0; + opt[i].clk = 0; + DCLK(i,0); + continue; + } + + opt[i].clk=!opt[i].clk; + DCLK(i,opt[i].clk); + if(!opt[i].clk) + { + opt[i].Numb = (opt[i].Numb<<1) | DIN(i); + if(++opt[i].bit>=32) + { + error.all = 0; + + opt[i].Wait = (TELE_FREQ/1000)*optopowse; + opt[!i].Wait =(TELE_FREQ/2000)*optopowse; + if(get_crc32(&(opt[i].Numb))) + { + numb = opt[i].Numb; + numb = numb / 256; // óäàëÿåì êîíòðîëüíóþ ñóììó + Riso=numb; + + if(ist[i]) { kff=1; ist[i]=0; } + else kff = optofiltr; + fRiso[i] += (Riso-fRiso[i])/kff; + + numb = (long)fRiso[i]; + Modbus[i*2+0x10].all = (int)(numb & 0xFFFF); + Modbus[i*2+0x11].all = (int)(numb>>16); + + Riso=numb; + Riso = Riso/256; // ïðåäïîëîæèì + Modbus[i+DATASTART].all = Riso; + opt[i].ers = 0; BLIN(i); + } + else + { + if(++opt[i].ers > 20) + { + opt[i].ers = 20; + error.bit.Tear = 1; + } + } + + reset_errs(i,error); + + } } + } + + sig.all = chk.all; + chk.all = 0; + +} +void timer_Init() +{ + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT13 = &cpu_timer1_isr_ISOL; + EDIS; // This is needed to disable write to EALLOW protected registers + + ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/TELE_FREQ); + CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + IER |= M_INT13; + + period_ready = TELE_FREQ / (READY_FREQ * 2); + +} diff --git a/isolatio.h b/isolatio.h new file mode 100644 index 0000000..1b2e1ad --- /dev/null +++ b/isolatio.h @@ -0,0 +1,13 @@ +void timer_Init(void); +int get_isolatio(void); + +typedef struct +{ + unsigned int clk; + unsigned int bit; + unsigned int ers; + unsigned Wait; + unsigned long Numb; +} OPTOCANAL; + +#define TELE_FREQ 2000 // Ãö diff --git a/kanal.c b/kanal.c new file mode 100644 index 0000000..704f829 --- /dev/null +++ b/kanal.c @@ -0,0 +1,164 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "measure.h" + +#include "RS485.h" +#include "message.h" +#include "kanal.h" +#include "test.h" +#include "package.h" +#include "tools.h" + +#include "peripher.h" + +int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0}; + +void DCLK(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO6=1; + else GpioDataRegs.GPACLEAR.bit.GPIO6=1; + DSP28x_usDelay(1L); +} + +void DOUT(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO8=1; + else GpioDataRegs.GPACLEAR.bit.GPIO8=1; + DSP28x_usDelay(1L); +} + +void RESET() +{ + DCLK(0); DOUT(1); + DCLK(0); DOUT(0); +} + +void SENDBIT(int x) +{ + DOUT(x); DCLK(1); + DOUT(0); DCLK(0); +} + +void kanal_Send(int adr, long dat, int dot) +{ + long Word,data,aliq_part,dg[4]; + int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len; + + if(adr>1) // Ëàìïî÷êè + { + Word =dat; + } + + else + + { + if(dot<0 || dot>13) // Îøèáêà: -Å... + { + dg[3] = 0xA; dg[2] = 0xE; + dg[1] = 0xF; dg[0] = 0xF; + punkt = 0x7; + } + + else + + { + if(dat<0) sgn=1; + data = labs(dat); + + aliq_part = data; + for(i=0;i0) + { + aliq_len++; dat/=10; + } + + if(aliq_len+sgn>4) + { + if(sgn) dg[3] = 0xA; + else dg[3] = 0xF; + + dat = aliq_part; + for(i=1;i0;i--) + { + if((dg[i]==0)&&(i!=dot)) + dg[i]=0xF; // Ýòî çíà÷èò ïóñòî + else break; + } + + if(sgn) + for(i=1;i<4;i++) + { + if( (dg[i]==0xF)||(i==3)) + { + dg[i]=0xA; // Ýòî çíà÷èò ìèíóñ + break; + } } } } + + for(i=0;i<4;i++) + { + dg[i] = digits[dg[i]]; + if((punkt>>i)&1) dg[i]+= 128; + + } + + Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) | + ((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000); + } + + for (i=0;i<4;i++) + { + if(addr>0x10) break; + + for (j=0;j<8;j++) + { + bit = Word & 1; Word >>= 1; + SENDBIT(bit); + } + + byt = addr; + for (j=0;j<6;j++) + { + bit = byt & 1; byt >>= 1; + SENDBIT(bit); + } + addr++; + + RESET(); + } +} diff --git a/kanal.h b/kanal.h new file mode 100644 index 0000000..44cb4e7 --- /dev/null +++ b/kanal.h @@ -0,0 +1,7 @@ +void kanal_Send(int adr, long dat, int dot); + +#define adr_diod1 0x00 // Ïåðâûå 4 äèîäíûõ ïëàòû +#define adr_diod2 0x04 // Âòîðûå 4 äèîäíûõ ïëàòû +#define adr_digg1 0x08 // Ïåðâûå 4 öèôðû +#define adr_digg2 0x0C // Âòîðûå 4 öèôðû +#define adr_lamps 0x10 // Ëàìïû diff --git a/log_to_mem.c b/log_to_mem.c new file mode 100644 index 0000000..c26404b --- /dev/null +++ b/log_to_mem.c @@ -0,0 +1,34 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */ +/****************************************************************/ +/* log_to_mem.c + **************************************************************** + * Çàïèñü ëîãîâ â ïàìyòü * + ****************************************************************/ + +#include "log_to_mem.h" + +int no_write = 1, + never_write = 0; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî) + +#pragma DATA_SECTION(logs_block,".logg"); +unsigned int logs_block[0xF000]; + +LOG Log; +unsigned int flog=0; + +// Î÷èùåíèå ïàìàòè, ãäå ëîãè ëåæàò +void clear_mem() +{ + unsigned long i; + + Log.Start = LOG_PAGE_START; + Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN; + Log.Adres = Log.Start; + Log.Circl = 0; + + for (i=Log.Start; i (Log.Finis - x)) Log.Adres = Log.Start + +/* Î÷èñòêà ïàìàòè (îáíóëåíèå) */ +void clear_mem(); + +#ifdef __cplusplus + } +#endif + +#endif /* _LOG_TO_MEM */ diff --git a/main.c b/main.c new file mode 100644 index 0000000..d574b57 --- /dev/null +++ b/main.c @@ -0,0 +1,180 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +#include "cntrl_adr.h" +#include "RS485.h" +#include "BIOS_DSP.h" +#include "filter_bat2.h" +#include "measure.h" +#include "Message.h" +#include "package.h" + +#include "spise2p.h" +#include "i2c.h" + +#include "tools.h" +#include "peripher.h" +#include "ADC.h" + +#include "ecan.h" +#include "log_to_mem.h" + +#include "measure.h" +#include "isolatio.h" + +extern void DSP28x_usDelay(Uint32 Count); + +int kaka[3]={64,0,0}; + +void main() +{ + int i,j; + static int canpowse=0,cancount[3],cancell[3],circ[3]; + RS_DATA * rs; + + + InitSysCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + DINT; + + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + init_zone7(); + + setup_leds_line(); + led1_on(); + led2_off(); + for (i=0;i<10;i++) + { + pause_us(50000); + led2_toggle(); + led1_toggle(); + } + led1_off(); + led2_off(); + + get_Mode(); + set_cntrl_addr(Mode,16); + create_uart_vars(sizeof(CMD_TO_TMS)); + setup_uart(COM_1,115200); + setup_uart(COM_2,115200); + Init_Can(0,Addrr); + Init_Seeprom(); + clear_mem(); + + EnableInterrupts(); + + if(Desk!=dsk_ISOL) + { + setup_adc(); + Init_sensors(); + I2CA_Init(); pause_us(500000); + Load_caliber(); + } + else + { + timer_Init(); + Init_optic(); + } + + Load_params(); + Init_packMask(); + + LastMode = Addrr; + + for(i=0;i<3;i++) + { + cancount[i]= 0; + cancell[i] = CAN_send_start; + } + + EALLOW; + SysCtrlRegs.WDCR= 0x2F; + EDIS; + + MAY=1; + + while(1) + { + if(canpowse) canpowse--; + else + { + canpowse = 0x1000; + for(i=0;i<3;i++) + { + if(cancount[i]) cancount[i]--; + else + { + cancount[i] = Cancount[i]; circ[i] = 0; + + while( !((Maska[i][cancell[i]/16]>>(cancell[i]%16))&1) && circ[i] < 2 ) + if(cancell[i]>CAN_send_finis) + { + cancell[i] = CAN_send_start; circ[i]++; + } + else cancell[i]++; + + if(cancell[i]<=CAN_send_finis && circ[i] < 2) + { + CAN_send(0,(int *)Modbus,cancell[i]); + cancell[i]+=3; + } } } } + + if(cSaveParam) + { + cSaveParam=0; + Save_params(); + } + + if(cReadCal) + { + cReadCal=0; + Load_caliber(); + } + + if(cDefParam) + { + cDefParam=0; + Default_params(); + } + + get_Inputs(); + + if(Desk!=dsk_SHKF) + { + Modbus[23].all = Inputs.wrd.word_0; + } + + for(i=0;i<2;i++) + { + if(i) rs = &rs_a; + else rs = &rs_b; + + j = get_command(rs); + + if(j!=-1) + switch(j) + { + case CMD_INIT: init(rs); led2_toggle();break; // íà÷àëüíûå óñòàíîâêè + case CMD_INITLOAD: initload(rs); led2_toggle();break; // íàñòðîéêà çàãðóçêè + case CMD_RUN: run(rs); led2_toggle();break; // çàãðóçèòü áëîê + case CMD_LOAD: load(rs); led2_toggle();break; // çàãðóçèòü áëîê + case CMD_PEEK: peek(rs); led2_toggle();break; // ïðî÷èòàòü à÷åéêó ïàìàòè + case CMD_POKE: poke(rs); led2_toggle();break; // çàïèñàòü â à÷åéêó ïàìàòè + case CMD_UPLOAD: upload(rs); led2_toggle();break; // ïåðåäàòü áëîê ïàìàòè + case CMD_EXTEND: extendbios(rs); led2_toggle();break; // ðàñøèðåííûå êîìàíäû äëà áèîñà + + case CMD_TFLASH: tflash(rs); led2_toggle();break; // ïðîøèòü TMS + +// case CMD_STD: ReceiveCommand(rs); led2_toggle();break; + case CMD_MODBUS_3: ReceiveCommandModbus3(rs); led2_toggle();break; + case CMD_MODBUS_6: ReceiveCommandModbus6(rs); led2_toggle();break; + + default: break; +} } } } + diff --git a/measure.c b/measure.c new file mode 100644 index 0000000..a08046a --- /dev/null +++ b/measure.c @@ -0,0 +1,656 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "package.h" + +#include "measure.h" +#include "package.h" + +#include "peripher.h" +#include "ADC.h" + +#include "RS485.h" +#include "message.h" +#include "log_to_mem.h" + +#include // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!! + +int MAX_TPL_CANAL=0; // Êîëè÷åñòâî òåìïåðàòóðíûõ êàíàëîâ +int period_ready, period_blink, period_dac, time_dac; + +FLAG chk,sig; +long time_1_5sec, time_5msec, time_5sec; + +long err_count[6]; +float lev_count[6]; + +int sens_type[24]; +int sens_pair[24]; +long din_count[32]; + +int adc0[24]; +int tmp0[24]; +float tmpK[24]; + +FILTERBAT def_FILTERBAT = DEF_FILTERBAT; +FILTERBAT filter[40]; + +long sens_count[28]; + +interrupt void cpu_timer1_isr_SENS(void); + +/********************************************************************/ +/* Ðàñ÷åò ìîäóëà òîêà èç ïîêàçàíèé äâóõ ôàç */ +/********************************************************************/ +float im_calc(float ia,float ib) +{ + float isa,isb; + + isa = - 1.5 * (ia + ib); + isb = COSPi6 * (ia - ib); + return (2*sqrt(isa*isa+isb*isb)/3); +} + + +interrupt void cpu_timer1_isr_SENS(void) +{ + static unsigned int + count_ready=0, count_blink=0, count_bright=0, count_mode, + blink_over, blink_alarm, work_lamp, heat_lamp, errr_lamp; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + if(++count_ready >= period_ready) + { + count_ready=0; + + if((!sig.bit.Error)|(cTestLamp)) toggle_READY(); + else set_READY(); + ServiceDog(); + } + + if(++count_bright == maximum_bright) + { + count_bright = 0 ; + + if(Desk==dsk_COMM) + { + if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO60=1; + else GpioDataRegs.GPBSET.bit.GPIO60=1; + if(heat_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO58=1; + else GpioDataRegs.GPBSET.bit.GPIO58=1; + if(errr_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; + else GpioDataRegs.GPBSET.bit.GPIO62=1; + } + + if(Mode==adr_SHKF) + { + if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; + else GpioDataRegs.GPBSET.bit.GPIO62=1; + } } + + if(count_bright == Brightness) + { + if(Desk==dsk_COMM) + { + GpioDataRegs.GPBSET.bit.GPIO60=1; + GpioDataRegs.GPBSET.bit.GPIO58=1; + GpioDataRegs.GPBSET.bit.GPIO62=1; + } + + if(Desk==dsk_SHKF) + { + GpioDataRegs.GPBSET.bit.GPIO62=1; + } } + + if(++count_blink >= period_blink) + { + count_blink=0; + count_mode++; + blink_over = (count_mode & 1)?1:0; + blink_alarm = (count_mode & 7)?1:0; + + if(cExtLamp) + { + work_lamp = cExtLite; + heat_lamp = cExtLite; + errr_lamp = cExtLite; + } + else + { + if(cTestLamp) + { + work_lamp = blink_over; + heat_lamp = blink_over; + errr_lamp = blink_over; + } + else + { + if(Mode==adr_SHKF) + { + if(sig.bit.Error) work_lamp = blink_over; + else work_lamp = 1; + } + else + { + if(sig.bit.Error) work_lamp = 0;//blink_over; +// else if(sig.bit.Alarm) work_lamp = blink_alarm; + else work_lamp = 1; + + if(sig.bit.OverHeat) heat_lamp = 1; + else if(sig.bit.SubHeat) heat_lamp = blink_over; + else if(sig.bit.OutHeat) heat_lamp = !blink_alarm; + else heat_lamp = 0; +} } } } } + +void Init_optic() +{ + int i; + + for(i=0;i<24;i++) + { + sens_type[i]=0; + sens_pair[i]=i; + } + + sens_type[0] = OPTIC; + sens_type[1] = OPTIC; +} + +void Init_sensors() +{ + int i; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT13 = &cpu_timer1_isr_SENS; + EDIS; // This is needed to disable write to EALLOW protected registers + + ConfigCpuTimer(&CpuTimer1, (SYSCLKOUT/1000000), 1000000/SIG_FREQ); + CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + IER |= M_INT13; + + period_ready = SIG_FREQ / (READY_FREQ * 2); + period_blink = SIG_FREQ / (BLINK_FREQ * 2); + + period_dac = SIG_FREQ / (DAC_FREQ); + time_dac = LOAD_TIME * DAC_FREQ; + + time_1_5sec = (3 * ADC_FREQ) / 2; + time_5msec = (5 * ADC_FREQ) / 1000; + time_5sec = (5 * ADC_FREQ); + + for(i=0;i<24;i++) + { + sens_type[i]=0; + sens_pair[i]=i; + } + + if((Mode==adr_REC1)||(Mode==adr_REC2)) + { + sens_type[0]=TERMO_AD; + sens_type[1]=TERMO_AD; + sens_type[2]=TERMO_AD; + sens_type[3]=TERMO_AD; + + sens_type[4]=TERMO_AD; + sens_type[5]=TERMO_AD; + +//sens_type[6]=TERMO_AD; +//sens_type[7]=TERMO_AD; + + + sens_type[8]=TERMO_RS; + sens_type[9]=TERMO_RS; + sens_type[10]=TERMO_RS; + sens_type[11]=TERMO_RS; + + sens_type[12]=VOLTAGE; sens_pair[12]=13; + sens_type[13]=VOLTAGE; sens_pair[13]=12; + sens_type[14]=VOLTAGE; sens_pair[14]=15; + sens_type[15]=VOLTAGE; sens_pair[15]=14; + + Modbus[12].bit.bitE = 1; // Ignore + Modbus[13].bit.bitE = 1; // Ignore + Modbus[14].bit.bitE = 1; // Ignore + Modbus[15].bit.bitE = 1; // Ignore + } + + if((Mode==adr_INV1)||(Mode==adr_INV2)) + { + sens_type[0]=TERMO_AD; + sens_type[1]=TERMO_AD; + sens_type[2]=TERMO_AD; + sens_type[3]=TERMO_AD; + + sens_type[4]=TERMO_AD; + sens_type[5]=TERMO_AD; +//sens_type[6]=TERMO_AD; + + sens_type[7]=TERMO_RS; + sens_type[8]=TERMO_RS; + sens_type[9]=TERMO_RS; + sens_type[10]=TERMO_RS; + sens_type[11]=TERMO_RS; + } + + if(Mode==adr_SHKF) + { + sens_type[0 ] = POWER_380; sens_pair[0]=1; + sens_type[1 ] = POWER_380; sens_pair[1]=0; + sens_type[2 ] = POWER_220; sens_pair[2]=3; + sens_type[3 ] = POWER_220; sens_pair[3]=2; + sens_type[4 ] = POWER_31; + sens_type[5 ] = POWER_31; + sens_type[6 ] = POWER_24; + sens_type[7 ] = POWER_24; + sens_type[8 ] = POWER_24; + sens_type[9 ] = POWER_24; + sens_type[10] = POWER_24; + sens_type[11] = POWER_24; + sens_type[12] = POWER_15; + sens_type[13] = TERMO_AD; + sens_type[14] = TERMO_AD; + sens_type[15] = VIRT_24; + sens_type[16] = VIRT_24; + } + + for(i=0;i<4; i++) err_count[i] = 0; + for(i=0;i<6; i++) lev_count[i] = 0; + for(i=0;i<28;i++) sens_count[i] = 0; + for(i=0;i<32;i++) din_count[i] = 0; + for(i=0;i<40;i++) filter[i] = def_FILTERBAT; + + for(i=0;i=edge) return 1; + (*count)++; return pre; + } + if( (*count) == 0 ) return 0; + (*count)--; return pre; +} + +void reset_errs(int sens, ERROR er) +{ +// unsigned long report; + unsigned int set; + ERROR err; + + err=er; + + if(!sens_error[sens].bit.Latch) + { + set = sens_error[sens].all & NOER; + sens_error[sens].all = err.all | set; + } + else + { + sens_error[sens].all |= err.all; + } + sens_error[sens].bit.Ready = !(err.bit.Stop && (!sens_error[sens].bit.Ignor)); + chk.bit.Error|= !(sens_error[sens].bit.Ready); +} + + +ERROR control_ADC(int sens, int number, int zero) +{ + ERROR err; + int erwait; + + err.all = 0; + + if(TermoSW) erwait = SENS_ERR_WAIT; + else erwait = ADC_FREQ; + +// Êàíàë îáîðâàí + if(er_anal(((number <= zero)||(number >= (0x0FFF-(zero/100)))), + &sens_count[sens],erwait, + sens_error[sens].bit.Tear)) + { + err.bit.Tear = 1; + } +/* +// ÀÖÏ çàëèï + if(er_anal( (sens_prev[sens] == number), + &sens_count[sens][1],ADC_FREQ, + sens_error[sens].bit.Stick)) + { + err.bit.Stick = 1; + } + sens_prev[sens] = number; +*/ + return err; +} + + + + + + +int input_freq(int chan, int Volt) +{ + static int prevolt[4],tics[4],tacs[4],tic[4],tac[4]; + static long Freq = 0; + int i,sum=0,bum=0; + + if(Volt >= Zero_lev[chan]) + if(prevolt[chan]< Zero_lev[chan]) + { + tics[chan] = tic[chan]; tic[chan] = 0; bum = 1; + } + + if(Volt < Zero_lev[chan]) + if(prevolt[chan]>= Zero_lev[chan]) + { + tacs[chan] = tac[chan]; tac[chan] = 0; bum = 1; + } + + if(bum) + { + for(i=0;i<4;i++) sum += tics[i] + tacs[i]; + Freq = (80L * ADC_FREQ) / sum; + } + + prevolt[chan] = Volt; + tic[chan]++; + tac[chan]++; + + return Freq; +} + + + + +void Current_count(int sens) +{ + float Numb,Current,fAmpl; + static float aCurrent,Amplitude; + static int prezer0=0; + int chan, pair, ist, thrd, i, ignor; + int freq=0; + + ERROR error; + + error.all = 0; + + chan = sens - MAX_TPL_CANAL; + pair = sens_pair[sens] - MAX_TPL_CANAL; + ist = !(chan & 1); + thrd= (chan >>1) + 4; + + if(sens_error[sens].bit.Bypas) + { + sens_error[sens].all = 0; + sens_error[sens].bit.Bypas = 1; + Modbus[sens+DATASTART].all = 0; + return; + } + + Numb = ADC_table[sens]; + + if(cTermoCal||cSetZero) + { + if(!prezer0) + for(i=0;i<4;i++) lev_count[i] = Numb; + lev_count[chan] += (Numb-lev_count[chan])/1000.0; + adc0[sens] = (int)(filterbat(&filter[sens],lev_count[chan])); + Zero_lev[chan] = adc0[sens]; + Modbus[sens+DATASTART].all = adc0[sens]; + } + prezer0 = (cTermoCal||cSetZero); + + Current = (Numb - adc0[sens]) * tmpK[sens]; + + if(!(cTermoCal||cSetZero)) + { + freq = input_freq(chan,Numb); + + + lev_count[chan] += (fabs(Current)-lev_count[chan])/1000.0; + +// Çàïîìíèì + if(ist) + { + aCurrent = -Current; // Çàïîìíèëè ìãíîâåííîå çíà÷åíèå - äëà àìïëèòóäû + } + else + { +// Âû÷èñëåíèå àìïëèòóäû + Amplitude = im_calc(Current,aCurrent); + fAmpl = filterbat(&filter[sens],Amplitude); + + if(fAmpl<100) + { + fAmpl=0; freq=0; + } + + +// Modbus[sens+DATASTART-1].all = (int)fAmpl;//(int)Amplitude; + Modbus[sens+DATASTART-1].all = (int)(fAmpl/RADIX2); + +// Òðåòüÿ ôàçà äëÿ ïðîâåðîê + lev_count[thrd] += (fabs(-Current-aCurrent)-lev_count[thrd])/1000.0; + +i=(8-((sens+DATASTART-1)%8)); +Modbus[sens+DATASTART+i-1+(thrd-4)*3].all = lev_count[chan]; +Modbus[sens+DATASTART+i +(thrd-4)*3].all = lev_count[pair]; +Modbus[sens+DATASTART+i+1+(thrd-4)*3].all = lev_count[thrd]; + + } + + Modbus[sens+DATASTART].all = freq; + +// Çàøèòû! + if(Current > 1.1 * sens_hi_edge[sens]) + { + error.bit.Hyper = 1; + error.bit.Stop = 1; + } + + Numb = lev_count[chan]; + if(Numb 0.2) && (Numb>100), + &err_count[chan],time_1_5sec,0)) + { + error.bit.Wry = 1; + error.bit.Stop = 1; + } + + if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.2) && (Numb>100), + &err_count[thrd],time_1_5sec,0)) + { + error.bit.Wry = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(!ist) + { + if(Amplitude > sens_hi_edge[sens]) + { + error.bit.Hyper = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(Amplitude < sens_lo_edge[sens]) + { + error.bit.Out = 1; + if(!ignor) + error.bit.Stop = 1; + } } } + + reset_errs(sens,error); + +} + +void Temper_count(int chan) +{ + float Numb; + int Temper; + int ignor; + ERROR error; + int zer0; + + if(!chan) + { + sig.all = chk.all; + chk.all = 0; + } + + if(chansens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) || + (Temper>sens_hi_edge[chan]) ) + { + error.bit.Hyper = 1; + if(!ignor) + { + error.bit.Stop = 1; + chk.bit.OverHeat= 1; + } } + + else + +// Ïðåäóïðåæäåíèå ïî òåìïåðàòóðå + + if(Temper>sens_lo_edge[chan]) + { + error.bit.Over = 1; + if(!ignor) + chk.bit.SubHeat = 1; + } } + + if(error.all) chk.bit.OutHeat = 1; + + reset_errs(chan,error); + +} + +void Power_count(int chan) +{ + float Numb; + int Power,ignor,bitt; + ERROR error; + + if(sens_error[chan].bit.Bypas) + { + sens_error[chan].all = 0; + sens_error[chan].bit.Bypas = 1; + Modbus[chan+DATASTART].all = 0; + return; + } + + Numb = ADC_table[chan]; + + if(cTermoCal) + { + Modbus[chan+DATASTART].all = (int)(Numb); + return; // øòîáû ñòðóêòóðà îøèáîê íå âëåçàëà â äàííûå + } + + Power = (Numb * tmpK[chan]+5)/10.0; // powK[sens_type[chan]]; + + Modbus[chan+DATASTART].all = Power; + + error.all = 0; + ignor = sens_error[chan].bit.Ignor; + + if(Power sens_hi_edge[chan]) + { + error.bit.Hyper = 1; + if(!ignor) + error.bit.Stop = 1; + } + + if(chan>3) + { + bitt = (chan-4)*2; + error.bit.Contr1 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + error.bit.Contr2 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); + } + + if(error.all) + if(!ignor) + chk.bit.Alarm = 1; + reset_errs(chan,error); +} diff --git a/measure.h b/measure.h new file mode 100644 index 0000000..ce5b7c4 --- /dev/null +++ b/measure.h @@ -0,0 +1,136 @@ +// âãâ +#ifndef _MEASURE +#define _MEASURE + +void Init_sensors(void); +void Init_optic(void); +void Init_packMask(void); +void Temper_count(int chan); +void Current_count(int chan); +void Power_count(int chan); + +typedef union +{ + struct + { + unsigned int Tear :1; + unsigned int Stick :1; + unsigned int Wry :1; + unsigned int Out :1; + unsigned int Over :1; + unsigned int Hyper :1; + unsigned int Contr1 :1; + unsigned int Contr2 :1; + + unsigned int Stop :1; + unsigned int Ready :1; + unsigned int res :3; + unsigned int Latch :1; + unsigned int Ignor :1; + unsigned int Bypas :1; + + } bit; + unsigned int all; + +} ERROR; + +typedef union +{ + struct + { + unsigned int Error :1; + unsigned int Alarm :1; + unsigned int OverHeat :1; + unsigned int SubHeat :1; + unsigned int OutHeat :1; + unsigned int Test_lamp :1; + + } bit; + unsigned int all; + +} FLAG; + +#define NOER 0xE000 +#define EROR 0x01FF + +#define SIG_FREQ 4000 // Ãö +#define READY_FREQ 1000 // Ãö +#define BLINK_FREQ 2 // Ãö +#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // Ãö (777*5) +#define DAC_FREQ 50 // Ãö + +#define LOAD_TIME 10 // sec + + +#define SENS_ERR_WAIT 10 + +#define maximum_bright 10 + +/* +#define SNOW 1720.0 //1920.0 +#define BOIL 2360.0 //2561.0 + +#define tmp_T_0 0.0 +#define tmp_T_1 200.00 +#define tmp_A1_0 978.0 +#define tmp_A1_1 1686.0 +#define tmp_A2_0 1017.0 +#define tmp_A2_1 1736.0 +#define eta_A1 1002.0 +#define eta_A2 1542.0 +*/ + +#define tmp_T_0 84.31 // 68Om +#define tmp_T_1 234.19 // 100Om +#define tmp_A1_0 540.0 // êàíàë 1 68Îì +#define tmp_A2_0 500.0 // êàíàë 1 100Îì +#define tmp_A1_1 1055.0 // êàíàë 2 68Îì +#define tmp_A2_1 1060.0 // êàíàë 2 100Îì + + +#define ZERO 27 + +#define mka300 2040 +#define mka400 2700 + +#define C100 650 +#define C150 2370 + +#define Cooling 5 // (°Ñ) Ãèñòåðåçèñ ïî ñíàòèþ ïåðåãðåâà + +#define COSPi6 0.86602540378443864676372317075294 + +#define RADIX2 1.4142135623730950488016887242097 + +#define CURRENT 1 // òîê +#define VOLTAGE 2 // íàïðàæåíèå + +#define POWER_380 3 // ïèòàíèå 380 +#define POWER_220 4 // ïèòàíèå 220 +#define POWER_31 5 // ïèòàíèå 31 +#define POWER_24 6 // ïèòàíèå 24 +#define VIRT_24 7 // ïèòàíèå 24 +#define POWER_15 8 // ïèòàíèå 15 +#define TERMO_AD 9 // òåðìîäàò÷èê ìåëêîñõåìà +#define TERMO_RS 10 // òåðìîäàò÷èê ðåçèñòîð +#define OPTIC 11 // îïòîêàíàë ìåãîììåòðà + +extern int MAX_TPL_CANAL; + +extern FILTERBAT filter[]; + +extern ERROR * sens_error; +extern int * sens_hi_edge; +extern int * sens_lo_edge; + +extern int adc0[],tmp0[]; + +#define Zero_lev (adc0+12) //((int *)&Modbus[0x74]) + +extern float tmpK[]; +extern FLAG chk,sig; +extern int sens_type[]; + +extern int period_ready; + +#endif //_MEASURE diff --git a/message.c b/message.c new file mode 100644 index 0000000..74251dc --- /dev/null +++ b/message.c @@ -0,0 +1,355 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "package.h" +#include "RS485.h" +#include "crc16.h" +#include "cntrl_adr.h" +#include "bios_dsp.h" +#include "filter_bat2.h" +#include "measure.h" +#include "message.h" + + +#include "ADC.h" +#include "peripher.h" + +#include "ecan.h" +#include "spise2p.h" +#include "i2c.h" + +WORDE Modbus[ANSWER_LEN+1]; +WORDE reply[REPLY_LEN]; + +unsigned int param[ANSWER_LEN+1]; + +LONGE* outputs; + +int DataAnalog1,DataAnalog2; + +ERROR * sens_error; +int * sens_hi_edge; +int * sens_lo_edge; + +unsigned int Maska[3][9]; + +void Default_params() +{ + unsigned int i; + + for(i=0;iRS_Header[2] << 8) |*/ rs_arr->RS_Header[3]; + +// ïîëó÷èëè êîëè÷åñòâî ñëîâ äàííûõ + Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // Îòñûëêà + /* Ïîñ÷èòàëè êîíòðîëüíóþ ñóììó ïåðåä ñàìîé ïîñûëêîé */ + + rs_arr->buffer[0] = CNTRL_ADDR; + rs_arr->buffer[1] = CMD_MODBUS_3; + rs_arr->buffer[2] = Length_MB*2; + + for (i=0;ibuffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi); + rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo); + } + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3); + + rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc); + rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc); + + rs_arr->buffer[Length_MB*2+5] = 0; + rs_arr->buffer[Length_MB*2+6] = 0; + rs_arr->buffer[Length_MB*2+7] = 0; + rs_arr->buffer[Length_MB*2+8] = 0; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8); + + return; +} + +void ReceiveCommandModbus6(RS_DATA *rs_arr) +{ + unsigned int Address_MB, Data_MB, i; + + ///////////////////////////////////////////////// + // Îòñûëêà + /* Îòïðàâëàåì íàçàä òî æå ñàìîå */ + + for (i=0;i<8;i++) + rs_arr->buffer[i] = rs_arr->RS_Header[i]; + +// ïîëó÷èëè íà÷àëüíûé àäðåñ çàïèñè + Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]); + +// ïîëó÷èëè ñëîâî äàííûõ + Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + Modbus[Address_MB].all = Data_MB; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, 10); +} diff --git a/message.h b/message.h new file mode 100644 index 0000000..2b694a5 --- /dev/null +++ b/message.h @@ -0,0 +1,51 @@ +#ifndef MESSAGE_H +#define MESSAGE_H + +typedef unsigned char CHAR; + +#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6 +#define REPLY_LEN 0x19 + +#define byte_hi byte_1 +#define byte_lo byte_0 + +typedef struct +{ + unsigned char Address; // Àäðåñ êîíòðîëëåðà + unsigned char Number; // Íîìåð êîìàíäû + + BAITE byte0; + BAITE byte1; + BAITE byte2; + BAITE byte3; + BAITE byte4; + BAITE byte5; + BAITE byte6; + BAITE byte7; + + unsigned char crc_lo; + unsigned char crc_hi; + unsigned char add_byte; +} CMD_TO_TMS; + +extern WORDE Modbus[]; +extern WORDE reply[]; + +extern LONGE* outputs; + +extern int DataAnalog1,DataAnalog2; + +extern unsigned int Maska[][9]; + +//void ReceiveCommand(RS_DATA *rs_arr); +void ReceiveCommandModbus3(RS_DATA *rs_arr); +void ReceiveCommandModbus6(RS_DATA *rs_arr); + +void reset_errs(int sens, ERROR er); + +void Save_params(void); +void Load_params(void); +void Load_caliber(void); +void Default_params(void); + +#endif //MESSAGE_H diff --git a/package.h b/package.h new file mode 100644 index 0000000..bec9f68 --- /dev/null +++ b/package.h @@ -0,0 +1,56 @@ +#ifndef PACKAGE +#define PACKAGE + +#define TERMOPAIR 14 +#define CURRENTOS (TERMOPAIR*2) +#define DATASTART 24 + +//----------------------------------------------- +#define adr_REC1 1 +#define adr_REC2 2 +#define adr_INV1 3 +#define adr_INV2 4 +#define adr_SHKF 5 +#define adr_ISOL 6 +//----------------------------------------------- + +//----------------------------------------------- +#define dsk_COMM 1 +#define dsk_SHKF 2 +#define dsk_ISOL 3 +//----------------------------------------------- + + +#define CAN_send_start 0 // Àäðåñ ïåðâîãî ïåðåäàâàåìîãî +#define CAN_send_finis 0x6F // Àäðåñ ïîñëåäíåãî ïåðåäàâàåìîãî + +#define start_sens_error 0 +#define start_sens_hi_edge 48 +#define start_sens_lo_edge 72 + +#define optopowse Modbus[0x60].all // ïàóçà ìåæäó çàïðîñàìè, ms +#define optofiltr Modbus[0x61].all // êîýôôèöèåíò ôèëüòðàöèè + +#define Brightness Modbus[0x64].all // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê + +#define Cancount ((int *)&Modbus[0x65]) + +#define Zeroes ((int *)&Modbus[0x70]) + +#define LastMode Modbus[126].all + +#define Commands Modbus[127].all +#define cTestLamp Modbus[127].bit.bit0 +#define cSetZero Modbus[127].bit.bit1 +#define cSaveParam Modbus[127].bit.bit2 +#define cDefParam Modbus[127].bit.bit3 + +#define cTermoCal Modbus[127].bit.bit4 +#define cReadCal Modbus[127].bit.bit5 + +#define cExtLamp Modbus[127].bit.bit6 +#define cExtLite Modbus[127].bit.bit7 + + +#endif //PACKAGE + diff --git a/peripher.c b/peripher.c new file mode 100644 index 0000000..70048b1 --- /dev/null +++ b/peripher.c @@ -0,0 +1,143 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "filter_bat2.h" +#include "measure.h" +#include "RS485.h" +#include "message.h" + +#include "package.h" + +#include "peripher.h" +#include "GPIO_table.h" + + +int Mode,Desk,Addrr,TermoAD=0,TermoRS=0,TermoSW=0,Currentoz=0; +LONGE Inputs; + +int ExtraCanal[24]; + +void get_Mode() +{ + int i,qua; + + EALLOW; + + GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 00—11 + GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 19—27 + GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFCC0; // 32—34, 36 + GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 48—53, 58—63 + + GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO21 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; + + EDIS; + + Mode=0; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO22; + if(qua>50) Mode += 1; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO20; + if(qua>50) Mode += 2; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPADAT.bit.GPIO21; + if(qua>50) Mode += 4; + + Addrr = Mode*2; + + Mode+= 1; + + qua=0; + for(i=0;i<100;i++) + qua += !GpioDataRegs.GPBDAT.bit.GPIO51; + if(qua>50) Addrr += 1; + + if( (Mode==adr_REC1)||(Mode==adr_REC2)) Currentoz = 1; + if( (Mode==adr_REC1)||(Mode==adr_REC2)|| + (Mode==adr_INV1)||(Mode==adr_INV2)) Desk = dsk_COMM; + if (Mode==adr_SHKF) Desk = dsk_SHKF; + if (Mode==adr_ISOL) Desk = dsk_ISOL; + + EALLOW; + switch(Desk) + { + case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR; + GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break; + + case dsk_SHKF: GpioCtrlRegs.GPADIR.all = VEPP_GPADIR; + GpioCtrlRegs.GPBDIR.all = VEPP_GPBDIR; break; + + case dsk_ISOL: GpioCtrlRegs.GPADIR.all = ISOL_GPADIR; + GpioCtrlRegs.GPBDIR.all = ISOL_GPBDIR; break; + } + EDIS; +} + +void get_Inputs() +{ + static long butthurt[2] ={0,0}; + unsigned long butt=0; + + if(Desk==dsk_COMM) + { + if(!GpioDataRegs.GPADAT.bit.GPIO7) butthurt[0]=0; + else if(butthurt[0] size) len=size; + + writeData.dataPtr = buf; + writeData.nrData = len; + writeData.se2pAddr = adres * WORD_LEN; + + spiSe2pWrite(&se2p, &writeData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +// diod2_off(); + +} + +void Seeprom_read( unsigned int adres, + unsigned int buf[], + unsigned int size) +{ + unsigned int len; + +// diod2_on(); + CpuTimer2.InterruptCount=0; + CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + + while(!spiSe2pFree(&se2p)); + + size = (size / WORD_LEN) + (size % WORD_LEN); + while(size) + { + len = PAGE_LEN - (adres % PAGE_LEN); + if(len > size) len=size; + + readData.dataPtr = buf; + readData.nrData = len; + readData.se2pAddr = adres * WORD_LEN; + + spiSe2pRead(&se2p, &readData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +// diod2_off(); +} + +void Init_Seeprom() +{ + se2p.init(&se2p); + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitCpuTimers(); // For this example, only initialize the Cpu Timers +// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100); +// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 10); + ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100); + + IER |= M_INT14; +} + +void SPISE2P_DRV_init(SPISE2P_DRV *eeprom) +{ +/* Configure SPI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SPI functional pins. +// Comment out other unwanted lines. + EALLOW; + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O) + GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output + GpioDataRegs.GPADAT.bit.GPIO19 = 0; + EDIS; + + /* Configure the SPI: 8-bit, Rising edge with delay */ + SpiaRegs.SPICCR.all=0x0007; + SpiaRegs.SPICTL.all=0x001F; + SpiaRegs.SPISTS.all=0x00; + + SpiaRegs.SPIBRR = (LSPCLK / SPIBAUD_RATE) - 1; + + SpiaRegs.SPIFFTX.all=0x8000; + SpiaRegs.SPIFFRX.all=0x0000; + SpiaRegs.SPIFFCT.all=0x00; + SpiaRegs.SPIPRI.all=0x0010; + + /* Disable Chip Select of Serial EEPROM */ + eeprom->csr=0; + eeprom->msgPtr=0; + + SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI +} + +void SPISE2P_DRV_csset() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 1; +} + +void SPISE2P_DRV_csclr() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 0; +} + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p) +{ + if(se2p->csr&0x3) return(0); + else return(1); +} + +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x1; +} + +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x2; +} + +/********************************************************************/ +/******* SPI bus Serial EEPROM driver Tick function *****************/ +/********************************************************************/ + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + + se2p.tick(&se2p); + + // The CPU acknowledges the interrupt. + EDIS; +} + +void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom) +{ + static unsigned int step=0; + static unsigned int dataCount=0; + static volatile unsigned int dummy=0; + + switch(step) + { + case 0: + /* If write request is SET, then trigger the Write operation + If read request is SET, then trigger the Read operation + If Read request is also not SET, then continue to poll */ + + if(eeprom->csr&SPISE2P_WRRQ) + { step=1; + eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/ + eeprom->csclr(); + } + + if(eeprom->csr&SPISE2P_RDRQ) + { step=13; + eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */ + eeprom->csclr(); + } + break; + + case 1: + /************************************************************ + *********** SPI bus EEPROM Write Starts from here *********** + ************************************************************* + Prier to any attempt to write data to SPI serial EEPROM + Write Enable Latch must be set by issuing the WREN command */ + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=2; + break; + + case 2: + /* Wait for VSPI State machine to send the WREN command and + serial EEPROM Chip Select must be brought to HIGH to set + the WREN latch */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + eeprom->csset(); + + step=3; + } + break; + + case 3: + /* Assert CS of Serial EEPROM and send WRITE command */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=4; + break; + + case 4: + /* Wait for VSPI State machine to send the WRITE command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=5; + } + break; + + case 5: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=6; + break; + + case 6: + /* Wait for VSPI State machine to send the Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=7; + } + break; + + case 7: + /* Send Data */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount); + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8; + #endif + + dataCount++; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=8; + break; + + case 8: + /* Wait for VSPI State machine to send the Data. + If all the data are sent, then set the CS pin to HIGH + to program or write the data in EEPROM array */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=9;} + else + step=7; /* Write next data */ + } + break; + + + case 9: + /* Read the EEPROM status register to check whether the + data sent are indeed programmed to the EEPROM array. + Hence, send RDSR command to EEPROM to read status reg. */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=10; + break; + + case 10: + /* Wait for VSPI State machine to send RDSR command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=11; + } + break; + + case 11: + /* Send dummy Data to read Status reg. */ + + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=12; + break; + + case 12: + /* Wait for VSPI State machine to clock out status reg. + Check, whether the data are written to the EEPROM array, + If written, then reset the WRIP(write in progress) and + WRRQ(Write request bit) and go back to STATE0 */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { eeprom->csset(); + + if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK ) + step=9; + else + { eeprom->csr&=(~SPISE2P_WRIP); + eeprom->csr&=(~SPISE2P_WRRQ); + step=0; + dataCount=0; + } + } + break; + + case 13: + /************************************************************ + *********** SPI bus EEPROM Read Starts from here *********** + ************************************************************* + Send READ Command to SPI bus serail EEPROM */ + + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_READ_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=14; + break; + + case 14: + /* Wait for VSPI State machine to send READ command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=15; + } + break; + + case 15: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=16; + break; + + case 16: + /* Wait for VSPI State machine to send Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=17; + } + break; + + case 17: + /* Send Dummy value to clock out data from serial EEPROM */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=18; + break; + + case 18: + /* Wait for VSPI State machine to clk out data from EEPROM */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF; + #endif + dataCount++; + step=19; + } + break; + + case 19: + /* If all the data are read, terminate the read operation by + rising the CS. Then reset the RDIP (Read in progress) bit + and reset the RDRQ(Read request) bit and go back to STATE0 */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=0; + dataCount=0; + eeprom->csr&=(~SPISE2P_RDIP); + eeprom->csr&=(~SPISE2P_RDRQ); + } + else + step=17; + break; + } +} + diff --git a/spise2p.h b/spise2p.h new file mode 100644 index 0000000..6cf27e4 --- /dev/null +++ b/spise2p.h @@ -0,0 +1,134 @@ +/*===================================================================== +File name : SPISE2P.H + +Originator : Settu Duraisamy + C2000 Applications Team + Texas Instruments + +Description : + Header file containing object definitions, proto type + declaration and default object initializers for + SPI Serial EEPROM driver using VSPI + +Date : 30/6/2003 (DD/MM/YYYY) +=======================================================================*/ + +#ifndef __SPISE2P_H__ + +#define __SPISE2P_H__ + +// ¨ìêîñòü ïàìàòè â áàéòàõ +#define SEEPROM_LEN 0x10000 + +#define NULL 0 + +#define SIXTEEN_BIT 15 +#define EIGHT_BIT 07 + +/***************************************************************/ +/* Configurable Parameter for SPI bus Serial EEPROM */ +/***************************************************************/ +#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT +#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT +#define SPIBAUD_REG_VAL 1//12 +#define SPICLK_PHASE 1 +#define SPICLK_POLARITY 0 + +#define SPIBAUD_RATE 100000 +//10000000 + +/**************************************************************/ +/**************************************************************/ + +/* Serial EEPROM Command words, left justified */ +#define SPISE2P_READ_CMD 0x0300 +#define SPISE2P_WRITE_CMD 0x0200 +#define SPISE2P_WRDI_CMD 0x0400 +#define SPISE2P_WREN_CMD 0x0600 +#define SPISE2P_RDSR_CMD 0x0500 +#define SPISE2P_WRSR_CMD 0x0100 + +#define SPISE2P_RDID_CMD 0x0A00 + +#define SPISE2P_DUMMY_DATA 0x0000 +#define SPISE2P_BUSY_MASK 0x01 + +/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/ +#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT +#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT + +/* Status valus */ +#define SPISE2P_WRRQ 1 /* Write Requset */ +#define SPISE2P_RDRQ 2 /* Read request */ +#define SPISE2P_WRIP 4 /* Write in progress */ +#define SPISE2P_RDIP 8 /* Read in progress */ + +/* Message declaration */ +typedef struct { + unsigned int *dataPtr; /* Data pointer */ + unsigned long nrData; /* number of data */ + unsigned long se2pAddr; /* se2pAddr */ + }SE2P_DATA; + + +/* Object declaration */ +typedef struct { + SE2P_DATA *msgPtr; + unsigned int csr; /* control/status register */ + void (*init)(void *); + void (*tick)(void *); + void (*csset)(void); + void (*csclr)(void); + }SPISE2P_DRV; + +#define SPISE2P_DRV_DEFAULTS { NULL,\ + 0,\ + (void (*)(void *))SPISE2P_DRV_init,\ + (void (*)(void *))SPISE2P_DRV_tick,\ + (void (*)(void))SPISE2P_DRV_csset,\ + (void (*)(void))SPISE2P_DRV_csclr} + +typedef SPISE2P_DRV *SPISE2P_DRV_handle; + +void SPISE2P_DRV_init(SPISE2P_DRV * ); +void SPISE2P_DRV_tick(SPISE2P_DRV *); +void SPISE2P_DRV_csset(void); +void SPISE2P_DRV_csclr(void); + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p); +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data); +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data); + +#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + #define PROM_LEN 0x8000 + #define PAGE_LEN 0x20 + #define WORD_LEN 2 +#else + #define PROM_LEN 0x4000 + #define PAGE_LEN 0x40 + #define WORD_LEN 1 +#endif + +/* Óñòàíîâêà äðàéâåðà ñåðèàëüíîé EEPROM. ** +** Èíèöèàëèçàöèà SPI è ïðî÷. Òàêæå íàñòðîéêà òàéìåðà. ** +** Äðàéâåð ðàáîòàåò íà ïðåðûâàíèàõ îò òàéìåðà 2! */ +void Init_Seeprom(void); + +/* Çàïèñü áëîêà â SEEPROM. Ïàðàìåòðû òàêîâû: ** +** adres - àäðåñ â åïðîìêå, êóäà ïèñàòü. ** +** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò ** +** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò ** +** buf - óêàçàòåëü íà ïàìàòü, îòêóäà ïèñàòü. ** +** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */ +void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size); + +/* ×òåíèå áëîêà èç SEEPROM. Ïàðàìåòðû òàêîâû: ** +** adres - àäðåñ â åïðîìêå, îòêóäà ÷èòàòü. ** +** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò ** +** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò ** +** buf - óêàçàòåëü íà ïàìàòü, êóäà ÷èòàòü. ** +** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */ +void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size); + +#endif + diff --git a/test.c b/test.c new file mode 100644 index 0000000..5427b15 --- /dev/null +++ b/test.c @@ -0,0 +1,183 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "message.h" +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" +#include "test.h" +#include "kanal.h" +#include "peripher.h" + +WORDE PRES; + +int isMask = 1; +int isLamp = 0; +int isBrit = 0; +int isNumb = 1111; + +long cownt=0; + +unsigned int Light = 0xFFFF; + +int quaLamp = 6; + +void what_is() +{ + static int numb=0; + + if(keyTest) + { + if(keyNext & !preNext) + { + if(!isBrit) + { + isBrit=1; + isMask=1; + isLamp=0; + } + else + { + isMask<<=1; + + if(++isLamp >= quaLamp) + { + isMask=1; + isLamp=0; + } } } + + if(isBrit) + { + if(keyUp && !preUp) + if(Bright[isLamp]<10) Bright[isLamp]++; + + if(keyDown & !preDown) + if(Bright[isLamp]>0) Bright[isLamp]--; + } + else + { + if(cownt) cownt--; + else + { + cownt = BLN_FREQ/4; + + numb++; if(numb==10) numb=1; + isNumb = numb*1111; + + if(!isMask) isMask = 0xFFFF; + else isMask = 0; + } } } + + else + { + if(isBrit) + { + isBrit=0; + Save_params(); + } } + + PRES = KEYS; +} + + +interrupt void cpu_timer1_isr_PULT(void) +{ + static int count_bright=0; + unsigned int light=0, i; + static LONGE Diod1,Diod2; + static unsigned int Cownt,cownt; + int dig1,dig2; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + GpioDataRegs.GPATOGGLE.bit.GPIO0=1; // Ready + + if(count_bright) count_bright --; + else count_bright = 9; + for(i=0; i> 1; + + for (i = 0; i < t; i++) + { + DSP28x_usDelay(40L); +// powse=40L; +// for(powse=0; powse<40; powse++); + } +} + + diff --git a/tools.h b/tools.h new file mode 100644 index 0000000..2107dc4 --- /dev/null +++ b/tools.h @@ -0,0 +1,26 @@ +#ifndef TOOLS_H +#define TOOLS_H + +void init_zone7(void); + +void setup_leds_line(void); + +void pause_us(unsigned long t); + +#ifndef TUBER +#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1 +#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1 +#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1 +#else +#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led2_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#endif + +#endif //TOOLS_H diff --git a/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd new file mode 100644 index 0000000..b3707a7 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd @@ -0,0 +1,176 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:25 $ +//########################################################################### +// +// FILE: 28332_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28332 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28332 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd new file mode 100644 index 0000000..25f0fc9 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd @@ -0,0 +1,178 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: July 9, 2008 13:43:30 $ +//########################################################################### +// +// FILE: 28334_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28334 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28334 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd b/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd new file mode 100644 index 0000000..b469211 --- /dev/null +++ b/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd @@ -0,0 +1,176 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:36 $ +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_common/cmd/F28332.cmd b/v120/DSP2833x_common/cmd/F28332.cmd new file mode 100644 index 0000000..ecdc06e --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28332.cmd @@ -0,0 +1,197 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:41 $ +//########################################################################### +// +// FILE: F28332.cmd +// +// TITLE: Linker Command File For F28332 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ + +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/cmd/F28334.cmd b/v120/DSP2833x_common/cmd/F28334.cmd new file mode 100644 index 0000000..ec4d6c3 --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28334.cmd @@ -0,0 +1,203 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:49 $ +//########################################################################### +// +// FILE: F28334.cmd +// +// TITLE: Linker Command File For F28334 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */ + FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */ + FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */ + FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/cmd/F28335.cmd b/v120/DSP2833x_common/cmd/F28335.cmd new file mode 100644 index 0000000..b00d2a5 --- /dev/null +++ b/v120/DSP2833x_common/cmd/F28335.cmd @@ -0,0 +1,203 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/v120/DSP2833x_common/gel/f28232.gel b/v120/DSP2833x_common/gel/f28232.gel new file mode 100644 index 0000000..9ad95bf --- /dev/null +++ b/v120/DSP2833x_common/gel/f28232.gel @@ -0,0 +1,2822 @@ +/********************************************************************/ +/* f28232.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28232 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28232_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28232 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28232 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x330000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28232_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28232_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28232 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28234.gel b/v120/DSP2833x_common/gel/f28234.gel new file mode 100644 index 0000000..cd5726a --- /dev/null +++ b/v120/DSP2833x_common/gel/f28234.gel @@ -0,0 +1,2930 @@ +/********************************************************************/ +/* f28234.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28234 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28234_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28234 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28234 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x320000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28234_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28234_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28234 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} + +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28235.gel b/v120/DSP2833x_common/gel/f28235.gel new file mode 100644 index 0000000..9d35fee --- /dev/null +++ b/v120/DSP2833x_common/gel/f28235.gel @@ -0,0 +1,2939 @@ +/********************************************************************/ +/* f28235.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28235 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); + +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28235_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28235 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28235 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */ +/* 0x300000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28235_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28235_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2823x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate."); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + + +} + + + + + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28235 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28332.gel b/v120/DSP2833x_common/gel/f28332.gel new file mode 100644 index 0000000..9a9d2fb --- /dev/null +++ b/v120/DSP2833x_common/gel/f28332.gel @@ -0,0 +1,2845 @@ +/********************************************************************/ +/* f28332.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28332 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28332_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28332 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28332 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x330000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28332_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28332_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28332 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28334.gel b/v120/DSP2833x_common/gel/f28334.gel new file mode 100644 index 0000000..fde0000 --- /dev/null +++ b/v120/DSP2833x_common/gel/f28334.gel @@ -0,0 +1,2951 @@ +/********************************************************************/ +/* f28334.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28334 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28334_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28334 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28334 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */ +/* 0x320000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28334_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28334_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + } + else + { + GEL_TextOut("\nADC Calibration not complete, device is secure"); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + +} + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28334 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} + +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} + +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/gel/f28335.gel b/v120/DSP2833x_common/gel/f28335.gel new file mode 100644 index 0000000..a3c37ec --- /dev/null +++ b/v120/DSP2833x_common/gel/f28335.gel @@ -0,0 +1,2960 @@ +/********************************************************************/ +/* f28335.gel */ +/* Version 3.30.2 */ +/* */ +/* This GEL file is to be used with the TMS320F28335 DSP. */ +/* Changes may be required to support specific hardware designs. */ +/* */ +/* Code Composer Studio supports six reserved GEL functions that */ +/* automatically get executed if they are defined. They are: */ +/* */ +/* StartUp() - Executed whenever CCS is invoked */ +/* OnReset() - Executed after Debug->Reset CPU */ +/* OnRestart() - Executed after Debug->Restart */ +/* OnPreFileLoaded() - Executed before File->Load Program */ +/* OnFileLoaded() - Executed after File->Load Program */ +/* OnTargetConnect() - Executed after Debug->Connect */ +/* */ +/********************************************************************/ + +StartUp() +{ + +/* The next line automatically loads the .gel file that comes */ +/* with the DSP2833x Peripheral Header Files download. To use, */ +/* uncomment, and adjust the directory path as needed. */ +// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel"); + +} + +OnReset(int nErrorCode) +{ + C28x_Mode(); + Unlock_CSM(); + ADC_Cal(); + +} + +OnRestart(int nErrorCode) +{ +/* CCS will call OnRestart() when you do a Debug->Restart and */ +/* after you load a new file. Between running interrupt based */ +/* programs, this function will clear interrupts and help keep */ +/* the processor from going off into invalid memory. */ + C28x_Mode(); + IER = 0; + IFR = 0; + ADC_Cal(); +} + +int TxtOutCtl=0; +OnPreFileLoaded() +{ + XINTF_Enable(); + if (TxtOutCtl==0) + { + GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); + GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers."); + TxtOutCtl=1; + } +} + +OnFileLoaded(int nErrorCode, int bSymbolsOnly) +{ + ADC_Cal(); +} + +OnTargetConnect() +{ + C28x_Mode(); + F28335_Memory_Map(); /* Initialize the CCS memory map */ + +/* Check to see if CCS has been started-up with the DSP already */ +/* running in real-time mode. The user can add whatever */ +/* custom initialization stuff they want to each case. */ + + if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ + { + + } + else /* Do stop-mode target initialization */ + { + GEL_Reset(); /* Reset DSP */ + } + +} + + +/********************************************************************/ +/* These functions are launched by the GEL_Toolbar button plugin */ +/********************************************************************/ +GEL_Toolbar1() +{ + Run_Realtime_with_Reset(); +} +GEL_Toolbar2() +{ + Run_Realtime_with_Restart(); +} +GEL_Toolbar3() +{ + Full_Halt(); +} +GEL_Toolbar4() +{ + Full_Halt_with_Reset(); +} + +int GEL_Toolbar5_Toggle = 0; +GEL_Toolbar5() +{ + if(GEL_Toolbar5_Toggle == 0) + { + GEL_Toolbar5_Toggle = 1; + GEL_OpenWindow("GEL_Buttons",1,4); + GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0); + GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1); + GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2); + GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3); + } + else + { + GEL_Toolbar5_Toggle = 0; + GEL_CloseWindow("GEL_Buttons"); + } +} + + +/********************************************************************/ +/* These functions are useful to engage/dis-enagage realtime */ +/* emulation mode during debug. They save the user from having to */ +/* manually perform these steps in CCS. */ +/********************************************************************/ +menuitem "Realtime Emulation Control"; + +hotmenu Run_Realtime_with_Reset() +{ + GEL_Reset(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Run_Realtime_with_Restart() +{ + GEL_Restart(); /* Reset the DSP */ + ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */ + GEL_EnableRealtime(); /* Enable Realtime mode */ + GEL_Run(); /* Run the DSP */ +} +hotmenu Full_Halt() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ +} +hotmenu Full_Halt_with_Reset() +{ + GEL_DisableRealtime(); /* Disable Realtime mode */ + GEL_Halt(); /* Halt the DSP */ + GEL_Reset(); /* Reset the DSP */ +} + + +/********************************************************************/ +/* F28335 Memory Map */ +/* */ +/* Note: M0M1MAP and VMAP signals tied high on F28335 core */ +/* */ +/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ +/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ +/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ +/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ +/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ +/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ +/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ +/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ +/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ +/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ +/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ +/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ +/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ +/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ +/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ +/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ +/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */ +/* 0x300000 - 0x33ffff Flash (Prog and Data) */ +/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ +/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ +/* 0x380400 - 0x3807ff OTP (Prog and Data) */ +/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ +/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ +/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ +/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ +/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ +/********************************************************************/ +menuitem "Initialize Memory Map"; + +hotmenu F28335_Memory_Map() +{ + GEL_MapReset(); + GEL_MapOn(); + + /* Program memory map */ + GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ + + /* Data memory map */ + GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ + GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ + GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ + GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ + GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ + GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ + GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ + GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ + GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ + GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ + GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ + GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ + GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ + GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ + GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ + GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ + GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ + GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */ + GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ + GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ + GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ + GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ + GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ + GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ + GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ + GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ +} + + +/********************************************************************/ +/* The ESTOP0 fill functions are useful for debug. They fill the */ +/* RAM with software breakpoints that will trap runaway code. */ +/********************************************************************/ +hotmenu Fill_F28335_RAM_with_ESTOP0() +{ + GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */ + GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */ + GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */ + GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */ + GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */ +} + + +/********************************************************************/ +menuitem "Watchdog"; +hotmenu Disable_WD() +{ + *0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */ + *0x7025 = 0x0055; /* Service the WD */ + *0x7025 = 0x00AA; /* once to be safe. */ + GEL_TextOut("\nWatchdog Timer Disabled"); +} + + +/********************************************************************/ +menuitem "Code Security Module" +hotmenu Unlock_CSM() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + /* Write passwords to the KEY registers. 0xFFFF's are dummy passwords. + User should replace them with the correct password for their DSP */ + *0xAE0 = 0xFFFF; + *0xAE1 = 0xFFFF; + *0xAE2 = 0xFFFF; + *0xAE3 = 0xFFFF; + *0xAE4 = 0xFFFF; + *0xAE5 = 0xFFFF; + *0xAE6 = 0xFFFF; + *0xAE7 = 0xFFFF; +} + + +/********************************************************************/ +menuitem "Addressing Modes"; +hotmenu C28x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C24x_Mode() +{ + ST1 = ST1 | 0x0100; /* AMODE = 1 */ + ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ +} +hotmenu C27x_Mode() +{ + ST1 = ST1 & (~0x0100); /* AMODE = 0 */ + ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ +} + + +/********************************************************************/ +/* PLL Ratios */ +/* */ +/* The following table describes the PLL clocking ratios (0..10) */ +/* */ +/* Ratio CLKIN Description */ +/* ----- -------------- ------------ */ +/* 0 OSCCLK/2 PLL bypassed */ +/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */ +/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */ +/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */ +/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */ +/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */ +/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */ +/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */ +/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */ +/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */ +/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */ +/********************************************************************/ +menuitem "Set PLL Ratio"; + +hotmenu Bypass() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */ + PLL_Wait(); +} +hotmenu OSCCLK_x1_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x2_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x3_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x4_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x5_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x6_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x7_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x8_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x9_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */ + PLL_Wait(); +} +hotmenu OSCCLK_x10_divided_by_2() +{ + DIVSEL_div2(); /* DIVSEL = 1/2 */ + *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */ + PLL_Wait(); +} +// hotmenu OSCCLK_x1_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x2_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x3_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x4_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x5_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x6_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x7_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x8_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x9_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */ +// PLL_Wait(); +// } +// hotmenu OSCCLK_x10_divided_by_1() +// { +// DIVSEL_div1(); /* DIVSEL = 1/1 */ +// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */ +// PLL_Wait(); +// } + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */ +/********************************************************************/ + +DIVSEL_div2() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + temp = *PLLSTS; + temp &= 0xFE7F; /* Clear bits 7 & 8 */ + temp |= 2 << 7; /* Set bit 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + + + +/********************************************************************/ +/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */ +/********************************************************************/ + +DIVSEL_div1() +{ + int temp; + int PLLSTS; + + PLLSTS = 0x7011; + + DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */ + wait(); + temp = *PLLSTS; + temp |= 3 << 7; /* Set bits 7 & 8 */ + *PLLSTS = temp; /* Switch to 1/2 */ +} + +wait() +{ + int delay = 0; + for (delay = 0; delay <= 5; delay ++) + {} +} + +/********************************************************************/ +/* For F2833x devices, check the PLLOCKS bit for PLL lock. */ +/********************************************************************/ +PLL_Wait() +{ + int PLLSTS; + int delay = 0; + + PLLSTS = 0x7011; + + + while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001) + { + delay++; + GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); + } + GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS); +} + +/********************************************************************/ +/* Load the ADC Calibration values from TI OTP */ +/********************************************************************/ +menuitem "ADC Calibration" +hotmenu ADC_Cal() +{ + /* Perform dummy reads of the password locations */ + XAR0 = *0x33FFF8; + XAR0 = *0x33FFF9; + XAR0 = *0x33FFFA; + XAR0 = *0x33FFFB; + XAR0 = *0x33FFFC; + XAR0 = *0x33FFFD; + XAR0 = *0x33FFFE; + XAR0 = *0x33FFFF; + + + if(((*0x0AEF) & 0x0001) == 0) + { + XAR0 = *0x701C; + *0x701C |= 0x0008; + *0x711C = *0x380083; + *0x711D = *0x380085; + *0x701C = XAR0; + XAR0 = 0; + + } + else + { + GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate."); + } +} + +/********************************************************************/ +/* Enable the XINTF and configure GPIOs for XINTF function */ +/********************************************************************/ +menuitem "XINTF Enable" +hotmenu XINTF_Enable() +{ + + /* enable XINTF clock (XTIMCLK) */ + + *0x7020 = 0x3700; + /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ + /* XZCS7, XREADY, XRNW, XWE0 */ + /* GPAMUX2: XA17-XA19, XZCS6 */ + /* GPCMUX2: XA8-XA15 */ + /* GPCMUX1: XD0-XD15 */ + *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ + *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ + *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ + *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ + + /* Uncomment for x32 data bus */ + /* GPBMUX2: XD16-XD31 */ +// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ + + /* Zone timing. + /* Each zone can be configured seperately */ + /* Uncomment the x16 or the x32 timing */ + /* depending on the data bus width for */ + /* the zone */ + + /* x16 Timing */ + *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ + *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ + *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ + + /* x32 Timing: +// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ +// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ + + +} + + + + + +/********************************************************************/ +/* The below are used to display the symbolic names of the F28335 */ +/* memory mapped registers in the watch window. To view these */ +/* registers, click on the GEL menu button in Code Composer Studio, */ +/* then select which registers or groups of registers you want to */ +/* view. They will appear in the watch window under the Watch1 tab. */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "______________________________________"; +hotmenu __() {} + +/********************************************************************/ +/* A/D Converter Registers */ +/********************************************************************/ +menuitem "Watch ADC Registers"; + +hotmenu All_ADC_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); + + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} +hotmenu ADC_Control_Regs() +{ + GEL_WatchAdd("*0x7100,x","ADCTRL1"); + GEL_WatchAdd("*0x7101,x","ADCTRL2"); + GEL_WatchAdd("*0x7102,x","ADCMAXCONV"); + GEL_WatchAdd("*0x7107,x","ADCASEQSR"); + GEL_WatchAdd("*0x7118,x","ADCTRL3"); + GEL_WatchAdd("*0x7119,x","ADCST"); + GEL_WatchAdd("*0x711C,x","ADCREFSEL"); + GEL_WatchAdd("*0x711D,x","ADCOFFTRIM"); +} +hotmenu ADCCHSELSEQx_Regs() +{ + GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1"); + GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2"); + GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3"); + GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4"); +} +hotmenu ADCRESULT_0_to_7() +{ + GEL_WatchAdd("*0x7108,x","ADCRESULT0"); + GEL_WatchAdd("*0x7109,x","ADCRESULT1"); + GEL_WatchAdd("*0x710A,x","ADCRESULT2"); + GEL_WatchAdd("*0x710B,x","ADCRESULT3"); + GEL_WatchAdd("*0x710C,x","ADCRESULT4"); + GEL_WatchAdd("*0x710D,x","ADCRESULT5"); + GEL_WatchAdd("*0x710E,x","ADCRESULT6"); + GEL_WatchAdd("*0x710F,x","ADCRESULT7"); +} +hotmenu ADCRESULT_8_to_15() +{ + GEL_WatchAdd("*0x7110,x","ADCRESULT8"); + GEL_WatchAdd("*0x7111,x","ADCRESULT9"); + GEL_WatchAdd("*0x7112,x","ADCRESULT10"); + GEL_WatchAdd("*0x7113,x","ADCRESULT11"); + GEL_WatchAdd("*0x7114,x","ADCRESULT12"); + GEL_WatchAdd("*0x7115,x","ADCRESULT13"); + GEL_WatchAdd("*0x7116,x","ADCRESULT14"); + GEL_WatchAdd("*0x7117,x","ADCRESULT15"); +} +hotmenu ADCRESULT_Mirror_0_to_7() +{ + GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror"); + GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror"); + GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror"); + GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror"); + GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror"); + GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror"); + GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror"); + GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror"); +} +hotmenu ADCRESULT_Mirror_8_to_15() +{ + GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror"); + GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror"); + GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror"); + GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror"); + GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror"); + GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror"); + GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror"); + GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror"); +} + + +/********************************************************************/ +/* Clocking and Low-Power Registers */ +/********************************************************************/ +menuitem "Watch Clocking and Low-Power Registers"; + +hotmenu All_Clocking_and_Low_Power_Regs() +{ + GEL_WatchAdd("*0x7010,x","XCLK"); + GEL_WatchAdd("*0x7011,x","PLLSTS"); + GEL_WatchAdd("*0x701A,x","HISPCP"); + GEL_WatchAdd("*0x701B,x","LOSPCP"); + GEL_WatchAdd("*0x701C,x","PCLKCR0"); + GEL_WatchAdd("*0x701D,x","PCLKCR1"); + GEL_WatchAdd("*0x701E,x","LPMCR0"); + GEL_WatchAdd("*0x7020,x","PCLKCR3"); + GEL_WatchAdd("*0x7021,x","PLLCR"); +} + + +/********************************************************************/ +/* Code Security Module Registers */ +/********************************************************************/ +menuitem "Watch Code Security Module Registers"; + +hotmenu CSMSCR() +{ + GEL_WatchAdd("*0x0AEF,x","CSMSCR"); + GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit"); + GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit"); +} +hotmenu PWL_Locations() +{ + GEL_WatchAdd("*0x33FFF8,x","PWL0"); + GEL_WatchAdd("*0x33FFF9,x","PWL1"); + GEL_WatchAdd("*0x33FFFA,x","PWL2"); + GEL_WatchAdd("*0x33FFFB,x","PWL3"); + GEL_WatchAdd("*0x33FFFC,x","PWL4"); + GEL_WatchAdd("*0x33FFFD,x","PWL5"); + GEL_WatchAdd("*0x33FFFE,x","PWL6"); + GEL_WatchAdd("*0x33FFFF,x","PWL7"); +} + + +/********************************************************************/ +/* CPU Timer Registers */ +/********************************************************************/ +menuitem "Watch CPU Timer Registers"; + +hotmenu All_CPU_Timer0_Regs() +{ + GEL_WatchAdd("*0x0C00,x","TIMER0TIM"); + GEL_WatchAdd("*0x0C01,x","TIMER0TIMH"); + GEL_WatchAdd("*0x0C02,x","TIMER0PRD"); + GEL_WatchAdd("*0x0C03,x","TIMER0PRDH"); + GEL_WatchAdd("*0x0C04,x","TIMER0TCR"); + GEL_WatchAdd("*0x0C06,x","TIMER0TPR"); + GEL_WatchAdd("*0x0C07,x","TIMER0TPRH"); +} +hotmenu All_CPU_Timer1_Regs() +{ + GEL_WatchAdd("*0x0C08,x","TIMER1TIM"); + GEL_WatchAdd("*0x0C09,x","TIMER1TIMH"); + GEL_WatchAdd("*0x0C0A,x","TIMER1PRD"); + GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH"); + GEL_WatchAdd("*0x0C0C,x","TIMER1TCR"); + GEL_WatchAdd("*0x0C0E,x","TIMER1TPR"); + GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH"); +} +hotmenu All_CPU_Timer2_Regs() +{ + GEL_WatchAdd("*0x0C10,x","TIMER2TIM"); + GEL_WatchAdd("*0x0C11,x","TIMER2TIMH"); + GEL_WatchAdd("*0x0C12,x","TIMER2PRD"); + GEL_WatchAdd("*0x0C13,x","TIMER2PRDH"); + GEL_WatchAdd("*0x0C14,x","TIMER2TCR"); + GEL_WatchAdd("*0x0C16,x","TIMER2TPR"); + GEL_WatchAdd("*0x0C17,x","TIMER2TPRH"); +} + + +/********************************************************************/ +/* Device Emulation Registers */ +/********************************************************************/ +menuitem "Watch Device Emulation Registers"; + +hotmenu All_Emulation_Regs() +{ + GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF"); + GEL_WatchAdd("*0x0882,x","CLASSID"); + GEL_WatchAdd("*0x0883,x","REVID"); + GEL_WatchAdd("*0x0884,x","PROTSTART"); + GEL_WatchAdd("*0x0885,x","PROTRANGE"); + GEL_WatchAdd("*0x380090,x","PARTID"); +} +/********************************************************************/ +/* DMA Registers */ +/********************************************************************/ +menuitem "Watch DMA Registers"; + +hotmenu All_DMA_Regs() +{ + GEL_WatchAdd("*0x1000,x","DMACTRL"); + GEL_WatchAdd("*0x1001,x","DEBUGCTRL"); + GEL_WatchAdd("*0x1002,x","REVISION"); + GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1"); + GEL_WatchAdd("*0x1006,x","PRIORITYSTAT"); + + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); + + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); + + +} +hotmenu DMA_Channel_1_regs() +{ + GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE"); + GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL"); + GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE"); + GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT"); + GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP"); + GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE"); +} + +hotmenu DMA_Channel_2_regs() +{ + GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE"); + GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL"); + GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE"); + GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT"); + GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP"); + GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_3_regs() +{ + GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE"); + GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL"); + GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE"); + GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT"); + GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP"); + GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_4_regs() +{ + GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE"); + GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL"); + GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE"); + GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT"); + GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP"); + GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP"); + GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE"); + GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT"); + GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_5_regs() +{ + GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE"); + GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL"); + GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE"); + GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT"); + GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP"); + GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE"); +} +hotmenu DMA_Channel_6_regs() +{ + GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE"); + GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL"); + GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE"); + GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT"); + GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP"); + GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP"); + GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE"); + GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT"); + GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP"); + GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP"); + GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE"); + GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT"); + GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP"); + GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE"); + GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT"); + GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP"); + GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW"); + GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE"); + GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE"); +} + +/********************************************************************/ +/* eCAN Registers */ +/********************************************************************/ +menuitem "Watch eCAN Registers"; + +hotmenu eCAN_A_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME"); + GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD"); + GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS"); + GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR"); + GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA"); + GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA"); + GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP"); + GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML"); + GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP"); + GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC"); + GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC"); + GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES"); + GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC"); + GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC"); + GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0"); + GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM"); + GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1"); + GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM"); + GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL"); + GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC"); + GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC"); + GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC"); + GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT"); + GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC"); + GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS"); +} +hotmenu eCAN_A_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0"); + GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0"); + GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0"); + GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0"); + GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0"); + GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0"); + GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0"); + + GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1"); + GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1"); + GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1"); + GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1"); + GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1"); + GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1"); + GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1"); +} +hotmenu eCAN_A_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2"); + GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2"); + GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2"); + GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2"); + GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2"); + GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2"); + GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2"); + + GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3"); + GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3"); + GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3"); + GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3"); + GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3"); + GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3"); + GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3"); +} +hotmenu eCAN_A_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4"); + GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4"); + GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4"); + GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4"); + GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4"); + GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4"); + GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4"); + + GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5"); + GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5"); + GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5"); + GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5"); + GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5"); + GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5"); + GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5"); +} +hotmenu eCAN_A_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6"); + GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6"); + GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6"); + GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6"); + GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6"); + GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6"); + GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6"); + + GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7"); + GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7"); + GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7"); + GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7"); + GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7"); + GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7"); + GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7"); +} +hotmenu eCAN_A_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8"); + GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8"); + GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8"); + GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8"); + GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8"); + GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8"); + GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8"); + + GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9"); + GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9"); + GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9"); + GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9"); + GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9"); + GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9"); + GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9"); +} +hotmenu eCAN_A_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10"); + GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10"); + GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10"); + GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10"); + GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10"); + GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10"); + GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10"); + + GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11"); + GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11"); + GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11"); + GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11"); + GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11"); + GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11"); + GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11"); +} +hotmenu eCAN_A_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12"); + GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12"); + GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12"); + GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12"); + GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12"); + GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12"); + GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12"); + + GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13"); + GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13"); + GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13"); + GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13"); + GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13"); + GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13"); + GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13"); +} +hotmenu eCAN_A_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14"); + GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14"); + GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14"); + GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14"); + GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14"); + GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14"); + GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14"); + + GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15"); + GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15"); + GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15"); + GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15"); + GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15"); + GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15"); + GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15"); +} +hotmenu eCAN_A_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16"); + GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16"); + GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16"); + GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16"); + GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16"); + GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16"); + GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16"); + + GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17"); + GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17"); + GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17"); + GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17"); + GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17"); + GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17"); + GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17"); +} +hotmenu eCAN_A_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18"); + GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18"); + GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18"); + GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18"); + GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18"); + GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18"); + GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18"); + + GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19"); + GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19"); + GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19"); + GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19"); + GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19"); + GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19"); + GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19"); +} +hotmenu eCAN_A_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20"); + GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20"); + GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20"); + GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20"); + GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20"); + GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20"); + GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20"); + + GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21"); + GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21"); + GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21"); + GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21"); + GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21"); + GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21"); + GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21"); +} +hotmenu eCAN_A_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22"); + GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22"); + GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22"); + GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22"); + GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22"); + GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22"); + GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22"); + + GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23"); + GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23"); + GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23"); + GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23"); + GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23"); + GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23"); + GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23"); +} +hotmenu eCAN_A_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24"); + GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24"); + GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24"); + GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24"); + GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24"); + GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24"); + GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24"); + + GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25"); + GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25"); + GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25"); + GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25"); + GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25"); + GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25"); + GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25"); +} +hotmenu eCAN_A_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26"); + GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26"); + GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26"); + GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26"); + GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26"); + GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26"); + GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26"); + + GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27"); + GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27"); + GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27"); + GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27"); + GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27"); + GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27"); + GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27"); +} +hotmenu eCAN_A_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28"); + GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28"); + GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28"); + GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28"); + GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28"); + GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28"); + GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28"); + + GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29"); + GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29"); + GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29"); + GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29"); + GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29"); + GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29"); + GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29"); +} +hotmenu eCAN_A_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30"); + GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30"); + GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30"); + GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30"); + GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30"); + GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30"); + GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30"); + + GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31"); + GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31"); + GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31"); + GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31"); + GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31"); + GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31"); + GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31"); +} +hotmenu eCAN_B_Global_Regs() +{ + GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME"); + GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD"); + GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS"); + GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR"); + GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA"); + GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA"); + GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP"); + GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML"); + GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP"); + GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC"); + GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC"); + GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES"); + GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC"); + GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC"); + GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0"); + GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM"); + GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1"); + GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM"); + GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL"); + GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC"); + GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC"); + GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC"); + GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT"); + GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC"); + GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS"); +} +hotmenu eCAN_B_Mailbox_0_to_1_Regs() +{ + GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0"); + GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0"); + GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0"); + GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0"); + GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0"); + GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0"); + GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0"); + + GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1"); + GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1"); + GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1"); + GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1"); + GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1"); + GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1"); + GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1"); +} +hotmenu eCAN_B_Mailbox_2_to_3_Regs() +{ + GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2"); + GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2"); + GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2"); + GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2"); + GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2"); + GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2"); + GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2"); + + GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3"); + GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3"); + GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3"); + GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3"); + GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3"); + GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3"); + GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3"); +} +hotmenu eCAN_B_Mailbox_4_to_5_Regs() +{ + GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4"); + GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4"); + GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4"); + GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4"); + GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4"); + GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4"); + GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4"); + + GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5"); + GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5"); + GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5"); + GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5"); + GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5"); + GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5"); + GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5"); +} +hotmenu eCAN_B_Mailbox_6_to_7_Regs() +{ + GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6"); + GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6"); + GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6"); + GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6"); + GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6"); + GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6"); + GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6"); + + GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7"); + GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7"); + GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7"); + GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7"); + GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7"); + GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7"); + GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7"); +} +hotmenu eCAN_B_Mailbox_8_to_9_Regs() +{ + GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8"); + GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8"); + GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8"); + GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8"); + GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8"); + GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8"); + GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8"); + + GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9"); + GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9"); + GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9"); + GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9"); + GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9"); + GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9"); + GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9"); +} +hotmenu eCAN_B_Mailbox_10_to_11_Regs() +{ + GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10"); + GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10"); + GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10"); + GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10"); + GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10"); + GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10"); + GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10"); + + GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11"); + GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11"); + GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11"); + GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11"); + GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11"); + GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11"); + GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11"); +} +hotmenu eCAN_B_Mailbox_12_to_13_Regs() +{ + GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12"); + GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12"); + GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12"); + GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12"); + GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12"); + GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12"); + GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12"); + + GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13"); + GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13"); + GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13"); + GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13"); + GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13"); + GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13"); + GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13"); +} +hotmenu eCAN_B_Mailbox_14_to_15_Regs() +{ + GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14"); + GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14"); + GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14"); + GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14"); + GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14"); + GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14"); + GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14"); + + GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15"); + GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15"); + GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15"); + GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15"); + GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15"); + GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15"); + GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15"); +} +hotmenu eCAN_B_Mailbox_16_to_17_Regs() +{ + GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16"); + GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16"); + GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16"); + GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16"); + GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16"); + GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16"); + GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16"); + + GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17"); + GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17"); + GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17"); + GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17"); + GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17"); + GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17"); + GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17"); +} +hotmenu eCAN_B_Mailbox_18_to_19_Regs() +{ + GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18"); + GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18"); + GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18"); + GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18"); + GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18"); + GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18"); + GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18"); + + GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19"); + GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19"); + GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19"); + GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19"); + GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19"); + GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19"); + GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19"); +} +hotmenu eCAN_B_Mailbox_20_to_21_Regs() +{ + GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20"); + GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20"); + GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20"); + GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20"); + GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20"); + GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20"); + GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20"); + + GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21"); + GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21"); + GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21"); + GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21"); + GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21"); + GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21"); + GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21"); +} +hotmenu eCAN_B_Mailbox_22_to_23_Regs() +{ + GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22"); + GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22"); + GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22"); + GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22"); + GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22"); + GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22"); + GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22"); + + GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23"); + GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23"); + GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23"); + GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23"); + GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23"); + GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23"); + GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23"); +} +hotmenu eCAN_B_Mailbox_24_to_25_Regs() +{ + GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24"); + GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24"); + GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24"); + GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24"); + GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24"); + GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24"); + GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24"); + + GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25"); + GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25"); + GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25"); + GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25"); + GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25"); + GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25"); + GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25"); +} +hotmenu eCAN_B_Mailbox_26_to_27_Regs() +{ + GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26"); + GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26"); + GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26"); + GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26"); + GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26"); + GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26"); + GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26"); + + GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27"); + GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27"); + GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27"); + GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27"); + GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27"); + GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27"); + GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27"); +} +hotmenu eCAN_B_Mailbox_28_to_29_Regs() +{ + GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28"); + GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28"); + GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28"); + GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28"); + GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28"); + GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28"); + GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28"); + + GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29"); + GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29"); + GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29"); + GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29"); + GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29"); + GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29"); + GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29"); +} +hotmenu eCAN_B_Mailbox_30_to_31_Regs() +{ + GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30"); + GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30"); + GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30"); + GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30"); + GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30"); + GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30"); + GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30"); + + GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31"); + GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31"); + GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31"); + GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31"); + GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31"); + GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31"); + GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31"); +} + + +/********************************************************************/ +/* Enhanced Capture Registers */ +/********************************************************************/ +menuitem "Watch eCAP Registers"; + +hotmenu eCAP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT"); + GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1"); + GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2"); + GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3"); + GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4"); + GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1"); + GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2"); + GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT"); + GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG"); + GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR"); + GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC"); +} +hotmenu eCAP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT"); + GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1"); + GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2"); + GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3"); + GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4"); + GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1"); + GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2"); + GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT"); + GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG"); + GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR"); + GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC"); +} +hotmenu eCAP3_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT"); + GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1"); + GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2"); + GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3"); + GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4"); + GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1"); + GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2"); + GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT"); + GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG"); + GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR"); + GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC"); +} +hotmenu eCAP4_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT"); + GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1"); + GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2"); + GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3"); + GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4"); + GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1"); + GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2"); + GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT"); + GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG"); + GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR"); + GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC"); +} +hotmenu eCAP5_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT"); + GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS"); + GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1"); + GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2"); + GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3"); + GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4"); + GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1"); + GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2"); + GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT"); + GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG"); + GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR"); + GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC"); +} +hotmenu eCAP6_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT"); + GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS"); + GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1"); + GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2"); + GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3"); + GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4"); + GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1"); + GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2"); + GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT"); + GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG"); + GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR"); + GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC"); +} + + +/********************************************************************/ +/* Enhanced PWM Registers */ +/********************************************************************/ +menuitem "Watch ePWM Registers"; + +hotmenu ePWM1_All_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG"); +} +hotmenu ePWM1_TB_Regs() +{ + GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD"); +} +hotmenu ePWM1_CMP_Regs() +{ + GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x6809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x680A,x","ePWM1 CMPB"); +} +hotmenu ePWM1_AQ_Regs() +{ + GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC"); +} +hotmenu ePWM1_DB_Regs() +{ + GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x6810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x6811,x","ePWM1 DBFED"); +} +hotmenu ePWM1_TZ_Regs() +{ + GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC"); +} +hotmenu ePWM1_ET_Regs() +{ + GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x681A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC"); +} +hotmenu ePWM2_All_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM2_TB_Regs() +{ + GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD"); +} +hotmenu ePWM2_CMP_Regs() +{ + GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x6849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x684A,x","ePWM2 CMPB"); +} +hotmenu ePWM2_AQ_Regs() +{ + GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC"); +} +hotmenu ePWM2_DB_Regs() +{ + GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x6850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x6851,x","ePWM2 DBFED"); +} +hotmenu ePWM2_TZ_Regs() +{ + GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC"); +} +hotmenu ePWM2_ET_Regs() +{ + GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x685A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC"); +} +hotmenu ePWM3_All_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM3_TB_Regs() +{ + GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD"); +} +hotmenu ePWM3_CMP_Regs() +{ + GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x6889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x688A,x","ePWM3 CMPB"); +} +hotmenu ePWM3_AQ_Regs() +{ + GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC"); +} +hotmenu ePWM3_DB_Regs() +{ + GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x6890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x6891,x","ePWM3 DBFED"); +} +hotmenu ePWM3_TZ_Regs() +{ + GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC"); +} +hotmenu ePWM3_ET_Regs() +{ + GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x689A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC"); +} +hotmenu ePWM4_All_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM4_TB_Regs() +{ + GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD"); +} +hotmenu ePWM4_CMP_Regs() +{ + GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB"); +} +hotmenu ePWM4_AQ_Regs() +{ + GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC"); +} +hotmenu ePWM4_DB_Regs() +{ + GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED"); +} +hotmenu ePWM4_TZ_Regs() +{ + GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC"); +} +hotmenu ePWM4_ET_Regs() +{ + GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC"); +} +hotmenu ePWM5_All_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM5_TB_Regs() +{ + GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD"); +} +hotmenu ePWM5_CMP_Regs() +{ + GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x6909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x690A,x","ePWM5 CMPB"); +} +hotmenu ePWM5_AQ_Regs() +{ + GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC"); +} +hotmenu ePWM5_DB_Regs() +{ + GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x6910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x6911,x","ePWM5 DBFED"); +} +hotmenu ePWM5_TZ_Regs() +{ + GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC"); +} +hotmenu ePWM5_ET_Regs() +{ + GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x691A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC"); +} +hotmenu ePWM6_All_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG"); + +} +hotmenu ePWM6_TB_Regs() +{ + GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD"); +} +hotmenu ePWM6_CMP_Regs() +{ + GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x6949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x694A,x","ePWM6 CMPB"); +} +hotmenu ePWM6_AQ_Regs() +{ + GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC"); +} +hotmenu ePWM6_DB_Regs() +{ + GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x6950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x6951,x","ePWM6 DBFED"); +} +hotmenu ePWM6_TZ_Regs() +{ + GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC"); +} +hotmenu ePWM6_ET_Regs() +{ + GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x695A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC"); +} + + +/********************************************************************/ +/* Enhanced EQEP Registers */ +/********************************************************************/ +menuitem "Watch eQEP" + +hotmenu eQEP1_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT"); + GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR"); + GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD"); + GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR"); + GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD"); + GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL"); + GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL"); + GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL"); + GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL"); + GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT"); + GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG"); + GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR"); + GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC"); + GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS"); + GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR"); + GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD"); + GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT"); + GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT"); +} +hotmenu eQEP2_All_Regs() +{ + GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT"); + GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT"); + GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX"); + GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP"); + GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT"); + GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT"); + GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT"); + GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR"); + GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD"); + GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR"); + GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD"); + GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL"); + GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL"); + GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL"); + GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL"); + GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT"); + GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG"); + GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR"); + GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC"); + GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS"); + GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR"); + GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD"); + GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT"); + GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT"); +} + + +/********************************************************************/ +/* External Interface Registers */ +/********************************************************************/ +menuitem "Watch External Interface Registers"; + +hotmenu All_External_Interface_Regs() +{ + GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0"); + GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6"); + GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7"); + GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2"); + GEL_WatchAdd("*0x0B38,x","XBANK"); + GEL_WatchAdd("*0x0B3A,x","XREVISION"); + GEL_WatchAdd("*0x0B3D,x","XRESET"); +} + +/********************************************************************/ +/* External Interrupt Registers */ +/********************************************************************/ +menuitem "Watch External Interrupt Registers"; + +hotmenu All_XINT_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} +hotmenu XINT_Control_Regs() +{ + GEL_WatchAdd("*0x7070,x","XINT1CR"); + GEL_WatchAdd("*0x7071,x","XINT2CR"); + GEL_WatchAdd("*0x7072,x","XINT3CR"); + GEL_WatchAdd("*0x7073,x","XINT4CR"); + GEL_WatchAdd("*0x7074,x","XINT5CR"); + GEL_WatchAdd("*0x7075,x","XINT6CR"); + GEL_WatchAdd("*0x7076,x","XINT7CR"); + GEL_WatchAdd("*0x7077,x","XNMICR"); +} +hotmenu XINT_Counter_Regs() +{ + GEL_WatchAdd("*0x7078,x","XINT1CTR"); + GEL_WatchAdd("*0x7079,x","XINT2CTR"); + GEL_WatchAdd("*0x707F,x","XNMICTR"); +} + + +/********************************************************************/ +/* FPU Registers */ +/********************************************************************/ +menuitem "Watch FPU Registers" + +hotmenu All_FPU_Single_Precision_Regs() +{ + GEL_WatchAdd("RB"); + GEL_WatchAdd("STF"); + GEL_WatchAdd("R0H"); + GEL_WatchAdd("R1H"); + GEL_WatchAdd("R2H"); + GEL_WatchAdd("R3H"); + GEL_WatchAdd("R4H"); + GEL_WatchAdd("R5H"); + GEL_WatchAdd("R6H"); + GEL_WatchAdd("R7H"); +} + + +/********************************************************************/ +/* GPIO Registers */ +/********************************************************************/ +menuitem "Watch GPIO Registers"; + +hotmenu All_GPIO_CONTROL_Regs() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); +} +hotmenu All_GPIO_DATA_Regs() +{ + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} +hotmenu All_GPIO_INTERRUPT_Regs() +{ + GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL"); + GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL"); + GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL"); + GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL"); + GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL"); + GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL"); + GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL"); + GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL"); + GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL"); +} +hotmenu All_GPA_Registers() +{ + GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL"); + GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1"); + GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2"); + GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1"); + GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2"); + GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR"); + GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD"); + + GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT"); + GEL_WatchAdd("*(long *)0x6FC2,x","GPASET"); + GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR"); + GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE"); +} +hotmenu All_GPB_Registers() +{ + GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL"); + GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1"); + GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2"); + GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1"); + GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2"); + GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR"); + GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); +} +hotmenu All_GPC_Registers() +{ + GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1"); + GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2"); + GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR"); + GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD"); + + GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT"); + GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET"); + GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR"); + GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE"); + + GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT"); + GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET"); + GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR"); + GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE"); +} + + +/********************************************************************/ +/* Multichannel Serial Port Registers */ +/********************************************************************/ +menuitem "Watch McBSP Registers"; + +hotmenu All_McBSP_A_Regs() +{ + GEL_WatchAdd("*0x5000,x","McBSPA DRR2"); + GEL_WatchAdd("*0x5001,x","McBSPA DRR1"); + GEL_WatchAdd("*0x5002,x","McBSPA DXR2"); + GEL_WatchAdd("*0x5003,x","McBSPA DXR1"); + GEL_WatchAdd("*0x5004,x","McBSPA SPCR2"); + GEL_WatchAdd("*0x5005,x","McBSPA SPCR1"); + GEL_WatchAdd("*0x5006,x","McBSPA RCR2"); + GEL_WatchAdd("*0x5007,x","McBSPA RCR1"); + GEL_WatchAdd("*0x5008,x","McBSPA XCR2"); + GEL_WatchAdd("*0x5009,x","McBSPA XCR1"); + GEL_WatchAdd("*0x500A,x","McBSPA SRGR2"); + GEL_WatchAdd("*0x500B,x","McBSPA SRGR1"); + GEL_WatchAdd("*0x500C,x","McBSPA MCR2"); + GEL_WatchAdd("*0x500D,x","McBSPA MCR1"); + GEL_WatchAdd("*0x500E,x","McBSPA RCERA"); + GEL_WatchAdd("*0x500F,x","McBSPA RCERB"); + GEL_WatchAdd("*0x5010,x","McBSPA XCERA"); + GEL_WatchAdd("*0x5011,x","McBSPA XCERB"); + GEL_WatchAdd("*0x5012,x","McBSPA PCR1"); + GEL_WatchAdd("*0x5013,x","McBSPA RCERC"); + GEL_WatchAdd("*0x5014,x","McBSPA RCERD"); + GEL_WatchAdd("*0x5015,x","McBSPA XCERC"); + GEL_WatchAdd("*0x5016,x","McBSPA XCERD"); + GEL_WatchAdd("*0x5017,x","McBSPA RCERE"); + GEL_WatchAdd("*0x5018,x","McBSPA RCERF"); + GEL_WatchAdd("*0x5019,x","McBSPA XCERE"); + GEL_WatchAdd("*0x501A,x","McBSPA XCERF"); + GEL_WatchAdd("*0x501B,x","McBSPA RCERG"); + GEL_WatchAdd("*0x501C,x","McBSPA RCERH"); + GEL_WatchAdd("*0x501D,x","McBSPA XCERG"); + GEL_WatchAdd("*0x501E,x","McBSPA XCERH"); + GEL_WatchAdd("*0x5023,x","McBSPA MFFINT"); + GEL_WatchAdd("*0x503F,x","McBSPA Revision"); +} + +hotmenu All_McBSP_B_Regs() +{ + GEL_WatchAdd("*0x5040,x","McBSPB DRR2"); + GEL_WatchAdd("*0x5041,x","McBSPB DRR1"); + GEL_WatchAdd("*0x5042,x","McBSPB DXR2"); + GEL_WatchAdd("*0x5043,x","McBSPB DXR1"); + GEL_WatchAdd("*0x5044,x","McBSPB SPCR2"); + GEL_WatchAdd("*0x5045,x","McBSPB SPCR1"); + GEL_WatchAdd("*0x5046,x","McBSPB RCR2"); + GEL_WatchAdd("*0x5047,x","McBSPB RCR1"); + GEL_WatchAdd("*0x5048,x","McBSPB XCR2"); + GEL_WatchAdd("*0x5049,x","McBSPB XCR1"); + GEL_WatchAdd("*0x504A,x","McBSPB SRGR2"); + GEL_WatchAdd("*0x504B,x","McBSPB SRGR1"); + GEL_WatchAdd("*0x504C,x","McBSPB MCR2"); + GEL_WatchAdd("*0x504D,x","McBSPB MCR1"); + GEL_WatchAdd("*0x504E,x","McBSPB RCERA"); + GEL_WatchAdd("*0x504F,x","McBSPB RCERB"); + GEL_WatchAdd("*0x5050,x","McBSPB XCERA"); + GEL_WatchAdd("*0x5051,x","McBSPB XCERB"); + GEL_WatchAdd("*0x5052,x","McBSPB PCR1"); + GEL_WatchAdd("*0x5053,x","McBSPB RCERC"); + GEL_WatchAdd("*0x5054,x","McBSPB RCERD"); + GEL_WatchAdd("*0x5055,x","McBSPB XCERC"); + GEL_WatchAdd("*0x5056,x","McBSPB XCERD"); + GEL_WatchAdd("*0x5057,x","McBSPB RCERE"); + GEL_WatchAdd("*0x5058,x","McBSPB RCERF"); + GEL_WatchAdd("*0x5059,x","McBSPB XCERE"); + GEL_WatchAdd("*0x505A,x","McBSPB XCERF"); + GEL_WatchAdd("*0x505B,x","McBSPB RCERG"); + GEL_WatchAdd("*0x505C,x","McBSPB RCERH"); + GEL_WatchAdd("*0x505D,x","McBSPB XCERG"); + GEL_WatchAdd("*0x505E,x","McBSPB XCERH"); + GEL_WatchAdd("*0x5063,x","McBSPB MFFINT"); + GEL_WatchAdd("*0x506F,x","McBSPB Revision"); +} + + + +/********************************************************************/ +/* I2C Registers */ +/********************************************************************/ +menuitem "Watch I2C Registers"; + +hotmenu All_I2C_Regs() +{ + GEL_WatchAdd("*0x7900,x","I2COAR"); + GEL_WatchAdd("*0x7901,x","I2CIER"); + GEL_WatchAdd("*0x7902,x","I2CSTR"); + GEL_WatchAdd("*0x7903,x","I2CCLKL"); + GEL_WatchAdd("*0x7904,x","I2CCLKH"); + GEL_WatchAdd("*0x7905,x","I2CCNT"); + GEL_WatchAdd("*0x7906,x","I2CDRR"); + GEL_WatchAdd("*0x7907,x","I2CSAR"); + GEL_WatchAdd("*0x7908,x","I2CDXR"); + GEL_WatchAdd("*0x7909,x","I2CMDR"); + GEL_WatchAdd("*0x790A,x","I2CISRC"); + GEL_WatchAdd("*0x790C,x","I2CPSC"); + GEL_WatchAdd("*0x7920,x","I2CFFTX"); + GEL_WatchAdd("*0x7921,x","I2CFFRX"); +} + + +/********************************************************************/ +/* Peripheral Interrupt Expansion Registers */ +/********************************************************************/ +menuitem "Watch Peripheral Interrupt Expansion Registers"; + +hotmenu All_PIE_Regs() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); + GEL_WatchAdd("*0x0CE1,x","PIEACK"); + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} +hotmenu PIECTRL() +{ + GEL_WatchAdd("*0x0CE0,x","PIECTRL"); +} +hotmenu PIEACK() +{ + GEL_WatchAdd("*0x0CE1,x","PIEACK"); +} +hotmenu PIEIER1_and_PIEIFR1() +{ + GEL_WatchAdd("*0x0CE2,x","PIEIER1"); + GEL_WatchAdd("*0x0CE3,x","PIEIFR1"); +} +hotmenu PIEIER2_and_PIEIFR2() +{ + GEL_WatchAdd("*0x0CE4,x","PIEIER2"); + GEL_WatchAdd("*0x0CE5,x","PIEIFR2"); +} +hotmenu PIEIER3_and_PIEIFR3() +{ + GEL_WatchAdd("*0x0CE6,x","PIEIER3"); + GEL_WatchAdd("*0x0CE7,x","PIEIFR3"); +} +hotmenu PIEIER4_and_PIEIFR4() +{ + GEL_WatchAdd("*0x0CE8,x","PIEIER4"); + GEL_WatchAdd("*0x0CE9,x","PIEIFR4"); +} +hotmenu PIEIER5_and_PIEIFR5() +{ + GEL_WatchAdd("*0x0CEA,x","PIEIER5"); + GEL_WatchAdd("*0x0CEB,x","PIEIFR5"); +} +hotmenu PIEIER6_and_PIEIFR6() +{ + GEL_WatchAdd("*0x0CEC,x","PIEIER6"); + GEL_WatchAdd("*0x0CED,x","PIEIFR6"); +} +hotmenu PIEIER7_and_PIEIFR7() +{ + GEL_WatchAdd("*0x0CEE,x","PIEIER7"); + GEL_WatchAdd("*0x0CEF,x","PIEIFR7"); +} +hotmenu PIEIER8_and_PIEIFR8() +{ + GEL_WatchAdd("*0x0CF0,x","PIEIER8"); + GEL_WatchAdd("*0x0CF1,x","PIEIFR8"); +} +hotmenu PIEIER9_and_PIEIFR9() +{ + GEL_WatchAdd("*0x0CF2,x","PIEIER9"); + GEL_WatchAdd("*0x0CF3,x","PIEIFR9"); +} +hotmenu PIEIFR10_and_PIEIFR10() +{ + GEL_WatchAdd("*0x0CF4,x","PIEIER10"); + GEL_WatchAdd("*0x0CF5,x","PIEIFR10"); +} +hotmenu PIEIER11_and_PIEIFR11() +{ + GEL_WatchAdd("*0x0CF6,x","PIEIER11"); + GEL_WatchAdd("*0x0CF7,x","PIEIFR11"); +} +hotmenu PIEIER12_and_PIEIFR12() +{ + GEL_WatchAdd("*0x0CF8,x","PIEIER12"); + GEL_WatchAdd("*0x0CF9,x","PIEIFR12"); +} + + +/********************************************************************/ +/* Serial Communication Interface Registers */ +/********************************************************************/ +menuitem "Watch SCI Registers"; + +hotmenu SCI_A_All_Regs() +{ + GEL_WatchAdd("*0x7050,x","SCICCRA"); + GEL_WatchAdd("*0x7051,x","SCICTL1A"); + GEL_WatchAdd("*0x7052,x","SCIHBAUDA"); + GEL_WatchAdd("*0x7053,x","SCILBAUDA"); + GEL_WatchAdd("*0x7054,x","SCICTL2A"); + GEL_WatchAdd("*0x7055,x","SCIRXSTA"); + GEL_WatchAdd("*0x7056,x","SCIRXEMUA"); + GEL_WatchAdd("*0x7057,x","SCIRXBUFA"); + GEL_WatchAdd("*0x7059,x","SCITXBUFA"); + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); + GEL_WatchAdd("*0x705F,x","SCIPRIA"); +} +hotmenu SCI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x705A,x","SCIFFTXA"); + GEL_WatchAdd("*0x705B,x","SCIFFRXA"); + GEL_WatchAdd("*0x705C,x","SCIFFCTA"); +} +hotmenu SCI_B_All_Regs() +{ + GEL_WatchAdd("*0x7750,x","SCICCRB"); + GEL_WatchAdd("*0x7751,x","SCICTL1B"); + GEL_WatchAdd("*0x7752,x","SCIHBAUDB"); + GEL_WatchAdd("*0x7753,x","SCILBAUDB"); + GEL_WatchAdd("*0x7754,x","SCICTL2B"); + GEL_WatchAdd("*0x7755,x","SCIRXSTB"); + GEL_WatchAdd("*0x7756,x","SCIRXEMUB"); + GEL_WatchAdd("*0x7757,x","SCIRXBUFB"); + GEL_WatchAdd("*0x7759,x","SCITXBUFB"); + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); + GEL_WatchAdd("*0x775F,x","SCIPRIB"); +} +hotmenu SCI_B_FIFO_Registers() +{ + GEL_WatchAdd("*0x775A,x","SCIFFTXB"); + GEL_WatchAdd("*0x775B,x","SCIFFRXB"); + GEL_WatchAdd("*0x775C,x","SCIFFCTB"); +} +hotmenu SCI_C_All_Regs() +{ + GEL_WatchAdd("*0x7770,x","SCICCRC"); + GEL_WatchAdd("*0x7771,x","SCICTL1C"); + GEL_WatchAdd("*0x7772,x","SCIHBAUDC"); + GEL_WatchAdd("*0x7773,x","SCILBAUDC"); + GEL_WatchAdd("*0x7774,x","SCICTL2C"); + GEL_WatchAdd("*0x7775,x","SCIRXSTC"); + GEL_WatchAdd("*0x7776,x","SCIRXEMUC"); + GEL_WatchAdd("*0x7777,x","SCIRXBUFC"); + GEL_WatchAdd("*0x7779,x","SCITXBUFC"); + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); + GEL_WatchAdd("*0x777F,x","SCIPRIC"); +} +hotmenu SCI_C_FIFO_Registers() +{ + GEL_WatchAdd("*0x777A,x","SCIFFTXC"); + GEL_WatchAdd("*0x777B,x","SCIFFRXC"); + GEL_WatchAdd("*0x777C,x","SCIFFCTC"); +} + + +/********************************************************************/ +/* Serial Peripheral Interface Registers */ +/********************************************************************/ +menuitem "Watch SPI Registers"; + +hotmenu SPI_A_All_Regs() +{ + GEL_WatchAdd("*0x7040,x","SPIA SPICCR"); + GEL_WatchAdd("*0x7041,x","SPIA SPICTL"); + GEL_WatchAdd("*0x7042,x","SPIA SPIST"); + GEL_WatchAdd("*0x7044,x","SPIA SPIBRR"); + GEL_WatchAdd("*0x7046,x","SPIA SPIEMU"); + GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF"); + GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF"); + GEL_WatchAdd("*0x7049,x","SPIA SPIDAT"); + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); + GEL_WatchAdd("*0x704F,x","SPIA SPIPRI"); +} +hotmenu SPI_A_FIFO_Registers() +{ + GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX"); + GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX"); + GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT"); +} + + +/********************************************************************/ +/* Watchdog Timer Registers */ +/********************************************************************/ +menuitem "Watch Watchdog Timer Registers"; + +hotmenu All_Watchdog_Regs() +{ + GEL_WatchAdd("*0x7023,x","WDCNTR"); + GEL_WatchAdd("*0x7025,x","WDKEY"); + GEL_WatchAdd("*0x7029,x","WDCR"); + GEL_WatchAdd("*0x7022,x","SCSR"); +} + +/********************************************************************/ +/*** End of file ***/ diff --git a/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..8919b97 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h @@ -0,0 +1,147 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// Non-Peripheral Interrupts: +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// Group 1 PIE Interrupt Service Routines: +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// Group 2 PIE Interrupt Service Routines: +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// Group 3 PIE Interrupt Service Routines: +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// Group 4 PIE Interrupt Service Routines: +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// Group 5 PIE Interrupt Service Routines: +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// Group 6 PIE Interrupt Service Routines: +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// Group 7 PIE Interrupt Service Routines: +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// Group 8 PIE Interrupt Service Routines: +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// Group 9 PIE Interrupt Service Routines: +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// Group 10 PIE Interrupt Service Routines: + +// Group 11 PIE Interrupt Service Routines: + +// Group 12 PIE Interrupt Service Routines: +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// Catch-all for Reserved Locations For testing purposes: +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..7b8dfaf --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h @@ -0,0 +1,81 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// MODE +//========================== +// PERINTSEL bits +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 +// OVERINTE bit +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 +// PERINTE bit +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 +// CHINTMODE bits +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 +// ONESHOT bits +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 +// CONTINOUS bit +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 +// SYNCE bit +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 +// SYNCSEL bit +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 +// DATASIZE bit +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 +// CHINTE bit +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h new file mode 100644 index 0000000..061842f --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h @@ -0,0 +1,164 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// TBCTL (Time-Base Control) +//========================== +// CTRMODE bits +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 +// PHSEN bit +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 +// PRDLD bit +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 +// SYNCOSEL bits +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 +// HSPCLKDIV and CLKDIV bits +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 +// PHSDIR bit +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// CMPCTL (Compare Control) +//========================== +// LOADAMODE and LOADBMODE bits +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 +// SHDWAMODE and SHDWBMODE bits +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// AQCTLA and AQCTLB (Action Qualifier Control) +//============================================= +// ZRO, PRD, CAU, CAD, CBU, CBD bits +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// DBCTL (Dead-Band Control) +//========================== +// OUT MODE bits +#define DB_DISABLE 0x0 +#define DBA_ENABLE 0x1 +#define DBB_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 +// POLSEL bits +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 +// IN MODE +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// CHPCTL (chopper control) +//========================== +// CHPEN bit +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 +// CHPFREQ bits +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 +// CHPDUTY bits +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// TZSEL (Trip Zone Select) +//========================== +// CBCn and OSHTn bits +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// TZCTL (Trip Zone Control) +//========================== +// TZA and TZB bits +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// ETSEL (Event Trigger Select) +//============================= +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// ETPS (Event Trigger Pre-scale) +//=============================== +// INTPRD, SOCAPRD, SOCBPRD bits +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + + +//-------------------------------- +// HRPWM (High Resolution PWM) +//================================ +// HRCNFG +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_Examples.h b/v120/DSP2833x_common/include/DSP2833x_Examples.h new file mode 100644 index 0000000..c38ebb1 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_Examples.h @@ -0,0 +1,141 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------- + Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +-----------------------------------------------------------------------------*/ +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode +//---------------------------------------------------------------------------- + + +/*----------------------------------------------------------------------------- + Specify the clock rate of the CPU (SYSCLKOUT) in nS. + + Take into account the input clock frequency and the PLL multiplier + selected in step 1. + + Use one of the values provided, or define your own. + The trailing L is required tells the compiler to treat + the number as a 64-bit value. + + Only one statement should be uncommented. + + Example 1:150 MHz devices: + CLKIN is a 30MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 150Mhz CPU clock (SYSCLKOUT = 150MHz). + + In this case, the CPU_RATE will be 6.667L + Uncomment the line: #define CPU_RATE 6.667L + + Example 2: 100 MHz devices: + CLKIN is a 20MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 100Mhz CPU clock (SYSCLKOUT = 100MHz). + + In this case, the CPU_RATE will be 10.000L + Uncomment the line: #define CPU_RATE 10.000L +-----------------------------------------------------------------------------*/ +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +//---------------------------------------------------------------------------- + +/*----------------------------------------------------------------------------- + Target device (in DSP2833x_Device.h) determines CPU frequency + (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz + (for 28332). User does not have to change anything here. +-----------------------------------------------------------------------------*/ +#if DSP28_28332 // DSP28_28332 device only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + + +//--------------------------------------------------------------------------- +// Include Example Header Files: +// + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + // .c files. + +#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28332 0xED +#define PARTNO_28235 0xE8 +#define PARTNO_28234 0xE7 +#define PARTNO_28232 0xE6 + + +// Include files not used with DSP/BIOS +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultISR.h" +#endif + + +// DO NOT MODIFY THIS LINE. +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h new file mode 100644 index 0000000..9c90607 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h @@ -0,0 +1,207 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---- shared global function prototypes -----------------------------------*/ +extern void InitAdc(void); + +extern void DMAInitialize(void); +// DMA Channel 1 +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH1(void); +// DMA Channel 2 +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH2(void); +// DMA Channel 3 +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH3(void); +// DMA Channel 4 +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH4(void); +// DMA Channel 5 +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH5(void); +// DMA Channel 6 +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// DSP28_DBGIER.asm +extern void SetDBGIER(Uint16 dbgier); + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +extern void InitFlash(void); + + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + + +//--------------------------------------------------------------------------- +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h new file mode 100644 index 0000000..ce3f1f7 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h @@ -0,0 +1,117 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +//-------------------------------------------- +// Defines +//-------------------------------------------- + +// Error Messages +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// Clear Status Flags +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// Interrupt Source Messages +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// I2CMSG structure defines +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// I2C Slave State defines +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// I2C Slave Receiver messages defines +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// I2C State defines +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// I2C Message Commands for I2CMSG struct +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// Generic defines +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +//-------------------------------------------- +// Structures +//-------------------------------------------- + +// I2C Message Structure +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000..c3f3ea1 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h @@ -0,0 +1,5850 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:21 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedIsrLevels.h +// +// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SW_PRIORITZIED_ISR_H +#define DSP2833x_SW_PRIORITZIED_ISR_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//------------------------------------------------------------------------------- +// Interrupt Enable Register Allocation For 2833x Devices: +//------------------------------------------------------------------------------- +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +//------------------------------------------------------------------------------- +//------------------------------------------------------------------------------- +// Set "Global" Interrupt Priority Level (IER register): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 0 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 0 // reserved +#define INT8PL 0 // reserved +#define INT9PL 1 // Group9 Interrupts (PIEIER9) +#define INT10PL 0 // reserved +#define INT11PL 0 // reserved +#define INT12PL 0 // reserved +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +//------------------------------------------------------------------------------- +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 8 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG11 to MG18 +// MG21 to MG28 +// MG31 to MG38 +// MG41 to MG48 +// MG51 to MG58 +// MG61 to MG68 +// MG71 to MG78 +// MG81 to MG88 +// MG91 to MG98 +// MG101 to MG108 +// MG111 to MG118 +// MG121 to MG128 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 8 = lowest priority +// +#define G11PL 7 // SEQ1INT (ADC) +#define G12PL 6 // SEQ2INT (ADC) +#define G13PL 0 // reserved +#define G14PL 1 // XINT1 (External) +#define G15PL 3 // XINT2 (External) +#define G16PL 2 // ADCINT (ADC) +#define G17PL 1 // TINT0 (CPU Timer 0) +#define G18PL 5 // WAKEINT (WD/LPM) + +#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip) +#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip) +#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip) +#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip) +#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip) +#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip) +#define G27PL 0 // reserved +#define G28PL 0 // reserved + +#define G31PL 4 // EPWM1_INT (ePWM1 Int) +#define G32PL 1 // EPWM2_INT (ePWM2 Int) +#define G33PL 1 // EPWM3_INT (ePWM3 Int) +#define G34PL 2 // EPWM4_INT (ePWM4 Int) +#define G35PL 2 // EPWM5_INT (ePWM5 Int) +#define G36PL 1 // EPWM6_INT (ePWM6 Int) +#define G37PL 0 // reserved +#define G38PL 0 // reserved + +#define G41PL 2 // ECAP1_INT (eCAP1 Int) +#define G42PL 1 // ECAP2_INT (eCAP2 Int) +#define G43PL 3 // ECAP3_INT (eCAP3 Int) +#define G44PL 3 // ECAP4_INT (eCAP4 Int) +#define G45PL 5 // ECAP5_INT (eCAP5 Int) +#define G46PL 5 // ECAP6_INT (eCAP6 Int) +#define G47PL 0 // reserved +#define G48PL 0 // reserved + +#define G51PL 2 // EQEP1_INT (eQEP1 Int) +#define G52PL 1 // EQEP2_INT (eQEP2 Int) +#define G53PL 0 // reserved +#define G54PL 0 // reserved +#define G55PL 0 // reserved +#define G56PL 0 // reserved +#define G57PL 0 // reserved +#define G58PL 0 // reserved + +#define G61PL 3 // SPIRXINTA (SPI-A) +#define G62PL 1 // SPITXINTA (SPI-A) +#define G63PL 4 // MRINTB (McBSP-B) +#define G64PL 6 // MXINTB (McBSP-B) +#define G65PL 2 // MRINTA (McBSP-A) +#define G66PL 1 // MXINTA (McBSP-A) +#define G67PL 0 // reserved +#define G68PL 0 // reserved + +#define G71PL 5 // DINTCH1 (DMA) +#define G72PL 4 // DINTCH2 (DMA) +#define G73PL 4 // DINTCH3 (DMA) +#define G74PL 2 // DINTCH4 (DMA) +#define G75PL 3 // DINTCH5 (DMA) +#define G76PL 1 // DINTCH6 (DMA) +#define G77PL 0 // reserved +#define G78PL 0 // reserved + +#define G81PL 1 // I2CINT1A (I2C-A) +#define G82PL 2 // I2CINT2A (I2C-A) +#define G83PL 0 // reserved +#define G84PL 0 // reserved +#define G85PL 4 // SCIRXINTC (SCI-C) +#define G86PL 3 // SCITXINTC (SCI-C) +#define G87PL 0 // reserved +#define G88PL 0 // reserved + +#define G91PL 1 // SCIRXINTA (SCI-A) +#define G92PL 5 // SCITXINTA (SCI-A) +#define G93PL 3 // SCIRXINTB (SCI-B) +#define G94PL 4 // SCITXINTB (SCI-B) +#define G95PL 1 // ECAN0INTA (ECAN-A) +#define G96PL 1 // ECAN1INTA (ECAN-A) +#define G97PL 2 // ECAN0INTB (ECAN-B) +#define G98PL 4 // ECAN1INTB (ECAN-B) + +#define G101PL 0 // reserved +#define G102PL 0 // reserved +#define G103PL 0 // reserved +#define G104PL 0 // reserved +#define G105PL 0 // reserved +#define G106PL 0 // reserved +#define G107PL 0 // reserved +#define G108PL 0 // reserved + +#define G111PL 0 // reserved +#define G112PL 0 // reserved +#define G113PL 0 // reserved +#define G114PL 0 // reserved +#define G115PL 0 // reserved +#define G116PL 0 // reserved +#define G117PL 0 // reserved +#define G118PL 0 // reserved + +#define G121PL 5 // XINT3 (External) +#define G122PL 3 // XINT4 (External) +#define G123PL 2 // XINT5 (External) +#define G124PL 2 // XINT6 (External) +#define G125PL 1 // XINT7 (External) +#define G126PL 0 // reserved +#define G127PL 6 // LVF (FPA32) +#define G128PL 1 // LUF (FPA32) + + +// There should be no need to modify code below this line +//------------------------------------------------------------------------------- +// Automatically generate IER interrupt masks MINT1 to MINT16: +// + +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#define MINT13_12PL ~(1 << 11) + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG11 to MG18: + +// Beginning of MG11: +#if (G12PL >= G11PL) || (G12PL == 0) +#define MG11_12PL ~(1 << 1) +#else +#define MG11_12PL 0xFFFF +#endif + +#if (G13PL >= G11PL) || (G13PL == 0) +#define MG11_13PL ~(1 << 2) +#else +#define MG11_13PL 0xFFFF +#endif + +#if (G14PL >= G11PL) || (G14PL == 0) +#define MG11_14PL ~(1 << 3) +#else +#define MG11_14PL 0xFFFF +#endif + +#if (G15PL >= G11PL) || (G15PL == 0) +#define MG11_15PL ~(1 << 4) +#else +#define MG11_15PL 0xFFFF +#endif + +#if (G16PL >= G11PL) || (G16PL == 0) +#define MG11_16PL ~(1 << 5) +#else +#define MG11_16PL 0xFFFF +#endif + +#if (G17PL >= G11PL) || (G17PL == 0) +#define MG11_17PL ~(1 << 6) +#else +#define MG11_17PL 0xFFFF +#endif + +#if (G18PL >= G11PL) || (G18PL == 0) +#define MG11_18PL ~(1 << 7) +#else +#define MG11_18PL 0xFFFF +#endif + +#define MG11_11PL 0x00FE +#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \ + MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL) +// End of MG11: + +// Beginning of MG12: +#if (G11PL >= G12PL) || (G11PL == 0) +#define MG12_11PL ~(1) +#else +#define MG12_11PL 0xFFFF +#endif +#if (G13PL >= G12PL) || (G13PL == 0) +#define MG12_13PL ~(1 << 2) +#else +#define MG12_13PL 0xFFFF +#endif +#if (G14PL >= G12PL) || (G14PL == 0) +#define MG12_14PL ~(1 << 3) +#else +#define MG12_14PL 0xFFFF +#endif +#if (G15PL >= G12PL) || (G15PL == 0) +#define MG12_15PL ~(1 << 4) +#else +#define MG12_15PL 0xFFFF +#endif +#if (G16PL >= G12PL) || (G16PL == 0) +#define MG12_16PL ~(1 << 5) +#else +#define MG12_16PL 0xFFFF +#endif +#if (G17PL >= G12PL) || (G17PL == 0) +#define MG12_17PL ~(1 << 6) +#else +#define MG12_17PL 0xFFFF +#endif +#if (G18PL >= G12PL) || (G18PL == 0) +#define MG12_18PL ~(1 << 7) +#else +#define MG12_18PL 0xFFFF +#endif +#define MG12_12PL 0x00FD +#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \ + MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL) +// End of MG12: + +// Beginning of MG13: +#if (G11PL >= G13PL) || (G11PL == 0) +#define MG13_11PL ~(1) +#else +#define MG13_11PL 0xFFFF +#endif +#if (G12PL >= G13PL) || (G12PL == 0) +#define MG13_12PL ~(1 << 1) +#else +#define MG13_12PL 0xFFFF +#endif +#if (G14PL >= G13PL) || (G14PL == 0) +#define MG13_14PL ~(1 << 3) +#else +#define MG13_14PL 0xFFFF +#endif +#if (G15PL >= G13PL) || (G15PL == 0) +#define MG13_15PL ~(1 << 4) +#else +#define MG13_15PL 0xFFFF +#endif +#if (G16PL >= G13PL) || (G16PL == 0) +#define MG13_16PL ~(1 << 5) +#else +#define MG13_16PL 0xFFFF +#endif +#if (G17PL >= G13PL) || (G17PL == 0) +#define MG13_17PL ~(1 << 6) +#else +#define MG13_17PL 0xFFFF +#endif +#if (G18PL >= G13PL) || (G18PL == 0) +#define MG13_18PL ~(1 << 7) +#else +#define MG13_18PL 0xFFFF +#endif +#define MG13_13PL 0x00FB +#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \ + MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL) +// End of MG13: + +// Beginning of MG14: +#if (G11PL >= G14PL) || (G11PL == 0) +#define MG14_11PL ~(1) +#else +#define MG14_11PL 0xFFFF +#endif +#if (G12PL >= G14PL) || (G12PL == 0) +#define MG14_12PL ~(1 << 1) +#else +#define MG14_12PL 0xFFFF +#endif +#if (G13PL >= G14PL) || (G13PL == 0) +#define MG14_13PL ~(1 << 2) +#else +#define MG14_13PL 0xFFFF +#endif +#if (G15PL >= G14PL) || (G15PL == 0) +#define MG14_15PL ~(1 << 4) +#else +#define MG14_15PL 0xFFFF +#endif +#if (G16PL >= G14PL) || (G16PL == 0) +#define MG14_16PL ~(1 << 5) +#else +#define MG14_16PL 0xFFFF +#endif +#if (G17PL >= G14PL) || (G17PL == 0) +#define MG14_17PL ~(1 << 6) +#else +#define MG14_17PL 0xFFFF +#endif +#if (G18PL >= G14PL) || (G18PL == 0) +#define MG14_18PL ~(1 << 7) +#else +#define MG14_18PL 0xFFFF +#endif +#define MG14_14PL 0x00F7 +#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \ + MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL) +// End of MG14: + +// Beginning of MG15: +#if (G11PL >= G15PL) || (G11PL == 0) +#define MG15_11PL ~(1) +#else +#define MG15_11PL 0xFFFF +#endif +#if (G12PL >= G15PL) || (G12PL == 0) +#define MG15_12PL ~(1 << 1) +#else +#define MG15_12PL 0xFFFF +#endif +#if (G13PL >= G15PL) || (G13PL == 0) +#define MG15_13PL ~(1 << 2) +#else +#define MG15_13PL 0xFFFF +#endif +#if (G14PL >= G15PL) || (G14PL == 0) +#define MG15_14PL ~(1 << 3) +#else +#define MG15_14PL 0xFFFF +#endif +#if (G16PL >= G15PL) || (G16PL == 0) +#define MG15_16PL ~(1 << 5) +#else +#define MG15_16PL 0xFFFF +#endif +#if (G17PL >= G15PL) || (G17PL == 0) +#define MG15_17PL ~(1 << 6) +#else +#define MG15_17PL 0xFFFF +#endif +#if (G18PL >= G15PL) || (G18PL == 0) +#define MG15_18PL ~(1 << 7) +#else +#define MG15_18PL 0xFFFF +#endif +#define MG15_15PL 0x00EF +#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \ + MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL) +// End of MG15: + +// Beginning of MG16: +#if (G11PL >= G16PL) || (G11PL == 0) +#define MG16_11PL ~(1) +#else +#define MG16_11PL 0xFFFF +#endif +#if (G12PL >= G16PL) || (G12PL == 0) +#define MG16_12PL ~(1 << 1) +#else +#define MG16_12PL 0xFFFF +#endif +#if (G13PL >= G16PL) || (G13PL == 0) +#define MG16_13PL ~(1 << 2) +#else +#define MG16_13PL 0xFFFF +#endif +#if (G14PL >= G16PL) || (G14PL == 0) +#define MG16_14PL ~(1 << 3) +#else +#define MG16_14PL 0xFFFF +#endif +#if (G15PL >= G16PL) || (G15PL == 0) +#define MG16_15PL ~(1 << 4) +#else +#define MG16_15PL 0xFFFF +#endif +#if (G17PL >= G16PL) || (G17PL == 0) +#define MG16_17PL ~(1 << 6) +#else +#define MG16_17PL 0xFFFF +#endif +#if (G18PL >= G16PL) || (G18PL == 0) +#define MG16_18PL ~(1 << 7) +#else +#define MG16_18PL 0xFFFF +#endif +#define MG16_16PL 0x00DF +#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \ + MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL) +// End of MG16: + +// Beginning of MG17: +#if (G11PL >= G17PL) || (G11PL == 0) +#define MG17_11PL ~(1) +#else +#define MG17_11PL 0xFFFF +#endif +#if (G12PL >= G17PL) || (G12PL == 0) +#define MG17_12PL ~(1 << 1) +#else +#define MG17_12PL 0xFFFF +#endif +#if (G13PL >= G17PL) || (G13PL == 0) +#define MG17_13PL ~(1 << 2) +#else +#define MG17_13PL 0xFFFF +#endif +#if (G14PL >= G17PL) || (G14PL == 0) +#define MG17_14PL ~(1 << 3) +#else +#define MG17_14PL 0xFFFF +#endif +#if (G15PL >= G17PL) || (G15PL == 0) +#define MG17_15PL ~(1 << 4) +#else +#define MG17_15PL 0xFFFF +#endif +#if (G16PL >= G17PL) || (G16PL == 0) +#define MG17_16PL ~(1 << 5) +#else +#define MG17_16PL 0xFFFF +#endif +#if (G18PL >= G17PL) || (G18PL == 0) +#define MG17_18PL ~(1 << 7) +#else +#define MG17_18PL 0xFFFF +#endif +#define MG17_17PL 0x00BF +#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \ + MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL) +// End of MG17: + +// Beginning of MG18: +#if (G11PL >= G18PL) || (G11PL == 0) +#define MG18_11PL ~(1) +#else +#define MG18_11PL 0xFFFF +#endif +#if (G12PL >= G18PL) || (G12PL == 0) +#define MG18_12PL ~(1 << 1) +#else +#define MG18_12PL 0xFFFF +#endif +#if (G13PL >= G18PL) || (G13PL == 0) +#define MG18_13PL ~(1 << 2) +#else +#define MG18_13PL 0xFFFF +#endif +#if (G14PL >= G18PL) || (G14PL == 0) +#define MG18_14PL ~(1 << 3) +#else +#define MG18_14PL 0xFFFF +#endif +#if (G15PL >= G18PL) || (G15PL == 0) +#define MG18_15PL ~(1 << 4) +#else +#define MG18_15PL 0xFFFF +#endif +#if (G16PL >= G18PL) || (G16PL == 0) +#define MG18_16PL ~(1 << 5) +#else +#define MG18_16PL 0xFFFF +#endif +#if (G17PL >= G18PL) || (G17PL == 0) +#define MG18_17PL ~(1 << 6) +#else +#define MG18_17PL 0xFFFF +#endif +#define MG18_18PL 0x007F +#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \ + MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL) +// End of MG18: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG21 to MG28: +// + +// Beginning of MG21: +#if (G22PL >= G21PL) || (G22PL == 0) +#define MG21_12PL ~(1 << 1) +#else +#define MG21_12PL 0xFFFF +#endif +#if (G23PL >= G21PL) || (G23PL == 0) +#define MG21_13PL ~(1 << 2) +#else +#define MG21_13PL 0xFFFF +#endif +#if (G24PL >= G21PL) || (G24PL == 0) +#define MG21_14PL ~(1 << 3) +#else +#define MG21_14PL 0xFFFF +#endif +#if (G25PL >= G21PL) || (G25PL == 0) +#define MG21_15PL ~(1 << 4) +#else +#define MG21_15PL 0xFFFF +#endif +#if (G26PL >= G21PL) || (G26PL == 0) +#define MG21_16PL ~(1 << 5) +#else +#define MG21_16PL 0xFFFF +#endif +#if (G27PL >= G21PL) || (G27PL == 0) +#define MG21_17PL ~(1 << 6) +#else +#define MG21_17PL 0xFFFF +#endif +#if (G28PL >= G21PL) || (G28PL == 0) +#define MG21_18PL ~(1 << 7) +#else +#define MG21_18PL 0xFFFF +#endif +#define MG21_11PL 0x00FE +#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \ + MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL) +// End of MG21: + +// Beginning of MG22: +#if (G21PL >= G22PL) || (G21PL == 0) +#define MG22_11PL ~(1) +#else +#define MG22_11PL 0xFFFF +#endif +#if (G23PL >= G22PL) || (G23PL == 0) +#define MG22_13PL ~(1 << 2) +#else +#define MG22_13PL 0xFFFF +#endif +#if (G24PL >= G22PL) || (G24PL == 0) +#define MG22_14PL ~(1 << 3) +#else +#define MG22_14PL 0xFFFF +#endif +#if (G25PL >= G22PL) || (G25PL == 0) +#define MG22_15PL ~(1 << 4) +#else +#define MG22_15PL 0xFFFF +#endif +#if (G26PL >= G22PL) || (G26PL == 0) +#define MG22_16PL ~(1 << 5) +#else +#define MG22_16PL 0xFFFF +#endif +#if (G27PL >= G22PL) || (G27PL == 0) +#define MG22_17PL ~(1 << 6) +#else +#define MG22_17PL 0xFFFF +#endif +#if (G28PL >= G22PL) || (G28PL == 0) +#define MG22_18PL ~(1 << 7) +#else +#define MG22_18PL 0xFFFF +#endif +#define MG22_12PL 0x00FD +#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \ + MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL) +// End of MG22: + +// Beginning of MG23: +#if (G21PL >= G23PL) || (G21PL == 0) +#define MG23_11PL ~(1) +#else +#define MG23_11PL 0xFFFF +#endif +#if (G22PL >= G23PL) || (G22PL == 0) +#define MG23_12PL ~(1 << 1) +#else +#define MG23_12PL 0xFFFF +#endif +#if (G24PL >= G23PL) || (G24PL == 0) +#define MG23_14PL ~(1 << 3) +#else +#define MG23_14PL 0xFFFF +#endif +#if (G25PL >= G23PL) || (G25PL == 0) +#define MG23_15PL ~(1 << 4) +#else +#define MG23_15PL 0xFFFF +#endif +#if (G26PL >= G23PL) || (G26PL == 0) +#define MG23_16PL ~(1 << 5) +#else +#define MG23_16PL 0xFFFF +#endif +#if (G27PL >= G23PL) || (G27PL == 0) +#define MG23_17PL ~(1 << 6) +#else +#define MG23_17PL 0xFFFF +#endif +#if (G28PL >= G23PL) || (G28PL == 0) +#define MG23_18PL ~(1 << 7) +#else +#define MG23_18PL 0xFFFF +#endif +#define MG23_13PL 0x00FB +#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \ + MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL) +// End of MG23: + +// Beginning of MG24: +#if (G21PL >= G24PL) || (G21PL == 0) +#define MG24_11PL ~(1) +#else +#define MG24_11PL 0xFFFF +#endif +#if (G22PL >= G24PL) || (G22PL == 0) +#define MG24_12PL ~(1 << 1) +#else +#define MG24_12PL 0xFFFF +#endif +#if (G23PL >= G24PL) || (G23PL == 0) +#define MG24_13PL ~(1 << 2) +#else +#define MG24_13PL 0xFFFF +#endif +#if (G25PL >= G24PL) || (G25PL == 0) +#define MG24_15PL ~(1 << 4) +#else +#define MG24_15PL 0xFFFF +#endif +#if (G26PL >= G24PL) || (G26PL == 0) +#define MG24_16PL ~(1 << 5) +#else +#define MG24_16PL 0xFFFF +#endif +#if (G27PL >= G24PL) || (G27PL == 0) +#define MG24_17PL ~(1 << 6) +#else +#define MG24_17PL 0xFFFF +#endif +#if (G28PL >= G24PL) || (G28PL == 0) +#define MG24_18PL ~(1 << 7) +#else +#define MG24_18PL 0xFFFF +#endif +#define MG24_14PL 0x00F7 +#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \ + MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL) +// End of MG24: + +// Beginning of MG25: +#if (G21PL >= G25PL) || (G21PL == 0) +#define MG25_11PL ~(1) +#else +#define MG25_11PL 0xFFFF +#endif +#if (G22PL >= G25PL) || (G22PL == 0) +#define MG25_12PL ~(1 << 1) +#else +#define MG25_12PL 0xFFFF +#endif +#if (G23PL >= G25PL) || (G23PL == 0) +#define MG25_13PL ~(1 << 2) +#else +#define MG25_13PL 0xFFFF +#endif +#if (G24PL >= G25PL) || (G24PL == 0) +#define MG25_14PL ~(1 << 3) +#else +#define MG25_14PL 0xFFFF +#endif +#if (G26PL >= G25PL) || (G26PL == 0) +#define MG25_16PL ~(1 << 5) +#else +#define MG25_16PL 0xFFFF +#endif +#if (G27PL >= G25PL) || (G27PL == 0) +#define MG25_17PL ~(1 << 6) +#else +#define MG25_17PL 0xFFFF +#endif +#if (G28PL >= G25PL) || (G28PL == 0) +#define MG25_18PL ~(1 << 7) +#else +#define MG25_18PL 0xFFFF +#endif +#define MG25_15PL 0x00EF +#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \ + MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL) +// End of MG25: + +// Beginning of MG26: +#if (G21PL >= G26PL) || (G21PL == 0) +#define MG26_11PL ~(1) +#else +#define MG26_11PL 0xFFFF +#endif +#if (G22PL >= G26PL) || (G22PL == 0) +#define MG26_12PL ~(1 << 1) +#else +#define MG26_12PL 0xFFFF +#endif +#if (G23PL >= G26PL) || (G23PL == 0) +#define MG26_13PL ~(1 << 2) +#else +#define MG26_13PL 0xFFFF +#endif +#if (G24PL >= G26PL) || (G24PL == 0) +#define MG26_14PL ~(1 << 3) +#else +#define MG26_14PL 0xFFFF +#endif +#if (G25PL >= G26PL) || (G25PL == 0) +#define MG26_15PL ~(1 << 4) +#else +#define MG26_15PL 0xFFFF +#endif +#if (G27PL >= G26PL) || (G27PL == 0) +#define MG26_17PL ~(1 << 6) +#else +#define MG26_17PL 0xFFFF +#endif +#if (G28PL >= G26PL) || (G28PL == 0) +#define MG26_18PL ~(1 << 7) +#else +#define MG26_18PL 0xFFFF +#endif +#define MG26_16PL 0x00DF +#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \ + MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL) +// End of MG26: + +// Beginning of MG27: +#if (G21PL >= G27PL) || (G21PL == 0) +#define MG27_11PL ~(1) +#else +#define MG27_11PL 0xFFFF +#endif +#if (G22PL >= G27PL) || (G22PL == 0) +#define MG27_12PL ~(1 << 1) +#else +#define MG27_12PL 0xFFFF +#endif +#if (G23PL >= G27PL) || (G23PL == 0) +#define MG27_13PL ~(1 << 2) +#else +#define MG27_13PL 0xFFFF +#endif +#if (G24PL >= G27PL) || (G24PL == 0) +#define MG27_14PL ~(1 << 3) +#else +#define MG27_14PL 0xFFFF +#endif +#if (G25PL >= G27PL) || (G25PL == 0) +#define MG27_15PL ~(1 << 4) +#else +#define MG27_15PL 0xFFFF +#endif +#if (G26PL >= G27PL) || (G26PL == 0) +#define MG27_16PL ~(1 << 5) +#else +#define MG27_16PL 0xFFFF +#endif +#if (G28PL >= G27PL) || (G28PL == 0) +#define MG27_18PL ~(1 << 7) +#else +#define MG27_18PL 0xFFFF +#endif +#define MG27_17PL 0x00BF +#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \ + MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL) +// End of MG27: + +// Beginning of MG28: +#if (G21PL >= G28PL) || (G21PL == 0) +#define MG28_11PL ~(1) +#else +#define MG28_11PL 0xFFFF +#endif +#if (G22PL >= G28PL) || (G22PL == 0) +#define MG28_12PL ~(1 << 1) +#else +#define MG28_12PL 0xFFFF +#endif +#if (G23PL >= G28PL) || (G23PL == 0) +#define MG28_13PL ~(1 << 2) +#else +#define MG28_13PL 0xFFFF +#endif +#if (G24PL >= G28PL) || (G24PL == 0) +#define MG28_14PL ~(1 << 3) +#else +#define MG28_14PL 0xFFFF +#endif +#if (G25PL >= G28PL) || (G25PL == 0) +#define MG28_15PL ~(1 << 4) +#else +#define MG28_15PL 0xFFFF +#endif +#if (G26PL >= G28PL) || (G26PL == 0) +#define MG28_16PL ~(1 << 5) +#else +#define MG28_16PL 0xFFFF +#endif +#if (G27PL >= G28PL) || (G27PL == 0) +#define MG28_17PL ~(1 << 6) +#else +#define MG28_17PL 0xFFFF +#endif +#define MG28_18PL 0x007F +#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \ + MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL) +// End of MG28: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG31 to MG38: +// + +// Beginning of MG31: +#if (G32PL >= G31PL) || (G32PL == 0) +#define MG31_12PL ~(1 << 1) +#else +#define MG31_12PL 0xFFFF +#endif +#if (G33PL >= G31PL) || (G33PL == 0) +#define MG31_13PL ~(1 << 2) +#else +#define MG31_13PL 0xFFFF +#endif +#if (G34PL >= G31PL) || (G34PL == 0) +#define MG31_14PL ~(1 << 3) +#else +#define MG31_14PL 0xFFFF +#endif +#if (G35PL >= G31PL) || (G35PL == 0) +#define MG31_15PL ~(1 << 4) +#else +#define MG31_15PL 0xFFFF +#endif +#if (G36PL >= G31PL) || (G36PL == 0) +#define MG31_16PL ~(1 << 5) +#else +#define MG31_16PL 0xFFFF +#endif +#if (G37PL >= G31PL) || (G37PL == 0) +#define MG31_17PL ~(1 << 6) +#else +#define MG31_17PL 0xFFFF +#endif +#if (G38PL >= G31PL) || (G38PL == 0) +#define MG31_18PL ~(1 << 7) +#else +#define MG31_18PL 0xFFFF +#endif +#define MG31_11PL 0x00FE +#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \ + MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL) +// End of MG31: + +// Beginning of MG32: +#if (G31PL >= G32PL) || (G31PL == 0) +#define MG32_11PL ~(1) +#else +#define MG32_11PL 0xFFFF +#endif +#if (G33PL >= G32PL) || (G33PL == 0) +#define MG32_13PL ~(1 << 2) +#else +#define MG32_13PL 0xFFFF +#endif +#if (G34PL >= G32PL) || (G34PL == 0) +#define MG32_14PL ~(1 << 3) +#else +#define MG32_14PL 0xFFFF +#endif +#if (G35PL >= G32PL) || (G35PL == 0) +#define MG32_15PL ~(1 << 4) +#else +#define MG32_15PL 0xFFFF +#endif +#if (G36PL >= G32PL) || (G36PL == 0) +#define MG32_16PL ~(1 << 5) +#else +#define MG32_16PL 0xFFFF +#endif +#if (G37PL >= G32PL) || (G37PL == 0) +#define MG32_17PL ~(1 << 6) +#else +#define MG32_17PL 0xFFFF +#endif +#if (G38PL >= G32PL) || (G38PL == 0) +#define MG32_18PL ~(1 << 7) +#else +#define MG32_18PL 0xFFFF +#endif +#define MG32_12PL 0x00FD +#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \ + MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL) +// End of MG32: + +// Beginning of MG33: +#if (G31PL >= G33PL) || (G31PL == 0) +#define MG33_11PL ~(1) +#else +#define MG33_11PL 0xFFFF +#endif +#if (G32PL >= G33PL) || (G32PL == 0) +#define MG33_12PL ~(1 << 1) +#else +#define MG33_12PL 0xFFFF +#endif +#if (G34PL >= G33PL) || (G34PL == 0) +#define MG33_14PL ~(1 << 3) +#else +#define MG33_14PL 0xFFFF +#endif +#if (G35PL >= G33PL) || (G35PL == 0) +#define MG33_15PL ~(1 << 4) +#else +#define MG33_15PL 0xFFFF +#endif +#if (G36PL >= G33PL) || (G36PL == 0) +#define MG33_16PL ~(1 << 5) +#else +#define MG33_16PL 0xFFFF +#endif +#if (G37PL >= G33PL) || (G37PL == 0) +#define MG33_17PL ~(1 << 6) +#else +#define MG33_17PL 0xFFFF +#endif +#if (G38PL >= G33PL) || (G38PL == 0) +#define MG33_18PL ~(1 << 7) +#else +#define MG33_18PL 0xFFFF +#endif +#define MG33_13PL 0x00FB +#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \ + MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL) +// End of MG33: + +// Beginning of MG34: +#if (G31PL >= G34PL) || (G31PL == 0) +#define MG34_11PL ~(1) +#else +#define MG34_11PL 0xFFFF +#endif +#if (G32PL >= G34PL) || (G32PL == 0) +#define MG34_12PL ~(1 << 1) +#else +#define MG34_12PL 0xFFFF +#endif +#if (G33PL >= G34PL) || (G33PL == 0) +#define MG34_13PL ~(1 << 2) +#else +#define MG34_13PL 0xFFFF +#endif +#if (G35PL >= G34PL) || (G35PL == 0) +#define MG34_15PL ~(1 << 4) +#else +#define MG34_15PL 0xFFFF +#endif +#if (G36PL >= G34PL) || (G36PL == 0) +#define MG34_16PL ~(1 << 5) +#else +#define MG34_16PL 0xFFFF +#endif +#if (G37PL >= G34PL) || (G37PL == 0) +#define MG34_17PL ~(1 << 6) +#else +#define MG34_17PL 0xFFFF +#endif +#if (G38PL >= G34PL) || (G38PL == 0) +#define MG34_18PL ~(1 << 7) +#else +#define MG34_18PL 0xFFFF +#endif +#define MG34_14PL 0x00F7 +#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \ + MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL) +// End of MG34: + +// Beginning of MG35: +#if (G31PL >= G35PL) || (G31PL == 0) +#define MG35_11PL ~(1) +#else +#define MG35_11PL 0xFFFF +#endif +#if (G32PL >= G35PL) || (G32PL == 0) +#define MG35_12PL ~(1 << 1) +#else +#define MG35_12PL 0xFFFF +#endif +#if (G33PL >= G35PL) || (G33PL == 0) +#define MG35_13PL ~(1 << 2) +#else +#define MG35_13PL 0xFFFF +#endif +#if (G34PL >= G35PL) || (G34PL == 0) +#define MG35_14PL ~(1 << 3) +#else +#define MG35_14PL 0xFFFF +#endif +#if (G36PL >= G35PL) || (G36PL == 0) +#define MG35_16PL ~(1 << 5) +#else +#define MG35_16PL 0xFFFF +#endif +#if (G37PL >= G35PL) || (G37PL == 0) +#define MG35_17PL ~(1 << 6) +#else +#define MG35_17PL 0xFFFF +#endif +#if (G38PL >= G35PL) || (G38PL == 0) +#define MG35_18PL ~(1 << 7) +#else +#define MG35_18PL 0xFFFF +#endif +#define MG35_15PL 0x00EF +#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \ + MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL) +// End of MG35: + +// Beginning of MG36: +#if (G31PL >= G36PL) || (G31PL == 0) +#define MG36_11PL ~(1) +#else +#define MG36_11PL 0xFFFF +#endif +#if (G32PL >= G36PL) || (G32PL == 0) +#define MG36_12PL ~(1 << 1) +#else +#define MG36_12PL 0xFFFF +#endif +#if (G33PL >= G36PL) || (G33PL == 0) +#define MG36_13PL ~(1 << 2) +#else +#define MG36_13PL 0xFFFF +#endif +#if (G34PL >= G36PL) || (G34PL == 0) +#define MG36_14PL ~(1 << 3) +#else +#define MG36_14PL 0xFFFF +#endif +#if (G35PL >= G36PL) || (G35PL == 0) +#define MG36_15PL ~(1 << 4) +#else +#define MG36_15PL 0xFFFF +#endif +#if (G37PL >= G36PL) || (G37PL == 0) +#define MG36_17PL ~(1 << 6) +#else +#define MG36_17PL 0xFFFF +#endif +#if (G38PL >= G36PL) || (G38PL == 0) +#define MG36_18PL ~(1 << 7) +#else +#define MG36_18PL 0xFFFF +#endif +#define MG36_16PL 0x00DF +#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \ + MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL) +// End of MG36: + +// Beginning of MG37: +#if (G31PL >= G37PL) || (G31PL == 0) +#define MG37_11PL ~(1) +#else +#define MG37_11PL 0xFFFF +#endif +#if (G32PL >= G37PL) || (G32PL == 0) +#define MG37_12PL ~(1 << 1) +#else +#define MG37_12PL 0xFFFF +#endif +#if (G33PL >= G37PL) || (G33PL == 0) +#define MG37_13PL ~(1 << 2) +#else +#define MG37_13PL 0xFFFF +#endif +#if (G34PL >= G37PL) || (G34PL == 0) +#define MG37_14PL ~(1 << 3) +#else +#define MG37_14PL 0xFFFF +#endif +#if (G35PL >= G37PL) || (G35PL == 0) +#define MG37_15PL ~(1 << 4) +#else +#define MG37_15PL 0xFFFF +#endif +#if (G36PL >= G37PL) || (G36PL == 0) +#define MG37_16PL ~(1 << 5) +#else +#define MG37_16PL 0xFFFF +#endif +#if (G38PL >= G37PL) || (G38PL == 0) +#define MG37_18PL ~(1 << 7) +#else +#define MG37_18PL 0xFFFF +#endif +#define MG37_17PL 0x00BF +#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \ + MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL) +// End of MG37: + +// Beginning of MG38: +#if (G31PL >= G38PL) || (G31PL == 0) +#define MG38_11PL ~(1) +#else +#define MG38_11PL 0xFFFF +#endif +#if (G32PL >= G38PL) || (G32PL == 0) +#define MG38_12PL ~(1 << 1) +#else +#define MG38_12PL 0xFFFF +#endif +#if (G33PL >= G38PL) || (G33PL == 0) +#define MG38_13PL ~(1 << 2) +#else +#define MG38_13PL 0xFFFF +#endif +#if (G34PL >= G38PL) || (G34PL == 0) +#define MG38_14PL ~(1 << 3) +#else +#define MG38_14PL 0xFFFF +#endif +#if (G35PL >= G38PL) || (G35PL == 0) +#define MG38_15PL ~(1 << 4) +#else +#define MG38_15PL 0xFFFF +#endif +#if (G36PL >= G38PL) || (G36PL == 0) +#define MG38_16PL ~(1 << 5) +#else +#define MG38_16PL 0xFFFF +#endif +#if (G37PL >= G38PL) || (G37PL == 0) +#define MG38_17PL ~(1 << 6) +#else +#define MG38_17PL 0xFFFF +#endif +#define MG38_18PL 0x007F +#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \ + MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL) +// End of MG38: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG41 to MG48: +// + +// Beginning of MG41: +#if (G42PL >= G41PL) || (G42PL == 0) +#define MG41_12PL ~(1 << 1) +#else +#define MG41_12PL 0xFFFF +#endif +#if (G43PL >= G41PL) || (G43PL == 0) +#define MG41_13PL ~(1 << 2) +#else +#define MG41_13PL 0xFFFF +#endif +#if (G44PL >= G41PL) || (G44PL == 0) +#define MG41_14PL ~(1 << 3) +#else +#define MG41_14PL 0xFFFF +#endif +#if (G45PL >= G41PL) || (G45PL == 0) +#define MG41_15PL ~(1 << 4) +#else +#define MG41_15PL 0xFFFF +#endif +#if (G46PL >= G41PL) || (G46PL == 0) +#define MG41_16PL ~(1 << 5) +#else +#define MG41_16PL 0xFFFF +#endif +#if (G47PL >= G41PL) || (G47PL == 0) +#define MG41_17PL ~(1 << 6) +#else +#define MG41_17PL 0xFFFF +#endif +#if (G48PL >= G41PL) || (G48PL == 0) +#define MG41_18PL ~(1 << 7) +#else +#define MG41_18PL 0xFFFF +#endif +#define MG41_11PL 0x00FE +#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \ + MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL) +// End of MG41: + +// Beginning of MG42: +#if (G41PL >= G42PL) || (G41PL == 0) +#define MG42_11PL ~(1) +#else +#define MG42_11PL 0xFFFF +#endif +#if (G43PL >= G42PL) || (G43PL == 0) +#define MG42_13PL ~(1 << 2) +#else +#define MG42_13PL 0xFFFF +#endif +#if (G44PL >= G42PL) || (G44PL == 0) +#define MG42_14PL ~(1 << 3) +#else +#define MG42_14PL 0xFFFF +#endif +#if (G45PL >= G42PL) || (G45PL == 0) +#define MG42_15PL ~(1 << 4) +#else +#define MG42_15PL 0xFFFF +#endif +#if (G46PL >= G42PL) || (G46PL == 0) +#define MG42_16PL ~(1 << 5) +#else +#define MG42_16PL 0xFFFF +#endif +#if (G47PL >= G42PL) || (G47PL == 0) +#define MG42_17PL ~(1 << 6) +#else +#define MG42_17PL 0xFFFF +#endif +#if (G48PL >= G42PL) || (G48PL == 0) +#define MG42_18PL ~(1 << 7) +#else +#define MG42_18PL 0xFFFF +#endif +#define MG42_12PL 0x00FD +#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \ + MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL) +// End of MG42: + +// Beginning of MG43: +#if (G41PL >= G43PL) || (G41PL == 0) +#define MG43_11PL ~(1) +#else +#define MG43_11PL 0xFFFF +#endif +#if (G42PL >= G43PL) || (G42PL == 0) +#define MG43_12PL ~(1 << 1) +#else +#define MG43_12PL 0xFFFF +#endif +#if (G44PL >= G43PL) || (G44PL == 0) +#define MG43_14PL ~(1 << 3) +#else +#define MG43_14PL 0xFFFF +#endif +#if (G45PL >= G43PL) || (G45PL == 0) +#define MG43_15PL ~(1 << 4) +#else +#define MG43_15PL 0xFFFF +#endif +#if (G46PL >= G43PL) || (G46PL == 0) +#define MG43_16PL ~(1 << 5) +#else +#define MG43_16PL 0xFFFF +#endif +#if (G47PL >= G43PL) || (G47PL == 0) +#define MG43_17PL ~(1 << 6) +#else +#define MG43_17PL 0xFFFF +#endif +#if (G48PL >= G43PL) || (G48PL == 0) +#define MG43_18PL ~(1 << 7) +#else +#define MG43_18PL 0xFFFF +#endif +#define MG43_13PL 0x00FB +#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \ + MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL) +// End of MG43: + +// Beginning of MG44: +#if (G41PL >= G44PL) || (G41PL == 0) +#define MG44_11PL ~(1) +#else +#define MG44_11PL 0xFFFF +#endif +#if (G42PL >= G44PL) || (G42PL == 0) +#define MG44_12PL ~(1 << 1) +#else +#define MG44_12PL 0xFFFF +#endif +#if (G43PL >= G44PL) || (G43PL == 0) +#define MG44_13PL ~(1 << 2) +#else +#define MG44_13PL 0xFFFF +#endif +#if (G45PL >= G44PL) || (G45PL == 0) +#define MG44_15PL ~(1 << 4) +#else +#define MG44_15PL 0xFFFF +#endif +#if (G46PL >= G44PL) || (G46PL == 0) +#define MG44_16PL ~(1 << 5) +#else +#define MG44_16PL 0xFFFF +#endif +#if (G47PL >= G44PL) || (G47PL == 0) +#define MG44_17PL ~(1 << 6) +#else +#define MG44_17PL 0xFFFF +#endif +#if (G48PL >= G44PL) || (G48PL == 0) +#define MG44_18PL ~(1 << 7) +#else +#define MG44_18PL 0xFFFF +#endif +#define MG44_14PL 0x00F7 +#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \ + MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL) +// End of MG44: + +// Beginning of MG45: +#if (G41PL >= G45PL) || (G41PL == 0) +#define MG45_11PL ~(1) +#else +#define MG45_11PL 0xFFFF +#endif +#if (G42PL >= G45PL) || (G42PL == 0) +#define MG45_12PL ~(1 << 1) +#else +#define MG45_12PL 0xFFFF +#endif +#if (G43PL >= G45PL) || (G43PL == 0) +#define MG45_13PL ~(1 << 2) +#else +#define MG45_13PL 0xFFFF +#endif +#if (G44PL >= G45PL) || (G44PL == 0) +#define MG45_14PL ~(1 << 3) +#else +#define MG45_14PL 0xFFFF +#endif +#if (G46PL >= G45PL) || (G46PL == 0) +#define MG45_16PL ~(1 << 5) +#else +#define MG45_16PL 0xFFFF +#endif +#if (G47PL >= G45PL) || (G47PL == 0) +#define MG45_17PL ~(1 << 6) +#else +#define MG45_17PL 0xFFFF +#endif +#if (G48PL >= G45PL) || (G48PL == 0) +#define MG45_18PL ~(1 << 7) +#else +#define MG45_18PL 0xFFFF +#endif +#define MG45_15PL 0x00EF +#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \ + MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL) +// End of MG45: + +// Beginning of MG46: +#if (G41PL >= G46PL) || (G41PL == 0) +#define MG46_11PL ~(1) +#else +#define MG46_11PL 0xFFFF +#endif +#if (G42PL >= G46PL) || (G42PL == 0) +#define MG46_12PL ~(1 << 1) +#else +#define MG46_12PL 0xFFFF +#endif +#if (G43PL >= G46PL) || (G43PL == 0) +#define MG46_13PL ~(1 << 2) +#else +#define MG46_13PL 0xFFFF +#endif +#if (G44PL >= G46PL) || (G44PL == 0) +#define MG46_14PL ~(1 << 3) +#else +#define MG46_14PL 0xFFFF +#endif +#if (G45PL >= G46PL) || (G45PL == 0) +#define MG46_15PL ~(1 << 4) +#else +#define MG46_15PL 0xFFFF +#endif +#if (G47PL >= G46PL) || (G47PL == 0) +#define MG46_17PL ~(1 << 6) +#else +#define MG46_17PL 0xFFFF +#endif +#if (G48PL >= G46PL) || (G48PL == 0) +#define MG46_18PL ~(1 << 7) +#else +#define MG46_18PL 0xFFFF +#endif +#define MG46_16PL 0x00DF +#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \ + MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL) +// End of MG46: + +// Beginning of MG47: +#if (G41PL >= G47PL) || (G41PL == 0) +#define MG47_11PL ~(1) +#else +#define MG47_11PL 0xFFFF +#endif +#if (G42PL >= G47PL) || (G42PL == 0) +#define MG47_12PL ~(1 << 1) +#else +#define MG47_12PL 0xFFFF +#endif +#if (G43PL >= G47PL) || (G43PL == 0) +#define MG47_13PL ~(1 << 2) +#else +#define MG47_13PL 0xFFFF +#endif +#if (G44PL >= G47PL) || (G44PL == 0) +#define MG47_14PL ~(1 << 3) +#else +#define MG47_14PL 0xFFFF +#endif +#if (G45PL >= G47PL) || (G45PL == 0) +#define MG47_15PL ~(1 << 4) +#else +#define MG47_15PL 0xFFFF +#endif +#if (G46PL >= G47PL) || (G46PL == 0) +#define MG47_16PL ~(1 << 5) +#else +#define MG47_16PL 0xFFFF +#endif +#if (G48PL >= G47PL) || (G48PL == 0) +#define MG47_18PL ~(1 << 7) +#else +#define MG47_18PL 0xFFFF +#endif +#define MG47_17PL 0x00BF +#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \ + MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL) +// End of MG47: + +// Beginning of MG48: +#if (G41PL >= G48PL) || (G41PL == 0) +#define MG48_11PL ~(1) +#else +#define MG48_11PL 0xFFFF +#endif +#if (G42PL >= G48PL) || (G42PL == 0) +#define MG48_12PL ~(1 << 1) +#else +#define MG48_12PL 0xFFFF +#endif +#if (G43PL >= G48PL) || (G43PL == 0) +#define MG48_13PL ~(1 << 2) +#else +#define MG48_13PL 0xFFFF +#endif +#if (G44PL >= G48PL) || (G44PL == 0) +#define MG48_14PL ~(1 << 3) +#else +#define MG48_14PL 0xFFFF +#endif +#if (G45PL >= G48PL) || (G45PL == 0) +#define MG48_15PL ~(1 << 4) +#else +#define MG48_15PL 0xFFFF +#endif +#if (G46PL >= G48PL) || (G46PL == 0) +#define MG48_16PL ~(1 << 5) +#else +#define MG48_16PL 0xFFFF +#endif +#if (G47PL >= G48PL) || (G47PL == 0) +#define MG48_17PL ~(1 << 6) +#else +#define MG48_17PL 0xFFFF +#endif +#define MG48_18PL 0x007F +#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \ + MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL) +// End of MG48: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG51 to MG58: +// + +// Beginning of MG51: +#if (G52PL >= G51PL) || (G52PL == 0) +#define MG51_12PL ~(1 << 1) +#else +#define MG51_12PL 0xFFFF +#endif +#if (G53PL >= G51PL) || (G53PL == 0) +#define MG51_13PL ~(1 << 2) +#else +#define MG51_13PL 0xFFFF +#endif +#if (G54PL >= G51PL) || (G54PL == 0) +#define MG51_14PL ~(1 << 3) +#else +#define MG51_14PL 0xFFFF +#endif +#if (G55PL >= G51PL) || (G55PL == 0) +#define MG51_15PL ~(1 << 4) +#else +#define MG51_15PL 0xFFFF +#endif +#if (G56PL >= G51PL) || (G56PL == 0) +#define MG51_16PL ~(1 << 5) +#else +#define MG51_16PL 0xFFFF +#endif +#if (G57PL >= G51PL) || (G57PL == 0) +#define MG51_17PL ~(1 << 6) +#else +#define MG51_17PL 0xFFFF +#endif +#if (G58PL >= G51PL) || (G58PL == 0) +#define MG51_18PL ~(1 << 7) +#else +#define MG51_18PL 0xFFFF +#endif +#define MG51_11PL 0x00FE +#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \ + MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL) +// End of MG51: + +// Beginning of MG52: +#if (G51PL >= G52PL) || (G51PL == 0) +#define MG52_11PL ~(1) +#else +#define MG52_11PL 0xFFFF +#endif +#if (G53PL >= G52PL) || (G53PL == 0) +#define MG52_13PL ~(1 << 2) +#else +#define MG52_13PL 0xFFFF +#endif +#if (G54PL >= G52PL) || (G54PL == 0) +#define MG52_14PL ~(1 << 3) +#else +#define MG52_14PL 0xFFFF +#endif +#if (G55PL >= G52PL) || (G55PL == 0) +#define MG52_15PL ~(1 << 4) +#else +#define MG52_15PL 0xFFFF +#endif +#if (G56PL >= G52PL) || (G56PL == 0) +#define MG52_16PL ~(1 << 5) +#else +#define MG52_16PL 0xFFFF +#endif +#if (G57PL >= G52PL) || (G57PL == 0) +#define MG52_17PL ~(1 << 6) +#else +#define MG52_17PL 0xFFFF +#endif +#if (G58PL >= G52PL) || (G58PL == 0) +#define MG52_18PL ~(1 << 7) +#else +#define MG52_18PL 0xFFFF +#endif +#define MG52_12PL 0x00FD +#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \ + MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL) +// End of MG52: + +// Beginning of MG53: +#if (G51PL >= G53PL) || (G51PL == 0) +#define MG53_11PL ~(1) +#else +#define MG53_11PL 0xFFFF +#endif +#if (G52PL >= G53PL) || (G52PL == 0) +#define MG53_12PL ~(1 << 1) +#else +#define MG53_12PL 0xFFFF +#endif +#if (G54PL >= G53PL) || (G54PL == 0) +#define MG53_14PL ~(1 << 3) +#else +#define MG53_14PL 0xFFFF +#endif +#if (G55PL >= G53PL) || (G55PL == 0) +#define MG53_15PL ~(1 << 4) +#else +#define MG53_15PL 0xFFFF +#endif +#if (G56PL >= G53PL) || (G56PL == 0) +#define MG53_16PL ~(1 << 5) +#else +#define MG53_16PL 0xFFFF +#endif +#if (G57PL >= G53PL) || (G57PL == 0) +#define MG53_17PL ~(1 << 6) +#else +#define MG53_17PL 0xFFFF +#endif +#if (G58PL >= G53PL) || (G58PL == 0) +#define MG53_18PL ~(1 << 7) +#else +#define MG53_18PL 0xFFFF +#endif +#define MG53_13PL 0x00FB +#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \ + MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL) +// End of MG53: + +// Beginning of MG54: +#if (G51PL >= G54PL) || (G51PL == 0) +#define MG54_11PL ~(1) +#else +#define MG54_11PL 0xFFFF +#endif +#if (G52PL >= G54PL) || (G52PL == 0) +#define MG54_12PL ~(1 << 1) +#else +#define MG54_12PL 0xFFFF +#endif +#if (G53PL >= G54PL) || (G53PL == 0) +#define MG54_13PL ~(1 << 2) +#else +#define MG54_13PL 0xFFFF +#endif +#if (G55PL >= G54PL) || (G55PL == 0) +#define MG54_15PL ~(1 << 4) +#else +#define MG54_15PL 0xFFFF +#endif +#if (G56PL >= G54PL) || (G56PL == 0) +#define MG54_16PL ~(1 << 5) +#else +#define MG54_16PL 0xFFFF +#endif +#if (G57PL >= G54PL) || (G57PL == 0) +#define MG54_17PL ~(1 << 6) +#else +#define MG54_17PL 0xFFFF +#endif +#if (G58PL >= G54PL) || (G58PL == 0) +#define MG54_18PL ~(1 << 7) +#else +#define MG54_18PL 0xFFFF +#endif +#define MG54_14PL 0x00F7 +#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \ + MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL) +// End of MG54: + +// Beginning of MG55: +#if (G51PL >= G55PL) || (G51PL == 0) +#define MG55_11PL ~(1) +#else +#define MG55_11PL 0xFFFF +#endif +#if (G52PL >= G55PL) || (G52PL == 0) +#define MG55_12PL ~(1 << 1) +#else +#define MG55_12PL 0xFFFF +#endif +#if (G53PL >= G55PL) || (G53PL == 0) +#define MG55_13PL ~(1 << 2) +#else +#define MG55_13PL 0xFFFF +#endif +#if (G54PL >= G55PL) || (G54PL == 0) +#define MG55_14PL ~(1 << 3) +#else +#define MG55_14PL 0xFFFF +#endif +#if (G56PL >= G55PL) || (G56PL == 0) +#define MG55_16PL ~(1 << 5) +#else +#define MG55_16PL 0xFFFF +#endif +#if (G57PL >= G55PL) || (G57PL == 0) +#define MG55_17PL ~(1 << 6) +#else +#define MG55_17PL 0xFFFF +#endif +#if (G58PL >= G55PL) || (G58PL == 0) +#define MG55_18PL ~(1 << 7) +#else +#define MG55_18PL 0xFFFF +#endif +#define MG55_15PL 0x00EF +#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \ + MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL) +// End of MG55: + +// Beginning of MG56: +#if (G51PL >= G56PL) || (G51PL == 0) +#define MG56_11PL ~(1) +#else +#define MG56_11PL 0xFFFF +#endif +#if (G52PL >= G56PL) || (G52PL == 0) +#define MG56_12PL ~(1 << 1) +#else +#define MG56_12PL 0xFFFF +#endif +#if (G53PL >= G56PL) || (G53PL == 0) +#define MG56_13PL ~(1 << 2) +#else +#define MG56_13PL 0xFFFF +#endif +#if (G54PL >= G56PL) || (G54PL == 0) +#define MG56_14PL ~(1 << 3) +#else +#define MG56_14PL 0xFFFF +#endif +#if (G55PL >= G56PL) || (G55PL == 0) +#define MG56_15PL ~(1 << 4) +#else +#define MG56_15PL 0xFFFF +#endif +#if (G57PL >= G56PL) || (G57PL == 0) +#define MG56_17PL ~(1 << 6) +#else +#define MG56_17PL 0xFFFF +#endif +#if (G58PL >= G56PL) || (G58PL == 0) +#define MG56_18PL ~(1 << 7) +#else +#define MG56_18PL 0xFFFF +#endif +#define MG56_16PL 0x00DF +#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \ + MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL) +// End of MG56: + +// Beginning of MG57: +#if (G51PL >= G57PL) || (G51PL == 0) +#define MG57_11PL ~(1) +#else +#define MG57_11PL 0xFFFF +#endif +#if (G52PL >= G57PL) || (G52PL == 0) +#define MG57_12PL ~(1 << 1) +#else +#define MG57_12PL 0xFFFF +#endif +#if (G53PL >= G57PL) || (G53PL == 0) +#define MG57_13PL ~(1 << 2) +#else +#define MG57_13PL 0xFFFF +#endif +#if (G54PL >= G57PL) || (G54PL == 0) +#define MG57_14PL ~(1 << 3) +#else +#define MG57_14PL 0xFFFF +#endif +#if (G55PL >= G57PL) || (G55PL == 0) +#define MG57_15PL ~(1 << 4) +#else +#define MG57_15PL 0xFFFF +#endif +#if (G56PL >= G57PL) || (G56PL == 0) +#define MG57_16PL ~(1 << 5) +#else +#define MG57_16PL 0xFFFF +#endif +#if (G58PL >= G57PL) || (G58PL == 0) +#define MG57_18PL ~(1 << 7) +#else +#define MG57_18PL 0xFFFF +#endif +#define MG57_17PL 0x00BF +#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \ + MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL) +// End of MG57: + +// Beginning of MG58: +#if (G51PL >= G58PL) || (G51PL == 0) +#define MG58_11PL ~(1) +#else +#define MG58_11PL 0xFFFF +#endif +#if (G52PL >= G58PL) || (G52PL == 0) +#define MG58_12PL ~(1 << 1) +#else +#define MG58_12PL 0xFFFF +#endif +#if (G53PL >= G58PL) || (G53PL == 0) +#define MG58_13PL ~(1 << 2) +#else +#define MG58_13PL 0xFFFF +#endif +#if (G54PL >= G58PL) || (G54PL == 0) +#define MG58_14PL ~(1 << 3) +#else +#define MG58_14PL 0xFFFF +#endif +#if (G55PL >= G58PL) || (G55PL == 0) +#define MG58_15PL ~(1 << 4) +#else +#define MG58_15PL 0xFFFF +#endif +#if (G56PL >= G58PL) || (G56PL == 0) +#define MG58_16PL ~(1 << 5) +#else +#define MG58_16PL 0xFFFF +#endif +#if (G57PL >= G58PL) || (G57PL == 0) +#define MG58_17PL ~(1 << 6) +#else +#define MG58_17PL 0xFFFF +#endif +#define MG58_18PL 0x007F +#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \ + MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL) +// End of MG58: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG61 to MG68: +// + +// Beginning of MG61: +#if (G62PL >= G61PL) || (G62PL == 0) +#define MG61_12PL ~(1 << 1) +#else +#define MG61_12PL 0xFFFF +#endif +#if (G63PL >= G61PL) || (G63PL == 0) +#define MG61_13PL ~(1 << 2) +#else +#define MG61_13PL 0xFFFF +#endif +#if (G64PL >= G61PL) || (G64PL == 0) +#define MG61_14PL ~(1 << 3) +#else +#define MG61_14PL 0xFFFF +#endif +#if (G65PL >= G61PL) || (G65PL == 0) +#define MG61_15PL ~(1 << 4) +#else +#define MG61_15PL 0xFFFF +#endif +#if (G66PL >= G61PL) || (G66PL == 0) +#define MG61_16PL ~(1 << 5) +#else +#define MG61_16PL 0xFFFF +#endif +#if (G67PL >= G61PL) || (G67PL == 0) +#define MG61_17PL ~(1 << 6) +#else +#define MG61_17PL 0xFFFF +#endif +#if (G68PL >= G61PL) || (G68PL == 0) +#define MG61_18PL ~(1 << 7) +#else +#define MG61_18PL 0xFFFF +#endif +#define MG61_11PL 0x00FE +#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \ + MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL) +// End of MG61: + +// Beginning of MG62: +#if (G61PL >= G62PL) || (G61PL == 0) +#define MG62_11PL ~(1) +#else +#define MG62_11PL 0xFFFF +#endif +#if (G63PL >= G62PL) || (G63PL == 0) +#define MG62_13PL ~(1 << 2) +#else +#define MG62_13PL 0xFFFF +#endif +#if (G64PL >= G62PL) || (G64PL == 0) +#define MG62_14PL ~(1 << 3) +#else +#define MG62_14PL 0xFFFF +#endif +#if (G65PL >= G62PL) || (G65PL == 0) +#define MG62_15PL ~(1 << 4) +#else +#define MG62_15PL 0xFFFF +#endif +#if (G66PL >= G62PL) || (G66PL == 0) +#define MG62_16PL ~(1 << 5) +#else +#define MG62_16PL 0xFFFF +#endif +#if (G67PL >= G62PL) || (G67PL == 0) +#define MG62_17PL ~(1 << 6) +#else +#define MG62_17PL 0xFFFF +#endif +#if (G68PL >= G62PL) || (G68PL == 0) +#define MG62_18PL ~(1 << 7) +#else +#define MG62_18PL 0xFFFF +#endif +#define MG62_12PL 0x00FD +#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \ + MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL) +// End of MG62: + +// Beginning of MG63: +#if (G61PL >= G63PL) || (G61PL == 0) +#define MG63_11PL ~(1) +#else +#define MG63_11PL 0xFFFF +#endif +#if (G62PL >= G63PL) || (G62PL == 0) +#define MG63_12PL ~(1 << 1) +#else +#define MG63_12PL 0xFFFF +#endif +#if (G64PL >= G63PL) || (G64PL == 0) +#define MG63_14PL ~(1 << 3) +#else +#define MG63_14PL 0xFFFF +#endif +#if (G65PL >= G63PL) || (G65PL == 0) +#define MG63_15PL ~(1 << 4) +#else +#define MG63_15PL 0xFFFF +#endif +#if (G66PL >= G63PL) || (G66PL == 0) +#define MG63_16PL ~(1 << 5) +#else +#define MG63_16PL 0xFFFF +#endif +#if (G67PL >= G63PL) || (G67PL == 0) +#define MG63_17PL ~(1 << 6) +#else +#define MG63_17PL 0xFFFF +#endif +#if (G68PL >= G63PL) || (G68PL == 0) +#define MG63_18PL ~(1 << 7) +#else +#define MG63_18PL 0xFFFF +#endif +#define MG63_13PL 0x00FB +#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \ + MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL) +// End of MG63: + +// Beginning of MG64: +#if (G61PL >= G64PL) || (G61PL == 0) +#define MG64_11PL ~(1) +#else +#define MG64_11PL 0xFFFF +#endif +#if (G62PL >= G64PL) || (G62PL == 0) +#define MG64_12PL ~(1 << 1) +#else +#define MG64_12PL 0xFFFF +#endif +#if (G63PL >= G64PL) || (G63PL == 0) +#define MG64_13PL ~(1 << 2) +#else +#define MG64_13PL 0xFFFF +#endif +#if (G65PL >= G64PL) || (G65PL == 0) +#define MG64_15PL ~(1 << 4) +#else +#define MG64_15PL 0xFFFF +#endif +#if (G66PL >= G64PL) || (G66PL == 0) +#define MG64_16PL ~(1 << 5) +#else +#define MG64_16PL 0xFFFF +#endif +#if (G67PL >= G64PL) || (G67PL == 0) +#define MG64_17PL ~(1 << 6) +#else +#define MG64_17PL 0xFFFF +#endif +#if (G68PL >= G64PL) || (G68PL == 0) +#define MG64_18PL ~(1 << 7) +#else +#define MG64_18PL 0xFFFF +#endif +#define MG64_14PL 0x00F7 +#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \ + MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL) +// End of MG64: + +// Beginning of MG65: +#if (G61PL >= G65PL) || (G61PL == 0) +#define MG65_11PL ~(1) +#else +#define MG65_11PL 0xFFFF +#endif +#if (G62PL >= G65PL) || (G62PL == 0) +#define MG65_12PL ~(1 << 1) +#else +#define MG65_12PL 0xFFFF +#endif +#if (G63PL >= G65PL) || (G63PL == 0) +#define MG65_13PL ~(1 << 2) +#else +#define MG65_13PL 0xFFFF +#endif +#if (G64PL >= G65PL) || (G64PL == 0) +#define MG65_14PL ~(1 << 3) +#else +#define MG65_14PL 0xFFFF +#endif +#if (G66PL >= G65PL) || (G66PL == 0) +#define MG65_16PL ~(1 << 5) +#else +#define MG65_16PL 0xFFFF +#endif +#if (G67PL >= G65PL) || (G67PL == 0) +#define MG65_17PL ~(1 << 6) +#else +#define MG65_17PL 0xFFFF +#endif +#if (G68PL >= G65PL) || (G68PL == 0) +#define MG65_18PL ~(1 << 7) +#else +#define MG65_18PL 0xFFFF +#endif +#define MG65_15PL 0x00EF +#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \ + MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL) +// End of MG65: + +// Beginning of MG66: +#if (G61PL >= G66PL) || (G61PL == 0) +#define MG66_11PL ~(1) +#else +#define MG66_11PL 0xFFFF +#endif +#if (G62PL >= G66PL) || (G62PL == 0) +#define MG66_12PL ~(1 << 1) +#else +#define MG66_12PL 0xFFFF +#endif +#if (G63PL >= G66PL) || (G63PL == 0) +#define MG66_13PL ~(1 << 2) +#else +#define MG66_13PL 0xFFFF +#endif +#if (G64PL >= G66PL) || (G64PL == 0) +#define MG66_14PL ~(1 << 3) +#else +#define MG66_14PL 0xFFFF +#endif +#if (G65PL >= G66PL) || (G65PL == 0) +#define MG66_15PL ~(1 << 4) +#else +#define MG66_15PL 0xFFFF +#endif +#if (G67PL >= G66PL) || (G67PL == 0) +#define MG66_17PL ~(1 << 6) +#else +#define MG66_17PL 0xFFFF +#endif +#if (G68PL >= G66PL) || (G68PL == 0) +#define MG66_18PL ~(1 << 7) +#else +#define MG66_18PL 0xFFFF +#endif +#define MG66_16PL 0x00DF +#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \ + MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL) +// End of MG66: + +// Beginning of MG67: +#if (G61PL >= G67PL) || (G61PL == 0) +#define MG67_11PL ~(1) +#else +#define MG67_11PL 0xFFFF +#endif +#if (G62PL >= G67PL) || (G62PL == 0) +#define MG67_12PL ~(1 << 1) +#else +#define MG67_12PL 0xFFFF +#endif +#if (G63PL >= G67PL) || (G63PL == 0) +#define MG67_13PL ~(1 << 2) +#else +#define MG67_13PL 0xFFFF +#endif +#if (G64PL >= G67PL) || (G64PL == 0) +#define MG67_14PL ~(1 << 3) +#else +#define MG67_14PL 0xFFFF +#endif +#if (G65PL >= G67PL) || (G65PL == 0) +#define MG67_15PL ~(1 << 4) +#else +#define MG67_15PL 0xFFFF +#endif +#if (G66PL >= G67PL) || (G66PL == 0) +#define MG67_16PL ~(1 << 5) +#else +#define MG67_16PL 0xFFFF +#endif +#if (G68PL >= G67PL) || (G68PL == 0) +#define MG67_18PL ~(1 << 7) +#else +#define MG67_18PL 0xFFFF +#endif +#define MG67_17PL 0x00BF +#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \ + MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL) +// End of MG67: + +// Beginning of MG68: +#if (G61PL >= G68PL) || (G61PL == 0) +#define MG68_11PL ~(1) +#else +#define MG68_11PL 0xFFFF +#endif +#if (G62PL >= G68PL) || (G62PL == 0) +#define MG68_12PL ~(1 << 1) +#else +#define MG68_12PL 0xFFFF +#endif +#if (G63PL >= G68PL) || (G63PL == 0) +#define MG68_13PL ~(1 << 2) +#else +#define MG68_13PL 0xFFFF +#endif +#if (G64PL >= G68PL) || (G64PL == 0) +#define MG68_14PL ~(1 << 3) +#else +#define MG68_14PL 0xFFFF +#endif +#if (G65PL >= G68PL) || (G65PL == 0) +#define MG68_15PL ~(1 << 4) +#else +#define MG68_15PL 0xFFFF +#endif +#if (G66PL >= G68PL) || (G66PL == 0) +#define MG68_16PL ~(1 << 5) +#else +#define MG68_16PL 0xFFFF +#endif +#if (G67PL >= G68PL) || (G67PL == 0) +#define MG68_17PL ~(1 << 6) +#else +#define MG68_17PL 0xFFFF +#endif +#define MG68_18PL 0x007F +#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \ + MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL) +// End of MG68: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG71 to MG78: +// + +// Beginning of MG71: +#if (G72PL >= G71PL) || (G72PL == 0) +#define MG71_12PL ~(1 << 1) +#else +#define MG71_12PL 0xFFFF +#endif +#if (G73PL >= G71PL) || (G73PL == 0) +#define MG71_13PL ~(1 << 2) +#else +#define MG71_13PL 0xFFFF +#endif +#if (G74PL >= G71PL) || (G74PL == 0) +#define MG71_14PL ~(1 << 3) +#else +#define MG71_14PL 0xFFFF +#endif +#if (G75PL >= G71PL) || (G75PL == 0) +#define MG71_15PL ~(1 << 4) +#else +#define MG71_15PL 0xFFFF +#endif +#if (G76PL >= G71PL) || (G76PL == 0) +#define MG71_16PL ~(1 << 5) +#else +#define MG71_16PL 0xFFFF +#endif +#if (G77PL >= G71PL) || (G77PL == 0) +#define MG71_17PL ~(1 << 6) +#else +#define MG71_17PL 0xFFFF +#endif +#if (G78PL >= G71PL) || (G78PL == 0) +#define MG71_18PL ~(1 << 7) +#else +#define MG71_18PL 0xFFFF +#endif +#define MG71_11PL 0x00FE +#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \ + MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL) +// End of MG71: + +// Beginning of MG72: +#if (G71PL >= G72PL) || (G71PL == 0) +#define MG72_11PL ~(1) +#else +#define MG72_11PL 0xFFFF +#endif +#if (G73PL >= G72PL) || (G73PL == 0) +#define MG72_13PL ~(1 << 2) +#else +#define MG72_13PL 0xFFFF +#endif +#if (G74PL >= G72PL) || (G74PL == 0) +#define MG72_14PL ~(1 << 3) +#else +#define MG72_14PL 0xFFFF +#endif +#if (G75PL >= G72PL) || (G75PL == 0) +#define MG72_15PL ~(1 << 4) +#else +#define MG72_15PL 0xFFFF +#endif +#if (G76PL >= G72PL) || (G76PL == 0) +#define MG72_16PL ~(1 << 5) +#else +#define MG72_16PL 0xFFFF +#endif +#if (G77PL >= G72PL) || (G77PL == 0) +#define MG72_17PL ~(1 << 6) +#else +#define MG72_17PL 0xFFFF +#endif +#if (G78PL >= G72PL) || (G78PL == 0) +#define MG72_18PL ~(1 << 7) +#else +#define MG72_18PL 0xFFFF +#endif +#define MG72_12PL 0x00FD +#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \ + MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL) +// End of MG72: + +// Beginning of MG73: +#if (G71PL >= G73PL) || (G71PL == 0) +#define MG73_11PL ~(1) +#else +#define MG73_11PL 0xFFFF +#endif +#if (G72PL >= G73PL) || (G72PL == 0) +#define MG73_12PL ~(1 << 1) +#else +#define MG73_12PL 0xFFFF +#endif +#if (G74PL >= G73PL) || (G74PL == 0) +#define MG73_14PL ~(1 << 3) +#else +#define MG73_14PL 0xFFFF +#endif +#if (G75PL >= G73PL) || (G75PL == 0) +#define MG73_15PL ~(1 << 4) +#else +#define MG73_15PL 0xFFFF +#endif +#if (G76PL >= G73PL) || (G76PL == 0) +#define MG73_16PL ~(1 << 5) +#else +#define MG73_16PL 0xFFFF +#endif +#if (G77PL >= G73PL) || (G77PL == 0) +#define MG73_17PL ~(1 << 6) +#else +#define MG73_17PL 0xFFFF +#endif +#if (G78PL >= G73PL) || (G78PL == 0) +#define MG73_18PL ~(1 << 7) +#else +#define MG73_18PL 0xFFFF +#endif +#define MG73_13PL 0x00FB +#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \ + MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL) +// End of MG73: + +// Beginning of MG74: +#if (G71PL >= G74PL) || (G71PL == 0) +#define MG74_11PL ~(1) +#else +#define MG74_11PL 0xFFFF +#endif +#if (G72PL >= G74PL) || (G72PL == 0) +#define MG74_12PL ~(1 << 1) +#else +#define MG74_12PL 0xFFFF +#endif +#if (G73PL >= G74PL) || (G73PL == 0) +#define MG74_13PL ~(1 << 2) +#else +#define MG74_13PL 0xFFFF +#endif +#if (G75PL >= G74PL) || (G75PL == 0) +#define MG74_15PL ~(1 << 4) +#else +#define MG74_15PL 0xFFFF +#endif +#if (G76PL >= G74PL) || (G76PL == 0) +#define MG74_16PL ~(1 << 5) +#else +#define MG74_16PL 0xFFFF +#endif +#if (G77PL >= G74PL) || (G77PL == 0) +#define MG74_17PL ~(1 << 6) +#else +#define MG74_17PL 0xFFFF +#endif +#if (G78PL >= G74PL) || (G78PL == 0) +#define MG74_18PL ~(1 << 7) +#else +#define MG74_18PL 0xFFFF +#endif +#define MG74_14PL 0x00F7 +#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \ + MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL) +// End of MG74: + +// Beginning of MG75: +#if (G71PL >= G75PL) || (G71PL == 0) +#define MG75_11PL ~(1) +#else +#define MG75_11PL 0xFFFF +#endif +#if (G72PL >= G75PL) || (G72PL == 0) +#define MG75_12PL ~(1 << 1) +#else +#define MG75_12PL 0xFFFF +#endif +#if (G73PL >= G75PL) || (G73PL == 0) +#define MG75_13PL ~(1 << 2) +#else +#define MG75_13PL 0xFFFF +#endif +#if (G74PL >= G75PL) || (G74PL == 0) +#define MG75_14PL ~(1 << 3) +#else +#define MG75_14PL 0xFFFF +#endif +#if (G76PL >= G75PL) || (G76PL == 0) +#define MG75_16PL ~(1 << 5) +#else +#define MG75_16PL 0xFFFF +#endif +#if (G77PL >= G75PL) || (G77PL == 0) +#define MG75_17PL ~(1 << 6) +#else +#define MG75_17PL 0xFFFF +#endif +#if (G78PL >= G75PL) || (G78PL == 0) +#define MG75_18PL ~(1 << 7) +#else +#define MG75_18PL 0xFFFF +#endif +#define MG75_15PL 0x00EF +#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \ + MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL) +// End of MG75: + +// Beginning of MG76: +#if (G71PL >= G76PL) || (G71PL == 0) +#define MG76_11PL ~(1) +#else +#define MG76_11PL 0xFFFF +#endif +#if (G72PL >= G76PL) || (G72PL == 0) +#define MG76_12PL ~(1 << 1) +#else +#define MG76_12PL 0xFFFF +#endif +#if (G73PL >= G76PL) || (G73PL == 0) +#define MG76_13PL ~(1 << 2) +#else +#define MG76_13PL 0xFFFF +#endif +#if (G74PL >= G76PL) || (G74PL == 0) +#define MG76_14PL ~(1 << 3) +#else +#define MG76_14PL 0xFFFF +#endif +#if (G75PL >= G76PL) || (G75PL == 0) +#define MG76_15PL ~(1 << 4) +#else +#define MG76_15PL 0xFFFF +#endif +#if (G77PL >= G76PL) || (G77PL == 0) +#define MG76_17PL ~(1 << 6) +#else +#define MG76_17PL 0xFFFF +#endif +#if (G78PL >= G76PL) || (G78PL == 0) +#define MG76_18PL ~(1 << 7) +#else +#define MG76_18PL 0xFFFF +#endif +#define MG76_16PL 0x00DF +#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \ + MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL) +// End of MG76: + +// Beginning of MG77: +#if (G71PL >= G77PL) || (G71PL == 0) +#define MG77_11PL ~(1) +#else +#define MG77_11PL 0xFFFF +#endif +#if (G72PL >= G77PL) || (G72PL == 0) +#define MG77_12PL ~(1 << 1) +#else +#define MG77_12PL 0xFFFF +#endif +#if (G73PL >= G77PL) || (G73PL == 0) +#define MG77_13PL ~(1 << 2) +#else +#define MG77_13PL 0xFFFF +#endif +#if (G74PL >= G77PL) || (G74PL == 0) +#define MG77_14PL ~(1 << 3) +#else +#define MG77_14PL 0xFFFF +#endif +#if (G75PL >= G77PL) || (G75PL == 0) +#define MG77_15PL ~(1 << 4) +#else +#define MG77_15PL 0xFFFF +#endif +#if (G76PL >= G77PL) || (G76PL == 0) +#define MG77_16PL ~(1 << 5) +#else +#define MG77_16PL 0xFFFF +#endif +#if (G78PL >= G77PL) || (G78PL == 0) +#define MG77_18PL ~(1 << 7) +#else +#define MG77_18PL 0xFFFF +#endif +#define MG77_17PL 0x00BF +#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \ + MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL) +// End of MG77: + +// Beginning of MG78: +#if (G71PL >= G78PL) || (G71PL == 0) +#define MG78_11PL ~(1) +#else +#define MG78_11PL 0xFFFF +#endif +#if (G72PL >= G78PL) || (G72PL == 0) +#define MG78_12PL ~(1 << 1) +#else +#define MG78_12PL 0xFFFF +#endif +#if (G73PL >= G78PL) || (G73PL == 0) +#define MG78_13PL ~(1 << 2) +#else +#define MG78_13PL 0xFFFF +#endif +#if (G74PL >= G78PL) || (G74PL == 0) +#define MG78_14PL ~(1 << 3) +#else +#define MG78_14PL 0xFFFF +#endif +#if (G75PL >= G78PL) || (G75PL == 0) +#define MG78_15PL ~(1 << 4) +#else +#define MG78_15PL 0xFFFF +#endif +#if (G76PL >= G78PL) || (G76PL == 0) +#define MG78_16PL ~(1 << 5) +#else +#define MG78_16PL 0xFFFF +#endif +#if (G77PL >= G78PL) || (G77PL == 0) +#define MG78_17PL ~(1 << 6) +#else +#define MG78_17PL 0xFFFF +#endif +#define MG78_18PL 0x007F +#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \ + MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL) +// End of MG78: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG81 to MG88: +// + +// Beginning of MG81: +#if (G82PL >= G81PL) || (G82PL == 0) +#define MG81_12PL ~(1 << 1) +#else +#define MG81_12PL 0xFFFF +#endif +#if (G83PL >= G81PL) || (G83PL == 0) +#define MG81_13PL ~(1 << 2) +#else +#define MG81_13PL 0xFFFF +#endif +#if (G84PL >= G81PL) || (G84PL == 0) +#define MG81_14PL ~(1 << 3) +#else +#define MG81_14PL 0xFFFF +#endif +#if (G85PL >= G81PL) || (G85PL == 0) +#define MG81_15PL ~(1 << 4) +#else +#define MG81_15PL 0xFFFF +#endif +#if (G86PL >= G81PL) || (G86PL == 0) +#define MG81_16PL ~(1 << 5) +#else +#define MG81_16PL 0xFFFF +#endif +#if (G87PL >= G81PL) || (G87PL == 0) +#define MG81_17PL ~(1 << 6) +#else +#define MG81_17PL 0xFFFF +#endif +#if (G88PL >= G81PL) || (G88PL == 0) +#define MG81_18PL ~(1 << 7) +#else +#define MG81_18PL 0xFFFF +#endif +#define MG81_11PL 0x00FE +#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \ + MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL) +// End of MG81: + +// Beginning of MG82: +#if (G81PL >= G82PL) || (G81PL == 0) +#define MG82_11PL ~(1) +#else +#define MG82_11PL 0xFFFF +#endif +#if (G83PL >= G82PL) || (G83PL == 0) +#define MG82_13PL ~(1 << 2) +#else +#define MG82_13PL 0xFFFF +#endif +#if (G84PL >= G82PL) || (G84PL == 0) +#define MG82_14PL ~(1 << 3) +#else +#define MG82_14PL 0xFFFF +#endif +#if (G85PL >= G82PL) || (G85PL == 0) +#define MG82_15PL ~(1 << 4) +#else +#define MG82_15PL 0xFFFF +#endif +#if (G86PL >= G82PL) || (G86PL == 0) +#define MG82_16PL ~(1 << 5) +#else +#define MG82_16PL 0xFFFF +#endif +#if (G87PL >= G82PL) || (G87PL == 0) +#define MG82_17PL ~(1 << 6) +#else +#define MG82_17PL 0xFFFF +#endif +#if (G88PL >= G82PL) || (G88PL == 0) +#define MG82_18PL ~(1 << 7) +#else +#define MG82_18PL 0xFFFF +#endif +#define MG82_12PL 0x00FD +#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \ + MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL) +// End of MG82: + +// Beginning of MG83: +#if (G81PL >= G83PL) || (G81PL == 0) +#define MG83_11PL ~(1) +#else +#define MG83_11PL 0xFFFF +#endif +#if (G82PL >= G83PL) || (G82PL == 0) +#define MG83_12PL ~(1 << 1) +#else +#define MG83_12PL 0xFFFF +#endif +#if (G84PL >= G83PL) || (G84PL == 0) +#define MG83_14PL ~(1 << 3) +#else +#define MG83_14PL 0xFFFF +#endif +#if (G85PL >= G83PL) || (G85PL == 0) +#define MG83_15PL ~(1 << 4) +#else +#define MG83_15PL 0xFFFF +#endif +#if (G86PL >= G83PL) || (G86PL == 0) +#define MG83_16PL ~(1 << 5) +#else +#define MG83_16PL 0xFFFF +#endif +#if (G87PL >= G83PL) || (G87PL == 0) +#define MG83_17PL ~(1 << 6) +#else +#define MG83_17PL 0xFFFF +#endif +#if (G88PL >= G83PL) || (G88PL == 0) +#define MG83_18PL ~(1 << 7) +#else +#define MG83_18PL 0xFFFF +#endif +#define MG83_13PL 0x00FB +#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \ + MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL) +// End of MG83: + +// Beginning of MG84: +#if (G81PL >= G84PL) || (G81PL == 0) +#define MG84_11PL ~(1) +#else +#define MG84_11PL 0xFFFF +#endif +#if (G82PL >= G84PL) || (G82PL == 0) +#define MG84_12PL ~(1 << 1) +#else +#define MG84_12PL 0xFFFF +#endif +#if (G83PL >= G84PL) || (G83PL == 0) +#define MG84_13PL ~(1 << 2) +#else +#define MG84_13PL 0xFFFF +#endif +#if (G85PL >= G84PL) || (G85PL == 0) +#define MG84_15PL ~(1 << 4) +#else +#define MG84_15PL 0xFFFF +#endif +#if (G86PL >= G84PL) || (G86PL == 0) +#define MG84_16PL ~(1 << 5) +#else +#define MG84_16PL 0xFFFF +#endif +#if (G87PL >= G84PL) || (G87PL == 0) +#define MG84_17PL ~(1 << 6) +#else +#define MG84_17PL 0xFFFF +#endif +#if (G88PL >= G84PL) || (G88PL == 0) +#define MG84_18PL ~(1 << 7) +#else +#define MG84_18PL 0xFFFF +#endif +#define MG84_14PL 0x00F7 +#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \ + MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL) +// End of MG84: + +// Beginning of MG85: +#if (G81PL >= G85PL) || (G81PL == 0) +#define MG85_11PL ~(1) +#else +#define MG85_11PL 0xFFFF +#endif +#if (G82PL >= G85PL) || (G82PL == 0) +#define MG85_12PL ~(1 << 1) +#else +#define MG85_12PL 0xFFFF +#endif +#if (G83PL >= G85PL) || (G83PL == 0) +#define MG85_13PL ~(1 << 2) +#else +#define MG85_13PL 0xFFFF +#endif +#if (G84PL >= G85PL) || (G84PL == 0) +#define MG85_14PL ~(1 << 3) +#else +#define MG85_14PL 0xFFFF +#endif +#if (G86PL >= G85PL) || (G86PL == 0) +#define MG85_16PL ~(1 << 5) +#else +#define MG85_16PL 0xFFFF +#endif +#if (G87PL >= G85PL) || (G87PL == 0) +#define MG85_17PL ~(1 << 6) +#else +#define MG85_17PL 0xFFFF +#endif +#if (G88PL >= G85PL) || (G88PL == 0) +#define MG85_18PL ~(1 << 7) +#else +#define MG85_18PL 0xFFFF +#endif +#define MG85_15PL 0x00EF +#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \ + MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL) +// End of MG85: + +// Beginning of MG86: +#if (G81PL >= G86PL) || (G81PL == 0) +#define MG86_11PL ~(1) +#else +#define MG86_11PL 0xFFFF +#endif +#if (G82PL >= G86PL) || (G82PL == 0) +#define MG86_12PL ~(1 << 1) +#else +#define MG86_12PL 0xFFFF +#endif +#if (G83PL >= G86PL) || (G83PL == 0) +#define MG86_13PL ~(1 << 2) +#else +#define MG86_13PL 0xFFFF +#endif +#if (G84PL >= G86PL) || (G84PL == 0) +#define MG86_14PL ~(1 << 3) +#else +#define MG86_14PL 0xFFFF +#endif +#if (G85PL >= G86PL) || (G85PL == 0) +#define MG86_15PL ~(1 << 4) +#else +#define MG86_15PL 0xFFFF +#endif +#if (G87PL >= G86PL) || (G87PL == 0) +#define MG86_17PL ~(1 << 6) +#else +#define MG86_17PL 0xFFFF +#endif +#if (G88PL >= G86PL) || (G88PL == 0) +#define MG86_18PL ~(1 << 7) +#else +#define MG86_18PL 0xFFFF +#endif +#define MG86_16PL 0x00DF +#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \ + MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL) +// End of MG86: + +// Beginning of MG87: +#if (G81PL >= G87PL) || (G81PL == 0) +#define MG87_11PL ~(1) +#else +#define MG87_11PL 0xFFFF +#endif +#if (G82PL >= G87PL) || (G82PL == 0) +#define MG87_12PL ~(1 << 1) +#else +#define MG87_12PL 0xFFFF +#endif +#if (G83PL >= G87PL) || (G83PL == 0) +#define MG87_13PL ~(1 << 2) +#else +#define MG87_13PL 0xFFFF +#endif +#if (G84PL >= G87PL) || (G84PL == 0) +#define MG87_14PL ~(1 << 3) +#else +#define MG87_14PL 0xFFFF +#endif +#if (G85PL >= G87PL) || (G85PL == 0) +#define MG87_15PL ~(1 << 4) +#else +#define MG87_15PL 0xFFFF +#endif +#if (G86PL >= G87PL) || (G86PL == 0) +#define MG87_16PL ~(1 << 5) +#else +#define MG87_16PL 0xFFFF +#endif +#if (G88PL >= G87PL) || (G88PL == 0) +#define MG87_18PL ~(1 << 7) +#else +#define MG87_18PL 0xFFFF +#endif +#define MG87_17PL 0x00BF +#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \ + MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL) +// End of MG87: + +// Beginning of MG88: +#if (G81PL >= G88PL) || (G81PL == 0) +#define MG88_11PL ~(1) +#else +#define MG88_11PL 0xFFFF +#endif +#if (G82PL >= G88PL) || (G82PL == 0) +#define MG88_12PL ~(1 << 1) +#else +#define MG88_12PL 0xFFFF +#endif +#if (G83PL >= G88PL) || (G83PL == 0) +#define MG88_13PL ~(1 << 2) +#else +#define MG88_13PL 0xFFFF +#endif +#if (G84PL >= G88PL) || (G84PL == 0) +#define MG88_14PL ~(1 << 3) +#else +#define MG88_14PL 0xFFFF +#endif +#if (G85PL >= G88PL) || (G85PL == 0) +#define MG88_15PL ~(1 << 4) +#else +#define MG88_15PL 0xFFFF +#endif +#if (G86PL >= G88PL) || (G86PL == 0) +#define MG88_16PL ~(1 << 5) +#else +#define MG88_16PL 0xFFFF +#endif +#if (G87PL >= G88PL) || (G87PL == 0) +#define MG88_17PL ~(1 << 6) +#else +#define MG88_17PL 0xFFFF +#endif +#define MG88_18PL 0x007F +#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \ + MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL) +// End of MG88: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG91 to MG98: +// + +// Beginning of MG91: +#if (G92PL >= G91PL) || (G92PL == 0) +#define MG91_12PL ~(1 << 1) +#else +#define MG91_12PL 0xFFFF +#endif +#if (G93PL >= G91PL) || (G93PL == 0) +#define MG91_13PL ~(1 << 2) +#else +#define MG91_13PL 0xFFFF +#endif +#if (G94PL >= G91PL) || (G94PL == 0) +#define MG91_14PL ~(1 << 3) +#else +#define MG91_14PL 0xFFFF +#endif +#if (G95PL >= G91PL) || (G95PL == 0) +#define MG91_15PL ~(1 << 4) +#else +#define MG91_15PL 0xFFFF +#endif +#if (G96PL >= G91PL) || (G96PL == 0) +#define MG91_16PL ~(1 << 5) +#else +#define MG91_16PL 0xFFFF +#endif +#if (G97PL >= G91PL) || (G97PL == 0) +#define MG91_17PL ~(1 << 6) +#else +#define MG91_17PL 0xFFFF +#endif +#if (G98PL >= G91PL) || (G98PL == 0) +#define MG91_18PL ~(1 << 7) +#else +#define MG91_18PL 0xFFFF +#endif +#define MG91_11PL 0x00FE +#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \ + MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL) +// End of MG91: + +// Beginning of MG92: +#if (G91PL >= G92PL) || (G91PL == 0) +#define MG92_11PL ~(1) +#else +#define MG92_11PL 0xFFFF +#endif +#if (G93PL >= G92PL) || (G93PL == 0) +#define MG92_13PL ~(1 << 2) +#else +#define MG92_13PL 0xFFFF +#endif +#if (G94PL >= G92PL) || (G94PL == 0) +#define MG92_14PL ~(1 << 3) +#else +#define MG92_14PL 0xFFFF +#endif +#if (G95PL >= G92PL) || (G95PL == 0) +#define MG92_15PL ~(1 << 4) +#else +#define MG92_15PL 0xFFFF +#endif +#if (G96PL >= G92PL) || (G96PL == 0) +#define MG92_16PL ~(1 << 5) +#else +#define MG92_16PL 0xFFFF +#endif +#if (G97PL >= G92PL) || (G97PL == 0) +#define MG92_17PL ~(1 << 6) +#else +#define MG92_17PL 0xFFFF +#endif +#if (G98PL >= G92PL) || (G98PL == 0) +#define MG92_18PL ~(1 << 7) +#else +#define MG92_18PL 0xFFFF +#endif +#define MG92_12PL 0x00FD +#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \ + MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL) +// End of MG92: + +// Beginning of MG93: +#if (G91PL >= G93PL) || (G91PL == 0) +#define MG93_11PL ~(1) +#else +#define MG93_11PL 0xFFFF +#endif +#if (G92PL >= G93PL) || (G92PL == 0) +#define MG93_12PL ~(1 << 1) +#else +#define MG93_12PL 0xFFFF +#endif +#if (G94PL >= G93PL) || (G94PL == 0) +#define MG93_14PL ~(1 << 3) +#else +#define MG93_14PL 0xFFFF +#endif +#if (G95PL >= G93PL) || (G95PL == 0) +#define MG93_15PL ~(1 << 4) +#else +#define MG93_15PL 0xFFFF +#endif +#if (G96PL >= G93PL) || (G96PL == 0) +#define MG93_16PL ~(1 << 5) +#else +#define MG93_16PL 0xFFFF +#endif +#if (G97PL >= G93PL) || (G97PL == 0) +#define MG93_17PL ~(1 << 6) +#else +#define MG93_17PL 0xFFFF +#endif +#if (G98PL >= G93PL) || (G98PL == 0) +#define MG93_18PL ~(1 << 7) +#else +#define MG93_18PL 0xFFFF +#endif +#define MG93_13PL 0x00FB +#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \ + MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL) +// End of MG93: + +// Beginning of MG94: +#if (G91PL >= G94PL) || (G91PL == 0) +#define MG94_11PL ~(1) +#else +#define MG94_11PL 0xFFFF +#endif +#if (G92PL >= G94PL) || (G92PL == 0) +#define MG94_12PL ~(1 << 1) +#else +#define MG94_12PL 0xFFFF +#endif +#if (G93PL >= G94PL) || (G93PL == 0) +#define MG94_13PL ~(1 << 2) +#else +#define MG94_13PL 0xFFFF +#endif +#if (G95PL >= G94PL) || (G95PL == 0) +#define MG94_15PL ~(1 << 4) +#else +#define MG94_15PL 0xFFFF +#endif +#if (G96PL >= G94PL) || (G96PL == 0) +#define MG94_16PL ~(1 << 5) +#else +#define MG94_16PL 0xFFFF +#endif +#if (G97PL >= G94PL) || (G97PL == 0) +#define MG94_17PL ~(1 << 6) +#else +#define MG94_17PL 0xFFFF +#endif +#if (G98PL >= G94PL) || (G98PL == 0) +#define MG94_18PL ~(1 << 7) +#else +#define MG94_18PL 0xFFFF +#endif +#define MG94_14PL 0x00F7 +#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \ + MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL) +// End of MG94: + +// Beginning of MG95: +#if (G91PL >= G95PL) || (G91PL == 0) +#define MG95_11PL ~(1) +#else +#define MG95_11PL 0xFFFF +#endif +#if (G92PL >= G95PL) || (G92PL == 0) +#define MG95_12PL ~(1 << 1) +#else +#define MG95_12PL 0xFFFF +#endif +#if (G93PL >= G95PL) || (G93PL == 0) +#define MG95_13PL ~(1 << 2) +#else +#define MG95_13PL 0xFFFF +#endif +#if (G94PL >= G95PL) || (G94PL == 0) +#define MG95_14PL ~(1 << 3) +#else +#define MG95_14PL 0xFFFF +#endif +#if (G96PL >= G95PL) || (G96PL == 0) +#define MG95_16PL ~(1 << 5) +#else +#define MG95_16PL 0xFFFF +#endif +#if (G97PL >= G95PL) || (G97PL == 0) +#define MG95_17PL ~(1 << 6) +#else +#define MG95_17PL 0xFFFF +#endif +#if (G98PL >= G95PL) || (G98PL == 0) +#define MG95_18PL ~(1 << 7) +#else +#define MG95_18PL 0xFFFF +#endif +#define MG95_15PL 0x00EF +#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \ + MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL) +// End of MG95: + +// Beginning of MG96: +#if (G91PL >= G96PL) || (G91PL == 0) +#define MG96_11PL ~(1) +#else +#define MG96_11PL 0xFFFF +#endif +#if (G92PL >= G96PL) || (G92PL == 0) +#define MG96_12PL ~(1 << 1) +#else +#define MG96_12PL 0xFFFF +#endif +#if (G93PL >= G96PL) || (G93PL == 0) +#define MG96_13PL ~(1 << 2) +#else +#define MG96_13PL 0xFFFF +#endif +#if (G94PL >= G96PL) || (G94PL == 0) +#define MG96_14PL ~(1 << 3) +#else +#define MG96_14PL 0xFFFF +#endif +#if (G95PL >= G96PL) || (G95PL == 0) +#define MG96_15PL ~(1 << 4) +#else +#define MG96_15PL 0xFFFF +#endif +#if (G97PL >= G96PL) || (G97PL == 0) +#define MG96_17PL ~(1 << 6) +#else +#define MG96_17PL 0xFFFF +#endif +#if (G98PL >= G96PL) || (G98PL == 0) +#define MG96_18PL ~(1 << 7) +#else +#define MG96_18PL 0xFFFF +#endif +#define MG96_16PL 0x00DF +#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \ + MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL) +// End of MG96: + +// Beginning of MG97: +#if (G91PL >= G97PL) || (G91PL == 0) +#define MG97_11PL ~(1) +#else +#define MG97_11PL 0xFFFF +#endif +#if (G92PL >= G97PL) || (G92PL == 0) +#define MG97_12PL ~(1 << 1) +#else +#define MG97_12PL 0xFFFF +#endif +#if (G93PL >= G97PL) || (G93PL == 0) +#define MG97_13PL ~(1 << 2) +#else +#define MG97_13PL 0xFFFF +#endif +#if (G94PL >= G97PL) || (G94PL == 0) +#define MG97_14PL ~(1 << 3) +#else +#define MG97_14PL 0xFFFF +#endif +#if (G95PL >= G97PL) || (G95PL == 0) +#define MG97_15PL ~(1 << 4) +#else +#define MG97_15PL 0xFFFF +#endif +#if (G96PL >= G97PL) || (G96PL == 0) +#define MG97_16PL ~(1 << 5) +#else +#define MG97_16PL 0xFFFF +#endif +#if (G98PL >= G97PL) || (G98PL == 0) +#define MG97_18PL ~(1 << 7) +#else +#define MG97_18PL 0xFFFF +#endif +#define MG97_17PL 0x00BF +#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \ + MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL) +// End of MG97: + +// Beginning of MG98: +#if (G91PL >= G98PL) || (G91PL == 0) +#define MG98_11PL ~(1) +#else +#define MG98_11PL 0xFFFF +#endif +#if (G92PL >= G98PL) || (G92PL == 0) +#define MG98_12PL ~(1 << 1) +#else +#define MG98_12PL 0xFFFF +#endif +#if (G93PL >= G98PL) || (G93PL == 0) +#define MG98_13PL ~(1 << 2) +#else +#define MG98_13PL 0xFFFF +#endif +#if (G94PL >= G98PL) || (G94PL == 0) +#define MG98_14PL ~(1 << 3) +#else +#define MG98_14PL 0xFFFF +#endif +#if (G95PL >= G98PL) || (G95PL == 0) +#define MG98_15PL ~(1 << 4) +#else +#define MG98_15PL 0xFFFF +#endif +#if (G96PL >= G98PL) || (G96PL == 0) +#define MG98_16PL ~(1 << 5) +#else +#define MG98_16PL 0xFFFF +#endif +#if (G97PL >= G98PL) || (G97PL == 0) +#define MG98_17PL ~(1 << 6) +#else +#define MG98_17PL 0xFFFF +#endif +#define MG98_18PL 0x007F +#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \ + MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL) +// End of MG98: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG101 to MG108: +// + +// Beginning of MG101: +#if (G102PL >= G101PL) || (G102PL == 0) +#define MG101_12PL ~(1 << 1) +#else +#define MG101_12PL 0xFFFF +#endif +#if (G103PL >= G101PL) || (G103PL == 0) +#define MG101_13PL ~(1 << 2) +#else +#define MG101_13PL 0xFFFF +#endif +#if (G104PL >= G101PL) || (G104PL == 0) +#define MG101_14PL ~(1 << 3) +#else +#define MG101_14PL 0xFFFF +#endif +#if (G105PL >= G101PL) || (G105PL == 0) +#define MG101_15PL ~(1 << 4) +#else +#define MG101_15PL 0xFFFF +#endif +#if (G106PL >= G101PL) || (G106PL == 0) +#define MG101_16PL ~(1 << 5) +#else +#define MG101_16PL 0xFFFF +#endif +#if (G107PL >= G101PL) || (G107PL == 0) +#define MG101_17PL ~(1 << 6) +#else +#define MG101_17PL 0xFFFF +#endif +#if (G108PL >= G101PL) || (G108PL == 0) +#define MG101_18PL ~(1 << 7) +#else +#define MG101_18PL 0xFFFF +#endif +#define MG101_11PL 0x00FE +#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \ + MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL) +// End of MG101: + +// Beginning of MG102: +#if (G101PL >= G102PL) || (G101PL == 0) +#define MG102_11PL ~(1) +#else +#define MG102_11PL 0xFFFF +#endif +#if (G103PL >= G102PL) || (G103PL == 0) +#define MG102_13PL ~(1 << 2) +#else +#define MG102_13PL 0xFFFF +#endif +#if (G104PL >= G102PL) || (G104PL == 0) +#define MG102_14PL ~(1 << 3) +#else +#define MG102_14PL 0xFFFF +#endif +#if (G105PL >= G102PL) || (G105PL == 0) +#define MG102_15PL ~(1 << 4) +#else +#define MG102_15PL 0xFFFF +#endif +#if (G106PL >= G102PL) || (G106PL == 0) +#define MG102_16PL ~(1 << 5) +#else +#define MG102_16PL 0xFFFF +#endif +#if (G107PL >= G102PL) || (G107PL == 0) +#define MG102_17PL ~(1 << 6) +#else +#define MG102_17PL 0xFFFF +#endif +#if (G108PL >= G102PL) || (G108PL == 0) +#define MG102_18PL ~(1 << 7) +#else +#define MG102_18PL 0xFFFF +#endif +#define MG102_12PL 0x00FD +#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \ + MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL) +// End of MG102: + +// Beginning of MG103: +#if (G101PL >= G103PL) || (G101PL == 0) +#define MG103_11PL ~(1) +#else +#define MG103_11PL 0xFFFF +#endif +#if (G102PL >= G103PL) || (G102PL == 0) +#define MG103_12PL ~(1 << 1) +#else +#define MG103_12PL 0xFFFF +#endif +#if (G104PL >= G103PL) || (G104PL == 0) +#define MG103_14PL ~(1 << 3) +#else +#define MG103_14PL 0xFFFF +#endif +#if (G105PL >= G103PL) || (G105PL == 0) +#define MG103_15PL ~(1 << 4) +#else +#define MG103_15PL 0xFFFF +#endif +#if (G106PL >= G103PL) || (G106PL == 0) +#define MG103_16PL ~(1 << 5) +#else +#define MG103_16PL 0xFFFF +#endif +#if (G107PL >= G103PL) || (G107PL == 0) +#define MG103_17PL ~(1 << 6) +#else +#define MG103_17PL 0xFFFF +#endif +#if (G108PL >= G103PL) || (G108PL == 0) +#define MG103_18PL ~(1 << 7) +#else +#define MG103_18PL 0xFFFF +#endif +#define MG103_13PL 0x00FB +#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \ + MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL) +// End of MG103: + +// Beginning of MG104: +#if (G101PL >= G104PL) || (G101PL == 0) +#define MG104_11PL ~(1) +#else +#define MG104_11PL 0xFFFF +#endif +#if (G102PL >= G104PL) || (G102PL == 0) +#define MG104_12PL ~(1 << 1) +#else +#define MG104_12PL 0xFFFF +#endif +#if (G103PL >= G104PL) || (G103PL == 0) +#define MG104_13PL ~(1 << 2) +#else +#define MG104_13PL 0xFFFF +#endif +#if (G105PL >= G104PL) || (G105PL == 0) +#define MG104_15PL ~(1 << 4) +#else +#define MG104_15PL 0xFFFF +#endif +#if (G106PL >= G104PL) || (G106PL == 0) +#define MG104_16PL ~(1 << 5) +#else +#define MG104_16PL 0xFFFF +#endif +#if (G107PL >= G104PL) || (G107PL == 0) +#define MG104_17PL ~(1 << 6) +#else +#define MG104_17PL 0xFFFF +#endif +#if (G108PL >= G104PL) || (G108PL == 0) +#define MG104_18PL ~(1 << 7) +#else +#define MG104_18PL 0xFFFF +#endif +#define MG104_14PL 0x00F7 +#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \ + MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL) +// End of MG104: + +// Beginning of MG105: +#if (G101PL >= G105PL) || (G101PL == 0) +#define MG105_11PL ~(1) +#else +#define MG105_11PL 0xFFFF +#endif +#if (G102PL >= G105PL) || (G102PL == 0) +#define MG105_12PL ~(1 << 1) +#else +#define MG105_12PL 0xFFFF +#endif +#if (G103PL >= G105PL) || (G103PL == 0) +#define MG105_13PL ~(1 << 2) +#else +#define MG105_13PL 0xFFFF +#endif +#if (G104PL >= G105PL) || (G104PL == 0) +#define MG105_14PL ~(1 << 3) +#else +#define MG105_14PL 0xFFFF +#endif +#if (G106PL >= G105PL) || (G106PL == 0) +#define MG105_16PL ~(1 << 5) +#else +#define MG105_16PL 0xFFFF +#endif +#if (G107PL >= G105PL) || (G107PL == 0) +#define MG105_17PL ~(1 << 6) +#else +#define MG105_17PL 0xFFFF +#endif +#if (G108PL >= G105PL) || (G108PL == 0) +#define MG105_18PL ~(1 << 7) +#else +#define MG105_18PL 0xFFFF +#endif +#define MG105_15PL 0x00EF +#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \ + MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL) +// End of MG105: + +// Beginning of MG106: +#if (G101PL >= G106PL) || (G101PL == 0) +#define MG106_11PL ~(1) +#else +#define MG106_11PL 0xFFFF +#endif +#if (G102PL >= G106PL) || (G102PL == 0) +#define MG106_12PL ~(1 << 1) +#else +#define MG106_12PL 0xFFFF +#endif +#if (G103PL >= G106PL) || (G103PL == 0) +#define MG106_13PL ~(1 << 2) +#else +#define MG106_13PL 0xFFFF +#endif +#if (G104PL >= G106PL) || (G104PL == 0) +#define MG106_14PL ~(1 << 3) +#else +#define MG106_14PL 0xFFFF +#endif +#if (G105PL >= G106PL) || (G105PL == 0) +#define MG106_15PL ~(1 << 4) +#else +#define MG106_15PL 0xFFFF +#endif +#if (G107PL >= G106PL) || (G107PL == 0) +#define MG106_17PL ~(1 << 6) +#else +#define MG106_17PL 0xFFFF +#endif +#if (G108PL >= G106PL) || (G108PL == 0) +#define MG106_18PL ~(1 << 7) +#else +#define MG106_18PL 0xFFFF +#endif +#define MG106_16PL 0x00DF +#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \ + MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL) +// End of MG106: + +// Beginning of MG107: +#if (G101PL >= G107PL) || (G101PL == 0) +#define MG107_11PL ~(1) +#else +#define MG107_11PL 0xFFFF +#endif +#if (G102PL >= G107PL) || (G102PL == 0) +#define MG107_12PL ~(1 << 1) +#else +#define MG107_12PL 0xFFFF +#endif +#if (G103PL >= G107PL) || (G103PL == 0) +#define MG107_13PL ~(1 << 2) +#else +#define MG107_13PL 0xFFFF +#endif +#if (G104PL >= G107PL) || (G104PL == 0) +#define MG107_14PL ~(1 << 3) +#else +#define MG107_14PL 0xFFFF +#endif +#if (G105PL >= G107PL) || (G105PL == 0) +#define MG107_15PL ~(1 << 4) +#else +#define MG107_15PL 0xFFFF +#endif +#if (G106PL >= G107PL) || (G106PL == 0) +#define MG107_16PL ~(1 << 5) +#else +#define MG107_16PL 0xFFFF +#endif +#if (G108PL >= G107PL) || (G108PL == 0) +#define MG107_18PL ~(1 << 7) +#else +#define MG107_18PL 0xFFFF +#endif +#define MG107_17PL 0x00BF +#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \ + MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL) +// End of MG107: + +// Beginning of MG108: +#if (G101PL >= G108PL) || (G101PL == 0) +#define MG108_11PL ~(1) +#else +#define MG108_11PL 0xFFFF +#endif +#if (G102PL >= G108PL) || (G102PL == 0) +#define MG108_12PL ~(1 << 1) +#else +#define MG108_12PL 0xFFFF +#endif +#if (G103PL >= G108PL) || (G103PL == 0) +#define MG108_13PL ~(1 << 2) +#else +#define MG108_13PL 0xFFFF +#endif +#if (G104PL >= G108PL) || (G104PL == 0) +#define MG108_14PL ~(1 << 3) +#else +#define MG108_14PL 0xFFFF +#endif +#if (G105PL >= G108PL) || (G105PL == 0) +#define MG108_15PL ~(1 << 4) +#else +#define MG108_15PL 0xFFFF +#endif +#if (G106PL >= G108PL) || (G106PL == 0) +#define MG108_16PL ~(1 << 5) +#else +#define MG108_16PL 0xFFFF +#endif +#if (G107PL >= G108PL) || (G107PL == 0) +#define MG108_17PL ~(1 << 6) +#else +#define MG108_17PL 0xFFFF +#endif +#define MG108_18PL 0x007F +#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \ + MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL) +// End of MG108: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG111 to MG118: +// + +// Beginning of MG111: +#if (G112PL >= G111PL) || (G112PL == 0) +#define MG111_12PL ~(1 << 1) +#else +#define MG111_12PL 0xFFFF +#endif +#if (G113PL >= G111PL) || (G113PL == 0) +#define MG111_13PL ~(1 << 2) +#else +#define MG111_13PL 0xFFFF +#endif +#if (G114PL >= G111PL) || (G114PL == 0) +#define MG111_14PL ~(1 << 3) +#else +#define MG111_14PL 0xFFFF +#endif +#if (G115PL >= G111PL) || (G115PL == 0) +#define MG111_15PL ~(1 << 4) +#else +#define MG111_15PL 0xFFFF +#endif +#if (G116PL >= G111PL) || (G116PL == 0) +#define MG111_16PL ~(1 << 5) +#else +#define MG111_16PL 0xFFFF +#endif +#if (G117PL >= G111PL) || (G117PL == 0) +#define MG111_17PL ~(1 << 6) +#else +#define MG111_17PL 0xFFFF +#endif +#if (G118PL >= G111PL) || (G118PL == 0) +#define MG111_18PL ~(1 << 7) +#else +#define MG111_18PL 0xFFFF +#endif +#define MG111_11PL 0x00FE +#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \ + MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL) +// End of MG111: + +// Beginning of MG112: +#if (G111PL >= G112PL) || (G111PL == 0) +#define MG112_11PL ~(1) +#else +#define MG112_11PL 0xFFFF +#endif +#if (G113PL >= G112PL) || (G113PL == 0) +#define MG112_13PL ~(1 << 2) +#else +#define MG112_13PL 0xFFFF +#endif +#if (G114PL >= G112PL) || (G114PL == 0) +#define MG112_14PL ~(1 << 3) +#else +#define MG112_14PL 0xFFFF +#endif +#if (G115PL >= G112PL) || (G115PL == 0) +#define MG112_15PL ~(1 << 4) +#else +#define MG112_15PL 0xFFFF +#endif +#if (G116PL >= G112PL) || (G116PL == 0) +#define MG112_16PL ~(1 << 5) +#else +#define MG112_16PL 0xFFFF +#endif +#if (G117PL >= G112PL) || (G117PL == 0) +#define MG112_17PL ~(1 << 6) +#else +#define MG112_17PL 0xFFFF +#endif +#if (G118PL >= G112PL) || (G118PL == 0) +#define MG112_18PL ~(1 << 7) +#else +#define MG112_18PL 0xFFFF +#endif +#define MG112_12PL 0x00FD +#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \ + MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL) +// End of MG112: + +// Beginning of MG113: +#if (G111PL >= G113PL) || (G111PL == 0) +#define MG113_11PL ~(1) +#else +#define MG113_11PL 0xFFFF +#endif +#if (G112PL >= G113PL) || (G112PL == 0) +#define MG113_12PL ~(1 << 1) +#else +#define MG113_12PL 0xFFFF +#endif +#if (G114PL >= G113PL) || (G114PL == 0) +#define MG113_14PL ~(1 << 3) +#else +#define MG113_14PL 0xFFFF +#endif +#if (G115PL >= G113PL) || (G115PL == 0) +#define MG113_15PL ~(1 << 4) +#else +#define MG113_15PL 0xFFFF +#endif +#if (G116PL >= G113PL) || (G116PL == 0) +#define MG113_16PL ~(1 << 5) +#else +#define MG113_16PL 0xFFFF +#endif +#if (G117PL >= G113PL) || (G117PL == 0) +#define MG113_17PL ~(1 << 6) +#else +#define MG113_17PL 0xFFFF +#endif +#if (G118PL >= G113PL) || (G118PL == 0) +#define MG113_18PL ~(1 << 7) +#else +#define MG113_18PL 0xFFFF +#endif +#define MG113_13PL 0x00FB +#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \ + MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL) +// End of MG113: + +// Beginning of MG114: +#if (G111PL >= G114PL) || (G111PL == 0) +#define MG114_11PL ~(1) +#else +#define MG114_11PL 0xFFFF +#endif +#if (G112PL >= G114PL) || (G112PL == 0) +#define MG114_12PL ~(1 << 1) +#else +#define MG114_12PL 0xFFFF +#endif +#if (G113PL >= G114PL) || (G113PL == 0) +#define MG114_13PL ~(1 << 2) +#else +#define MG114_13PL 0xFFFF +#endif +#if (G115PL >= G114PL) || (G115PL == 0) +#define MG114_15PL ~(1 << 4) +#else +#define MG114_15PL 0xFFFF +#endif +#if (G116PL >= G114PL) || (G116PL == 0) +#define MG114_16PL ~(1 << 5) +#else +#define MG114_16PL 0xFFFF +#endif +#if (G117PL >= G114PL) || (G117PL == 0) +#define MG114_17PL ~(1 << 6) +#else +#define MG114_17PL 0xFFFF +#endif +#if (G118PL >= G114PL) || (G118PL == 0) +#define MG114_18PL ~(1 << 7) +#else +#define MG114_18PL 0xFFFF +#endif +#define MG114_14PL 0x00F7 +#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \ + MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL) +// End of MG114: + +// Beginning of MG115: +#if (G111PL >= G115PL) || (G111PL == 0) +#define MG115_11PL ~(1) +#else +#define MG115_11PL 0xFFFF +#endif +#if (G112PL >= G115PL) || (G112PL == 0) +#define MG115_12PL ~(1 << 1) +#else +#define MG115_12PL 0xFFFF +#endif +#if (G113PL >= G115PL) || (G113PL == 0) +#define MG115_13PL ~(1 << 2) +#else +#define MG115_13PL 0xFFFF +#endif +#if (G114PL >= G115PL) || (G114PL == 0) +#define MG115_14PL ~(1 << 3) +#else +#define MG115_14PL 0xFFFF +#endif +#if (G116PL >= G115PL) || (G116PL == 0) +#define MG115_16PL ~(1 << 5) +#else +#define MG115_16PL 0xFFFF +#endif +#if (G117PL >= G115PL) || (G117PL == 0) +#define MG115_17PL ~(1 << 6) +#else +#define MG115_17PL 0xFFFF +#endif +#if (G118PL >= G115PL) || (G118PL == 0) +#define MG115_18PL ~(1 << 7) +#else +#define MG115_18PL 0xFFFF +#endif +#define MG115_15PL 0x00EF +#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \ + MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL) +// End of MG115: + +// Beginning of MG116: +#if (G111PL >= G116PL) || (G111PL == 0) +#define MG116_11PL ~(1) +#else +#define MG116_11PL 0xFFFF +#endif +#if (G112PL >= G116PL) || (G112PL == 0) +#define MG116_12PL ~(1 << 1) +#else +#define MG116_12PL 0xFFFF +#endif +#if (G113PL >= G116PL) || (G113PL == 0) +#define MG116_13PL ~(1 << 2) +#else +#define MG116_13PL 0xFFFF +#endif +#if (G114PL >= G116PL) || (G114PL == 0) +#define MG116_14PL ~(1 << 3) +#else +#define MG116_14PL 0xFFFF +#endif +#if (G115PL >= G116PL) || (G115PL == 0) +#define MG116_15PL ~(1 << 4) +#else +#define MG116_15PL 0xFFFF +#endif +#if (G117PL >= G116PL) || (G117PL == 0) +#define MG116_17PL ~(1 << 6) +#else +#define MG116_17PL 0xFFFF +#endif +#if (G118PL >= G116PL) || (G118PL == 0) +#define MG116_18PL ~(1 << 7) +#else +#define MG116_18PL 0xFFFF +#endif +#define MG116_16PL 0x00DF +#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \ + MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL) +// End of MG116: + +// Beginning of MG117: +#if (G111PL >= G117PL) || (G111PL == 0) +#define MG117_11PL ~(1) +#else +#define MG117_11PL 0xFFFF +#endif +#if (G112PL >= G117PL) || (G112PL == 0) +#define MG117_12PL ~(1 << 1) +#else +#define MG117_12PL 0xFFFF +#endif +#if (G113PL >= G117PL) || (G113PL == 0) +#define MG117_13PL ~(1 << 2) +#else +#define MG117_13PL 0xFFFF +#endif +#if (G114PL >= G117PL) || (G114PL == 0) +#define MG117_14PL ~(1 << 3) +#else +#define MG117_14PL 0xFFFF +#endif +#if (G115PL >= G117PL) || (G115PL == 0) +#define MG117_15PL ~(1 << 4) +#else +#define MG117_15PL 0xFFFF +#endif +#if (G116PL >= G117PL) || (G116PL == 0) +#define MG117_16PL ~(1 << 5) +#else +#define MG117_16PL 0xFFFF +#endif +#if (G118PL >= G117PL) || (G118PL == 0) +#define MG117_18PL ~(1 << 7) +#else +#define MG117_18PL 0xFFFF +#endif +#define MG117_17PL 0x00BF +#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \ + MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL) +// End of MG117: + +// Beginning of MG118: +#if (G111PL >= G118PL) || (G111PL == 0) +#define MG118_11PL ~(1) +#else +#define MG118_11PL 0xFFFF +#endif +#if (G112PL >= G118PL) || (G112PL == 0) +#define MG118_12PL ~(1 << 1) +#else +#define MG118_12PL 0xFFFF +#endif +#if (G113PL >= G118PL) || (G113PL == 0) +#define MG118_13PL ~(1 << 2) +#else +#define MG118_13PL 0xFFFF +#endif +#if (G114PL >= G118PL) || (G114PL == 0) +#define MG118_14PL ~(1 << 3) +#else +#define MG118_14PL 0xFFFF +#endif +#if (G115PL >= G118PL) || (G115PL == 0) +#define MG118_15PL ~(1 << 4) +#else +#define MG118_15PL 0xFFFF +#endif +#if (G116PL >= G118PL) || (G116PL == 0) +#define MG118_16PL ~(1 << 5) +#else +#define MG118_16PL 0xFFFF +#endif +#if (G117PL >= G118PL) || (G117PL == 0) +#define MG118_17PL ~(1 << 6) +#else +#define MG118_17PL 0xFFFF +#endif +#define MG118_18PL 0x007F +#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \ + MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL) +// End of MG118: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG121 to MG128: +// + +// Beginning of MG121: +#if (G122PL >= G121PL) || (G122PL == 0) +#define MG121_12PL ~(1 << 1) +#else +#define MG121_12PL 0xFFFF +#endif +#if (G123PL >= G121PL) || (G123PL == 0) +#define MG121_13PL ~(1 << 2) +#else +#define MG121_13PL 0xFFFF +#endif +#if (G124PL >= G121PL) || (G124PL == 0) +#define MG121_14PL ~(1 << 3) +#else +#define MG121_14PL 0xFFFF +#endif +#if (G125PL >= G121PL) || (G125PL == 0) +#define MG121_15PL ~(1 << 4) +#else +#define MG121_15PL 0xFFFF +#endif +#if (G126PL >= G121PL) || (G126PL == 0) +#define MG121_16PL ~(1 << 5) +#else +#define MG121_16PL 0xFFFF +#endif +#if (G127PL >= G121PL) || (G127PL == 0) +#define MG121_17PL ~(1 << 6) +#else +#define MG121_17PL 0xFFFF +#endif +#if (G128PL >= G121PL) || (G128PL == 0) +#define MG121_18PL ~(1 << 7) +#else +#define MG121_18PL 0xFFFF +#endif +#define MG121_11PL 0x00FE +#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \ + MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL) +// End of MG121: + +// Beginning of MG121: +#if (G121PL >= G122PL) || (G121PL == 0) +#define MG122_11PL ~(1) +#else +#define MG122_11PL 0xFFFF +#endif +#if (G123PL >= G122PL) || (G123PL == 0) +#define MG122_13PL ~(1 << 2) +#else +#define MG122_13PL 0xFFFF +#endif +#if (G124PL >= G122PL) || (G124PL == 0) +#define MG122_14PL ~(1 << 3) +#else +#define MG122_14PL 0xFFFF +#endif +#if (G125PL >= G122PL) || (G125PL == 0) +#define MG122_15PL ~(1 << 4) +#else +#define MG122_15PL 0xFFFF +#endif +#if (G126PL >= G122PL) || (G126PL == 0) +#define MG122_16PL ~(1 << 5) +#else +#define MG122_16PL 0xFFFF +#endif +#if (G127PL >= G122PL) || (G127PL == 0) +#define MG122_17PL ~(1 << 6) +#else +#define MG122_17PL 0xFFFF +#endif +#if (G128PL >= G122PL) || (G128PL == 0) +#define MG122_18PL ~(1 << 7) +#else +#define MG122_18PL 0xFFFF +#endif +#define MG122_12PL 0x00FD +#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \ + MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL) +// End of MG122: + +// Beginning of MG123: +#if (G121PL >= G123PL) || (G121PL == 0) +#define MG123_11PL ~(1) +#else +#define MG123_11PL 0xFFFF +#endif +#if (G122PL >= G123PL) || (G122PL == 0) +#define MG123_12PL ~(1 << 1) +#else +#define MG123_12PL 0xFFFF +#endif +#if (G124PL >= G123PL) || (G124PL == 0) +#define MG123_14PL ~(1 << 3) +#else +#define MG123_14PL 0xFFFF +#endif +#if (G125PL >= G123PL) || (G125PL == 0) +#define MG123_15PL ~(1 << 4) +#else +#define MG123_15PL 0xFFFF +#endif +#if (G126PL >= G123PL) || (G126PL == 0) +#define MG123_16PL ~(1 << 5) +#else +#define MG123_16PL 0xFFFF +#endif +#if (G127PL >= G123PL) || (G127PL == 0) +#define MG123_17PL ~(1 << 6) +#else +#define MG123_17PL 0xFFFF +#endif +#if (G128PL >= G123PL) || (G128PL == 0) +#define MG123_18PL ~(1 << 7) +#else +#define MG123_18PL 0xFFFF +#endif +#define MG123_13PL 0x00FB +#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \ + MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL) +// End of MG123: + +// Beginning of MG124: +#if (G121PL >= G124PL) || (G121PL == 0) +#define MG124_11PL ~(1) +#else +#define MG124_11PL 0xFFFF +#endif +#if (G122PL >= G124PL) || (G122PL == 0) +#define MG124_12PL ~(1 << 1) +#else +#define MG124_12PL 0xFFFF +#endif +#if (G123PL >= G124PL) || (G123PL == 0) +#define MG124_13PL ~(1 << 2) +#else +#define MG124_13PL 0xFFFF +#endif +#if (G125PL >= G124PL) || (G125PL == 0) +#define MG124_15PL ~(1 << 4) +#else +#define MG124_15PL 0xFFFF +#endif +#if (G126PL >= G124PL) || (G126PL == 0) +#define MG124_16PL ~(1 << 5) +#else +#define MG124_16PL 0xFFFF +#endif +#if (G127PL >= G124PL) || (G127PL == 0) +#define MG124_17PL ~(1 << 6) +#else +#define MG124_17PL 0xFFFF +#endif +#if (G128PL >= G124PL) || (G128PL == 0) +#define MG124_18PL ~(1 << 7) +#else +#define MG124_18PL 0xFFFF +#endif +#define MG124_14PL 0x00F7 +#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \ + MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL) +// End of MG124: + +// Beginning of MG125: +#if (G121PL >= G125PL) || (G121PL == 0) +#define MG125_11PL ~(1) +#else +#define MG125_11PL 0xFFFF +#endif +#if (G122PL >= G125PL) || (G122PL == 0) +#define MG125_12PL ~(1 << 1) +#else +#define MG125_12PL 0xFFFF +#endif +#if (G123PL >= G125PL) || (G123PL == 0) +#define MG125_13PL ~(1 << 2) +#else +#define MG125_13PL 0xFFFF +#endif +#if (G124PL >= G125PL) || (G124PL == 0) +#define MG125_14PL ~(1 << 3) +#else +#define MG125_14PL 0xFFFF +#endif +#if (G126PL >= G125PL) || (G126PL == 0) +#define MG125_16PL ~(1 << 5) +#else +#define MG125_16PL 0xFFFF +#endif +#if (G127PL >= G125PL) || (G127PL == 0) +#define MG125_17PL ~(1 << 6) +#else +#define MG125_17PL 0xFFFF +#endif +#if (G128PL >= G125PL) || (G128PL == 0) +#define MG125_18PL ~(1 << 7) +#else +#define MG125_18PL 0xFFFF +#endif +#define MG125_15PL 0x00EF +#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \ + MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL) +// End of MG125: + +// Beginning of MG126: +#if (G121PL >= G126PL) || (G121PL == 0) +#define MG126_11PL ~(1) +#else +#define MG126_11PL 0xFFFF +#endif +#if (G122PL >= G126PL) || (G122PL == 0) +#define MG126_12PL ~(1 << 1) +#else +#define MG126_12PL 0xFFFF +#endif +#if (G123PL >= G126PL) || (G123PL == 0) +#define MG126_13PL ~(1 << 2) +#else +#define MG126_13PL 0xFFFF +#endif +#if (G124PL >= G126PL) || (G124PL == 0) +#define MG126_14PL ~(1 << 3) +#else +#define MG126_14PL 0xFFFF +#endif +#if (G125PL >= G126PL) || (G125PL == 0) +#define MG126_15PL ~(1 << 4) +#else +#define MG126_15PL 0xFFFF +#endif +#if (G127PL >= G126PL) || (G127PL == 0) +#define MG126_17PL ~(1 << 6) +#else +#define MG126_17PL 0xFFFF +#endif +#if (G128PL >= G126PL) || (G128PL == 0) +#define MG126_18PL ~(1 << 7) +#else +#define MG126_18PL 0xFFFF +#endif +#define MG126_16PL 0x00DF +#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \ + MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL) +// End of MG126: + +// Beginning of MG127: +#if (G121PL >= G127PL) || (G121PL == 0) +#define MG127_11PL ~(1) +#else +#define MG127_11PL 0xFFFF +#endif +#if (G122PL >= G127PL) || (G122PL == 0) +#define MG127_12PL ~(1 << 1) +#else +#define MG127_12PL 0xFFFF +#endif +#if (G123PL >= G127PL) || (G123PL == 0) +#define MG127_13PL ~(1 << 2) +#else +#define MG127_13PL 0xFFFF +#endif +#if (G124PL >= G127PL) || (G124PL == 0) +#define MG127_14PL ~(1 << 3) +#else +#define MG127_14PL 0xFFFF +#endif +#if (G125PL >= G127PL) || (G125PL == 0) +#define MG127_15PL ~(1 << 4) +#else +#define MG127_15PL 0xFFFF +#endif +#if (G126PL >= G127PL) || (G126PL == 0) +#define MG127_16PL ~(1 << 5) +#else +#define MG127_16PL 0xFFFF +#endif +#if (G128PL >= G127PL) || (G128PL == 0) +#define MG127_18PL ~(1 << 7) +#else +#define MG127_18PL 0xFFFF +#endif +#define MG127_17PL 0x00BF +#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \ + MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL) +// End of MG127: + +// Beginning of MG128: +#if (G121PL >= G128PL) || (G121PL == 0) +#define MG128_11PL ~(1) +#else +#define MG128_11PL 0xFFFF +#endif +#if (G122PL >= G128PL) || (G122PL == 0) +#define MG128_12PL ~(1 << 1) +#else +#define MG128_12PL 0xFFFF +#endif +#if (G123PL >= G128PL) || (G123PL == 0) +#define MG128_13PL ~(1 << 2) +#else +#define MG128_13PL 0xFFFF +#endif +#if (G124PL >= G128PL) || (G124PL == 0) +#define MG128_14PL ~(1 << 3) +#else +#define MG128_14PL 0xFFFF +#endif +#if (G125PL >= G128PL) || (G125PL == 0) +#define MG128_15PL ~(1 << 4) +#else +#define MG128_15PL 0xFFFF +#endif +#if (G126PL >= G128PL) || (G126PL == 0) +#define MG128_16PL ~(1 << 5) +#else +#define MG128_16PL 0xFFFF +#endif +#if (G127PL >= G128PL) || (G127PL == 0) +#define MG128_17PL ~(1 << 6) +#else +#define MG128_17PL 0xFFFF +#endif +#define MG128_18PL 0x007F +#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \ + MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL) +// End of MG128: + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP28x_Project.h b/v120/DSP2833x_common/include/DSP28x_Project.h new file mode 100644 index 0000000..399c1db --- /dev/null +++ b/v120/DSP2833x_common/include/DSP28x_Project.h @@ -0,0 +1,22 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/v120/DSP2833x_common/include/IQmathLib.h b/v120/DSP2833x_common/include/IQmathLib.h new file mode 100644 index 0000000..b62ddf8 --- /dev/null +++ b/v120/DSP2833x_common/include/IQmathLib.h @@ -0,0 +1,4493 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: July 10, 2008 10:59:52 $ +//########################################################################### +// +// FILE: IQmathLib.h +// +// TITLE: IQ Math library functions definitions. +// +//########################################################################### +// +// Ver | dd-mmm-yyyy | Who | Description of changes +// =====|=============|=======|============================================== +// 1.3 | 19 Nov 2001 | A. T. | Original Release. +// -----|-------------|-------|---------------------------------------------- +// 1.4 | 17 May 2002 | A. T. | Added new functions and support for +// | | | intrinsics IQmpy, IQxmpy, IQsat. +// -----|-------------|-------|---------------------------------------------- +// 1.4a| 12 Jun 2002 | A. T. | Fixed problem with _IQ() operation on +// | | | variables. +// -----|-------------|-------|---------------------------------------------- +// 1.4b| 18 Jun 2002 | A. T. | Fixed bug with _IQtoIQN() and _IQNtoIQ() +// | | | operations. +// -----|-------------|-------|---------------------------------------------- +// 1.4d| 30 Mar 2003 | DA/SD | 1. Added macro parameters in parentheses +// | | | in number of places where it matters +// | | | 2. Added macro definition to include header +// | | | file multiple times in the program. +// -----|-------------|-------|---------------------------------------------- +// 1.4e| 17 Jun 2004 | AT/DA | Added IQexp function. +// | | | Added IQasin & IQacos functions (thanks DA). +// -----|-------------|-------|---------------------------------------------- +// 1.4f| 10 Mar 2005 | AT | Fixed Bug In IQexp function. +// -----|-------------|-------|---------------------------------------------- +// 1.5 | 30 Jan 2008 | LH | 1. Changed the definion of the _IQatan2PU(A,B) +// | | | macro for FLOAT_MATH so that a call to +// | | | divide will not occur. +// | | | 2. If MATH_TYPE == FLOAT_MATH, then include the +// | | | following standard headers: math.h +// | | | stdlib.h. +// | | | 3. Added missing #defines for the non-global +// | | | _IQatanN() function +// | | | 4. Adding missing definitions for absolute +// | | | value when MATH_TYPE == FLOAT_MATH +// | | | 5. Included limits.h and changed the definition +// | | | of MAX_IQ_NEG to LONG_MIN and MAX_IQ_POS +// | | | to LONG_MAX +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +// +// User needs to configure "MATH_TYPE" and "GLOBAL_Q" values: +// +//--------------------------------------------------------------------------- +// Select math type, IQ_MATH or FLOAT_MATH: +// + +#ifndef __IQMATHLIB_H_INCLUDED__ +#define __IQMATHLIB_H_INCLUDED__ + + +#define FLOAT_MATH 1 +#define IQ_MATH 0 + +#ifndef MATH_TYPE +#define MATH_TYPE IQ_MATH +#endif + +//--------------------------------------------------------------------------- +// Select global Q value and scaling. The Q value is limited to the +// following range for all functions: +// +// 30 <= GLOBAL_Q <= 1 +// +#ifndef GLOBAL_Q +#define GLOBAL_Q 24 +#endif + +//--------------------------------------------------------------------------- +// If using FLOAT_MATH, include standard headers to avoid conversion issues +// +#if MATH_TYPE == FLOAT_MATH +#include +#include +#endif +#include + +//--------------------------------------------------------------------------- +// Various Usefull Constant Definitions: +// +#define QG GLOBAL_Q +#define Q30 30 +#define Q29 29 +#define Q28 28 +#define Q27 27 +#define Q26 26 +#define Q25 25 +#define Q24 24 +#define Q23 23 +#define Q22 22 +#define Q21 21 +#define Q20 20 +#define Q19 19 +#define Q18 18 +#define Q17 17 +#define Q16 16 +#define Q15 15 +#define Q14 14 +#define Q13 13 +#define Q12 12 +#define Q11 11 +#define Q10 10 +#define Q9 9 +#define Q8 8 +#define Q7 7 +#define Q6 6 +#define Q5 5 +#define Q4 4 +#define Q3 3 +#define Q2 2 +#define Q1 1 + +#define MAX_IQ_POS LONG_MAX +#define MAX_IQ_NEG LONG_MIN +#define MIN_IQ_POS 1 +#define MIN_IQ_NEG -1 + +//########################################################################### +#if MATH_TYPE == IQ_MATH +//########################################################################### +// If IQ_MATH is used, the following IQmath library function definitions +// are used: +//=========================================================================== +typedef long _iq; +typedef long _iq30; +typedef long _iq29; +typedef long _iq28; +typedef long _iq27; +typedef long _iq26; +typedef long _iq25; +typedef long _iq24; +typedef long _iq23; +typedef long _iq22; +typedef long _iq21; +typedef long _iq20; +typedef long _iq19; +typedef long _iq18; +typedef long _iq17; +typedef long _iq16; +typedef long _iq15; +typedef long _iq14; +typedef long _iq13; +typedef long _iq12; +typedef long _iq11; +typedef long _iq10; +typedef long _iq9; +typedef long _iq8; +typedef long _iq7; +typedef long _iq6; +typedef long _iq5; +typedef long _iq4; +typedef long _iq3; +typedef long _iq2; +typedef long _iq1; +//--------------------------------------------------------------------------- +#define _IQ30(A) (long) ((A) * 1073741824.0L) +#define _IQ29(A) (long) ((A) * 536870912.0L) +#define _IQ28(A) (long) ((A) * 268435456.0L) +#define _IQ27(A) (long) ((A) * 134217728.0L) +#define _IQ26(A) (long) ((A) * 67108864.0L) +#define _IQ25(A) (long) ((A) * 33554432.0L) +#define _IQ24(A) (long) ((A) * 16777216.0L) +#define _IQ23(A) (long) ((A) * 8388608.0L) +#define _IQ22(A) (long) ((A) * 4194304.0L) +#define _IQ21(A) (long) ((A) * 2097152.0L) +#define _IQ20(A) (long) ((A) * 1048576.0L) +#define _IQ19(A) (long) ((A) * 524288.0L) +#define _IQ18(A) (long) ((A) * 262144.0L) +#define _IQ17(A) (long) ((A) * 131072.0L) +#define _IQ16(A) (long) ((A) * 65536.0L) +#define _IQ15(A) (long) ((A) * 32768.0L) +#define _IQ14(A) (long) ((A) * 16384.0L) +#define _IQ13(A) (long) ((A) * 8192.0L) +#define _IQ12(A) (long) ((A) * 4096.0L) +#define _IQ11(A) (long) ((A) * 2048.0L) +#define _IQ10(A) (long) ((A) * 1024.0L) +#define _IQ9(A) (long) ((A) * 512.0L) +#define _IQ8(A) (long) ((A) * 256.0L) +#define _IQ7(A) (long) ((A) * 128.0L) +#define _IQ6(A) (long) ((A) * 64.0L) +#define _IQ5(A) (long) ((A) * 32.0L) +#define _IQ4(A) (long) ((A) * 16.0L) +#define _IQ3(A) (long) ((A) * 8.0L) +#define _IQ2(A) (long) ((A) * 4.0L) +#define _IQ1(A) (long) ((A) * 2.0L) + +#if GLOBAL_Q == 30 +#define _IQ(A) _IQ30(A) +#endif +#if GLOBAL_Q == 29 +#define _IQ(A) _IQ29(A) +#endif +#if GLOBAL_Q == 28 +#define _IQ(A) _IQ28(A) +#endif +#if GLOBAL_Q == 27 +#define _IQ(A) _IQ27(A) +#endif +#if GLOBAL_Q == 26 +#define _IQ(A) _IQ26(A) +#endif +#if GLOBAL_Q == 25 +#define _IQ(A) _IQ25(A) +#endif +#if GLOBAL_Q == 24 +#define _IQ(A) _IQ24(A) +#endif +#if GLOBAL_Q == 23 +#define _IQ(A) _IQ23(A) +#endif +#if GLOBAL_Q == 22 +#define _IQ(A) _IQ22(A) +#endif +#if GLOBAL_Q == 21 +#define _IQ(A) _IQ21(A) +#endif +#if GLOBAL_Q == 20 +#define _IQ(A) _IQ20(A) +#endif +#if GLOBAL_Q == 19 +#define _IQ(A) _IQ19(A) +#endif +#if GLOBAL_Q == 18 +#define _IQ(A) _IQ18(A) +#endif +#if GLOBAL_Q == 17 +#define _IQ(A) _IQ17(A) +#endif +#if GLOBAL_Q == 16 +#define _IQ(A) _IQ16(A) +#endif +#if GLOBAL_Q == 15 +#define _IQ(A) _IQ15(A) +#endif +#if GLOBAL_Q == 14 +#define _IQ(A) _IQ14(A) +#endif +#if GLOBAL_Q == 13 +#define _IQ(A) _IQ13(A) +#endif +#if GLOBAL_Q == 12 +#define _IQ(A) _IQ12(A) +#endif +#if GLOBAL_Q == 11 +#define _IQ(A) _IQ11(A) +#endif +#if GLOBAL_Q == 10 +#define _IQ(A) _IQ10(A) +#endif +#if GLOBAL_Q == 9 +#define _IQ(A) _IQ9(A) +#endif +#if GLOBAL_Q == 8 +#define _IQ(A) _IQ8(A) +#endif +#if GLOBAL_Q == 7 +#define _IQ(A) _IQ7(A) +#endif +#if GLOBAL_Q == 6 +#define _IQ(A) _IQ6(A) +#endif +#if GLOBAL_Q == 5 +#define _IQ(A) _IQ5(A) +#endif +#if GLOBAL_Q == 4 +#define _IQ(A) _IQ4(A) +#endif +#if GLOBAL_Q == 3 +#define _IQ(A) _IQ3(A) +#endif +#if GLOBAL_Q == 2 +#define _IQ(A) _IQ2(A) +#endif +#if GLOBAL_Q == 1 +#define _IQ(A) _IQ1(A) +#endif +//--------------------------------------------------------------------------- +extern float _IQ30toF(long A); +extern float _IQ29toF(long A); +extern float _IQ28toF(long A); +extern float _IQ27toF(long A); +extern float _IQ26toF(long A); +extern float _IQ25toF(long A); +extern float _IQ24toF(long A); +extern float _IQ23toF(long A); +extern float _IQ22toF(long A); +extern float _IQ21toF(long A); +extern float _IQ20toF(long A); +extern float _IQ19toF(long A); +extern float _IQ18toF(long A); +extern float _IQ17toF(long A); +extern float _IQ16toF(long A); +extern float _IQ15toF(long A); +extern float _IQ14toF(long A); +extern float _IQ13toF(long A); +extern float _IQ12toF(long A); +extern float _IQ11toF(long A); +extern float _IQ10toF(long A); +extern float _IQ9toF(long A); +extern float _IQ8toF(long A); +extern float _IQ7toF(long A); +extern float _IQ6toF(long A); +extern float _IQ5toF(long A); +extern float _IQ4toF(long A); +extern float _IQ3toF(long A); +extern float _IQ2toF(long A); +extern float _IQ1toF(long A); + +#if GLOBAL_Q == 30 +#define _IQtoF(A) _IQ30toF(A) +#endif +#if GLOBAL_Q == 29 +#define _IQtoF(A) _IQ29toF(A) +#endif +#if GLOBAL_Q == 28 +#define _IQtoF(A) _IQ28toF(A) +#endif +#if GLOBAL_Q == 27 +#define _IQtoF(A) _IQ27toF(A) +#endif +#if GLOBAL_Q == 26 +#define _IQtoF(A) _IQ26toF(A) +#endif +#if GLOBAL_Q == 25 +#define _IQtoF(A) _IQ25toF(A) +#endif +#if GLOBAL_Q == 24 +#define _IQtoF(A) _IQ24toF(A) +#endif +#if GLOBAL_Q == 23 +#define _IQtoF(A) _IQ23toF(A) +#endif +#if GLOBAL_Q == 22 +#define _IQtoF(A) _IQ22toF(A) +#endif +#if GLOBAL_Q == 21 +#define _IQtoF(A) _IQ21toF(A) +#endif +#if GLOBAL_Q == 20 +#define _IQtoF(A) _IQ20toF(A) +#endif +#if GLOBAL_Q == 19 +#define _IQtoF(A) _IQ19toF(A) +#endif +#if GLOBAL_Q == 18 +#define _IQtoF(A) _IQ18toF(A) +#endif +#if GLOBAL_Q == 17 +#define _IQtoF(A) _IQ17toF(A) +#endif +#if GLOBAL_Q == 16 +#define _IQtoF(A) _IQ16toF(A) +#endif +#if GLOBAL_Q == 15 +#define _IQtoF(A) _IQ15toF(A) +#endif +#if GLOBAL_Q == 14 +#define _IQtoF(A) _IQ14toF(A) +#endif +#if GLOBAL_Q == 13 +#define _IQtoF(A) _IQ13toF(A) +#endif +#if GLOBAL_Q == 12 +#define _IQtoF(A) _IQ12toF(A) +#endif +#if GLOBAL_Q == 11 +#define _IQtoF(A) _IQ11toF(A) +#endif +#if GLOBAL_Q == 10 +#define _IQtoF(A) _IQ10toF(A) +#endif +#if GLOBAL_Q == 9 +#define _IQtoF(A) _IQ9toF(A) +#endif +#if GLOBAL_Q == 8 +#define _IQtoF(A) _IQ8toF(A) +#endif +#if GLOBAL_Q == 7 +#define _IQtoF(A) _IQ7toF(A) +#endif +#if GLOBAL_Q == 6 +#define _IQtoF(A) _IQ6toF(A) +#endif +#if GLOBAL_Q == 5 +#define _IQtoF(A) _IQ5toF(A) +#endif +#if GLOBAL_Q == 4 +#define _IQtoF(A) _IQ4toF(A) +#endif +#if GLOBAL_Q == 3 +#define _IQtoF(A) _IQ3toF(A) +#endif +#if GLOBAL_Q == 2 +#define _IQtoF(A) _IQ2toF(A) +#endif +#if GLOBAL_Q == 1 +#define _IQtoF(A) _IQ1toF(A) +#endif +//--------------------------------------------------------------------------- +#define _IQsat(A, Pos, Neg) __IQsat(A, Pos, Neg) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) ((long) (A) << (30 - GLOBAL_Q)) +#define _IQ30toIQ(A) ((long) (A) >> (30 - GLOBAL_Q)) + +#if (GLOBAL_Q >= 29) +#define _IQtoIQ29(A) ((long) (A) >> (GLOBAL_Q - 29)) +#define _IQ29toIQ(A) ((long) (A) << (GLOBAL_Q - 29)) +#else +#define _IQtoIQ29(A) ((long) (A) << (29 - GLOBAL_Q)) +#define _IQ29toIQ(A) ((long) (A) >> (29 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 28) +#define _IQtoIQ28(A) ((long) (A) >> (GLOBAL_Q - 28)) +#define _IQ28toIQ(A) ((long) (A) << (GLOBAL_Q - 28)) +#else +#define _IQtoIQ28(A) ((long) (A) << (28 - GLOBAL_Q)) +#define _IQ28toIQ(A) ((long) (A) >> (28 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 27) +#define _IQtoIQ27(A) ((long) (A) >> (GLOBAL_Q - 27)) +#define _IQ27toIQ(A) ((long) (A) << (GLOBAL_Q - 27)) +#else +#define _IQtoIQ27(A) ((long) (A) << (27 - GLOBAL_Q)) +#define _IQ27toIQ(A) ((long) (A) >> (27 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 26) +#define _IQtoIQ26(A) ((long) (A) >> (GLOBAL_Q - 26)) +#define _IQ26toIQ(A) ((long) (A) << (GLOBAL_Q - 26)) +#else +#define _IQtoIQ26(A) ((long) (A) << (26 - GLOBAL_Q)) +#define _IQ26toIQ(A) ((long) (A) >> (26 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 25) +#define _IQtoIQ25(A) ((long) (A) >> (GLOBAL_Q - 25)) +#define _IQ25toIQ(A) ((long) (A) << (GLOBAL_Q - 25)) +#else +#define _IQtoIQ25(A) ((long) (A) << (25 - GLOBAL_Q)) +#define _IQ25toIQ(A) ((long) (A) >> (25 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 24) +#define _IQtoIQ24(A) ((long) (A) >> (GLOBAL_Q - 24)) +#define _IQ24toIQ(A) ((long) (A) << (GLOBAL_Q - 24)) +#else +#define _IQtoIQ24(A) ((long) (A) << (24 - GLOBAL_Q)) +#define _IQ24toIQ(A) ((long) (A) >> (24 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 23) +#define _IQtoIQ23(A) ((long) (A) >> (GLOBAL_Q - 23)) +#define _IQ23toIQ(A) ((long) (A) << (GLOBAL_Q - 23)) +#else +#define _IQtoIQ23(A) ((long) (A) << (23 - GLOBAL_Q)) +#define _IQ23toIQ(A) ((long) (A) >> (23 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 22) +#define _IQtoIQ22(A) ((long) (A) >> (GLOBAL_Q - 22)) +#define _IQ22toIQ(A) ((long) (A) << (GLOBAL_Q - 22)) +#else +#define _IQtoIQ22(A) ((long) (A) << (22 - GLOBAL_Q)) +#define _IQ22toIQ(A) ((long) (A) >> (22 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 21) +#define _IQtoIQ21(A) ((long) (A) >> (GLOBAL_Q - 21)) +#define _IQ21toIQ(A) ((long) (A) << (GLOBAL_Q - 21)) +#else +#define _IQtoIQ21(A) ((long) (A) << (21 - GLOBAL_Q)) +#define _IQ21toIQ(A) ((long) (A) >> (21 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 20) +#define _IQtoIQ20(A) ((long) (A) >> (GLOBAL_Q - 20)) +#define _IQ20toIQ(A) ((long) (A) << (GLOBAL_Q - 20)) +#else +#define _IQtoIQ20(A) ((long) (A) << (20 - GLOBAL_Q)) +#define _IQ20toIQ(A) ((long) (A) >> (20 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 19) +#define _IQtoIQ19(A) ((long) (A) >> (GLOBAL_Q - 19)) +#define _IQ19toIQ(A) ((long) (A) << (GLOBAL_Q - 19)) +#else +#define _IQtoIQ19(A) ((long) (A) << (19 - GLOBAL_Q)) +#define _IQ19toIQ(A) ((long) (A) >> (19 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 18) +#define _IQtoIQ18(A) ((long) (A) >> (GLOBAL_Q - 18)) +#define _IQ18toIQ(A) ((long) (A) << (GLOBAL_Q - 18)) +#else +#define _IQtoIQ18(A) ((long) (A) << (18 - GLOBAL_Q)) +#define _IQ18toIQ(A) ((long) (A) >> (18 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 17) +#define _IQtoIQ17(A) ((long) (A) >> (GLOBAL_Q - 17)) +#define _IQ17toIQ(A) ((long) (A) << (GLOBAL_Q - 17)) +#else +#define _IQtoIQ17(A) ((long) (A) << (17 - GLOBAL_Q)) +#define _IQ17toIQ(A) ((long) (A) >> (17 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 16) +#define _IQtoIQ16(A) ((long) (A) >> (GLOBAL_Q - 16)) +#define _IQ16toIQ(A) ((long) (A) << (GLOBAL_Q - 16)) +#else +#define _IQtoIQ16(A) ((long) (A) << (16 - GLOBAL_Q)) +#define _IQ16toIQ(A) ((long) (A) >> (16 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 15) +#define _IQtoIQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _IQ15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#define _IQtoQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _Q15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#else +#define _IQtoIQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _IQ15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#define _IQtoQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _Q15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 14) +#define _IQtoIQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _IQ14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#define _IQtoQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _Q14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#else +#define _IQtoIQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _IQ14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#define _IQtoQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _Q14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 13) +#define _IQtoIQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _IQ13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#define _IQtoQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _Q13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#else +#define _IQtoIQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _IQ13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#define _IQtoQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _Q13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 12) +#define _IQtoIQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _IQ12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#define _IQtoQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _Q12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#else +#define _IQtoIQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _IQ12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#define _IQtoQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _Q12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 11) +#define _IQtoIQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _IQ11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#define _IQtoQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _Q11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#else +#define _IQtoIQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _IQ11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#define _IQtoQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _Q11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 10) +#define _IQtoIQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _IQ10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#define _IQtoQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _Q10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#else +#define _IQtoIQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _IQ10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#define _IQtoQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _Q10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 9) +#define _IQtoIQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _IQ9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#define _IQtoQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _Q9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#else +#define _IQtoIQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _IQ9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#define _IQtoQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _Q9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 8) +#define _IQtoIQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _IQ8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#define _IQtoQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _Q8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#else +#define _IQtoIQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _IQ8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#define _IQtoQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _Q8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 7) +#define _IQtoIQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _IQ7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#define _IQtoQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _Q7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#else +#define _IQtoIQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _IQ7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#define _IQtoQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _Q7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 6) +#define _IQtoIQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _IQ6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#define _IQtoQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _Q6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#else +#define _IQtoIQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _IQ6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#define _IQtoQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _Q6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 5) +#define _IQtoIQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _IQ5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#define _IQtoQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _Q5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#else +#define _IQtoIQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _IQ5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#define _IQtoQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _Q5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 4) +#define _IQtoIQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _IQ4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#define _IQtoQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _Q4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#else +#define _IQtoIQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _IQ4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#define _IQtoQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _Q4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 3) +#define _IQtoIQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _IQ3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#define _IQtoQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _Q3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#else +#define _IQtoIQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _IQ3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#define _IQtoQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _Q3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 2) +#define _IQtoIQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _IQ2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#define _IQtoQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _Q2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#else +#define _IQtoIQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _IQ2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#define _IQtoQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _Q2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 1) +#define _IQtoQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _Q1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +#else +#define _IQtoQ1(A) ((long) (A) << (1 - GLOBAL_Q)) +#define _Q1toIQ(A) ((long) (A) >> (1 - GLOBAL_Q)) +#endif + +#define _IQtoIQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _IQ1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) __IQmpy(A,B,GLOBAL_Q) +#define _IQ30mpy(A,B) __IQmpy(A,B,30) +#define _IQ29mpy(A,B) __IQmpy(A,B,29) +#define _IQ28mpy(A,B) __IQmpy(A,B,28) +#define _IQ27mpy(A,B) __IQmpy(A,B,27) +#define _IQ26mpy(A,B) __IQmpy(A,B,26) +#define _IQ25mpy(A,B) __IQmpy(A,B,25) +#define _IQ24mpy(A,B) __IQmpy(A,B,24) +#define _IQ23mpy(A,B) __IQmpy(A,B,23) +#define _IQ22mpy(A,B) __IQmpy(A,B,22) +#define _IQ21mpy(A,B) __IQmpy(A,B,21) +#define _IQ20mpy(A,B) __IQmpy(A,B,20) +#define _IQ19mpy(A,B) __IQmpy(A,B,19) +#define _IQ18mpy(A,B) __IQmpy(A,B,18) +#define _IQ17mpy(A,B) __IQmpy(A,B,17) +#define _IQ16mpy(A,B) __IQmpy(A,B,16) +#define _IQ15mpy(A,B) __IQmpy(A,B,15) +#define _IQ14mpy(A,B) __IQmpy(A,B,14) +#define _IQ13mpy(A,B) __IQmpy(A,B,13) +#define _IQ12mpy(A,B) __IQmpy(A,B,12) +#define _IQ11mpy(A,B) __IQmpy(A,B,11) +#define _IQ10mpy(A,B) __IQmpy(A,B,10) +#define _IQ9mpy(A,B) __IQmpy(A,B,9) +#define _IQ8mpy(A,B) __IQmpy(A,B,8) +#define _IQ7mpy(A,B) __IQmpy(A,B,7) +#define _IQ6mpy(A,B) __IQmpy(A,B,6) +#define _IQ5mpy(A,B) __IQmpy(A,B,5) +#define _IQ4mpy(A,B) __IQmpy(A,B,4) +#define _IQ3mpy(A,B) __IQmpy(A,B,3) +#define _IQ2mpy(A,B) __IQmpy(A,B,2) +#define _IQ1mpy(A,B) __IQmpy(A,B,1) +//--------------------------------------------------------------------------- +extern long _IQ30rmpy(long A, long B); +extern long _IQ29rmpy(long A, long B); +extern long _IQ28rmpy(long A, long B); +extern long _IQ27rmpy(long A, long B); +extern long _IQ26rmpy(long A, long B); +extern long _IQ25rmpy(long A, long B); +extern long _IQ24rmpy(long A, long B); +extern long _IQ23rmpy(long A, long B); +extern long _IQ22rmpy(long A, long B); +extern long _IQ21rmpy(long A, long B); +extern long _IQ20rmpy(long A, long B); +extern long _IQ19rmpy(long A, long B); +extern long _IQ18rmpy(long A, long B); +extern long _IQ17rmpy(long A, long B); +extern long _IQ16rmpy(long A, long B); +extern long _IQ15rmpy(long A, long B); +extern long _IQ14rmpy(long A, long B); +extern long _IQ13rmpy(long A, long B); +extern long _IQ12rmpy(long A, long B); +extern long _IQ11rmpy(long A, long B); +extern long _IQ10rmpy(long A, long B); +extern long _IQ9rmpy(long A, long B); +extern long _IQ8rmpy(long A, long B); +extern long _IQ7rmpy(long A, long B); +extern long _IQ6rmpy(long A, long B); +extern long _IQ5rmpy(long A, long B); +extern long _IQ4rmpy(long A, long B); +extern long _IQ3rmpy(long A, long B); +extern long _IQ2rmpy(long A, long B); +extern long _IQ1rmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrmpy(A,B) _IQ30rmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrmpy(A,B) _IQ29rmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrmpy(A,B) _IQ28rmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrmpy(A,B) _IQ27rmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrmpy(A,B) _IQ26rmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrmpy(A,B) _IQ25rmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrmpy(A,B) _IQ24rmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrmpy(A,B) _IQ23rmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrmpy(A,B) _IQ22rmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrmpy(A,B) _IQ21rmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrmpy(A,B) _IQ20rmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrmpy(A,B) _IQ19rmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrmpy(A,B) _IQ18rmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrmpy(A,B) _IQ17rmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrmpy(A,B) _IQ16rmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrmpy(A,B) _IQ15rmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrmpy(A,B) _IQ14rmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrmpy(A,B) _IQ13rmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrmpy(A,B) _IQ12rmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrmpy(A,B) _IQ11rmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrmpy(A,B) _IQ10rmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrmpy(A,B) _IQ9rmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrmpy(A,B) _IQ8rmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrmpy(A,B) _IQ7rmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrmpy(A,B) _IQ6rmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrmpy(A,B) _IQ5rmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrmpy(A,B) _IQ4rmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrmpy(A,B) _IQ3rmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrmpy(A,B) _IQ2rmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrmpy(A,B) _IQ1rmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30rsmpy(long A, long B); +extern long _IQ29rsmpy(long A, long B); +extern long _IQ28rsmpy(long A, long B); +extern long _IQ27rsmpy(long A, long B); +extern long _IQ26rsmpy(long A, long B); +extern long _IQ25rsmpy(long A, long B); +extern long _IQ24rsmpy(long A, long B); +extern long _IQ23rsmpy(long A, long B); +extern long _IQ22rsmpy(long A, long B); +extern long _IQ21rsmpy(long A, long B); +extern long _IQ20rsmpy(long A, long B); +extern long _IQ19rsmpy(long A, long B); +extern long _IQ18rsmpy(long A, long B); +extern long _IQ17rsmpy(long A, long B); +extern long _IQ16rsmpy(long A, long B); +extern long _IQ15rsmpy(long A, long B); +extern long _IQ14rsmpy(long A, long B); +extern long _IQ13rsmpy(long A, long B); +extern long _IQ12rsmpy(long A, long B); +extern long _IQ11rsmpy(long A, long B); +extern long _IQ10rsmpy(long A, long B); +extern long _IQ9rsmpy(long A, long B); +extern long _IQ8rsmpy(long A, long B); +extern long _IQ7rsmpy(long A, long B); +extern long _IQ6rsmpy(long A, long B); +extern long _IQ5rsmpy(long A, long B); +extern long _IQ4rsmpy(long A, long B); +extern long _IQ3rsmpy(long A, long B); +extern long _IQ2rsmpy(long A, long B); +extern long _IQ1rsmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrsmpy(A,B) _IQ30rsmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrsmpy(A,B) _IQ29rsmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrsmpy(A,B) _IQ28rsmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrsmpy(A,B) _IQ27rsmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrsmpy(A,B) _IQ26rsmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrsmpy(A,B) _IQ25rsmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrsmpy(A,B) _IQ24rsmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrsmpy(A,B) _IQ23rsmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrsmpy(A,B) _IQ22rsmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrsmpy(A,B) _IQ21rsmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrsmpy(A,B) _IQ20rsmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrsmpy(A,B) _IQ19rsmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrsmpy(A,B) _IQ18rsmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrsmpy(A,B) _IQ17rsmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrsmpy(A,B) _IQ16rsmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrsmpy(A,B) _IQ15rsmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrsmpy(A,B) _IQ14rsmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrsmpy(A,B) _IQ13rsmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrsmpy(A,B) _IQ12rsmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrsmpy(A,B) _IQ11rsmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrsmpy(A,B) _IQ10rsmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrsmpy(A,B) _IQ9rsmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrsmpy(A,B) _IQ8rsmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrsmpy(A,B) _IQ7rsmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrsmpy(A,B) _IQ6rsmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrsmpy(A,B) _IQ5rsmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrsmpy(A,B) _IQ4rsmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrsmpy(A,B) _IQ3rsmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrsmpy(A,B) _IQ2rsmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrsmpy(A,B) _IQ1rsmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30div(long A, long B); +extern long _IQ29div(long A, long B); +extern long _IQ28div(long A, long B); +extern long _IQ27div(long A, long B); +extern long _IQ26div(long A, long B); +extern long _IQ25div(long A, long B); +extern long _IQ24div(long A, long B); +extern long _IQ23div(long A, long B); +extern long _IQ22div(long A, long B); +extern long _IQ21div(long A, long B); +extern long _IQ20div(long A, long B); +extern long _IQ19div(long A, long B); +extern long _IQ18div(long A, long B); +extern long _IQ17div(long A, long B); +extern long _IQ16div(long A, long B); +extern long _IQ15div(long A, long B); +extern long _IQ14div(long A, long B); +extern long _IQ13div(long A, long B); +extern long _IQ12div(long A, long B); +extern long _IQ11div(long A, long B); +extern long _IQ10div(long A, long B); +extern long _IQ9div(long A, long B); +extern long _IQ8div(long A, long B); +extern long _IQ7div(long A, long B); +extern long _IQ6div(long A, long B); +extern long _IQ5div(long A, long B); +extern long _IQ4div(long A, long B); +extern long _IQ3div(long A, long B); +extern long _IQ2div(long A, long B); +extern long _IQ1div(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQdiv(A,B) _IQ30div(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQdiv(A,B) _IQ29div(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQdiv(A,B) _IQ28div(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQdiv(A,B) _IQ27div(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQdiv(A,B) _IQ26div(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQdiv(A,B) _IQ25div(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQdiv(A,B) _IQ24div(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQdiv(A,B) _IQ23div(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQdiv(A,B) _IQ22div(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQdiv(A,B) _IQ21div(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQdiv(A,B) _IQ20div(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQdiv(A,B) _IQ19div(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQdiv(A,B) _IQ18div(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQdiv(A,B) _IQ17div(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQdiv(A,B) _IQ16div(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQdiv(A,B) _IQ15div(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQdiv(A,B) _IQ14div(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQdiv(A,B) _IQ13div(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQdiv(A,B) _IQ12div(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQdiv(A,B) _IQ11div(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQdiv(A,B) _IQ10div(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQdiv(A,B) _IQ9div(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQdiv(A,B) _IQ8div(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQdiv(A,B) _IQ7div(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQdiv(A,B) _IQ6div(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQdiv(A,B) _IQ5div(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQdiv(A,B) _IQ4div(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQdiv(A,B) _IQ3div(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQdiv(A,B) _IQ2div(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQdiv(A,B) _IQ1div(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sin(long A); +extern long _IQ29sin(long A); +extern long _IQ28sin(long A); +extern long _IQ27sin(long A); +extern long _IQ26sin(long A); +extern long _IQ25sin(long A); +extern long _IQ24sin(long A); +extern long _IQ23sin(long A); +extern long _IQ22sin(long A); +extern long _IQ21sin(long A); +extern long _IQ20sin(long A); +extern long _IQ19sin(long A); +extern long _IQ18sin(long A); +extern long _IQ17sin(long A); +extern long _IQ16sin(long A); +extern long _IQ15sin(long A); +extern long _IQ14sin(long A); +extern long _IQ13sin(long A); +extern long _IQ12sin(long A); +extern long _IQ11sin(long A); +extern long _IQ10sin(long A); +extern long _IQ9sin(long A); +extern long _IQ8sin(long A); +extern long _IQ7sin(long A); +extern long _IQ6sin(long A); +extern long _IQ5sin(long A); +extern long _IQ4sin(long A); +extern long _IQ3sin(long A); +extern long _IQ2sin(long A); +extern long _IQ1sin(long A); + +#if GLOBAL_Q == 30 +#define _IQsin(A) _IQ30sin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsin(A) _IQ29sin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsin(A) _IQ28sin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsin(A) _IQ27sin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsin(A) _IQ26sin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsin(A) _IQ25sin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsin(A) _IQ24sin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsin(A) _IQ23sin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsin(A) _IQ22sin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsin(A) _IQ21sin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsin(A) _IQ20sin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsin(A) _IQ19sin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsin(A) _IQ18sin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsin(A) _IQ17sin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsin(A) _IQ16sin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsin(A) _IQ15sin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsin(A) _IQ14sin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsin(A) _IQ13sin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsin(A) _IQ12sin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsin(A) _IQ11sin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsin(A) _IQ10sin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsin(A) _IQ9sin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsin(A) _IQ8sin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsin(A) _IQ7sin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsin(A) _IQ6sin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsin(A) _IQ5sin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsin(A) _IQ4sin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsin(A) _IQ3sin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsin(A) _IQ2sin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsin(A) _IQ1sin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sinPU(long A); +extern long _IQ29sinPU(long A); +extern long _IQ28sinPU(long A); +extern long _IQ27sinPU(long A); +extern long _IQ26sinPU(long A); +extern long _IQ25sinPU(long A); +extern long _IQ24sinPU(long A); +extern long _IQ23sinPU(long A); +extern long _IQ22sinPU(long A); +extern long _IQ21sinPU(long A); +extern long _IQ20sinPU(long A); +extern long _IQ19sinPU(long A); +extern long _IQ18sinPU(long A); +extern long _IQ17sinPU(long A); +extern long _IQ16sinPU(long A); +extern long _IQ15sinPU(long A); +extern long _IQ14sinPU(long A); +extern long _IQ13sinPU(long A); +extern long _IQ12sinPU(long A); +extern long _IQ11sinPU(long A); +extern long _IQ10sinPU(long A); +extern long _IQ9sinPU(long A); +extern long _IQ8sinPU(long A); +extern long _IQ7sinPU(long A); +extern long _IQ6sinPU(long A); +extern long _IQ5sinPU(long A); +extern long _IQ4sinPU(long A); +extern long _IQ3sinPU(long A); +extern long _IQ2sinPU(long A); +extern long _IQ1sinPU(long A); + +#if GLOBAL_Q == 30 +#define _IQsinPU(A) _IQ30sinPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsinPU(A) _IQ29sinPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsinPU(A) _IQ28sinPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsinPU(A) _IQ27sinPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsinPU(A) _IQ26sinPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsinPU(A) _IQ25sinPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsinPU(A) _IQ24sinPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsinPU(A) _IQ23sinPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsinPU(A) _IQ22sinPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsinPU(A) _IQ21sinPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsinPU(A) _IQ20sinPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsinPU(A) _IQ19sinPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsinPU(A) _IQ18sinPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsinPU(A) _IQ17sinPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsinPU(A) _IQ16sinPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsinPU(A) _IQ15sinPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsinPU(A) _IQ14sinPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsinPU(A) _IQ13sinPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsinPU(A) _IQ12sinPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsinPU(A) _IQ11sinPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsinPU(A) _IQ10sinPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsinPU(A) _IQ9sinPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsinPU(A) _IQ8sinPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsinPU(A) _IQ7sinPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsinPU(A) _IQ6sinPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsinPU(A) _IQ5sinPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsinPU(A) _IQ4sinPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsinPU(A) _IQ3sinPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsinPU(A) _IQ2sinPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsinPU(A) _IQ1sinPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30asin(long A); +extern long _IQ29asin(long A); +extern long _IQ28asin(long A); +extern long _IQ27asin(long A); +extern long _IQ26asin(long A); +extern long _IQ25asin(long A); +extern long _IQ24asin(long A); +extern long _IQ23asin(long A); +extern long _IQ22asin(long A); +extern long _IQ21asin(long A); +extern long _IQ20asin(long A); +extern long _IQ19asin(long A); +extern long _IQ18asin(long A); +extern long _IQ17asin(long A); +extern long _IQ16asin(long A); +extern long _IQ15asin(long A); +extern long _IQ14asin(long A); +extern long _IQ13asin(long A); +extern long _IQ12asin(long A); +extern long _IQ11asin(long A); +extern long _IQ10asin(long A); +extern long _IQ9asin(long A); +extern long _IQ8asin(long A); +extern long _IQ7asin(long A); +extern long _IQ6asin(long A); +extern long _IQ5asin(long A); +extern long _IQ4asin(long A); +extern long _IQ3asin(long A); +extern long _IQ2asin(long A); +extern long _IQ1asin(long A); + +#if GLOBAL_Q == 30 +#define _IQasin(A) _IQ30asin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQasin(A) _IQ29asin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQasin(A) _IQ28asin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQasin(A) _IQ27asin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQasin(A) _IQ26asin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQasin(A) _IQ25asin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQasin(A) _IQ24asin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQasin(A) _IQ23asin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQasin(A) _IQ22asin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQasin(A) _IQ21asin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQasin(A) _IQ20asin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQasin(A) _IQ19asin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQasin(A) _IQ18asin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQasin(A) _IQ17asin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQasin(A) _IQ16asin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQasin(A) _IQ15asin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQasin(A) _IQ14asin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQasin(A) _IQ13asin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQasin(A) _IQ12asin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQasin(A) _IQ11asin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQasin(A) _IQ10asin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQasin(A) _IQ9asin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQasin(A) _IQ8asin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQasin(A) _IQ7asin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQasin(A) _IQ6asin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQasin(A) _IQ5asin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQasin(A) _IQ4asin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQasin(A) _IQ3asin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQasin(A) _IQ2asin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQasin(A) _IQ1asin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cos(long A); +extern long _IQ29cos(long A); +extern long _IQ28cos(long A); +extern long _IQ27cos(long A); +extern long _IQ26cos(long A); +extern long _IQ25cos(long A); +extern long _IQ24cos(long A); +extern long _IQ23cos(long A); +extern long _IQ22cos(long A); +extern long _IQ21cos(long A); +extern long _IQ20cos(long A); +extern long _IQ19cos(long A); +extern long _IQ18cos(long A); +extern long _IQ17cos(long A); +extern long _IQ16cos(long A); +extern long _IQ15cos(long A); +extern long _IQ14cos(long A); +extern long _IQ13cos(long A); +extern long _IQ12cos(long A); +extern long _IQ11cos(long A); +extern long _IQ10cos(long A); +extern long _IQ9cos(long A); +extern long _IQ8cos(long A); +extern long _IQ7cos(long A); +extern long _IQ6cos(long A); +extern long _IQ5cos(long A); +extern long _IQ4cos(long A); +extern long _IQ3cos(long A); +extern long _IQ2cos(long A); +extern long _IQ1cos(long A); + +#if GLOBAL_Q == 30 +#define _IQcos(A) _IQ30cos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcos(A) _IQ29cos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcos(A) _IQ28cos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcos(A) _IQ27cos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcos(A) _IQ26cos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcos(A) _IQ25cos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcos(A) _IQ24cos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcos(A) _IQ23cos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcos(A) _IQ22cos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcos(A) _IQ21cos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcos(A) _IQ20cos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcos(A) _IQ19cos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcos(A) _IQ18cos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcos(A) _IQ17cos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcos(A) _IQ16cos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcos(A) _IQ15cos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcos(A) _IQ14cos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcos(A) _IQ13cos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcos(A) _IQ12cos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcos(A) _IQ11cos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcos(A) _IQ10cos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcos(A) _IQ9cos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcos(A) _IQ8cos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcos(A) _IQ7cos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcos(A) _IQ6cos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcos(A) _IQ5cos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcos(A) _IQ4cos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcos(A) _IQ3cos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcos(A) _IQ2cos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcos(A) _IQ1cos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cosPU(long A); +extern long _IQ29cosPU(long A); +extern long _IQ28cosPU(long A); +extern long _IQ27cosPU(long A); +extern long _IQ26cosPU(long A); +extern long _IQ25cosPU(long A); +extern long _IQ24cosPU(long A); +extern long _IQ23cosPU(long A); +extern long _IQ22cosPU(long A); +extern long _IQ21cosPU(long A); +extern long _IQ20cosPU(long A); +extern long _IQ19cosPU(long A); +extern long _IQ18cosPU(long A); +extern long _IQ17cosPU(long A); +extern long _IQ16cosPU(long A); +extern long _IQ15cosPU(long A); +extern long _IQ14cosPU(long A); +extern long _IQ13cosPU(long A); +extern long _IQ12cosPU(long A); +extern long _IQ11cosPU(long A); +extern long _IQ10cosPU(long A); +extern long _IQ9cosPU(long A); +extern long _IQ8cosPU(long A); +extern long _IQ7cosPU(long A); +extern long _IQ6cosPU(long A); +extern long _IQ5cosPU(long A); +extern long _IQ4cosPU(long A); +extern long _IQ3cosPU(long A); +extern long _IQ2cosPU(long A); +extern long _IQ1cosPU(long A); + +#if GLOBAL_Q == 30 +#define _IQcosPU(A) _IQ30cosPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcosPU(A) _IQ29cosPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcosPU(A) _IQ28cosPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcosPU(A) _IQ27cosPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcosPU(A) _IQ26cosPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcosPU(A) _IQ25cosPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcosPU(A) _IQ24cosPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcosPU(A) _IQ23cosPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcosPU(A) _IQ22cosPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcosPU(A) _IQ21cosPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcosPU(A) _IQ20cosPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcosPU(A) _IQ19cosPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcosPU(A) _IQ18cosPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcosPU(A) _IQ17cosPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcosPU(A) _IQ16cosPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcosPU(A) _IQ15cosPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcosPU(A) _IQ14cosPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcosPU(A) _IQ13cosPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcosPU(A) _IQ12cosPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcosPU(A) _IQ11cosPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcosPU(A) _IQ10cosPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcosPU(A) _IQ9cosPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcosPU(A) _IQ8cosPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcosPU(A) _IQ7cosPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcosPU(A) _IQ6cosPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcosPU(A) _IQ5cosPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcosPU(A) _IQ4cosPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcosPU(A) _IQ3cosPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcosPU(A) _IQ2cosPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcosPU(A) _IQ1cosPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30acos(long A); +extern long _IQ29acos(long A); +extern long _IQ28acos(long A); +extern long _IQ27acos(long A); +extern long _IQ26acos(long A); +extern long _IQ25acos(long A); +extern long _IQ24acos(long A); +extern long _IQ23acos(long A); +extern long _IQ22acos(long A); +extern long _IQ21acos(long A); +extern long _IQ20acos(long A); +extern long _IQ19acos(long A); +extern long _IQ18acos(long A); +extern long _IQ17acos(long A); +extern long _IQ16acos(long A); +extern long _IQ15acos(long A); +extern long _IQ14acos(long A); +extern long _IQ13acos(long A); +extern long _IQ12acos(long A); +extern long _IQ11acos(long A); +extern long _IQ10acos(long A); +extern long _IQ9acos(long A); +extern long _IQ8acos(long A); +extern long _IQ7acos(long A); +extern long _IQ6acos(long A); +extern long _IQ5acos(long A); +extern long _IQ4acos(long A); +extern long _IQ3acos(long A); +extern long _IQ2acos(long A); +extern long _IQ1acos(long A); + +#if GLOBAL_Q == 30 +#define _IQacos(A) _IQ30acos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQacos(A) _IQ29acos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQacos(A) _IQ28acos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQacos(A) _IQ27acos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQacos(A) _IQ26acos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQacos(A) _IQ25acos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQacos(A) _IQ24acos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQacos(A) _IQ23acos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQacos(A) _IQ22acos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQacos(A) _IQ21acos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQacos(A) _IQ20acos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQacos(A) _IQ19acos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQacos(A) _IQ18acos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQacos(A) _IQ17acos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQacos(A) _IQ16acos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQacos(A) _IQ15acos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQacos(A) _IQ14acos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQacos(A) _IQ13acos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQacos(A) _IQ12acos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQacos(A) _IQ11acos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQacos(A) _IQ10acos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQacos(A) _IQ9acos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQacos(A) _IQ8acos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQacos(A) _IQ7acos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQacos(A) _IQ6acos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQacos(A) _IQ5acos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQacos(A) _IQ4acos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQacos(A) _IQ3acos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQacos(A) _IQ2acos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQacos(A) _IQ1acos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2(long A, long B); +extern long _IQ29atan2(long A, long B); +extern long _IQ28atan2(long A, long B); +extern long _IQ27atan2(long A, long B); +extern long _IQ26atan2(long A, long B); +extern long _IQ25atan2(long A, long B); +extern long _IQ24atan2(long A, long B); +extern long _IQ23atan2(long A, long B); +extern long _IQ22atan2(long A, long B); +extern long _IQ21atan2(long A, long B); +extern long _IQ20atan2(long A, long B); +extern long _IQ19atan2(long A, long B); +extern long _IQ18atan2(long A, long B); +extern long _IQ17atan2(long A, long B); +extern long _IQ16atan2(long A, long B); +extern long _IQ15atan2(long A, long B); +extern long _IQ14atan2(long A, long B); +extern long _IQ13atan2(long A, long B); +extern long _IQ12atan2(long A, long B); +extern long _IQ11atan2(long A, long B); +extern long _IQ10atan2(long A, long B); +extern long _IQ9atan2(long A, long B); +extern long _IQ8atan2(long A, long B); +extern long _IQ7atan2(long A, long B); +extern long _IQ6atan2(long A, long B); +extern long _IQ5atan2(long A, long B); +extern long _IQ4atan2(long A, long B); +extern long _IQ3atan2(long A, long B); +extern long _IQ2atan2(long A, long B); +extern long _IQ1atan2(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2(A,B) _IQ30atan2(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2(A,B) _IQ29atan2(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2(A,B) _IQ28atan2(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2(A,B) _IQ27atan2(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2(A,B) _IQ26atan2(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2(A,B) _IQ25atan2(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2(A,B) _IQ24atan2(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2(A,B) _IQ23atan2(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2(A,B) _IQ22atan2(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2(A,B) _IQ21atan2(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2(A,B) _IQ20atan2(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2(A,B) _IQ19atan2(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2(A,B) _IQ18atan2(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2(A,B) _IQ17atan2(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2(A,B) _IQ16atan2(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2(A,B) _IQ15atan2(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2(A,B) _IQ14atan2(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2(A,B) _IQ13atan2(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2(A,B) _IQ12atan2(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2(A,B) _IQ11atan2(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2(A,B) _IQ10atan2(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2(A,B) _IQ9atan2(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2(A,B) _IQ8atan2(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2(A,B) _IQ7atan2(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2(A,B) _IQ6atan2(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2(A,B) _IQ5atan2(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2(A,B) _IQ4atan2(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2(A,B) _IQ3atan2(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2(A,B) _IQ2atan2(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2(A,B) _IQ1atan2(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2PU(long A, long B); +extern long _IQ29atan2PU(long A, long B); +extern long _IQ28atan2PU(long A, long B); +extern long _IQ27atan2PU(long A, long B); +extern long _IQ26atan2PU(long A, long B); +extern long _IQ25atan2PU(long A, long B); +extern long _IQ24atan2PU(long A, long B); +extern long _IQ23atan2PU(long A, long B); +extern long _IQ22atan2PU(long A, long B); +extern long _IQ21atan2PU(long A, long B); +extern long _IQ20atan2PU(long A, long B); +extern long _IQ19atan2PU(long A, long B); +extern long _IQ18atan2PU(long A, long B); +extern long _IQ17atan2PU(long A, long B); +extern long _IQ16atan2PU(long A, long B); +extern long _IQ15atan2PU(long A, long B); +extern long _IQ14atan2PU(long A, long B); +extern long _IQ13atan2PU(long A, long B); +extern long _IQ12atan2PU(long A, long B); +extern long _IQ11atan2PU(long A, long B); +extern long _IQ10atan2PU(long A, long B); +extern long _IQ9atan2PU(long A, long B); +extern long _IQ8atan2PU(long A, long B); +extern long _IQ7atan2PU(long A, long B); +extern long _IQ6atan2PU(long A, long B); +extern long _IQ5atan2PU(long A, long B); +extern long _IQ4atan2PU(long A, long B); +extern long _IQ3atan2PU(long A, long B); +extern long _IQ2atan2PU(long A, long B); +extern long _IQ1atan2PU(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2PU(A,B) _IQ30atan2PU(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2PU(A,B) _IQ29atan2PU(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2PU(A,B) _IQ28atan2PU(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2PU(A,B) _IQ27atan2PU(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2PU(A,B) _IQ26atan2PU(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2PU(A,B) _IQ25atan2PU(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2PU(A,B) _IQ24atan2PU(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2PU(A,B) _IQ23atan2PU(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2PU(A,B) _IQ22atan2PU(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2PU(A,B) _IQ21atan2PU(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2PU(A,B) _IQ20atan2PU(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2PU(A,B) _IQ19atan2PU(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2PU(A,B) _IQ18atan2PU(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2PU(A,B) _IQ17atan2PU(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2PU(A,B) _IQ16atan2PU(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2PU(A,B) _IQ15atan2PU(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2PU(A,B) _IQ14atan2PU(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2PU(A,B) _IQ13atan2PU(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2PU(A,B) _IQ12atan2PU(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2PU(A,B) _IQ11atan2PU(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2PU(A,B) _IQ10atan2PU(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2PU(A,B) _IQ9atan2PU(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2PU(A,B) _IQ8atan2PU(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2PU(A,B) _IQ7atan2PU(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2PU(A,B) _IQ6atan2PU(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2PU(A,B) _IQ5atan2PU(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2PU(A,B) _IQ4atan2PU(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2PU(A,B) _IQ3atan2PU(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2PU(A,B) _IQ2atan2PU(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2PU(A,B) _IQ1atan2PU(A,B) +#endif +//--------------------------------------------------------------------------- +#define _IQ30atan(A) _IQ30atan2(A,_IQ30(1.0)) +#define _IQ29atan(A) _IQ29atan2(A,_IQ29(1.0)) +#define _IQ28atan(A) _IQ28atan2(A,_IQ28(1.0)) +#define _IQ27atan(A) _IQ27atan2(A,_IQ27(1.0)) +#define _IQ26atan(A) _IQ26atan2(A,_IQ26(1.0)) +#define _IQ25atan(A) _IQ25atan2(A,_IQ25(1.0)) +#define _IQ24atan(A) _IQ24atan2(A,_IQ24(1.0)) +#define _IQ23atan(A) _IQ23atan2(A,_IQ23(1.0)) +#define _IQ22atan(A) _IQ22atan2(A,_IQ22(1.0)) +#define _IQ21atan(A) _IQ21atan2(A,_IQ21(1.0)) +#define _IQ20atan(A) _IQ20atan2(A,_IQ20(1.0)) +#define _IQ19atan(A) _IQ19atan2(A,_IQ19(1.0)) +#define _IQ18atan(A) _IQ18atan2(A,_IQ18(1.0)) +#define _IQ17atan(A) _IQ17atan2(A,_IQ17(1.0)) +#define _IQ16atan(A) _IQ16atan2(A,_IQ16(1.0)) +#define _IQ15atan(A) _IQ15atan2(A,_IQ15(1.0)) +#define _IQ14atan(A) _IQ14atan2(A,_IQ14(1.0)) +#define _IQ13atan(A) _IQ13atan2(A,_IQ13(1.0)) +#define _IQ12atan(A) _IQ12atan2(A,_IQ12(1.0)) +#define _IQ11atan(A) _IQ11atan2(A,_IQ11(1.0)) +#define _IQ10atan(A) _IQ10atan2(A,_IQ10(1.0)) +#define _IQ9atan(A) _IQ9atan2(A,_IQ9(1.0)) +#define _IQ8atan(A) _IQ8atan2(A,_IQ8(1.0)) +#define _IQ7atan(A) _IQ7atan2(A,_IQ7(1.0)) +#define _IQ6atan(A) _IQ6atan2(A,_IQ6(1.0)) +#define _IQ5atan(A) _IQ5atan2(A,_IQ5(1.0)) +#define _IQ4atan(A) _IQ4atan2(A,_IQ4(1.0)) +#define _IQ3atan(A) _IQ3atan2(A,_IQ3(1.0)) +#define _IQ2atan(A) _IQ2atan2(A,_IQ2(1.0)) +#define _IQ1atan(A) _IQ1atan2(A,_IQ1(1.0)) +#if GLOBAL_Q == 30 +#define _IQatan(A) _IQ30atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 29 +#define _IQatan(A) _IQ29atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 28 +#define _IQatan(A) _IQ28atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 27 +#define _IQatan(A) _IQ27atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 26 +#define _IQatan(A) _IQ26atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 25 +#define _IQatan(A) _IQ25atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 24 +#define _IQatan(A) _IQ24atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 23 +#define _IQatan(A) _IQ23atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 22 +#define _IQatan(A) _IQ22atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 21 +#define _IQatan(A) _IQ21atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 20 +#define _IQatan(A) _IQ20atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 19 +#define _IQatan(A) _IQ19atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 18 +#define _IQatan(A) _IQ18atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 17 +#define _IQatan(A) _IQ17atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 16 +#define _IQatan(A) _IQ16atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 15 +#define _IQatan(A) _IQ15atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 14 +#define _IQatan(A) _IQ14atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 13 +#define _IQatan(A) _IQ13atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 12 +#define _IQatan(A) _IQ12atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 11 +#define _IQatan(A) _IQ11atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 10 +#define _IQatan(A) _IQ10atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 9 +#define _IQatan(A) _IQ9atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 8 +#define _IQatan(A) _IQ8atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 7 +#define _IQatan(A) _IQ7atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 6 +#define _IQatan(A) _IQ6atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 5 +#define _IQatan(A) _IQ5atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 4 +#define _IQatan(A) _IQ4atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 3 +#define _IQatan(A) _IQ3atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 2 +#define _IQatan(A) _IQ2atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 1 +#define _IQatan(A) _IQ1atan2(A,_IQ(1.0)) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sqrt(long A); +extern long _IQ29sqrt(long A); +extern long _IQ28sqrt(long A); +extern long _IQ27sqrt(long A); +extern long _IQ26sqrt(long A); +extern long _IQ25sqrt(long A); +extern long _IQ24sqrt(long A); +extern long _IQ23sqrt(long A); +extern long _IQ22sqrt(long A); +extern long _IQ21sqrt(long A); +extern long _IQ20sqrt(long A); +extern long _IQ19sqrt(long A); +extern long _IQ18sqrt(long A); +extern long _IQ17sqrt(long A); +extern long _IQ16sqrt(long A); +extern long _IQ15sqrt(long A); +extern long _IQ14sqrt(long A); +extern long _IQ13sqrt(long A); +extern long _IQ12sqrt(long A); +extern long _IQ11sqrt(long A); +extern long _IQ10sqrt(long A); +extern long _IQ9sqrt(long A); +extern long _IQ8sqrt(long A); +extern long _IQ7sqrt(long A); +extern long _IQ6sqrt(long A); +extern long _IQ5sqrt(long A); +extern long _IQ4sqrt(long A); +extern long _IQ3sqrt(long A); +extern long _IQ2sqrt(long A); +extern long _IQ1sqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQsqrt(A) _IQ30sqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsqrt(A) _IQ29sqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsqrt(A) _IQ28sqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsqrt(A) _IQ27sqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsqrt(A) _IQ26sqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsqrt(A) _IQ25sqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsqrt(A) _IQ24sqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsqrt(A) _IQ23sqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsqrt(A) _IQ22sqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsqrt(A) _IQ21sqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsqrt(A) _IQ20sqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsqrt(A) _IQ19sqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsqrt(A) _IQ18sqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsqrt(A) _IQ17sqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsqrt(A) _IQ16sqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsqrt(A) _IQ15sqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsqrt(A) _IQ14sqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsqrt(A) _IQ13sqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsqrt(A) _IQ12sqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsqrt(A) _IQ11sqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsqrt(A) _IQ10sqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsqrt(A) _IQ9sqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsqrt(A) _IQ8sqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsqrt(A) _IQ7sqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsqrt(A) _IQ6sqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsqrt(A) _IQ5sqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsqrt(A) _IQ4sqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsqrt(A) _IQ3sqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsqrt(A) _IQ2sqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsqrt(A) _IQ1sqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30isqrt(long A); +extern long _IQ29isqrt(long A); +extern long _IQ28isqrt(long A); +extern long _IQ27isqrt(long A); +extern long _IQ26isqrt(long A); +extern long _IQ25isqrt(long A); +extern long _IQ24isqrt(long A); +extern long _IQ23isqrt(long A); +extern long _IQ22isqrt(long A); +extern long _IQ21isqrt(long A); +extern long _IQ20isqrt(long A); +extern long _IQ19isqrt(long A); +extern long _IQ18isqrt(long A); +extern long _IQ17isqrt(long A); +extern long _IQ16isqrt(long A); +extern long _IQ15isqrt(long A); +extern long _IQ14isqrt(long A); +extern long _IQ13isqrt(long A); +extern long _IQ12isqrt(long A); +extern long _IQ11isqrt(long A); +extern long _IQ10isqrt(long A); +extern long _IQ9isqrt(long A); +extern long _IQ8isqrt(long A); +extern long _IQ7isqrt(long A); +extern long _IQ6isqrt(long A); +extern long _IQ5isqrt(long A); +extern long _IQ4isqrt(long A); +extern long _IQ3isqrt(long A); +extern long _IQ2isqrt(long A); +extern long _IQ1isqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQisqrt(A) _IQ30isqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQisqrt(A) _IQ29isqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQisqrt(A) _IQ28isqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQisqrt(A) _IQ27isqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQisqrt(A) _IQ26isqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQisqrt(A) _IQ25isqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQisqrt(A) _IQ24isqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQisqrt(A) _IQ23isqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQisqrt(A) _IQ22isqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQisqrt(A) _IQ21isqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQisqrt(A) _IQ20isqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQisqrt(A) _IQ19isqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQisqrt(A) _IQ18isqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQisqrt(A) _IQ17isqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQisqrt(A) _IQ16isqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQisqrt(A) _IQ15isqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQisqrt(A) _IQ14isqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQisqrt(A) _IQ13isqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQisqrt(A) _IQ12isqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQisqrt(A) _IQ11isqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQisqrt(A) _IQ10isqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQisqrt(A) _IQ9isqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQisqrt(A) _IQ8isqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQisqrt(A) _IQ7isqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQisqrt(A) _IQ6isqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQisqrt(A) _IQ5isqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQisqrt(A) _IQ4isqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQisqrt(A) _IQ3isqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQisqrt(A) _IQ2isqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQisqrt(A) _IQ1isqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30exp(long A); +extern long _IQ29exp(long A); +extern long _IQ28exp(long A); +extern long _IQ27exp(long A); +extern long _IQ26exp(long A); +extern long _IQ25exp(long A); +extern long _IQ24exp(long A); +extern long _IQ23exp(long A); +extern long _IQ22exp(long A); +extern long _IQ21exp(long A); +extern long _IQ20exp(long A); +extern long _IQ19exp(long A); +extern long _IQ18exp(long A); +extern long _IQ17exp(long A); +extern long _IQ16exp(long A); +extern long _IQ15exp(long A); +extern long _IQ14exp(long A); +extern long _IQ13exp(long A); +extern long _IQ12exp(long A); +extern long _IQ11exp(long A); +extern long _IQ10exp(long A); +extern long _IQ9exp(long A); +extern long _IQ8exp(long A); +extern long _IQ7exp(long A); +extern long _IQ6exp(long A); +extern long _IQ5exp(long A); +extern long _IQ4exp(long A); +extern long _IQ3exp(long A); +extern long _IQ2exp(long A); +extern long _IQ1exp(long A); + +#if GLOBAL_Q == 30 +#define _IQexp(A) _IQ30exp(A) +#endif +#if GLOBAL_Q == 29 +#define _IQexp(A) _IQ29exp(A) +#endif +#if GLOBAL_Q == 28 +#define _IQexp(A) _IQ28exp(A) +#endif +#if GLOBAL_Q == 27 +#define _IQexp(A) _IQ27exp(A) +#endif +#if GLOBAL_Q == 26 +#define _IQexp(A) _IQ26exp(A) +#endif +#if GLOBAL_Q == 25 +#define _IQexp(A) _IQ25exp(A) +#endif +#if GLOBAL_Q == 24 +#define _IQexp(A) _IQ24exp(A) +#endif +#if GLOBAL_Q == 23 +#define _IQexp(A) _IQ23exp(A) +#endif +#if GLOBAL_Q == 22 +#define _IQexp(A) _IQ22exp(A) +#endif +#if GLOBAL_Q == 21 +#define _IQexp(A) _IQ21exp(A) +#endif +#if GLOBAL_Q == 20 +#define _IQexp(A) _IQ20exp(A) +#endif +#if GLOBAL_Q == 19 +#define _IQexp(A) _IQ19exp(A) +#endif +#if GLOBAL_Q == 18 +#define _IQexp(A) _IQ18exp(A) +#endif +#if GLOBAL_Q == 17 +#define _IQexp(A) _IQ17exp(A) +#endif +#if GLOBAL_Q == 16 +#define _IQexp(A) _IQ16exp(A) +#endif +#if GLOBAL_Q == 15 +#define _IQexp(A) _IQ15exp(A) +#endif +#if GLOBAL_Q == 14 +#define _IQexp(A) _IQ14exp(A) +#endif +#if GLOBAL_Q == 13 +#define _IQexp(A) _IQ13exp(A) +#endif +#if GLOBAL_Q == 12 +#define _IQexp(A) _IQ12exp(A) +#endif +#if GLOBAL_Q == 11 +#define _IQexp(A) _IQ11exp(A) +#endif +#if GLOBAL_Q == 10 +#define _IQexp(A) _IQ10exp(A) +#endif +#if GLOBAL_Q == 9 +#define _IQexp(A) _IQ9exp(A) +#endif +#if GLOBAL_Q == 8 +#define _IQexp(A) _IQ8exp(A) +#endif +#if GLOBAL_Q == 7 +#define _IQexp(A) _IQ7exp(A) +#endif +#if GLOBAL_Q == 6 +#define _IQexp(A) _IQ6exp(A) +#endif +#if GLOBAL_Q == 5 +#define _IQexp(A) _IQ5exp(A) +#endif +#if GLOBAL_Q == 4 +#define _IQexp(A) _IQ4exp(A) +#endif +#if GLOBAL_Q == 3 +#define _IQexp(A) _IQ3exp(A) +#endif +#if GLOBAL_Q == 2 +#define _IQexp(A) _IQ2exp(A) +#endif +#if GLOBAL_Q == 1 +#define _IQexp(A) _IQ1exp(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30int(long A); +extern long _IQ29int(long A); +extern long _IQ28int(long A); +extern long _IQ27int(long A); +extern long _IQ26int(long A); +extern long _IQ25int(long A); +extern long _IQ24int(long A); +extern long _IQ23int(long A); +extern long _IQ22int(long A); +extern long _IQ21int(long A); +extern long _IQ20int(long A); +extern long _IQ19int(long A); +extern long _IQ18int(long A); +extern long _IQ17int(long A); +extern long _IQ16int(long A); +extern long _IQ15int(long A); +extern long _IQ14int(long A); +extern long _IQ13int(long A); +extern long _IQ12int(long A); +extern long _IQ11int(long A); +extern long _IQ10int(long A); +extern long _IQ9int(long A); +extern long _IQ8int(long A); +extern long _IQ7int(long A); +extern long _IQ6int(long A); +extern long _IQ5int(long A); +extern long _IQ4int(long A); +extern long _IQ3int(long A); +extern long _IQ2int(long A); +extern long _IQ1int(long A); + +#if GLOBAL_Q == 30 +#define _IQint(A) _IQ30int(A) +#endif +#if GLOBAL_Q == 29 +#define _IQint(A) _IQ29int(A) +#endif +#if GLOBAL_Q == 28 +#define _IQint(A) _IQ28int(A) +#endif +#if GLOBAL_Q == 27 +#define _IQint(A) _IQ27int(A) +#endif +#if GLOBAL_Q == 26 +#define _IQint(A) _IQ26int(A) +#endif +#if GLOBAL_Q == 25 +#define _IQint(A) _IQ25int(A) +#endif +#if GLOBAL_Q == 24 +#define _IQint(A) _IQ24int(A) +#endif +#if GLOBAL_Q == 23 +#define _IQint(A) _IQ23int(A) +#endif +#if GLOBAL_Q == 22 +#define _IQint(A) _IQ22int(A) +#endif +#if GLOBAL_Q == 21 +#define _IQint(A) _IQ21int(A) +#endif +#if GLOBAL_Q == 20 +#define _IQint(A) _IQ20int(A) +#endif +#if GLOBAL_Q == 19 +#define _IQint(A) _IQ19int(A) +#endif +#if GLOBAL_Q == 18 +#define _IQint(A) _IQ18int(A) +#endif +#if GLOBAL_Q == 17 +#define _IQint(A) _IQ17int(A) +#endif +#if GLOBAL_Q == 16 +#define _IQint(A) _IQ16int(A) +#endif +#if GLOBAL_Q == 15 +#define _IQint(A) _IQ15int(A) +#endif +#if GLOBAL_Q == 14 +#define _IQint(A) _IQ14int(A) +#endif +#if GLOBAL_Q == 13 +#define _IQint(A) _IQ13int(A) +#endif +#if GLOBAL_Q == 12 +#define _IQint(A) _IQ12int(A) +#endif +#if GLOBAL_Q == 11 +#define _IQint(A) _IQ11int(A) +#endif +#if GLOBAL_Q == 10 +#define _IQint(A) _IQ10int(A) +#endif +#if GLOBAL_Q == 9 +#define _IQint(A) _IQ9int(A) +#endif +#if GLOBAL_Q == 8 +#define _IQint(A) _IQ8int(A) +#endif +#if GLOBAL_Q == 7 +#define _IQint(A) _IQ7int(A) +#endif +#if GLOBAL_Q == 6 +#define _IQint(A) _IQ6int(A) +#endif +#if GLOBAL_Q == 5 +#define _IQint(A) _IQ5int(A) +#endif +#if GLOBAL_Q == 4 +#define _IQint(A) _IQ4int(A) +#endif +#if GLOBAL_Q == 3 +#define _IQint(A) _IQ3int(A) +#endif +#if GLOBAL_Q == 2 +#define _IQint(A) _IQ2int(A) +#endif +#if GLOBAL_Q == 1 +#define _IQint(A) _IQ1int(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30frac(long A); +extern long _IQ29frac(long A); +extern long _IQ28frac(long A); +extern long _IQ27frac(long A); +extern long _IQ26frac(long A); +extern long _IQ25frac(long A); +extern long _IQ24frac(long A); +extern long _IQ23frac(long A); +extern long _IQ22frac(long A); +extern long _IQ21frac(long A); +extern long _IQ20frac(long A); +extern long _IQ19frac(long A); +extern long _IQ18frac(long A); +extern long _IQ17frac(long A); +extern long _IQ16frac(long A); +extern long _IQ15frac(long A); +extern long _IQ14frac(long A); +extern long _IQ13frac(long A); +extern long _IQ12frac(long A); +extern long _IQ11frac(long A); +extern long _IQ10frac(long A); +extern long _IQ9frac(long A); +extern long _IQ8frac(long A); +extern long _IQ7frac(long A); +extern long _IQ6frac(long A); +extern long _IQ5frac(long A); +extern long _IQ4frac(long A); +extern long _IQ3frac(long A); +extern long _IQ2frac(long A); +extern long _IQ1frac(long A); + +#if GLOBAL_Q == 30 +#define _IQfrac(A) _IQ30frac(A) +#endif +#if GLOBAL_Q == 29 +#define _IQfrac(A) _IQ29frac(A) +#endif +#if GLOBAL_Q == 28 +#define _IQfrac(A) _IQ28frac(A) +#endif +#if GLOBAL_Q == 27 +#define _IQfrac(A) _IQ27frac(A) +#endif +#if GLOBAL_Q == 26 +#define _IQfrac(A) _IQ26frac(A) +#endif +#if GLOBAL_Q == 25 +#define _IQfrac(A) _IQ25frac(A) +#endif +#if GLOBAL_Q == 24 +#define _IQfrac(A) _IQ24frac(A) +#endif +#if GLOBAL_Q == 23 +#define _IQfrac(A) _IQ23frac(A) +#endif +#if GLOBAL_Q == 22 +#define _IQfrac(A) _IQ22frac(A) +#endif +#if GLOBAL_Q == 21 +#define _IQfrac(A) _IQ21frac(A) +#endif +#if GLOBAL_Q == 20 +#define _IQfrac(A) _IQ20frac(A) +#endif +#if GLOBAL_Q == 19 +#define _IQfrac(A) _IQ19frac(A) +#endif +#if GLOBAL_Q == 18 +#define _IQfrac(A) _IQ18frac(A) +#endif +#if GLOBAL_Q == 17 +#define _IQfrac(A) _IQ17frac(A) +#endif +#if GLOBAL_Q == 16 +#define _IQfrac(A) _IQ16frac(A) +#endif +#if GLOBAL_Q == 15 +#define _IQfrac(A) _IQ15frac(A) +#endif +#if GLOBAL_Q == 14 +#define _IQfrac(A) _IQ14frac(A) +#endif +#if GLOBAL_Q == 13 +#define _IQfrac(A) _IQ13frac(A) +#endif +#if GLOBAL_Q == 12 +#define _IQfrac(A) _IQ12frac(A) +#endif +#if GLOBAL_Q == 11 +#define _IQfrac(A) _IQ11frac(A) +#endif +#if GLOBAL_Q == 10 +#define _IQfrac(A) _IQ10frac(A) +#endif +#if GLOBAL_Q == 9 +#define _IQfrac(A) _IQ9frac(A) +#endif +#if GLOBAL_Q == 8 +#define _IQfrac(A) _IQ8frac(A) +#endif +#if GLOBAL_Q == 7 +#define _IQfrac(A) _IQ7frac(A) +#endif +#if GLOBAL_Q == 6 +#define _IQfrac(A) _IQ6frac(A) +#endif +#if GLOBAL_Q == 5 +#define _IQfrac(A) _IQ5frac(A) +#endif +#if GLOBAL_Q == 4 +#define _IQfrac(A) _IQ4frac(A) +#endif +#if GLOBAL_Q == 3 +#define _IQfrac(A) _IQ3frac(A) +#endif +#if GLOBAL_Q == 2 +#define _IQfrac(A) _IQ2frac(A) +#endif +#if GLOBAL_Q == 1 +#define _IQfrac(A) _IQ1frac(A) +#endif +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (GLOBAL_Q + 32 - IQA - IQB)) +#define _IQ30mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (30 + 32 - IQA - IQB)) +#define _IQ29mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (29 + 32 - IQA - IQB)) +#define _IQ28mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (28 + 32 - IQA - IQB)) +#define _IQ27mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (27 + 32 - IQA - IQB)) +#define _IQ26mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (26 + 32 - IQA - IQB)) +#define _IQ25mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (25 + 32 - IQA - IQB)) +#define _IQ24mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (24 + 32 - IQA - IQB)) +#define _IQ23mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (23 + 32 - IQA - IQB)) +#define _IQ22mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (22 + 32 - IQA - IQB)) +#define _IQ21mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (21 + 32 - IQA - IQB)) +#define _IQ20mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (20 + 32 - IQA - IQB)) +#define _IQ19mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (19 + 32 - IQA - IQB)) +#define _IQ18mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (18 + 32 - IQA - IQB)) +#define _IQ17mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (17 + 32 - IQA - IQB)) +#define _IQ16mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (16 + 32 - IQA - IQB)) +#define _IQ15mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (15 + 32 - IQA - IQB)) +#define _IQ14mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (14 + 32 - IQA - IQB)) +#define _IQ13mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (13 + 32 - IQA - IQB)) +#define _IQ12mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (12 + 32 - IQA - IQB)) +#define _IQ11mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (11 + 32 - IQA - IQB)) +#define _IQ10mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (10 + 32 - IQA - IQB)) +#define _IQ9mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (9 + 32 - IQA - IQB)) +#define _IQ8mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (8 + 32 - IQA - IQB)) +#define _IQ7mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (7 + 32 - IQA - IQB)) +#define _IQ6mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (6 + 32 - IQA - IQB)) +#define _IQ5mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (5 + 32 - IQA - IQB)) +#define _IQ4mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (4 + 32 - IQA - IQB)) +#define _IQ3mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (3 + 32 - IQA - IQB)) +#define _IQ2mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (2 + 32 - IQA - IQB)) +#define _IQ1mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (1 + 32 - IQA - IQB)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A)*(B)) +#define _IQ30mpyI32(A,B) ((A)*(B)) +#define _IQ29mpyI32(A,B) ((A)*(B)) +#define _IQ28mpyI32(A,B) ((A)*(B)) +#define _IQ27mpyI32(A,B) ((A)*(B)) +#define _IQ26mpyI32(A,B) ((A)*(B)) +#define _IQ25mpyI32(A,B) ((A)*(B)) +#define _IQ24mpyI32(A,B) ((A)*(B)) +#define _IQ23mpyI32(A,B) ((A)*(B)) +#define _IQ22mpyI32(A,B) ((A)*(B)) +#define _IQ21mpyI32(A,B) ((A)*(B)) +#define _IQ20mpyI32(A,B) ((A)*(B)) +#define _IQ19mpyI32(A,B) ((A)*(B)) +#define _IQ18mpyI32(A,B) ((A)*(B)) +#define _IQ17mpyI32(A,B) ((A)*(B)) +#define _IQ16mpyI32(A,B) ((A)*(B)) +#define _IQ15mpyI32(A,B) ((A)*(B)) +#define _IQ14mpyI32(A,B) ((A)*(B)) +#define _IQ13mpyI32(A,B) ((A)*(B)) +#define _IQ12mpyI32(A,B) ((A)*(B)) +#define _IQ11mpyI32(A,B) ((A)*(B)) +#define _IQ10mpyI32(A,B) ((A)*(B)) +#define _IQ9mpyI32(A,B) ((A)*(B)) +#define _IQ8mpyI32(A,B) ((A)*(B)) +#define _IQ7mpyI32(A,B) ((A)*(B)) +#define _IQ6mpyI32(A,B) ((A)*(B)) +#define _IQ5mpyI32(A,B) ((A)*(B)) +#define _IQ4mpyI32(A,B) ((A)*(B)) +#define _IQ3mpyI32(A,B) ((A)*(B)) +#define _IQ2mpyI32(A,B) ((A)*(B)) +#define _IQ1mpyI32(A,B) ((A)*(B)) +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32int(long A, long B); +extern long _IQ29mpyI32int(long A, long B); +extern long _IQ28mpyI32int(long A, long B); +extern long _IQ27mpyI32int(long A, long B); +extern long _IQ26mpyI32int(long A, long B); +extern long _IQ25mpyI32int(long A, long B); +extern long _IQ24mpyI32int(long A, long B); +extern long _IQ23mpyI32int(long A, long B); +extern long _IQ22mpyI32int(long A, long B); +extern long _IQ21mpyI32int(long A, long B); +extern long _IQ20mpyI32int(long A, long B); +extern long _IQ19mpyI32int(long A, long B); +extern long _IQ18mpyI32int(long A, long B); +extern long _IQ17mpyI32int(long A, long B); +extern long _IQ16mpyI32int(long A, long B); +extern long _IQ15mpyI32int(long A, long B); +extern long _IQ14mpyI32int(long A, long B); +extern long _IQ13mpyI32int(long A, long B); +extern long _IQ12mpyI32int(long A, long B); +extern long _IQ11mpyI32int(long A, long B); +extern long _IQ10mpyI32int(long A, long B); +extern long _IQ9mpyI32int(long A, long B); +extern long _IQ8mpyI32int(long A, long B); +extern long _IQ7mpyI32int(long A, long B); +extern long _IQ6mpyI32int(long A, long B); +extern long _IQ5mpyI32int(long A, long B); +extern long _IQ4mpyI32int(long A, long B); +extern long _IQ3mpyI32int(long A, long B); +extern long _IQ2mpyI32int(long A, long B); +extern long _IQ1mpyI32int(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32int(A, B) _IQ30mpyI32int(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32int(A, B) _IQ29mpyI32int(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32int(A, B) _IQ28mpyI32int(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32int(A, B) _IQ27mpyI32int(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32int(A, B) _IQ26mpyI32int(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32int(A, B) _IQ25mpyI32int(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32int(A, B) _IQ24mpyI32int(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32int(A, B) _IQ23mpyI32int(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32int(A, B) _IQ22mpyI32int(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32int(A, B) _IQ21mpyI32int(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32int(A, B) _IQ20mpyI32int(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32int(A, B) _IQ19mpyI32int(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32int(A, B) _IQ18mpyI32int(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32int(A, B) _IQ17mpyI32int(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32int(A, B) _IQ16mpyI32int(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32int(A, B) _IQ15mpyI32int(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32int(A, B) _IQ14mpyI32int(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32int(A, B) _IQ13mpyI32int(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32int(A, B) _IQ12mpyI32int(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32int(A, B) _IQ11mpyI32int(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32int(A, B) _IQ10mpyI32int(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32int(A, B) _IQ9mpyI32int(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32int(A, B) _IQ8mpyI32int(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32int(A, B) _IQ7mpyI32int(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32int(A, B) _IQ6mpyI32int(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32int(A, B) _IQ5mpyI32int(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32int(A, B) _IQ4mpyI32int(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32int(A, B) _IQ3mpyI32int(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32int(A, B) _IQ2mpyI32int(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32int(A, B) _IQ1mpyI32int(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32frac(long A, long B); +extern long _IQ29mpyI32frac(long A, long B); +extern long _IQ28mpyI32frac(long A, long B); +extern long _IQ27mpyI32frac(long A, long B); +extern long _IQ26mpyI32frac(long A, long B); +extern long _IQ25mpyI32frac(long A, long B); +extern long _IQ24mpyI32frac(long A, long B); +extern long _IQ23mpyI32frac(long A, long B); +extern long _IQ22mpyI32frac(long A, long B); +extern long _IQ21mpyI32frac(long A, long B); +extern long _IQ20mpyI32frac(long A, long B); +extern long _IQ19mpyI32frac(long A, long B); +extern long _IQ18mpyI32frac(long A, long B); +extern long _IQ17mpyI32frac(long A, long B); +extern long _IQ16mpyI32frac(long A, long B); +extern long _IQ15mpyI32frac(long A, long B); +extern long _IQ14mpyI32frac(long A, long B); +extern long _IQ13mpyI32frac(long A, long B); +extern long _IQ12mpyI32frac(long A, long B); +extern long _IQ11mpyI32frac(long A, long B); +extern long _IQ10mpyI32frac(long A, long B); +extern long _IQ9mpyI32frac(long A, long B); +extern long _IQ8mpyI32frac(long A, long B); +extern long _IQ7mpyI32frac(long A, long B); +extern long _IQ6mpyI32frac(long A, long B); +extern long _IQ5mpyI32frac(long A, long B); +extern long _IQ4mpyI32frac(long A, long B); +extern long _IQ3mpyI32frac(long A, long B); +extern long _IQ2mpyI32frac(long A, long B); +extern long _IQ1mpyI32frac(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32frac(A, B) _IQ30mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32frac(A, B) _IQ29mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32frac(A, B) _IQ28mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32frac(A, B) _IQ27mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32frac(A, B) _IQ26mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32frac(A, B) _IQ25mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32frac(A, B) _IQ24mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32frac(A, B) _IQ23mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32frac(A, B) _IQ22mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32frac(A, B) _IQ21mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32frac(A, B) _IQ20mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32frac(A, B) _IQ19mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32frac(A, B) _IQ18mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32frac(A, B) _IQ17mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32frac(A, B) _IQ16mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32frac(A, B) _IQ15mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32frac(A, B) _IQ14mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32frac(A, B) _IQ13mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32frac(A, B) _IQ12mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32frac(A, B) _IQ11mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32frac(A, B) _IQ10mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32frac(A, B) _IQ9mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32frac(A, B) _IQ8mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32frac(A, B) _IQ7mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32frac(A, B) _IQ6mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32frac(A, B) _IQ5mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32frac(A, B) _IQ4mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32frac(A, B) _IQ3mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32frac(A, B) _IQ2mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32frac(A, B) _IQ1mpyI32frac(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mag(long A, long B); +extern long _IQ29mag(long A, long B); +extern long _IQ28mag(long A, long B); +extern long _IQ27mag(long A, long B); +extern long _IQ26mag(long A, long B); +extern long _IQ25mag(long A, long B); +extern long _IQ24mag(long A, long B); +extern long _IQ23mag(long A, long B); +extern long _IQ22mag(long A, long B); +extern long _IQ21mag(long A, long B); +extern long _IQ20mag(long A, long B); +extern long _IQ19mag(long A, long B); +extern long _IQ18mag(long A, long B); +extern long _IQ17mag(long A, long B); +extern long _IQ16mag(long A, long B); +extern long _IQ15mag(long A, long B); +extern long _IQ14mag(long A, long B); +extern long _IQ13mag(long A, long B); +extern long _IQ12mag(long A, long B); +extern long _IQ11mag(long A, long B); +extern long _IQ10mag(long A, long B); +extern long _IQ9mag(long A, long B); +extern long _IQ8mag(long A, long B); +extern long _IQ7mag(long A, long B); +extern long _IQ6mag(long A, long B); +extern long _IQ5mag(long A, long B); +extern long _IQ4mag(long A, long B); +extern long _IQ3mag(long A, long B); +extern long _IQ2mag(long A, long B); +extern long _IQ1mag(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmag(A, B) _IQ30mag(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmag(A, B) _IQ29mag(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmag(A, B) _IQ28mag(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmag(A, B) _IQ27mag(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmag(A, B) _IQ26mag(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmag(A, B) _IQ25mag(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmag(A, B) _IQ24mag(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmag(A, B) _IQ23mag(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmag(A, B) _IQ22mag(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmag(A, B) _IQ21mag(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmag(A, B) _IQ20mag(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmag(A, B) _IQ19mag(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmag(A, B) _IQ18mag(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmag(A, B) _IQ17mag(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmag(A, B) _IQ16mag(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmag(A, B) _IQ15mag(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmag(A, B) _IQ14mag(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmag(A, B) _IQ13mag(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmag(A, B) _IQ12mag(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmag(A, B) _IQ11mag(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmag(A, B) _IQ10mag(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmag(A, B) _IQ9mag(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmag(A, B) _IQ8mag(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmag(A, B) _IQ7mag(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmag(A, B) _IQ6mag(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmag(A, B) _IQ5mag(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmag(A, B) _IQ4mag(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmag(A, B) _IQ3mag(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmag(A, B) _IQ2mag(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmag(A, B) _IQ1mag(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _atoIQN(const char *A, long q_value); +#define _atoIQ(A) _atoIQN(A, GLOBAL_Q) +#define _atoIQ30(A) _atoIQN(A, 30) +#define _atoIQ29(A) _atoIQN(A, 29) +#define _atoIQ28(A) _atoIQN(A, 28) +#define _atoIQ27(A) _atoIQN(A, 27) +#define _atoIQ26(A) _atoIQN(A, 26) +#define _atoIQ25(A) _atoIQN(A, 25) +#define _atoIQ24(A) _atoIQN(A, 24) +#define _atoIQ23(A) _atoIQN(A, 23) +#define _atoIQ22(A) _atoIQN(A, 22) +#define _atoIQ21(A) _atoIQN(A, 21) +#define _atoIQ20(A) _atoIQN(A, 20) +#define _atoIQ19(A) _atoIQN(A, 19) +#define _atoIQ18(A) _atoIQN(A, 18) +#define _atoIQ17(A) _atoIQN(A, 17) +#define _atoIQ16(A) _atoIQN(A, 16) +#define _atoIQ15(A) _atoIQN(A, 15) +#define _atoIQ14(A) _atoIQN(A, 14) +#define _atoIQ13(A) _atoIQN(A, 13) +#define _atoIQ12(A) _atoIQN(A, 12) +#define _atoIQ11(A) _atoIQN(A, 11) +#define _atoIQ10(A) _atoIQN(A, 10) +#define _atoIQ9(A) _atoIQN(A, 9) +#define _atoIQ8(A) _atoIQN(A, 8) +#define _atoIQ7(A) _atoIQN(A, 7) +#define _atoIQ6(A) _atoIQN(A, 6) +#define _atoIQ5(A) _atoIQN(A, 5) +#define _atoIQ4(A) _atoIQN(A, 4) +#define _atoIQ3(A) _atoIQN(A, 3) +#define _atoIQ2(A) _atoIQN(A, 2) +#define _atoIQ1(A) _atoIQN(A, 1) +//--------------------------------------------------------------------------- +extern int __IQNtoa(char *A, const char *B, long C, int D); +extern int _IQ30toa(char *A, const char *B, long C); +extern int _IQ29toa(char *A, const char *B, long C); +extern int _IQ28toa(char *A, const char *B, long C); +extern int _IQ27toa(char *A, const char *B, long C); +extern int _IQ26toa(char *A, const char *B, long C); +extern int _IQ25toa(char *A, const char *B, long C); +extern int _IQ24toa(char *A, const char *B, long C); +extern int _IQ23toa(char *A, const char *B, long C); +extern int _IQ22toa(char *A, const char *B, long C); +extern int _IQ21toa(char *A, const char *B, long C); +extern int _IQ20toa(char *A, const char *B, long C); +extern int _IQ19toa(char *A, const char *B, long C); +extern int _IQ18toa(char *A, const char *B, long C); +extern int _IQ17toa(char *A, const char *B, long C); +extern int _IQ16toa(char *A, const char *B, long C); +extern int _IQ15toa(char *A, const char *B, long C); +extern int _IQ14toa(char *A, const char *B, long C); +extern int _IQ13toa(char *A, const char *B, long C); +extern int _IQ12toa(char *A, const char *B, long C); +extern int _IQ11toa(char *A, const char *B, long C); +extern int _IQ10toa(char *A, const char *B, long C); +extern int _IQ9toa(char *A, const char *B, long C); +extern int _IQ8toa(char *A, const char *B, long C); +extern int _IQ7toa(char *A, const char *B, long C); +extern int _IQ6toa(char *A, const char *B, long C); +extern int _IQ5toa(char *A, const char *B, long C); +extern int _IQ4toa(char *A, const char *B, long C); +extern int _IQ3toa(char *A, const char *B, long C); +extern int _IQ2toa(char *A, const char *B, long C); +extern int _IQ1toa(char *A, const char *B, long C); + + +#define _IQ30toa(A, B, C) __IQNtoa(A, B, C, 30); +#define _IQ29toa(A, B, C) __IQNtoa(A, B, C, 29); +#define _IQ28toa(A, B, C) __IQNtoa(A, B, C, 28); +#define _IQ27toa(A, B, C) __IQNtoa(A, B, C, 27); +#define _IQ26toa(A, B, C) __IQNtoa(A, B, C, 26); +#define _IQ25toa(A, B, C) __IQNtoa(A, B, C, 25); +#define _IQ24toa(A, B, C) __IQNtoa(A, B, C, 24); +#define _IQ23toa(A, B, C) __IQNtoa(A, B, C, 23); +#define _IQ21toa(A, B, C) __IQNtoa(A, B, C, 21); +#define _IQ22toa(A, B, C) __IQNtoa(A, B, C, 22); +#define _IQ20toa(A, B, C) __IQNtoa(A, B, C, 20); +#define _IQ19toa(A, B, C) __IQNtoa(A, B, C, 19); +#define _IQ18toa(A, B, C) __IQNtoa(A, B, C, 18); +#define _IQ17toa(A, B, C) __IQNtoa(A, B, C, 17); +#define _IQ16toa(A, B, C) __IQNtoa(A, B, C, 16); +#define _IQ15toa(A, B, C) __IQNtoa(A, B, C, 15); +#define _IQ14toa(A, B, C) __IQNtoa(A, B, C, 14); +#define _IQ13toa(A, B, C) __IQNtoa(A, B, C, 13); +#define _IQ12toa(A, B, C) __IQNtoa(A, B, C, 12); +#define _IQ11toa(A, B, C) __IQNtoa(A, B, C, 11); +#define _IQ10toa(A, B, C) __IQNtoa(A, B, C, 10); +#define _IQ9toa(A, B, C) __IQNtoa(A, B, C, 9); +#define _IQ8toa(A, B, C) __IQNtoa(A, B, C, 8); +#define _IQ7toa(A, B, C) __IQNtoa(A, B, C, 7); +#define _IQ6toa(A, B, C) __IQNtoa(A, B, C, 6); +#define _IQ5toa(A, B, C) __IQNtoa(A, B, C, 5); +#define _IQ4toa(A, B, C) __IQNtoa(A, B, C, 4); +#define _IQ3toa(A, B, C) __IQNtoa(A, B, C, 3); +#define _IQ2toa(A, B, C) __IQNtoa(A, B, C, 2); +#define _IQ1toa(A, B, C) __IQNtoa(A, B, C, 1); + + +#if GLOBAL_Q == 30 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 30) +#endif +#if GLOBAL_Q == 29 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 29) +#endif +#if GLOBAL_Q == 28 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 28) +#endif +#if GLOBAL_Q == 27 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 27) +#endif +#if GLOBAL_Q == 26 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 26) +#endif +#if GLOBAL_Q == 25 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 25) +#endif +#if GLOBAL_Q == 24 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 24) +#endif +#if GLOBAL_Q == 23 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 23) +#endif +#if GLOBAL_Q == 22 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 22) +#endif +#if GLOBAL_Q == 21 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 21) +#endif +#if GLOBAL_Q == 20 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 20) +#endif +#if GLOBAL_Q == 19 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 19) +#endif +#if GLOBAL_Q == 18 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 18) +#endif +#if GLOBAL_Q == 17 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 17) +#endif +#if GLOBAL_Q == 16 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 16) +#endif +#if GLOBAL_Q == 15 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 15) +#endif +#if GLOBAL_Q == 14 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 14) +#endif +#if GLOBAL_Q == 13 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 13) +#endif +#if GLOBAL_Q == 12 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 12) +#endif +#if GLOBAL_Q == 11 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 11) +#endif +#if GLOBAL_Q == 10 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 10) +#endif +#if GLOBAL_Q == 9 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 9) +#endif +#if GLOBAL_Q == 8 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 8) +#endif +#if GLOBAL_Q == 7 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 7) +#endif +#if GLOBAL_Q == 6 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 6) +#endif +#if GLOBAL_Q == 5 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 5) +#endif +#if GLOBAL_Q == 4 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 4) +#endif +#if GLOBAL_Q == 3 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 3) +#endif +#if GLOBAL_Q == 2 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 2) +#endif +#if GLOBAL_Q == 1 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 1) +#endif +//--------------------------------------------------------------------------- +#define _IQabs(A) labs(A) +#define _IQ30abs(A) labs(A) +#define _IQ29abs(A) labs(A) +#define _IQ28abs(A) labs(A) +#define _IQ27abs(A) labs(A) +#define _IQ26abs(A) labs(A) +#define _IQ25abs(A) labs(A) +#define _IQ24abs(A) labs(A) +#define _IQ23abs(A) labs(A) +#define _IQ22abs(A) labs(A) +#define _IQ21abs(A) labs(A) +#define _IQ20abs(A) labs(A) +#define _IQ19abs(A) labs(A) +#define _IQ18abs(A) labs(A) +#define _IQ17abs(A) labs(A) +#define _IQ16abs(A) labs(A) +#define _IQ15abs(A) labs(A) +#define _IQ14abs(A) labs(A) +#define _IQ13abs(A) labs(A) +#define _IQ12abs(A) labs(A) +#define _IQ11abs(A) labs(A) +#define _IQ10abs(A) labs(A) +#define _IQ9abs(A) labs(A) +#define _IQ8abs(A) labs(A) +#define _IQ7abs(A) labs(A) +#define _IQ6abs(A) labs(A) +#define _IQ5abs(A) labs(A) +#define _IQ4abs(A) labs(A) +#define _IQ3abs(A) labs(A) +#define _IQ2abs(A) labs(A) +#define _IQ1abs(A) labs(A) +//########################################################################### +#else // MATH_TYPE == FLOAT_MATH +//########################################################################### +// If FLOAT_MATH is used, the IQmath library function are replaced by +// equivalent floating point operations: +//=========================================================================== +typedef float _iq; +typedef float _iq30; +typedef float _iq29; +typedef float _iq28; +typedef float _iq27; +typedef float _iq26; +typedef float _iq25; +typedef float _iq24; +typedef float _iq23; +typedef float _iq22; +typedef float _iq21; +typedef float _iq20; +typedef float _iq19; +typedef float _iq18; +typedef float _iq17; +typedef float _iq16; +typedef float _iq15; +typedef float _iq14; +typedef float _iq13; +typedef float _iq12; +typedef float _iq11; +typedef float _iq10; +typedef float _iq9; +typedef float _iq8; +typedef float _iq7; +typedef float _iq6; +typedef float _iq5; +typedef float _iq4; +typedef float _iq3; +typedef float _iq2; +typedef float _iq1; +//--------------------------------------------------------------------------- +#define _IQ(A) (A) +#define _IQ30(A) (A) +#define _IQ29(A) (A) +#define _IQ28(A) (A) +#define _IQ27(A) (A) +#define _IQ26(A) (A) +#define _IQ25(A) (A) +#define _IQ24(A) (A) +#define _IQ23(A) (A) +#define _IQ22(A) (A) +#define _IQ21(A) (A) +#define _IQ20(A) (A) +#define _IQ19(A) (A) +#define _IQ18(A) (A) +#define _IQ17(A) (A) +#define _IQ16(A) (A) +#define _IQ15(A) (A) +#define _IQ14(A) (A) +#define _IQ13(A) (A) +#define _IQ12(A) (A) +#define _IQ10(A) (A) +#define _IQ9(A) (A) +#define _IQ8(A) (A) +#define _IQ7(A) (A) +#define _IQ6(A) (A) +#define _IQ5(A) (A) +#define _IQ4(A) (A) +#define _IQ3(A) (A) +#define _IQ2(A) (A) +#define _IQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoF(A) (A) +#define _IQ30toF(A) (A) +#define _IQ29toF(A) (A) +#define _IQ28toF(A) (A) +#define _IQ27toF(A) (A) +#define _IQ26toF(A) (A) +#define _IQ25toF(A) (A) +#define _IQ24toF(A) (A) +#define _IQ23toF(A) (A) +#define _IQ22toF(A) (A) +#define _IQ21toF(A) (A) +#define _IQ20toF(A) (A) +#define _IQ19toF(A) (A) +#define _IQ18toF(A) (A) +#define _IQ17toF(A) (A) +#define _IQ16toF(A) (A) +#define _IQ15toF(A) (A) +#define _IQ14toF(A) (A) +#define _IQ13toF(A) (A) +#define _IQ12toF(A) (A) +#define _IQ11toF(A) (A) +#define _IQ10toF(A) (A) +#define _IQ9toF(A) (A) +#define _IQ8toF(A) (A) +#define _IQ7toF(A) (A) +#define _IQ6toF(A) (A) +#define _IQ5toF(A) (A) +#define _IQ4toF(A) (A) +#define _IQ3toF(A) (A) +#define _IQ2toF(A) (A) +#define _IQ1toF(A) (A) +//--------------------------------------------------------------------------- +extern float _satf(float A, float Pos, float Neg); +#define _IQsat(A, Pos, Neg) _satf(A, Pos, Neg) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) (A) +#define _IQtoIQ29(A) (A) +#define _IQtoIQ28(A) (A) +#define _IQtoIQ27(A) (A) +#define _IQtoIQ26(A) (A) +#define _IQtoIQ25(A) (A) +#define _IQtoIQ24(A) (A) +#define _IQtoIQ23(A) (A) +#define _IQtoIQ22(A) (A) +#define _IQtoIQ21(A) (A) +#define _IQtoIQ20(A) (A) +#define _IQtoIQ19(A) (A) +#define _IQtoIQ18(A) (A) +#define _IQtoIQ17(A) (A) +#define _IQtoIQ16(A) (A) +#define _IQtoIQ15(A) (A) +#define _IQtoIQ14(A) (A) +#define _IQtoIQ13(A) (A) +#define _IQtoIQ12(A) (A) +#define _IQtoIQ11(A) (A) +#define _IQtoIQ10(A) (A) +#define _IQtoIQ9(A) (A) +#define _IQtoIQ8(A) (A) +#define _IQtoIQ7(A) (A) +#define _IQtoIQ6(A) (A) +#define _IQtoIQ5(A) (A) +#define _IQtoIQ4(A) (A) +#define _IQtoIQ3(A) (A) +#define _IQtoIQ2(A) (A) +#define _IQtoIQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQ30toIQ(A) (A) +#define _IQ29toIQ(A) (A) +#define _IQ28toIQ(A) (A) +#define _IQ27toIQ(A) (A) +#define _IQ26toIQ(A) (A) +#define _IQ25toIQ(A) (A) +#define _IQ24toIQ(A) (A) +#define _IQ23toIQ(A) (A) +#define _IQ22toIQ(A) (A) +#define _IQ21toIQ(A) (A) +#define _IQ20toIQ(A) (A) +#define _IQ19toIQ(A) (A) +#define _IQ18toIQ(A) (A) +#define _IQ17toIQ(A) (A) +#define _IQ16toIQ(A) (A) +#define _IQ15toIQ(A) (A) +#define _IQ14toIQ(A) (A) +#define _IQ13toIQ(A) (A) +#define _IQ12toIQ(A) (A) +#define _IQ11toIQ(A) (A) +#define _IQ10toIQ(A) (A) +#define _IQ9toIQ(A) (A) +#define _IQ8toIQ(A) (A) +#define _IQ7toIQ(A) (A) +#define _IQ6toIQ(A) (A) +#define _IQ5toIQ(A) (A) +#define _IQ4toIQ(A) (A) +#define _IQ3toIQ(A) (A) +#define _IQ2toIQ(A) (A) +#define _IQ1toIQ(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoQ15(A) (short) ((long)((A) * 32768.0L)) +#define _IQtoQ14(A) (short) ((long)((A) * 16384.0L)) +#define _IQtoQ13(A) (short) ((long)((A) * 8192.0L)) +#define _IQtoQ12(A) (short) ((long)((A) * 4096.0L)) +#define _IQtoQ11(A) (short) ((long)((A) * 2048.0L)) +#define _IQtoQ10(A) (short) ((long)((A) * 1024.0L)) +#define _IQtoQ9(A) (short) ((long)((A) * 512.0L)) +#define _IQtoQ8(A) (short) ((long)((A) * 256.0L)) +#define _IQtoQ7(A) (short) ((long)((A) * 128.0L)) +#define _IQtoQ6(A) (short) ((long)((A) * 64.0L)) +#define _IQtoQ5(A) (short) ((long)((A) * 32.0L)) +#define _IQtoQ4(A) (short) ((long)((A) * 16.0L)) +#define _IQtoQ3(A) (short) ((long)((A) * 8.0L)) +#define _IQtoQ2(A) (short) ((long)((A) * 4.0L)) +#define _IQtoQ1(A) (short) ((long)((A) * 2.0L)) + +//--------------------------------------------------------------------------- +#define _Q15toIQ(A) (((float) (A)) * 0.000030518) +#define _Q14toIQ(A) (((float) (A)) * 0.000061035) +#define _Q13toIQ(A) (((float) (A)) * 0.000122070) +#define _Q12toIQ(A) (((float) (A)) * 0.000244141) +#define _Q11toIQ(A) (((float) (A)) * 0.000488281) +#define _Q10toIQ(A) (((float) (A)) * 0.000976563) +#define _Q9toIQ(A) (((float) (A)) * 0.001953125) +#define _Q8toIQ(A) (((float) (A)) * 0.003906250) +#define _Q7toIQ(A) (((float) (A)) * 0.007812500) +#define _Q6toIQ(A) (((float) (A)) * 0.015625000) +#define _Q5toIQ(A) (((float) (A)) * 0.031250000) +#define _Q4toIQ(A) (((float) (A)) * 0.062500000) +#define _Q3toIQ(A) (((float) (A)) * 0.125000000) +#define _Q2toIQ(A) (((float) (A)) * 0.250000000) +#define _Q1toIQ(A) (((float) (A)) * 0.500000000) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) ((A) * (B)) +#define _IQ30mpy(A,B) ((A) * (B)) +#define _IQ29mpy(A,B) ((A) * (B)) +#define _IQ28mpy(A,B) ((A) * (B)) +#define _IQ27mpy(A,B) ((A) * (B)) +#define _IQ26mpy(A,B) ((A) * (B)) +#define _IQ25mpy(A,B) ((A) * (B)) +#define _IQ24mpy(A,B) ((A) * (B)) +#define _IQ23mpy(A,B) ((A) * (B)) +#define _IQ22mpy(A,B) ((A) * (B)) +#define _IQ21mpy(A,B) ((A) * (B)) +#define _IQ20mpy(A,B) ((A) * (B)) +#define _IQ19mpy(A,B) ((A) * (B)) +#define _IQ18mpy(A,B) ((A) * (B)) +#define _IQ17mpy(A,B) ((A) * (B)) +#define _IQ16mpy(A,B) ((A) * (B)) +#define _IQ15mpy(A,B) ((A) * (B)) +#define _IQ14mpy(A,B) ((A) * (B)) +#define _IQ13mpy(A,B) ((A) * (B)) +#define _IQ12mpy(A,B) ((A) * (B)) +#define _IQ11mpy(A,B) ((A) * (B)) +#define _IQ10mpy(A,B) ((A) * (B)) +#define _IQ9mpy(A,B) ((A) * (B)) +#define _IQ8mpy(A,B) ((A) * (B)) +#define _IQ7mpy(A,B) ((A) * (B)) +#define _IQ6mpy(A,B) ((A) * (B)) +#define _IQ5mpy(A,B) ((A) * (B)) +#define _IQ4mpy(A,B) ((A) * (B)) +#define _IQ3mpy(A,B) ((A) * (B)) +#define _IQ2mpy(A,B) ((A) * (B)) +#define _IQ1mpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrmpy(A,B) ((A) * (B)) +#define _IQ30rmpy(A,B) ((A) * (B)) +#define _IQ29rmpy(A,B) ((A) * (B)) +#define _IQ28rmpy(A,B) ((A) * (B)) +#define _IQ27rmpy(A,B) ((A) * (B)) +#define _IQ26rmpy(A,B) ((A) * (B)) +#define _IQ25rmpy(A,B) ((A) * (B)) +#define _IQ24rmpy(A,B) ((A) * (B)) +#define _IQ23rmpy(A,B) ((A) * (B)) +#define _IQ22rmpy(A,B) ((A) * (B)) +#define _IQ21rmpy(A,B) ((A) * (B)) +#define _IQ20rmpy(A,B) ((A) * (B)) +#define _IQ19rmpy(A,B) ((A) * (B)) +#define _IQ18rmpy(A,B) ((A) * (B)) +#define _IQ17rmpy(A,B) ((A) * (B)) +#define _IQ16rmpy(A,B) ((A) * (B)) +#define _IQ15rmpy(A,B) ((A) * (B)) +#define _IQ14rmpy(A,B) ((A) * (B)) +#define _IQ13rmpy(A,B) ((A) * (B)) +#define _IQ12rmpy(A,B) ((A) * (B)) +#define _IQ11rmpy(A,B) ((A) * (B)) +#define _IQ10rmpy(A,B) ((A) * (B)) +#define _IQ9rmpy(A,B) ((A) * (B)) +#define _IQ8rmpy(A,B) ((A) * (B)) +#define _IQ7rmpy(A,B) ((A) * (B)) +#define _IQ6rmpy(A,B) ((A) * (B)) +#define _IQ5rmpy(A,B) ((A) * (B)) +#define _IQ4rmpy(A,B) ((A) * (B)) +#define _IQ3rmpy(A,B) ((A) * (B)) +#define _IQ2rmpy(A,B) ((A) * (B)) +#define _IQ1rmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrsmpy(A,B) ((A) * (B)) +#define _IQ30rsmpy(A,B) ((A) * (B)) +#define _IQ29rsmpy(A,B) ((A) * (B)) +#define _IQ28rsmpy(A,B) ((A) * (B)) +#define _IQ27rsmpy(A,B) ((A) * (B)) +#define _IQ26rsmpy(A,B) ((A) * (B)) +#define _IQ25rsmpy(A,B) ((A) * (B)) +#define _IQ24rsmpy(A,B) ((A) * (B)) +#define _IQ23rsmpy(A,B) ((A) * (B)) +#define _IQ22rsmpy(A,B) ((A) * (B)) +#define _IQ21rsmpy(A,B) ((A) * (B)) +#define _IQ20rsmpy(A,B) ((A) * (B)) +#define _IQ19rsmpy(A,B) ((A) * (B)) +#define _IQ18rsmpy(A,B) ((A) * (B)) +#define _IQ17rsmpy(A,B) ((A) * (B)) +#define _IQ16rsmpy(A,B) ((A) * (B)) +#define _IQ15rsmpy(A,B) ((A) * (B)) +#define _IQ14rsmpy(A,B) ((A) * (B)) +#define _IQ13rsmpy(A,B) ((A) * (B)) +#define _IQ12rsmpy(A,B) ((A) * (B)) +#define _IQ11rsmpy(A,B) ((A) * (B)) +#define _IQ10rsmpy(A,B) ((A) * (B)) +#define _IQ9rsmpy(A,B) ((A) * (B)) +#define _IQ8rsmpy(A,B) ((A) * (B)) +#define _IQ7rsmpy(A,B) ((A) * (B)) +#define _IQ6rsmpy(A,B) ((A) * (B)) +#define _IQ5rsmpy(A,B) ((A) * (B)) +#define _IQ4rsmpy(A,B) ((A) * (B)) +#define _IQ3rsmpy(A,B) ((A) * (B)) +#define _IQ2rsmpy(A,B) ((A) * (B)) +#define _IQ1rsmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQdiv(A,B) ((A) / (B)) +#define _IQ30div(A,B) ((A) / (B)) +#define _IQ29div(A,B) ((A) / (B)) +#define _IQ28div(A,B) ((A) / (B)) +#define _IQ27div(A,B) ((A) / (B)) +#define _IQ26div(A,B) ((A) / (B)) +#define _IQ25div(A,B) ((A) / (B)) +#define _IQ24div(A,B) ((A) / (B)) +#define _IQ23div(A,B) ((A) / (B)) +#define _IQ22div(A,B) ((A) / (B)) +#define _IQ21div(A,B) ((A) / (B)) +#define _IQ20div(A,B) ((A) / (B)) +#define _IQ19div(A,B) ((A) / (B)) +#define _IQ18div(A,B) ((A) / (B)) +#define _IQ17div(A,B) ((A) / (B)) +#define _IQ16div(A,B) ((A) / (B)) +#define _IQ15div(A,B) ((A) / (B)) +#define _IQ14div(A,B) ((A) / (B)) +#define _IQ13div(A,B) ((A) / (B)) +#define _IQ12div(A,B) ((A) / (B)) +#define _IQ11div(A,B) ((A) / (B)) +#define _IQ10div(A,B) ((A) / (B)) +#define _IQ9div(A,B) ((A) / (B)) +#define _IQ8div(A,B) ((A) / (B)) +#define _IQ7div(A,B) ((A) / (B)) +#define _IQ6div(A,B) ((A) / (B)) +#define _IQ5div(A,B) ((A) / (B)) +#define _IQ4div(A,B) ((A) / (B)) +#define _IQ3div(A,B) ((A) / (B)) +#define _IQ2div(A,B) ((A) / (B)) +#define _IQ1div(A,B) ((A) / (B)) +//--------------------------------------------------------------------------- +#define _IQsin(A) sin(A) +#define _IQ30sin(A) sin(A) +#define _IQ29sin(A) sin(A) +#define _IQ28sin(A) sin(A) +#define _IQ27sin(A) sin(A) +#define _IQ26sin(A) sin(A) +#define _IQ25sin(A) sin(A) +#define _IQ24sin(A) sin(A) +#define _IQ23sin(A) sin(A) +#define _IQ22sin(A) sin(A) +#define _IQ21sin(A) sin(A) +#define _IQ20sin(A) sin(A) +#define _IQ19sin(A) sin(A) +#define _IQ18sin(A) sin(A) +#define _IQ17sin(A) sin(A) +#define _IQ16sin(A) sin(A) +#define _IQ15sin(A) sin(A) +#define _IQ14sin(A) sin(A) +#define _IQ13sin(A) sin(A) +#define _IQ12sin(A) sin(A) +#define _IQ11sin(A) sin(A) +#define _IQ10sin(A) sin(A) +#define _IQ9sin(A) sin(A) +#define _IQ8sin(A) sin(A) +#define _IQ7sin(A) sin(A) +#define _IQ6sin(A) sin(A) +#define _IQ5sin(A) sin(A) +#define _IQ4sin(A) sin(A) +#define _IQ3sin(A) sin(A) +#define _IQ2sin(A) sin(A) +#define _IQ1sin(A) sin(A) +//--------------------------------------------------------------------------- +#define _IQsinPU(A) sin((A)*6.283185307) +#define _IQ30sinPU(A) sin((A)*6.283185307) +#define _IQ29sinPU(A) sin((A)*6.283185307) +#define _IQ28sinPU(A) sin((A)*6.283185307) +#define _IQ27sinPU(A) sin((A)*6.283185307) +#define _IQ26sinPU(A) sin((A)*6.283185307) +#define _IQ25sinPU(A) sin((A)*6.283185307) +#define _IQ24sinPU(A) sin((A)*6.283185307) +#define _IQ23sinPU(A) sin((A)*6.283185307) +#define _IQ22sinPU(A) sin((A)*6.283185307) +#define _IQ21sinPU(A) sin((A)*6.283185307) +#define _IQ20sinPU(A) sin((A)*6.283185307) +#define _IQ19sinPU(A) sin((A)*6.283185307) +#define _IQ18sinPU(A) sin((A)*6.283185307) +#define _IQ17sinPU(A) sin((A)*6.283185307) +#define _IQ16sinPU(A) sin((A)*6.283185307) +#define _IQ15sinPU(A) sin((A)*6.283185307) +#define _IQ14sinPU(A) sin((A)*6.283185307) +#define _IQ13sinPU(A) sin((A)*6.283185307) +#define _IQ12sinPU(A) sin((A)*6.283185307) +#define _IQ11sinPU(A) sin((A)*6.283185307) +#define _IQ10sinPU(A) sin((A)*6.283185307) +#define _IQ9sinPU(A) sin((A)*6.283185307) +#define _IQ8sinPU(A) sin((A)*6.283185307) +#define _IQ7sinPU(A) sin((A)*6.283185307) +#define _IQ6sinPU(A) sin((A)*6.283185307) +#define _IQ5sinPU(A) sin((A)*6.283185307) +#define _IQ4sinPU(A) sin((A)*6.283185307) +#define _IQ3sinPU(A) sin((A)*6.283185307) +#define _IQ2sinPU(A) sin((A)*6.283185307) +#define _IQ1sinPU(A) sin((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQasin(A) asin(A) +#define _IQ29asin(A) asin(A) +#define _IQ28asin(A) asin(A) +#define _IQ27asin(A) asin(A) +#define _IQ26asin(A) asin(A) +#define _IQ25asin(A) asin(A) +#define _IQ24asin(A) asin(A) +#define _IQ23asin(A) asin(A) +#define _IQ22asin(A) asin(A) +#define _IQ21asin(A) asin(A) +#define _IQ20asin(A) asin(A) +#define _IQ19asin(A) asin(A) +#define _IQ18asin(A) asin(A) +#define _IQ17asin(A) asin(A) +#define _IQ16asin(A) asin(A) +#define _IQ15asin(A) asin(A) +#define _IQ14asin(A) asin(A) +#define _IQ13asin(A) asin(A) +#define _IQ12asin(A) asin(A) +#define _IQ11asin(A) asin(A) +#define _IQ10asin(A) asin(A) +#define _IQ9asin(A) asin(A) +#define _IQ8asin(A) asin(A) +#define _IQ7asin(A) asin(A) +#define _IQ6asin(A) asin(A) +#define _IQ5asin(A) asin(A) +#define _IQ4asin(A) asin(A) +#define _IQ3asin(A) asin(A) +#define _IQ2asin(A) asin(A) +#define _IQ1asin(A) asin(A) +//--------------------------------------------------------------------------- +#define _IQcos(A) cos(A) +#define _IQ30cos(A) cos(A) +#define _IQ29cos(A) cos(A) +#define _IQ28cos(A) cos(A) +#define _IQ27cos(A) cos(A) +#define _IQ26cos(A) cos(A) +#define _IQ25cos(A) cos(A) +#define _IQ24cos(A) cos(A) +#define _IQ23cos(A) cos(A) +#define _IQ22cos(A) cos(A) +#define _IQ21cos(A) cos(A) +#define _IQ20cos(A) cos(A) +#define _IQ19cos(A) cos(A) +#define _IQ18cos(A) cos(A) +#define _IQ17cos(A) cos(A) +#define _IQ16cos(A) cos(A) +#define _IQ15cos(A) cos(A) +#define _IQ14cos(A) cos(A) +#define _IQ13cos(A) cos(A) +#define _IQ12cos(A) cos(A) +#define _IQ11cos(A) cos(A) +#define _IQ10cos(A) cos(A) +#define _IQ9cos(A) cos(A) +#define _IQ8cos(A) cos(A) +#define _IQ7cos(A) cos(A) +#define _IQ6cos(A) cos(A) +#define _IQ5cos(A) cos(A) +#define _IQ4cos(A) cos(A) +#define _IQ3cos(A) cos(A) +#define _IQ2cos(A) cos(A) +#define _IQ1cos(A) cos(A) +//--------------------------------------------------------------------------- +#define _IQcosPU(A) cos((A)*6.283185307) +#define _IQ30cosPU(A) cos((A)*6.283185307) +#define _IQ29cosPU(A) cos((A)*6.283185307) +#define _IQ28cosPU(A) cos((A)*6.283185307) +#define _IQ27cosPU(A) cos((A)*6.283185307) +#define _IQ26cosPU(A) cos((A)*6.283185307) +#define _IQ25cosPU(A) cos((A)*6.283185307) +#define _IQ24cosPU(A) cos((A)*6.283185307) +#define _IQ23cosPU(A) cos((A)*6.283185307) +#define _IQ22cosPU(A) cos((A)*6.283185307) +#define _IQ21cosPU(A) cos((A)*6.283185307) +#define _IQ20cosPU(A) cos((A)*6.283185307) +#define _IQ19cosPU(A) cos((A)*6.283185307) +#define _IQ18cosPU(A) cos((A)*6.283185307) +#define _IQ17cosPU(A) cos((A)*6.283185307) +#define _IQ16cosPU(A) cos((A)*6.283185307) +#define _IQ15cosPU(A) cos((A)*6.283185307) +#define _IQ14cosPU(A) cos((A)*6.283185307) +#define _IQ13cosPU(A) cos((A)*6.283185307) +#define _IQ12cosPU(A) cos((A)*6.283185307) +#define _IQ11cosPU(A) cos((A)*6.283185307) +#define _IQ10cosPU(A) cos((A)*6.283185307) +#define _IQ9cosPU(A) cos((A)*6.283185307) +#define _IQ8cosPU(A) cos((A)*6.283185307) +#define _IQ7cosPU(A) cos((A)*6.283185307) +#define _IQ6cosPU(A) cos((A)*6.283185307) +#define _IQ5cosPU(A) cos((A)*6.283185307) +#define _IQ4cosPU(A) cos((A)*6.283185307) +#define _IQ3cosPU(A) cos((A)*6.283185307) +#define _IQ2cosPU(A) cos((A)*6.283185307) +#define _IQ1cosPU(A) cos((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQacos(A) acos(A) +#define _IQ29acos(A) acos(A) +#define _IQ28acos(A) acos(A) +#define _IQ27acos(A) acos(A) +#define _IQ26acos(A) acos(A) +#define _IQ25acos(A) acos(A) +#define _IQ24acos(A) acos(A) +#define _IQ23acos(A) acos(A) +#define _IQ22acos(A) acos(A) +#define _IQ21acos(A) acos(A) +#define _IQ20acos(A) acos(A) +#define _IQ19acos(A) acos(A) +#define _IQ18acos(A) acos(A) +#define _IQ17acos(A) acos(A) +#define _IQ16acos(A) acos(A) +#define _IQ15acos(A) acos(A) +#define _IQ14acos(A) acos(A) +#define _IQ13acos(A) acos(A) +#define _IQ12acos(A) acos(A) +#define _IQ11acos(A) acos(A) +#define _IQ10acos(A) acos(A) +#define _IQ9acos(A) acos(A) +#define _IQ8acos(A) acos(A) +#define _IQ7acos(A) acos(A) +#define _IQ6acos(A) acos(A) +#define _IQ5acos(A) acos(A) +#define _IQ4acos(A) acos(A) +#define _IQ3acos(A) acos(A) +#define _IQ2acos(A) acos(A) +#define _IQ1acos(A) acos(A) +//--------------------------------------------------------------------------- +#define _IQatan(A) atan(A) +#define _IQ30atan(A) atan(A) +#define _IQ29atan(A) atan(A) +#define _IQ28atan(A) atan(A) +#define _IQ27atan(A) atan(A) +#define _IQ26atan(A) atan(A) +#define _IQ25atan(A) atan(A) +#define _IQ24atan(A) atan(A) +#define _IQ23atan(A) atan(A) +#define _IQ22atan(A) atan(A) +#define _IQ21atan(A) atan(A) +#define _IQ20atan(A) atan(A) +#define _IQ19atan(A) atan(A) +#define _IQ18atan(A) atan(A) +#define _IQ17atan(A) atan(A) +#define _IQ16atan(A) atan(A) +#define _IQ15atan(A) atan(A) +#define _IQ14atan(A) atan(A) +#define _IQ13atan(A) atan(A) +#define _IQ12atan(A) atan(A) +#define _IQ11atan(A) atan(A) +#define _IQ10atan(A) atan(A) +#define _IQ9atan(A) atan(A) +#define _IQ8atan(A) atan(A) +#define _IQ7atan(A) atan(A) +#define _IQ6atan(A) atan(A) +#define _IQ5atan(A) atan(A) +#define _IQ4atan(A) atan(A) +#define _IQ3atan(A) atan(A) +#define _IQ2atan(A) atan(A) +#define _IQ1atan(A) atan(A) +//--------------------------------------------------------------------------- +#define _IQatan2(A,B) atan2(A,B) +#define _IQ30atan2(A,B) atan2(A,B) +#define _IQ29atan2(A,B) atan2(A,B) +#define _IQ28atan2(A,B) atan2(A,B) +#define _IQ27atan2(A,B) atan2(A,B) +#define _IQ26atan2(A,B) atan2(A,B) +#define _IQ25atan2(A,B) atan2(A,B) +#define _IQ24atan2(A,B) atan2(A,B) +#define _IQ23atan2(A,B) atan2(A,B) +#define _IQ22atan2(A,B) atan2(A,B) +#define _IQ21atan2(A,B) atan2(A,B) +#define _IQ20atan2(A,B) atan2(A,B) +#define _IQ19atan2(A,B) atan2(A,B) +#define _IQ18atan2(A,B) atan2(A,B) +#define _IQ17atan2(A,B) atan2(A,B) +#define _IQ16atan2(A,B) atan2(A,B) +#define _IQ15atan2(A,B) atan2(A,B) +#define _IQ14atan2(A,B) atan2(A,B) +#define _IQ13atan2(A,B) atan2(A,B) +#define _IQ12atan2(A,B) atan2(A,B) +#define _IQ11atan2(A,B) atan2(A,B) +#define _IQ10atan2(A,B) atan2(A,B) +#define _IQ9atan2(A,B) atan2(A,B) +#define _IQ8atan2(A,B) atan2(A,B) +#define _IQ7atan2(A,B) atan2(A,B) +#define _IQ6atan2(A,B) atan2(A,B) +#define _IQ5atan2(A,B) atan2(A,B) +#define _IQ4atan2(A,B) atan2(A,B) +#define _IQ3atan2(A,B) atan2(A,B) +#define _IQ2atan2(A,B) atan2(A,B) +#define _IQ1atan2(A,B) atan2(A,B) +//--------------------------------------------------------------------------- +#define _IQatan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ30atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ29atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ28atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ27atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ26atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ25atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ24atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ23atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ22atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ21atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ20atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ19atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ18atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ17atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ16atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ15atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ14atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ13atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ12atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ11atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ10atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ9atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ8atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ7atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ6atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ5atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ4atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ3atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ2atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ1atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +//--------------------------------------------------------------------------- +#define _IQsqrt(A) sqrt(A) +#define _IQ30sqrt(A) sqrt(A) +#define _IQ29sqrt(A) sqrt(A) +#define _IQ28sqrt(A) sqrt(A) +#define _IQ27sqrt(A) sqrt(A) +#define _IQ26sqrt(A) sqrt(A) +#define _IQ25sqrt(A) sqrt(A) +#define _IQ24sqrt(A) sqrt(A) +#define _IQ23sqrt(A) sqrt(A) +#define _IQ22sqrt(A) sqrt(A) +#define _IQ21sqrt(A) sqrt(A) +#define _IQ20sqrt(A) sqrt(A) +#define _IQ19sqrt(A) sqrt(A) +#define _IQ18sqrt(A) sqrt(A) +#define _IQ17sqrt(A) sqrt(A) +#define _IQ16sqrt(A) sqrt(A) +#define _IQ15sqrt(A) sqrt(A) +#define _IQ14sqrt(A) sqrt(A) +#define _IQ13sqrt(A) sqrt(A) +#define _IQ12sqrt(A) sqrt(A) +#define _IQ11sqrt(A) sqrt(A) +#define _IQ10sqrt(A) sqrt(A) +#define _IQ9sqrt(A) sqrt(A) +#define _IQ8sqrt(A) sqrt(A) +#define _IQ7sqrt(A) sqrt(A) +#define _IQ6sqrt(A) sqrt(A) +#define _IQ5sqrt(A) sqrt(A) +#define _IQ4sqrt(A) sqrt(A) +#define _IQ3sqrt(A) sqrt(A) +#define _IQ2sqrt(A) sqrt(A) +#define _IQ1sqrt(A) sqrt(A) +//--------------------------------------------------------------------------- +#define _IQisqrt(A) (1.0/sqrt(A)) +#define _IQ30isqrt(A) (1.0/sqrt(A)) +#define _IQ29isqrt(A) (1.0/sqrt(A)) +#define _IQ28isqrt(A) (1.0/sqrt(A)) +#define _IQ27isqrt(A) (1.0/sqrt(A)) +#define _IQ26isqrt(A) (1.0/sqrt(A)) +#define _IQ25isqrt(A) (1.0/sqrt(A)) +#define _IQ24isqrt(A) (1.0/sqrt(A)) +#define _IQ23isqrt(A) (1.0/sqrt(A)) +#define _IQ22isqrt(A) (1.0/sqrt(A)) +#define _IQ21isqrt(A) (1.0/sqrt(A)) +#define _IQ20isqrt(A) (1.0/sqrt(A)) +#define _IQ19isqrt(A) (1.0/sqrt(A)) +#define _IQ18isqrt(A) (1.0/sqrt(A)) +#define _IQ17isqrt(A) (1.0/sqrt(A)) +#define _IQ16isqrt(A) (1.0/sqrt(A)) +#define _IQ15isqrt(A) (1.0/sqrt(A)) +#define _IQ14isqrt(A) (1.0/sqrt(A)) +#define _IQ13isqrt(A) (1.0/sqrt(A)) +#define _IQ12isqrt(A) (1.0/sqrt(A)) +#define _IQ11isqrt(A) (1.0/sqrt(A)) +#define _IQ10isqrt(A) (1.0/sqrt(A)) +#define _IQ9isqrt(A) (1.0/sqrt(A)) +#define _IQ8isqrt(A) (1.0/sqrt(A)) +#define _IQ7isqrt(A) (1.0/sqrt(A)) +#define _IQ6isqrt(A) (1.0/sqrt(A)) +#define _IQ5isqrt(A) (1.0/sqrt(A)) +#define _IQ4isqrt(A) (1.0/sqrt(A)) +#define _IQ3isqrt(A) (1.0/sqrt(A)) +#define _IQ2isqrt(A) (1.0/sqrt(A)) +#define _IQ1isqrt(A) (1.0/sqrt(A)) +//--------------------------------------------------------------------------- +#define _IQexp(A) exp(A) +#define _IQ30exp(A) exp(A) +#define _IQ29exp(A) exp(A) +#define _IQ28exp(A) exp(A) +#define _IQ27exp(A) exp(A) +#define _IQ26exp(A) exp(A) +#define _IQ25exp(A) exp(A) +#define _IQ24exp(A) exp(A) +#define _IQ23exp(A) exp(A) +#define _IQ22exp(A) exp(A) +#define _IQ21exp(A) exp(A) +#define _IQ20exp(A) exp(A) +#define _IQ19exp(A) exp(A) +#define _IQ18exp(A) exp(A) +#define _IQ17exp(A) exp(A) +#define _IQ16exp(A) exp(A) +#define _IQ15exp(A) exp(A) +#define _IQ14exp(A) exp(A) +#define _IQ13exp(A) exp(A) +#define _IQ12exp(A) exp(A) +#define _IQ11exp(A) exp(A) +#define _IQ10exp(A) exp(A) +#define _IQ9exp(A) exp(A) +#define _IQ8exp(A) exp(A) +#define _IQ7exp(A) exp(A) +#define _IQ6exp(A) exp(A) +#define _IQ5exp(A) exp(A) +#define _IQ4exp(A) exp(A) +#define _IQ3exp(A) exp(A) +#define _IQ2exp(A) exp(A) +#define _IQ1exp(A) exp(A) +//--------------------------------------------------------------------------- +#define _IQint(A) ((long) (A)) +#define _IQ30int(A) ((long) (A)) +#define _IQ29int(A) ((long) (A)) +#define _IQ28int(A) ((long) (A)) +#define _IQ27int(A) ((long) (A)) +#define _IQ26int(A) ((long) (A)) +#define _IQ25int(A) ((long) (A)) +#define _IQ24int(A) ((long) (A)) +#define _IQ23int(A) ((long) (A)) +#define _IQ22int(A) ((long) (A)) +#define _IQ21int(A) ((long) (A)) +#define _IQ20int(A) ((long) (A)) +#define _IQ19int(A) ((long) (A)) +#define _IQ18int(A) ((long) (A)) +#define _IQ17int(A) ((long) (A)) +#define _IQ16int(A) ((long) (A)) +#define _IQ15int(A) ((long) (A)) +#define _IQ14int(A) ((long) (A)) +#define _IQ13int(A) ((long) (A)) +#define _IQ12int(A) ((long) (A)) +#define _IQ11int(A) ((long) (A)) +#define _IQ10int(A) ((long) (A)) +#define _IQ9int(A) ((long) (A)) +#define _IQ8int(A) ((long) (A)) +#define _IQ7int(A) ((long) (A)) +#define _IQ6int(A) ((long) (A)) +#define _IQ5int(A) ((long) (A)) +#define _IQ4int(A) ((long) (A)) +#define _IQ3int(A) ((long) (A)) +#define _IQ2int(A) ((long) (A)) +#define _IQ1int(A) ((long) (A)) +//--------------------------------------------------------------------------- +#define _IQfrac(A) ((A) - (float)((long) (A))) +#define _IQ30frac(A) ((A) - (float)((long) (A))) +#define _IQ29frac(A) ((A) - (float)((long) (A))) +#define _IQ28frac(A) ((A) - (float)((long) (A))) +#define _IQ27frac(A) ((A) - (float)((long) (A))) +#define _IQ26frac(A) ((A) - (float)((long) (A))) +#define _IQ25frac(A) ((A) - (float)((long) (A))) +#define _IQ24frac(A) ((A) - (float)((long) (A))) +#define _IQ23frac(A) ((A) - (float)((long) (A))) +#define _IQ22frac(A) ((A) - (float)((long) (A))) +#define _IQ21frac(A) ((A) - (float)((long) (A))) +#define _IQ20frac(A) ((A) - (float)((long) (A))) +#define _IQ19frac(A) ((A) - (float)((long) (A))) +#define _IQ18frac(A) ((A) - (float)((long) (A))) +#define _IQ17frac(A) ((A) - (float)((long) (A))) +#define _IQ16frac(A) ((A) - (float)((long) (A))) +#define _IQ15frac(A) ((A) - (float)((long) (A))) +#define _IQ14frac(A) ((A) - (float)((long) (A))) +#define _IQ13frac(A) ((A) - (float)((long) (A))) +#define _IQ12frac(A) ((A) - (float)((long) (A))) +#define _IQ11frac(A) ((A) - (float)((long) (A))) +#define _IQ10frac(A) ((A) - (float)((long) (A))) +#define _IQ9frac(A) ((A) - (float)((long) (A))) +#define _IQ8frac(A) ((A) - (float)((long) (A))) +#define _IQ7frac(A) ((A) - (float)((long) (A))) +#define _IQ6frac(A) ((A) - (float)((long) (A))) +#define _IQ5frac(A) ((A) - (float)((long) (A))) +#define _IQ4frac(A) ((A) - (float)((long) (A))) +#define _IQ3frac(A) ((A) - (float)((long) (A))) +#define _IQ2frac(A) ((A) - (float)((long) (A))) +#define _IQ1frac(A) ((A) - (float)((long) (A))) +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ30mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ29mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ28mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ27mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ26mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ25mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ24mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ23mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ22mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ21mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ20mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ19mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ18mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ17mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ16mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ15mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ14mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ13mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ12mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ11mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ10mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ9mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ8mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ7mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ6mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ5mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ4mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ3mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ2mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ1mpyIQX(A, IQA, B, IQB) ((A)*(B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A) * (float) (B)) +#define _IQ30mpyI32(A,B) ((A) * (float) (B)) +#define _IQ29mpyI32(A,B) ((A) * (float) (B)) +#define _IQ28mpyI32(A,B) ((A) * (float) (B)) +#define _IQ27mpyI32(A,B) ((A) * (float) (B)) +#define _IQ26mpyI32(A,B) ((A) * (float) (B)) +#define _IQ25mpyI32(A,B) ((A) * (float) (B)) +#define _IQ24mpyI32(A,B) ((A) * (float) (B)) +#define _IQ23mpyI32(A,B) ((A) * (float) (B)) +#define _IQ22mpyI32(A,B) ((A) * (float) (B)) +#define _IQ21mpyI32(A,B) ((A) * (float) (B)) +#define _IQ20mpyI32(A,B) ((A) * (float) (B)) +#define _IQ19mpyI32(A,B) ((A) * (float) (B)) +#define _IQ18mpyI32(A,B) ((A) * (float) (B)) +#define _IQ17mpyI32(A,B) ((A) * (float) (B)) +#define _IQ16mpyI32(A,B) ((A) * (float) (B)) +#define _IQ15mpyI32(A,B) ((A) * (float) (B)) +#define _IQ14mpyI32(A,B) ((A) * (float) (B)) +#define _IQ13mpyI32(A,B) ((A) * (float) (B)) +#define _IQ12mpyI32(A,B) ((A) * (float) (B)) +#define _IQ11mpyI32(A,B) ((A) * (float) (B)) +#define _IQ10mpyI32(A,B) ((A) * (float) (B)) +#define _IQ9mpyI32(A,B) ((A) * (float) (B)) +#define _IQ8mpyI32(A,B) ((A) * (float) (B)) +#define _IQ7mpyI32(A,B) ((A) * (float) (B)) +#define _IQ6mpyI32(A,B) ((A) * (float) (B)) +#define _IQ5mpyI32(A,B) ((A) * (float) (B)) +#define _IQ4mpyI32(A,B) ((A) * (float) (B)) +#define _IQ3mpyI32(A,B) ((A) * (float) (B)) +#define _IQ2mpyI32(A,B) ((A) * (float) (B)) +#define _IQ1mpyI32(A,B) ((A) * (float) (B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ30mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ29mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ28mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ27mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ26mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ25mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ24mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ23mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ22mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ21mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ20mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ19mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ18mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ17mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ16mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ15mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ14mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ13mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ12mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ11mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ10mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ9mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ8mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ7mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ6mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ5mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ4mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ3mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ2mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ1mpyI32int(A,B) ((long) ((A) * (float) (B))) +//--------------------------------------------------------------------------- +#define _IQmpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ30mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ29mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ28mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ27mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ26mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ25mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ24mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ23mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ22mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ21mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ20mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ19mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ18mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ17mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ16mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ15mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ14mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ13mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ12mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ11mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ10mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ9mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ8mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ7mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ6mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ5mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ4mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ3mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ2mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ1mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +//--------------------------------------------------------------------------- +#define _IQmag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ30mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ29mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ28mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ27mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ26mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ25mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ24mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ23mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ22mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ21mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ20mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ19mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ18mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ17mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ16mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ15mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ14mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ13mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ12mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ11mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ10mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ9mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ8mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ7mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ6mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ5mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ4mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ3mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ2mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ1mag(A,B) sqrt((A)*(A) + (B)*(B)) +//--------------------------------------------------------------------------- +#define _atoIQ(A) atof(A) +#define _atoIQ30(A) atof(A) +#define _atoIQ29(A) atof(A) +#define _atoIQ28(A) atof(A) +#define _atoIQ27(A) atof(A) +#define _atoIQ26(A) atof(A) +#define _atoIQ25(A) atof(A) +#define _atoIQ24(A) atof(A) +#define _atoIQ23(A) atof(A) +#define _atoIQ22(A) atof(A) +#define _atoIQ21(A) atof(A) +#define _atoIQ20(A) atof(A) +#define _atoIQ19(A) atof(A) +#define _atoIQ18(A) atof(A) +#define _atoIQ17(A) atof(A) +#define _atoIQ16(A) atof(A) +#define _atoIQ15(A) atof(A) +#define _atoIQ14(A) atof(A) +#define _atoIQ13(A) atof(A) +#define _atoIQ12(A) atof(A) +#define _atoIQ11(A) atof(A) +#define _atoIQ10(A) atof(A) +#define _atoIQ9(A) atof(A) +#define _atoIQ8(A) atof(A) +#define _atoIQ7(A) atof(A) +#define _atoIQ6(A) atof(A) +#define _atoIQ5(A) atof(A) +#define _atoIQ4(A) atof(A) +#define _atoIQ3(A) atof(A) +#define _atoIQ2(A) atof(A) +#define _atoIQ1(A) atof(A) +//--------------------------------------------------------------------------- +#define _IQtoa(A, B, C) sprintf(A, B, C) +#define _IQ30toa(A, B, C) sprintf(A, B, C) +#define _IQ29toa(A, B, C) sprintf(A, B, C) +#define _IQ28toa(A, B, C) sprintf(A, B, C) +#define _IQ27toa(A, B, C) sprintf(A, B, C) +#define _IQ26toa(A, B, C) sprintf(A, B, C) +#define _IQ25toa(A, B, C) sprintf(A, B, C) +#define _IQ24toa(A, B, C) sprintf(A, B, C) +#define _IQ23toa(A, B, C) sprintf(A, B, C) +#define _IQ22toa(A, B, C) sprintf(A, B, C) +#define _IQ21toa(A, B, C) sprintf(A, B, C) +#define _IQ20toa(A, B, C) sprintf(A, B, C) +#define _IQ19toa(A, B, C) sprintf(A, B, C) +#define _IQ18toa(A, B, C) sprintf(A, B, C) +#define _IQ17toa(A, B, C) sprintf(A, B, C) +#define _IQ16toa(A, B, C) sprintf(A, B, C) +#define _IQ15toa(A, B, C) sprintf(A, B, C) +#define _IQ14toa(A, B, C) sprintf(A, B, C) +#define _IQ13toa(A, B, C) sprintf(A, B, C) +#define _IQ12toa(A, B, C) sprintf(A, B, C) +#define _IQ11toa(A, B, C) sprintf(A, B, C) +#define _IQ10toa(A, B, C) sprintf(A, B, C) +#define _IQ9toa(A, B, C) sprintf(A, B, C) +#define _IQ8toa(A, B, C) sprintf(A, B, C) +#define _IQ7toa(A, B, C) sprintf(A, B, C) +#define _IQ6toa(A, B, C) sprintf(A, B, C) +#define _IQ5toa(A, B, C) sprintf(A, B, C) +#define _IQ4toa(A, B, C) sprintf(A, B, C) +#define _IQ3toa(A, B, C) sprintf(A, B, C) +#define _IQ2toa(A, B, C) sprintf(A, B, C) +#define _IQ1toa(A, B, C) sprintf(A, B, C) +//--------------------------------------------------------------------------- +#define _IQabs(A) fabs(A) +#define _IQ30abs(A) fabs(A) +#define _IQ29abs(A) fabs(A) +#define _IQ28abs(A) fabs(A) +#define _IQ27abs(A) fabs(A) +#define _IQ26abs(A) fabs(A) +#define _IQ25abs(A) fabs(A) +#define _IQ24abs(A) fabs(A) +#define _IQ23abs(A) fabs(A) +#define _IQ22abs(A) fabs(A) +#define _IQ21abs(A) fabs(A) +#define _IQ20abs(A) fabs(A) +#define _IQ19abs(A) fabs(A) +#define _IQ18abs(A) fabs(A) +#define _IQ17abs(A) fabs(A) +#define _IQ16abs(A) fabs(A) +#define _IQ15abs(A) fabs(A) +#define _IQ14abs(A) fabs(A) +#define _IQ13abs(A) fabs(A) +#define _IQ12abs(A) fabs(A) +#define _IQ11abs(A) fabs(A) +#define _IQ10abs(A) fabs(A) +#define _IQ9abs(A) fabs(A) +#define _IQ8abs(A) fabs(A) +#define _IQ7abs(A) fabs(A) +#define _IQ6abs(A) fabs(A) +#define _IQ5abs(A) fabs(A) +#define _IQ4abs(A) fabs(A) +#define _IQ3abs(A) fabs(A) +#define _IQ2abs(A) fabs(A) +#define _IQ1abs(A) fabs(A) +//########################################################################### +#endif // No more. +//########################################################################### + +#endif /* __IQMATHLIB_H_INCLUDED__ */ diff --git a/v120/DSP2833x_common/include/SFO.h b/v120/DSP2833x_common/include/SFO.h new file mode 100644 index 0000000..f698526 --- /dev/null +++ b/v120/DSP2833x_common/include/SFO.h @@ -0,0 +1,52 @@ +//########################################################################### +// +// FILE: SFO.H +// +// TITLE: Scale Factor Optimizer Library Interface Header +// +// +//########################################################################### +// +// Ver | dd mmm yyyy | Who | Description of changes +// =====|=============|======|=============================================== +// 0.01| 09 Jan 2004 | TI | New module +//########################################################################### + + +//============================================================================ +// Description: This header provides the function call interface +// for the scale factor optimizer for the 'F2833x. +//============================================================================ + + +//============================================================================ +// Multiple include Guard +//============================================================================ +#ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___ +#define __4090522384024n8273240x3438jx43087401r34ru32r0___ + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +extern "C" { +#endif + + +//============================================================================ +// Function prototypes for MEP SFO +//============================================================================ +void SFO_MepEn(int nEpwmModule); +void SFO_MepDis(int nEpwmModule); + +//============================================================================ +// Multiple include Guard +//============================================================================ +#endif // End: Multiple include Guard + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +} +#endif /* extern "C" */ diff --git a/v120/DSP2833x_common/include/SFO_V5.h b/v120/DSP2833x_common/include/SFO_V5.h new file mode 100644 index 0000000..2374f03 --- /dev/null +++ b/v120/DSP2833x_common/include/SFO_V5.h @@ -0,0 +1,70 @@ + +//########################################################################### +// +// FILE: SFO_V5.H +// +// TITLE: Scale Factor Optimizer Library V5 Interface Header +// +// +//########################################################################### +// +// Ver | dd mmm yyyy | Who | Description of changes +// =====|=============|======|=============================================== +// 0.01| 09 Jan 2004 | TI | New module +// 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels +//########################################################################### + + +//============================================================================ +// Description: This header provides the function call interface +// for the scale factor optimizer V5. For more +// information on the SFO function usage and +// limitations, see the HRPWM Reference Guide +// (spru924) on the TI website. +//============================================================================ + + +//============================================================================ +// Multiple include Guard +//============================================================================ +#ifndef _SFO_V5_H +#define _SFO_V5_H + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +extern "C" { +#endif + +//============================================================================ +// USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1 +//============================================================================ +#define PWM_CH 7 // Equal # of HRPWM channels PLUS 1 + // i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc. + +//============================================================================ +// Function prototypes for MEP SFO +//============================================================================ + +int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function +int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function + +//============================================================================ +// Useful Defines when Using SFO Functions +//============================================================================ +#define SFO_INCOMPLETE 0 +#define SFO_COMPLETE 1 +#define SFO_OUTRANGE_ERROR 2 + +//============================================================================ +// Multiple include Guard +//============================================================================ +#endif // End: Multiple include Guard + +//============================================================================ +// C++ namespace +//============================================================================ +#ifdef __cplusplus +} +#endif /* extern "C" */ diff --git a/v120/DSP2833x_common/lib/IQmath.lib b/v120/DSP2833x_common/lib/IQmath.lib new file mode 100644 index 0000000000000000000000000000000000000000..340caf0fb9b332ce03fd9fac2de1947b57ae1038 GIT binary patch literal 625984 zcmeFa4SXEsb^m*2rPazZB9ffQN+NA!Ng+ZIVXfA0f|A7;LJ|Um5QV%{wqZ>`0b4Od zA~Z`#mSC39Y#Q>?&@?3&9E|-B)D15;V3&Z~f}7h0Zb)fMLvKh^F2!|P*C~op_MY>d zotIth%7V0YY&8DN@w1O+W}j!~JiqfgXBVBccH@N?pWJXlXX&;$^wDjHX=mra;^e?` zj#<+n68VD2TmMxg`JBkI?~0uCgvhBaBJa3G}HWGzAkd5Uh9)enOn) zAByw3N5y&l?~Bv%oH(5iiqn0yIK9`2)BoqsKNIH#{f>XTK%D=0r#Sx^ z7iaPp;{57GiO5eSQoCIu^}mwH{2xf<=r2lS!OaqR{dXnO*(;HrT8X^nL5UoHl0+6i zDv`nU5?LCN$k3QX-gdP_R$e5L(}pB+MuSA&rN^H2bBUaLzeL_&FOd&CEs+m@Ln3Rp zNaQ1bE|K*~iEM0=$j9|MSDhh|tA8kwPhTaGYmb)5^`Df;@7|!SwoxKCoi35Dv`XY_ zdhFMKC6QZpOXT*~O5|J5N#xEuC34peiQMyqL>^2@{e*ACF7q|9z)KeyV-{tk?J#k;uR5_wR3$$blCm^5VB8@?ZB#P0f#_ zreT%T9Nj53%}+^9>-kdihM!7J#|=``8JC)#Yo+GcFG|hvS4qtYXGu*$`OwFD9ktOTUnsue~HSx9In6xlwBFyjW_! ztz+Dw*S_y~srkS3IuBkXH4o_+{_O9h=Fx|x<}be@HGidjkFSxMC(o3cztyq)gI@a| zbsRtWrPMqZk(z()lA8bcg4Dctsnq$pQhU-dQoHg?QhWNC)V{MQu~E3NbQ#{mD=Ce@qJy#_szvpyIIG#MaOdI52W@k9p4Te-#t3M`?c=@ zy~dxOBejp{`2J#z)b7#m|Nbwe_HiBKQ*o*N@r_dZ6aCJgbxQ5?w@B^2PdXxnm$zTuY=?TkqDm@bJP z{{@LIzCxnO<0ZO$yF`CW|NgcgOLXN%iJtzHMBnu@iJtXW5`E9D5oP$2%nYY@0-%J4T}aqTj#wCldX+_U+eW|MM1!PU&?D4@q6*OHvmd zmb!)!scX7g>RMlrx;Okl>f&FJy6z^ad&}3Qu5YE(9seV#8#qbomcCQ!RwShEq&lfP zS^G}WV^7;Hb??yYy!)q8ch3D%_uf&dJO2Wy8~KdXrGGAU7ynS|F4ez(?6p$&alPJ^ zdcCXk+)wHCuGQ;p((B!z*Sk^s@_N0S^m<>_Yf^wy1zeO>VB;IPg-W6yE2-PBi%n3V$RVLi+)~W^L`<*qrNV&*DRLUg0D!d?KX+M@kWWo*GO!U z_Vx5hthZHS$NgAhi~A)u7?IeLCnPrXoWxE!Mq+Q@A+dMq@n^qNV()!OV&|`v*av?m zvELq(*xH{;>>@qxlE0GJrMF0I!??sY>OQX5zDlok^(Q6v>C+{4tzJKOyu=h2VqgA+ z#J=_eiT$CD?bcd}ZMjZjTXhWEz9X@_dnI;{9(R9>#J;Q7-uYdLJ*4|?9rL3bCH8&& z{=dFKVo!WfVt=FG{}11m*iVNf_S|bF_Aff-pPwPI|JWn3|6DJz$rmN|(xp;gGbZ(Q z!%{!5SL)}#B=tw@-twH(x85uDZ>*L2j=z%n&TmNlo4+IV$Njt1C$5(IrRPiiP^;9R ze52H#dbHG^wnOUAI7#Zyyj$wuqsN_hv()Q)sQ=(fssC-=*B&qR>0e6yC1*(er7cpw z{wGp@`HND2)l#Xy=3%M7_UlrA{RgG~#ve%i@0~04H~m8DzjBS#-~58q|IyE-{?;E! z{q1*1{T=$<+jPI{VyXWVJ@>wArT)8TN&U{a)IXe*dc6nrfAx~oKcUz8(dVW9?{)mo zTqpHE>67}O>bU;DPO1Ob9;yGg2C3iwwABAX$33b0e|<^jITy&h=-o1}{wkR_|D7_g zX^qTl{f5lz=#zPiYGq!}cV*tOi)G$hcgVcO!!j@Nk1}uBnKJLBb7bDzmdd=9^)heO zk7eH5b${2RGVkoq%e?nKE%S!A9NzoK|6S%?H8y>}Iw|uueMRQoaLnq}Yp>Ywj`y4; zt5?6{Jp+r^Ubx|MuX*_;>%Ha`Yu6{j?Q`B&{1hCnEx$K?$$0Va>#iItwl3PZ_QGQG zlJ!@3t;;{Q(Q99}_9MmK%f>$Oj=@Ce1h*qNZKHM+kKK5A&<+NyEq^efuef5v>F#L* z!8`}n`lk)74d&^#y^9R^^R$-V>(6t*pXWd@>;Zqk1D6DY81UygP(IIMM{rs&&w|I1!p>!k=fNe4fRQ z;Iv?#iO@U~{yeSa4q6UnCGBB&tx#qWH8TUXr6A{yGYWXr?vcEf1XKy zp2=XINq@k}&^(j=Jd@?~EOrE^1@laX=9%>8X)S*+!90`xJeLIXToTN4NobyK+q=jT zf1cLzd;NJX@#ncDnCB9Iz)M2&T;k7jN%=gB9l>eAJeP##xx}BRwfw;Z^IYQ3b7?To zrNKOxhUV$Ey^AdM=V>j!*PrK7f1XQ&c`o$_yfie=rT#pZmd~@;5u6sxb7^RvOZ|CT z%O6ZI&!zr6mj&}&7R+;5Xr6A{yT~$sp4Rev{dq3)=eaDH=Q4l5%R=*9=Ff9k`8p+7-?e!=woVTLB>&#ioF?q~m$U}B+p`O^x`Dwvcvr$nIRY12DLo4)Q-Y!~O1 zSnN%Vmf!15EwR{}TVk<4xx`{`sM_+!kXY=^Pg|urp4Sna=1(!PIGAH%aWLRumfGv7 zk%`6rJOdps5$Jf@4CYy)<0X6@kCr#j0e_ypj+Y2@yo9ggX)73nuj3`kbv&=bpXWd@ z&ybFn@O3;|{$N61;mFaojK*!Uj&+Z`|PrGf--bH*J zFA>u55=noazK)j&bi9PG<7q1xgs5FrlyT=NagDi9pBGW-!kZ9WUYQc(lArFZbu^>v)Mk z$4mG+p0Tm~2WlhNkodNgjhL0_ArYE$cJRSFXDX(9|(9~zK6uSFWt+9dzt?x5bYt!?hE#i?y)=OU z59D`9e3wXXUwDW7Grs8dC3hgWeYqVH+rHE;7uschnLuQRB(^WGLq3_M{+xV|OdzZS zSsfD9C6d|~)FEGtFQ$Dd9SCV(Mu$YSFQLl?beRt(5YHj$>TK z`n_wfIB)F*m#z~HJYimx^$i%*mi1vim-P*p^eO98apqs!Mqc*k3L`+wbIxh&(>5gU z62*@w9%YxQFu(zO_GO2mYnSz@{t*5$mFD4(1BPB@XJC4k^$jE{99Q9XAhg3@P+^oD zbMA(Zmp+&Z1F7(p6)qRtPoD4elQ`gvwU=IW&N~>H9X4QSP&P*_va&woDgPw@L-9!s zm^dpt0sll9TNiyHz9IO zLxaVqb(Y1@aQ}u2Mo$R!sjlgFg}iR%ec{7w^^{+&*cU!5qyqX^3)DcrE2LGG_l2(( zQdIoI0%gVT3d#QRzVOvT;?zGZ5UGAwQ6kyHDDMkjEd=`hVFB>_T@`Md+ZDQ&=g5pnUgL~Fm_)&R%p}SV$-cDZy74B@YD|Dp__jURT zsBl+{U7;&gxTn*(zrr0Yc7?7~;eJl%{L9u}aWTkwxp#xl@`2Uux#VN(OOem*c5`fK z17`z?#miSLUXdKsRPHe1d3ZRmEV0DHy@xdg^y;gRKI1dBBCi+Qnw&qB{wvm9c?F+l zCY{AU_or3h&U`3;O?k&(aQWr4I9#qN9`ug)*v$#f$ZPXQ#gG5txQ)y7zf`gByh7)^ ztvBtA*S~bf8{Z`93+{MhMAoJ?TRDDud{um9d~5H`U%R9CYp>t>XAQdshii|$_WWDk zD01G~Ti*Cqd8g8TXMzZ`mrVw#vYT+O}_48ULpZHJ8<%`0Wky2XgZbFV)Ga%`5Bv zX!wk}cW(O7aOBeShtKFO6yDxj_|)mgop#)+<4*0BYgTH{DY~Ddqx^u5cdcIQJ$n6Z zb#}g{$rrb`i`_g;$yWLfsZsh)X+o^XnG#d_ZmCy#7H6F;^R@jRIZEld(x~*k za+Lf-AxY7&c zO-e76MM~4srF5P2D7{GDtn?%D7Nr+UuhLODR_RCOIHi}$Ta{iWn&L0(WwFu?GN5!! z298IhP&&Wz`XXR9- z*UBoTIXO+~4f1xSpVK=ha--fkk>AxjC-Ql{b0T@YbNXh3-Z_yk%GpY9l5>=PN$;7+ zm-U{Bd`0h;$XE4liF{4(mdMR|w?rTD2b6wY@0Q3P%7>MHL+_Tp8=?0}y-YrT(9&8de1~2*SjV1|LEP)H#YQci9D&hz;pKh zO9gw%wi!Per_}1dI_r=(=x$Fh=;_f<_9TOzgnn98(qm85oAyx*iSVZ=~8WAfs9N|JBs(xSrOxu(G+-~gIA@2=X)Yr@8BhDy|><)uwIjH?q;jx7;UNz3%jyR)S{i95>20))8!n!WUw+v4S^p3>bm=S1V@?Y)jXG8~ods@0rV z*b?8lO`d#BK{|I2H^>PENo}b~6^!?{#GNO%)V--7&i39mX&Qdh7q-4Ny5u4K%i@AF z{4LqEDXMAr7wUfN@TS=I`0PIYMeO!e{l3Nez22(YQnPE*qT%hTv27K1eZ5Y{YP-G% ziRNPZkF{+zxm(Jy)tYi_hAGD|IOW)1Q;w~Ulw)fx1)rxJ*0ggJJ;rY-=QU76s+6+; zYTuA@>^oD=La0g1lw*2)$}xGFa@wJ$TcsS+tx`@WbP==*+5>$v^exa{Xdm===v$$t zVWpfCpr&D^9MiB;P7=BVx)f@1Ipvscm2ysmo&+^{oN`RVN;#)MS3*yPu7aKhJstXX zsA*U!=Uq^f-zn$a(6gcMftqfWa!j{M*=+_p?EgTguoY_eyHL=V_vB2QfNq8>u2etM z)Cb+{{uO&{db-(n&LsJbhmCjbsZ~cgo4bEZ5#{X60OfwiDLLklqMVH^!b-GJdz*2L zZLZ|EmT`u=8OqsaPu<o zQTsK*ZrOLPq_^aNA~5=rK3N49mkh1|7K^y}`-+Pf=#93Ob9mUepVDy}F8)yYs!4CG zaqfk>r*yY1a^lYTaAE7F)9aLO-d?jazP;`owHJ5Bx7DpxWLh$O;_z+pCkuZ(e8)?7 zoL?A^6q0|i{a?0czq;v;UcJc8TX#o?Z&M_^O>P<9QgdD*sz`RB?zawaRgA3smzDY# z_o#0U-@fVi;cc5z5wGX2;oFC|-dHEw&QGb*c+Gf39vZKe=sMmoW4|2x zqv4x|9~ytH{Kf9Ao6jq}u?!3aOw6&8q^;*jVKsJ^;i93fA%e9d+BRIUcCEJU&b8?NT5SUl+7=lHk;g&gaS(ajvDG*Z zE{{8=HI0ML<4!$o!{~7^dK`2fcMP4!^_4-RHllIIzH{8MZyN`x$DP;GZiO0BkAu-!^?3ndfc%mGVa*37zdrlo%hjxKlFU)2cRE>ei&*t@3^xXx(2!ydI8j)=D4#C zdJ*&^(2Jp$KtBq-6nYtSJ#-BEG3Z9<<IA(az0vMB3|Ar*(Hb0rs!rI>2B6z^4=r|upd&H-5jwXh>Fy(PCxF%DdF&6AV1D|9}>iu zAIqx9kEH|p7u#ID`VUloY}W^H_{fhN_3oMc_*do5KE1srKWt5;bhqu*C_lDt+SdE@ znmc=U^?pPp!A@x3(3WYYJP>-?i!Oir^C2 zw&^Q3d^LMp%{9Xx8NOX2$KHA4oqgM4X2;xKWAwIIemFZ^M-0o=NmgU=xA3j283#>i z2CJJv>1Ob`8Dwq-lbgZhW-z%KOm4;_(+nmzgT~FEaWiP#3>r5(ZF=!$Fu55tZU&8; zLE~n}{4&j8aB zPG9f;*~0{ri0)=Rb_*2&Y|#d*Uq9K(*Z+LY)6axL4C0K8?d?jrZz3vNe8;j@qIsw#MJ2drEiPyfq$P+cI#?D_+yaao(D))AsZ= z9c4{NS<_M0bd)t6Mcaz9vZMG~qpa^JD?7@{j-qo#S>I9Cca-%V#p4=fl}B0SQC4}B zRUT!PM_J`j)_0Wk9d#Dz2&0azj3_HRip~{9=Zdnvqk7L?>Dsk>Z})uWwQG3eA5&br zc4n}4Q;gX^=8&#k8(9PnvQc}R`^0U`-by`~Woh0HckPzQZWiav>sJ#oy+Dk=el3Jp zNk$JWUg0Jg7T51rbp3uum%!n(e&4S5$<}XL`RJ3n+xkuFp3>d6o$=G_Jg?%3FStI% z!J<#mWc8+3;86@@yX#SW|L`Wwdf6oB4F8R0uKa~&uKcHFuKcrHGrX;?PA#@V;SSAo z`HW_<7^fRAmAnEFYk_0ZXaUyO0_?5@&Qf}oLx-RiZ&~1+41F6k1w93N zD)cny=};x$fc;;z90p8!ir5*p+UlgT-e7!V{4z844BDl@BSBnG>EG~%zZ&UnHCwws` zc{oIZe@pL`;m~u9qsU;W@Het`_mbh)-Msx9-%%}p>xZ_! zbxYmx!`pio$ce*Sci-77P1}y!mNitG_rtB5E>uLhJ+{TSBQ_5oCBG=#9=kneXB*WU*3%YG0#o#K4yr_!0wOV(1$&P$mYx#K4yrnnnywBL>RE zK$#etM$GBtnv0-jNyNaH7@9`RF{v5@Wn!RA3`-)0B@x4th=DROP$mY-#6X!CC=+uG zWny@DV)%7pj$uvAZjygTf~c#lnRfo-WpY`(!w}5H6m7^`bT^B8CX_MmFs^9O|EtGX zkLRz&V~QwaX9g&hkr+fJtsw{JDd^WC_olrH`&|L?`V~VT6 z&J0$=uZrubc+4SP4K^|_KY}L2LD=M>tKOJWz408iC_kVUe`A-mA-y09U;upYb6?z+(Ky3p>r(C)gh9=p)-y3p>r(C)g3-F2beb)naF zq1Sbx*L7hxcA?jGq1Sa`H+G@dbvcU|iD`6QP7l<4lwIg`UFdaP=yhG_bzSH=UFdaP zSdU$3bX{n4UD#S(#Ou0<*L9)Sb)naF5w+_=yX!)`>%x-ka#DQbO6V%6*^pg!lUTp@ z|4ayB++kcXGeWo;P$@##nE^ulHnZ@rb4cZujVuC>Ys24MzVhUjb$9rG^RzhECbn+t zIYs|B6tRrAFpiJ`r)pZ|m#9N;{vrXj0?ag6x4RY!AYy`x|Z7iLG`Im5$N2 zhgLe(;?@U3^?^-&Se|`gQy=zc9|+}U&-Z~!eb}6Rpi&>!W*?~32P*YpbM}EveR#I| zK&U;Iwz^Oh~cpsK$A2`(qPW6FMeIQgH2-OEd^?^`*WEb>-Q+?zW^f{+82E(a7=k3rl zpznab3wkEhtg1fe9O!$X=R)5LwY;@HXBc`u^aIcjK|c(&?1DbB3;K9OhFG@Ego$hP z@5Z|`W1@}UKc=Y5uhE_W6W2K<#~e~jw2?(viQ4eDQmx6lO>=TL4-<{cgC6q=C?*=H z1)3E_uCxR}d7*~Vq6sb<1~1{C;M)U=hL!38EH&2}o2z?mQ8YAPxV!!i2i?p3Qig`M zz2yD}Vx)@gqCF5_RkwP$)YByqvt_5-v3sx*_JFHpJrdjR5FTaQTw})};L66;oFKrKFn$7yKS=nr6ULWpLD%Bb6%wT=E5k3Dphje|o z9z;(^;8rMUEjC=w&s+49@qWOvB?{oyY?OMe;)S_3tn(I3%))0-{86#*eiS}`R9i03+5a=4zRkhLJ~LOFf7m~!i28PBz|}R#bN`q_%GEAEdnnJ) zmAtOlaJl-;`pM_&Qj6JVVwa~k>Ss@t^|0IC>IieQ+cusqrt22%=1(b459xz-M|3z~ zw>@d&>3`SV(9XEh{C6qcZ8J^Q)m_a(_Tr@WUPT?8>S>8~p1bMKziGpJx6`<}^sP?w zw|Vb#8eacQ_u28TjrHJ&?D|Yf5!ucRc()JB`8R`iZDbC2TpRx8-c=j3r=OSy(%r1* z1Z^re!>R!~+edS(Ppck=PC|{!a(_@2ALX*erCC9rR=zgR%HhM;Cew_sBRcA%bvK^0 zd!5qVw#s~69{-<-&!6X-&!e5_&!p)!p9fW+$7}aIe*5Ra>*qo0=ec{&qlG+AEbnUqXv+-ciP*llyNxy+2+wx;}Jir8&u2K?WThsZzXkYcxu%;Cw{sJ+eQvoQacdNBs{ zK;!?*4XZ;7z&=-B0ihS1eJ_2o3bLMA^V6h5oi^r;Nei&4%F>jWw0Fy_i zXPKs9QZS{vZC+kndG2fNv5^y3tMAg&)T?E`-cI)GZC>_kG4B80HVJr4R-Xg}1jxHLmXJ6LV@zq_7in+t2t%$}9qf$H%!8=-$pafREN!3saiDLLkl zu5cS!1kSTjdz+`N1rlz$O>WP?-Av{c*Sz;aulxFL@$KE}xv+Y`^jz2~Qg6jTX}B7+=i>Eh>~dR^mZhRM zuDHdBW5kGH#PAYU&rh-S?q#VMkCf)8*tJXZQ%rtT%2Ig){gwezDNDsxddx8|VQH3% z*}kQ@D%$Z1*Rnkedj>PFM+B4QjB-VP?M?bu`e z6KpLPb7S4b8OU!woBW<(JzJE*%4Dj?%(Kpt)!xQmTw0~%T3ydyRJL?E^l*^jEA_6~ zdj6pD(MH{M@UmF?WGoP28XxUA3FIK{wINZsG>r#0|QM7<3aW=q6UsO*FHc zSV1?@%x+=@-NXvIokfhqR(>}!vfD8!)9sl5x7#sE-%XUD+c946CYsqzte~4{X18N< zsGBH3H_^;)q6FP!sdW?0>?TUkO_ZRUC_y*xAa)Za=;rOiZf=jQa@%Io`i%$d+0U%? zn-=09Q^XNFGr*A%#_u0Kb zz3?f0Ke^^6&9vWE_s5$5@Vmozv`Jz6m$#_r2j=CB$7nyM&%!G5nIH2pY~jb?*T=Ah zAH%=#7#8tk_%R>D;(H9c_%RUUF;Mw2?5oGP@@&?I&FA1AAy?Nd^$6LS!P=+=Uw$*z zhK5IW%yI^hucBSUD0L+FG<=!8S)ghNiJj&lgjaLDPR z-2*kvaL9QJ)bx%abiyHY!Xb3RA;)|`Lugh*Xof@RghS+y451kgp&1UL84jTt4xt$i zp&1UL84jTt4xt$ikv}p-{>Tt@DTc_f7@|7G5V<5nRHqoCHr)`_DTb&{F+_EWA*xdh zIp;Dq%OWu!po<;$zpHIp%Vd94_qp11b~j45=~ZdZ(*yn&Ytt2f;kD$4F4Q&-)uwZQ z?6nAtzND{a4bRo4n^v37dyn*gsy5wiGuEcNt)w>HZNpZZ?u%NRuJwPlHeIXw>H>X! z3`8CSk;g#fF>LiQaCr=ieGGIS!)_k~qsPGLG0=GobRHu=U<`|W42&MbZXW}w$3W^a zGX2It>M<~S42&MbdLIL+$H?~^1F6THPF;axAoUpDyD_ZyF|7A7ka`Roehj1@1F6SA z>M@Xd%vsD863{_t5^5f)F*5ze$n+ZnsmDO-F)(@zj2?4R9C-@V?AS4odJLo<1Ea^N zAT$O>k5NHr42&KFqsPGLF)(_J3PNL45E`R`&=?hj#;71PMg^fUDhQ2HL1>H|zcFVG z-@6ui0rW!XI_O2vk3cVmUIP6n^it?$(Dl$U=*OTNp_fCifPNgR4r86^mC#Q>t%A@P z6@^$st*C zNR}LuC5L3mAz5-rmK>5Lhh)hiS#n609Fir6WXT~}a!8gOk|l>^$st*CNR}LuCFgYN zTFW6>a!8gOk|l>^$st*CNR}LuC5L3mAz5-rmK>5LhhI2{4UoeI$YBHIkSsYQOAg7B zL$c(MEIA}g4#|?k2FPIp3vgD8~ zIV4LC$&y2|$6b&)M2k4deo(~$&2aV^0#`E#W%md$p6{4nWo#9kVa_l?N=M&x}X)>k8vz7a{^h@@|HI+YU}iMli*;~SCjjaXle z$oNKNd?PZx(Xss7Mr3>=(!CM8tC84CBi2_Vc2^@&mqwy4jaXcb#9JD9U$+s9s}YN< z5sRx4TdR>sOCz>cV+FmTXRbD#-v97cnwMaIIanU=3Oz=#$ABb29{p5qF=*HHH){v1 z*i0Vc%HeIhq5A2D%Su5e% zbPibKfHDsF;(#m;$l~DLaljV`d~rY)2V`-uBpmR?0bd;O#lfC%Kp6*oaljV`d&0q< za6lOclyR^m9H&!9=wL}Wpo{~)I9L)6ejNvtaX=XdOTqzV94rY3lyN{A2b6I@83&Yc zKp6+`j)Pyv0c*GcXj=O9p{T2^8PkR=_uVuw_c!}2uQ2E_?Z+%`x2JM7F3WzKt4-%= zIA`hIa5w8&txZK4g9}3$w|Vf|bcQbmM6;<)H!xS5Zob~-lzY>)X1-gSZhn>8bT6m! z*F3%E1K1)DaP?B_z4B_XvAm#rj5Dg$k*}0jWoHJq`Vmo^4&HRL0q1Jd88@Zi3eDf} zxpaDMx_iV_zIzlsjMhLcJLVox`W`sz9<1eiwAbYs`+uhRrhWHwy3fp&uJ5RLOwog6 zX9iq(B-ExG@M_Zy{5rMiKC4>XtFbnn)}=d2>(jl$w>W~@Px;~8uT`6_9kr$%8?qhk zt{oe)9qX|j?XDf|t{v^J9qq0i>#-djuO02K9qq22*j+o?T|0VRJ9=F^dR;qqV>^0X zJ9=F^c4IqwT{{|GI~rZPV;-b-^tyKRx_0!scJ#V-^tyKRx_0!scC5#CG`e;)x^|*= z?ZoTaiPyEG*R`Y9wPQoJqusTm-L+#$wqrxK6R&G0QrC_R*MY&8jxtz+7!Q3Tq@9cRf( z0ik-prXEnK2b;48RO-Rn>;aW}K&2jR&K|I-2hUay2-O2Z^%)J>XOimS+z*)dNoTfKWXk zR1XN%148wHP(Ap%dcdh3aH74(o*+(TYLk7HI<54Guf$Sdd} ztGI{kf*!I9dZKw-1Vmr|D7Un7BrJ0!)0h z)TT3tGd!Hd8*c+zBI6x{32fJ(W|v0blDzU3e(z1|8PR)u-n4*uR-6W1%XD(uW)eH=lx=|X(%+PyBHWBmqvt_2?KO}NtcJ72xE>C9I% zy*Ay$aQMS;_``7c!|=?*aQMS;_``7c!*KY+aQMS;_``7c!^DdphR+{{3ytS&o5@zT z^)OePE?mvM$ke{wJXf2}{C6qcZL3_v>#pJ3s@A4^2F~{0?KHeDeXG+vf!_O^hS$&N zK08FVEQy07viWq%H5NNFK;$E|Hr;?8fSF9;|NF?DAi|JQ?GE zFE_?K^1blzG% z)@~%5^%Qes-Njk5n$LOPLDutJZ92V+Dfd>+vNl~Ys`(0kajX1yZC-wDx(;Fm9iTu5 z5rYn}paU%EAXd;pG_!+>zH?LENB&h(QOjf(~K@9Yixb zh!u1Y&Fmmn&_S%A!!b$UK{T_&>7i{>ro*u)K?l*y4x$7dL^C^xW_A!O=pdTeL6o3_ zC_x9&%nqUi9b~C>5Y6l$O3*=+po1tu2k#(u5GCj!7q(;8e)^RyIG`T+aNNmln^#^FyV=}|17FhUlfBX7YIKJ~y+!jO{z&(q>uxpQ3|PZClPT46 z-&R;$R+}zWwKm;T@bXje@>A%3Pr=bo!O>5_(NDqAPw_oZ!O>6Yx0Y*)m2)Uq5aIa8#JmJ-*qfyS$ukPA(i+{sw)7koZo${*fW(}IfWteMi ziwU?}63sA)W|%}XOp;5IB#R`8PMAa|OrjGe(Fv32gh_P5B)KF>w812vpd>nB5}h!K zPM9QrB#CC2L?=w56DH9KlTN1&CW&U4bZneSG{dB0nqks0n=pxHm_#Q`q7x?336tcH zB+(3$Xog92!X)`4Ni@SGnqd;nFo|ZEL^DjH879#TlW2xXG{YqMBT4c{l4QFj$s$Se z##EAAk|bFqNwP?iWRWDPPLZTKMUpI%Bv~X$vPhB@v`w8Bu|s9wo&nsYgNTQIL8Rj2HJW7t=C>4Z8$?+Q{$8VGhLZeg=8l{5JC>4Z8oi*Htwa^Qo z7ed!TFM@sqdNK48=trTKLN9}^hmJu%2Hgm?+H|8-5E`X|&?pszMyVh)N(G@&DhQ2I zL1>iPbfeS}8l^VfXa#vwSsVV8e$!lSI?uaN>Lt}%BeSVZ=ZXRIo9g?#ejH>L)qva+ zi}4X(epIOxGFO}KNR%JbYST6S_tmB=l`L5#OBTtJMY3d(ELkK=7Ri!DvSg7gStLsq z$&y8~WRWacBuf^_l0~v)kt|sxOBTtJMY3d(ELkK=7Ri!DvSg7gStLsq$&z(Cb**KQ zELkK=7Ri!DvSg7gStLsq$&y8~WRWacBuf^_l0~v)kt|sxOBTtJMY3d(ELkK=7Ri!D zvSg7gStLsq$&y8~WRWacBuf^_l0~v)kt|sxOBTtJMY3d(ELkK=7Ri!DvSg7gStLsq z$&y8~WRWacBuf^_l0~v)sZE!qHeHt5bXjWCWvNYUdd}9SX5dV#P3MV} zS0arU1iPMZx4Km>k6~69to_U~-gL zT@*}?g2_=ZISM96@ykRj=%TZ&Z)I6MbG7L_1bDOF4R^DiVh)}yT0erH&`&eQ@9lu; z`8ZWH&R1(~x@sABGuNiGHEq#>nR9U_iEd1C&ZN{s=Rqy*FiBivQY;r|QY>qB zl1SYo{=!MVVUkGQBtG3qyu6cQxj2(z8F-Uowdp3sGVmtljZmw`GD&T^NwM6!Nm&Fn zkL#rLK#jvD#bWW3Vt&_2-OHu-Y}c+uisx$6d26@SvMlD`xQnr5^&TYuCSfI|%4hDDj-$u4(-_h{hTRn-_7cPT zieY!fh`Pjxy2P-!V#HfwyssO>;)-E$#jv!6RBu?Je^krCfFwX3{Zwu-XxH@GbcwmzbjJHB_Xf+(TOS%fzN9wYf@!ts znqPKpy5=gi>0Vo*Hr??WJ+LS4#db{taknX=3RC1!OcC>)l9>K!3VmaWJc=nXe3?Su zn36`?hAdO)8&l{TQ|KF0=o?df&lLK`6q?2qn#L4km_pN-64NxMqyuW2#*}nIP2ZT3 zZm99(6q?4An5Hl#CLyP!4|+V*?(~%OL(LMHLg$?l%hI0`TM1LL6uKO0oINFGCr`;q zP$g(u_P^_Uu$HYE8)Hz3&NL*`r-L3tKD(0JQ`vVuSDQ|6klvw){U>KZjabiW{ogG} z_p)l!8NL`0&89Y;`+k4f?_@92pRcW$XEmTk4x5{2^-ayQ>Q@QV#HbI4JS)qovOFu> zUU2_o-KL6duj*>rn?J?br*PY7jo+^wt2Ibv(mCA@d+6BTRIY2AoQ$T_gsFx55}IbW@{>9j80QTiswD}0M1 zT$}FtU#m7yE56}Y;&`oih+FXxx8fmgC3e?}pSTt4u@&pF6>o7Xe&SXlc&)_l zTJaXQlDXH4pSTr2aVt@~R{X@R_=#Kb5VztXZpAm;if_2p>0wl+*R|pyZY5sViuKrv z_1KDsxD^j^E7oHxc4I4cV=Ga+R^oN7#OqqI9$SgpwPHiI618i^l5EA2Y{iCbC0^G` zq^=bkvej-9QpNtCNp794f1j&O=V@{Fdy(#DJ*Q|>wKx|p0&9`arl!rRHeF(_Hl6WU z%Dt_xg4%R(5GoEf#mO#+gH3TfTX7I74mQO>r8v>6IH(kN%zqvSmExdMoETOdY>MOA zii1#b5Gqb2D-J@%iDAV-s5l4}cRIP+B4`)X?9Vva1#xgH4o=0vsW|?vI0zLdh84%Z z6$hu{;8Yy{Rves)gHv%3Dh@)$L8v$g6$hc>_`2fYR2-a&Ru4yqx5|aO8-G`-P4^%i{vaIwARPW6Jo6wN{vaIwARPW6 z9R462{vaIwARPW6-~Ax>??JwQHe79Uu(8ijlc4olUHOO=Sm@C#@c?IXV z?*`T&g^C@;|N7IK$W&}c^#6*-TyVLiMYGi?t#r)vcSdYv?vtQVB<@>LHfBR~vsnz$ zDH>|-nh>sgeJ)SW)uuE5U8;B&E7$P4Yj|_j+H_CB+1|UIQN2#-Tb8CFW|=85g8h?5#`=`O{r$Oqc(M6s{3wfFt+tb9@o@P9=;eX5hnX64_Xg;8K zLeadeHl54j=Cc^6xB~PQziD|j$>pW`xcAQfiX~dWip}+iUa#89VijAKfuTB!^M}$O zl6iDiA)Uqku>7lXDBUUV_>e4|>G*4ke+#_){X)8l2i%rimnQKxorMqoAdq4WN zoxMFZ<+-orwdty5zaFe^)$H*G(ySQEk1NfGF^$X1iZQ)DhVLMT@1Qgv z#$x6%yqhunnlXF_F?!8EqnM z?0?rQIoo_XduH~m+*n1m-+r; zN6ub5vyr*_mp1&(o}z88c4jSmTJGlACqdv8-FtG$iCI9YT#xH9}&mEm7ha5FACJY@Jv9jD3g4=QYL)ZLKTBuz?p z+w5)0t-J3j++%Os*GCF>oWDJ_{iYvi9UiMZ`PCbYZps#;ny>H|x5{hNT|2yM)A7T1 z*2^`i;lI(DlcOg-Ng+vJ!63tvlG;^V2S!xT3W-cU3u#hOhLZX=qi4rU%7j_}h%!Nb= z77`^`NR(h9?;tKDO0dv5g{vtkLzc=JXvPEf>}U4am=@w6Q`8CU%s?j?Vf_9vhg2u9 zkwxHS8@0E&Tol#`EN9Q%JRC7yEa<6Nn=bJ(YSSg=YSYzLwUZ>qiUhM+@vn|LaHp>xZxV(f|6<|N7DY`qBUTi8J-1 z`Sqju^`rUq?c>GpIniCw7`C}z<#vA zesV?nofPMu0yRyjpIniCGTZve80qKjsD3g=`l&(DPsT_;86*8SWx1E5 zk@eV$v0az9CWpPt@2RYn8qXT98WQLXF1U#QjRYE}Lmq{H zOi}XMnZYr?!~OA(Iiy;tjV!{-vw3)1SFsUzs>~X2H%}`a@;Y>85jjmi8P2JBi>vCq zwV$|j!^Zcn+jz;k%g^4JUbis}cj~>WT6=DAuJ+u8dM{JOyBj%iXI!h!Z909{wdcI| zME|F1&)qs>?YUb^YR}zD?YS>#?YTGnuhyP>LrLwqG$@<~h11yLX|Om=4qqBXPLsoz z2A9*|avEGtgUD$t@-(=d2A9+1^QA%OH0YcLoztLm8gx#B%W16hH0YehI!}YqY0x?C zbn25%gU)HtIgNFm2A$KOa~c~xjdh*|oztLm8gx#B&S|XkH0YcLoztLm8gx#B&S}s& z4f>?9&eK@uY0x>1jh-fxFAX}ULFY8MoCcTEWb&m!=QOySrb1Af3PEXbIZX~_@TJM&OH&~zO%7k09KJL;d}(J5_hBvc0;sKnG!=rd>yO@*K|6@t=K2uf2SC{2Z+G!=rX@M5!0l?%ix^&$(j2;vD+Et{>-^MeRBF#JSpYcB6HB zHOh}^wdXqj`)bdXN|p?gC4*$iAXzdkIhn3;62`ceo**=GzSF0n_ts=4#Jr9NuE_wzg%UT1MT>wdZV28^?L^ z^*U|0@Q7Elj@_rdpZ0!^+|Qcc4|ng!Tfd)`y&tdLe%AMXR`z~Y_I~_@`}v0btndA- z@BLz)-Tkcc{jBo+tn&S=^8Kvx{jBo+tnd9|>w7&wCJ@_q%@WV}Pv#lh}!$X9W&yBueLzb2qb z=u+r%sQKR=Vk{0Z76*&V!QyhTxEyRPhv0KyNq;OVZar4yoQ?Ba4XL+wk`C^#-fZrIv#MNq{{1soY}FuIaVs z2Ip$enSPrpJ_4&fx45MCT+6iDb4@S1_FPky+H(sk)Sg>hwf5Wr%>WQNK(53AqKpT` zkmUgS#sTz=1LzwE&^HcXNgP1mIDo!!0Da>C`o;nDjRWW#2hcYTplKXH(>Q>paR5!@ z0Gh@D?1=+t8V974?_C5n&G!JB#sM^q17e!O0W66FSP}=YBo2t(=>u322gKI>0p2S) zAcisrSP2KjQ09Ob${Y~m>;uF!4-h3hpr6aN7wfS#Ggo`g?nL;V6hpll{9zI9y#3wV z?2g+OSSKgB9rQ(LpHe`o@=a9d+y~__L`?p?=G<6E}p9KhHW$X?<~{6a=Z*;xUI*6SR@JIg~Vtq*N0$?~#IT$(!_pUhTQT zx!QB4`=^R`Zgy{JXx+J^^i7Rd_?AYv_S|*9R_(ba45KFEcumCdnuy~y5y5LBcGpDg zu8G)P6V_uB)?*V9ye8h(Xu^7IB6in=_1J{<*hJK>iEOo3?-Xj@19``(yU@*yiE)>u<)|XtwHT>|HWz|Bbfmh+H%= zlhxR7p1+#~M}Hd#)dn`TkzLRRHnovm&;~-aflY0oQX3fsZJ<&c-mErIsSQ+WBcq@V zY-+=^)doVfflzH^7qo#;ZDbU*flzHARGZVOBWeSu+MF)hW`DMUQ*Gc>8#vVlPPO6R zY6GF#$SY{Wztsj#wSiM@8wk|~LbZWVZ6H(|2-SwKs|}oL1E<>Xb+v(0 zZPcD?Bd?&1yn;3|iQC94Xd{!jjZES;@(S9hJ=aEdK^xfxZO$+=Iv@H0=!c*mhK@kZ z9&4L5Ca%$==W5S+m}t_>-K@vr@Tysr)SfelGd#36+x!GD`%uAyR;~8jz<`#z=nPl? zef8F!Gf$V*o@=a7d+vU$g!}bLh}@5ra6fYXer$#Nu@&w|TfZL*_I~1M_v78VAMe)v z__glGuXR5$y8H2N-Oodwja6Z9PaM3`k&BY0R)w7zSQST5?YY5#uU)%0DCM=`1m8QO z^{od6EAaWNwDz3&YPN1o3`dTwgR5acxtI36aQMA&_`UGVy>R%waQMA&_`PuWy>R%w zaQMA&_`Ucz?}g9roi$gRB!5x&nQdi@Jo(2IZDl(%;OZl%_FR#veY<(C_MG|eQo7q# zxklGr!?#wgJ@+`A?Y+NgG0(^0Ht)?%^8`K)H$M(HKW<+GXW9QVS#idd2S;Srb5e@P zc4ol4M`-Q2LBIB#v2=Ouxxu;GbH)WJ-EFJP*VAjyRp;|3;qxcK?k7R*C*kuaiMl;W zyzNOi{7I1dNpz7X(L$ai#`YvJwkH|SY&4QqJ#w!0oayHSdM8vrFRMN0vbgE!0~J?* zy$e{LS2I_8?qId&s%5_(tS;5;@?X6?8RLI1H^w~m4!(m*`7q`K_p)Lv_s+q0;AO>F z{;Px6z`<+a;N5iaYdZK29DD~3z5~bUEPWg&5h}&{{*PT zuDuKyZI;Qi+2+Dp4E9{L;N4h7wKsZgg#Ix_?aa=!d-&?AJvXRJ+Sa=!*##!~CF|X` z)t<8hrsu-W)t(!dlG=0CvSDYl#*ORDHn2(qbxLhbTH9=QcRN7)0Q`A?W2)z;9Hpmt zSt_>DOY>9g+NJp^CKD@VsaP&t^(+-z=?Cy~mS(BgdN0jY(T-QRmMt1GS9{L$uN`YQ zlFfRGxv}oz3^LUCe311#S9?zHV#>Xhv#dQ=jB38ZU)1{bYtJL^GR-8#EKmY$k5dOf<8ZxIr^K*)ciVOq8J6G5>EfQG#Zo1kK3%W}=zRj%BGe6U}TUO3+M{pqXf9 zGf{$OYR@$j&1@!0&`gw|nJ7UsIakd@37W};ZB{8?jx3e)TvzIGbG7F@95G$Y-K?i# z?YY61QG0H1uJ)XHuv5i*I=%MX7Y5r=gl6ZXce7?nJwl~E`XizCoUt-q`Q%*f zIr9OgjCpjk+H)ssHP)c^+*ws?&+UPa_rS+{(EIkFukOJj+XFZ6ft&Ym?b-0C`8yBp zad$1gQXVbMnLI*k&%v#3VsO%{Jx9ZH)p&8GS99&TlYgUY&)Ir1JbfK&qFU{_UbMho zw7_2Uzh3meUi80S^uJ#8zh3meUi80S@_z|UbE-RH zUNS~{sX@_8#z-$2BfVsd^pY{sOU6iV1#MENLTu0?Fmtu%>~559)8C6YR}c7KtUc$# zoqDgT)}BjNtUWhannB|ITFStZ!Q#)QxHUMxsx>%2r~+yM(>@$(a9*t={gLiZC^sLi z3Z-%G1-hqnx9#QE4)Wd;{hz8m_stn=&waC`_S`qAJ@?Rf`~OPiIlFJ>Eo)a#9N=I# zP)5Mu5iocJOMC<*9wCEo1Uw!ggKq>>9s!j{K;;qecm#WV1XLaYl}E_t8v&a~z~&LK zc?4`80h>oaT25wLj#+k6Cs9s!$2oK8l#2x=L8BiQC6VDkvrJc5Njf^9wmHjjYK zBVh9g*gOI@kATf1VDkvrJOVb4fXyRd^9a~Hf^9y6Z9W1vkATf1VDkvrJOVb4fXXAF z@(6i+BVh9gs60Y_pb_c=jeyD{WbloU!8byEpb_c=jZhzGg!(`u)CU@&KF|pDfkvD) z%zZ7?p5usxgh#Yl#o865M+)JgJ>Ii&Ao*vO(F zl8xHiT;I2i+4E6!cz^PHO1+=<=Vc|wyh}f6Jky1H-yiD2zxhM;JzYP(F^igW?uoOm zIk%W!3hgZZCg{y7H*PzuNsi zkPr6%Ouj)w1w(_GCD0{y8Sj{)1hO*&3ABg$d;T$pR07$^qF|ei+S^TSrGo&t!!cQ`yNjQ5FujV9Y zP2$g-#4kT7je6E3-uX$q^OJbzCwUH&czGtNK{Y80IkF9EZ=z1h8=+QpVNy&7nv^)y zDp5^JC)7A|QcSy_lpd%>-X^I;H7TYiO-disD$Pxb@$IBorp=`8Zcjw@JT&jdR|S{8goU*L~(8Zp04em>(e-V*7jTU9@*ON(NUkIyRB{G?Ue4e zd29QcaS7F!tCl%8bB(##RG8b#2=>C6ds)kS;qARdDE6|V_Y!a0%evmnir&kL-iudo zFY9_Q&tNa>dN2Oly{zuNtnR(kec3C%5|84Sb=`hPS^w}^w{O>bZ0pu)4bJcO{!0U0aIYW6jFT(sXm2NpOWJ^#-#cbm1C#GGH0jA z=$?`UZF@pfvJ|=;YPIF2QT&{LqNLQjL94pjmU*#AXKVXn5E-Hg!o^7Vxk zdba8d1|$LU=%;cELA$2E8JnD|EoZ!+Dn0?LEtf2*E!RA)w%lu8c5S)WRH-f3QlYk7 zvTAL)ePGQ#av}ENQ`?7~ybp=I4^3kq__7at*@x}04^3kqn#MjfjeTeu`;Z#@&@}de zGW*am_Mv0!L&w;Mjg8K6H$Ipv*orjeXb-`@old=otH?SMTONP-Y(}vro)+ z*oW<~58GiMD6~uLgIm6ptyc20JrY4M#+6xuo%?%cXO*<&2wBy4x0T>Gaxi zn~_+X6@NrFBeymqw>D!TZ-%orBfU0rt=Vv;efM*^&&-vs{aMPDc4okpM?!76r1y?| za;~=Apg!G{?zYXYww%_LJ4)Zgc!h6aglo%v_SdQ{*FeOsfrwoL5xWK=b`8Yp8i>+0 z5T$D%O4mR(UIVeZ24Zy$yp7R7tgeA5T?0|N2HwVKAU@YXHeLhqxd!5M4aDaf$i{0R zKG%RZwSmZ7gVUpTvVr(qgJZs<2FLWe2D0%Q9Pt zXaS*Gz@`>ZsfFBu7Eq~$+<_KQsRdMOA$On!Y-%Bcpaq0#0ijyRBWMAkTJRLNfKV+U zREyK8cfAFiYH_+~o0qEvoN585TEM9maH@r@;T908g$#lgG6-56!>JZ@x1TEB-Yax%Ig*<{5YRk2dN68; z)?*S#F|nk!oI#x7;Vf#)C4(AV{Xxwwjl2ykQPMeATW+gt?=?@C)s{QDLT$MnSP47y zNr>#gO4xy(z5`of2e!fvtb`p{usiUZ@4&mY1Mk)j{8~HkYwaM?z60;p4j%GstO|Qu z;w9Z@wkqt+JpY)Yt!rlnR>cuiTQ0=cuH9R;w%oD`eEuq}EoZ)(>9ytVhQsfM!|#T} z?}lgYhQsfM!|#T}?}o$ghQsfM!|#T}@5aY@H++6KTsRx9wm9aC0moi&5oa0+IM(6% zuN2FDyZwdIOT?c2?BwdKrzm(ty~$~Cy|8vbV0+H!l~Z14R{i+Sz=L%laM%@eo> zZr%eo@3F6ev+VzwtT>B@9vqR)r&G?mc4ol4M`&%iq+eUkSh~EnTyn0qoN+-)ciSrS z_4L|u)%pDYXYbvEBe~0a?{4i#Hj)5Ahz{=?WzmW?c!8MR^-l)6 zs_AzPyJRH&VP}l;^kGj-Gy893miGP|niTfLsDJj~(4?>@M*Xh;Mz#9is8;`*Q?4gQ zeQ{xD%ntTDn01AUJ7bjLEY%rv9mkd74Etkjcby%pw)a){O83aGQIzX_RaPT+P7rJ8 zow|AZr>_q)4EY8m6DK>=M+fdwle1wN}txVjciIC5?A;qRhQS;bnmN_ zH=mufSJHE9uFE}hWrzHIamwwpR~vg@%klt&; zHr>f~+dSJeLR}AgUn9HfjwJh>J>|Mz&#&9M$8X`Y%Q4EGVHIbP&NIX_<-1a(=V5P( zB&4`2MS5P`l_E=6sy9X2UcNV_gWpO+ihEPu%@OJO8QU&YhjkBh?JMiBa3^<8pu>7+ zUWacatC>6JqUx|#R)-{M)#32(d!Y{d9lrW~m`~F?{h=eJx#WB$J&zvOxa90Idcn2a zR2B0AzaeWqm)v*y^i4GS?iqdaOamURpY=+Tdk9g$L_Zi!uJ)U#UN%u7Xrg-AM1`P< z+CUT4%O)xWO;j(Ns1r0%y=i=t^df9{>YoaR9( zF1aSEmrYa!ny3miQ59(7>B1(e0!=(u*u>?LmTOdsa&NTX-)3i5&O6HQ$ek15h~AmU zk*gBK9}77kV}r8Ff~)-l5>xAUD8}~(kJ0*WiGi6yuc2;zz+Ps4*b6k{J#$T zzYhGr4*b6k{J#$RL^|;NI`I5D@ccUH5b2;dqyzu21OKms-jELbzYcmsI`IEG@c%m8 zc3Wo$USNkSFR%kIu)~%A*WoJi>%jl(pev*U|E~l8uftV_r-R;*4*b6k{J#!*LptyR zJLnDRpf{ugFR%kIumdl!gWix1*W+_;V7`(0!^}4^tCOt*j)@LBL^@!X=%7QSgAS1n zIz&3?5b2;pq@#p4X&-|>u8K>IOHNm#cx=p2_1X!)MlLxY?ksCnmP>AbjZ5xUyC+_7 z<2KI;6h0UFtKyP7UXe@gcoCP}apRJEwD0A??Y~wox$Q+E4Tj&2g|f4mQWZ<~Z0K2bJT*=5eq&PHY|r zq2pk4+-tD?aboj0v3VS9juWBB>D!Cbw-<-`Ck`sdLFG7odvUNi4l2iC{)xl<69<*! zbnM0H*o(vb6Q^S@PRCvx=ASssKXI6U;xPZj-G2V-TbL#PahQMNF#p71{)xl<6NmXH z4)aeO=ASssKXI6U;xPZjVg8B3{1b=yCl2#Z9Oj=m%s+9Mf8sFz#9{u4!~7F>zsXAVpP!mJveAM$&6(6n7ftI7koFxa5xXJ-&Tp?YX|ER-cNm4c4t~b-S^FOYV;UI4-$ji;~8oq_HSz zEJ_-SlE$K>u_$RQN*arj#-gOLC}}K88jF&~qNK4XX)H<_i;~8oq_HSzEJ_-SlE$K> zu_$RQN*arj#-gOLC~3Fd^eT--Nn=scSd=stC5=T%V^Pvrlr$D4jYUagQPNnHG!`X| zMM+~((pZ!<7A1{ENn=scSd=stC5=T%V^Pvrlr$D4jYUagQPNnHG!`X|MM+~((pZ!< z7A1{ENn=scSd=stC5=T%V^Pvrlr$D4jYUagQPNnHG!`WdD`y%mxil6fjYUagQPNnH zG!`X|MM+~((pZ!<7A1{ENn=scSd=stC5=T%V^Pvrlr$D4jYUagQPNnHG+c6Nxa89A z9o(I7Gk=HqyUfR!?_~Zy^ItRnfZ3+1EYMwcUX4pGv_Pt0_#-@`p7#8akK1l&feN|g zLQ`@fR>-RHVG^gtC6}wYukWuZ=92r~1#rpTZM~PuABL4T^=qm|Ud$!8NN#fx-B~27 zxyZW~$!9K-mtS<$TeC=Zev$0_BA>cQUVf1*&mv4Si;jA07U`{7q_<|#QMG2#5zE3N zOc0B(CM`OuaW6XU%sZIh$-I+UnU_UaXBHh*i5H#sFpEQB(UIIPI?B8(+O}TvtL>*z zb*#oE7izwuDu3w69@{m|m$K&iY4+QzigkFMu(6-U+GYx$WeGjZLm?&A6~-l3u2ZfO zmz;E2m9J2j8*G20E>EM&)0{btE>EM&(^M#?(dcRFZPV!WG#WjPMo*I!oaQe~qu0~u z^)&h0X|#J9?Vd)vr_t_dw0j!uo<^^y(d%hP8a?fFFiWGS;dz;Mq}S87U8v3~7hB_! z3w5?+|BSDMMOu3vF1h`pfU0rHc@j$-rMTp-yM(#q&Qfg;zngWN{RiPUwAQmPv^Y!U zJ^Z#-`2uG_g0mn&_&u%ao-O{KR&_U?1q0540ma|Ys!qD%?`GZ3k#=TjfB4<3!hrA_ zTBXBhvFc~B>Sy7SJBw963zytkxm!7cTypzsTypYgz2FXr zOYTq+mt4yRF1a^tnoI6YWw_+tQi4nFP+2ay8L(!CUWgfbdS*bD89a>{JdGJVjT!J| zhS*^SPh$p8V+K!S22W!KPh$p8V+NF&!N-`v$C$y#n8C-G!N-^(f|$X_m?3tU!PA&= z6g$k|W6a=V%sA=^n*n8JK$#gwvBL}~Gehh!1Io;RGBcpej3bnpafC86j!B!ni<<$k03fCol%sNXO2_kBR@KSM98O4@{iQGM-(x>mIUny}1mR z+-8`%-e8~k6R_bYe7YhUjY<_Gt!37>t8}7M?wJ?)Gr4nuK3Ba{f5Cs|<+9+CLpFJ) zet(TiPSWJrrjeJ@ja+h%V6h${Hhu)V^$2$B5hCPAkgP|rUXSou)kvlO_RnprES1W> z<<1GDQt!-5<>kO7Cs7P!l8$RXjtu+r_U$j7{n@koVDRXq|1{Mxdzva^M!?T%Y=tK$ z6;1q$ZMV8UYnUvUI{!V}G^%?F!+7MHjZf|ZpTa2QlKal<;*yI{v5Qc#i%_wPP_c_p ztBX*ji%_MDP^F8|jTfO-7ok??cS}d8)kUb%MX1t6cp4)@eJ(;bUWEEwg!){B`dox= zya@HV2$i`AmAQz!)2?KM`doziT*Q@M7oi(3;wmQ`p*|O(J{NJ7(~Y=zUDW3y)aN2p z<|0()B0P-|p*|O(J{O@r7jfl%MCitgxE}jAGT+3k7&2n_+Gb5QD%mYbM~zD^^x~u! z{?HLc=H|MsVH7+^HnCD;CD}YO`8H8#Eo0{n(Xa<{_=_6Be_ z-hpPG5o>mpId2A)nn9&zdIy@pre-<_nn9>$5UQCzf@Tn^ncjhB5ULr3YIfWCv>nVH z%!)so!Kr3&su`SW2B(_o8g2%mn&}{Drh}jvoN5NAn&}{D2B(_Asb&zW8H8#Ep_)Oc zW)P~GK7wX&s+kUgW;zI(;gV~HORkv?f@V4hn&}j7rh}lFPT^)cg`4RhXogF!nLdJM z`Uslgl53`qpqV~`X1L^<=_6>SkD!@8g666*vEQyyjY}@X#CO@%@Q02lD`1#d#3d() zQ`lMsm)!ocTylr4!K=Nn{?^`p;7~DZ#S`Xx>3dcDC+)U^@1^GoqkQx?rFzH z5D#p>sUg`{-}kihS=%z#D$^w{xi^>KlFJY!Wb95jPKGEUgPqS1D`bcjGDHa(BG?Rh z^9vRfHeRE^J||4RQ&<*35HOTjroRH1k3FZi+UWyB>{AlH73 zQI1P)@17EJeuZ+$DOaWj9{23(t86^A} za-7c~=g*k5Rp$vyFVFv^n<`H^$q%Gj@61c}<-;Wx2z4%Qu5rmJf9KhzQJQn>AN!7% z<&t{^$qt{-RL%1hFf@EJQ<=b5kmgsA=2!G*kSzVI6vas@&yUE;>8zJsy)!SnmnoOr z{v4N_M0!1!-2NJuoTR|BO{272Z{(6IFXyi!=dXg@uY%gIBImDCb$gY1+p9?Ut048O z_#&_3g}h3Q?Nw@Qud<$MJd##Bv&JPS|9p>K3G>g_amo22E+2hQNevJk)%w1g8kgMq zURR%I>YwfmJ@sZD!Dj8O|x+l_EV4dsEc8QQVcH&o1stktHnEn<8y5-<#6G zZ*?nUt{g5oUrEoS$ECRB zEMZodLkoM@_v{V{VEroQcTA7(wG`6Usbbz}QlL!Q@0%QnPs|oiSCnTzH8xenyufe7 zdi`8-_0$IHsb1DoA*iQ%Sx<$ap4vb?)ysM+1oc!e>!}meQ@yOGPT*(G>ZuddQzxjW zLQqd_pq|=5J=M#4Y6JCDFYBod)KeR%cV*k_sb1E*vhDR$1?pYpd+VtR)Ke9xr+QgW z^|Ibo|6e`T%X(L~xt^*(J=M#4ssiz{pGy8y?X=d zZ{N%N8}ss3%u!NIur*lzdu^Ta^3;)ZuWhz?df7euso@^^z$MKkCw&s0R_2mx!wYP~ z3v9#xYs3F*!~bi;|7*klYs3F*!~biePo#~$wKhDzHax#JIz-y&4Qa#wYs3F*qc@}t z|F4bSkT(3kHvGRfx82s+h8Ng|7ubdu*oObt<|^`Q!~bieE2ItouMPjN%~gh{joy$p z{J%E*zczY9+VBF~=nZM3H>3?OunjM;4KJ{b-jFuBLfY^G+vp8xqc@}tc8NARMB3n( zXrn`<4R(n(Iz-y&5NV@Bq>T=dHabMwN_dmDSZaZ)xYW4hbTx{{Mdy<9;m)#FWx3=I zY>rDV{0amg2OlsTywMDlo)O#{IQUIlr*QCpnKWN*ASlVzGbNsF8k^^m3!e-9RdLBZ z{lf-lDDM5paqbwbb6y^dIQ4xGSU<}H&Oa9M$o=@LM~p?T{dKd*MeQntS+jjm2LFHahxffLK1(kcj<6ffjUQoH0sJs_!?gf>5-F8;EgIW2wUZV0| zP`MXW?j<(wB`WU)m3u+uUQoFgRPF_pdqL%1P`MXW?gf>5LFHahxffLKB`WVFD(?lA zdqL%1P`MXW?gf>5!Q)==xR;K-UhudVJnjXLd%@#gdi8qUPx4>%F@K6V&iwn#pJx6; z=Fc$euJyw9(+k^Aulre!e2zKA{71}RVE!WWA2WZ6`A?Ytl=;idUtvx&-^Tnk=09T| zWd3vJuQPvx`7fAl!vEFJO5Uw>R=Qd_JE8wEcTSL<&^z}d}T z-#$ES_Th(H%07JGuAc0}l)+j@U>~Fto^2Xel6_dm7Wdw#>}!LDw%z=3vlCb|H-b2vO9HaN$0{X$ABvyC16Ym$EXM$rV*txBfaMs#atvTO z2Cy6hSdIZK#{iaN0Lw9e%z zV*txBfaMs#atvTO2Cy6hSdIZK#{iaN0Lw9eyC16Ym$EXM$rV}Snd0odXO=<*(b zCvJfL?g3YpV*tb)pv!vz%Q1lE7{GE2z!oF?GIR9G%sIcs zd)t`h>&(F+HRq^iJ?FGDOETvi`RsGfPG(io=HP~#bL0=rIeHFo&UqiRN;U#e@u-V&P?6Qwu$f2*;B6b ztr9n!bXm41jM^J)U(tCn&*KETJi(b0=<)=*JVC`_0*#)ael~$#PoU8gX!Ha=-UNSP z0==FxYTR)9Os+iJG)i&9{mv!K4R?kNUHC1l+w4CG zziU;w&+r>p<;{lQyQ*g~&VU4GK!WfaSKq{OMSEvJf-@k&88F}s7*PCOtLls^{+8A4 z9BF5k_MgG3pTVk!-?b_oK7&<1gH=BRH{2OVR{ab;C}-$TIzvbH8D}rYb%)M42bd2r zcQSu~`Gd?KV)mGCVE!=k&CK1*Hi3}(8AJ*-Za7_xg7M~HKcA(#5NVuwjkW|G)p5|o()WhOzH zNk=F%3Cc`5LYYZN+;EeQ;^Il_>65m%9zk?OIwL>G=Y7)=MLv6qjtKemN&Y#dJN3Hk z_g`=wu3>pLEX6^&bAk+o-kHx(+(?!xcg{u4P-ta!TzRcJ9Kv;tJjw{m{SkUN9}5rI zS*lTykJv0XobW|JR1G)Wff_fQI)=R9x`(V=EoHdjHp9I22K&rMkn2bIbjhklrF@;% zGHaVKro1-DpUIsQXoKFF*M`f28xGmz8TkV>Za7JkXPZV|N;h)DJ%Gh}z|g~S9>8ur zfZck42>Agd>jA9S1AJCBQmMcFbK5FQ<<)#%a84kVdS_lLF9&WoiDDp=HEuY&yB>GF z+NUav7p~d(;V$s0ib8IV|M;@7R>*R48=8&~msrO5TXn=sw(2N1vg)XgzKUPBieISraprC77Z4HtTG)o{Zd*c><9ff_fQWX!WoL(Bs{ z2hz~bp3dH6uWqsqvYVVw^__4&-RJc^>3pzne_wCklRGp&{j(R=UeI^mU0t{KRQ$>N zGCzLG``^~xt}OKfKhS*VcLHR(K-S9j&wKsTo$u@WN#CdXhFHzhwwh`(E}H<2TSR&_KUHgRAJUfv$lDSCMCfE1YU@g;Nc#BF_f;1sYsM zjSa5iqXzna8(ihO8eETAIMqPEKm(n>4RFIX&@a$Hzd!^10uA&FG|(^5K)*l(oxcrq z4K%bF(axZy%fl$7{GM|6MJ zbHfSZ6t-5u4R@d%H{9Oq)vi_eT(jeaQGCJ&=>RNFTCvymI_aU}e4B>ZtC{BdOFaU}e4B>ZtC{Bb1w zaU}e4B>ZtC{Bb<|$C2~LtCnh6-sSU3wJJ|J$q!;>y)!S>mk&2wAk?|Ic~jhQ`wttQ zYxw=Qw_E@1UV|}RtF7^T#v5&&|6<#}+V=0Z34;rBIi)$Y{;@1G+)I2y__U=e5-)+E z;d7SC1HObTzhryWMQ>W8)>avbOXYX;&b-WCN>5vAWiD6Rc5=hFCR%gom#Avt4;@jD zlsK^rcMBSUa-47y<@KC!2R6qEXY@G?U!K2Z@+_W;ts~FBX;(<{EHM;MvgBFU+Otig zv^;O*glhnY!x%`P;*Xd4#Fs(rmpSKUV#3I zpj0P}`df?pVe9}}rk}nZSKI3ZAIW9df)jd+J4)3z}duE+|zq7^#XP1K^9o}zy zX0LsvEYjlh^}ZGqEpyMKi1DqI9@n_weigNWZ}+J>pn8C+0S)+Sp&zWDAqtr22V)JN zcn$qu!!uq31=c`;H8f-m|9A~MzlN8*MijWl=da-_uVLrcu=8tp%xhFD*Qi#mVdvMd z@M}~n*Qi#mQLS8~TDj)Pwy#mYSfg6GMzwN{D#jYs$~CH$Yg8-Os8+5~tz09zvPS~= z1a(8LQLS7<1fmT03hVlut`Uw!@3AFkNwE79wBFWXL6aiP4 zgO>-fUN?$!@RtJ@oJ5(d`@tF)Tw#XNv-q9(qP9M_hbHN=9x!~9d zQ!_O#IQPhrOPUK#`XoG6?oJ&c^0D+<`^xb9qt%s1*b1jat1HcEr6Z)3UXWH-I@?M| zNGn`$tz;!z=?iIvL86t8kXAZETImRBr5B`?UXWILL0ahrX{8sWm0plmdO=$01!;BL z`72sstE(=MR(B_}WV6*(|Fyd6lxlVNF)OBN zr5B`?UXWILL0ahrX{8sWm0plmx_v5Sn&bZ(@eyv<^9frQZ0#`2z`bI(DC|!9` zFgQwYUKAvb!srtPkE7sm6g-ZC#8FpuvM6{Q1&^byV*Mzn90ir5pmG#cj)KZj@Hh&i zPZU&+!srtPo1>s|)NSW;gvwD+IqE9s8+C=sQBXPRDjyeh#VZj7m7}0?ln%Wps2p{L z%27}`3MxnG(2Ih~QBXMwDn~)(D2zT)dh?>7auigKg33`)ISMLA!Q&`+9Hm1q3LZzn z<0yC>1&^cj=0#!jiPDu9h0!NUZ(bBepD0~bIVf2Z@=o5v}Ckmra6h@yYj6P8qeWEb>L}B!a!sru)(I*O{PZUO+xZnz3N%mnQ7hK(c7#Cczb#M)SOJxt2vYHw=fEmeCv91`>gHS`}@r`X%; zwh}Y7Dk|y}+hzf#NvH-;{capoAhJccfhQE?bUqsOS9jiJ|LX!IBwJw}#qjK463UXP*IW8`DU z(C#s`dkpO!L%YY&?lH7`480yhugB2nF_3NyjUJ;yK89Y8v2y)C8k_5BQ*O1!1sCdU zaikdZ!}v;Aq_yYihdEf|f>ZY0vrVHE7u@?UVJ^5CGIZg$q;9kSApEY>diI4DGgQ*U z?@iScvoj#U3`h`uW2&CWDgMS(F$&Ls0W)Ag@pq-FGp_hsQnz!YowK$GX6THW;R*g3I%8(I zk2Cbg%s3zBT{km#GuyO2QmApk>7o=2zt=(6DMT7EgZU#oQtU72xn=Vg1SEOnu~+LO z1UuCGr!kJFF^;D(j;Ars z-x&vG#_=)6@iE3(!#F<1I6lTW5yUt?#yGLVIG)BhvBNk%#yCF4I9+(-pv*WZGfwO< z4$6!ZJB))e38SVxZosB9#T;#r5m~6?!jW+(gOE7|x!theZeN+q?w;KT?Rg6g z{~6$8mf6kNE%LJ(E$$=Ebp=n5>ROc>?ZGdu`564Xb@XNYx@G*jWn#!>yt`$*yJaHDW$xlKTyV?IO}tAnq&jeY{ngJ( zJ>`;)8W&s`D@rf?p(8iguEmNzT;!w0&2hmUtZ~6f#ytPBUIAQij%y%m4dcphIdly; zE^!uJ0}fpSj*BNqzkoxhfa8+OaLJt0Dd5m4;Ls`Hzy;^fFW}HG;L!i;&^6%DFW}HA z;L!i;&@bS)?Y0ER6;3&B2eYzV4qXF|`!4p?Y39%c?6~h`pK2@p0uKEGj;kt*L)U=g zD!=8p%HcXL{XVWDPltX1`yy}lKfwG!W<3SwxE}M3%*u5+bpASU!8!B`IP?oR^b0uj z3pn%(IP?oRbpASY4LESYIdH)_^bR<54LESYIdH)_^bR<54LEcSU^uW9`ty}AvEP1Q z9nvujtH3r-NHu(b**y>Epx-$MJ%W;{_eZ|2dB5a~#j-IN7b^cs|F;YaPe` zIgbBxT(`I?{ZO{8#szoVEuSq&A?M}Vk9+;sM8A1Cw-{sZ;SzGbjtlPZEyn0IBckUS zY~BJfhOCxi3=QA+^z)1!M{;rR_L~}#eIXaDXe^9%Tj9#LD^~&i~|^Do?q1`ZDK&3&1)TH`ln}3UfK7 zxwD=v%LVrWaveTxS#MJG0(qJ6IZI^_UqF^$kcd@<#Ck@d#sw$8L_Ja#s}*y>9n5jT zNtD-f!5yq|!AX8R+cZkc^Lj40^78#6^8F%+{UTWXBJ%wr*_ao}!@LMezX(3RhzIf_ zzQ>DH)?Q>C)nN5++L<*jILW;tGs%517o0EJ^2zs;URTL;jSDV}y^DKS0$rE# z=ChIZN_uY1bfvlA4*IlHzP5)E_kIhs3uA46zrFp+<$^2M?RtLQmc}Y}P>-wfd>i{+ z$BAXe(TH)*Dc^-6Jr8?Pq~XO~DEjQ;E|gY|NZX5hQPlBPz86Kgz*4;^>Uaw~Qf&7E zb$FM()3f;1uPc_Tg$s9b=LC_I-l^;9R~>KkvzX!M6x7-5!>wDxrgfvRwx$e8$#V+o zY0A--I;XIPruA$iKU(Ls+kWBj@4MCwT?p!HJ8) z3$Ep+s+Je{4OZ*FCuZ|paOd!e&!PY4@QlwP-{(Mqb4d0%{Nr=vGS1;8pCbx9hp&7N zU-=xljB{YiIXvcbR4dO>tvpAy@*Eca9M#HmR4dO>tvpAy@*LI5b5twOVcXA9tvpAy z@*LI5bI9sBs+H%cR-U6;d5-An9KPl`s+H%cR-Qwe&(Vc;j%wvO>XhfGQ=X$vdCn0R z+&Ma4&rwl3#~qYbX;jL?-)O(DalwViLY;c`OP z$5>4@x=~#Yo|h8P z<7bhNXR%SwVxyi#nx93QpRHO(mC-zZM&0)kgATPoM)l6Tj9#W(a7e4q1$QXqf@3F4 z&E%pr>p&|Nt?k(xK6dQ)ru~i8jaJOPEe`PSuUnfpo8Jws^b-&wgsSM>;QQ zE;#9v@KpIo#eX|&)@$u6!|#t4Izn3DlxT4!*DZ8}w9pIE;!0;*=m=?n3$BH}kQVwv zT40c9p(CV)j*u2QLR#nrX`vUSgt~ zGONDd;wtiMA$= zkQP_HAT6$XL0aenX@NVU1@4FzxFcHNj%cAHqy+|v7CJ&&;DT$RBcz3nkQO>ZTIdLA zp(CWlq{hbz{q(&_?a8+54%E2dbTx{{#^_dhScm2np4kz+$Vazy25~g>N;`9J(2<+% zm3gH?Gg4HayyY8T`tohD)NNl(ef8tFeJ*udA>3Kksw@}Wp&A!l(ypZ!T;0uc{e;hf z{%W}3{-FXF+&>g>!Tp1A!TopRg4_9P<$~L3=nE`x^}0ddZqT=zuDotAxSQU*ZjiW} z-n?$`xEnm~29LWz;%--UvTpFW8$9lImHFugmAgUZZcw=!RPF|qyTRjb7=5}yN~9&iSbQlw~O9g7aZs84G*fHdnvkq~cc}x#dfr|3pvzNnHPp zH7+==ullQgy1j4h={vg{Z2n1R+fTP=8a`p)XZ_RdLk+j|Wq8Kp@$DmP&*^)$<7 zOTq=0gbOYS7hDp{k%S8_2^U-vF1RFIa7p(L?#Q>8zs>wz=3~s?W4@EwCbAs*S;^9T z-+o`?f(tFp#u%hJF1XNST!^)?>Ux-zsd2$o$p!b<7r+H~S5;ha6Xb~|(47ggloMnr zC&*7ukY}HudNx6}eS&QJ1ljfp^6V32X(q^&O;AIdpoTW#s8?o!8rlRkvovdH{+RdMJ8N8U zAr>fB@`sM>v0d{qrL4J<*dcpWu|Gy9)VSbsnTFC_aOFDRDsjO{mla3(Jrd=5V@A;B z5zZVzmq*a$5h@NNX!Hp6vk~-q1dSd+qesZ{jqn#n(CZQOdW3xJ2--b@c8{RlBWU*s z+C74HkD%8h==F#rjUJ){%74*;%7Z-*GZL<&$*8Cm$upB9cAA= z+cZjX!M*nq=7O6fLl=Ha>Nfii!tYA0XTO2@DrQv(CqaTqkYExd2){A)P5f5*{z;Hv z5+s-e117hC^v6unA2UgR%p{riNuJ=Jq%&rc`#4E|%p_cJljPDTVQ-kU6|DCc zcGkGyxGMR{?{(013Xw*>oIk=N#s0!!`=w!zfF$oP*sJvsf*sn(1$U^%1*b^N^Di)5 za5oik!M$+<7hKb(x!{`0aKXK)1Q*;*mi5;i59_a?t#+JIux6CrhEb}5qx8g#;%SWH zX^es|qu|RZvBM~y#web~D4xbB_%aHEN1nzgvBM}n#wb37sn~r|9*vV!6BPG6Mv{A7o554r9AfihY#bg zhaUT*=CN-#zgK>qI!P{l-YrRvJa&zr`#-QWUa+5+(v4hjcVV&aGW>CzyRch#VYlug zLcR;hx(n-d7oS#*RBAn1M`fv$ubn$5=*H7K^%pK5E;xx|Ad>};RfPR^<+3Rsb-cb&^B#ZcB>JYEf3(ce8*MdV=14m4>wRHg#{xRC!2hs-jw~Rh3+TuK+OdGf zEr8z(_;w4#jthML0{+hepS{3cT)?+mz^hxpt6RXUTj1G>1-!ZiJf;OQM+xYXxjt0h?BcI9I@? z736sZY+3=ER-AUb>MJ1B3c2kSaB2mFS^=R}K&TZEYK6Sk3fQzl#JNJmxdKA1piwJC zoGT#I3JA3VHm!h7D`3+Kapwv-t`!h!h5Nq(SLF&gwL*?-#W~6fKf>I@tZtzdC(8UW z=1(yHE^{w)jQRJN`^DC4C zPC1&VpWfS7x2plE_AmB>>_3QvKZt}sh=f0ggg=OcKZt}sh=f0ggg=OcKZt}sh%J2( zIe(B3twySK@6Z3lnkr5?i4CM$@63C`+vxbqopVv8+L!0BI>ORz`psa+m+EWmRZgmv zrdco4xp=w80jF$;7hJv4oLT=+mILltnG_duz#YnQz{&4e&jEL+ z#sQ~m?FHAdv^=lpfGaQG&m-T@gV@i5)z2fB&vP%ICj;|5DE&P6{5&4W^Y|Xm6XiV5 zN~)22Ay|zAPIAA;u7u>im;=riZIzJrl$3luqqn|)X5XP=|J%>Z8!yy8c`O=!=JWfO zjlZ^TEA`Ll8Y%O6$nsp`7qi8asq^foM%efE(`)~q|M#cY{^jr9G3fAJsOvf4%5}9? z=83AVuQlw3k@QdE<4oe?guO4#9GAXM;^R!BLzDP8lX&ry=up`EB37ud>qV9ENwS!w zdSBkbZ`+x7Fn2KTWR`ajcEDWAzMe%Z?trwm{wMY#A(&x2)(lEdsg&0rt9GYwn^06URCauvlBM< zxR$BBUAY`^<+@zYuiKKjw{TO-^|_9MIHO4CD7sy~`$T#k_Mk{Yin~wV$`Qq?VfTq5 z)KWbt>U1mLgCY$t)q|o4H|#{Q-3!#=UG`4zygDr0S+B!-XI_V|91gfcDCv3h*!Z17 zqn)c(nrSXoLEp1GG}^w+{*Kw~d(G@gezr!n@URI&8ylwoaBKSLC-*|5&w9R zT*e|^@*+{-BEIq>c772%zsUVt#A9A0ieID_ut+Un5evUaEnty4UvrTvz#?_ZMXCUcbe}C!r(C28 zut=78kt)CX2luIvnSVZgrl#FMr7IFUbLSNDU1_5&g_PM6DMkdRS{5aJuSVa81FJpA5CFtv%DW zcKb*AhPK^x9uByN(CvrN?T66qhlqL~LS7$2s~P2(5ky zt$v8rRHGZ!<=}lEGti%sIrz(g1MX1B0e8402V9xB_Q1XaM73dDd#~BZ>kMst6yFM6 zX37}KMylUXnQPgd!VIN2;0_mY!1a{nfO`@-eiAu;66|~u8}%eM>PbHLNu>En`zz}` z!_vJaTHpCI>ZP)idS@QLFQx3HR<`-aEEIgaOzp|f*ZGaj-T-P&tDA( zT&4mCT&92nE@K>U4;u&EyMC=4aPKPOfb&3K5A^liZMv#pu;&UNJdoIf$;ShaJ@D8A zk3EpsbE%Vo#~yg>x$+V{P}u{OJy6*Ll|4||gUQEpm5K8}WzW^~Rvy^wfy$oS&Jm%q zN5Ll|5JSqvw8z*<%(edocNUpt1)ld*HDL9(yqPc;K-I9(&-i2OfJc`FJq-crf{R zF!^{e`FJq-crf{RF!^{e`FJq-crf{RF!^{e`FJq-crf{RF!^{e`FJq-crf{RF!^{e z`FJq-crf{RF!^{e`FJq-crf{RF!^{e`FJq-c<$HvufM_k7tA)TvnQp!+i%)=SJ&k- z54V0^Z)D^>SJzShVeXtD0@FM5=RD_sPi>gxxTx6)t*qX(r+D}gk=CrtgT`;?P6&_4 zbMQxaM3R?3@=@EB2VBen=fk`*7WSNNE@4px2b}-L8V6i(g|8(0u#p4q>i;kfxMItZ zz;Yz890@E(0?U!WawM=E2`onf%aOoxB(NL_EJp&%k-%~!up9|2M*_={z;Yz890@E( z0?U!WawM=E2`onf%aOoxB(NL_x83f2!jdy@NaQE#_}Cf0y|f^Y@tVWVWd)OY?m@uf_ov+7i5Rk)<3XKRHI8 zeT?ea7}@qQvh8DJcE`xGkCC+*qrZEM8rm2&v@xEi8KZ_aMh$HYUuTR;+8C9zF{jZbKQtThfe zF?}DI^?APEa|v_6jZ>`*za3Rsx$rwu>)CH$zKU5@l5vn=93&VA3BqqmeG|V`zJDAf z7zYW)!GLivU>pnxzav%oxZ-a|7591gf~ zTfusNp~eBH+Ed~1dmRe1RH}#hBgCF!e?he>!yW-iz9?(2)<+0-Xk-7(;n%|f_q6#9 zgJydDy5UynHBi1-euH|mzYzEhWTE{F3?8%uD&eWWZ0 z+%Q-(OmD+5Rl#Aht;2X4!+09Q;L9-hGED3+jHfY-r!kDDF$}&8gD=B)8pGVdVen-b zA7dCFV;CP}7$0Mp2x1r?V;Gbf#?u%kb{NLT7{zKhQ;)}hkcpta1}Chw)ZHu$;{oD*n+-kH~ie-HF2IOn2j zgI4B%j_d@JyeRpdF~{-*EsaKO!?BeUqpEIKla zl+L0fvqRK)y?A7&EnO~;?>RK)y?A7%@RA#;?K?E&&~2|#VpTO z%)+oVi&r;`S2s%pIg3X&%ToZeM3A$@jSR*)EH^$OsCTLPPwK&2%t_Y$bIg!Nqlo0dSOCGcp8 zSaS(HS|Z9^0*{u!qa|X^B~WRJjMfs^v;;OS5pgboO-sa@OJLIy*tA5%xdcKjk=tGZ zrQI$=9=!mibhKWTSaDq66t5rOCcDR5*tC$0B z|K9fEy4yw$xW_GXrtd-VBaf|+Ia9a3GG`jA{tq{s#Tx=i8WQ6a*`j! z$a-g9sxKc7xIn0L@p6p=PB{n9HjUDpS(&mNa8DxF;Zv6N_6bjdpyBhC%CbF)EI+A_ zN22tzQuL;06aL+{%1B%)ucLS7W%g2f%2F%a{8N_iw|ALeQp^E&IL84eQC`mhceus@ zr)%xmrcqj+*K@#?m+v9udkDlH0;`9R%OUbGLu6ovK_O1@~M*7wiUIN;950avc8wK7jsb$zX2H;klz93N*K zA1Ca6Y38`}bsQgO932|R#~H_qA4iA6-WPGegCxpWem>ukQFz;km z*F@L>b1nON7Ol7gMt!ZteK2-lo&Bn|$5rxNG`m27plX%?46$FX?(x4 z9FL=LCwEQ|N$H)so?%Bw(K#2j+NhP)kx#Xq-0<(a)*Nc=Z|8m&9??7fp(8=htFM$r zTKtLMJC7dMIN<&j{N@| zb;>!a0CQ9U=BNV9Q3aTzPB}-Na*kTS9CgY$e9bwk0CUtS=aA+(y3gjQQ_fKZm?KL( zM-^a>I^`TyfH^8^bKF5`xkjbv_D1`CjRP*k5uvg_bVMC$=J&5FP3mQ}nfMw9oHEp& ze@T5#$s!K8ADo8+?ml$;K6Lv&bo)M{-usAp??bEaL#yvYtM5ar@56h)53Rlrzu`W# z`aZP!K2}qWZd8|p_q$;#<=`&|4!FZ12V5ZqTzklqdZ3K2dqBTn_&lliTXpG!=C$}X zeJfO#6b-7n^slxl3uuc+(meaAAr80?tsN<1f&2K{N6YfSUBlDv*SLBj;~G~|c#W$( z1QQ8*Lu&Ntt{0Wsdwi6!uPmE=Ui03P%Cq} z>b8>`e(kH!FO)y-525!?+coqq=7iHLpAs%)gwxLrd7Az9O+vop7S8P^@B36*vf<0~ z-6qeCb}JPjYz^MuPue;q&wphS^|!XkYxTO&dhh23<+ppes}# zbcIucut*HTA~ERdZw|sDG3bgFZV)bsL07Uj=(aI$XI5M_=(aQOVAeVZUCHI3tE|JI zt5|T*mDe%oD(5rkzK{8Ln3eMxbd_}h`Ezl-2;Q}2bkr- z47wj;zJd8h<_|O9#C$We`iBPHqs%?b>Jb@)OJdOdFYJGu`FEMsBQof!M`Tc!c^x+C zi1br;qnII1sNz5A5Z!CLHk3IFj_BXB5w*=fQo8?JGA!9uHK%<4xBmCsIYI2Jcjhtf zn{aL9&bg=gY@q>Iu~p`hN13Z+z*?x5ZMo zeKGabkKgvW)NKXmXDO|c1aX$pDx`A%?a|Cv;^)cJDzS$pl-rm=bcpRVB9&|eKd+&}g`TY(`?zx~^*!d@4>`tend_5Gdk z#MQlSo;V?a@4Y1*;eqz+40nYJ+K<@2uAH)HIu1D4zT;$E?PtK_40xQu|H**L8CQ9| z4A`7;mDS3C&>0Xq12$*C<_v5<8Q6X@AausnU(0~g8E`rS+fN3Z&VbMv5IW=P8Hx-z zoq_Eq;|ixUZaec1=65m+p);;Jvohdx2As}-(;09&;|ixUu5dcz?q(LKWn2MS2As~g z!s(1FwyumTUCqGulW~R984xG~LT6l$BR4P$r!%nqWMKQr!1j}Y?I#1Kk=dzJT?aFQx^T+X0$qsu&H&^=LVDYPu-14Q*f1<}f7Fv(6Ad-s_ z%W!_|Ij|=n3iqwYe>dxq*;3Zyhj#5`J?0JI-eVFcuSXi;*`{$NT90)sa`uI0PrY|& z+sz+0=KnViHGFSX-$|;9ioC?SwWM?5b|s5l$zoTs*p)1HC5v6jVpp=*l`M88i(ScL zSF+fZEOsS}UCClsve=a@b|s5l$zoTs*p)1HC5v6jVpp=*l`M88i(ScLSF&!q{eM|k zb|ve|u4M82v)Gj^b|s5l$zoTs*p)1HC5v6jVpp=R>`E59lEtoMu`5~ZN*244#ja$r zD_QJH7Q2$gu4G}6%fcd;#ja$rD_QJH7Q2$gu4J(*S?o#{yOPDOWU(t*>`E59l7&Ss z3yWM9yOM=VE(@1j78bcIEOJ@5pY_YGWWm#{E4z}#u4J(*S-9k~aLHxilFPc%qAXl; zS-9k~aLHw1k;}p&mxV&mWV;gZY3C6|RuE{k2s!X=k=WmmE=%4K1c%eunTtotqI z?=XLt`55!}n7_~b*UUd)zKhwWs_c-^L8wsK4*jt{E<7i&LwaZ44*fICdbx8hsvXkG z>cKdzIvl>gUucKg!(Z9|VVA(h`!*a=)annN^D)~E?NA|O4MxW=-)+toS;8lm-pNHW z`_1AMW_H3X<>9^i6~@@`ZP9--Thwj~_y4o45Xs03l`T48w&-KF>8cBNJlixv{;BnS zIK|v@CoX_n?niw;tcqRkC`f%2j6MoF9|f0>g2+cft(C|G79RzRkAlTVU1emBg2+eRcJ_BL>&hH;cQVV-E3d{u|vR-5W(Y=$wm+2wGVklE$)a z;_DNYZncs3Oy3;-I)?~~$owJwf4A+L{!44A+*jzjv2#KnQ<>S_hYs&Pyl;P*Z=*SM zI7m?hnyqi6S+;wybu?QZyfph=wrbT-q}lJV&9hA-)a+trxhF4JlO<<jwpwCC}vyPzEN6_jcX!Q{?tVhu8Bk1-Kbo&Up zeFWV;f^Hu{tB;`7NAR$YxYCCs=<^Z$tRwhYN6_jccFitSV|DFy%`0oHP$qXyps{*q zUSmDhoIB^DYOGdPhXiTW;n;jExzFC}YiyytMmfti+gOZfR(zvfK48_AQg(UI?n8SD z?egE6_Wn;(fUTpwN9`&}d-ZJHUk2K%E9cp!@zd?y4eGZkH!maK!YC8pa(SQ!N&K12|b`e4`|Q>8uWkzJ>WnOIM4$Q^bl|L zfB-#M_a1br$8BdlLVzA3tsZco2OQ`D0eZ0OJw#eP?t3{?8N41WdJmCSkGqE>inn@* zw0fwq^th_A^blk9P+jS9Kgf{}F?-B6Fn^f&X69~Yn?M2m402X`WHBAObt=_5BsY?m z%E)s)pB0=FAdlXeN1l%nJLW#;q9Tu0R_93i!-210h@jWi`wH*3vkiHKB!RC`7#i6A zMpn5(Qn{SZaH!n(f9*bOztQlcfgwYk%a2vgdcpf%b#Ae5Tz&dy`}?+UV3ljzG^<=& z8CJP>lwg%p&G!GY`}j89dfS)8`lHJg!gPTxU7$)Ac+v%)bm3!kfht{~N*8$21)g-_ zV|0NkU7$)AsM3Xx(FL}2fht{~N*CTm7v4n|*wO{Ibm3iex$UfE2eV>^E>NWl@1l$R zO&8eG1-5jN#pxnu=ptt50$aMkmM(HRU0_QW*wO{IbdkmBB7f5b!gT2ZLJ%NF|p;po3*9tGU#8fIxq52y~rEMGI@) z3i*g8TdDjWjamOkQU6rP(&d)nlKUkU#9!JSahzY$0r*SHJZZmy`6^~vzF*P}_)Dje zeVgn)`lC{nNbA$O^f~2YaeZd)oWQ>7oq7AZ)wtyTZ(F?ybupJ5RC4B<7ZSl+Y-DI9kDH8c-%>LA2D=uajQ-sAHFV6=j*YyGZe)`C1@id|{40AmD%2g6~9|{t=zQ1;75GB4jwct#lZz7{#_{Lkcye((xj6N>IG$V_A1;m$7srQ- z6B)+w;o|skaU#PwK3tp(QJlyy?(Vef9LI-?3(H$9s$8 zy~T;9;?&^c)ZpUyaB+ONI8kC8PcDup7pEQs*MIm4Vn zGP#`fJ77kxWM*pb-l7=s5yPC`ZQ&D&TLE+W?TQI=)KU4YZSu5~weW1y5NCnUnl$vY zr?WTNtDCH&_a^64*46vzKF_**KiIdwuea~X9h#s1*$Zng^gXru)YWxsPsN|SFZ1K4 zy#H<8@#+bF;0K!T{El&3HXFy~1>)2CC&vEi&iD2Gr0-LGL#*a$Tg@|9J9lVhqqg7R zC|>jZ<)ot;kDuWz>`dzirTW3Aej?3&@Ts48vmcb|2cP;urha0~evql3=&~PV>Ia$n zi81@Zr+)HR{h(AoDAiA-*$+zf6Jz#+QvIM*zuRsr><6p*-46D({(i8kAFS#JtNOvJ zezI8opj1DRW(8ANcuf6vB#($G@HltQMMXrdtPV}I9R?ng zc;Ia05piQhtr#Q8XBM!@RmCA!Kq2?#Jcpc>(5~kjnhKFn9CE=!5kZuC!Z7ek;E+>3 zOB`};2@W|2OmXmh9FWDq^Krlz2Yhir76)W;Ko$p|#{pj)d>#jUaljV`d?DbdN-LC8 zTeYpSR`}Q$oD*n;-kH~mt;QiIls6xsK!!;Vi>W1l%+3g2`O$7(%B=-t-yTW$Iw@Ci zis45WKar(3%-K4*7+F49dW~iO2Qily?3ZRrRAy!)gWM`&xQe&1>TI)5SVdx1iGEj! zepiWmSINk%I?bH(M&>s$3%ORgev;DakY4|T)?Qhr_4&DT0-4r3^D@2F802=^>T@z3 zM##QF_{ukWuHUOb+9bM=J}&3G?lVCylx2V4aQi@Ux6>Ua(VZsIx>8#sUenZC^Dr1I9! z+q?adm&%Zntr(5<&ipy=AzsdX&PDZ6v@(|~9{el(@UN=Y97b)*Hu^(HsJX7^k;~D@ zm0*!8B$3NYb(wtR!QGY~D!}P)n^fPrrKGymE|sLZ&Q|><+a!^?(w=P^rKNg3i(Dls z--VR#!Y|o{N3x4pXBV=yi!978e34y5IlJ&ecHw{QBEH#0e6veSLpJrZl83JUN&ib_ z+?Gb=&Ixc^@61d8b-srbe$GXeeyz;q&S=%)@X@nS`iuSX_uGkv5~_O$Ar>0bF& ziE?~YT4C;-K)?0QyncVoEjs6->bF)_hvaG18aQ00joQy!H{Dl%g!ZmvPiy!{t|_^7 z$K@WNvcvwq>K*o?L{Fnt}=neohR?+h_pQHKe62l)L`8U-Gj;++^#0k znH!UoJj^ia)6WnI zY`MWmxY|#E0SP?h1W1qo2@>S&68OmpGIt5Qx{c)GQNJ0}|9M6I25dR09(34pt()Phb}l)BzII0TQlcG(jC8LCrEj%`!nXAVJMC zK^-7L9UwuqFF_q3LEl+|nq`7IK!Q3zf;vEgYGr~tK!R#zg3BWv*Qn&@O9piBEBpEK zJaXp*D57`fQRFkMKX=YWMG>v64oTLk!*RYSSLX?z{UH?jfb9xJL^7ENk?QE=%r__` zlgmW`>Ub#S8ywhwz3&TZ!-ZBBW>fY5`(q|J8#eZRL~i;w)cf zXFwR_$G9O5>Z{gD;^6+UG~?so1BQb)+J%-MWs=}N;#^m7bvamOY7dTI_c{CfWzH!) z?1ksw`qi%%9xu0lNAQcD-~E$YzV?OuS>Lo>;o$!=xl*Q0lB-T7&o+(CGyS~hSIQGN zRDmUKsDLAG$Qa@tGJd#gUpGHo)UHApQ-3Vj7Z2Pgf_?GB>59G8wrgz1r*VpmHau+zBdog36ts zawmA)NhID0Dt8izcY@8GpmL|%&gbl4Ry^M6Uc)Spp%YZ@Bp&Z167K|+J3-}6P`MLS z?gW)PLFG67M7u?*x@QiN`zP@#zGWJ3-}6@VFB^?xZiT z6Flw&k2}HRPVl&sj=WCyldQatS^RLF@c4AX;L{0%PpA8b9RCcn?pmjN3-hhapJo0W zbBg(on58hCF!*%BSXZ)5%%vzXyJVesj6|D64=Gm9Ut z6CNMchSuAY(sn>PD_spd*IP^1-St1_&I#;*-kG-p&%tMuJEs7tw3KbEN1u@&h3I4p zD1A-=B5f;kP9X|uJ=@?gsz;CVe=XEI-%jf9InHnAejVC@T^o)ZEIJ~qD$7vB0~f&j zCW+wk_8}-~TG4F)T+6%MrtJ#IPJO zEJqB>5yNuCupBWgM-0mm!*ay195F0M49gM2a>TG4F)T;SZMXX#!=I1g&&RMFG5q-$ zmLrDch+#QmSdJK$BZlROVL4)0ju@6BhUJK1Ibv9j7?vZ3<%nT9VpxtCmLrDch+#Qm zSdJK$BZlROVL4)0ju@6BhUJK1Ibv9j7?vZ3<%nT9VsvrGV1SEZIbv9j7?vZ3<%ofp zF&N-tSdJLnZ!x&vVy-Ml3YwtSW74B zoR8bj(9#qz#{{-!(^PL*8_`Csuea?tn^GzoIUFWsg1q97%-X!&?%vjkM&55%P}XLj zS(~VBws@z*HqSPVuzJ3}Po|jb?XC-8i2CcQnBGQM(Fl?~Vv)P!jF6=qAwM}nc74QA zMQ(%~`v^Jq5#omt?!yRKn-Qm#bJQU-;wTd^;;2Jr#Q7~|^;eDH>x}SiOe4-aIMU86 z$sBRs$-I;KUCi%hmOnJ&s7^fMypLIOJL0HAX2iDjnqO@{jP8x@$<=&DxqcX}Eq6|U z1$t*53!+$#+&LE&3$(I2BuuLg$D4zleD*>2#vdUTC|1fJ*<-t=`BK)f47PW-y((Ku z4|O}&8WVbw`^!8De2Ax1+HLrr*%(mQ@Xv=R{a6nq}$tV^K8=ybvx{g zkxn~%%6)t4($K^!lVDtvQJto^+(qC+X2T=}50n+IFEjt81=nU0G-Sm?}6Y z&{@4Rud^QhU+!}*s?KUi&b#l5>l&$Qkq zA1Kq&wr6*!xW3;0*!1@D=Xu+83G=*-lA#+#`$wrdjw0!!#J1|Fahy>+-cj^s6eJi0 z2}VJJQ7rr@crXeQjDiHCAi*dYFbW2Yf&rsoz^J2+xKXr!6x%+E6puRX9PeP3RUZWd zM!|qlIxa>XS@lt@`l$0>_GQ&a9a*qZIypuiS)oy9FY`X;1I&k*l`kKq#$`_tv;QGx zkNF1X4>RA)+|6tgS4TgCNTJ5_ri)Q9Ht#PSws#x$jRfiI`Pms8-&DgMqWQ05f) zateGo#TriGW1IqIPJuF~@G(w-GN+s!wy;yg4yVAEQ}`ICta72_LYY&b%qe1rQ;tyP z6tTl8Q05dUa|)C>MHlHQM<{d35z3r$B-y7N#l@$GuYl@^A|D}G z{)jBSKFL2)Iv3t$zrXw$-|U~{itA_I!%_F0KSG~J^{M<3)i(@fHpBP^5ZN09L{)IV z?cH5S{uW}I0h;l0~LNUwZnPN5@HXvY-z zJq3PGVI!u99jEZ{rjV2=EZ-D&aSGpV3a@SouWkyjZi=XJ3h!tNk7xpM-0rFZ6$;Sb%S zb1rIrN-L|&d23p^##{U!w&u`R+nAry)%S zyO8=VM41C+zENb)-s_8E#lJI@sWHE8E#|j*uxTDtn#Xd_gG%%0*gV)Y4=T-rNAtv* z^Wf1uQaTSF&4Wkt#G3P<(mWZhd9Z07Y?>$HoCllci8bfJrg^Yw-f1@po(G}k$!*Vr zQ}ZCyJP0)pLd}Cv^W?SW!KQg4&Uqrvc@SzIjhZLooCl%iL8y7KX&!8v2b<=JJLk!9 z&4W<$Sebd}M%E*ons=n7^UhJ`k1+Qzf0S9B8}oc~*F1fG^L!iZywl6^81wHj_c6zr z6U=|W{Ap(OV9nFjG;e#=VPe0X_w0EwQR`oiiT!pYkBOHy^P5&*>@DetJSKmHD5(la z{)n;xhKT~Te4S1FafW=t#rz}a_M#XYi39RvS=Z&+v8;D%-(G!}QeiY84!8gegUs3E zhK5%H2b?lo;(&Ww2@bfsL6^JneC`Hg?ndJ725IgFY3>GN?gnG-24n8V=eZlCxf`G7 zZjk0~kmhcX=5B6sHPM8!Y^%0a_8I(~LUA;qcjonDt8u`++g2~xha78Nq?co+8s9CVO^SZVj@ilQ352p=rn-h7|BlH_@oKr*4d5q;ac*E zEyc3cSav3oVoTbwUGMFly2qXID6FN>Hq8qTc87x*qRbHF3`w2g#|+5MfV=>CLGpqZ z9bW9=MMgUB|F^IRED|6=If=foMtBG;E`UpGJ`!f_8M8XevcUacw zw8~Ovw)It(0sAhi#i(c@FmVasY!XMMMQNS}4BBle-Kv_7w8fGe-x7x~1CcWk>*MXcr`6_|_s z#f$joi(I>l#2y#PaxQWnmH2A?U-W<2Snu!V^Sr)V?=0wj3zOQbpL1QS7CJM-_2IPh z!qG3Cvm1|ls}`;HIO+XytKdZu`6~5WY0bAQj@Ql4l=}vZ2ZP?|MBjj6zj~efc5|$- z(>0RjKVUWHQTwnbPo*wme`<5*-qy~vuH}9!H`Tf^LsVsRt?o38bkm)Hk>7S_U!=?4 zsTajp?(B=I(EpANxw9{td~>H>l+%@;efbl9+km_m*@(Oksp!C+fNAEr=32cIFfHtn z2X^OR>{F~vKb>w_r8BO&SGq?IW|ixoX+~%Dn0!4_?<`pMBgS*gb+v4r*)}vzXYFpf zf7%L`y*~HW)ps^ozdpy>x{S8~aUu_}xwjpfE2Q2<>~Fhv+5^_lxLQ~%g>nzNi)r&2 z_s^}Z%Uo`r8CT6u$kr`^x-XKq^#=PoVjtRETX$z%UG}$fQ?8rawsh|Qk!H0f4;21OQLY6j(g_RG#M+sC!q zuY%(A5R{lneAJ7w82n(5GAge-`Kh zEYPQ1K${nsK3kwqxj+|SfiA!TU4RAplnZnL7U-xgU<|TyZ5z$f?6bdr&iav!qkP33 ztHb=YSCTh4{JH-vB?ow-&1MZXd`b6wQ zn>gV1dN|->WjWy9L66@-kKe&}z5_5zr$x&qNA#4ZeCG$qC~Hb>YWAu zeIr#Tb!JFro zEWP$}z}u%z|8D7UT-? z-xcD&E6jpiAqu?0EXWmRL9P%5ULgv+LKJv~S&%DurYl5&SC|F4;?pe16=v41FcETv zZ>PKB`x^WIEAku2Zz3N-K8pOmkXGO;^wWtZ^-R6fJM5#%0jI0s-PUveXsYIS$N}fL zI}6=qIpA8W9B@Cd_au_Paa-s3ao2yo-)ukRpFbG5qwS*ohSiI{U$p&l`**Io-@f`U zZR+}z{>{GCS>5)wOP24v^IT+``@Ro1;DGzEhy(6J%K`WQS`N4`{7yOGzF`K_jmm zgvloelTQ#PpCC*=L8DkTXjF*{8s&3AQ;$@QC`fH9Xc~Af+z3*!4jR>bgGLcU(AHE zBKINXm4h((1YztihAg>)u|n$5lDt-0Fm1myONcBh7O*?Gc760`_viIc{DR3%kyC zwSU1u-dA7S|HHq1^y|((C)3jh<@*|L^?BMx%JL5?`c5eGTqAV(bJh=Uw)kRuLq#6gZY$PouQ;vh#HPN7ILHwPIpQEk+z2`1AV(bJh#MhC+z2`1AV=H?IpRjh5eGTqM#vEdIpQEk z91gfR$PouQ;vh#HPN7ILHwPIpQEk9OQ_D9C45% z4sygnjyT8>2RY&(M;zpcgB)>?BMt{#91gfR9B^?s;Noz=#o>U9!vPnE11=5+TpSL# zI2>?sIN;)Nz{TN!i^BmIhXXDS2V5KuxH!lWhXXDS2V5KuxHueeadV2RcN%#H`3mw? z^Sj6=|@uxqB4R6!v_}K6R0%xX0#T%{6hrwTf11E#FL)18(iS zjF$uM^=sgOJ6{n8+!(dWF>GgyD&-he$}#GbW7OHl=$?&HZ6BkCJVv#Bj2g-qHIy-G zC}Y%6#;Bo;Q9~J{hB8JEZH!9F7?qSUDk)>W2CHFXR8q#Mq>NEX8KaUiMkQs8O3E0W zv@t3vV^mVcsHBXctU?lPTbqvw*mqPp;9SdBuHja{cX^J}wNUGpjjoNKe*Oi{6>W3wKt#wa(o+bRc~>O2wq(3ZOA z;T>ARuPiUT1Qogotbc;8;{-lnf~x%lo?wDb`UL)90#7i3Cz!w!On~qc z_=5>N!33UQ0#7i3517CQOyC11@BtG{$xLAV6JYxUK41b=pTPPjK=lcHzyv;E0#u&> z)h9sp3A!W`p!x*!F%$GhCP1MHx+D|yM<$q$nP5IJ@-{P;J7LU@t^WfE1#!TRn+<(4+mVUeYLh8Wp}M#$=X`wfKw(G z$zS!DAf98ySfH!eYZV+EHh?g0} zzYOA82JtL|L>hzmmqGl?Af9Cq&oW4)F^GQ|#J>#UUk3R*gLs)i{L3KzWsq|iB*qxT z%M9XW28l5S@iK!%8iRP5LHx@gF~%TMc!PMELA=Z$xx*k{W{})r5HB-`ml?#%4B}-5 z@iK#WnL)a+gY;hq@il{72(JgxF4>HF60#Y^XH^b3T?1XG?bNxpapkqo-Bc~pR`4=^ z?(AUSHl9D?*`q$5^)g%KfRlfbBdUZ0uC>Ymr@4tp{<^yyaGx&20k;)~E%gF_if{NS zpYFAx(w!ll%aVQE$veueVNri^^_cwJs@|!;;CyGpEx`eYZaUL>RSr05Q^Y>B6|{6c z2i%Jw){8{PFM?Yyf?F@*rC&s|UIe|=xpZ_!KR24D*56*VkBznRE`5x9OkOMX&Vp9n z3LJ2)Ru%I)$pp3cy9TQqaQ~`4;a%IVzW>-qk&pgi+|H2x$~Mja>F1K?ewJ$c#ocyg zMa{)?2W@Zhm*-lq!u@|PYF}x_r1k0tKQI5g0tejBKNbgE4jai~BROm&hnD8BksQ{M zBeu)ozjMTPIdaDw5nhh?Cr50Tqc)Wzw#yOK<%sHXM0Gi`#vD;yj)*Bo)|exz%Ms7z zi05)-jX9#a98q14s4hoTmm{jn5!L00Epp_JIpVn-@m!ACx*St=Ii~7zM0Gi$x*Qo~ zj@T~8+KL<*WRBc1NA8$oo-QXt=8EX&MxNoT_V+)wRm_b&gQ}~m$K*YO-dXSrw+{zg z>()5nTB{sz4_i%%*oQXFoPA(D#RtC5fe!{BvacSpuO9M!ukDw<@3%$TI(&c87Ha!; zTgSbU9}N8K)q+3j_=k`F@%_kJkMx^e=k;%P+U>oz@7ehYoy`aKY(BipcS_GKZ@;Z- zH`)J#rodFm{=AiLh1;4?ep|#hE#j3HLGDGo(jqpth;LfND=p%W7Rfai@kfh%-Xi{J z5r4EuuDOU;TBM@2h;LfNH!YHJF5;UO$u$@8O^f)ZMKaDsJk%o9twqj%5f8P<`7h$3 z7V%Jv)U_7zO^alli)5UOc&J4@)FK(@A|7fH54DJITEsUk;+q!9I~S>OE#jdTx&MpI z{Vw9C7O8P9!U4C)#P6c->-GvRGA*>|)5Py09B_+pz%9Z7w+IK^qE8%fi@xt7+mMeT z{|fmy^7}|}z%AN)C8@2F82$-+T$KaPt=UVaa zo|xx6p5{FM>pY(3Jf7w}o<@@^U)#sV*;}c)j^0_&*&At6@!0R;tKUU0-=z-oE)|$}@zU?& zpWh_{d6(GZU9y~aIgd*8{?qozDhFKA+}j!sxYhy(TuIFrjnvwi)+z_w+L_k19B}2P zS~up2s%);+oraP2yAv?-+wSbk-8`4Qx>GOe-@3Cenys6_hTPc~u|m01FY1h!pMCig ze%pY&7ukrs5BWLd{m5pd)}nbQV6>vZI|pNTfG+yEwHa4c8mk;|ZtktC?`%c3F5@lC zxY}16&&okBmA7_xwN%I^+QqrH^Sq(q_T_*pH|4syZOdZaD&P+LeEpp3Ai2yS7BNWv zQhxeGcJ9ug$iltTC;Dvf^hq6iWbNJ=6s)8>@b4dz>Hm z3O&oMbHL3K6VGD*vqZ+T==UsMU=|CRB|e^|mN83|JWCchORPLgtUOCCV;0{sOT;`& zM_`s-z%0FhS^AW-^a5t-Q_j*0n57pmOBZ04`u{9_%2~PqvvdJw=>p8s1(>BzIZK~% zmR`Uteacz70JC%fX6aMT(gm1h`fQdyDtoj^r!#S+_99Dgfv#G>3DyzXO zf>^B%;D)SW0XU%|}lsCO3fMygKg%(h;gR1eiwC%qhSXsg2kx69># z`DGq^+-*GsD7f?daeq;v#o#>D_GbHwzYz7tzcU#*wzZR zwE|MCfD|hr#R`$%3K+2hMy&7`R+t4@A^uw-{##)dWQF)|g;|gl;=dK*zZGADJ((5G zaD^yvg(z@^_-}1gsdBKaG)bq+Xp{pW9o1MY(j zIN&}g;(+_Wa=`tQ<$(L*@00`Xi`M(v@>70mF?!wtlTV8glTV9L^wMJFA6krRb}caZ zv>3%AEk-d^i_sbl=R1O0jOy+!M!o+QBhS)eRPk#us>ij!DdR&W9=GS6WcW*IYM1BdW zx_gV+iQI)0lTV8YBDK1@#fXWk#XN`<2V9HM1Xl|yoLbD6c^*MVk;=JSVDf2!$)^P- zpB9*WT43^Nfyt)@CZ86Vd|F`gX@SY71ty;sn0#7b@@av|rv)aT7MOfmVDf2!$)^P- zpBA&9zk2|A5P1msB=RZbVdN3y)5sqppFuv0Jc>Mq{1NgwW{uucp zQXFtCQWh{;KR2pQykvi0<$!am6RO-go4ZGvSJ)#AR|M?kfOFiuDi(H~t(W!9`)Vx* zob$#i2VDLN-%j|jo&zrO8{>fUB1a75h=Ck2kRt|i#6XT1$PoiMVjxEhPK6m}y{-kRt|i#6XT1 z$PoiMVjxEhPK6 z7|0O=IbtA33=X)M5pu-ffQ!Ka7lQ*X1_xXW4!9T`a4|UGVsOC4;DC$40T+V;9_vV#Xyc29B?r>;9_vV#o&O8nNys@Y2+E?E67)oXOZWSR#b#E=k0M- z4mcNAq`}VS?omWj*z+y>)J2+NUKtlMt_5vGE46lBrcw^LzqdS5pV@XZ@k9me6`Zn< zppAvZH)c2QY-gBC$}p9bVQMJDR8NNK zo()q&8K&AkOtpQO8p<#=lwoQp!_-iQsi6#0Lm8%qGE5I`m`chpm6TyBDZ{=7dku!E zqzqF@8K#mlOeJNQO3E;mlwmq)!&Fj+siX{3Ng38fTx0o_en+D2O_c-AwS47D&Za$@ z9kP}$V_lt(*=1jC*jLv9>p9@cun9l#U~7Z3Ip3{zyKumjn|#}d15UQAJbUBWm=w00 z;>Z-XoWhnrP?UDeO9hMW^s|DJ(ighdhN{r%*Hff3$6FrcGIVl>^STS#PGOSktjt4_0H88{4g@ zo7Q6T9&4VZ=Gt0!x`yl6?LS&f{$Dp0Cdce`5+)zAc>Ho6lU3)5*oU@K9B}vFz#MRw zsnEIKj=J6c58Uray@Thf%3Y?D?tWjY>T#Fx1efsy?l-0W9{W|5yNoBej3>B^54emE zxQq{Qzav%kIPbTk-ou^-WFxW(c^^_3a~V{>460uS)i2W}xeTgbWTIs>@x}|Pidx?zM^cCv?5njIg59;A18!GI4!AONwXLl?J>SXtzV$yR ztpE8mr&nv<^|cgz!)^YgOa5rc?`=6`OKByK@a~Mb#~(O;-20o-uTJH67x##?OY=tZ zKbp-xocBM<#3J^gO&oCF@o>O>avcZUom=LByR!@jTuliMxbN7izwY>d=6s4d;QH`2 zeatrW(G~2&v-A;Z^bu+F5oz?{U;4-$`iM08h&1|$H2Ux_efXC?{!Slvun+&zM~uBGzPkvsI^W%|e+`tUM+ zc$q%DOdnpR4=>Y)m+7Mm+eiPk4`0*AHStC-+9jJ&WvR*mSFG>4PS>3SPX0xXs1gpi zT_1-7?ibb`)-DFMtt||wdv?-$7ZnuJ# zuIGR|4q_cAH$Dz-9S66LlOZ2RvyOva4yb!Qdue7u{q05j*jOv?(y6(}as+2S)#fuQC*hYF-ts`C7#PNTbE_3F3VJ1mZ&aERF@@# z%o5vWiORENkXdraEV*NrdAcljv=YzoReNNW1J2D6)d_Vr?TOl_Hb;c>ttd;}8VB62 zDhJ%d_BuwK%X%Adz|G;C=I}~$Aomd=@~@DO zBfpOn2i%;k4oGUN#3w#skE?RPxjs?Th|Z=x>bF~;=;45qi&MH<0SDZ!0#{axhXXFO z)3)6jitG2cF9)0|T;hPME5QMG2Jdo)$ma|`<_tQ022XPaPjdzza|R!C1|M^VnCA?h z<_s~<89dDyJk1$A%^7ZTCHA2zTa^RO!vR;M*G_Ixjsq^VtAw84rW|mp(X8iyJB5ay zLc>p?;iu5>Q)u`pH2f4AehLjgg@&I(!%v~%r@+!v==rINwOYOE%~!0crZW^ahI)-ITHalL#6Rk_O7bZ z_#gK1Yx_`nuegR&nltNzvK(-4@d@rKOLaQmA|iCxSE{o47P|bFeO6hdqI1-_ZN09e zcNTQ^Mp|X5Gu!$qOU*{vxC9j~H1zaRk;yKp@>&kKT~!V^UF(Q_Xe+JHYdPS`>-XE} z_uF{vxAE0)qnB@EHE&aac^fbNHvai-e8Jnq9&eN7yv=!35`n09TIGOKJl<-rg!KNn zd~=cF>veg}7md`~`I#yQ+}fGewH$Eerdl`ViK=X_)t!cs_FpE(@y@q#b;d7K#Vj@ZqP1w3sT5rH-OKYv29hzHRHDz}>&&71Q%f4Da<634` z<@V)(D>vo3xoyj0ov60lcOCbU%k*Ipeb{#S=@Z$xJA)z%_fDVuK6{jZyVECiJeRe5 zXHYchR(=LW7G7!w<$m_d&Pz>=R63{bx9^YGaM|f6mg|Ab@2nn^?>6e4x}LWi2b^Q1 zo7nM|IN)}NinFhu+3f4*+gyIan<4v(S}joa^_bP8WA2eX4n)|s360VwSH0DH3eZJLO9nsc8fE}llar||*P*vB-{@idi;X=3DQ za=>Xmf0{^nn$MpG<)?|4r|Abw(+QZS6EF?FPtysQrb{_ZCt#XRz%bgBrJSZqIZY>En(IDIq&ZCwV45!FG(CW6X3wVSQclwYn5ITNO%Gt2 z9>BCOVz0O>9(^&Ostok(B?rHS(H1>QNdp?alpT?d~Q<*%CJ)b6CIE_7@ z#-2}eHkH^$Wwm!j4r^^g?=0BHt-$>zRi@g$yUP7mT$vR2Tgb!x_SLf7Z?B=puc61U zp&ze-POpJZuc6Jaq0O(MQB z!~M3~<$mLdTas~W>!I72`z>@sbHB-+G z1}T<7ie->unV4@Gj93OEmiddz%z!Kt`7IOqEi(hMOysxB49GH(-!hTkvai9O=Q8o% zGV$Ls@!v9$-!f~PmWlk9nf_QN@>?eITV@7inHi8}BEMxKzh!1XmWltCnE_d524tD| zZ<+XSnfPy+_-`4sU1pwYnHi8}WNl+;1(vQ|`AG5BFQMQI^*XgHN+jrq*l} zy)+y7hi0Qyrp++;G#kYt%|vr&Jn*{J8=Y~)#*jk5e^qdHtO3_i_9 zIM57(PcsZY%|`Y1W}^yRvr#_RY_!g*83vzb7<`&d1AFd8YQ<@@QLVSxC}L3xK zWq!>@_4a1-MWpPonXIT+QY|q-?d>XmYFBD1U4=Uq(id zQRF`4SC9`OA4Yx+`E}$skl#c;f_xMyFVYNyPcsZY%`o^h!{E~lgHJOIKFu)rG{fN2 z41-Uz+0T0qAP*uBA)iD(g*=Qrf_xhJL*z5aXOTyd$B;ilK8JiB`2y00#r8b^4k_-p zW_Wy>%}JhH0Y>ZRM%9Uz?C-1GZ!Qk_b-CEwJ<>d9(;n%JkipCS=D2y)JMH?~)xHG> zd0(yNeskWK?`ODi@}4q`9j&1UJXO$twpGyAtqb@APVZ)@f}Xc$sw(Kbb!B3KlIN05 zMC?P`?Sv2Ox!+Fx#<<_S$PooOq98{Ub|5 zw(*3|mqxSGR8rDZQqt5=(o|2<^v%-LP|{S}(^T8jpnjSfN}3uZ<0BFWp8`>ou>+eX}PvSne9 z+YjGipZ`Ah>j&5`PklW+@8QTEY`F(p?x8B$gGKjH745;Ud$8ypEV_p(Uk`tw2fOaU zu6wA*_F&yTSa%QB-Gg=aVBI}fcMo>mgI)LdWYImWkL$srd+3e#VAnmIuKqvTwl>Rl zzkNrQ`^~jkZ>FeN)1tLwgdVGX^t&6|ttgw;&aPIu-!9%Wc{RNB{$p29Y`gmT8<_iT zke-P9t*G0r7P#Mys@&H7hEzqf?)Rjs9yf?57{n8}-;k=Roc9}26-5r>0|xN{gZKdV zyHQn-^L{I;xZegr^+BxP{Z`cb*e{G31l0#Y^+8a5kS@s}s6NO%#~}TYLFQuy>5>f6 z9~opaW{}C4K{_LYRN4pWi43wXcF-5$uSAhwL4FnaFwzPB+^I{X(Wj>l0+Iw zB8?ftQha@pZk{Bb&{9O_+lf=s;$sLk- znIySG5-*d)%OvqKNh~3Wmr3Gfl5}B{^k0+snk0A08@*_kY(_l^$Af5(`V_66J@?yJ z%CI-`GU_IX5l}w5yq8h$V)dB3m(e>5US=Ovs?}qztC!K4ZR5)8tldr3GHrzl#h*Jn z*ys2i^+cRaen)*g>t*CF1FRl@zYyCnBp znW>RIt={^?t;_xPhh@0mw!*CSNqhH>qu0l|rCu8Z&`oDLuN3#&o-*r(Ll1h_4Zmx9HuqQ$Q_D5I8G1I-9QACpEjm9ynn?b+%l-C; zzV+O1&wyCZSnuKUJp*n%18zM-hWreg^$h5x-lyY1^>d?srOrp^v9VSaQrlgcTilTTPn z`mudTzl3NJ`_NX|YKm0bFYdPdZ`Zh*qQL!j?qhMkWw4P9|A!1Vl0i!|*hmKJ$Y609 z{C9@fE<^5^A;QZL|77qf8SY|+*e*jN3Q08REGN zm7@$%U52PGLsXX`s>=}7Wr*rB#1;HA7u%2H!M8 z#yLaAIfI9q!J=l!IA`!sGkB;OeA5iRX$IdkL*6+!2LGEw9pI_zcWny&M@&i!^H0l+;1~*zs#uiVT1rohV+ zdELI;Z>n&K`|S@)aKF8bcX=7SdKn+{GAR5qp5|pd&CB?hm+>(#<6~YX=6M-U^D;5d z%XpfX@iZ^vXpyzgKBt#lfoMBi!zfHN{ zRHIqX{dN)!KZ%B)M8i*_;V04XlW6!!H2fqQei98oiH4sxC((1w^;YKf6(4TC zVoe>VwUMyiS%`#h9qzZhQm^LARqi)cLn8K}tu$BG`(?S`UPG_lRhDT1)aT-R$1!Iw!X?zvr#rK@p8ZIUgdt1 zDzD{!+g;^;)3uJ+hqluCyq5c|ynerle!q#weiL8)CVKfMb(lA)z`TiKf82fY$epNc-Dt)eUzqz@$uD-Js*}A*H)@c>n zSF&?EM7O$X%I+$vKiXI8XI!h?Z+0Qzuk6F&cl5QEn{wUUwq>!(0DQK}RC>-eNiLJb zB9a_ae){BY`#J6miY(kaeIh&ePM_4VN7nA0L6NnWpFxp@mzqJ5ox77L_USd+u;0Ej zVtWcs+*z&%F2A#SOuna}cj|iHZrpFXG15)!xXS%zH6vml+P2iKyvA>;`ncS0lSIUm zSpOt(@g&+ki4T~>J|>BdCqem1V&qA3z)2$INh0M*DjAd1>L!VoC+P=F(g~QP6EI1a za*|HKBwfl$Isub(0w(DJOj7-yq)RzT4`7lWz$86@NqPX2bSWq4Qcltdn50WNNu)VR z4`7l$*(5!HNoLO`=~7P81DK>nJV_5=k{-Y$cWsjUChOL=QC6$ITb29GjR6#OIh*!q zGR?;ODzz7d`&;0C+g;^;(;QL6xulLCd9Snn>eUbHum1FFZJpcCZo>Wc5?1{ZR{auI z{Sw*kOJut*Vb3pN&o5!mFJaFwQJH)Rdwz*{;U(<(CG7bn&ZZLEsI2y`$YHfAl*d-R zvw*F)0{5F#nQD8m%KcVcnH2Y1(8K-qP+9J`SJ2~E(BoIok5@paS3sv%(B@ar=2y_E zN_13}%*`w5PIQ>BT$Y@HypgJs`af;GDyiP7_10eQH?-9m^bNY)Z#;2JGVUze?acia zyrH?@WKZ&^szWO8Q{6k>3() zo0f?DmYDunBJx`z@>^mCWQiG&B_h8iBEKbOK$eLAmY4xqVg_W1_-~2$Z;AMCiTG~` zv|VDJYKa+;C1yaDm{nV15@ZSPwVSz;1IGuCVKQ|%G9 z>kd@8-*h#++jZxDbKIS+R+Z&`3s$+`v}Podzj0gV_HoyJ{&u+EIyT^b>nP%W>#*E! z|7f}2cK%Me-*#H>Ys*ggt#K6^P9z^~bQj=SaM)_l-`7$zsj3W0TwfeLX2A@V4d>Uc!X@tS25eA<| z7rx6C9Mi_h=Ven~$!KV=hpGFvb8e#Bhgu$l~2A@V4d>YMu{^9}TLF6Ii zlgOu#hml8+Pa}VbdT>$%^2 zrgQsOzh!GSpX%Ik_R2Q@4x(cD>1|hkK-}o|WgfBn^js@4AI(4igncfol`r=qM;PP? zgB)RyBMfqcL5?uU5e7NJAV(PF2!kA9kRuFogh7rl$PorP!XQT&@E*a$ho zAV(PF2pb_s7~}|p9AUWM!bZpu206kYN7zKzBjgAhAx9YQw=l>N206kYM;PP?gB)Ry zBMfqcL5?uU5e7NJAV(PF2!kA9kRuFogh7rl$PorP!XQT&?zb@9Z(+FK!f?NZ;eHFl z{T7D%Ee!Wt81A<)+;3sH-@c5@4qwNFVLHl^~8o1wHt%&nfK^(7xKRpRNPe&&5=^-)xekxft2BueIF7+eX}PvSsPG z8+$3wR*a?E=r(>zbo0EMBfGKXZfv=ms%SSB-Az@r8@uktqPwx^ZmN9U{Dp4px*NOh zrXJgkb$4Uk-B@=w*4>SDcVpe%*mXB{-Hk+Zv&!PD+;6VU zdNW1EnvTtSuo|P>*ltDHw03s2%KcW%{r0&VnES1d3Z46HsN1a;xZjC-2hZg#`sk#) z-;b(#TpymG4^QBJGped`-fu=#J+AzBqN*O}{Wer_zx9FYeOSNyZK(ILUl`K|s`r8F zeV}?DU6MXfy^qP5KKdhlpim!Ol0Nz)eN4vmF&WcGXQYpwNFP0sKGwzd`6B!kWm0|g zMEdB4^wACJvwPQN3RUhmu1Y~TvktmWuBTD`)!E!V-grS(QR{o;NDA?SeYG}2u)Dmg z`}OTK!7BHgGO>trf#H7pzK8qm&UM^xcWjya?T#|sZ+Dg8e*3dYFOM=`XL8Or&(nt_#B#1N;L>dYHPJ&1yL5z_g#z=4u z31W-{F-C$6B0-Fiz{@0vG!ovuTfNi`L6*mHSQpMUJQv?zdo-`%QB>5$B@YoaGb#AGCec{FyS`Z(Cv3 zQZMise1p17vI1w@s57K<(Oklv99nMfUGdE7F(v1oZVB!;bkmv6t8%|dn%_t1CzC^~)$+_b~+t0^q++ufG`?HX586u95cek|^{QEX%s8yUq$M$yty zY-AMc7$vqF#ea_y+l`VtjuPRG690@6+l^A28YQ+HC8`@Gsv9M$8)a3+DACa<5z{D@ zqfw%|QR2B#;<-^ON25e_qeOM1M0KM?b)!UeqeOM1M0KO&j-$j}qr`Kg%+`%ERX561 z-6&DrC{f)g8RRGt*(j?3M#&&YnW`HlcN}G&Zj?J(30{5G9$DpnbE7xS&^Vj+C?mJg z+ZygS$89J)tBCt8Sml0u*j~qob6IZ#?zbs?(-dB53gn)`D@}o{Q~0JSywVi@Xo_5O z3V$?3mN|t#n!+DVk!w!jm8Pg_PvM)U@J&->oKyIwDRRvzeA5)ZX^M<<3J*0!b!!Sg zHHC+o!b45rp{DRqQ`EJl@J&->oKs|+Q+TK;Jk%5!=M)}l3J*1fZ<@k4P2roS$UCQ~ zaZTZ&rnvu8%>7Q`r>3ZJO~L&(#l-Iv+;3A%{7x~sF~!916w?}0O#Dv4{Wb;n+Z5by zQ*ggc!TmM`_uG{3ajR=nzV9Q&{We7&HiZUO;uD{+M^?GtT%Y)PuA7ARs2X5>qKErU zE>8Zi0`9k9S?;$7EHPHY8cwVScH4d0oNrRQX!&*znVX3NTJ(MmLpy%Z=Jw7%YF33y+;5*L!Toju?{dQ437_u-KIR0G&j~!u2|UdSe9Q@a%n5wV z31XfTc$yQ$JSRAh6L^{vcpBUAvs)$hq5oBt`_04sR;1TXzFUs_ZO_gUdVZU7zo|yE zp8M^2H2irq{CPC|d9?C*H2irq{CPC|c{KcaH2irq{CPC|d9d_(^jx#Qm1(u?a`P2y z>Nu^pFU8L1%BIRhBxlt*^4wY?O^lyxecWRqi*b@>=e<`h6b#K99#fkFP$DUY@58bDj#!dA#&_{PTGtkn_YI=gD$3>sp!Kf7%{b z<$hBwsJ3GAT_rW&Qq8QJpQ&=ct(|Fgc%e3*YTcM0s5wT7tPl7VMFfhi`bz0s1fv0Bj}@wS!(v>PdKsxc`vdNc^|TP0;ZWg zT8rkLfN5cmJg_?lW1p_cBr2V8l|EOw-`w2WJF}9vbs2AAX2rgeo!gqPkt}gdmxhdDpZCe(r44^#sTY_9Bfkh;+?efznvU7I^MHcRzK9QY! zr%&qGBWw50plH&q{0xdLywnWJ{p^>Wmzo->)Q0``{SjNIar%kndf@UqtH-Wj%%(hWa)mginbKiB&uElD7ud}&(^v=Sb{LHIklpZVILU*UX&f4Gpb3^_xQF>}R%e_LeOfIWyQd!#7p!vzKhjKK|P3(R21;Po7$I z#QxN_rEcXlepA(2?zdmG{oA=OwtaY)?^LAi->n@hde%xqS-yU{UcjDiej6hu9^>rC zh>XY3?=if<7#1={d^|=iV~i+yj4W`B&mSXJ9^>=JxPN0r%wu!}#^?o%f%9V^{20A} zG5VBa^a94{1&sObwdXWO{eO%;?A zPFFqRT+$L8aIbE{0rvv7{Q|cA0=E4ES?>$z>kC-*3t06FSoI57^$S!eU%;wgz+=3C zRlk5$zrfj4VjGp!;1xlvwGF+qU>mmr2VBtQfD2VQ;67>ZZp1#cMQnV#+rt6(m9iXg zKS7Uwf*$__{rCwO^%F4aCus9e(B_};*_G(1Dw>;D)SW0X@8e6(Lf%N#N&TO;UY%4A z)p~0$2OQe!aKMFJ4mh5;r5QKMyPY}UcHht(aIz=)Q`I9C1uDkUYdu$m-`VCtig_$- z9^0D7w&t;|d2DMQ+nNU{=0S>ikYb+5Zyt=82P5YB3-io^%oG336aURq=b0z|n`ahe zp7?K`_;23VU{7YAGn^+1oF@vLC;ppfjnh2w-#k+w^TdDi#DDY5g3J@O%oG336aURK z3o=g>IL|D|JhLG4M1k`}f%8Ox^UQ+G;6hanIISIt zDL?e{_BlAOTAI9UvE@TsfWp@ z-pKFQ!{k#BlTW?TinMy8N?g5BK38wF-l`rZpL%Lr^`?P6!i{>$_g z8)bg=Ms@dk^F`#BkgB`ao1MsANX@U-n;=q^rg|eLu6m=@j`cA4)EiB3)f?rH_2$dS z2r`P?hx`iiA>_lzuOYvV{08!y$VZTmBEOCN4zdmTJ>+A^zeZ{*uO23!dYF9bVe+Xr z``Ld0c@TLB`6TiwBA-D%i#&=vhWruoIpp(5z{g zZ_M{K+&Fnp8Rm}G&;$BnS-UxNg#T=-p|4vP@CTgU%}@Nv2F~qXq>v+Igd8D|BLs4U zK#mZ|5dt|vM#vE|LXHr~5i&xKkP&i(K#q_Ra)dyR5Xcb%IYJ;u2;>NX93d0o$S6|C z5rP9Q1P5FQ4!95;a3MJ0LU6!^;D8Ik0T+S;E(8Z$2oAWA5psm!fD6F^7lH#W1P5FQ zdeAvoYdaKMG&fD6F^7lH#W1P5FQ4!95;a3MJ0LU6!^;D8Ik z0T+S;E(8Z$2oAUq$PofLLSRM+4!95;a3MJ0Lgp0ba2k0A`3mw?zrK_k$yXyyGI)A z-J^)6u;*L$sf#qlyfQ9iTnpOR?z&r)*_;DzcOGo=X!G|LZ5r&|yLr$?5v9;(kMa2) zu@8IlR16~ar?yHt;7(lw3*0LevB33kPCe*$54DsYYAHQbQF^GK^w2-+p^DN&y}gHe zdk=S_hbl@Bm75-_C_PkBdZ?oG&`ax~i`GLerH5Kd54DsYUxU30JwEAX59?}rsHODK zQR|_W(nCkBhhAC_6_p-pDLvFudg!S2*!QpX0G0OGb&qs!?&34b`GiJ(n?EM+6ZFo4 zPxz+s9CKZLg3fFkn#O78h10_*_6f?XoXzzKLcYSDR{PX?02%FShdpFpZ8#^R1J=*U zl!+)Gc(7IBq}`l|@_$$x{||dNZXO%I-(Dlx_HJF)Ig?79=X?xfn+ z$zSN?9&}>eomh7#mC{aZyb~Mm#Kt?Rly+j{o&4WBvF=Xaz4nwkvFlFkx)ZzZq*B_+ z>FWQZ&B+fdwOL*BDi@qnk1eei4REP z1Csav_d8Nmm-Bu*s{CKl*MJl%y5Ej^AJ2s`Nw7UhpCk#kC&Bh4*q#K{lk`cFOv@zc zmL%zuB$<;*GAEOyLz1L7lB741WI`s1|4q^%Nzxlh(iKV46-nANSQ{_gSLK4^suaZ5 z;{{bmt?!W|DZ~r*)!IzK?pn_U7pii>DI<&IZ$Ro_es$sr4;S2ybzE?t*fJN~C(3Za z-C2SQ?g<-LC_+>{UNMG?)jnSrzNU*Ahc0SpU3iu*B8@I0jV>aMF8oUu8AKP6Mi-Gr z7m-F6kwzE(rHjAQg_r5VzjP5}ba4({#28(~7+vHMUBnn&c$qFDjV>bIE@F%>VvH_w zhc3KK7ha}|ZfqA`ri%=s3op}!m+8XGbm3*X@G@O^nJ&7qUG!nQ@HJgr6ZeWZ(TjG; zX4IP~Fu$o^p*Xs*N70KiZD&uF3(j7O{MB%x*gto6u+Q0}-iWg)=21V-dYP?q!O6eK z5mmwk7pii>X+9_7Ty%GJee)lc;ey)=)7B^LXFi2*c#2Q=+E8h0(77zx$DO>RT#l}I zX7!ko^G~+~7aY3D+W1hF3r^Y;(QUVz%LVsGzV%#i`$4Sz)_eGT`@yaK;MRUJTfUF$HrRe)Qs}Sk=;<+K>xgjb?Lqv5$M0G<%bwfmTLqv5$M0G<%bwlKiL&RJ| z+>0S*?1q@G8)CX{h^TIesBVZ1a)^j*h&2{NWROGTjzi>*L(J6;aYrlh4AP1!7o1z4 zQb*L;v?pqx+URW!7hH(f3ePIyf(uo-;2yTuG2&d-+kgvh9N#pKR~iSo$MH(zpzk=o zX&kRKjz1bF*Br+mjgw`LLjc z<8Z-^!v!}E7u+~paN}^njl%^u4j0@wTyWz)alws~hmE6wmH5Ob?2%P2IM*kBp6e!| zJ*oy+pXlL&lZ%r-tbhwHRE`U7&n_)qEsnez8ur|#TyUyzi3{$JN^rp)!@C?K@;Qc& zIY#7j3{P_mPjd_(a||DI3?FlhnCBRt<`^;0F+9yNJk2pY%`xtCCHA2zTa^pW!v$BQ z*G_IxmJ5zW+H3UuHsyj-jb=R;+_Px-vuOCUX!x^e__JvEvuOCUX!x^e__JvEvuOCU zX!x^W>9gp$CWM^~RzEkI?N$G1^ObArIIZT<`5amAEab?y4i{WrsaNymDi>UF4W~4B z)-TI)!Tkiic2`@f)AIJU)#sl>pFU8L1%BI)s{N5t*^EW z*mv2u#LER2TIGV1DzD{&3zg)8v#z<=J3G%C8usq=PXC;;^&jz6$oB2ZGxM&mrD%?d zon=Hret*j$JM&)VnBv_L_xJeb3&CitOf(v;y|D4tQowj&*^US@e$|=qNGpq97whw#q zWWW*oQ=2>YwmBDEx#`x88KWwjZ*}Kkr2k2x9PjkY-RzflOcLcJv7#hVPLeo2i4}RL zUp~X}>WwFAP&vdWybF2scRv*DuKrKVPb@iBhG^TeJj(Nn~$Gh^MQ{Y6IM ztH22tvai<9x|Tt^2Y2qZ*|;`m*7fJs=4CcFkInn-^_9&x+dCYw58cTI`-s?wHrM9e zSyz`6uH3Zi<`%Ad>_h`UzbjIF zC)~fby?^EXyS80@|FMrEAN|9)Wx)B>37_wuelB_LXZfz>HGYHD$LE9_CN>_%{)dT> zhq0+)yudIPGEAI2Oig2$XnB}yaG02R7_=V-?T118VZ8A$as4nofnja8F#XD5dIH1rD~E|Whv^0k)2|$+ z8!*fi+A#gfVY&gsREvk{1`N}$9HtvEOlNIaj%AH!DLqrO&mLFhgmdfh^2*MpJtaBe z@DY_(HEeA<`-q;{jVXxtI_s}q{jmP(PrugI zx&4(*IN^?B+efkOquBOQvfra*zelm^qgeG(tokTceUupfC{}%xxZx;PeH5!c%DE__ z(6&+4va(vd6JvTOd-P8I1!uD7R^WsSxtwr&s+@4emCA_4z+E0rxP4_g;YxkWkk(_k z-!G)kb-!iEKCQ@qtFpOyW!;Gqy*jFQ7IgGRs#5CAwqB)FFV$9Syqs`otHTMm$K{0M ziCdy^XVY$HPPkn+G$)+wN&ZxINv%InjHTClu1deN!n}DM$R5V;Uq!{FfvC%P|v@VxqQD$8AvtD3a?Gyfm<-9W`YFd`NDfZ89FrkACPQ*ehUAzG$uSv{;}Uxj zQ@e!ix&u{CI9(0zw!T93ZF|5r?o{!SsuE}`Ff@G0*}=YTJpVJ#9!(X>&$%V4@9cl^ zhex0L%O{^Z^5pSvJ$LBI=Zf8(ty-1kgxgc)g!_1$aPB(L-wr3-r42aYE){XYU9y~T z|6n=cg1=KvxS;jEHaW>}bwWu1fbw<_qI-?nYIwQ|gXH@a4Gpfhc!R%9K&#B%E~MsI z>r4ZB|cMYk{6)v@_DE-h3|>w+$IYu^Vb|NP_Ae^ngmd1Q?`ybma+MSA;T>&PKX~t>?Wub{ z+VN;xr)3D}+_AsyBdQx>3Fua}^s%cawq3n>@u37K+$VlhoN!*`2!I>`kRt$c1VD}e z$PoZJ0w6~Kl4W zzzG+C6D|O91VD}eoNxg+;R0~N1>l4WzzG+C6D|O91VD}eoNxgn`Fe3mbTmVkE0Gx0E zbBc2~jXZ;V1^FuSEb<)Eii(itygjbU3FqR<`W!?NjkD>PZ`r3V(iHQ{xR7xzXk)wU zZc%2n_ZG5W?p$hO?7=E0obO=U2fjDkPG18j+|MfFgzL8V+2`xVdb+8lbW=;|ri#){ z{iK`zSvOUbZtCsb)Z4qMqI6S5>85hiO%7{j3QR$|Z(oHR;n~qwyeg9eyP$|EZqW&r;oa+;m zGdY{~))erl;J?p=)580D4 z(ujR%TRSJSE!=k1*ZO8#xkAH9TqU&6jGVcD0c_g&&IT%uNb3H!c;eP5zhdI>AP zgq2^y$}eH%m$33nSotNc!6jbx`SuY#UdP)6NU$j_aIVOa0^3U%Pv}nWJJ)i{6egdaQSo z`ItSTbgFX0Me^6T6gOPc4a^Ofpkn8Kd+K)kzi_`p^$wozK;DUzO(gIK3H(6Y3A!T*x+4jD z25Ws!l^ae~&*IIQeJJ)ls>eE;>w9!B3wu;0wZ2D=q~Lk%tF;+}-L;+@ZcmjPPMKN6 zxtu<6!yWQ)!`-ot8*clSx#6~#;fC8$f*bCT?E>hIyZu<7Yy4!OTtv zh}=QE(Sd*Iz`t}5X>^cDbP#WJ5N~u4Z*-7PbntgN@G>3vmkuJ04$h&2u51U9MhB5b z2UyvGm+A1`Yfr3$u51T6LA=f$;AJ}SG97rC z4!leUUD*!$u^srD4laayMXKCzdBrIDvA##Dj>$Hze9>WCalI}?IKL%sIQbVjqDr{o z_EfpyG^Z2Mjj@}{y7gbmaKmkddFzw*^Y-H#_Vd|Z8!A1=s&iSg4@EEKztiD1;f6yu zSu4M%$_*!NibyH!R?yP*+;ESBSdUx(TfUF$HrQzSbO!DTb3J6s+iZwqGc9tU$M#!xA7_q%L{k6U1@QRt1JrKa6kK4+;IKa zNIy2xkB#(W2mRPcKi1JtY}b$f?kBeECwJ^8!s{ot>nFDBr;5~1Y}Zdz*H2W}PgK`W z<*1*iuAiu`pZah=QC&arTtD$#Kb7HrqPl*fx_+X%exka5qPl*fx_)Adesaft;<Hq=DB@h!+khKx1m84*R~iAiNAOA`pzjF2X#}q{ zfrV)J82pQ)HzG;M9a|GWsf^Qlj;~c?5 zjZobh!B36gp+@jfBY3D0Jk$tvtr2|F2pQ)H8RrNdY6K58LdH3QhZ?~{jo_O`@J%E5 zrV;Ya5o%l`c&HKX{|IxyBlxKiYFs05!;LTjJOVe|2-8C&OaPBC0X)J4@CXyYBXGlw zzzsJ7H{1x^a3gTTjlc~z0yo?U+;Ags!;RSLfX_FA23Fz|pRh+(x#3)&s2LMy(;oHT ztxxoD!^y=dU9Er{ZckZmxIMdUldZVNe*1F6slp|0xc^du8}4bm%hN^V#K@3*g{`^R4V`tDtnT?(b+!cHf* za9)%32Hf0Yubm><^FRqbzfHN}RHIqX4R;s~Ka7SSM#B%IGl$Xe!)W+nH2g3cei#iu zjD{aZ!w-X{htc!H+`&q`zV7|zE7;U=TGiORR_mPwt-f`*;quOUHD9iB!xh(XN^@yl zD$5Ob0=+(gMxQ{JPvAjMkf)v?Lp^~mpFqbd(b-SgBdgqS^34HzC9H4ua>MOe<%W|g zujPi@Q{{$}{zU9UTWNh>%MDjvzfYpyC(-Yd==VwV`y~2(68%1jmp+MqK1l>}lGx)U zS8q6v;obFmmAJeZN=ofN@~8=?5&-jsdB?@&J9;?%5`JrsLJMC z-FX=4e}X6{L6qZ8zue7!S!{wRCxI2Y(=S?`mcWX<(=XzQN>C+8P{&MAD@af)NKh+C zP%Cg}VAP%VPQo}dFvWycW3O%1ym)ZsW3CCxa}<4%fkXbYK%5*m(Il6xq9X8bukkJBK2Bcc)Q=h8^Up zrKV9d^XAT^Xd<%%t1mT;av#5yrFW3)dS_DX?rXGV-3#3Vr@vTk2DU+ez&$3PS?Qg+ zs!qLNpJ}kqSC6@_^#YyQHZ+P;$_wZ2>zswn+A5rZb&Ru6PT=(>_WYygo_9gqtuRzM z;wtK1UgI}gt>uVoZ~M1%Uu^sEF5jt0+rL|D7B)LouOIN!^#xY-^IMu2IgM_liImgm zcN$-iM*Gvm%V}yGX`<#dSz(&bPlNhtK0i(ME{#`C(;-OH8%Wa|NQ3uj@IFo7GL7Y@ z!TU72o2DO-rf-?1E0CrukOt|~bOqA%Ez|TZ)ARW%$0%`h|X}SVwI&5jKjjUYTMpF#??C+}_ajs`+=6XqJk0#b^9>7FHksGl- zqSDHINshP&yft~JK5wg-Ybutv14rD?HsOdnf^8qcwvS-jN63PYkOd#Xs*hmRN3iN6 zSoINN`6F2M5u%49SoIOC`Uv;965FV(ChyEi=j-+*Yx1`ON8BElBW`b%Bd)k&8L@@M zRu4y9v@A!Qm+Md(cod8}3PyPu52d7)=%{8RH?OdlnnKe%^%tBt@D}BWLt7ovq`fXj z98cCpdABo1TAwzAk(7Np366j_iW3sPi3iY$>| z7L3S(5n29Xmi#YE{Ff#E%To2p68~k%L$btwS>nH}ufd*SmMAbw6qqFn%o6`)$^Wv% ze_5tNvc!K`;=e5Qo-DH=S>nGe@n4qNkStMPmf4Ujvmsfcz${TSxGWPQStdlXOo(Ke5XmwjlC__*)*ES$;_^G}qskGd ztKr?&uYVA`)9;WY&T)6PdR3MqZf}(%PBToA{EgcdPTgbKf6i6T0pzX+{q1nXUEF{p z?qU%~+(pX~_m<^|+w(i+h}+}gh^sZq$7^BwsWqCfuQiG-YK{Cut=WN8j9hCJi_{v$ zP_?E8sj6J9A=5XS1*m0)rPe6duQjU5)xz{sYlH)}F#XiR^iylJLao-Q9#?BVixfv( zElfYPMl14bO#|{?WD`>L_gbT>T&>XrO07}mS8G&(sx_*=*P1UOTaY`Esx{Xd&9l~; zAX2NXYmJzGYK>Mu)|x*hHh zPWVuQBkr!>6i1vFIs71pALQ_Z9Db0)4|4cH4!;p{_(2Xo$l(V${6@&(2RZy8hacqd zgB*U4!w+)!K@LC2;RiYVAcr61@PizFBjoUd9Db0)ZyMMmBjoVI5$A^^&JRbNAC5Rb9C3b-!w+)!K@LC2;RiYVAcr61@PizFki!ph_(2Xo z$l(Vw{BXqi;fV9Y5$89jIET~7GsstvuOiPP&mpa-2x-pSI)`Ev1uM zN+-3HPG5snw@zv)ovgFzq?Xc2N3D}uN+%t)PI_sbR8%^trF2qD>7=99iP9<;(YCdD z8TsxiN1W>cgnZ7XJ+1bs?TyK3S6gFy?W+y@>pEclyiAoN&h`*~Wgjj_T)Bz3jX2_D z)6#OcKdy{hnX@XU+xRJQf#(-E@&Yz}0h_)+ee?pBeS!Mu1?>9*_I&}%zCgY20)OEG zpM3%QzJPsSpjLVTE5Cr1U%<*QVC5IE@(Wn`1?>9*_I&}%zCf+?0+xM&TImJs`vT{E zZMLg?zRD5j+O9WqRP5>4t~ExF^=`ruw^!6oYiC^d*snP*USsC=vs-sQnEwJ~hvV@d z?Y!InvZ{FV%)7;GCY#*{C)qNuNp{*20T;mPQ5!XeJ#Qiqa?e>4*ey8dk zJeSYtqO%xqb|B8UEHBA=4HB=m+7KY(nXJ? ziylcAlQLc0$1dh&y6BN~(H-fcJJMzU>blIKRS|)YcW4@Ihp#kWjr2zPau-LJo6S=l zarKz|+<@LGf9LdMA0cC0J?6U3=IP9~ac%9B)$KRK5hu5@He)Es5x2L>5vR;7lE41q zh&$}zi2KAkjySuzxb1_151W0poqyW-GesGn%zSX}VB0z0r8|GQnn%3XcDL_;U%hna zr8_@r-d2Vq?v4^1afi!t#I@sV+L_sDr%Tw5XKBYO+KD&Xi8tEuFYQDc?PL<|#2f9z z8|}m!?Vv_G@kTpdrXBy%j(=$<(rBkE+fJm>PNdOJq|uI-X(y9t$IG-6X|xk*w39=$ z)0J(<%e2##ZO6;BlS#DWW!mvF?Rc4XETJ7Q(~g&Erz_h|KeioT)6QM;MlaeWn^C37 z@gUmsS^H2tUDzYfr;K|eFQe|lVe4h&qsy~msh6>OOy0}rodqwmkE+$`G1t}0=*+Go zN1XhN98o14aeJ#Aahf2C*oQWkee1JjIO4X#!1YP{d5@#lkMr4H8!C;tI+rE;xRZC3 z!(7K!^2g+@!8-@_>%2YXkGZbapfmH~9eI)$wfUd&4cqV?HkS9UoJTiVGrzaW5hrbm zXZ!g-%##-sbiC(SL zI}1Mgf9GS#8$l~|W;TjI7KAqvR9D_=rIfFbU%G4F_d4WHP9C|s%EB&=DxF2{$uFC7 zvdC9$7J1R$BB!=dYu@#>6xnFueAYi}$nR=7WP6|Mf4y!`#6AAN@#E`$Sz^bj{J!GJ zAMN_8eJG23!eX^p!K7d62Sw~d8{eEg@UK@lUS(nV;qJCPao4!YqQDV%`eSj#^TjyDJK`! z#nYas{VDI^U3lTR4TWd?!pk7;?k%j%+*{>{d)Qvbh<#`i6M@q+>KyoB@FDx^A=^QE z$oIXrU;4h^7HRA7{Y6`-?b~e~_ey@?@kbs1@XF1K?ewJsgyhe|- zcHNg&eZANAJ^P(|I-3vd*=P-zp8vajz5_dVBA*{%;clJVI@J6&fNvVWD-D3$19+tY z(02geG=Ntcz#k2eYYyO#2FNl8@J9pqqXBZw0ld-x6|Dh$(*V9{fQ)kh-!wq3Ie>2( zz&8!}8tgd@;GqVnZVhn$19+$b&VK+8HGqd2psqE5ZyF%u93bNyz(Wn-p$5n}2k=k> zc&Gt<(*V9{0N*q~-Z?;xYXA>5!2KV9BW?gcH2@wBz!5jV1n>YHaRW>M4=@2dzy$CB z6TkyZ01vw&Jer~iD?Fsw) zDo32_6F;xZ#il)~23Viy;fRxqlRvD0BW`bjORJ^8onoIfRcnM9gytPjiTv=MbLe5T51`p5{>g z9y|AXBm2msg32wl zX%(0@WnvLMv0Fahz2~7FKWKCDU;15&BklkiegF+WfQBDH!w;b02hi{XX!rp%`~Vt$ z01ZEYh9BT>AK>~O;O|!w3G4r``3g35oL2MbeC0;()L(GACASVoT;5r)=F3%%I8_@W z_Mxpbr`E-?9C1g{>!WD&QFQqz5uv-@QdPF2=<-oMzY?AOls)p-_ObQ4j^0_&*&Auq zrOwQ(tLu2HjrI^?Uj1}(wSfI;;}S1N+}>4=IH~elj<~&5jyPTGh<#`)tzpy zarFB*`h6VzK8{`<=UyJC0&^TMeH{OMoCxGNvBz<;9H+chiQa$Oo^O>SPVsoFy%N%U zFGrlC+KS0{mDGGoL9=dtrpghwcE;7=jjCkI^%CEjdeQyX)cp6Q^4+O-?rN)S&effV zk^XlP<#?xGw8p?Y_o4{Poqkarx(h4vPQQGH{i=hz(=Y1sc2O(nqE^sFt-zguxtHHI zBAbw!x9p-;&_%7Fi&}v@1Eaof7qx;?lQ8y|pp1TQZRS;#X~n=B&#v634|b2qM`Lmv{kAyb_F9vcz1zvw z)wNZ2S5X}j+Nr$NyWNhEO}LA5Zs&PJ!-KamM_jq7*UfEQcUifBW?f6qy|&x?@AI{z zpY0q|ehx+U?wv+a4CKzC$ll#)6ro`|wZT%;C|Z;1&ZPV?&o%Sb?rT8aivPt6BG1OWW9%8}tXYW9Qy%jj(_PQK#4^%ngiYt~8+b`eg;fRZr<%lcw z9W9D!-EU{n=epm~VxO*w49m|(ZeC$`qD1c$ns+wxMygio%(h;wR8Q4W zIN}~~IpTQYmTKH6?{?;h+j&EC#L1rIPnD6C=ZMRI6d8~rgXLt1|1!jX8IU3aQe;4i z3`mgyDKbQU889LPMr8Pl8S=jj@n44cFT-p|hWIZ-y(dHbmm&VkkpE?f0y9K`8KS@p z@n42@j~U{>3{xQ);=c^>Uxs>5hS`t|@n44cFT-p|hA1$@Y)FRLkPJ~^hA1#Y6qsQ) zBm>%JhypXrhGdux$uPr~VL~LsDyR$-A{jX1GE9hMm=MV@A(CN2B*TPAhAZzyOzjf3 zYjs(bBTiStyRENOecK-JJLHIS+?}mnmF0+g;Nx(_y>0vH`>aa*0srlrp`ZSeJyZ45 z|36htY`8DY{dgR4?t0MQ4oBR38*s$ESHuzbp5=)9pOz!;f!`@d+ynO7*$bK9YK)%O z7-dm4M%CLIBY#n2bd_t2qMRC-erk+jks6~|r^aZ_MvYNbuEwZuR%0{^P-Em-YK-cB zHAYpr8kl}+jBua^rk@&^erk-W@HIyDxEiA>e2vlis~VVoYK%DIYD@$2UZkpWHAeOK z8l#Az#;7V+W0d*T7*(KZjOy<-=1WL1{nVJ9NY$EajOJNuOb{7Dim9u{h$F7Xh$F7X zXrimeD1WRm;)ts;5o8p(5BU}3L&%4bUqgN!`3>YZk&hrBMaqlR!1PmNG^JMq(@zad zKQ%D@)WGyp1Jh3pOg}X+{nVKK9De|L5P1msB=RZbVdN3y)5sqppFuv0R4=^-rk@&^ zerjO)se$RI2Bx1Hn0{(t`l*2H^mX>MUEzrqY30_0y&yMjwXwkfRCYXaYH!K#nGmqY30_0y&yMjwX;Kzb01E;TBqx<<;hw>b#c~1OSX|ftdfop@f9tRuby$u%EJq!dqYlea=O#Et zmZJ`ixH>rE>fng0gCnjEj<`BF;_BdttAiu14vx4wIO6Kyh^xbL)L}X5upD(*jyfzy z9hRdG%Tb5rsKav9VL9sHh^upDIqKkut8-;J>fng0gCnjEj<`BF;_BdttAiu14vx4w zIO6KC9CcWZIxI&WmZJ{KQHSNI!*bMNGwR@otAiu14vx4w_Zj~0SDF8m`D@HyXZ{BB zNoJeMvNYec<0>3+fnAaBz?yF^S z#7(lMNwjB@T*@T5lu5EEljKh(sh>@fMVTbuK1sfPl3!wyEXpLAn@O@LlVnjQ$)ZeB zOPi#MHc2jJl3dCpxs*w#*3QBtxs*w+vza89GD$^kl3dCp^_od)X_I7BCds8tl1rJS zqBg0MnTG(stp+a})8_7bxr@TNRsBX4j<^5;>N#hcw8!s}lhS6Bt@f&9zs!C+pu!R7 zB>XcO==d{ML->1p1RQaf!}}WPpS7sEQ9_7eUbb1t>9wk3Iie`_JA00)%N73(5 zG<%eM-zfiKlw9d3`aOz%kCH1LMaxIg@=>&W6fGY`%SX}jQS^Hh{T@ZLM?t<(G<%d> z=_vX=%6Zba(zvu z?kpL*;GU}2**6I8ta?4$%F>;svL4)J^=9^{9(NWzD1Lucd0uBhfD$sBQR z5stX(0vvHqS`|RQxbpIF!uz9jK9lEe^6 zsNN=1VrU<#O<$e#K|v6*h3>=-}*oij<`!<;JV2^?-O9dC;05J4i%2o zwU(FdaRcwT#yR4UO|F^WU*U+8G$oLVTq)hi5qCcp>wd!@$GIQ7bw76Ne&Xc&k*xc% zUdn!M@C}=LI`3q^{!;5-y`=yBqCHAW<&C`0KgRDM)jK8k$6WpK-M|qiQS@ap=Q4|+ z|88%EBd+hcwdZcET7T}y`Na9tMHrbb^D2uhN8B^-h$C(R9a%s}7SNFeq;vrtSwK4$ z@a-1B?*)9j1!BhqJiG<`p9Oro1+qvB_;w3;bqjcP3wU)4WR4c_>K5>r7RV1T;MFbQ z&n@83Ef6&>;MFbQ)h*!FE#TEH;MFbQ)h*!FEf6~{;Lk1K&n?hvw?LQO0$p|scy$YS zbqhq03;1>mTotguwH6D+jtj(&3-s45NLe#paH;Dq?z7`69C1O6sGb^cXiu|kT8x;- z5x1Y$a?i@*h}-{8IO39Gi?IZWdXIFs#H*i)@-bVd>Pg=-dm)}JSuu4LCG4T`?&pYG z2Ah^arDZJlGN`nS^<4&=mO-Uu@MxJ>a~V8ZCdypq_g)5%mWef&L8WDK+sk0nGT5|C z#JLPMEfZ@lgH6j|)3Q@*XM7oiS|-E23{EYBP|G0HG6=N{LM@ZmS_Yezi8z;uIF~`F zWe{qah;tc)S_Yw(!KP)fX&G!T4aBW@XvxMeuvmf?t7c8>5(Kgs+%%nvgUFsr|E*&gL#;$wDP zg(EJHATF|#th)|41hEP_&ft3%>YO<0MbZP%F_>J z+1Bh)I-1z3j|+||cs<(nbV+57xuVy6dznM8YRSTx-sf+6dF8w8m1O_K7Z2~*9cDw{ zpWW%j7T#;3-YgfQb&e7a`(d^pM#3LP!XHM$A4b9- zM#3LP!XHM$A4b9-M#3LP!XL(#K8&2p3X~_+`t2`%1>1Z0yl{-HcV=VccMnILFVvZM zxgbZ}{xE8L2yWONJ79RO;c=>e#XQ;F<_~%rwi!IxTkThsC;PAV_;-8Q;)y5|_N-Bu zQ|kvsIpUt+6P`e#pFozM03Dy;Q=cG0eF9m2g3m7}+o&~aZKaX8P+mvx%*yQ5bk(I+ zcIj7LHrl%ko5LJ&`!gJI66Ji3xcwE5IGyW+Jv0i-b3R90aru4{`F;}leiHe961jX5 z`F;}leiD>^5`2CVEO-*%<4K|%UExt4R{xqESK)}0KOVI+A-NB8#Cf7EpL};g$u|m` z4Lz9C2sK5}YNEd6ry3xcfy{r=2BNaMrnl?d{B7Cye?g&XOxQORnH7xq_ev=EM9| z*BBJ)gt6UN89iTG-<+;-t8l~xF?hIl#n*W$akh8GUP<4rnJycG=W@jDhjyyM5hqc! zk>B&`>ADjgGDgR9?_YPHSwDAV`DB~jE5fOoIr+VB|K+oj7u9iTuIJwtdy@3M zhI>+M_hss`u4X-C?z88I7ORQZ>K_EhT;m*Zp0ZvI#QUHWZEZn;bo54_iFB>4ZINly`@#U+n#4zTc-i%IF?4x`WIXd|NN; z^(a<3zye#YKQ7=SUtskY@RTp0Qy0L33rPP3{N)SeHZI^bUmz;Hz~^7U>R;gVFJSdA z;6Y!YLU4iFzy)dp7qIsiu=f|JTV9|xaDm#u1?LW1(*^1Q7pPlapek?yOMd}Ne*sH> zfx6`d>XsL%4P2mZc>&+^0#$(v)GaSi6}Uh*+6C&C7pMwcAZvVqs=x*6mKUfBT%f{s zfpa75)F@S}lnm&%FCFbF63iUqspcLcC_q1x8u2g zTfR=$Sp;{Y$z@SFiVPn`hL0k{NBNwi*r%hss~nlsdbEzxc#*E{ETtgrX3Pi_0rjPp#T;+M|-4!I_qH$I7OWDp|&_3N+{W=v4_9MZ}$4F%$~v>-I7ts zraHSFr&#o=>xnYQ_+F>pnYFB6azn>lQ54h4s`#a}>R@d5H?m&mM}j}u_mFOS+Uf1o zp8IT5xE7?MdXIkb$Di_`?J5`he?m$5fxZOpf+1RdlF78!0 z;HuVx>pg!t9B|(+!2$RE91ghe8wcE<8wcD+|3f+8K5B?-3hIw)SKHOD)uq+0 zw6NM0K2+mNRKw&`?Sc<3-iE7dOsidG-Kt$>*{fmlsisGz+Laer?JDb54U|FW@H(}%#*EBcrdTLrd?N?sZ(%J z_*MJSCqMnbVQ-(Vxb@z6nH+GV<`;k0AVAlKZw|lso3_q>w#V}ZWnzO8a!Dr=_RzR= z4!F&09|~~5)&8P5;KG(8g5`){IU-n&2$my)<%nQ8B3O1j`X|WjP{PjtG_`;>vPFTgh;39CqMc{yozyTM511w$wOqV zIj|y)hKc?L2;Eg0!*k6 zc7PjEdu0e9rOoui9I#g<>*qS4!U31@DD(Sa0uH!h9d8%YX;~q!a#E}p<}^Be8l66k zPM=1nPm>cpjb@)F>vkIbK8=2#Mzc?o?>o(ZI8A=^H2QrS{XR{8^fX$28ZAGKmY+t; zPow3h(el&i_i6O|G@5;y{OD;k`!xB{)9CkUBu?K-3o2 zZj`gM{))OOpQm-7)kAWxAqy&c(Om~Zm68#Q2>);Mur^Ob*kalqAH#T;-GWbA@_re0^?Ah>ht^=xlpmUkQ6MOFE^3GiS7JScwuRQ;+GAVHx! zrz$@;0R~Kf0TWpI2{2#+4441|f_tXQ)=Yo_6ZFGOVB;sS@e|ni39S1BT^tisN+zh3 zOz;a$P$QY3MlwOpeS%Jy39gTwpgJ-E4o^@WnV>E*L2iA5Yo{k{1^IqMg#%7m&)jk8 zeuL^UhCKq3tlwa-@*@V@wed>U1DC`Bx9fm^Ih0qaea`UbDO2HJ;|pwt-U7v3!k-Sq z9$}F1N0C{=9vb3+I}zf5tIFqqYdF|bTsZzJH$ z2=&(y@@ON()g$;CBlsF4_!=W%%Lrb^2vNiczQzc?#t6Q~2)@P$c4GvOV+3Dg1Ycu> zHH_e8jL>&C0?v$pFeCUHBjC&kI5R>NF@mo#0>X?CMT~$mBjC&kI5R>;c7#}B1hg3e zZAQSE5pZS%oEhPo{1IxgBcRO)=Opa8XqWWmc6)f$Q0>vH#?YR-?3J{{JEm}bRFWZy z5Iz^rR;Z4VImXXc=$+YY#UV0QnPaYKwn8hrg8Xm77J*PX{BH*;{BNqvC+wjS@V`Zh z@V{LOyVgzidG{mN_w(6d9V)C1TFcA!@bhwydl@*rJuB(1uPgpBzBcHc*<=1ae9RTq z2CXdUZD5mWtH0^x?t~p?OT$;iBb#0)UWNZn(vq zOpJUO$vTYnI?Sh)BbEB!FWRHDRNlzvg{4yO%u40Ef&cA5a6S70kJ!nJA%iS$x%_Wm zGY{^E_7kZiU~|+I@3VEvgL}+uwHUu7U#bNq?4eQK6%;?}8^6V_qPY2o=DD4BrcOrJ z$>yGHwpX9(`=JwEKlkn8f6MZ}jlU!Qw^?*#mhUi&j?5yZv*^ey+A)i7Hw%u=;@iy< zH_qbW&Eo&e;@i#gE6(E8&Ek{K;?K?E&&}e`&Eg%+;?K?E&&}e`&5{+KC1RY#pPR*> zn3+|ILmJ_OK;sQ*HO&k$;}cs&f}TQ^H@ z-7L}LEOFy3apNrgbhG@T$EETZ-2M`cNsp)v!~CGJeMfKNO_rvG-Wt;&dK7EuITzf-$QoY=fiyo z`^#@~eV4ZX#kRMg=bq>DC>kE*xD8PKu?RLTf=Y{6?nO{(5$n4MHZ6imi{Q~BvF0Lp zv`Cb>2p%nhM~g(6i=fgXvF0M!vB-UIc%3K7Y7D1>*V$DSmY7vB51e+GYrbV!6k^I&o`K?6| zY7r~5NZ;=wIJHQAYmtuMMfl$q>HA%zb7&F%w?+8h7U6$eg#T?3{&!Qt%t3}HWXx1nP6CbnVD*SH&CVoh#jiEh?j13b*{BMFd;b9s4 zZwInGS$X_#aV5xdG4a~ve^Z7_{BMy0{BK7n;UcpnnphlKYb;eAMW9}?b&g!dugeb~}I z(lPRT^l`y4e&$B+%*M#?9{x8UtTXX)h5s!#hf|m@>-$Cd-;N^Jg|4d9ryeCjJ&G(J zm57xkv$xuD75+E*C8}GPUlQhjJCNajlPKr&za6OXze#=)_RuIS&-wgs#pU}L@_h`% zJ_c4F11FD>hdG9P9|NV2fzQYAK#t*i93#p(#yZOJ&{a3B@V`m!qjn}F_hJ4wPqgKe z?=C3$x?V58cc#MsmfzpHk^ik&hihqWsPcMTgI*ZP{{&u6xbx)}_Df?Y@Ny>5q6xg5 z3H`YAn1Z=;IFFd zPLL}o)CFUI%(G+V_PZ)G-EBz~uO?CKs@psD4}xQSZ%psZdShK~=$I>7N7KrxIG+Sj5|| ztvwJ8-`D)xR_)NWZ=0uIPFGK=+HtqZ&>?#$nviTK?4gn0@0#U*E7tLPaUGY`DHc!% ziu%`n)!)|t_QnY77(qTqIHq_Xiu66)jiS6`p*|E@!$N&1lA~}pimpTrx>0J`);Sp= zD;RX6DBn}48^w0BZarUG|Eqor{RX9VxmF(>9OLV<-kH_qLvF3T&Kz?^by+K`LZVob zKY71?t}g40dn3^0oxu+KW>w@-&3=2zne9U3^+oi#!vAJxGU1=iOR8R8=H09EYXz6i z|2Bt@JO>KQ;VI7{-*aHW9MV6BzdT27V-Bx*j;L@B-+2zJKZn(y17YSsXvg@ra3JA9F~5Ls=yp|%Q@eN zJ?E$j%u%?)A))plz=5mfPH$ znbjk>jcee=nOC07mY2QM=jUhK_0Fu!-pv{^$6QgrP%Cpe>soa%yp92_IY4h+h2jnE zxzjccy~F%)dgbva1?+I}Eam5Iid~l+-M!cNld|&sXC}`#+fVsE{_SRv=U!W>vfxewU-%g-uCtPXT z2{i2lQhvgfrkz03PPme`6RuGGge#mn0mH-zSO4LJtN(cdhKUod@<1nCMT93@$=(SV zCQi8G0zcs@19ZZzWxj)1>pbB~E>F11KAdpxVwTr&!d3Kh!d33)g!>U@aTA?zm4!dy zMw!)1b;8}t9AnhnQQK?`6J^xs|z%`7rZuGj}j| zGT+bqAagf!53@}mhn_uOQ(Mwc{TgBRI3bUBS02+8 z*gWMbt2G5ePl3==VDl8%JmsoiUDT_DVTt!!09OvdJ2S|a&=9` z6gWKv6VMbmJ>}N2{|@FlW+C*H`ypoG^pq={o&u+*!09P)ddd|}Pr198cQXsfroibb zS2#W8iV0{6CZH)-I6dVGr>8)mDG++fO|Yk#SvWlf6VMb)KvOUQO~C{-1ryMe`&%3% zw48GFyG*(IMW$T+7E`XUdCL6+vtphpn1H6-PqN+5tbV>Jn1H5W0-ACkW6x3M$C>qO zPQe5;1^3Mqd_Yt10ZqXNH0Ayt$2`gW`^2XDx3NS0(b!rXGaRI!JSa^P9?geAmvMtjDVcc6Zz9me(VVNZ3Q;TC^T{40AiGo#z@#G0a`Q zU0K1dtYBAGuq!Lrl@;vD3U*}$yRw2^S;4NXU{_YKD=XNQ73|6ic4Y;-vVvV%!LF=e zS5~kqE7+A4?8*vuWd*ykf?Zj`uB>2JR@_?q{a0Msl@(WZWd+ZF1-r6>|G$D=S;4NX zU{_YKD=XNQ73|82E4#Ad%C4+nS5~kqE7+A4?8*vuWd*ykf?Zj`uB>2JR$!Q0fnjb1 zyRw2^S;4NXU{_YKD=XNQ6&U7Luq!Lrl@;vD3U*}$yRrhq+zNJO1-r5W&)f<;b1T@D z73|82`xq;iU0DH7SKygj!LF=eS5~kqE7+A4?8*vuWd)wO6?o=W;F(*2VQvM6xfK}Z zR$SSY6?o=W;F(*2XKuxnU0H!=ZpD>dS%GbC1-7{rS9rSOewF!I=C3h-o%tKg-(>z4 z^S7D5!)#Moc1Y+TR48qSj_c!sV|+WLcV_L-Kft<|Ip&JmA+79sFixuu#((lRvUaF8 z_>+API|VjAykU>LA#doIF53+3P%e87M(2S~T)Hi?giod|ClkrU%;FS^WDe{O*XaM; zY*DQ(-1}ymA-^LpRJLfJ*`h9c=&TEO686vtYV`SiIbq(p$;)7!8|wQ`S-f-2Aayes z-3&T6gUihzax;kB3?es!$j#(pnnC1du(%m4ZU&2+!Qy6eG0h-yGg#aV7B_>%&17Vn zLF8t)*3LpRh};Y!H@kPTN1lE&h}`U|p4L24Hg5H@$gbp`!%oRlht*i=3W7#&*LZfu6jVvO(H~4b~5fqVmL;9~s z%k*DbOUbQ7_l+GB_?Wd>%`S59?EMG)6op@j(4A=BwBKO!Xtq3fY4(R~)vBRLvp;B$ zggrC@&3@)-#}N~Z$2K>0*_tdl^CF94oi{NwIff?3(Bv4J9K*wkq0cdLt1+}XhCav8 z=NNug46Tl#)iJa>Mus(pZpYB=7`h!pw`1sb4Bd{Q)iJa>hCat!=|c>Cj^Ss;@UvoQ zb9OQqd#k6hx%L|6 zEZS^iF`^ivg0f3Sd-oN)JH@X3A+9;yo#NfkHFxkT=9+6E>S_T2T8O$@z=0N`t`^Xs zg{Z3qOlScOT0nyq(4Yky-vTDIfCep~K?`Wm0uHo*11;b{3pmh1yww5%v|!y^(5V); z*5t4S1Zcsow}1mJ;6Muq(1KlW!LGNs4IKXw=0;}OuofyUEyP#$zs9mRLo}fJ)<4_h0h6F7>>-~)5}&Y#h8X6m zLkx3~e1^Flw>y`}F=y{6%rdvF0Lz?e1gZeu#(Ew_V%c=!AWR%=iGwO}@FWhN#PKoW zph_H6iGwF`@Fb3p5eHS`ph_H6iQ{9$!In6v5(ib{co%WJi#XU42V3HJ7jd`NmK4Xw zh=VP0P$iCc5qD)t<6ui1Y>5*y#EBW=#0+t=IB~Eg4z|R>mN?iFcZDr+vN&<_H*pXq zZogPQZfK8uXk~ak+|VBR(9zHy`O&H{l)@HChos_WdoCV_coDmQjE^mPXBJzoCYCv^ zEX*yJ zEtg9zmqDO-5d_Ml#{H;e!Vu^l`^C1h*3E!GzhWyD0%^SLJ%#$G0@kjoBHVI6cccVA z2f2RkT*tQZ>pwS(srd$GS;wE#4fu1U`RDdJUvmoESFKO$(&rS{0Z;nYZ7cyt?#++|*ok>za~GCsMJ?}$^b+ZB3u6D4-z$#oMYb`u|V zd7$#vt&b>qo(6CZZt&voO;b>qo(Q;+M$lk3KZ>&A!c#)s=BGVI2O>&A!cCNk{C zhwH|B>&AQQcJE|W^~}oqcH_f!qWzlkx4wd+Ww~>n57&rUutd4Xzs> zt{We&n<%jxPp%tJuA6#XH?d+jQDQeyVmDD@H#N9!ohr0f&!zA|Qlgl!G(LDSp?^%l znD7xlCiIWF%3?yDg>te{VNWh$?-GWDFWTUxvQZbMmov=CC6~)!&OS481!KhByF)SJ zUmNCho13zEFy}ElW5OJDRQ`=U6eB8Yk+6qGmM47X$LIdXy~Zkjud!0z>pW!leHMq? zS>tev^>z21y+iZ4A8$T(xqeWpAAIU3((DJH`iVFDL8*T5sUKwOC&ugtnfi$?`$49D zkg1;-vmbowCx6usO7(+M{Y0Ampj1CGW?| zAFS#pi`5TG^%H6K6KVE?RsCR9KaplXSk(_!^@CFVpj1C7)elPblhNu2rTWQe_0uoV z4_5VqRsF8er=Na-e)EZqI2ynrEMhFz{KPPr`g);*tX3_7^tRzlk!RUIuC3B@VrUlif{T~mgE z@?bVk1fc9w5CN>|^xBZ^Nod1{9|3H;cgv%FL0|3p9m;2kQ?9B2r`+4b1#jCg=s0f^ z7rc#}y-jrRHqpV`#075?vA*rx!jZQ!tHbqe&fnXt<8AE8+f*yxw!f9%xuRO3m1X?`UfA?Lf5X!Xd32Ka6JI>MXLmTl&F-@!c6+b9 zXg4e6)&jDBk2NdiOSy_u3@^_8fh_%|l5$COAmwlRXG}3y!rv||<;u)#WR!ao`F<1m zeiQkA6Nz~f`F<1meiQkA6Zw7<`F_)pe81^PzTYI?dlM=5RwIeiDCPU=JLu@rGOf?g z9OKKh-kFu@&BiEqr>#CC(?Nvn83e>!fwW0R*yidpg6lJt$=QY%7+jgD ztY2_Vres-}uJX`WYrQxcD}$3Sxq4?-a_=Ty&Kz?^(O4@B?!2LOd&4`cT62(FSGLg` z+M^1T$#R%iE<-D4pq$StmrE*_mFgn-$oMW{w}yw)e`-?w_@m96?c_K=9_ zOegH2QCO<;S>;Me`F2;Ixt)k-I}y)zqz!HYzlT+2j=7@Jua&v{GFo*oJoL=i+@4nb zX8NtXs>HjMTMmcIw9z|HfpydG>WyGe!JgLOl3Y`A>yFD@PL;U=SM?5iQJ|;Q6uOZA zb|7jOO8rN{nGNF|HL*gQ-g&Phc2qYwfYBvmirc3@61~0LvF3T z&Kz?^Ewolv^1N2Y_=%HHKLmi-pYGn_n zM>?)i%FmY!=(jKJ=gSAq9OI*i-kC*_0oI>6=8B?-R#t^1Yt_NHSd^>dgwNg(ihRsA zg(4w7IlU5w=sD{X*o$!Us=-YznOr6cR>wmj-(X*CkLMcrQGo7_JYc_zx9ZK%3!zM} z&_pB1$!qlq?Xa&hjlH zytl|!z6D;qMK=B|BC5AoOF5dM?{o3|kLOGJ+T&}6-kH^mtD8*@4_RDstXWd8Z)8$0 z>GivM_U!U#20Y6c*u|pPe(Vk3=Udl)eAG_I=80$j$j*Qy`5#RGwwUlKt2khfggrDa zogbj~m&z_PQG#1$B8ORK!gyu={^^gsV@{b4I|qRs?((`{ci=F~FZ!7LlTMiyhuQGIF++pvb8x#q}E zU2{IntO$M0xrccdv#j@;qkf(>Jkd2roHA=pocRFrN14^}z2>L~dd>MbbAq{<`4Dpp z^S#Vc(>3lCx5k~~*0@vL8h46Y<67)BeuXve5x3^_a(o~2L(E5*`AYslu-xUv{E#CtV#f7KB6)zJM_L-$t=QC|&FUk&kI4e?%$o8Y~&7&UZ% z)zJM_16xcDovJl-f7Q_aRYUhz4c%Wgbbr;*{Z&KXSB)!+QA5X94Qw$ru*KBC6H^0E zObtj`L*G}8`xwW|V${GBQv**-jVp^$15Zp1JTW!!#MHnOQv**-4LmV5@Wj->6I0{L zV${GEQv+K}4LmV5@Wj->6H^0EObt9SH88}~xL@X7f6V+R%+D}?mHAobuQ7j}`5VkO zf&Y3gWnrZC()Q98=9oSvIL5aydS}+c`~%!MnPaY~h0)5c2fMWDV0a#Su7#0gdn2$p z@^->|I(M=yIJAH_=_#Y-P`R7V?iB)6k@>7%xluleOx&Gg&oH@T6| zC{{Jo+A_!ZSfF=iv7iH+kvZmyVu4mx#hKKqgYjN}BkOJcdhjRv9-cJljC(_SqPA(8 zFJ;YomiDS>!W|FN4#*VH0uQnn+tdC7;YzvKp8nN-jm@LmciB0TZr^FE{+K;<9=F*e zVGoT!x1X`F=NxwTX1^(plF6dHYs==&6UeTvUMgVuUpG5nUXnzu`o&*DuSoNf%>_!r+ zp2VsrvFb@j7A#4_-X}HW;0ZoN?*?g7Tn-Jpz)fzhJNOBLv$OF0J7=%vJ8PKL!ikJXflL%F$AUzfhj|v$q;BVgm*Cn zrVN28LwFZMco#$bYD4_rAuweKzhVev83I{`K$anpWe8*$0$GMYmLV`@2)|+oWEmn} z7y?;_K$anL`$NPFLmK8w z=D?X>v2_Y(G+y?e(9eXw9WZNbE5iPA7`;CXJ{?B;52O8u(SgHYz+o`pFc@$cxjxLN zhjpm1HfViX*A2X*Sp4njihqo+4SHu*8#WvJi~3Vd(nHtAd9o?ijXk@(OX7|<%Ekp! zTI>q=SWuq#t)Z@fe|Pe~Y;!j9zqBBsEl6k!654`5 zQvT4K94}+B8M>boF9;Ruq9yF1aY?Y5cZndNQW*-lp-} zrpXFTJ9pT*o5pXOCL)~1dz;34o5pXO#*>)Fdz;2@nzX}Ik~4j!NK;;syM4ck5GH1;YZM5c~R;YEMG49OMo&( z?_9HckKbhJp^WZaQ{jGjZtb}ntJa@8a`yE3k>?Ws%kGS-2=On!t@-4$J~!1bsJmOe z-9PAisBZ=)nsdfPqfT$J()^2UZ$ZyJZ~0L)+>@%@4zhW$X&zLX$8yhuO7rO0JlHf3 zD$RpO^Td?%;L$wMrvcQ_h1;^I+4wQ)}`( z4?@ioU(U1sc@S!z_0NM)^B~kbk>xztG*4tXPh>d{Ld~O5^W?1NL8y5UY94Hw2b<=> zrg{33=gD8qgHZEWnR(|B>k&@PJJQm5r;WLtSzh)$9YFK+i_Oz7Hc!9UJokf}r)zB9 z>EXyvF!wR5Yi!>6B=heut9NXk9;JDU{I#u7jt~Es9rrgE#YC+?9}^$5Jy}e=y18Gp z`f_q&AJTygVWMo0VPb~+g>Y32GPZG%hI0=MvlJR(evFuy19H2v!~zrUI2S+0wZH-+ z_7}0hhz(|UU)4@8pXL1q-JnZ1o=-Oz(~ZP+gEZYBO*a_R4aRhXG2Qq)-5^ajK2JAD z(+$#egEZa#Z|wb_QqhF6X>0ZZ1s};tO#e*!r7f(Y~j5o z>dnfzU8l7_UO>+Gh2{MFvigQUn zweupG{#SeayFG02M3f18)+o%GF;SEUrk_vfN22?Y<$h$XpHJ;4LhVPE`}zEGWL9g` z+Dgl8p}daXnU&eQ-Ow>tGn2qAQ!ks;0Hquq8n@65iO9Z2B)wkF~@~m^6u!lxrdCup6 zDK6gweBuD|J%D@-K34d8nW5as9!4^JxfT*?E{chPq!E%&$R zV}fJ+tcBj0mHT_>zs?+UMde;Ab2&d+buc{n%9Z=@H5E}iP;!qbXWfwu`AcERx9iL| z^v3M9(oi8JKd?9Kot!kuH-bWbx6M&A(m9gk?>C8gz#g`EGIa@i)(CpqF2?>+ykoUA zOGG(6t3juWWHab)5he$HEt2JMM~h;&psz()=p;H6?rV8J`;`R``dWmV;l392tOngJ zcd)&kxsF-hL6S^Cl1xF+Dklca{E{HTj@9Q>`}4$nbwv$ z#@B4UGppHMZs?dRs@Ymu6%waa2cw+WTW8-JvT^zx({(9tR@3cO={`6(CGxCX%oM$# zuIDkGiRnq|vU&PfciK6UuJ14zO8B~7Yp)ab&nWr84S3QO&CtAFN^|*RMLpp`d5YjnB{8GHjM0y_XHIe5N?lRG@5$-anVUM&u+-o9jFVt%yJr8;?YK-G)^DJ5Us{KSJDFpA9o9RuI(&$0m@>y)Q61LGs+?MzbBFi4Yt4aI8n(_l zR`2wNj)~c(r^BIsR+RK2dMuI$zo9kbt(s{rq{q=+fzkG&FEJKYm|vz&M%U>-KiS-O z-a5*D=tS4gefx*jXLjBx^tUPd%Q+`|_lh4}GV{v}KJg6tKZ9pHgM80`0yAjH4F2&9 zxr`aSqj`vpBLDnP0-ut-j$7 zO$^~klWhq{1PVFMfW0g?6Q4`|65xsW*bCvwzPt>j_}Jg=+%JD}5$=}<(d`G(?FZ5A z2Z?$gL|z|6s~<$GA4IDkM5`YpL-`__LKdNo`CyBwlGl=jCN93-w0kXDdU;Tv5N!%U0@a%Hq!+kQ0T{L_2ao!TGw-Rv~3JBg|566=!uscr5*O>Oz$y5pYT z@qX*G{NSIT`^fb%^^ELVckLcSC+)g|Df0rSobUIYyy5(|@?QPV8zvJs{-0g;e*>MG zx^DU89p*vaYrdkVUCQL?p(_ry+bqP@_Vqk#I_}!nvsvHpxNAR>&HC$ccp{FwH?b`# zKkiDlj+3W6?n>H@yF$d{u5ju&+z`j%hB)r(e;$V$;y7G@$6<nxFoxFL?i1$dme z>bP6W@pmw5oyT3t<#AV8hvV*D%o=cQW74Ec#fDN5*MRHr54mC#FkhSsm=cAWQ1lpU{u1XWbIcXRIIXM-O|*^7ki=+YV_(UKH-c#RK(ND( zs-iPds3%kt>h&J|;*+0!s^{2KpE>rq`=1&-_EZk~nO)a$K7XOT+I@hwJE7v|kN&~# z02Tw!bzdtn zz5Q+9`4Vhz`s?>@2(IYTtC1Vd^o{lX{nK0CG3%Re;~@07E5sNFo5#WCaaa8T<8b(l zgV5uy{@XY>Jq}Kf!{IXyPLG4o;~@07tC(*boF3;&?s0H>+^uE*9n5viLg;ZyD z2tDp5*x$@7oF0e6XB-ZnaX5U&;qV!U!)M(6Eshadj=TC@#$Ej) z_>9BhGwyzpV^sehhskFg4xe%E-8Sw%#{Q$sk2CAn9EY`L944P}n0&@z@)?K8XB;M< zahQC@Ve%P=$!8o6pK&;R#@(m*oX;_Tp7}pBo3mh_{{`kRGXD|tmzclI{Kw2+VYUej z*K?`pO*$=I_9L^$Kdm<~vKGK~^c^$D_*O#i%pNlbqfzFVD{3XQvg^?=tvVQtv!Olm9K0dBAz6~$0Qa-*vR*3LVVB=#Xl^e;2^Uz8fY2jjJ&M#mqnX>K zXZx|wZz}8YT|0NO9+yT`NZ3Q;TC^T{+;BT?be?M{#SM4)c4Y~>vV>h( z!mcb~SC+6VOW2hq?8*{$WeK~ogk4#}t}J0!mar>J*p(&h$`W>E3A?g{U0K4eEMZrc zuq#X0l_l)T5_V+?yRw8`S#oRb_g`{lSC(Aal_ghpWeK~ogk4#}t}J0!mar>J*p(&h z$`W>E$(3DM!mcb~SC+6VOW2hq?8*{$WeK~ogk4#}t}J0!mS6;5f*WoLyRw8`S;DR? zVON&0D@)jwCAi_1uq#X0l_l)T5_V+?yRw8`S;DR?VON%5h+D$0EMZrcuq#XMW2|3x zWeGf8f+21RyRw8`S;DR?VON&0D@)jwCG5%)c4Y~>vV>h(!mcb~SC(LiTY@2O35K{O z7~+<&D@(5I$`U+rORnt7k}Hd{@`mhC zmu&`iD7Sit(Rtt#mu`!4)0LU4VvBK09oVhTVGYj~iCe1He!I;R$;bGN@G@BAhWfs3eVI4f|M2{gM~U_2nJZS%I=pcZq&^5n9|WBb zg3AX%y^}ri^bdl_2VK>Z4}!=CLF9uV@<9;!AQ_p1c5d_azuf*C{YLt2 zbgqiCIc(>z{xLox=$%^JQ<*gTrO!_JH}`$M*B)lj5S zAGAlp9vXpW2VFNFYh1Crsg>f4^E6p<7HIMo+uo?jjc9Tsn%sycH=@ancvy|-b0fLc zMzp#SeQrdb8}YLm(dtIDx)H5zB*WT>Za1Rajp%kGy4{FwH=^5(Xmul6-H1Lny3&V6 z^tll~s}Vn|5v^{tb9T8Jt8=e&URqQA{oHXMy^6Wxnp~+<69~{m z)YSwIG!b<*fd)-PT}@y@6KK!`8Z?0hP1yJ*Frf)FXaWtIK!YZ5pa~pk0tcGFfhOXu zCJ>+r>)wP;HMzB{M+ne_U2g&hn!tf35TFUW-h^FmavL~O8N4PedJ~aWlN)7^;;kkk zttM(LO|EJzO~hDDR9Bi@)yR8yVwr3F9)Tqf1~5b>tXhrQeqCMFTU2I!~L~RSnQ` zi|$`L_v9crJBv)U{{DLgEsiO2Oz!SPaQx$+!+*;CTcPb|{GEp%{QaY!eu7-Ee3Kptb<`5nLE9PGOk-Z;JE!+nL=<05vgZ9aS4jTRgH zx~=3k)|1N~7X@LWU`rHKiGn9l@Fa?l5d~GEph^@xiGn9le2gfl5(QPFph^@UBMP=e zL6s<|62-fS;$1|+mMGW~#k+{QwYIt_K1LL5iGnIoyo;zSOBw}RqF_sum?28c5G7`a zf-O<7B}y(Q3bsVSmMGW~C5sa!e-i~^qJr2w+|VBR(8}<7HB#-74=vov?vWpTFtev{ z9aYjHskqsmi^m~e#O@#Cdo_Az)~h+h_sx7xj!x(cT*tT2f5?tpJ&;TmJSIo>uPbs) zuDokK*OB+~?o}TAH?T!yZ#J^nB7FCTq7IFFy_Ys?&nN8Jutj(wZ1FZbKKt1d(VXqw z{`P%e_zW$9<#5U6QpsfyC|(4CGO2MtYMC$uy2sAvR@S;15J)w8A&|z)-V=5Egufkd z$z4~3OYS8{;`0)}(Myix;3dmEX;w_~5*f3X@VQ^28}KEh`6c_CC!u;SRVC8;w64!&YxX9p;kLE8Dv#mq;!vqvnAZvXZg=;j56(n2c`QR5Geg zpg=}nv~3OTOK8JJRz^26$^8uZ{2B83GvxDU$mh?H&z~VzKSMr$#%D=lG)l>&{W}K1~NcTnF)C z2i{u;-dhKixDIM?9n|1D@Zmb};W~&CJMiQ>@Z>u1OFD=ZJBSiHh!Q)95<95D>5d}h z*(^zkq@y%G?9s;s$N2c5cV_Y75xzy{m@DeHX=UCWyS3_Il#`7LdvXbTt1u*d(MI`n za)vp%WO5nnSBytBx_fshMih@~g-vdAvB~vj#F)L{Q!n|eUQntRl;Rm7KW-sw(FId$JR`rs_>IJ2Gi8OnOG<(6SUa+c{NV6BL>IJKML8)F)suz^%1*Lk) zX!U|py=1g{=@;k)t9rqzURRphOTR!b{Q|w*ORkrGfnM$<*UP=+dg&MFrBk?Zx9!}fd}^nalsqN*&9R$Zx9{4L0s?#5$hYyE%rOT;oQos4%at` z^51Y|1K*(f_6F6;H|%wJT5+2lw`PwU^aiI`pS+h#@Q?AeLhsCK#b)D>lSe0sFTf#} z-DgMa@m_h+ZdS^z1>`_fMm;y$H7QqdDo4u2l-O;Uvw3nclB6KcebcrzgdPcP*eJ{( zr_9Vo2D#Ue@7Iv;*O2emkeJty@7Iv;*O2emknh)!@7Iv;*Br_BYy9umIDfD4|0Qu6 zrI23VL2EB9)B60(F}_UeomrXQYz%UD+Uheh9Yn~UK|stENSj3G(#K_d*J6BI`vSUk zKVBB!)<;dEb*45)eM7&qBwF$#q_f2%Z3%nUD9pE|Dflx_5e_NW47vK;1-%h1RfDCe`t<&wx{rMk%dSK@j6I^yMcd{asF`|SKks;g|( z@3DtOOlLY_4~@c7ozEgyO3H6{^_jO5@!U?tb33ul?a0>cWMOV6|8hG~&h11ww-evo zPJDAa@y+e}n6ji_-$~!4G;T|yGROG1t#@Xn{~lJAIp&H=zgFh*%V^cX@X#|?`osQs zqa7&e53|W-$>a*if9@s9S^2lLd#;D#r#@>B?Dbn^d{h^|)UK+{)aj;-j^tmqNFJ6g z-chbDVGoU<(=ES;)#I63&fLqaSQl$)wyARaScBdd$!5^+qMUrt=^}qV+~Xo&E9i9j zRkr142c0hBmkN4ZR1q)U>7uT`px@;Vwzo6OM+o=3>|oE`%ni)K-X<~yg}Pqsk9pc$ zZcnRzGyPUxRiap|p%rG1@%3Bp%<6ZS8#?BS>bF)_h2&|~8aQ00joQvyw~Y~a!JbxW z@x^*t?U({Rtwkzt2cn9_HN3d{JErM3ZYoWeWJ=TTHpw~UYq}&lVGoT!(}SMYfJv@c zS8F+%Em`w0x)_&SlzK&!N=1}RVDX+4X?f6jA~^{6oJh;VJtwjmg*s2nl7}mW zd&&;kaZlONrTu*Qz?oxw6wy1gD6$#(mt z!20_12iE_jy>I5av5Tc%pC4KGjHAC;rYR1*gCWnVCt~k~#sn<6$ zsSnuXtgB~lg+ngX1DSYQ9CG{fION)ka>#APHf_Z=ZN)ZiC5N+>9L`p3(^hQLR&3K& zY}3}VFFy~ciMp_yCDua zq?br=ug@XJbLL{Ez|Xt3Ipp?VV$AYS00Tgw{m zVBXFwxg5k79CYPl4B`t8;sp-k1rFi`4wC5^#1|aI7aYV39Hb{?5MOW*UvLm#a1dW` z5MOW*UvLm#a1dW`5MOYRo{&L$LI&ZG7^E{~kS?}C`a=fk3>l;|WRT8~L6{^4VUif6 zGh~p?kU=^_)Gd(jUuuu^^Ll$!IOKFT!eisL550E4e;kLLhkoX{7U7WF>v0L?_3l>j8;+BUQ0sBv4$pZ(#se_EgGv+lVg>rYp$2iJc-x5J#? zv2#DZ-q_T|s6O5|bzSdz!0-0`KGlN?|K(677e3K9X?IrbeoF1chZw#Cs1EI%2=rN-8F>rc}4!$vPdd#i0HI5Opj}fzv zfzV?_>to>b7&tu!PLF}pW8m}{I6da>;uDm29s{Sx!09n?dW_z^F?#pL!09n?dJKdf z1EI(0+8YC>$H3_^aC!`!9s{Ar=-nFwp~v9*83UomKt_tEpE0<8#@xqP|54`0nLovRjQP{dzsvjt^JkcUkNHXF-)B~ueGIOj zF}Qxl;QASZ>t_tEpE0<8#^CxHgX?DuuAecue#YSX8FRnP=ln7ASD0-oE1MyHpbCea zqBxCkPE>pLX=3P@-?A-v%OMUq&kS5LZ;$u3pcWGN)J5;`EHDlE$v2u`6lpN*cS8#;&BXD{1UX z8oQFluB5RmY3xcGyOPGPq_Hb$>`EHDlE$v2u`6k}*7PckT}fkC(%6+Wb|sBnNn=;i z*p)PPC5>H4V^`AHl{8u4GH4V^`AHl{9uG zja^A&SJK#(GH4V^`AHl{9uGja^A&SJK#( zv@5%khC?n5hg=#CxilPdX*lH4aLA?MkW0fMmxeH4V^`AHl{9uG zja^A&SJK#(G?aL5&5D$eJS z`>*C@UJD#@#ro(v8OQoU3o+*!4ITJx-(* zr_vH9-ii}x#i_BxsjMC)ft9SwAxwFC{XTMi4 z)OjF8(ChMj1$81B@(4+MU%@sreK@uqZo^UcLWM)l`G}phggrFGA$LoNL+49V>Ey&4WLQ`c+vo#G~i=2fGQ23 zN&~3UfRE7twlsh$4WLQ`-bDl6MFZH<0Jb#XT{O70cCH%mF&e;@22iB|@1lYHO#|4{ z0Jby`Gcb1Iqf}?#uh`#Tw#TLSOX;22Sp40q(5BOUb0<_(gk^ zmPs!&@OkVvQa*{M#vX9Gtw`p*Ny!^EahaB;BLMO>ac^q=aA9ssgiE)`% zVT3v4zV?ndG5?hH6Tk+&t@#I?Zoq*!?ohWwc^9I5*fDQ!?ohWwGtV&;={G#y|v=KwYqoOxopLUYsH6a#fNLfhik=$ zYsH6a#fNJpK5WH%YsGtOr4rXl4X%|MTq{0YD?VH+QDQ5eTq~YjEA_ZmV#QXX#8#rj zR-(jKqQuq$-d^GBG}>(S6%M(;Zwq^J2|G6y6NWkDJQz_niv8iRFxcw_j)plE4mn4c z0O(9=s6*|X^{$#F$;+Qy2NGE>Nlql;k2_h%viBsV-2e%dNE)c7au0uCm!( zAXXPx)df~{fmK~#RTo*TE>NnANVAJbvkR>10;{@+G`qm6F0iT#lxQniVF1iM~ z+&;dSIOMwM8t8JxA=gFMKo?yDU33koMpmB3^q3v@H+FPskLf;rTyTulkZF2Eu8DsjQ9#09Ss7rcs`z3M1Bc$MhjRpNqIiCABCZehQ!b$QhhW6Z0d z)~n#vtB$Tlf7SU<%r@~^dM*`5=-RW3U$y38V>ph`JF{Bx?%|Njk!!`d#X00+lJGn! zzeYLal$qJcA@?%!{W9|XGV=X067w?h{W9|XGV=X0^8GUM{jwwZei`|GnLOspNVzgF z<;k?HcZEal4?gczJXAKx2(cu(!XbyWB_vKZ3bSqL>WN|;a$E5QgX=Se)!{2MmGuj* z$&@UYe`TgH{o-h>3{Jj}qIYJ|_}$4NhvX_klRW2f$nC9g$bpy%iH42BQoWHwuDF!n zhLqn%#B&=F&uzpyw~>pvjV#P<(h%DIgw=QiS-+lX&&Bfhz_)I*m> zF}&>{Ax+yEZuF_L?^8{FI8oFPB43pIxA*wMgad z+U1Zd*40{$W=mg#9H6=16XoHtOfXrNNjKqjzw&xy1==sb~rhkH)++2NiOS+hc& zC*mI}-gzSZF4TE)7yG5jUQ#=THA~s{`M>WDdDDeB(ASpbZbX4J2p-3EHRzwBaYWQ4?sxTW+H= z(1y?4hR@ta&9aTkKpUQO8$NRz)qpmt0d3SQ+o%S#QL}8L8qh{Hpp7~}8x?>y_f8YX zHtGOv)B)P41GG^GXrpG?M$NK~YCsz`%Qor&ZPWqUs9CmA2WX@3tc{vw8+Cv->Huxj z0otfmwowOYqgvTkwx55<#TH#38r0Y!11-6%ILag$e(RZsd>~y$FZg zE95L+A!qptIm=hbR=z?_=oLq~msiLiy+V)LE95L+A@+WSY~?F>4zJ)dyh1kq6;>mk zLgSrhL8Mkdt;@oI`E^UvL0@8$jO%(6j+GZ2(OhK+^`$v;j12055O=FK~d& z=>Y!U0QsH)yubmxzyZ9#0eV6P@C66(0tfH{2k-(1+**^u0ery$SCQZVzTg19;D9S1 zV*p=p055O=FK_@aaKKfj$K&H2z!x0A3ml*)WB^}q0AFwbUvL0lZ~$L$0AFwbUvL0l zZ~$L$fS!;6dO`-^kQksdWPmQV0s2D*=nNU4Gh~3ykO7z^24IpHpfhBE&X55*L&R>I zAGd0cYSXI0R5;{xHp1gdbI5t4bV zzbp>9>5?3B(;*JIX*lHm$~fe1{txAlyE()mHw+#RgU7?*@i6|+FsM9Cggy*54-=;k zgV4hu^f1^w3^otb!8c5VJ`6$+6Q>V@)5GBOFui-j;PfyEJq$t*6Ri(})5CP|4TICe zZms>&!{GEVG5atGJxsJd3{DS&)5GBOFgQI7P7j0A!|pCVLAmr{aC#V=9tNj}>D?Qq zcW)S+9tNj}LFi!+dYG=gVQ_jFoE`?Jhr#J#5PF#2yB$M_M73w1CWekF$RX#M0cA;ZFV4j_WG>a^ zRr}E=KmEYrpbOi3TTlxLeCi5^+_hvq@;T&ce}NowVY`yTuB5OlDeOuLyOP4Lq_8U~ z>`Dr|lESW}uq!F-N(#G@!mgySD=F+s3cHfRuB5OlDeOuLyOP4Lq_8U~>`Dr|lESW} zuq!FI)-)`IT}feAQrMLgb|r;fNnuw~*p(D^C52r{VOLVvl@wXv6m}(rT}feAQrMLg zb|r;fNnuw~*p(D^C52r{VOLVvl@xX*g`Dr| zlESW}uq!F-N(#G@!mgySD=F+s3cHfRuB5OlDeOuLyOP4Lq_8L{IOI}r$fe+rOSxa; z_xd{XH<-W4{4Hj2$fexxFxzD4>Wxyl!|&Q56%M(;4t>}^V_C~o7KdD5QZC&ViH#~K z<7KXgt#HVd=8!XP>-Vp_&#a$2vV5}5uFi3)W=?+Z+kg3NY38YKmc=302vRqK(T$*U zBe>iMA~%A_jUaL(h}=jnrV&JL1dAKN;zqEz5iD*b7t;tLH-g2DU~wZ@+(<^I5kziu zYfShgR32&vj&2>(J*q{H!{(x(=9*Z zh(k_@px5R53XOKORd|IYWpc>HDjagoN9?R6?4cnJxve1%x!>5pA@}}E=8$`T5e~WA z3vkG7Ey^KR55m-w(WxhwQ%@GB9v`C~AEO>0qaIYLCuXR}$Ee50sK>{s$H%D0$Ee50 zs0Ul>@hhUh>@h<9#9P05d>fKs9SM~T9^~4PIph`X7MLqeOdSZrpVupHR zhI+82o|vH?Y^euZ>cN(Ju%#YssRvu?$>P+Lzo`dd>I>k8Erf2S3WuD|#Kt;mlkKfS z#`Sj%u;r@Zkc(9~n}z4jzV&!sZPlH(WcQCcRw?2&)WCgqTmr0Hygx=nL9 zac^q=aA9suKG+ib~Q`bh z$tCdQ5_ob6;==^~TmnxnfhU)s9+$wAOW?yL@Zl2pa0x1L34FK&K3swfQ34+>f%lfc zdrOcZO5npK@Zl2pa0z_41U_5>A1;9pmmoe&;JqdA-V#*e64c-l)Zh~Ma0z_41W{rF zPcDHcm!KY(AXZEeB_@ax6GVv#qQpc2Z?AA?Lz_uLg+ngLMycb*8`_hwO^XS`9C99v zC>vDjlxio^Y$wue2dmn_s&*pHcCe})tZE0P+CiyyP^ul2YA2)B4obC?(Q2n(pdGAg z2dmoY5pJhnpq+k!b~=UI=@)2+L#`bTxpw*m+UXQ-r)!{{u7P&9k8dOnxpuk++ToCE zr)!{{u7P&C2HML;#K-Kjt_==3p_6^tl36n42D~9eyc`a>SaA-yeMTf#o5!xTf4A+^ z@a_USW%p;&oy9$NvaRl4JNJD4*cWj0f`t`%uJ!ldGiYsPMUKhcod}M9{BzV9bN^Oo z`x$>{Zr(tPN@FLOTi$n)65*@rqT<{{%<%^E4Mt{-K^*b**%89?o`FoLdyy)m^^cNjv#uXWq z7f0w@>D!c!BfMWJ97pJ#+1U2o!y%U=*NSs9^jlVm$}%O!j45%ym67wM{2JwuQ)Xr( zhurhX_w&g2^T_w}NX+xd_w&g2^T_w}$oKQe_w&g2^T_w}j{EB@1&a`IlRXa&9Hcxs~|lR^ppmiEnN#+e3e!t-Hb@Cx6_pT6;2`>6hVU zG5I&LnvK0O6%M)l9@cygxnfTwa9LeS|Ve?E#P z1)VP9kc*Ndh>|0SlFuyE=^_rfs9Vc?2eUE-QTI;fdgi;BcQ9}4ce#iClEiS=i|xSD z=()lnr_5rNqw^UIYRRUJdR=~>ihc{rNlJ?^*3$|tRiNv^l~b__hn#f=WmzJNceR$I z+0s`<5#o(gjZT^v=8&tWUQth_qMl4(@tzY!?Lp^>^gG;hqR$TZoX8Fq>O4_bTk*~l z>35;d6G>LM|HO7&rUnZoDjae_RYAz<4ei-$o1O++$9cwPqpYQRTq_)Mj;?h`cqj7G zs+X5}2dw-%%v?H$Tr<9LGZ@f}hujPjG=l`qR0Epvlbf;h&3MbrR0f*ynVa#Mo2gkg zQyFN+b8g0GZl)U0jHPeJ#y3+9Xr^Y_Of{gHYCtn}fM#lz%~Hy8|hwO|tQwM0K z4$w@^vYDD?Gu41*YL?B^0h*};G*h!|rVh|d-&r#?%Vz2T&C~&!sRJ}qt!$xxz?f_a#h%-Dr{2~wyBC7P8B(v zDr{2~wy6r+RE2G-`v2QI6Y!?0w2$AkP#8*;TC~)$q|g={3T+B)O4}$QlmJ=~D_~(z zWK~>1QBh~2gBh2MIvHgQE>Xv*Lqr{y(Q*AmP!tz7Wl>oa&`}f+8BrNP@}2j0bK9g% zOVRIh8FHT|w>PIJHz()5@BdxSd;ho97%q9u1c#g;wnWs*?~CD(LwczywnaGP_-h1h z4fhzA#;zdgYo>CiVrgW#R9`LisnyaBYJpH919>LN&wsUaq#Ea1^}0$))LiuvJUvmp z9O@;Tsj7e2_A}>@6YV-Uhg==LU>*8ahrZRJX?18?9hz2$rq!Wob!b{0USJ(wU>%v$ zI{d#n@;!BUfpvI+b$Eew+k~W@B-^hIciSp@CEBk-8mMytiu!9fb@+mH_=0u#f_3-kObyTs{Q6ExAWk?;BA$3%S)WIZC2a`k{l_7OhhSX6RQWpoC z)WEU#vIdjjkdxVn-J)w4#Q#V(iC!k5iP1epVq|N`S2g8esL;F6D@m(Xe+Bi7gw@Ci zSDZg%=4n%APMdP^DKjTenHhzCYQ?4*4mn$bLr$BdX40WvvK=~yoN@o>{}+ec{1!Rn z=Ercz&4)woHpL;=@kiy5>lni!=L3&@;IR)p_Tm5dKxH2hx({sj5vTh=Xdeje1Dkzd zvyTcs9}&6_g!U1q`@m@*IPIf$&j(KXKxiKb?IT+Efzv)J_`$82TuFIX&*T4GfB3@N3`w(r+whG51jTlO3D%IY}Lf-MD1J^gi`jQr!$lmh_M~|i>`Dl`62h*8 zuqz?#N(j3W!mfm{D|i>`Dl`62h*8uqz?#N(j3W z!mfm{D|i>`Dl`62h*8uqz?#N(j3W!mfm{D`NZ6>FaMiSyL+;Nizmua3sMK!%GV(j(g-U+M zru-z~DHH3Tt6mQElI_KU^ZLJ7keA%J{ze$57F=)C#|OU`hurn8;*hg|)D|$>0yY>g*q&u@XHcIOGf)9ve%Rs<}~-qppoceT}Z1 zE!5Z85*%`x%$!5LWP7ozD@9htqdDZtf5segg+yJ(6I+wjFEF0lDmj1S>8WR0beHI_nRtU^{-3c2I9kQl3w7^{#N ztB~lbkad+pqN~C<$dllZ6X`cLe1#u@L(Z1qkkcA-$aRk4kjrYqA(wf`9CDe>aL64S zheNJ&vmA0}5XMYK$4oBAOcuwCk735gFymvG@iENA3}$=`Gd_kHAHxi)m_ZdYK86`= zG2>mB@h;4G7iPQ*Gv0-n$ia+vVK(I`K{exJn28z8po$sq!c6|gOw3>=W-t>on86k^ zF@qUwF@r5;u*D3vn86k^*kUG&VdkeCPy+oXkYib=3GAa-#Rrzab8h z`vdgN@M@}!2GuJ`8>QYUuSW1fd>Z|*X2y&QOQMeZM2-htKJ60mbyRPjqcUvT^kEY& zk8T+_W6IR2S_c&oB{<|_>Zc5Tu9Rjtj@l=}UbC+}0 z_xZ2okV7_=NZS$|a@3PLxazX{uXD(y#Nm)zr3px{QivgY@q<@s;sLMHlH#Evh72REZ~7i6>WyCs&ClS4n(Wi9c6~Cs&ClSIK%@ zC7xU*K3pX}TqQnSB`a~2_;8i@aFt|;D)Hee@!l%&-YUruRpP@{;=@(q!&TzLRpP@{ z;=@(q!&MR=R^q)?;=NU}5?9F@TqSF8mH2R#_;8g(iIsSAm3VTMtjARnD^?OERuUyv z5+zm=C054q_TpDI3|1PG;E*%?wpdTjq2@+8Yq1=1I*f=v)(Q?eTY^LGFyoMOf>KWK z$w{Q?1fQJ5n@&*52|hVNCMPkb6J&A{T{=M~C&=U^#&m*DPV!eyP|68PIf*o#pp=ss z(+NsBK`EyxN6D`fta6ggc7j+=u*wNmIl(F?Smh*(6O?k2(Q;BR-~_9jV3m^^VJGzhPU;1mR0=z(7jVKM=Y&Jf zNxguRN?|8e15T<2oN&lFsTy!nHQhMH7NUbK zLY=#8$zBeJ?n~?8KNX#bW zdlT}#3HjcHd~ZU&H)$f@n~?8KttHAA;BRR#Ua-q#3IoN4mqUFA>yRA z_-tE`jh^2uhg=fApmBeuWO8Ef%#?hgaZjema_jHR6ih!j8cXh{F&fJ!8_@W_lS2;4 zl?YAbxePCMr)-uVwiq+@pDny53U5C$c5HYvKlr3^>$Fw)j%rltZq0 zDNjMlQ;2v{hzP4A^(y>l#@b~lR|uxLVS}#e3K$WLpJ4aOI5J)o8-5& zoYNGIs_zrYY04)Xq`!z!)%S_wCYGTjGafld!xqg)ELqyPeWEysC5IcYPt&y~8JUSI z)9`JEoXMCC4?Wf&FIJsZh9Z_jP8ad!*)Yf{6S;E-!v!`hfbuDL4KgE39Du8!5H zeG%C->RqBMUBsV{t#Oe^t&mJ+A^CzrG|8xR5e~URas-9s2nxw(#;bG@4!J^84*PEG zyR*+@pU?hy_66*l*1HtZE|M5q^`aUYX>)69S|tlttF%vFl_;7xRZhj$pt~kbMp)k` zqTlk#hCahhF@1hg{g#n6<&d)}ZIoZppx;d+@VGUt#x1$Z$f;sE7K%mTRkMC9tHbI| zoSN1IhukbJhC{Bos@B$Mw#Zt`b**OBE6l7^n8^e-UvnZ_Zd9I#9K_a~NYox%b0Rh) zUge2YwKZRPBKjS#@`Utsi!Xs~>;L4%#99QD4w&rhns zGO{F1Ffw}6uYR-!$69FVE6AyDV#TFaP1$T+JL_v)c`GU$SDi(hFPeEtz2P?QgDh>7 zS*Yh0vBq+XT%-KfIm%%X8Tw`1d*W2%T&rGVl@tk&m>RrhRWFBn$#zJqm*4XVSdBU4 zt{=VN`d*_SYOl?9jDA;TCB(zjGhXBQYaoFdZe**%H?9H$s_>AjK!Pfepo-OiD*WUs z)XmaAA9sKPs~!e_3+(pO>WtMHtw@R_Sv4XDD>S7GC;SPiIR&9aKsfGSo4s!Sre zRjdG1VHc}d2dFajpj~9Nigkc0)-0=7v#eq@po%riD%Jt2SO=(L&9aJhfGX(6w5DvM`MADnVrOo6lH%L?pN{-mq*lhgIpF>V0 zRi-7Tswav=t~|jZ7gGbNbI6r7;*cBEEQj1aBzPYZybsT7A9B18Io^jH??aCF@jd&H z<9)4`RI!o!)hi-}&BSsYIA5%!$|oB59*}WjNmuTG!PJ6*=FF5T5r@i2` z7o7H*BwOMoTK9s}UU1qAPJ5}{^HRI#1*g5>v=@Z-g3w;7_PpS<7o7Hj(_V1e3qpIT z-SdLbUbud|AhZ{R_JYt}5ZVhid#T#&FY%j~A{VFI+!fxPH8F{dnQ}@xt}v zh3m%)*N+#jA1_=#Ubud|aL9RK{PDse=Z#}+;#XQHIONoYQyzVi{ArXEl@^=q*rd-% z>PWoh7!Enz3`mCKkT~S@j~QzrM(#AhA=i2ixnI8ZXv`ru`~Q$bF4nFDu`5CBN)Wpe z#I6LfD?#i^5W5n@t^~0wLF`HpyAs5%1hFeY>`D;362z_qu`5CBN)Wpe#I6LfD?#i^ z5W5n@t^~0wLF`J`D;362z_qu`5CBN)Wpe#I6LfD?#i^5W5n@t^~0wLF`HpyAs5%1hFeY>`D-e5`;r8 z2!~t{4!Iy4azQxcf~M;jt(W~D+26qaM)qn)zC`}ElvTe;{XfAWXV{@$GF@y&ORG5K z43l!`wn(k-)u(qFo)OTf4&GSDtLUTt!KObW;Be)TyZ3u>$X(Ye4!K;AIv0%21)X!j zKf0G5aWPvSN#0*))3|YhsSzt>R*pdad zWPvSNU`rO*l0_CLi~LO%2$K~DH{`-eosm?%idQY3na;yp64N3p%T@I)@iXMYw|0*D z4!s(rxw?NnVvqER#3Ay@hB(B@@2x-2Pa22B=a3VaS7__^9O!y$Jl99?q%;>Mo2&6x{!E?!s`Xxsbass+ZWRzUt*rFWFjm7lz`G>!^6-zUN&Su^e)L zR`+1kjy`?#5>4*G7%}==ZOrITwZ~L`NUAc8{7@%#EH5pl;-eG~u9PfMDSlijxuQ~X zMWy(0rTB5B_;IE9aiv6urFe6t_;IE9aiy%rmEy;h;=z^T!Ik2{m9h?3iU(JU2Ukjd zs1y&b6yL2B->uY?r^Z=|2Um&*SBeK$iU(I}>dAk_>nX*9D<$7sitkp6?^en>Tq!GX zrL4e};=z^T!Icstmg2{i;>VQ|DV7o=ma+m@%Gz5gF=8oT(i&V4=@6-C*;eVEO{}ew zPd3=9Gx!zt=lMx(m5eM28CM7On=V%dE=Y6JyS!pOIEU(^>{%>#oDLt7g=z(NTzP^! z?l9wyvx84|kjYMjX$P6?#F=*R$qq8v!6ZAer5#MN6II&5Bs-X7C$_YMOm^~CcJRp# zKG}&d?ckH0*wPL@*}*5fDM!h#9h9=0x^tY%KA(LL_L6tCgHm>~S9b8pPK0SE!nA`@ zcJ$j$glPw*?4Xn#e6oX2cJRp#KH0%1JDDsyC}jtw>}0a+pp>23U^{gJcIpJ|R0!Lt z6R^V_XNNn^PMv_A3Sm3d0(Pne>~P1~sTQzPEntT`&Q7&}ooWF))dKcbBjQ22aCG{#8D2Pi}oREw;n$<1pm+@>aLYAtZb$sMi*HI@T4~2TW!F1 z-JnTEe1m%FR$TtJ6hCy9|EpKaeuD0=#rg^I$p$~+zlS?6O0FfoZGk(^)`+j+@a2w^ zj7(GRxOK?)I^=sD^1Tj;S%-YDL%!D`-|LX?b;$QR;kIz*B)H>bjY(<@ls_KJ9jA+UbMmi9 zYMR!rCb;7c#vRvO_3FVGrdn6OYSg@lpKR2*NR?(jnSyw=EfT326)uvC&L>k~RJaIt zTs}F1d~yW&WHRGbxCnQgQRmW)W62ccoATI8rogCkkxW6nIv2U4IG=oGY_*GO#*34` zdSubsT2{%z9Uk0q1W^aO0WrMpqBbF^0} z0ErTR8EjLMW0!S~o+{HLyk(NV5Q%oEmu$w9&W-0G>+FzPNpsb#thtawX=SioVP92wkEjaG^?6KM`R`sY1Q(3 zKKbg0bH|mL6cA};U_cpb0%agU8AwpZYCsvQm1S7^GFB_gSQ#i|wX%$rfihMr%UBsG zV`ZR>HGwi#1In=UW!U&KRs+gdtt?|Tpp4akGLv9o8LO3LSobnkE6Z4|EMv8@jCFuA zRx8V>zba!jpbYC?#yUV5>i}h}R+h02P)5C38LO3LtOJy>4p7EAKpA%pmaz^{MlEZZ zOi3eLiC;_RRQ(d%aR!PAKI@yb*wvx({A0M|%H^G4$U&0wDlkrP$B`>^L}s)pcih~A zaL27D>RpeeUr+42p4fLivG00f-}U5=))N7*Cug~yY~_05;PrS8>+u=Z<7cgBG~!dp z_QSLB`f5%~+4!G7cbrJ7%tlN#PZW1tzXW$2^5u|8Qk%{lSK5d>uDV(7xZOzbZX|d& zsJt6F-i;jZMviwQ$GiES-N^B7zNJ^c~iBtKc?Bvt>^MvBpLdqu_`uult z$05CN$MuVF$MM$)+8XXHKCHRpN`L0uaiU!Z=Z>qv7p%b-ticzop+2OB%8(koz#6>3 z8oa<7yucc~z#6>38tOx8@c(Ma_tfA8*5C!!;04x@@2SBTticPc!3(Ux3#>8aD6Oi& z7u4_ctuf`%BAK2VllT}l_<}Wffi-x6HF$wF)P&UF3)bKZ*5C!!P!m#vFIa;wSc5NE zgD+TvFIa;wSc5NEgD+TvFIYoONDVb1HPo-wP#IFgJx(>$htyCRQbT1(4V57^Fi6zE zAW=hQNDY-CHB^Sw#PKiH&%)lz8cc#aPG%!^`>DC(bo5i6Yct$&{Sw@9+9Y+!9Ffa* z=-hF}eV_kd+;O26x#L1H+;Jhe>*C~fY2Tg+5d>$fn4+!lcPWOP*9&p-2?Vbmm_JGhH5ZXhu?g6JgRPcGg zX^$yKU1<+E?IC9O5UqQN);-{~2b}hR(;jfz15SIuX^%;=B_5)64>;`sr#;}bhuS?4 zwR;|L+5=8|KxhvL?V)PV15SIuX%9H<0jE76w1?U~4+!mn_rbeaQt}S`0>E;P96ug7emrpec;NW)!13dOvt^}|v0qjZuyAr^z1h6Xs>`DN;62Ptmuqy%V zN&veOz^(+aD*^0E0J{>vt^}|v0qjZuyAr^z1h6Xs>`DN;5-{bc@dmIf0qjZuyAr^z z1h6Xs>`DN;62Ptmuqy%VN&veOz^(+aD*^0E0J{>vt^}|v0qjZuyAr^z1h6Xs>`DN; z62Ptmuqy%VN&veOz^(+aD*^0E0J{>vt^}|v0qjZuyAr^z1h6Xs>`DN;62Ptmuqy%V zN&veOz^(*LVpjri#|7Yy3t(3Q*p&cwC4gNCU{?azl>l}nfL#e-R|43T0CpvST?t@U z0@#%Rb|rva31C+O*p&cwC4gNCU{L}lu@M2d;{tHU1>lYgz#SKWJ1$`I(nq-C0;U_- z-^gC=$d}09mU4$TssAUq;|x30OQws>XsI+BuvNp=JHrks3u3I-87Ae>ZIQ50HFkH<81Ia z8$8YikF&|dWP``qAaOQ1m~4spJHh7#39%sk#KU-U8BiBZ*NqhCTdCs_Q{5R4ka-X_< zvLQFC=acHs^ON5DCnHNj!Wg#N2@gy^rFHWDkn3zjTMtraBj+}J%LHd!gGL*5HloQ| zNptmc2iIYdGs6>$Ut^Pw4yU8T>F97eI-HJYm5wH-lT%GcpVQIgbTl~~|0*4QPDh{9 z@vPF(>U6X^9j#7BtJCqa($VU4v^pJqPDh{9@vPF(=X8@~R@2evbo4nL|0?|lXskp{ z3C=jfQp;@Uo3xawLuILTZLGJ`yltVbreA_Hj+t{rW-=aUT-ncEHe?7nY9%&Yb$1AD>JJq zX702#6I+>yt<1z$W}+%H>nUcUDsvpHj#K%ZEHxUrA4Mv7#p}?w3=k%ROil(loD8xz8Tc3( z_!t@Z7#a8&8AJ;i_!t@Z7#a8&8Tc3(_!t@Z7#Uzo2Hr&m-bDu9MF!qQ2Hr&mF+&F4 zMTRLy4JiX3BZFum160YtyT~9~$N*b1z?KZMHyL0{2GK$W*pdOZWPmLhU`qzrk^#14 zkiE$uZ<7JSWW>P@nVTck>p1liuUb5_1ZSMgfk;j=`K}~nT-syM#`Q~Z#%X=ktT<$n)YiJYFBD%~N5vcWJ@3AV=8W@={vn)kMR;&UWQmIK zn=8VPE5eT}Vim3kKduN5t_TmV2oJ7^tZxw> zToE2z5&5AaJh&o!w<3JEB9p|0MR;&UcyL8{a7B1aC%5guF-9$XPIViA5^5q?||kzx@sVi7BEMXb3M5hE7G@$%wVGDtyof-}y@ zLdo5#`X((7btu>ob7O`MACiS?1!r8p1ZUh~#u;Y=pKKtLjR?~QGTDeTZQzp)WU_%t zHeyQ~m}DcWw1G)BFv&)2X#<&T zIG4TD2irg?8z^N1rEFxcY~YiP2-8M{X#=Hfpp=aW(*{b}Kq(veWCNdU;FAq}vVl)F zGFdiI$_7f=$Yj|-DH}DxHtGXx)Cbt847O1pV1qNx24|d&`T!f1!8WP{Y*Y!@;Ec0T zC19gUzy@cWjVb{fRRT7u1Z=HF#Iw}w93Gr;f==qks))nDKk=6I&1jLFKtoH3I#h^w zNStx~THuT;uSjsl$(r~h1(L@S&ban*IOEn553E%dN!H&b9#~71xR$73Em6T*;(@h9 zs%y25^pU%6)@qUqU#m$i)LKo}-qvbT=d_l(16j>)UHl-qw1cx0$+y(Uy^-~0`D8;( z``^PE7bVvc-?qRRSJAJDl-nXi)Hyms!~LojL|8KP`Rio5TPuoMd1q3a+2usqizch` z%4YgRH#>~}6E9{JJ^Fv~j%P<2qwgw^CS8*Be+uuKY=RyRIZ#_9zU^9_GJdpC`61FB zk27vH^1T}QUX6UOMq*YY->Z@D)yVg19bUX6UO=DSxjf2;X^kvQ2}%G1bi zNN~nQamF%a$)jBj5 zOg}gpAFiBnNUlU^BF~LDW_}M?y$6)ugYDRZ|FMTPx;>iQaj9F8*5LLrs&|4jPCWEtH51Ao zkL8ThMZ7ur7q+P;HLJ~X#`W!+qi?#O@<-*T6eu@TswtGW@(b`&Bw`USx1aK^MyQwg z(2}cjsF!Tb)vW4_QU|MAJs7W4>*`jGiWiZ6qsm2UG|l7*;#IbYr)AW)h&OL0PY|!N zMb^R1WC-Hbw+LgLQRUK&W62PhO)^7fG6eCeT%>N*sB$UdSme;Cby0_SZ}M07zFJ$u zD%VP`QKUX~Vtjr98DV{&NQ@z$l-bkQ&4!bct?v`%Nvo5q^<1@Uv_*T*A|Y}6M0v~- zgT?C;?Ip{2lF6MUA#ui6vUaSrP~Nu`dH>q@fa;Z`9k1RgO&9GwSPd)mQ-+QkcSt3; z;*1(rgDbAND%RHMv|L+>9;CV?ejRHDD-;>5O=OS(Y`(@sqIILvL^M0L#zgcxw#G#4 zU%W~asbXus(xf~8743Sk%rbm!dwwCfTA_EDoI0HolpY=^z;&H|GYc*F~ zzXVqt8taJ6Xj85@|3SFo))4Kk0hiVg^R6N0T|>;fhM0E^d80K%zH7);t|8`LL;Sl2 z&tVOiyoN|>4Wns|X0$E~FFr)eS@@qnSDZ+y{0iMemS3d2-zcuQiUe0&OwFUt71y^B zSKPp6x#D&p!8?%P9e8^?kmDW5@ebs82XefF@7aMI?~qH<$Ty5%S0ee$1Xr9Ow%A-H zyU45I_94Ag5m!XG;`nO>ZHLSi_b27&bx=X6LU3h^myg(PVATE4C7ha$XFVKY-=rZM~Id$O+x=h_U7P)lc3%X3=W4Q1I zU3h^myg(OTpvxpV9v8l#3t!NM7wDoE#Dy>D!WVSm3%c+HUHF17d_fn!pbKBng)iu$ z7Q{s@h>N;47Zo8c?rm~W7viEK#6?Aji;55zj1evvBV1I3xTpwmQ4!*b<6o+QWAA0{ zCBYRZvk|*B%~y$DCZUPZJw;+hw68&q}^p}WCmH*vZfgm#0_Zm`)6HoK|Z za}%MvL1;H|x*ME!gVSzm_T1pK8-#X)&~Bo2H#qI4a?cG;yG=Q2jBaq+O%~e?Lc599 z-QctvoOXlLZgAQSPP@Trw@I=kZlZNJIPC_f-QcvFnmso)dv0*r4Nkj3Xg3J$HaR%M z0QOGy1KEpCyFq9-HG6Il+6||V8-#X)&~6ag4MMxYW;fM(Za971RO`8^)^o$@A2*ynZa971aQe96^l`)Kf^Cy zRyE`|*7u35YRD(ssF%K~@dVsP^?iQQRSg+gTaZZ|)NgtoEZR!MRu4+Y*qo@e*ks2h zcH<;L_^~T~?1~?|;>WJ|u`7P;iXXe;$FBIXD}L;XAG_kmuK2Mle(Z`L zyW+>L_^~T~?1~?|;>WJ|u`7O4j?ybXcEyif@ncu~*cCr^#gAR_V^{px6+d>xk6rO& zSNzx&KX%2BUGZaA{MZ#gcEyif@ncu~*cCr^#gAR_xk6rO&SNzx&KX%2BUGZaA{MZ#gcEyif@xvA82T%QQ#rd%- ze(Z`LyW+>L_^~T~?1~?|;>WJ|u`7P;iXXe;$FBIXD}L;XAG_kmuK2Mle(Z`LyW+>L z_^~K{li;Zzt~ftjaelbs{BXtj;fnLa73VhzSDYWNIKSyej@7PJ8JU|@zXVsD5v??h zUs}Z#XPA^jw?)D}Wh~=0@*#dXbvNRLN`6P~yBMxsYVcaF zdO6ffw&vw~=ck*QVuqo9?PteV>SDDxYldO!cP^)c5&GJyRK3 z5|SpPmQCtyDwOugaYOz>Un9}mL^gH43l3DT`g$AD+Jn^F$hi$4vo)M?#`B1E&Avrx z_Lu4!{Bkr~a)qMVd1};l^^(~Wwj_so$!2J_QE#Jj#(iHs7AZ5<*W*{(q@u^E=y57~ zoQfW&;$Nkr&8cKoQ_<#Bv^f=RPQ}Yg#lK2Lr&H1CRPw8-Xm%=^or-3s;$@|x*{SGs zDmtBN%2DG?MVnL6=2Wyf6)!6lolaGA)!0(ER#RopWv*M+)NJ_zqfbOr<&zDX>R`8F?+FHS*);R5ocu)VP&zllEvCe z7O_aK(xA8yh~tkH8gIk>HBcMB*Kh zi5IT8oEWaSW14Wqbv|USxX#UR#bw6fipx=J1M#`y(m>rguSg?rlSZtNMy!xVtdK^mkVdSKM)oERY)J!K(!iE9uq6#_Nh5oc zM&2e3gh`8o8*<^qcb3eqc+=vOCAi{b4#dl9jw?>|UhiY%ANt5!HlwB5Xi#TL(nhIw z%BvB)5T8arteG+6!jh=tK9S==mrvtav8wmT2@}tsGHlxPVG}MF@5g8vIAhAxsagjW z2_?AVV(O+09BUPqRTyYf%t~jl)njnWvlG<8#_l4q#>!|qRzUSQ+ z(Ohvi{UENm0z9|^@X> zk1N1~E5L&*z=JCwGgN>FSAYjsKxU`_53T^;tpMMxz?7$EvH%aR01vJJ53T?Yt^g0N z01vJJ53YbbZvnnr0lr%S>u&|DycMwWR)7arfCpDVj97plSAZW^K%`hej99?RTLEis z1;mI2alE|vl?*O5?gUqy;jhJda1J#$%1Mjmiqqjk{IFJV#Z@G@;tn&eI4k&M1(~cw zm{yRcDZ>I1CQ2Uw{Lwo)Hpg)7bqSDcml z04tTjR;mQ7R0&w&inCHBV5LgH3Rj$!Dgi510#>R7tgS}Gv(!u-9$ayPPU^?1h{M3Y zrYmT%)m|m4w?f22;)<(io-3}T#MXpGt6waO);zVAHd$S}PBPG61Up4%HBMPelTG-1 zWRn#Tha9LaK8u#*v4kt`S8=%FRuT`aRNkzntt1{;NtC#fs9+^g!AjzRl|-s5wT|?Z z`*l`ok_%tS{Hb=ucqOZoE7ei!;s^Ov@@ra-Y4xiV=@W@*<&zCD?SBtfT$Ef( zeA_%%TuI+X6(Kn}w!@SwPBJp{=l2;cPjdy3m27C*a*mfH-^-EjE;94G!0KI~^e()RUHBinH1Q60X>!NqE=JTE z=|4vGOmM}C&n`6v${&yAiql2BIr*2H_nOqKHp>-PT9Tu04P0?n<%a%pD%&KZBi?wW zayNvHSA6Jv^>V0}Y(`~UgxMb4Og}tnVXOYQ_SK(sjzd7u?vG2}4kG;%Pmg#u*1?-#FxfIbZl9)xl zz^Han4R~?#_s}@wDqsS|m+kh~^pN(paZRV}&A(JYe&cCZgkqQfVSq@L=^OQpIM}n}~L& znMAwOOrjUD^(La@M%9Tr{GOUC*FfgJWz7}LsqYifT=`^!<~qq>*7x~IHCINKq~)l6 z^rm0;Xw8kylu2JfOnnnuU8)Y1t=6@&zNVG8VyjhgD|H@ntQz%W<-#Vo;xwz8Ifp)x zhqhYzJ)dm#!@1%tCZzH9WN9c&mXj87ZTMxn& zw}NPQg}M@&wt|><1u^dmV%`0Ku>$30?8`Nj&<7VN1{#Ta!) zvc8R1mC7r`@0CsWZm(3{?JN}}>HIc7N6vHk?UEHSwh<~>DBf-3O}s5*yZMMWwDCvJ zF+JAtH%SY&=O(ZC`}XAgA^&WX{M40gANy=j%FNAa?dJYvO}n%A+||Ck{p4Sbd7)>A z?j3e@*tz}b)UM;)9WzD@NGn^^_K2@SZyd2;|4m08@$4y`CcTrM-oJWPdU49FN4?T% zWX7%IGCDiAyxn=$oqs-hJgfSOomqvi&pWn5r!#*2 z-q53tyJPxm$Bnz}itK)86m~r=YeUx!58P-z@;?~tmfH! ztZTI^N`~C=ZOLD%FX{97cVG0mdEwc8Ke+ybz5`A@?qZeejiP_sNb|>R`heu?OCyP^B*d+<5t`=@y- zx4!&N$SoKE}P)z{eHPk+^Z`nO3ZJnA{|ggH-KcEXCQ zA3b5nt}Q2g`(5V~cmA#V#4(>8uirSL|4IKY?tkE+;r&1Q z_qqMIynappeT8@RAM)!b`v1rOO8>EeRsG-Uxw-$6f!q6U`q%FMi#qM=-+S?a{z?WM z@>kwVyZm4JNq_mAd|u8Y=aciw`Q>}$`{aA&`(+$59vPR6PsS4f1 zPktxASN(4J{W1^Chng4WN6nMWm&}{YpUk7or_8I&ugtT|x6HfDzg!2o9&%me`p9*X z>m}DsuAf{-xt?-e<@(BXmg_CoU9P{#fyjf%g~*4S zoyecap~$1irO2nqsmQCyt;ny)vByjp&c) zk?51?mFSn~ndqD7o#>zFq3EONrRb;VspzZdt>~}lvFNktwdl9#x#+v-y=)imvW0`6 zUvS{muO9f$nXzGiNo~gd_0OEN@4J&ddrv*)`TzL3{(H~4=l9%mN4rVizVU6~n^5(d zuRr+uh_BN#hVI^S{~x~E@z{cYzjfl?U1@c;UC!i-zx?;$$9LY{`-?9Yz0m86xBqkA zjuUo1y#4(9w{KgJU9|0nDHnd8>v{6C6~Fy<>x$9#tz)u1pWe0R^-uoix=x?0DIfE% zZ+71Ialz9&K05oBijN-fUbp4-`&MuM`zN`Z^L}&5rd=toeYpI~E+0-YU+_WQ9WQU} zHzjN1pZ<8!hUFdKT0iyc{Pj-_^{h+jwCVkOhWCH}(bRk28#65Fy{EILzWc_kx7K>k z?X!0M-aFUa*1PSRKeWGS_2^qZSoPGhVXOMSvf!Q3mzBJ8^UlA$?JPO&?H2~zy0W6j z5i7TT^v4yOf8TCJ&+v82pPkx%`2{cBxa^pu^koG4P2dUHp`TaWgA z(wjFPHru^ZJS^qiqjXn=Q^?K;45wAaa*%wQ)@ANIX?KA6=1=H5N)}^ca zwJsgAJAue=-*49GkkZ z|IRiGS5=u7s>{z`c`xnqf9WUv<#Y0RIggxA&MW7a?~(75@0IVDamaXNTrxfxr;Jy| zE#sHpA-_j{m;65Yo%~+)yXE)GJTM<>UYH*>PcmOJZ!&)}k20S!uQIk0O^MpCYFsuOhc1zaqyX&mz|%-y-KC?;`gi|Dp$?526>M zAEGCsFQPZ1KcYvXPoh_%U!rHCZ=!dif1-z?kD`~NpQ5LtucEi2zoN&Y&!X3&-=gQD z@1pmj{|Wnlc-wy^0`>0Tfp8d^5V=r?953v@u>Z&kXa6zXUOUmd{p1sO{dv_1Uu$Qa zaB|sJ`|j?S+U*OI?aw9OTIKpUzsfY`xym79hF3nf;p2*4>)jPk*Bn!EpXG^uGtV8? zZ)3Y{>PY zTSuzm$&S|hPg-1@clMRV?~W`l&h7N?qHFwrFS>E_w4(K2_9!Y^_;K%HHTU;Edd|e& zm-@Q*KL5mzdUg2g1HCT#`_x`5r&@ZQ^ZNEe?~2C@|8&Krg!EKGhxE4;LLNzY{` z`+ENUz^I-t59-?UwXUC9uDbql%L`Zj*7BQhwWYd4C(E?E))&0?WT;@m@JkAYojai5 zzP3jeT-$Zy@wrbveEdHa{r32ahMaVKXwb38Kk&@wJzl!&g&t$Sx~a$d=g#c$k1wn} zM&F#=qx$Z(`AMB0%Fq7l%KRP`wfWC{+#~;@-TU(PPJKJ?yUI{r(Tpqe1|^NmGkw)F zFVB&bcg5ECbC-YqMDCtJH{`C|GcmU`$)4M8!qK^XI`8a$-?49WA9C^i-H*+_s(a_m zG2Q!~RodPC?UCKTUcar|!yRAm_K5d^ZfU1n-RW$CdG;ZUW|FUgdzOB>7|J?KWhNa)VvccN!?hWmqzjQ;Nqla&} zKC{P$4KIDSKHPE5`WL=?c>Oy!d)6nvTDLysj-vH{PHnS(=&#>jx9+vSuluN@XWfBq zqt^Y;M9aE|X6%1|c>0R>^IgIB=XJdJ{Q;Az-yb*R==aAw|F8G{{LDY!8-C)o?`^CZ z`QGm~cYp89yPXAxOlYiv_O0 zaJy&a8UL(W8Q%ZZito;Qc*XAyOjvQ<!Y6k&F@Bet}Y(+&Ww*oo{)Rz z$n$O=G4hzD?M5E)!b_)>O}zZHs~41<_RZ35wU6E~ulDWT6KZd7-?etwE9*`j(*5>R zzwAEx)E8gwd}>K})rie&{xagc>X9RUH{|FMOFvwDN^bi*PN{wAH>Z>(n@@S>?JdLK zEC>yso^t;1htDY)?jQE;upv*rIBdsl*9?2|KPL}cy*6XmUwUt-soMWQjd{TIn!ERw z*JK`_RI`8a(vx3&=eCpI8$Rje<>kdE_q=J}N$!(gKWW@W{*$JKC!RF;E9*)3pBx_A ztKIUUcjetZ^wImyA6hWmK6K>^9fw{va^sMlLmnNHe*5o-yy!S}$eIDULk8UW_28XD zULU-oCNTK@2c{2hKf*b9?66}7uL^wb`d#Hqt}_a5b=^35nk(~*6J5tH?(BN(U!M>9 z`qV{(I<>!jP=31^gT@bc4cfjTd(gfozOH_G>9Xp}dd;gIx$>&&+n+hT+OyeOefqEt z)#LVlG;rOgFAg*xefz-6uAVv2)@#_n$2u1b>{ppQu;*PLI6ta*-nrnYxz4UVW;!Qd zJly%se|kEro@?j4`|*zlT>s&s0p|?*>ww2My9caza_j*63;hP1`|U9UR-gT~V^`{G zNB@uh;i%eii(|6oB1hG2BOKK>t0Ot3lgNTY?l_Y>&7>wtR*xm~J4L-D%9x|_4SA}= z5Y^!pwPe*@b*NSyypvURuIiAZI`mf^ey=(lxVfXYuUnS(?Z7_Tj_W6D>yLax`=@!1 z={(h8%~eBE9{TR)jw4lv`QHrebEmCZ{eYASuRjc0r z^66Xd2?witRiAP3iCow@S zt@nTN!Qajae|FiGgT8#S_ZJ=Jjt!r&;H^R1UtPE(|CXBYKd(Q=_0RTa>?nQl#PCyf zXSi0Mk+j1$pd@_bOMi8}bkF14U#ZRu+eU75&AI#R?T_uu48Qs8(SujyAHV(4X&uA< zJBAEC?z=CxrK~fB3;urT;P6Kaw)H!E&w&w7-8K03xpTKIuzh*p(<@#aT)XVjZA;Go z?7+S6ygT?$Cyd(`F8uhwGk0wpJowI`+s61e9hm#lp21JvdcwAkmV9tvT48wbn;Xiv z{cY0+2OfU!z~I&0`fdBe-c1J{TJr7S%}1TMEw|`js!;9o!6%F#x^2rX+YY4Pyk_v4 zr^jqtT(SGWZ*O{j@U3r7-!`i}eBh=d?-=}4jd$BgcXkZF)bFCf?RNcbn`6dt;lf@6 z2bWy1WLw&zqOf+Y+8gp{-pJt@NWyiiL--Nf` z)P7LTKTg=OH#b{bvj3s#Q;TQq7(3ae%_?g`HQPoCY#Qia+kB?*89F#+o{4d^MeAX@8->4r&d%#<9x|1jRxv;uc-GE87Jg!y{_Km6e;je|&d%NQlHOU>-|>pJY3Hpu zlat>x$#CKDhS&r4VNxdkt)|u3eAHHhW*NpY=tslN>XZVr+^}|=~3_sFdKYZ1$AM59de68vg8NS~C_mTG5s@sN4?CjTqlO>OiE57;emF9G&L1`Wus-{`JVXsYtk1sQ9yR>1KKpum)bPW` zv5Ye^1inj-jdSTM9MMlhmro@dA2mLv{{CM*!%AJV&*B9Mk7-s-?XeS3{p?Rm;|2 zMYo6zK1yAnhCc79mfbOZwyTz2G3Sv>ae2&lWvJQi64P?LYDtP2q3}GaFN*rEL8|4h zm`{ySE%um}3slR(n3k(m%ULlke$|qvM6Tgi%u_92#`JkkwZ#6?6{@9k%9N#%M{hpJ?2`>Y;qotYI!i` zQ*%|zkeHT-R7>oySfE;BfBP!cvNYyXpQ@JF>$Oj{?2qYlgs7~Vk%rkgR<*>Axj?n# z#LPyOYB@jVJg2CZjxjBhREy|P!wud^gg$#clxs_BI|ZK2TH?2o>ab+ z*cz2=tF}I+P1{QPHf`%u(zLC_+O#d2Z@h7Zxca&{BY?S_Q4g9vS%ztxBJ#FRoYTY^ zU`gX=m&=cf^L0ikP~_}JHBjVjNm#AEoUe>? zx`z3b$&52jIt-a`{?rje85yEc9_Qq7h9Jcd^&hH#V@zHgS?UvK0Da?3l$@(}#--CI zpEjZ43rgY$osy0w{o)MXxXkk78ZLsoi!;cQI3m_3&PikE$oSQ) zpD_6>ZRg3Sv>j_z&$LqhxR{w|j(RNy$`(D=Jf>wl5WcUQhV%z4dy8sN!q!cpKF`^_%WuOJ1;eD{cMr>%(OO| zx5H;C8?&zu&v>>n>GJt=&0X(qr=4;08SQs0o&H_^#p9BXKH^mKwI8KvmtWkg!>gCx zxwp&nZQFj>c1zbyuXNGYZ@9Q){?!Y=xqscPc7J-Kr0cV17i!&3KJ&=JdoSH}?j`A| zmtJ~o_PyOs)~2i~$S}K){rt1;=XZMl<1>GK`rg@UX2cHYo9_QzI75-LsM(ZFEJTV% zi~7yV&_uVW?1Fv|X?-76gw{2-k1DQ|*^fF;nVz?ZYEiD7R8K{@;j+U1Q}`f8p=Ev4E`jatgIxs6(E+P(EHKdr|sTGMpP zk2J||Pa;zkgC~t`eC>n_1bylON2+=ZJ~K+y>nnK_`b6W7fj$*hRouhYP|5R!(lI@j z`MIJ`Zq&rdHD4R`-Z*p!q^PZ@dP(#oa=2Ih4XD36)!#z(|JCa60EM-;sK29>I(?&- zc}`Wn?O(nNhj*zdxI}$mwo;Ajz6ysc6#2dD<8b&>C7PyJ!r^D$QF)l(s?Yz~q=h~_ z5YGR1lD2Ekci~%ZY^xP4+Z%ptN(b%3t-Hg&J10YXfBM#N@6IDXu3(otZcf5 z$dSb9#+cQ`RNHCnqx(!zEe3+=Vr&RUX7{6&(y=7JiO89Q{l^ z8RSy+5*?ndE{!~kT@7BVQZI*k$#(1kSJ&z*2f9ZWo?ciz?wUFIwbkx6+mr6x8D5|* zo>NrYW``Uhv9U9u}!b7_5*m3%tl*sdhNQ?7atDsH1_pMR?_Ye|kXJ(~eZup)hElBIdF@oc4$^PO#DU`$ z7ml8D=YbSWb;sh%9XlR%JV?Fd_$jp?9645(GqNRtH|?nJZO@8G26ep0fI69El)7l# zYo~QlpZPVbCE1#=Nq5x*?95u8+II)jb79HNhkLDurW_5;Lj7q^@SqUc>7_YUdv9%^ z+86V@#S+HYN2^gSeYI26-lmOI`*OUJ3QclPcKi{iHdP&0Ytz(zkanKh57%a>{i)ha zwXfAKR{PP~Rce2__ItIj)2>(hvDzQiew_9vwLe4isr^~nEowheo1^xVv|H7Fs&>2D zpQGKQ_S3Zc)P9EcfZAWIJ*f7VX!F(nGVL+7|E>0<+Pk$E)c#8C6}7(#-puP*JGx$b zQ?=Znxx}=oO=enuf~P_v zgwaPIwBUr%q7VAXhL%41n3qJg=wlXy&_7iaxpP5uzCpWRSMM6OAJgB9_5ox($tD?D zGIrk>(Wsidyy~H&BX1=ll9pko$n}#=T4WPx(l=@8t`5h`?Z5(pJljSN#-BaqlJUaq zJbsck?V{r9OZr+ELhn1p`M#sHhf`^r&=45STja|+EwyT$1(e~<ReFZTeYFT91fl zB=aTnbQJ%H_KZX$bkFEGCDkIKdY|zF=*ljvo_eo)MmY_Q>S+83{TW-j2ayu-Xd3ky zu3PMHu%gZMiF}vt(I}0TL20q)F)Xe46ecy!6fN4)>Me#%kY6jO(0^B+I%?RWB}w`u mbFXZYu|QA9Xz7t_6nE`8N@9|m>Ek*rFK^(m5u8&;_x}aq6Dnf> literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_common/lib/IQmath_fpu32.lib b/v120/DSP2833x_common/lib/IQmath_fpu32.lib new file mode 100644 index 0000000000000000000000000000000000000000..426802a7c95c2a6dcb2dfc71db83049aaa03df96 GIT binary patch literal 861356 zcmeFa34mP1buL`pGt;xO2n@zRM1y59Vv(l1XO&n+3qlgxu(h#Sq|pK>fCQ3|!C)*_ zVT^%53^uDk3mQoVOaS9Wm=FSv6Z^-G9kSR7&xsSq&yV;gn2^|y`MpQ-HCpkW>K3`(R-9S z_HCtlT9ld|Q)+O5QgeT#)MCH*{IapKUC^JpHk}mO-g;RpNcfBRgu;X71`@871{3} zRpcW_sK{YERAlmE6*>C5Dw60_k=|db$Z_9Mk(n!0WNwR!obrr{ocYHplD<+!&Obp# z79Ff2%l1`~KfFOjR{l&yuD(V^K7Fc+e0GkC+2Ys?^lUWE$KO}ci+WXb=}Rhl*(w#i@^4jiEz(?vdv5%Zir)5V z75)5&(1hPo(fc>3=tI}5=!OLz|3bRo{Z2JR-%<_D-%<@7cc_L5OI5>xY1MGZ zE2`n}NvdJ;H&nyXcd3T1+f+mEtE%DnS*l_7uT;bQvsAlI5`1ik24R0g<-EP(J z-}kGA(PLC2x>94y`>JuDUe$QObE@&si&W#`ud2o)bWqsKy&VP>r`E&%5?h zjrU!t8o%7B8Xx_gYTUR%HE!)vjbHhD)%Yj){l&XfmTLOQ`>N@% zpQxruxSn#GYMQ!8HKh>W|B`AtA+DNczo44t-JzOJyGb>j{jzHM9#Rk$UcEYz*Y|cR{HvjKc z?2H#x?3{~K>^!8q=us70dXtJR$MuS1RBUxj#Xg1j&n#83n_g3~+drvdUqC+hPFArm zA@0$iso3T_RczZkD)!9jD)z#@D)!B{RqW+IRvKgRXnFIKUCI!?v@ z1@Zs>po+cyI~9BPUKRWAi&gA{i&S&t!>YOcVAVX~Rn`3AV^s5@x2xtO7O3XVPSt$O z_f>P^Qq|nIw`xA_9o0M&*K?8nl(njP2=V9sjcPu>Uo|g6{IVxh^B+E_n(@sxe=4n- z0eQ_gBhBrvsph+GSIvKXv1=SG%}?R_S)~8kv#R-9h<{~2)%-g0 z{$7V_{=r+S`ET&sPY+bh|NO_Q`IjfC=Kt8Dnt#)%n*ZlD)uJ}3mZo{CrS)g3WuMzs z%K?|GmV`6)tJVpdRO^A)sMbSPsn)}vQ>~pRsMe|Ps@Cqa zRO`Sqs`bQ6RqIJeKmRS&dis^B^_+uM>nHI0Mc-GgOCDCOm#$T#LWm z*1wpeTEE|`TK^i?f7hs5|M5Z9`p?Ms7fV&^+gnuYZ@N_LZ~s-bMdqls*b}O)RYPqnl-BJhIy*(reCSH_1CMmFHBZ#_u=;k{$8~`yj8V5 zev@k3vR1Wi$MsiFP;D>#NVR?QQPuYHmsHzpi2L4B)%K%lbaD!?e>{jh3-K*Lc{93gSZB^~)H|^)gRr|tcRQs||s`kt9`;~jE_BB6I?bp7b z+HcsV+Hb-2=T@oqyIWNIeLqy~U-~Q6{utsme@V6PI9;`Wb%$#ITAOPB7T)2N`&Ikv z(^dOlepj{s0QbCks%rnqWYzu_p8xajtM*?a&98C&n>$qdZ}HsGU#gDAe^DLnlU2ur zXH>^Q7psmxctv%5G_E>2|5kNO-Jv>CL#m_iE!A=S?W$w;V%0J4IMs1lo9Z|d_ob2M zg6XPb_)*nyNw?~_>;u(t<@>7RQ;7S_tE%IcPpgj4AnM4#&=Z5 z$b+im={2h3xzkn0*AG=4JKs|suOQ8LaQ(ffRL5V>Q5}D~cWwXu*C$oSZ&CitztM-) zUI%PbdmViF!iB?YR?a{3bhU8d{4*0>!%J4K7IO9S6+*5VUXk?ap>yq3kQ|hYUAla& z{e9UrS6b@gRl`dxxqQVMp;lkDO6V(wFR`&#TzT#MRMNY_LCn@(bK{=DIoT;Fksi2%GubhUKOj53#q+F~kXUdf`6|`r{y>QAa zXUdf`m03<35!@D(Gv$>t<;qFQy-ZNflq+X~SyLy^{c zl1Z;CCn*=}%GvA6*&CFz*S&DBSI%Bn&fd&&+KAw`pq#y4IeT3>Nx7E^%GvA6*%y?v zFDPf9S58AqCVj4)q+F~kXP+x)Ur^3I_riT%Is05W`!dUEBZAw4a`t)U>~rNLfLG1|S58vyWrA`JxN-)?3`*%0Qj?N_E239IS3p<3pm^>zy~4S&Wfsj`yIX>S zdF67&@=6sHO3IWBWIT{^4@f8bSlX5=*(C+jl#7+3CA*|-$u3v8WS6`uDEAJ@E-4?V zu#6`W!ELUH$*!P`$*$mqgHj?^#K>fqD`z0%B?B1`WKhnKjF)sWo~ERn30F=h<0S(b zFX?1FP{B($884YB<4J@oXCf%4C*viZjHfC0GTtLxIRhCl8OV4bgK~ysyrh%yG$mOl zT{)eMmkeaQq?7SL1ux-byks)7J#B<5XEG?KC*viZjHfC0GTtLxIRhCl8OV4bgK~ys zyrh%yG$mQ5TsfVLmkeaQWXip;C*viZj0Y;C-)6{o$y88IPsU3+8BbI0WrA`#87~>g zcpzPO_hdXov&@o-lkt+CjF;?o<#aM$GLZ3-PR0Wjyo8hSl9@7|M7Zkd4$A4tcu6PY zY0AB#_XyXXfsB_7WIT{Tdxm7Zq?7S9C0X~layl6=8OV4^C*y$%Uc$+E$xInfB3wCp zf^vE?Ued{UnsP7WJ;IeUknxg%j0Z9(XGq3NIvGz>l69{ur<3uLfsB`QG9IYlC7g_x z%#`sY!j-c(D5odmC7q0?DfcqoBV0KH87~>gcp!svhGe{?lkqeqS@*eeIvFn+$aqO7 zgcu6PYfeK#2$#}_38BZcyIR}DrdNN+p$#|M_FXKJJmD9<19{2PL zsY%Jei9&&l7cfpI2L)n~drhx!P6oP&7G^Z)|GTtLxiCilM zyx(K}A&KhWsfa~xUyr)p5Dc=WXF*M zhV1yU$BrF0&Sb_J`j&tddz{!YVo%r7@5U&yc0jxj3~`^ zT>{N@^wmi#mhui(amF2d!;C0C+vNe4?dPB$FmL$si-+dBB*A0&4Bma#%B#b#>aw&i zqFG(WV-xJunQ{DhGvjiUJCUP$5@b3V_h!c=lG$-!>sckxh0KagP*aid45=|zMuI#( zYmXpKc?T#h=> zim8lr@_1Wfc^a!JM;qj5yj;)8QEfT8Oz>IQhikz<NLCe=crK|<>i#4KC^rN6~k*T)xf!0D)@AVt0rdoRV%{4XQJDTjg7w0aF$4R4fOUT zQiyFup4KOQ7eu!eKtX;8PoqPz*EWN0-f zwJ**vZr9;jd**2?{!$G}U1ihTQz-qdUizaz{{zxz2Fd@N(Rk~~eLE+%e6aP9!_?Bn zTMvn<;iW1%Z{pmEb0*H3IMVsxm$!C)`6DBL-u6-|-8kiz^EMo!)H%Z&4mnmWz;UWN zaCk$@8>1&L-Ec^&nzMMz`eo^P>f`ARYI|%JsCg6Tr01%^^ma9O;?Gv9A8&3mIkf1z zj?s5bS^S%oH~wVvA#JK@=^a1a6x-aeY2uxD&QulGsXn4p9k_T_Y{PxCCO)}-R(g(_ zlb(gAjHo#yDzOAKpD=6U&sR2F(KzF&mFgk&;2j^t)SQj8VvnWg#TKkTKOMdNy!5=z z(b1DTM?X9F=#!3~bM)*^wQd$-X5w!MZ}|zl?=bQ@6ZvnC@&4_oHZ%@GV`S>o3s$dM za)IsA!>g~*@#ma&b}HF5JK5FM6`#3!^|C7<+OLWa&5p0_nc6iq5ud&C%4=6GzvR+2 z@y;bv;)#KQ-eZxrKYq@#Ylc_H=dW13X4TbKEL*XL^pcgUu3Wilc+Ikv_}r z64R53zDfGI>}OF}>aV~#61|H@1#4Qq?#Fl$QD?Q`h%-Z0UOHAa>9P%7$nf-qPhVt+ zr*T@yYxD1-3!m21(-$p90uwomGXj3%KYicRNQIOa4PSU6{_8)+FJv_0pTY0XTzFwD z8sS?_h%~h98~a$x=Lg&I#<$-XQ4=Dc8|+Z3;d3`e@Y{sQevv_}$XBrPCi7vU)_|V9DZHU|*Jj9~} z-dI}=5w?hF1uuybNNd(<2x{Tr%sCOw`iZK?KzZM)G55TDgc5_VSp)=7f*4( z{y@_EWyLZWYU(?dty;BmmCziRo7fdghhRlIb?LIjS6{O5^5rX*2|c`c@v3EO8RK6a9ccu*l1I$t?`kqHa`Ff-V|}A#5)D6(v^{mf1s6QULtYdoa^H~y#~VF} z*SYSkj|=tDG?c-2umgk%>M$HlgHKS`f#!Eld?!6q(`x9;IGgwh>Jg8A#-m^GXple# zhUicij*=&7Vl=`~3J1xP5z>hazVBJ|WXqxfGXlFegF#Pz1oF;0S|6m_vt$hscKqxh zm}=0IzxTLA#8Yw~zi;G+x!e}@HoXQvt-s(9A`|_(0ev~quctfZqu-rCziyP%hy%4S zE;t9(NAz1~(Mf;&^{-d?mrzsL+?-;U0R`m=PC+5rjqoY5^4cWzfd-e*+BUro2EX`^azOT*wOadOMV z$d9+g4jWaG9i0cMeba~CGjeQG&&&9wYc!I6QmtR#l-{D2;O~j_`sN)IOS^i#dGlb) ze{|uwg1}oEURr;6dIzNc5mgY2*|)|Oi|qraV=yp1)i*Fn*C`uauox5aG}b!+QIW>8 zc{EaGF)a2=B3S(GXq$#&VlfaICkM@-@XuWalul{zd-vd*B`~7*Ld71qKmMfenqFt1 z+(;${$_ZVBb;7rS_-rT_=qHp5{ftKw$|WA8?coN>B~L>6Y5dVbd3JhVROh$Rgul_z zM%AEBP4G4>RKuSUu}`H`j_?uu*%1Ww;`fkWPEf@U@q(Ty^%cRm+#HK4aC=WvfI6&LJIp0t-p| zy?}DMCb`+;AvDUdOvFjh&>-dHA-#!ipNBjO92s#{S@e>Xr@DK^9vvFd4eguxoIO#`yub^YP~@~6n~d;uO3ow0LbdURy{ z+!&4jzuU8(kY6?S5#-|K4%)1M9bT zszLSO$g551P2d`v)Q0qyhI2-nfci`D_e6RG{3Q1;v+#>a^>}*o`eV}D*AGS|=IQk2 z^vIpi>YO)-k?6X$QT6iLM%9#l0J%P(`0M@6e%dcKKbF2P{qoumsn=f}*?7+A{4?gI zw|8uhoijRHQ(HjIKO>pm(#-2E9b01Cn@_^^Z68FZ#MCy_j`>DHqXgY!$C@=oMSH}L zQJx6C)IGgBm71iRkevyzvej~uccQavvJsXxoAdz>rKj0+L!ICvZWV{jlPU>iT8L%8`&P))NbCN{h z8Ri4~L@4GeT>1T8*hYSy!;a0#-C&m4U1eBGxH)fsIHPqr%wyFvplPMGR2lT;tsnSNU5L?KQzvVME#PZn+Ke5vyi@LcQ+)VTHN?F}c9bM3V~W_T1O zggiV7eR>?jEbpVpk)d`aI6)aU=STr|_a6pYmQ`IMrPZ95vZ67Mx0W z86Hs$9P0>Fl5i|?dEqpq?KozLY+pDHQCsNk9u3lQEZ!&ikmh^~!cZ>`axWv~gRKUR z#U3O8#dkA7;Kpz)0*<`1qzE8}CCkULjmCCiKvZg^1$3?=msAJGMY6~7}9`BD(#$y`8AD`IgO;7fvrl(TL zNxCN3R7Cx0IHLvlxfGh%#>eBowjlmJ(KbE6uw#(Wz(VWEb^)o`31qC$23p1$ARS5) zQ#u%dkApMSOh=k%X*!Xasb=XAh91Dd#7}_bLO>IdB_5>9pZ7^Vq^+Jx&rWBj7nRp3 z3Fd)rjeciTUVBz~rQ6uNl6N$9EAturq~tRS63ItY2$v}$Fa)@4d7h3l-Tp+K!la6- zkAv_!QZWQZha>vp)tN_l+V3T(cXa7uIf)O?dE(^~3_^J}? zb{SWRSqxd@NH54rEsP*yrbb2(k+QDPPkJ;+hpdE1$%ph*{%AEa zaxWtUlZ<>@ZOGb*H_Yzu@(CG<8DOqLYe16egEx^^c*GszDEUEi%KbUhhWOLQHy=qC*wcU7*`*&h82=y#F+ zJe%GO360=ly0mf|g7r445?0^+21J*AgWC&WUqlqUoRUE2HO6 zSv^0c+4Z}ifQ|r>(V=?GHMn|{8>hmU8 zbnd|GWn(jYkigqmA+xjS#Ft>72bs4AGH>@JU1w}q;Bs^j=SXxek4mk;sfgt3zr0}c zy@6Jq*i41I6@s$}(ONu}TWR6x)iaGV*?R<}_XaKC4blN>siLqoHYrII9zp)uU~G&w zO?*TfaL(q70K6$4XQvmjcv7NEC!2{QAuSfNF-H?%=&uum4r6B|sk=ewS-c2~#r#I) zy9|=bS6K+WOA(9t1||@^$tZ#@TU42j-bmoaDQm4A;aJ&PV zK49~go+60ML?`H!=0F7hjl6^xFX?wa@$%Y9z*gewn`-3Mp7a3^?s)V$Xc9)wA31hQ z?3nb9&i&Pl^vJ8*I@P}0kKTSWalQ3NBkPv{lQ%bSak`3)=??YY=;r3l&Aj87w0h~$ zyZ2Hz{=@8!B*1jBVp9d)#8j7UVP_PjxMIVPV+U62o z7BIcX7v#UT;Ph?4X)^1l#zMe-s!bk9-D#JB=$S7K#oUT3 zuiF{&R9L_#Y&7YlrBAwM`I@5Gjvh>G$4TRO_S#vqOg2;d;a1oIvqk&Smv3$~ksQ$A zZqa=^(ES+TnCYUmfbQ+6cA|S`h%arz`}5x2f~fDtcBrnWpv1R@`N7@^u)xCC3wb<$==^1F7lB z9*e!KVq!1x12socxriC1ZU$)VZ4L%V*`fl$t zpnz_!jf-h+nNYAUuqBjLu|yw1sos3HgbC}6$fDF%pwvfe3Z>Xbi=kAYFgG&jHTc%< zvq+K)rDTl4mN^-JM8+?RfD~=~X z+2>79^!H6qcK1%w@6F03KCzNeXS4O2evB9SG_3w>3p{t$dfAUIyKJR#G!{U|uvhO7}J3bTWRB zP8+0=F3XbTvj~`ClN)e45mx{wY2aemgmfWjqHUSpxh7-wC8aZsdG-0x=V`^<5*^)o-j2Z?_q~C2gB%4vaEI1$-u$ifhK`-- z4K156Cf=d8tWS*U`S|rSaYYN~#OTN!`G0%BjgRk6e?EP8`la<}r9Y1G_#npPL(p}8 z0=mwpF{8f?FP8%ox$5Uk+# zxY2HkB{4?EdU$NkcF4>hB>_j+ozv; z=^f<*G}y{dP(HgLk$iN8u=Qx0JQxLM&poksnZR-JB_N5vt|JviV5a0SH@quaj_t!T z$GOVJeb~=AGZr(`WA445fvc&OIWS45vaahzs(5VW?PF|$2WTu zbUs}u``mcSyY_ipZ$3TMV>csNgt{iK6CKeb*735iF4TW*LG=->3*}^$L32GW7Yrx1 z=RdrxzC1Zwh1)!InRSf2ljv!C45A3&a5uUa3A--*z5xA)! z&_T2Wefcc868#}tgRcVP(?F=&(Pe%Jby`eIFw?byQZItO3kdL&2n3k1%W=2Uxso@mu=5tJ|Gw^i>-mY=u3aP<% zjCkzyWLJ{*T9fqau>pvz`{RsyJ&Tv>7+&O)m~#|D0QN7mLcszokg{@GPwF;Av2Y`3 zgISRw(!KaY7}|`3VA+UAf7PQwTD*vQO9~>Ij`K(4Gk}BS!wA8bYFKK(=E@Gz;|(UV z&&xXpX{DDJ!o)6{+z7v?;fi<{>OG=6$h+1pNG?f@26S373~mnF^2x7>K6``NsqZOZ z+bK1LZ5)ym!!{~!B)kCPc6@{1G{9jkO2V`72S{R^&&J;gNP9>DY&+abPi*@mo3|HT z1lu@kGcsc4Y@Wq!CWCBL6a5o&9xDqcf6moq(AI$#KqGA@?}j$I_zCJskAB*tK{`O=eUcAp3X%vz+=|7- zn^CfWLp1=Jc_aOv-a)##0W@}WdFLRJbZwR_pQd!0O>O|~6kIt#lg2J8#%cIN>JXe! zYq|2pbH{6Hn}-l<5tR{=DWnLFM?H2ajzo7WQj(YP6ZQ$H&9o7{sT-`ulq&+(MY z*a;a7ez9w3iLioi_ z&JbuLEpO0qQFSiPKs46@ih&sua!{J(bif~mYHV8_fSX`jGT*vQ?78e?+jYP;>d9&c z+bBO1+g>byZDbx2o&s?%(!W{&+kD1$I?@j!?W6+OCdz3(gUx~lm2cXk3Bvc@}!R!g1llAFm@4T&7_rAIm*46^DA%4OPDP5QPRsQ%FNa3jZ>mC7GlO)^l|yt zt8dop)i=p{b-Pks&yqJMG3T9s#k%Y^$JZH;v8{bxc=ZmOi%3bRK`U@7q{tkI|Js6+ zShu64LMrF%bca^d@yh<&1+^WU(=`1;ZPRV!AHJf%fRP?Mbj zr}E8oU~#dJwx0vqJ_KB;9kiuPN3<1tMFF~a(1Kc1C6|;jzk&4a7Ci+q1r3=_crNK- z{9TGnFDrny!he~b@ADV(5{$4x@)xvShtV@f&<17muUan!UCBYrBYj!a^n>vnc)KTt zSKP2lh_L)hQ1ch+w=F1(x{Qz%!OEgob7Q1X4XOlI9d-j>`Lzqa5(A3iYaD6X@W(Df z@zivl?7aj{yxB`o=qFuz)4dGRn7srgAM&6s{2^#jRqkbkAX9a&T-R;P*9-;ukPN=^ zQ<72y$>ifHgs;VfSLQa`Wl4NJA6FQ`2OX&dgrz^c~+!#C3Y0tdJGZt&o(D(Uw27`^l#Zb;fLb<#7>t*-`cE^Z<4e z>9ISButAB)GjT>cUB=78t|dY*E`a<*spg#4(C4XgHKyg-a*l`g)XH&Htv%K4i$)Cx z`Q!{5^P`gwEl4MySs^s$=f@C8yJ77qf8!gNKr~(gl4xu@qfGhao$O{pVlmGp8u?JW z3PuhPW3&n+pjqfS`8ubs#N+ zAgiDz0#DjzP1ab~x8#OCcqyLoVp${V*IIy$=T(9zFgH`9juu$##C z*jHgm|Aq9{gVgAbFK$VX?A&jkn94mPj`m%6@s(GnlH;mj4Lvn%<-;cMw5(_Hvha*} zC^J(_R=PDtK6+wFD-13u8!efg`J%&fN|O*T3f6U?`E3LDht}a}zueuP6OSV=gsPqs zXKQ5#>GB2@+3B-UQM!2{RGenBHmJzyMIc_dxr@o5NG;H)jeCG;3GJOKL(=TQm_6rg zc!saB`+;ef;OjL*oLay%GJIlMZTT8YWcV7JS&hENl30hG)7MynemZpL-ECiE|5*1m zwud(%vepe2i{uoR{1zZO8{@)~A8nhmLovzkRNMm8a~}1I0G}v8R2FC92%lSOF|Xj~jDA(%(EzyemylB`{Mz*1pERt_SBvo}|T+ z(Uf%iv&R7?E?R&OPNyaurFTYCqjg>%PYJ^uBcGpdGS@Wk=}N5mTzq;3}IX zOtoo@*qfUr9B0!6%7Bw?40ANkJu4JLZ4;S7+*cJ9w+Sk|} zp5-=17K-ud#eA z>%PV)V?*X07#m+>cLrK{QOM_3#1p|qHJ?)yuKOCR`x>Kif*?!br5JQ09mQgt!n-z_ zxZJ+R5_H3qiQsi#V}jt6C*Oh|Vo&-S>kRoC`%spzvHi;SHMUGt>T(A<#3YO@xj!&%HDhb1SX@+~VTSkh|k+j4(}XFVojpLOTJS&(xbXnxY1bR$iLC&F%T z@>cgXc9f|}3x+ds1#~Ob*O`yrqaH~9x~cZXEaPZVl!?ws!R@|Nl5~Zu*=0zuD07- z_p!RKG3*wOn#g5CJparqhS%6(C(*JYG8f0}QE+(fX*JShV{4`6p2GIQm*82%-%>ZI zFlftRZn?h35_EHuB|+x%)zHoPe+IKhMcvmJ+R0A;lB)X}t9D;w$x8bg+o*M+5O)dJ z6nk~B7*0gbhw=vJbpj+R7wA8Vz9v9F8MK%nun!uL3Xkx|Lx|>96$n)=L@&Y%W&?d# zh`t4BvVp#QAsX3;$+FJTJa>@MI?%{q7!-iML|l&DyJ!(gvJvProt<HMXf5eU171t8u8veIcnI zgw~nLrXu_6I#*Lj>NY&bc4{2wa&%knfVBy^$bgkO8et+lNF9%9=(?{l5z_*j9LpPY ztCa0)Ea7~OQA|5)#nQ8f?H0M#=+f;RX%PWBAoMr7+&U#)x&a?KIj9f2~m9s)_G69-E1~Cr(c$VdYq9Ut>QLxEnjji=(DQWV;@; zh-{=2_(Q1s8nb4I?D5%S&`M0el*@HK{YJ6bB#(;s#k#7>3C z{03%4%9R+Yo{(vcHqcaAm{$}S2(PT<$du`5J^pDNjd~+8M0y&d0i_S%VB#mJhdi2l zKS?}DC!O*>$%k~^*BEOj9H!XIK%T6uuQ4Jhp%x1<1J?`7S7a~Bv1psMX1(rfOd9Md z5Y^~wEZ?g2QqVQGEQ&s3_oQLj#|dBEx^-{G%~5zf5td&G5cWb|sv~)k&+l#c)y1_9 z*4!8=6i7;J-FkW`cUsqd_`+CEt;JNZZMR z8e6%p+nB`)g$ee`OrQ+oYHWm8J|^eN^`IjaTmGn1mX5LXnvvig0E zSw)dQJZ8^t7dwQbjpSC!)dmM}8vxwy)fQ4hCiSabP|e5`&2cN6hAy$HlB z%hwq3D`eaQOiR{%jj`_IJlHTO1kOA0w+>^@AINFurYizI@eT^kxotV?tSh8}y#@?*^8ms#n zE8W+a1~=nt%ydG3x|}mdI#xtFnJ=&V8WSWU`t507V_jA5YpehkL*+B(8z$%WHP+QX z_P)mcL=Vo5JV}cst25O~Q#~a`N-xq04mO4nIfc)ruEW2h6t{5P!2`p|7z-rG1Uv;#qEEgrNr-dYqvLC?=xZu>}XtVpm92Q8By1@vz&rdaAmw zG5K-bs{0yabA@MmWq`@}h4>qL zUt{^!#1!^5MqDM|FpS?{KWO^E9`ZHT4WBlZ_BHl?-Pf2hJLguL7spQ50YSJRpODef z@FU8Wcq^r&neCoR`IcM5LcR^YfMU|EPFXU#)_sk!w&Oh5aJCRQKZCz&^EH;J`x>*p z#!_SBYwWf_E3Y-{)U;E-jzcC9Xy9{-!gXI`<20q`!-*I05_e2pdRzQ$PJaUN{ARtTIaPre1+r&u=1+^uifXorCME;=;2 z16}9=J5MY<#ZP~NPH7HD;q;sAF6S&EcRum*+G9e##`e$hH8!DaUt<&U_!|3A75f^4 zhN7~*#{S3b!Qsz+5~9t2t)LK^7dZjCz&t4WOx@R**U?Fi-OT9m$UXZjk`L2J-8JoN zj4(~1yi8wX$-1vGcDy(bHrS;Z`id(mtHIY;N0s{;gD;;7`x*T4T zf0MVmuQ5t23`V&-6BH!WQhkkSJPIww(e~)v-7<40qq?s#UClU92E7LI#C?{-<&r_o zw1~NbV~DZvHP%tBzQ+1`D(!3RDZP&_;=@OcEN&Z|LC;5=B`x*<+Je`O-0XUVocWyGruDQv&uQAkNNPeP1Spuz`tKZic z{ET&ASBhQSks{cO;_meAwdHH959?tn?Q86drEX3^@TA5QI?r;)&gJe;5l1%^Y~`Lo zf{B^?2MLBg=F*t`gCri&4qFp0O=O7lEdGd<*xaWrJH4{AQG0et%3Qo#_9!?!_p};m zL@5Q*hDyynh3$hcLGHxgQa7kDXv<-4xxU7dbzfs_$v6)-aLK&{N|2M$Gw!!q$zl@Z zElB?c(!W8&4ZZHbOui4x9hhV!P{(WQS10-Z-S1gEhw1zuzafmajnEskHcdROWE{n~i!mbPQhC?T z2nf#OAw=8nrtWJDEg(j;+2&h=xg4e7BkPGAetypM!v>&YK4Lki1iFp*;vUs&xMH}L%ayTH-a|8Y2DWt>q{x= z@#G>65%&3P;a7S&YcAh5L|yoe!C>NPpon*6`5H?G$-^4ZX#;t%t?p|~*SS(J;Cwr< z?VA>Va$(y6HZ4!I!5VvCW1O|A0bgVN{bS>6?3*D-tDL5E5*kkcZ5?OPz$b8cWuFjj?LuJlHT_2%I_VT#dfQHe#f^ z74K$1)*tDHTy~AeP*)x}J?ZbS#-SqDqf$QzZa`(zuJ{_mc4}HLiScW>1J))yQURvz?g4f7M(P8>IJJ;Ex7<(*Y`EnRe4`y{~&N@ ztj)&)^5UpT5!uFS0>(~JRP_W5N1N#U8A1BH8H2LNXNzo=n1CtQ*O-B_qM)ZObhxQs zriD)3*O)Xkk)#%UjpbXfUd$U#{uS%vvDu@KmG*hi(s`?QXy;40kn^?h65GvhAf{aSq^d%uHQGRPO04c{Y&EB$b)fdSAsaI>8ogq8&7~#{ z;j$s3TiHZ-M^m@5IA;ld$p%-Msw^}fo?`P1#4kcaFShSPGnKrD;VatI^k3zE$g`plfbf)bxY#T(|C?2%Vv~;)YE`gymO)mb#FayW(pMYigVFAJTTRpzdpom1M)w z_8j1ApZtV+G@tzJPz((XF*?qmNd;pT|nY>gKR`Pn$4LhGgN^Huk<(CFygCJG~3 zAvtfRzE=(9lk=Xz?*;)UXqG56Zxi&SoF^zrTGmEVtCyX=I@a&7UFCBDX#+bpgPA^J z_m?iOqxC^LJWJLPVVBPi)ZsAXlle}?Z@@d(Gm1c+hBY(tHeJvck^p5LXRfywIR{HHhnJKJHkuP z0nqD6|3LxVo9d-!Czxf^deIK|A~Q~`avx(c^>w_ssYl-$iGVle6ZCmJj3omPV{C9i z;pBiG@36N<8Yx4fBYaA~{A6C_-7eoRiJfRE9XtS z3EX`D{qRTNJ{-sWEzOevD`Ch;BNG%soCAC+Q`tWWU?}bo>6w}~Aa3H#U|nc}xX>Ke z2+iB%Sp;qq9~mNj3V(!%N)XRZFCfk&1Wg)ijgB^|26Za6vIzXf2!DZpF|q|4W9NJL z3=^|w7jx?Fg?9-DK?K7LSkKwaKv19%GdRv>8!&^D-Gf9Wz&9{~F_(cPdyp=B&hWLD zuUvKZvQ^8Mtv+Mb(q*eeC!0?{Yq&(I{>4&t|6;8BI1e@~69Q+>fz_6OG1+%?to(~T zQP98G6CwX%PiX&Q_rSl{!M`v5#d>-x?_cbnjdB>=g$%|pB61+P6vpJZktQ@B(u~S# zLUej}mmzFsc}5xqHh=msIzGXjEQ-r;WSqeXVxh@^g^8(6B2=^M%7igA`@COydqhO8rpCX>Y?>5P7$rI<_%wd@z8u1 zhuu>R?GI%1IEGKF`xkQ!q11AZein3X`4_8wPL$te6W! zF<0YCIF@ycS5&cP_|0x|Ef^Y#@-6UtlZwZUv7mp1Uz}7DYmFI<_U&$H-!?*bWLSSK zXy2$Ep!V&zrd4d?gvU=D*-O|4;x(k--)hKY=76H5&_--DcMRinCGuWv(@Tf)(;s4z z>LZn{Kd|rOMLX@=&d$qD+}Sy)VQ1&p{&Z*O^=GbIs}y&(iOxumzT|exxn-C9i>=GM zV-5R+DE-I7bj3aowuC*E_AmBT*85c`By$tv*Bf|z^N1&XRrZHgPUO$BgP2AI5MA^yhRzgWI?Fope#5m(7KOvms3}$V!cjLB4E_j36RqU7?@!XpjzB6E5ED=s1-> zT8)g{%Lu`wx_>d&Mz)S-HluYQ)}9Z_AZv-zt^QU@M%SGF#qvq9-3j~>NU>jr6#Fi4 zr*@>+lTn$JVh1f+3JZNbb7J^C5Y)#hKUtL|TnGB#x1zOnHywl2_hXwAAeB`ngg zOcIOMqQJcHgvjRxAseHxc~P!b8GXhIHVf59K<|gYT=te`9@OY6 z1gxp6Fw%9lu0o`40<_QsXrV!dKw0u3KwF~{4a(W+MOVQb2ziI%&ww&x2ym3pgP0?6 zHN(a1S>Qe%?~x7MRySky%rub62JRCO%g~I!e0t_nbqZ5<^OUrWVVsG%G!%0yt^nM` zR*pIidFslQS0+3UwGH$zWOJnUQlWx}`j-RwxI~qANzsdS$m)?vHOxfNrJw7t?qoSf>{iYD@IGe=$~S zoCg~Mg?aV(7u%~^{fqTt?M-*@Bwcj`0InD0U=%VK$Du{`8j|f)_3d`0;8wkNE{E^s z%6-g5z=NNffD`AU1e_?}38;{!Y=$tz0l0~;`xnawCrY3Ug}`ZwNn*i?b4&myY2aeB zN=O%iCfb(e@-LPg$Tv&hZ#N1zv-CGYzxne9QKr|zEd5+m81k$=b2#6l zIeYXD(w}S78x4>tvCxK}nwwVRv;mnuZ_`U7lQ&6vF;(OpQ4G#d-4SwTjkXwVd#&BYMK9sk2nIvTc{YUWz0`!wX7X$k75TfmOQ}-_h zHX+K*U^FT*gJ>-i7&8nKKrcP3n4rBY{>2gri`fRbWxaacznHYciy*4czZhqf=wEEF z+VC&d-#teD#lEH$3PvE-lT2k}CEM8uZsEmo#Cj2aZv-tuD`_qbKp671n0}1_SVS2wtRL}iN4T|!e4>>dI}^#!%1sFe&vva@@r;@ zdl6LLNO%E6_4ya$tW7QW7fWLHW?+)8OIAFkMGkdP|7Y;B@NR0R(~1gBXJTc>=R=TI zIZY|wQ~+%qXaOS9Vyd*!#fLqFKkdbXbb!YDBp=cgBoV55FEtsrn^%?N0hTa;b~diE z0qt;`rVyY_vuO;Voq{U|Xwuk4#W)RrxwNKr|6;7&I1e_=7XoL_I#;8Au_vn0znH(T z8W|kXi~2#J7nMy#wowy5Wk`u&feYKHX}u)Ix#emmn~;kPSec{w_QC?$VTc#}8mnn& zS`;Bv^)xi=39Xb7jFL^(e)6-(#;@|Hq4^NY8+49k`xi^Gr%>~lpqN&`zgVj7UyPL< z=fMUt4+&3!xEHNn?f%7xb<~O)b-BM*$a(wHMH-J)nC^-2riisdT}etn#x*k0jvOB~ zx&WslJ{?>}yxqawj|A?FwfR^;UK~#o$Q!E(7&}E#_b&#(6fInM0_Njr1qg9LFDNF! z>6Ar5Ph044SFz0bmAZd1RJaaAl3MUDmT$d!F%LNTSFFo!bF7B(z)JhP@ai4f`4TA; zI0Gp;6;fml#D8rO3$bp82x%s+?KFs;3egiFW?rOR_@r5bOl!1(Hu4W&Q6!)7U$fq= zpI&Qg)^#hJH}{UFZbhD4;%e1PqHWiCU1&T!#oiErYxbl^ppqg0Tey|3R19p9uH;pf zNSn20z3yL3nv^nTHToCJw`#oY`ntm{z>(<>9VNvO=xH$?{PK4!G0))Mgm%HL$ z3~O!#VKtoYKE87FDELa9STTH!BMotwt8*x-8nd&?u3YcZ`K!8rF;frvSc>(~Y?q$+ zN<%}4v#v+Vq)FcWYjw)fF_uP2R-~2Lrj{Lu6S^-tRe=%qW zD(qkEo>I*@#XP87`L|qK&hgNmS~;$&wWs`G%iTe$L~pntJc-M<*CJkEm+w7HPLd2ni1>1TpLZ05;_gq8_H{(dh0 z<{|Bo7WJjG_~{R4LK`UNJ(At)G@oPs+TMQS_CrTUw;ekA*?H;h4foWde=*<6hXx{^ zmi0_t7M>9gJDfs#r)f1tK1PF}%_yHL7cH5YX{7L+(j>%-f^{8enad_^=RJlty7*n2 z6OZG5gsPqsXKQ5#>GEbyoSj}edXQGSc_AIZG@IP$064t}#0xifu~B{w|6<*B|6;7y zI1e@q3W4)Z{OxJ~VkeCH{>4tOO8;W8;u+{C4wyBCz%1imth;jl#r~r1Uu?~?Yu4yG zHgnevV78fI>Qd}ZZzIVobEa9mnhR}oAn(nUX8xI146nJ=q#<54MA~u8exMm-ip)0; zX|mBRJYzmC{>3z`8UJFY3tDJ&tGab;<_J5LZ|!7{*g%@Klb^>3yY64?2-7?Ck)|Y- z^)GfpRr?n!fWlDpjQKXnIsJ4L+mmnK=H5ieEAJ!V9$Qf{#)P&O^s_ghcB!BJ zi5;oa(2yankLIwjzuU8(kY6 zm3>FY%D>p-1^tUX9`Y~txb`ph^4ddxZ@i0j1>VKjm8jA949@6LkMgqcT%GyUWSUXz zA%1F9!?Fa_m_KN>hGt2Q`-BO@s>r6S9z;*^xq~JQOGCyvxm9?l(*`mxy9uiLFv?=Y z;nJLoEk=5o90X~xGOSvOBVJT1V`aN`6(0`O3Joue>c)JV@)cIY<^k+Bf;xOz69hvH zzafgqJ4=eO+B|^yf5JV49Ei0@4pgdhF~dSQA*gS0T4;S$igPhqzL`v{HHPq^UT_=V zLyKLG6;Jf`^q4hVW)$-{_|O}uFjI@Qz=uAMIwl`#w9PC%BJNru+q>BH;6sBpeJ(z< zzjrU^6{mu)Y_RF=$!VCGlv6+w$cO&E&WD<3pD{1JrDIEMdvlg=vB8@0ErxvryL+q- ziye(z>JFUI-?s8nY4ehN`xfZW)^1{t)K2UE-Wc;KVPsXpuZ}>;g^X0y9I3qBk~@m7j&vC!CwzQr~GachTXaoUDF>wWMc276L*ePs@(c=R^V zuOdCiLkziimXR9G?~8C+flRNo>7_@>Scs_(;lT#-tnbT9NF>gZzBJ!rx9*Z}v6$L| zCz*%)t6JD2M8F>pJ8k2cp2gTu#C$3!Q2!U`H~knd@?pOJ+A=PAzqn_ya>o_y z0WwZ#11)0=kQP72-$*;bhXaFY_H25n`68wFRj2zK-NgFE{eyf>29+1#Cn-gcO1_{% zs7(2QAwXrz@pPQ&_13t@##ke5=|@GTZ@ZDMBm+V{GC<-iEA8&Q7KC99)xAL3dus}1 zk3@|UWq)arO#m*AcnN0+fipE!&mn!Z0Lq#kZEm^g0gW{zL`R} zdbG_nz|}tY7?E~ohhomh6=d6>7nOjlL+6%`t#!X*tnN4uHk>U4&d=bl+Wd-5tNRtB zgpHMniLvo3_CK=Uj#Zyi#}0hvA(If5MS=O?x?eHxdotwM8TOov2V{#XVX1f((qyA| zrKDoMfeFO(g&=|6CHfWX-W9)M-F3fWtnWAvHdw8izM>A|El6s6(yv%|$gkLhEWcv= zlE(Fa?S}V^wo?zhd^g z!oonz4cH69Y%Xidsk>y6c|3B<25zck7>w9`8K`XFK0&7tBOIy(v%{%2DiFKVE|G}c zmxf|)#T9_Na(=}K)0E0_((|LIEnjik@HKwS?3K$dzF5{?YU57MistkyhH228v!V%l z%wRCHqT8VRI0mEqy>-!QVOF#qZ%W-qW{7(cb{U3_;k-jN_!Zl`y8VjLZ%>8&iUp2) z%GXw~>CA^5wh-Zbk<7SV2bv>ks9Axxr9k4H(WuJ^;E> z{fcQk3W1c?&~his%w3Cm^Vtw45+UzBPXeVrT2m;+K3WW=0)2V)_!Zl`YW<3(D(zS7 z2|b3VSXizql{k|NoF*b(z^U$6jJ4#4@DQ7W;B0Uze~8T~CV*3k`{Z`#*de#O?pKV> z6z9Q)^M$~fb4S(hR}4PII`hnL7%-wEmd%#`MRrF6M&tAa*7?A-%0d ztt0&==zO+X;zo(JJRY`M_IcBjechGzEA~e~bvrqwHJ=*0O$Q2^y(AZ6tg3$)7> z;rB++qV*)*YdS~Wub7uX6?-}aX_W)CNoZ^Vv~{2b&`8_KyWQSHjoMg*s@_9Q#_i@+<#>Q4%$zoj z4YL95aGQoTmk-dU*)>wd*pyKx?Dm@fp*oOP~7 zzhaM9rC%{`KQ#^&X+2NT@txZS)+qU{P}*s*`ioFIv5_G-w?0639FxJO!c_{E89l zs1-HE@>gI6Zkbr7@zCqJCr(dxVaBG?e#O2gaA&N|#{%-=s3{TI#%cn_PEl0#1Ps3x z`9eV2AcC9`*-l4nHsn=e0>-YPblpkBvV4vh43rfGJ#C@Gt^6`Abn^QZOTu=C!PpVr z3e?*I)HC%^3#gYs8xi$Bu&8HGDsEepCm;2QB;P^$15rwbVk^}bBh4ygy4I$b{y^p^ z_lmg#^P|nxkK`p7VS}X4w^F@vN_57;^h@iTFsDI}3;EWn7xR3RZw6#MHh7FqnmYA@ z)vK0VfbofaUU=;e8;epQP5jUXTwS*dUd6C#hxn)`LF{CQR@2G!$1dsY*p@P<(FWQG zKU~!z7%=|p)vYeS#@4IrM%MM_A57hfFv+h(vd$=3lX199zjf z%maNn)bxV!T(j<;h&AipY8y5X@wF3Y)cXbcZI9$dzTH4vMo5HU-FaiZjo_;WQ%-{H z7P|6V7j&g;RSaF@NJA7J%T?>sbpEyGQcO3od2{b5Uy+ep7vYy|bd@is5V{_1^9<0n z#8vA-KPmxV%UQLq4U()lD>KP;pJLMV)K6BwPcduN*_PjLSUEn$ZibY6jJEor%}>nk zbH^G9VX}Bt;t%7Y8W77l%t~VykqY}1yQ5T7PGbo4RM}o~%C+Mhj|DtdjH_zR=`8fF zYzf4$HxYJMvTL#%hC(GYr_7LVU;>5RB_KKalHOkwjghcS10O10>psO;<#8Tt7!U$y z&Vg5#PqDje(WjVi;X`#DC0ov^Lb5%Rm%Hjy%oz9>{Q*rOFDM%=@pSt|hv$mpM>F3O86sV&`S3XMLa6HbaJE)<2+xO~iv-!Ic(}c-kdSHxcic_Hqa8aCuPmQp z#4k~~%KGb`x=%6IeVhjy28FBG-0H0!yre9t=@%P22 zSa)~jeTuzlRKw&ung=-!WG{seIX0vT!>Y)ptRBSPW^U5F%#t|ebX)cY`cy%C4& zKE;fBxN_U)-GI8KX>&M)=l`C-kJ*EdO3nXK;bMYtpifAI=1EuKiUX8VeTo?tLM61m z#aUhGt5SW6nM|xLhVY@@e7omm_!Qd!ON_ctvHe{unspC*)~8sl^Pw!CV(V(grx^AS z90Q+XzaC>gC5)^}_!V^mG8I6~mZ<>JV%PVWi=Uu2dh~XW25GT8>P>`3G;Mc3uKN^2 z4GAxr!3xtsV&+SPOLJi;=4xCCzcP+MitE(K+l&>eSp?o&*+Nv5TC_4^dN zZ5Mos-IaHr8up0sv?H|7!=8+(O8XRh$FtJLkV6kcfXxV6J;sP~#}(CRqn$8VQe!sS zoI*9)BlG&^xR1RkWJNfpHrmqti_K{uUCB1uJxH8oqh0qYChblQRrUE4%eVTakWVq9 zYHs^%(*wpCSB)qE`)v5GskBeAe+}%jD}k%j6_{^-q27H(bT{lHGEqxR=wJj)TjDs5 zwRLvgrx@!x9Cq0{JNN)fK-My>vwP}3#n?h|ubIyF=x0Dzn@_Q+b)RC!r&xE-*!UEC zSN7V`+ITJPYK+Dqtb*67cl%RLNtpA&b)RD1_hiVib4_zH9#Bjwu3n#F1Y=6YIGwff z>J>}R9$w>g>4?j{g0ZLWQ;fYT&VvnBtER6gPre0PuRZBgtUu&aY~L)OVtbeEQ*7@% zKE)=$OQ4Wp3IS_!Ho?0>DV5SkY`0lL5xDEds@rd9WccrZuyi)!ZhA8hmC3|@A6>_RiD;7VcYnq}9lF)0-pK~C$BF>|nJ z>cc+Xos3RLmLx7fe71#1*gX9xcdt)KteJ6}iJvfcR;o`ijYl%O=62EOsrwXT4aa$~ z!OjrtE6SkPpc~z1Ih zE=$q>*>l1<;4F zF%7;1c@uw2-HgJZEr+?~`V{M-JDbcsFMGT5?DX5+9omO&6RdwHqfU&3Tnl?%E<(j} zAGRCpnnY>zIN~L6dA$TmkaeG8zc)U`diyKwQ|$9Vbvrp_EVV3n>l3t}_^0Fb*(yny z-d*$8@`3)N=$EnpeKKgVL14c%AQfJWJ|04}{ch?$#n1v`K^u%lC1#LKqyuAyK>_GX z^eINLCdiX5xCts=glDZn>(r-VV+HO~EJ0Ry)P0KCW~fr1Vw_Q;PqBS!#HScMSo9_) z={n^iYwkF-KhEH_TxAdj-S&!-q?ZEC@%Sl8J26dMUaTIB$Z z=qrG>4zvIoX*+pW_bFxp?QGPE5tKo=aJZ#dbNMu-(`*_eX z1ZUKm)_sbxcH=zQFkc9qxo2-R`V`wxg+9eX`>AoLNQrDWeTrfGG_99}6jrWgk_+!; zzzQ6P5%&{hURCHjbG(YL-PrNVF!n#9L59DG!m7vOBxe$ zP@15aR=}rNPu-^&D?84E4P+h?o&r$|KE;T2)QTF-slRV{;F5`D8jp>`-4mxL2H?w~ z(musr6S&iJF=GOGanzKEY-2S6W2Y#pdIE;q-eyBycmn2hq{)W7N=(3%>r>1?Sy9lV zPq7|u<(E0XlFH{vF%|YHc1zu-7}{J+96+kY_}ddc#qzCHFYNaw|7!K|*x)gzPceV( z4rga66?Wl_kMAO0Dr&{@>goK~76lzv?GPXJB#52t&}ur)VcUP@i;LB`Uft^QYizx` zZe+A+ILJ3;%!c??Wg~0(W_dflg( z)IKH5YV;|VZ^e3XY|Sl)nqDxTYu4Qpv1Z*{Z8HTGPJHde8TfhuFV&H}$Ttt-GD0E* z>r)KtZ3JI6vT_n+x6qZ}y38080nE^HAs-nUn2+bGb*om>QmV1dHPWBpk}(rHg>Z(j z4W_rFqm8Oz4_l1uCN{6+9nG7I;m{)dBBcltRYGoMZnIsML|57vV(=dHqhhK^ow5vs zrFWdVPcc{LO7kk-4f%6Oat1h2nch#g%G0(z>>N-lc2jC3J_Do*xs!uUv;A8X$R2bBK ziWv;cx%6@I>eZ-g9caOvE6w~fuNYo)sYyeeYlyJ5vIEywR&hwBu^lAyHt z@RM){5U(tsV#Ke^neg7aPchbgoCg~Qg}`|y{`Ry_vExEM#ZIk8pJM&}d3=iXR?er` zH!(T~Xyuy|FWEH>TbDDxb)RCagVNEBi?+doGD2A9n}=Vs(Jd_Vjf+n)4Qs}ynCXHc zTW!d4IyQ5JUH2&_txMe7vp&U+t7@NO1yC589%o!VR+IC&eTwyWkG)T^hd3m6lTZX? zYDjr7b5QP5$C)2Y0?;{!=OqJo-KSXHrx@9bQ9M-GrHLhcff>u`gJvN-)p?cCY(wip!c=W63tsiVXZ**;RRQ4PlE1zN`cgEEA^9Ju$ zYTeqXdUZ(^zbz?&F55p@~dTLgXSAzl`qr86Iy zOfbqU-4BdXm>frQAIE#_rEnm}fGiWj3IEIlpZU#Zpjnu?nK3z;RDpf;d{<(pqEIrn zINhU%Jet#gGARhs%FE$pq;bTLwYk~~KD^5J3t*oSu+eX;4+0%VqeAcyzzEU^TohVi zaI{SxEF!9p2Y--`GiDhR&*7vpoa;%YLSUR!#SvX-bJ@8dhBAHyXfJIaG(61 z#OO&N;6C&u_B!gTcDT>&sA6)T-xlCL%Uz==^(<(Btm?D9LO6(U2PWO$OFsg-6L~*i z(@SUa(;w!gC-?b5o%?ibiEVGr@F8~e*3O99-f+?x^U~Y*+8(>@gXol)-h;=;Y`zt< z?*7)95i57BhDyG5p7+e@soqrJLyTRFylFko=xLjIsc3T$$!9_0Wrbu2)`sMlW67O3 z?gD!whpPrIbp(nnT#8P^h_$G)A<|;RM|3vvyXHV_Ewcod>cv6wVT637)v&7#drvl( z5{NNeiXbEJ%=b4zV1*^ir}wvRCUCcKpc!(zi=sl zo=}u*f&Z}lR@n)kQ{4qlwE;L=JDiHPRpeCf8@RJ0)$lmUUyDM!y6X2Iwtg4? z{D-CbD(ye)SDr<-LFQm6p$8k~!!%_T8632MrVNs6qCzYNx!(-a@hjoL%E&sAA=2!P z2tyCxVB#m}QJ2sgy?7=x@Dv^5eUcC91b;+6+^kyeWrV<4by^Ja&FyE%m$hLZdp4lF z2v<@H`vXpgSh5f(Q#N1-K-n@p9cP|g0T&*B@1<}@ZM=@}@ zeEEuHLJu!qylNRd&v5m$0n5^{weCNR)g9--hO>ph`5F9GoByz5>;A(iVqlF7)@rA^ zC+X%o8AoV1qJua`qH}pviYnkDD-qfKg{_E=<89ej$EYHJ$3~w{)r1D?fH3NIM(0HA zy8p18riEkYhDLV-w0by%rQ%iiF&n)rB^C1xOdxtM1PSz(URF#gfpkP}oWeUXnz-El z!+LZ256ic6S$B76uJ&uxmO}?&lsUC9S9?5alsbsR@YW1628!z|bEr1|VaJ91hwYQ) zKWwkE{fF(9$A8$q)$2bj3H?N6{fGU`?5kk}XDvNbbhiIRldQ3t7dZjCz`Q5=m=*gL zD(?2PpYB`ypank6oaWv-W`d%sLev&iPZ+gDwyHwZ84tNMMsqCj%+A1*QB_Dj9Pl5< zAFZk)JH0r+VG=?f?GibFr!v3{`>E;(Vkqj)a4~y!#SK4e`IJH0K$Q%GQD@ z&?ySrmUG^kAy8+eO@xj!&%HDhb1SX@+{9Lj2ZlU#<;p7)9-XxGN!KiQjw|xY<-6uT ztheqzjO`NV!G<0oaNdExYVaSnZ*}_*qkor`l&Q0fqr@68oQYq7Zl(GU(|9C$2j@Smx9&fT zl^o~6hCpAAT?P^8BBJ5Bih!)~fA|6x5?@lt93VgJ`?H?=0y&N$hzvQcj8I6Z3Sz*<`rmyMz2 z?mH1jzYuJ_9<*R0X_=mX$i>(FhskG$DzQO6I@Vl1Y%Sj&_!8ts{4I6k34^v&VV3JZ ztheqzj4c`G!3Hj+mp}=!?mz7J$A4I|(*DD4g|C(em2OgE)RuzGJq?dar;68(qqoJ@1Q!*filGw?06j4u+WM&j?|VWt&+ z?DRx$?-=lGCEc_|>iVY{Ng;{vo!*Lcq zGsL|JDsLpb0HXT*hjG@X2KI)-N&3E(oGRZfY#Cgo;8T$VJUTd94pGVaxRh3T3XG?X?KD&0Eb9z7i zz4lsb?;rVpD+Af2t;#PbN52z!mt`QEsiyf0*89hEBimH{b?<%kZ+koI|Lkq8|D{8^ zS=>o(6rP3pOkR9gS05;IX;K0nZwE7T`6qz1)O56Y%x{znWS=>2gvDSIvSv ze$5U0O6IT%3fMvz@rWbeLA{@?2$m$vnR5ewzYCue!5o&hN}(KqA-b)gE*rO-p|YY%wbrsi9%a~QEUwo<)h4zqfvbXi2^u(Y-6jj=UZ3YAu1%L=<;2JxSW)#{;j zHmgwJ#MhNL17ElCGJ8)#|3=7)pi(GS+Bo^s0jz^n#?)rqiY|$?v5_*C~-eHtYTr=Riu(9O20?A6&1ltYv4{0-V*c)QHaUMU-xc5At zS5->&pQ%a-&IZ;jJ%N($t4&pmE1APk1B6f z$sEQ~ukfIu*vw&{>_z6Vuy4=VC}v8ws`et#{uOErU$d1;r-VOA}~y%WnEwyx03 zVHqe4oshrRTBl~<$;@G65Ac|&{`3aiz z(wdt)1=Nk#QZ0)>_XNV}@0nqVGet~p3WThe26*h z`TFNh{SuhNmY+1tVYT)%hyBM+ac#fB?F^BzsogAI0yr&MVAfpt;eH*17MqD&qC36^x z0^v+Ksb*{jSMgEmJk2AMA=80rqMk0*b1)fN=V!1nX-h2S)=0{IxUx~IIp#1Kr;e97 zYz*EmrerIb!(5f9mcYg7S66)Iu*X|q4*Ns_nZv5>W)Ay{kVm#4vxDZa%V6Hg1U>R> zazIZ&n^>^92z-b`N;mznRXx>X{@C<$jBBW*Y|UJ;!!K1t{BW+uvOsy2<_SQ#Nq=kt zVl(y&0=nso?LTpCtqO*k zb~A_lao~$B4l6)abpa&E=EYTFr{OBK(~WSof;_}uu5;;>C$5L=^!%7NY!Mu8F2{Ss zdy#caakydEwC))6H0z96>I~Yg83J`iT@qZHJok=B%44_!aJP>+j4(}X$H^Hz-+kxZ z@80=9IAy~i9L9R7@StJDA~+w#rwGhpOA5{$2LJUoGlvD#Jo&X1 ztU&3=-CutAlYBVbLa5IqWZ3N0fTak#ww>nQYyN=}1%rU$)ri?UyJUBWx}sAyi3dv+ zFkFue0J>&(&vked0V(dsHpaaw=W7v0$I^D1tYQz!K#On)T7>f=)b|9>QO4xsM$t37nQ9ofU6e0||JUj{uqe9LOZd+Y89_E)*D%>2jUDnn+zix`kUTf-`ML#b*u! zYuM@7ZKB1UCc?~N)4jzUHjEW7?Pd=9=VmvZAb3*anWo&#m^!$wBi%^Wu8bfJRRRDnux<|-!gpK3&18nvR%m?cNafMZ@I>G^1vGH)xH!$8@H z(n#8FW6RbL?Yvj@i-hh4eLHZB1ASD8eiV7)K%ZZT#%&UI)0||o3v{yGi5P&sN#-zu zH9?-kg1?%B7g4KKWKH^-+L-zd2y&Y&UNVPiHF&QeQat7`T9n8fwxmax!v;IV9QKTe z%}yXDc(zZmZ~^Mwgx^OHH=&jBQG5_e<}lTI(rgpQ#O1D#q~y|Qa|bn#Xg%MJE8<-) z=CH9Kdqm9u=CFxmY)g}0OXe`G4NB~0g+EKvc%ly$87aZ0Odw5!GN#nPrRBlC-8Ja~O-Z!h?n_7QvZT=jpzpF^4^0NanE6&S}&Nauq5U z_n`DP^0EcyFl?0Ow37K}s|)c&o2??M9k2T~XfyNBMkwGYDn0{(BA9ttS*WCWK{RZp zirkEE?VW>+`EAhrZQ#|x`6zW?fU{1UW?s33thwUXVbC}>5m2lN8$m7@CGi<(Z&QKcS z4b>u+l}BM&Ifyx!6hkjqz^kYtT2|iB*`Q4dD@eCMVc7z4q!*aO(pITwv)iPvQ@5Su zSPtF5Nqt^))eb9*65$}us57psYk@fo>vf2ZV(btzhf~m*;iDyO9kmjokKgWAN{ZyO z9jOKZ-CwCrc@d$yjYtAz%Y4jXgipdOmQ@C(j?{e< zkvX1JtNjbRV5{--4 zx&v2nbZv*&%ExTr!3Cl#y$dmO_Zy^HN%y)>J;h>tu*=CFSe(~XF{g2E1naUdMy zBQd)!nZv@Z6*z?bNHv9BD#>Z5HI5v1SnH(0BL#3wZOTq(9WBUX-7L%I!|ulrtYeI- zP5B+)Kmy@-H==}NqGmHI(3vr(YY%k{iOgZZ-Y_036j!R%v4~dn8$jiofGMJx?*&vo z8-+?#o*ycqgkm#?eWE9s!$Q72tO825s3(Xvsfx^)AxH$-mvQs9f6y~s6=b6JkT{4H62t0@imOU&=<}fyP&s#1h z6?GrNReUg5t$9QNkUSV%rg;Jdz$Q)M9YyhQeI(^BTyc1?&X=1xOhyUnYMWsW8yBXS zsDD+-9A;HQ3s`S4huLnUona39S_X62*Fwx;UjuX4(_ju;ak4On)kfRT9QHe%d!+?@Erd)OTC^DOa>gyM)Q zg7=3uEbMb}Skf7$MsX;r-k$(vpv0GzaHgI`?>~d9_$YOr=8?&e>A*BmPnYUBm<+A+ zGuW84C6;n)B;`I_aeAbTlTDaNZHzh2kqZ8VrerIb!(5eI<5!IAm{@$~u%B;%Iqc)b zV-Blf-O5mHg)9CwIMS|4WdtOPZM^g@;6T6Tj*2} z3%(!n$QEQKIx`Ta9aQHvvCFV&)?a77_ah6+=tsW#`9wh!kp*b?p>qVW`SaJbEjaJ zm=nuw&o>uM5ntZIn>CWnFv#t3uRn_|pir{!i2J1vDd z?2O_vhgG4UXfJcvf0A7_L?IzUG$C64JN1Ocd65Xv85(73NS3$;wcUFg&Tr8;PXZs} zC4PoW7gdF+EvTLl@j9-mFtMBBwZ*BbusCmL_va+v?!&k`jyP3CJin+j4(~9JSTJ5c*z{bda3ZBVZO`_o|$~J5k9T=874IS$rOVJn^KCaH1uPuICo* zo%~`GPRo(^A2h!WdOwbI`z?oa3#`#QHLs=dZ25KH+?8)BDs$M-M7x>8o^W$`$bY%z zJ{DXOIMEbk;6(Y(KxMuu%E0MqKhF{`>=}S$|NfNe>^_X!mXefv>^_KUev|J`tfVGo zz_$tqYrZ0>ZNgX9XoFnVWcin+tpbc1o@inMI5oKwE>S1~O%9pdqUoq7a|UzR2tCQn zmyFC|f40D^l)d0fb`=VYzGQ3h)(i#;6?Y|vTS9T#j{Xk$uh;yBE`}V;Dw81j5p^fO zjGMlw`K^+}`OP(vzaTRGxaQ@x1_U%#pTZEv#v zI%ehn?7gr4m)_S??M?w_65qTVb|?RdKt!x}G2Sp%EG_yQaYlXJ&CBdPfczUFD}vhe z|68+LP7pew?o88cW=x#lgr~`*c)J^c1RAIbGf;>wudX27fR*+q1H}2ZCMn0bl;GR!t`p-fC+D~>;_tKOt}-}fh|(o*7|XrFg9a|7w?O%^PQXze#nMOsv(-+{6+ z$qZ2qQ4#u4q{fjxzX;8n$9=aZnd}0QekWo;`X+h92-ZY-jtf4>^CAP|*9=v$S8)(* zRR{MFO5R;)T)B8;RmTgE#OshFrM2~fB>q;EX`|hRR4Q@x@CuH_;|-%diM(NN=?&hn z5$w}3T3z7^loddUnSSbhnBnl!yMz~MKCl5XRLm9jiy}5ViJ0KoKDELHcq5a3A3NE($;>dBfBIM59d{6PLR}l9Ef4eg`#==sdXrJn=3UZ`gQ{J)&e7SOd4~0NJo# zWo>X`bOgIrmb_tF>M!H`IQrnf(?Ksu%W#(F<%u3xo#zds&88Q4!)l%34SOmAY3&0v zqOSqkG~xzmjH~Ic#pUsHg)23J0yHLEQZJWJAX0sV+M*XIR&4^rryaO3JQ@Uzcpw9GOy|<1 zI65%6wA{R5<34W~Wwb2buNjOAY8K?8>l3(q6+3#j(r%0M>LNAow7qr1-=Mx>)g zGy&=Mq5l23TUVgYo(QZPZ$EF?uNv63WQb`7@G2-slh!(Ad{Ia!wDE=0k2v62V;8_< zbB_aFJB%;7c+zK~vk7ME@=2GIN;sHK(jkvubH}jxo;f9N7;4f5;z%#>hNZ1h&*rvC zU!`vQ$gvQ*fs^{Y=$aiGW+@R;IfK6UeqLs;QV+kjS+ucQhv?`G8EWP*6Np$fTG7@~ zLt)m80mMb}iQBL#%+f=GmJQ}(oDM)~8(XJd@`hRQQ@Si7Z&=z&^~TtmEQLxd z=;m5=|A|T`8m*x-w3DK`42{q#WEaDz@%GS{z;5A-3{i8+dSm=t|#0C?bP))C9gx z-IxPm$$+Ectl3#g-Y~5Ir4z!0i>=Af$UQ(Z3>`l|7GffBT`>?U7x+3th zp}JM-!`MBf&AefMFQyw2d4a(A$Ag@mdD^A;*ClV5^$>UN+S5xxyO(s)PZ}V~{>scx(4^CX?5}*Ss&*+tQ@C5?UCVXx2=t)R6g7(R8Ip2h z7styg1HNN8EY}NhBX|f`_O}PQR%=xJrjiGP%QTOOy1dw=DZHah0r>_Jm~t1Q93HIm z<>n2OQKDJiu!)j4jAdWpLBk%4;7kixZ}EoNUZb7i4Lh2_8+J6r8+H`DVZQ|4unSKb z-mt;;^M?KVPBOE!u;A$&G;CyE&{vzVN#T(YUqfeYSY;mvfhGDP3;gRtbuHih6BlYb2afXiL zIbM3Jc#*b-HcY{Ue7+CKf9~YyMCH9Rf2QcbGB&H}#3)5^-$tp25w}r_adYAek4y*r zJSA@!iUQ$0Ib~WyFV#H3WN4kH1e2jHv6NdQDfi)u)1&5j!)%N>&XEfKgr;Qk*9#A0 z6>;KT2t&21tS^?m5IzNq=~rMIl;OS?_Ci>LV&+~5|Dsk(Jw@h8swHsMGmB&KdBdJ) zfj8_4tX(;XzfMXZyh@KPqMJU0`aF0HPPCgh?2khp*@DbOX9mKwgX%<6MFvdMwhdg2~xJU(e@4`#-|SFYF-X!Y0Hu+8!!Z*tOK4) zljmOHa!4-UAKRLL1AoB@wJ4t0D%d#%jCgvBq+^IwOg_eo{PxF| zW+AGQ;R+}FD=dfSwM!+l!M`O{GPmFgqOIQ?&A}yYNuhvc^VnMQhOxLSJZQMVA~?T* zPtkb8E-rb)#3Q>_?F?_&pV*E%ip!969Y*6YKceetkenz9m%L$+Fhku*qn&f&*@P!F zl8W~tPaM75B^C1xBoMu~BMS6xk~eIk72dFkk~fUyUEx7P(Rjl)M|i_dkMV{L)j4(~9JST71 zM9CY*da3ZBVZUQSJZ`^y|hy0gY?qj7Tfzwi?8#tA`Vb-+m95p;~5*!Do{8Mb2m;g>q?u0v$um|ph z(B721VOCL|(DX!tNz;=70L}=|dC2tsNz*L)Y->pejkqgYT z6EPrtle}RBYoa{Ig{aV{Qj7;QE^z#BF^+8N%k&qN@teSo$Cm2H4Fjkp0C<7&DqdBY088>V=cq%$pf z!_ZbEv+*rV&_J8>bYIbU!;Th_H!Qqw8r6bagUY2nD7}rmY=Jin+oU`JOo?Zy0LQ1>#6A@P?(W zQP1YKNnfRI`^d2nx`C7WJn)8v*6dXAaH1q#`_T8es;&jzFs#-gIyys!nmNn_B36x7 zv~^ssXx5AY#6|MqY7T<{@m!=ZTk?jvLU4z;Rohi^kU?WnccEQKjRR|bcOl+9ZtI{E zkp#+?`FO(!pM+T~zYI(rX}n>~99ySe@`hRIQ@Si7Z&=z&^~TtmEQLxd=;j_E{u9^M z!mDgnp}>i+D{%(CZsTPuykS^pWBBTj)wu?#S-B-!2>ZIBYf)CKufaPZ^w?^3SH<$? zp<`5R-GOi7=-Ljkm5)qZt?oC-hEsQ!GY7(w0cSpM*ht!bOJlMPQ$_Y$`dRF^^g7(J zWGwH6{g$po`EtLdHFP3FFz>L6yOIOPGYiyA7N0jvy*U^Ei13CDVfT3eQ7BTI z_TX%dH*BKh4P%j4c+fCm5u9oL{wz@Z+uAZXw`5?musGFE7O4I1EN|Eoy~rCD_U${+W0hj;e;0wm4bAhXFFrxzqm+WRPJzN#37s0$T6 z^JEL{8UH3e)5!FDnqQiE6w_?jWB#l0xeR$nRg$#hbgz}ZO8e{h-fZ44h2s2~LFk~L zF1#~8$uCa=dpY}nwR`s$xr4QOmdb)Yw)=RvSd#*e?qNR@L63I^==qJj!RDLHC){DK z35Kb|v{~8|+ef}(csM5RX*|N+ju~W*{YfC-F#bpyK8X-t_QHM)E)fSJ&HPZ&gs^aK zd6M!^TK--8_F2BH^R#{$)=)F)z4-9{(;0JYS|%(UL*xtq%oj9&67ns#%sBrnKK~K< zPtmHk7GOxmtgCs@z!tDs?`>&3TmHUv#J!^{`@H{9U+5iOIXCy-xr0lO9r3>R<~gtO zT7AG7xixZu_O%j!qHjrAE%aQHXy&IvdS zeNV@?M~>jIJ`l`dSamZtvBH%pD;@Hq!{OS5oAo$R@)YjhLr?6$Gq#RbPDeTnyFKhF}kFQTQt97^ZU>{-NdyC>r`pCh!)A2xs= z69EJMu(t&%YWBI-PYL4=;U;MfW*BQ&fr)uS_`+_PlqZZS{OcF=xdw(JhPexpYa3uyao4uNb~E-9}$@6r+CmnY2hV(7fa*W?%%)e*wXsk%>H*R!tub- z1;>^iT{Klc;vHLhWYJDwIC;jOUHZMbU#%a097_5N2~fkb_+E1`LVARmR2uVU89K24~6al)3R z??zk(tL=yxSVna$6{MSvpArhjGOr$PEr` zu8n3X%t*_i`-Sg);jT9C{NQa!vNec`UlE>nM=1Ux;tyja+MxN9Mk0|S5G= z@w+frxBx`P{KHK}IG^AgL;mHTTd)z>TwwrlRu<%YeV5x{tYZ;B$C3JB2d^GQpT*I2{&!b32-Bu5mW+n z9Z#`u3`Mn5zX){wTu-6vN)#W_^=~uK^*w%p3%C8t$iFZHU2R&)pRtQko3$qcU2TfV z{6yFP&;+`MQPry+Y8g#u@jQ84SeBMXU`ms2NYefj*A7)j0zNTT4-xeuoKfnxxVLo| z8Hg$ZIkF9 z)n=4|sB}|s4Yz3z?J%8~kFFzWvg`0*MECzR(DesBg|3@Wm_*k}MLz?!ieKa?>`?p# z#EZr!c3H_M<~((VYGlwIUg4^X6$@PMpTxPZ|6M$K-rYDgkavyg2|0ai{!YM|?lk8i zJ8)F}9+rv|mFp#+Sfc&4b9P+U3|w7?4^d&5=7BhPHzf>{@5}w#MBlhDe7XN%=D879 z0B>t$8PL6DD>6lQWCWTcEm>0@CK2;-dps4lxq_TQyncQIxczM)peS#8K~v6BC2pUW zf!p`^B`-RM?<4=1<`>Z=u&FYuPWRle?!xg23}FBKxY82NzPP91pl3OLNA@FA`zA|Y@T>8RmGJoVy@J2=p0ATTsPlUYqu4?lVN@^&C=PR2UqP9}YQxobGl%`14^DYyJ=AR?G%ZECK@%lw8St&b;mvv>(6k9x z_Rc}BrY6(e$=3avk{4}AfF{CAwy#;(WsG>_)=JOYVPYt4^~=yiWQU250+0R*cqC}s z3o;XnyOI8q3S$e;BNEnM+FaJ=smy1pZN^z6U&Xxk6_g5tRc$!`PsvyA$noWD%^OPg zJT;hT?69)0q=SO>`Y@l#Lmxc{T=;tTsU_`)9VDbBDVa?2QJ z7%P|aW7S@Mn3vhU!~xfnD}0?Hzb^VqnInsZUgyQ4zI1jbPLf5UbKb+b<+?ZFi89wH z4r|y3R|>^;{B@Nq?-@E;9~4k!FSMQ)WU_vDDw5LVy=Kfy8~s}ncyGfMfw$Q`CtOCF zmt4em>2+68_2oRI4pW8&l4H8YGUD6&9FY1#6iM$O^$wIPk@{gpM^hG7kZ$1`i{Lzq zPstf}vT%kCjnvxB8TO}6?@6aCr`V+a6T!!D;(Rj7OCEm5e|d%E^U*F1=PyKD#J{+s z7PUE)CAuLz)2f0{XyJJWUeNkHUsgg?czzU#ahz{TcqXTp`?V=DgITDhjLIWjE`J}* zCOE_LGKHB;E!s$1wK10Fp;aA^*rHwpve$u;y`#5$D@wGHPGHh6d&ts=7mq27HX|~H z!ELEtt8*2@H}Ia)V#A(S0gF<{*MWx@GDIH>jV4%iMyo4av9bavC)0e15%zlb-k0zq z%?B%bH{?W6VR=sWW)oNiKIV62<;|oQM>U-Evo$rsBZyOOqlS}l?VBZ2m})rdD3dr6 zE@y!uWJ$b(k_Epe?$N*lX?9+HXPDjTF%{%CbB^0pXwC2-^qN8Nku6PTtx^xlAXfIT z1KF7;sfAM(2XrC!QPgreaxHCLq|1$z;?SnI7uff?g;s$4os|R?= z6Q*!>1Ii>0XUmYvkOgPd4KoOw(eUHLS!3O(GkOb}QMnqPfOB& zCX@<;RXFq5Z_P%>@2M;OH+pYgTd@2ySc|j~yC!UOtCMc3@AoG0;SLImyu-*WKMl)f zKH(B?)eWb3dmwg53+k@5}il|maR2=Ju z!I>M}AQYM^jOAoq!M&|JSi=?tB%8K1=OB+Y<}CbTBWDQKaSls@OY8TDj6gJNNQO~q zRAJ0VWg}&@G@>vf+dh16YcNett6`7FL}aTCMs$lG0kXZfr;zPz6e5xB6-5)P&I-~k zunH|aj|g|PeNFQlIvMgXpJ|{Oe-A#B$h#r~*-RVF{H*j(>AiVv!S0`oY*X-ze4q1> z{AX`#{Vx^iX7OXWRRrl=1$T4(k5BLgtb-4uF@>?{iFIe;j1s-tz3oN3NSk~5H$o-^ zopv5Juf)5Bd3}T?iQTyJbCgpDOZbD=73 zA&6?Q_AY?O79R&ZYvcTjTeY}QS4qJ08*qcksLR+0@+i%5Yp~d=^Px1%8={=YAam1? z0rO_iyQLI*L7JnZ1Tn8qG0EVjf^-Y(ErK&~3)|yfV)Hb*F95;%uJs(Q5Yz$Q+`oAZDu}=d{dIw{P zX~funP+T*3tN6t(vY}m4uKZ2pKTR<+31j82mtX9}=?>iVt_+N|F_*vK`}{BV5=_uA zA7gFpxnOJh>hoqWbr#Q%M~3B3X$akvKm8|S{ds5&4U2@h%ASCdztz3%MZ8FpKm8ja z6GE_xMkG(#koDtEVkK??RoTZ4RoU|!p=t$r2Jm4Ap?E5dCoY~E8b0IaS>hcE#Sv9} z5%JXSL#Q0&mza+eUF|+hFgz+Is=7MnYes@~BtcbnCHpIaY}R?wP?b5GaS^)Gza?>2 zSD*(CDFatIS9ckkUV$EV;0&~qsTdozu}lMFPd<*Yx?lXBN3Gp<2)ZP*!x#XMP3#ELW{$A`+^o~4y7QDAVWCda$u)|^!nh0~qnjj{ z%T_tU#Hq)blAM}gTW+*uElZD%T9H;D-IS`+h*Q#n@I5t+W4o;272FHqN0cMX&HTym zg&;Hkb%+7+n&k*n=~S7)YJ*{FFtZJf0LBuLtX9R^AqLTtejZ4+6G$c#n_fUN`r&d8 z{~J1HA?iX!&pb_r;>Qr@s_Ng-{L;9iJ7w5l$DeJ+X99Vv8FP3W_?VykIFIPPd2NCB z{GrXsp8;>TcyuS)zndnO;Vot8O?T7IvWBnc4S+vi#6j>)$Yd=3LMWXB zp`|10W9FcrE~H?#-f_rJm-(zoO+{Gm$a=Nzf~W>-{4(!m^S5`l9G+(lo+Z&dDOgl@ zsjiED%gCN&3#>U-FhnuqHaXD29wazPH4Bm9-cZ^~?UA8~P5k4)z18?T-|GIxUcfzi z0TcIrMsdj?r{ewsIY@VqIB{*8}%>U(i?Z6;#83P_<)=5{}y~`j9P{x9o&-)QzDIYpAqaD_dcyNg0YWL zqzf3qI4o!iM+O8wLsCxccK5D%xi<yMb1+&p(1hf1^sd;oTvZm)t7(Jdr!N?Hb z3!?{XlB35TDq_>2kfGv^a@Z4!Kacn}RMVTa`o*{qm73+Rmmkr1F@SsDqxr4Xm=w%h zro3mICII?p%nz17KPTA59pwZ&lEDaeB*X`H1Z-em1Q*!KlY|Rws5%^Qfw2)$gTZ}5 z(3YO&W%l}g>11YBv=QhxL=}utg#(NG&w~y@rvH^O#|9pkRmLYbcFEwRH;|v|jq-cf zhIzm!rP|!$J)!tiC{8iUEP;qBL`L-}6{MRU>i6|sLdm|CEzJu%%Ki26 z7T9WjzHrQ6wdzp7{KbkQ-mk_P<-d)W*?Vn=Z7Vht`6E~)T;N1RW*}}BBGVCa_|oFcD6Oe~iodh_ zFka=CxK9m-cz)=7=eS#W(VVaO=JBTgX8t7z0?IoOvp&RB3D$$MKzWts4WVJ+Qwc*cwyOI3-Sg zB@KJI^!@Fw?>EBL3i2DSQUPOl$hhI*(|&qu1Yj!I^_cs$t6==)(IDtyxXK+`xDs4#Qm}RHt$A!EIn8_tb_6_MiJJc5D8J$tfvqPW1K16I`Fq|A zi2nfn{AR^UnGQy=)y7=@Y%e~~0={0$z*ZZ7nV;C2wS(@lrSDqAU38ya`n|bze{=Ze zx%>O)R+S83&JVjrX2wo1fc+=iLq~Pyz+}q3Jj{B&z7_lTP^u&<|FucDuPox z!5|)vzfNsAuu7CUyXFk9FD*H&b!~e^MP>6hI{thc3Z@elS4w7 z7R+=XV`;X~YAvz`eHQ3`^09&ij4~%;k zFS8vbea0wc^%WS8Iw6_DZ+>kBZzB>|)GdVOBAH<=ab$dy#qg3PE0`+>(dn2D;%cPD zrP#N-oMNh6(8t+jJXorL;d*2M(D`-TNO2pZ1#{l!+?{g13_1#*@51_9-sZ*0A4Xw>lSYMn&EJt43iNordEx>+j^A+Z2joulb_V^mw{&lCU z+Fn1p@~s8s1*_J;S~xtqf`5wx0OAw>P?Q<9VGV3owlyk$ZTi(WJos@tu`qFBp5aNr znK_dhDoD3*i$!pL9-qHM{_8cr zp-UKPO!v*7QFrpoxao_U-zqtr-}KLdKd&uV{^l6MzFGgu>0k+4{OtbS^`qXw z{nfeM^%?KE{Q+Oh%oFL~J%ychXRx#GjQ5G2Vh5`YVZDp7gRx?XiW_l8ebKqKf!#?O z{(SG^KNsDm(^?WAoo>@jlSPr~(s=D8JEz{v3!p{h23s!;uh7oGu8QS7Lr3d zaaq9HjOB@MAc4Be+Yu%BHo4b?LM>;s?kB$Mue*xsGZn~#)rw(yFhl9lbRA}7wc-Jw z^o0PT-a+XdC|RO(7CYFDQW5Sri(|i~}=Xfa}~Z=s^9Z`VntieG=ci)9oI_ z`0I!-@(!Z>WF!px6c`y2i?|ye1^T?TwW0BLvxEJu(}Yssb*fIz$q^Lfvru00xM2X< z@*@5DD7iCOe6Vv|h@*KRFhwMT=={DLBDD6KA5nHNmV8u%W=b#@HQ%jCCcD6tornSH ztwS^tvyqP|pJz{@HN!Q}@G^Z1(Ns+!1$AoCrqUhR}Zh?SUjFE+LOo= z_ST-@39Am*I>Zz9NfDa`V1bnF(|KNidN;MgBZ!OopyUa2ox(d?PU_D}qm9it^$VPq zYcxyx9n?Ic^L#h1h<6`;aLZ7wY0YPlJz}I8STj7FjBRQ1YnAq!0NcI>Y&-dw!UFGL z&wCl=T|A~R+H8u?6jmL^-a{i3D_jHSWRO|_PIWMUxQ>_EyQE2@H3gcxiF%-ZJOXL$ z12n#=0opX;255|{>8@l7Q$VAuVI0twA(bHu(AG#6{F(wB7v1=PW|iGgjC1gpq%(E= zJZjD{NsTs}M4f4MJhH0kexMn(k1`kN1)VANRh*4eugQR@3l%-{v?UZjiug1#&1(K6 zovG*|cR^42^9$9xOF*#|eBo2xpwb1J3;VZ-ivV6IL6~j4!%) zGH3)15s!poRKjIK9>3-$ck?}ShSFE4M=UFk0`U%_Z%Z-sf-F}>6%p~?P?RySsUY1# z81aZB-$8y`gJbfT$y)r4NV4+lT{!K_@N1i=4_50qc~A}3PC4h|P}b?c z{F7U@1F84okc6ogzsJ_8yGllBMuYV!0ao^^IIvnj$^zC^dfPyfjN3W_O%!EIg<5M# zjer*U2(wsJ>D#lBl(G^B-^A9b52aZ+K+DkA&!+fl@b?U|!mbOy8F}5a4 zq0$P>@uo}YDvN`$Rz0-Jh80A7U5PWweH$;ccO;Cyx*;sq**N*r*_3HlX5@I#m3`gN zl?cEZ%Gw2_f^P?y1(FB_Q)xNz?E)pewbklt-2HovEX-B0ym{zoy-3h?2fm4;tM!~L zbZsQI@{t>OaDnJb-$KmXgLc#ezRD&{O(HCLZ{}$xYw+1joWBo6?JPeFggyD#!Z@B; zpk}i8Y+>rnIgswLndQwn-}h&_;A~;FA?zN~X11`u5YvtN_hdM6s(Vjv{u`?QOjSy7 zHn3(x6DaAv+Em53DGGR|jR@YywrM)C+lF6>7m73x2)_*}@{eJ#-79WUE@ct-Q>(gGcG3TrsIZNnCqqP!f^0WD64vTYx4z zKdj!hZ=a>HbtdK6vh_nd@4Z8EajaO-$J&YqYw{wbveCzdRBPs0LaGYxii&h$2jWGm zyAkXmw?U)vhER zk2_lc@0#TebFe17VbTN@8vT_xE_MD4yW|bCiaCbJiRBF&D>QFd1`0zbbb@%pMqrsA zQxD4PQGq@Rw~;sOe{xDLLZqCWILU+9p!`dbGu;=0+DJG);4XQ?O5QLIFERyW1DC** zyAb8@V4d&1J0JYuJ$rB1v-i$D`>xyjfjxUo?)~7Mcki+I&Rx6q?!iWMbT5!mqFLUs zs_?`_{i{meFsl(-zc3i_flq4k zH&^dM=(E5QtS!zw+) z8#dGl-mw3*lcN*oU6@gEQdNXeYB@TZjZzOIZleq1=EN5snGX1QmUu@(aYX%5DzJL? zISc6h{1T(oC=Nv(r5?w-#Yd?#`Q8Yk8Jj^YK1!YEa>!qnwo}-pnkTS^uG19WQ6@uM zVkx&qQtrbQr$@>+*@TJI#+c(Aso?EmO16rPR3&ei)y*s-#pezCL<dJO;E){TeMWP2OTLa}CNR5MXNByy_`8P1tR*|o1e{5!s`D2qUIN4jU^jW=v%$s0xq8xrqCXL!TDD{k2W$b!laqjB)9 zz8cZ>G`LDc?2bh7kqFQkc2D{Oir823hFQnz9B^NbN5p})j4(}X&&eBBb=z9bTPZo3=D$9VH*5y}>m_fP%!Q?Puf}O5 z>id6aTeIdA)|Hq$FMn|{KHMi{ez5$;$a7Y)dBe!d(`MeVfS4!0wt}T8CExw!hd(J* zS?J}5bVZK`YsUhHY{}MogS^&uv%rvTnnA#DJz@a5W_QnZcw`QSfwwvLs+_+&(P)~6 zb{=ooL7-I08)lk&)(qzmo!|{StFXLb)pqlS{Y%LkcJEHMB?OLNNh|zXTLmZ{5$?vJ zgEe0PCpO?XIOU&WUxE7ooSNJTx0I%r(?H?7I&Hm z_+_5xE#9yi*1NQuH|$TF-Esm`XR15XG@BU{=e(OvRL};^&5E`t$}Y6=GhTIZZ|Z5B zCB3z+D=Fn56xtb>uDJ23M%40@th;QNGHp}Iz5Mf?C^4iSr zZ1ndnzo~xEF?AgRJJ(44`ud?|JkGrK(%eh+!*3j3+&_2t=0i^&{oLWn?_!Pjx8Upe z)Dt}J|7d&n4(c`Duv)u$!~W7~LItqRM@x-WOyocHti@S$qRy1%(lrAzd44JZ&w-Y}it zvoO?I88LIHon*2LOyNWUNZ%xH7{Qt-pN}_;+JGRKuWZR1rq$pTlQ)d^B=Uxx)f>EF zL!%wy4cl)n0ThTG!sf+F*0W(2C&{AYTjE`SxMAWWh#QtM&P4$TQ_taGm^c%P|7s|X zsDFR{&hEo_1s{Yd?q+58VS>C*F}7Ue>i2j!Ta!esP{);FtO5jDgNn}^Mx>j?n~J~}UL_Rp zF7dDF24jQ&#I@BC_%{yLDE){qORPIy-motj*tKMcX$J5rcv}O!P8na+DW%ZH7fwGg zD$NT~;|r&a@#$wfj4w)NhNZ1h z&*rvCU!`vQ$gv!{fs^{Y=$aiGcZre|iqQACs;&jzFs#-gIy%FKnmL?;&I}(dY3sON z(X1H*i2pb~St z`DJ6?Fk)?No%&EJt4)+QY(KmpOWrUWa9LkF@aYC`SlUYU#@L!Hg-R>v=2~_CiEAUP zY}h%7uPbo|zHZ}XE4*P?XJh#4z|^@01yTZoV;NInK=-) zDZ(z-=EURP)IYH97(__D5ixsbm+TJ9G|Im$4HfD1$snkB6=FcVT)bh#FVnahZ&5&m zwf6CbeFn30Ovdp^#I2Gy%(cMI$$WI=L{FF(qB0+we;nPSGGAAC!yK#$BaAdb)qnac zxm~ImjLb{Bj$ad;6??0SPLm%=TRLVdx@%^N18 zM6}#E5X2DpMI7nq|18@!+yBYSl|C+hpz9$r)3dOlqrWpkhRe3qOK~x3lrct3G&@?KH zSMfnO?yUmu*87yaVS%1`Ov(gD8)m3ykzgtBvjmstr*XxBhm0&v>}%j?AtMKM&+aF_ zvxU3byz_&%O>Obhusy28!;=^2q2(SWZZo_A*`{vzVN#T(YUqfeYSY_eB)!?0K2 z@Q8BVKaM6tJ^Ox~q2qXtm)~d9xMqyYa2WWPrRn`IbvgKJ8-dnoN-#=oiKW~cNx2VKHcAQGhuHzrJg;qx zInI#^{)DDvD|y3Qm0aUj3|7`5UVPrLPqx4tw!eV9Vbyl?hJ7dGkuAtfbY^g_D!j-G z(~Hp}Y;r(PK$}>w(FlCVM1hM7>4V)3e{7p@aFc4jpKTXza8^uy8=6biXy@Kp4pO#e zjNO4m`zwM>=V~+ylqnl91fZ+~o=cPGCi-I&5a}}8Xqte0O?wO0kU8d$UGj#x3c`Wf zsBb`i>(^Ztqzy-HxFS@@FW!$+=Xt}@R=Q;Ih7nacW=Q)AuLzVD&`n=#|A}j>ha<#d%59iQ9Q9#uq%1Pq}#dUJ2W2PYFs6=!Ou^D_!eA2wDp@~Gsv2Q zH>^fVoB8VsM`|gYjKfvzg~K2_HhuwXU48)65p%YH5Zj-rXB(tsmNX?;SzTO^EXTlZur#f>weoh35^ssN@Z!h=DbT zL!IFb`#o{X7C~2}U5C*)I7=`O8qxJMxJs0SOWv^L4a+|Ob+Gn0_Q3XSYR>*`eLCpU zQK>k2@7;Du#e4$^L~j~HfZhbzW~5@|qg0I3_4nL&_Xlp+d2hC|e1O{Wk~fUyUEx8) zgBHP=^5pk{_+uH;F=u`jXlZ`}P3S4jZ}TV4R86ver)9?ZVtoEF-sIfOmido;^;`G9 zH^LkCV=>;aQ*-l%otnZMHc(*RFz6@R%NzEp?5YvMY0A<1-!#b%t9g+K&>415w3(7O z3}p}wVR5a!zbd2)jt8wZCZ`j!d=M4id zPn&te0%D&0T42_NbmXX82+c)iaC-=Gc4^osrx+h}aqqZyZ7X@hD6udI7_LVQK-Vm9 zn8PE}K?L6BC2tr@w8DdiKwmC0=mS8hCo@pW<|zC*=MbIX4LiH2ykXUmcJqe)eaRcv zp((Ziw6=2pWX)G3H8$Y5q?Uh*O%oHqsY%|jTEZTq@f7{$&^UJa3G|!O&~N@3 z=7AzX^n!kq?tIj5uFcSI-r`r9*p7TEXE$%cC@P_?-Z}EmzvEHTKykY-mvs+GJ z-b^iLnr1U&;>-<#%}JO&$LvyUc1coS1?eXBb;=o-QVv3)x2|O0jZcBiax1`^th@Xv z_s3;T3BJwlIw4TYIc{#=uv*C*#&WOlpn(hNEl`JfA)3bLGjy0X z0P{DG;#2a5ZL3e#Uk9VvBJUu|LwZ)&r@&~ESYqASJ5!&xwpJT$H*eVg>olPP*yc;1 zHYz6apXx)!ZspRPqExS4mfR}R^HFk!^cN!D2*`xZ;H6yiTY%6)gv}Rt$`SCu_`*$+<_;z&84$We7mgeQ@ z27Eft8%CSW%uKD`ziN^9BAzHO7m*NM12OFr->fTgV)&_RtF`gY@P^Gf4XMhEIJFDV zR-l*+(54YLKx14@cgMY38U;y&LhqJl6L)!4J6barA&(6`4rt3XGfOUQ)zlizBY<`d zu6#hV_S#U4vvwANGkO%2ykRWe3J)5#SOjO-^Hvr5YxV9SJH;rmR zu0iF}9+cijUbes+hHcWES~9;w&q6%WW~+#5$BRm1-LOEHykSubH0weK23IS&dBYrD zaYkCBjF!b4Rug8Pk~fTHE`dXb1+FA2K5rP2jvCPfq}zx3caFCFi@E}J_C)Z84Yr>* z>~jWoEg52(0lW$d%A~bU8DDg8E41;2av4UYdBJ2jk=8hEw81;b*bd_hH~)wH)--RJ z;8;V*BO-FUzWM8WO5QN5KH^9(@P?(WQP1YKNnfSjjZGZ;Lz_72^P+2ZswjL)go8Mv z@4cUw9`#{;X}gkyU)$3iNw8Xn=;#a?YUVH#h*&jf$<8~urB=eM83TxmJkQk}1_9k) zr>csad%tTL^_HLsyDcjnK7%JVaqG$f1x*bjF`F#W)8M1h-wF zq?f#5){8`J-GSoijM&P8-@teH|KhkCcQZ?QN%Q*V8xZU95|j?pl0%~kbk4*m;NAsaX4=I??&Voanolt zzqJyUkmc9OoBPSdINB~FEo5k4_$a^1I-7pr-Pv zCwScdQT65=Xb*4LtNSmh&o1_+>FblG0rfrD_`cmx3)lnK)~eV$#8|^voy6lwoKZ{v znwQxcP`eLuBB;Ro$6|{Xffx9Te>}+98K+%}UO#_QkcR0ZzbQ(0Vo(x{vld$fdK_21 zuA;&RK^xnVi9OEVIml&wEX&}-zQ+(qx>21ezq^tL7l_5X5hE58GMia^&WuE2o&#YQ z7tyuoDlrFZe@fOc7I}pS4aH^++uxI{VIj|+vr){%QPtUP3(Kwd7^ zuv!9Z*igwD#4);zhYuHGkS;I0=7*{SroxXE1t*UZ)pE5AI6C(c=$w z^q{*9L&Y8CuqPC!{j0ZF!)&L~&aj3Z&R`8Y9AXVS4A!vEgEegRNx~Xdn;30BYuKSq z^0KtxKyeNlyGX&?y=xIa!*zu1-g`pvsZg9^mYD>ZRpjNUMx}yu)2Pt&XBrj8tN0+4 ztYNBAc?N|MpL4XsSB=F?J&Obzc#e-XOhyhWpWP7RYoFa!ldNHKkCHXaY6j;!LvgNf z>Mho=-W`47tYOnV!x~oY1Z&v0IypLV-lbEn#Hm!qRyCa%rIw?k*(mie;x*-G#kd*_r=IfDmv~Qy;s-); zME(2ocXl7fZNgFW(?xS(a8|O0pL2-YyL)3lp4?B&1{o0xjMxJs-t zTrG+pwhDG`v7q2>FW~A$e*3fj#k0J*Ik~(aDKz}IV<-&zUf9O(m|cdlf0 z$BS`1Tl0pJom|BH$Ckcp5q+_rUHZMbb$@gC=DGX(=PoQ+!vvQn#yZ0q_L{h5i=Zpg zuES^?=$_*a8qw7>xJs0SOV+StMzE4KY>%y{*|}@i-aX(7+2SRZ^!0u1= zgx!bn%lIX1qf}McZ<%0XhNvo-LZO6yiPWlcLLg!XRUJVJMcs9NN|^AKe|sX8W5Z1d&NqvlS!isR*&cKv%c%NY$UGxqewF44 zl%2s`)O@!l{rfUyC$50>*0LIT7_`J1HaskIemUBj!jd)2Dx#RIVYDZaHSC<;U=6Dc zcZfCYhY^Y$%Eo!kNvvn-&(WoD7a-j*@e#yL`el3+AB2)MObtLZ+Qcz&xhte>ou_J# z@oVB8w|^(z>6wtWn#s@T0hc^`C(pbZWO4cxzZiNR8TP%VzZO+quMPm&+TtwEe@V;qO z3v#AQ9~qS1MqXy`nQQE0$cdna9c+{4)ROrfdKTg)He2NlrQ=1Vv2IwPOV+Tc1)6mc z_;gS{qwWiE=GT8CBx6SE9cz@)vRK20O4cxzc7+EG96Bt}8dQANFd`i_qM|houM!Ga zm-rWTV|#G_iC{>?Dxtv|r612b3m;+~xAX$mar9`w*Wlj>SrHWMK4oCnk|CxUz^mY4 zCarbK_@YiJg*Lvh#!yr9Le%)eX=7YkYlrbg7f%L_pdsRst*#;D5fQmv-+aqT$r@($ zOdRP2*08iS>e8sScv58|6YgjeBW~Yk6CrVN|gTBXAbq#DE;ny~d#A+R)qcdcv znZryVV%2CxTSw<3vt|q+F1E$E4V%I&Jr`-&U_Qn>wNBl(9HCP*-_P9B4U&qvPTf_q zd)x3KYU|jAuk5b~a<$9W5on?)TPoCAOKJqP$VZsP@=Jd!D(oouFso5Y zmqla^OIxYl7+aI2P-z9-T&wOs5o^^$t87-Gz=^LbaR$C_<7F$XVOVEl`09|=xdy3O z*(Kz)g|M$1y3+r<5xQ28$Iz8Rs-R!V8n&R%RWV8=8lqzB4tyC$*LH}ld@B8OB@kWd zTZoyv-yqFWlExY)keLHvNr9u{tl5xjBPn*4p^`OBYKHww`i%88NxvJX?z4ueH|OFX z4c0Jd1=`FS_D9XSa8eq^CoekZ_22A<&Qurqm8@Yva^fsQRAqXYEuxHQNC}zsFsBzN1 z$tck*YuIqf8ph(U@StIjMR2D5tG8IgY^TxAu!bGVU=2GIVhuY4*09fkHEi&tVGSE> zKWo^pbdr|^V^!iHm9YuHIcV%=*1Hz*Gw|`ek~Pc~gMV1PYu`S*zzU$mJ@>Y3{m{;P z?~q*7GcD+Q2uJ$%MMKo+_YA%ityDNyyNrI+vq-Rk=lEE|WaOaoxpmesxyL-#u#t%r z+u$hq0~my}@)@kb`Zmf-3b7aV5O^Hr&ox*-WV=DI22pWWa=0@Te-ZKCVh!uv(I?It z=Jg#}aMg92>qp*nWYNdo=wG$SNdqFYg*}+V3`VTHZul^Vp1F1iI|UApsLqN_jC%I{ zIHRRK$4ieM2Yr3s^#eHK%&>a(wtahdZ=<9cB4Bb~sUP!ic5-y$yi2ECMHr=);}18z z|HFuz-k))E;UhXrddV6VAEjteW?%^wi#5!~nByF&poKFfTge*csye(1gAPh9g7gEli3OXEz=xP#yXlQx<-=im z?JaNYHF#x_I^5gqA?l621F3OP?x;650kH`em0@STXwn;-nPcAA!>PW4)hcHLHXry5 z<^!LFWZgUSfs0UUoDcl9R9S&TrF8=D!%9Z`n&QL4)N#w(_nkj;&m=VETUK!>4~;ea@?@%#eqL zrD`SGcl&oReUwC?l#slBK zG5=drz-)-5s2{f99L>Qc%@13^vS~l;;gU6s#a;2sy!fnP7nH1F6fwY)TkQ;M*sJ1} zEr2YjY-V5I>Z=i5O@pgMNw{PUOH_n+&WUFe`f*%TiAu$Lk;i17pxd`gD&`wVAf9hW z6xuX`Y%@}EE39F|C2JVVyTXHpqOpc;i?D{B8eS| zWlxO|POJ8qI%Lx%yErcr0XoC(i5Znn8cWtN>sXxw?#uCrIB-)X!@w!cf<8LI#DQBE z6lLm|X}4ww#O}HzxHNh09g&pBa0TFQA8Qz4no@aA*0AA{HH`IA;Xy;NTBH*$6huk~PeggXqc)46jC791L}Xrc5xT zK951ba6MuGx@K9!93GhtBJegZS;JVO6&^IGf!JM9r}+Tni6?c0OVZHV9ECsN9AY{0 z{)6VXdNz$K^Vocaan|UanwQrWEPwyHQ&w%SA6@wqg=GyJYBy`xUzDt2KXR;L!wIZm z!zF7N(V$|GfHO797HB&vK5G~l!%oLu6D{sD5wOdAthZRh2C?3y-K=5%TeDkEP~*vk zF!?9Wd3T+tpbeVT$31~e>SNq&^H2NfOT4hl)uB*2qP|qg-`RZ_r<8+G=#4AsiW?uq z&2lSK;AGvUS!?+hr@2`*V|n5mNTBZWc0?f=Hq9C)P|G=PZq~5jk~NIwUg1H*jTXU~ z@?*&wcG9qhRfpTn8umS>2^GLLA1$W?C5R&d|5P7}GZQ35k36}5c~zw6qg~o^kP8tv z4+KPgBqna1#snx+m*QwhU$Ta|LJ1vg1}I4XD88|IUy#XWeOXAqO0x&b&R{NTJ_eKi zEt#?tS3vqES;Gj{MEN|s3#}O$2M1&jY{$2;G%v2I<(E|*Uxyc09sWwv+InGC2Uqhp zV%AZq#MMPHS;J^gB5T-B^ag8Kb-Y8YVgDGR*dd1I#Y$GP^yjF~^8%zBCO(3=Nv({J z;)77KhN%IFMw>V$E_a0_C6^}s4r(63L~j31yvxNJHXLM+>Oa?v4klw;$r`4m{xZ(R zV-2ItrUzKVs-vA@4f}@(q_q#wR-m#C(54YLKx14@cO`3>0@@8IlQ^I)Ln=d-khey% z;MWx3uECWLXic()DV`22g?3#?(-Ce5iO^XnxS;)ym}MN~UpR2u7s1-fJni&~&r7lBU);f%U3z*)1bVZ%Oa z7%?r2HEdXTd1Tvhn}gP{UMS4#s+6u=&l%ZS;6cnmw_*+|^YmVrgPw(QYf$l7!-#a$h{_)oUL_Q;F7Yqw#)^CYiEFFeovhugVfzj2S~A2m19%k_ zlu2uyGQOx&N}-J}>?+nh5Y-ShzHr(Ym)6>0e96liCOAeVTrCUo_%*ldD_O%TR--tF z5sx_13#?&jYt*xuZPHh%cViRBWY)0InjIQuDG^dRgTBXgsV%UEVYLp?(HS<>%mHJD z3uf2IKe;X9I(6G}q_@_oyGlmQMnlxru?t_ufwf(>jw}2}Q?|^<8b2$Sb@iFoUYdKUe)x^Ui~Hve-+XlP z=#$?CzXSILdFlxs_kUEqIS1Oq8upd?tNSmh&o1_+C+n{RO%CIoq@2Q<0iQaFZ`=*V zfIV<+Z4kSM7;hLWl!&|@XVlYOyv){t+I^4{K{w(1{brpwDG$>RD6g?PuM1~4)TS!N z6`DBA)vr`l=xAL|9DCU5tfK{)tea)oeAxXM0>_@H+LYh%4J1(5-Hj*|seU7BKpZyA zj5%F6&lVo1BWSxh_ z*3*~(QFR55rdypxyc3r23hs+g@`foY(uEy}my0)y_!V*K0j7MZ_IzqIL}k9s__C4A zHy*u#UNw^WxU&WD&Y@KkI}ABk6W%asg7bO9T&fw2%tBuBhFRSZ_f9Nt*ifN)!!l49 zN=ml}7K^e|Gw>ANu))srhW$CGGq(+uUTQ2wRP$en%4P0x{#C~%g%VKf~f zP=w}`cae9k?gvBquv+to0w8%X zxJ>f|3V=~OE5A4}%a&OvpqB2S} z%NsW0Xd`s^u+d`#UQ~(xRilIOkY^D6?3bXQeFg=y#Jzqm=x14z)X)B*>O|>q!%%TY zIqV6=X#wjk-Z0y1v@^V62QzrX4u*Kc4uUuA7r`4=J6U+c#)sR_8}@W3nOQJgB@R*< z`{$j5#x7Fuc8^l(8LlIgykV{w{6onbX0s6z4pH~)h7jM`!d-3N`N7+!w)kn-B~{|# z$&1t3C}|P>-Tcv~2bS z=~0O6u7QbEW;jzf9_L5}e?n8THNzV=9G)kA3iG4`m~r&ZJZTWc%z4reb!x1q$UKQN zcnhm(zZ!%1iWN`R5a?c&YU5&KZ!EmE|JS84VD zmvzi@ca&bIzC4;f;;eF70Lxn+?3N+X1WWVr$79#^SEvv&y70A&jyz z+K|hi?ZxL=z}IUzWZ1JcFMn@=Vi84@V@uz)i2m5mF8$uzy1zMm^W6RYb1O>bFp8>c ztK%b`VGesm9J49u5}PUNI*i6)eneN)AURQGQ8I^h*^P&m)cBOpdZ<`#*+)Ak6!Q%v z5YM+G3iNK0IgDUTnyupJTRuthQEuv2m~ zhn z=YZU6@44s0HH}~Oz@7Itl*?OV4jU<%!`S#L)&g-3mP-|fIqYo(XAT21Pn(&;0&1T8 zN?=x|NMPOHx9umTB^7!B;%V}Z^Nyk_H`VUdei??dg@WTRh2mcg#rdsa-x@!?&l#m`Pe~f2>^?z$ z&wFFe1E0%@^^Gt@F# za~O-X!h;5Clr7M9RD9+zu!fzE{U%!6Ya(C{d$h-x!?5C|-OOR%Zg$fN%$uq1Ow(*; zOq}y>J5fO!6jYIYfdu*D`vMsvK7;%gKNN~1>LV)`o!EUCr<8+G=*=s+=s7-!i+_+w zeaX7ZpK^bk{KaX=+KlCiZyOsLd+8tYcu!XiZlM%FN%^b(G9uRuQit@~J*}%xc3((h+dO91C?s z-i5puW_TJbx6C+GNARV1qnocISh{i1_PY7T9$iU$5}Cu^)+5YeV5%6cu5f=gsoUrS zdnV2(*Xw!dUBZh#@A?58ab^hA9|1K~%oX;(Mrd}3uz9hPkFt4x7!xl*x=Fu}AZ}7C zW>l+0mDw8J(Z*DF{nXUU~Wzk@7C1ko$J8!_TtF6OY2AbV8*xn^`Y8QV(cFjwZD z_cG4KV-BOurWcsQ20OzX_O}s8YagHyeGSm25jQ|%TupZ+bC?1eT@B-awhXBZS%5~> zF@pfwHHi6uW?KA4>Qce8`ASpzgeEeF!Df@V|3h^g%sULS|HFN-=B$NGBGPOxSaYba zqBZB2RXRe{g^Hee+7gO$f8J?in$`SClA77-__NLUT!Op<8IqdW?Ue^_inw3Fxl5*eK1Z zCG*c#7veTHTjd?4<8|KxZB`!6$^;xm$7euL1S=0K%lZM!N`kd&@uOtBws*E1o@XsN z3%uCE83Hf(z^8-rQR=<`XMX)RLNcE@j51mlbJ$499L935@SuT1hXq=Liq9NIq@zYu zATn&f_IbSAAJh#Cw*SPn)fzY(+RYp`Egp_E!$4h^cgooe;8jpmCarx0ag){S-Jds9G_;C?pix_;MEh#yH?bjW3)w#sRM##ur^X>9;1EV5aWp<#JL9SIdGte$73@ zV$5NX*b-&Ap`i%Z!bc&?%|L3AV(0}~j-C^g<@!|CGBK)xbPHj`BaZwY^1n^$Zav!8CE{tJJgkZPM4N z+g@^fp>80hJ}4GB;{cAaCtpfxLU zZ6r;eExE&_a!lUjmGm`9zXzx8bBC!v=i(m~?l9~h(q`_k?=EvM?@=Cu{0GhIt z4aUHl%|@W4`-)SQ;tIWV=Sq}Me7w{{Mrck) zOYShXs|pVqCM|;VF?>!mcUUdL9d>0Axx>hJI5AEf5I1OGR=?xn7;PVS7`P7!TKFVN zc}-K$@EuL&V>}7b&O^E(+CzvNqA|W6AB3qd;vnfuyf261FNETB39~$i`p+8l)BC0v z?*(Hy-P`-{iH4}mw;5kbd4_XEWxnz7SAM*a%y%tv0`HpT4s)<3yY)*GREf}E%k5Il zWMnh!k~_@mgSdBMxx;FO<_^n1VQ6}M$Lda*oRYc2YQvr94*OG1$wi2ilM^R-a6+X> zmwuYNwZb{33PiGx(eMgZrav5OR3a)*glctL!c z;Fa8AHXAv9?l2jB)C0rjE+Zv(n2ta%;@n%@VZA&0ByfkF(kt9yL!ICbd%lyS6X#u= zNfl(2T8@rpTC$QmOwq?b$@J8=w3$JATr>+VG?@%-iKW~c zNx2VKoE|mL9cE(;T~^%Be6K)v)g;U1DBKB6$rf;jrTS&pBHUr0EV;u_ZKBPP+T4lL ziQo=WLl} z<}_Gxhp}XcZy(xu?;R3nIW6d;f==*JQsrnJO1xCqrQ*1JuKpkkmse??KuOi4M>a9B z2`3d|XHyP?wBjOf%p*I4J1l~;p8?MP|LnaBxLn0`Cc2M=BrLFlz{WOU(E>wgA!GV~Av7^{=f@8-98)FQ59!Unw80;h#KI(3D%e$nrckSA>A6-@ZuT^WU zs{f0a>7m|~y)gf!A4SjkFMsW7*DATzHcvKiP&3yoBtAWGe(2?vt5eV!-%T~aBqEFI4@A!KqvjN z{S(&?j)A4d*uz*o^jbL&dzAVI zL)Hq;5`o+4j=fs$uS+&+Q`ClNO|CoLv89If&4aCdLW->Xi0oIyne4MELe>jh_83`P zO&_Ls*)Y16>|v~timMjxZV2KpBHnH6VP}`@VU#g2PX_a~heuXQb#26!o;g$4_bs@b z+bFsRyE?NGjn@e|JvP6juGuQ-s<=zFgfsLeB5qDik^OgB->0X5x(kzPcIlf9q~C;R z8+h|Q6k60h+W@;r6gEf1CvdF+?NdQ~R}kl5-SQynpS8xP>q_S9c@h?1PW?;gH;eDe z!2!v33ASqAJ-Ta~OEZu+3O8D|rmol_?;4(Gyj5Z`-#`Nu80;vZoUm3_$9H=S`3T(D zC0An9wDg2U&Zim6WDm<*xopH%I@7g&UV(i4IwV0===6eod@)Lt^6{BYel^jwqJ=Ko zZetI-J;5HfD8(MOuxa+Ng*ohDi@TRSYz!KT*0P7~)wMMOoOT*y>XA*GEO8z*D^a73 zxnX0;9%kQG$sRUu_AtUUu^l_X@oVnB=b9}KhAHc}Z@c4;ln;B8>|qnKkege{Z5HT$ z0dSJ?MT8a4o=(hkwMr$L)`p5p2rJz3WaXc-{I}hApXDps&$yGJVv9-iEz7!pg(qEb z(vBP*#FjqnPq}VDC6!n^!AvS;N%rVU?9M~p|Kal6AdY$LT65{;71VzGymc{5aKZ8$ zFVATS_ON}(r5A-d3{TL+d$h}YG9*B^2MRk+i^;=&;^}#s*8=nRhaxU3omfkY(HmU+ zA?%k(T%8&zo+3;?iH)W&i@qAfcL#Aq{rxGP+I<)=$-~&B8B_yt31SdXt*IFNr=B+w&v2lIR3IcN2^B6PJ9Cm z)Lh<)DABjkbtlH=&mA^aa)+_pE8MtnlSQyUfWMME?AYNB8)`Lo*zb!TQ~_HYXbIk8 zu97{HOdEzXkM3g-I~(dVN0anf<2JF zLGCbuHMN%P7rfsr50VzE#GLdsV`K1(jf2hWD7nL|BEEx2_i=~Onndof(|UtDY+$TS z++qJYL9{~*Z5At8&-y(l7hO9C=_dU?inw7J<74N7Mr*ue19wPC*i(tJh1jfxEt{ZQtS|I-IAYVOq#r z;qveo=MCqbxQweQz+Hu$6ySsmu~BuY&z-X7l-yygfeJS+Y_bUUhwwMk*KOQkd%BT3 zEL=H_i`CF?p6-k&y$w8^2X`12N)xqY^X@#0@I)J}BI-W8q%>A!fF9sQ0G+(0(e~h^ zf>fwmTp&xJ8F=v?y|5e_D+`rW6R5RkQ1H3}u{3y@??e%JB@NKLqw5&tj!koijd|`c z%4kL0VPne9qn2uu(}wb9Yz_^;g3X|wk{^Sdb{*t29jEt#oW{e0eW!2l>snCX>i=op2;4m2g8v zkjK+pGpyD#XE+b>O71XMuOWh&UY4h};_v8ihvm&uFXp$&pQmnX$?;cp0x8||l5=)A zwS+R^AolqBXd|vOTPJ*Nn@Ne;I>bjYZ8)=r*f_lH1ICT!$G7bKwCYRlFcgJ^`K@y$ zwQRTWd;6>uTlrz7v9(p^j#wGR(XvBZYfAN|c5TrCpdYro_x6l_qhu<{jke#4J1V8 zTKV$#?InVDu>7?%)s>;KXs&vFbj_ATwHLpOCFq(Jdc}6^I?o>F zJUW-QhCS?AuePUZuYRpdXYUW^zS(p#Z1Z8Y3{D$;e6S{)V)VF2$X0`_Au>0 zTesFVYbzaCcMPfnxCybejJiT{sA;V+Yxrfj0*KcXdl>P{pwVVEj+g9VEc*&KE=*Yj z`@{G<+U#M23HGo{x{^H%lN&SH!^T_39`^r~>|ytBd+>hOI5GNx-;6s5cHvS6l$|p3 z1j`q21eKL1T(W?8wXp95Y|{_4VV0uX708oDx1_neBkW-UYr0;)Ho=6aHe@+TtsP;P z>|v-s3B`GkNW7WN<~fT4|NiboX`wN$Q+(GO#4`} zhehH9*$peuN%N9+5pK?M2ih4tgrjt4u-fHOb!>KLaFNRsD*!gS6y8x)0(=7vO!+XP z5Qlw}ZJIqydx=Kb!^TVYFqVCV8yB`&1bg~e^%i@Wtv1>o_ORUr>|whD_ORVx5BogW z!^Vyo_OPMWvxhz2PJR}2W|^H-!BPNkMPpYfxMUA&wMK9z9ORN?jZgW;=RQl*1Nq= z27B1?y}=$fG&$Z5_OSi!?43C7!ib84s&43|DDInI^~VvXNRPqgG~;eM{xs29)0aiN zg80E8j;KTM1%cJGPvQ^oBqpScVPp4Uf+4=LD;(XW4t@pilkTNX;cFu3U}zRGduK_O z&6zIBUzVr$f2Ye64~Evc6y8w>Lz_}5A55ft6i3!eq2Hj-Rzv;N^i40v` zx(zms)N~j%Ka{12+t>n8kCMccMko{3@FJk+6WH*+bi92kh!c@5oo5xH7EJRxP1gly zhIkV9;Xa+;7M!_iP;x~F;H)<{cU-hEu@E!bd8VbIeHM!WJW=sc-%GdlK`ActlSF$CeTwdk!#JHSZg2wss$TPf8HZidg1V+9_{RPL7H|3LEvWK}E5`9!RvWMl(cPU~I zBd#9657UMn`u=Gf=%hckf8yG~QLxmsnmz1mfj@RDkd@!LAuGTBddONq9wIPNlk)}* z5gB(-CyO>3B2w11_`V>Hs7F>_XZK;;sl#R7pj{j1?^a~($1A3hbs1kAL6LPcVrgV; zm0o7OJc%31z#qUK@~v-=b){R$*)Y12*rs-V;b`8V1?^ummn zjVMgcc$soisa13Z=@z)ChlLjr={EMTvr6_b${3i5INTogutVyat&*;ay8_YJc+0Pg zxH&aA%2Zke%j%ZwVfIa-W4Ij(Vt2?dFw042ep40secLx3KQAd3@4$&Pc(+O{<{M}r zc(bDbcsIx%Ha;KruTjOAV7#)WQU54$VD9(G)cJ#0bK>|qOX*uxfeF?$#^6s=_s z`?{=}D>@0=5Tf|yp{wGX&2#v{_e?Q}Cv>ZT)18o1x( zUTz8Yd3xrnU7lE|x`=>r*pZ za%?h>nP;eE50h%-@K=YNHWb#{y%M{2u!o)A-Rxm-VQ(>eSWM8xHX@Fa!>|p{&rh)MDY)bYp7IK9f7h-jJ6wy5T zAf$=UyZ$Z2C5zh#g_m;#(GK>o)4P;CY+|(4>|uW*OXE@|%p8>$2z@O7ENJ3_wQt}_ zh=e73m=r{?vDT}~QMTVSG&MiIrhy62)ZlWs<5}!s<0X3-tEs|`3sfgtpfB^^0-3s- zJq*lYCt|&cd9F1Pvxhy}TkK&InDNqT_ORb+bkPZ7C&$gr51X4^cA|ndXvj+A6Nhnh zw5l~kY5KB=hA4~g3*x-WkekLQyAR`+@FaxCl07UQ0FP^#U~7(6Nq68oafayI=(-aM zwH)EfC4Q+jIVxb5;e5qR_OM(V)JTGT_Bq&~&PBzm!Lt`^P`9FFX@mNBfengN=`9>U zq+|~}R@lP^C&yaN9`=3FgDPN~ix$zF7*1s<{yA-^q){U(XLYL?ux(aWJ{#@wP0~m= z%VbNH0%`Gxk(d(U36io*NFNO8Yh`E~-qV@O(EX_(zAK3Hc82u4&XAsQ_uZ82VJIQP z^>{35DN`sZ4NTdBD3HEE_Ar7qQJ(#R2YDV8VEmf#0k=}7dJovj?InAd)kAl(htZlu z_OR1?ggtDaP3&R+K0&q9O1;84XaI(Zk0NeZ#yF=1Ae8K3PUT6HOG~5Bu!`{pVXOGxqeqx)^y+bMmp(d1%vF5#*;r`*ZHzL9&bps9#;M z?zmN(tB00vSiHHqs5%>M#UC*(W)J%&bIGNl&#C8E5(^+tw`<9Z1uIvtzU96hTW|5r z(kZ>xPENFkJna8YAX@A6q$^QMhG#Q~8=f)F(Ko{MbJ&=Sw>OAW8)fN;dKqujr}s@W zPF*ZQNgn28JkGkQZ8(Nec?1;WzHwVlG3G4gXuM<(WAmzTHj`s#cUQ891uLgfEy&d#IkN|)w}FSn zOY}%HG>?Cyioil?qLyraw8}}0Hd;m0qf0nKJrn7MUJoH|=*9Q|{t!y`Fei<%U0csA zB_kVa$t<}%X)I}g=4C{64IGc&gedUL*MGg)oSr?5pjN~lHm>|U>P%x}(2_mO%AWmi z_p^r)>8KG^hz#Ymn0<-As1vf9f8yG~L97toYWA@I*T8OGhL}bGuY!Uyz-yQB#X&+> z8(-dnazL+C6FAUeP_s6NjcLGZ#hjn_;?4xT`+#2!&7PE;RKme@k`H-2%?0~vXZMus zVXRaJ;>aJM-rw$Ivn*Lowc3*XD6)s;%~CJsx5=NU-id`A!%?k!UUJS3y?ZGW(nO0| zpygm5>|vO#Lwr~>Co1`fO^s;@)2nl4s7h&2}#sH5$s{XJR1(Rh_L)hfUsORXI|`Km}z4O+ai4B*KYVq3{aH` zy8uH1^$oX`Kq^RI%9CxJuWmzpDk@bJPzlhGN!MfQwv|Anj-_P6O;UEZV@;#{qe zU3s_l{+7ho58w#WtZ$K~V9ZrTO3ubH7N%wsY5f>}G-p1{@OXlu@t0t0`7vZYZEU?@ zYq=DKNn6VrC!v~Ru;Pon7umy{N9XZBCG24nSU;r2>|x(+)R9x&fJ*kT;Cn%|ee)Rk z!P-X}KT`q6Gzr^rB8|qaP@VFLd;<+cV@lRUW1=PnlDgt9GB)YnLp?*u9>yZCaN|OE zvxj}6C)vXS|DID(%#>`M=I%Nk&X+w*-FsAnAlibaxfWUH`b8&aG_FLt=~rhEH-i%6 z&ge0{%cn1k_66}5f;gi7{=Cla!*~UM2wiOsXKkee>yANn05>6)M#UA9Lw|9eL1~T4 zqdEY(u>ME z=CFqiwVyrgha8f7GnCn(#1JJ$D8_XDjgPq$q-M^&DcQql8APB6P2p~FbhTR%=xuR| zo8Ce%NX>I}7tFsN?~zsjoP|^d6?N%PmKJqaOAZrtyM{eXdx=Kb!zN1hFjiy5)g^b^ zf;eqpy~Q48tBtmYJ#1G2d)TgkJ!}`)!+rzoVH3v+d)U}m>)FFT-A;ZM^i`RiRKa2@ zZ$)D_yB=3ydy{+!o1^yx@#!E=>z~;KnKetJQbD?DRNCdSb`Kv8jY>B!7r-ur9)8J? zwE8`Rlj&}zRaQUhSu{}3%y4AvVcK(0_dI|0Fug~~9;Wpo+q;AKONjRtdsy%GJ{jy` zC-n+@*kC)@!=7tr@5FJJ8*+6+FGX?RdMPr7nZBNJH(n{(!`xtK7G;v|rOreu14}MX z@BdE8!K22Yc9~-Nzm_hS@8_Lo2292e74Ol~y&>06&*HUfFEQ=Im$_^>znd*?CUc z%_4O-`eZwORLLGDZAUk&Ts+3*^b$1h_W6m_&L`U%QXMCi3FK?kUyylIKG`LEn3X>D zQQgQMmN(y}h&_zB%6>yT{%~fXwgH2vPWWT{CxSf;EH$lW4|_83#};b>v@-}|XP_M1 zEV5GmGR;f3cw?{DHY!?}-torn_YF{AU$;rU4E0=TiMLgHnf3m`L{{gG?c1Yyx#W3c zD_%B?t|faIOS|HWTvxBL!xs_hHukU;C3_f!Rm_taZx4IeUUkh@JXTOPgReLLx`>-o zgQHBqF4@DfnZZi-ux$q8TW-5;$F>KYJI{RB!zN1hFrsyZ8yC8bJ?tY1_OOL1_OQOD z*~9vB*u#$NUiPq2Xee6C9`+SkHJ8vV6U3eR7{~l?+GL6IAQPYqY@g7alnjzL_a4AX+rf0s(5=8U-DI7to+&cC! z!Zd~QCfUO#O7<|;ONAR3IAy}ZK}6`o{*-GwI?Pn3g)naUuSBFB>|tkgHG3HOd0NaK z78CR|ud85X=y#l)YeS2X+1%(IVKz6$-3*bEJNBPf5h4Xtmm~Q!2_o24=;<=!#Bp=OuDY7Jv5PP8ro zm#lW{*^`hjjY=|Qx@N6Nu&e5V65+N|862L#3KR^wruPg`>E8jB_|5eOD$$vbsI(Su z&0v5~kt5xFAc)g$)cwq1U=2GFYfa2^or#z^Y^KMU!!X;W)y!cpH@e`24yfsm)hvK= ziD2!=H_Ml!&_H8}fkIN?t03KgwOy{j6mSr_+7+1Ju6?iawz5f@oOU2B4Xmv)IVD|z z@5HkRzKyOqF(ElQx^0>{Y@%ciV`W#kae>q5EzlZXGKU>I%wYqqW)3?nI#3F{s_~>U zRJ5PEhu+gPq1dZtROT>BI*;{Vvq*n7+NB}=xro<8`XUjU;xEGV6WEvt{ZtU&6~qzE z6`|dC)72vMt$6=5(kDgePx{}8h!4$+(7ZGrhnkvm%HNSGTW|!VZ;&~RU`>=~zYwpb ziGxDsuwloRqw=+__*TFi2HqV8mBe3wBz_ZQT5WB;pdWZM%Cw$-z)2-i7vIMA*ZZRA zU%7^1WBhQuA1=Q_)%9h_dybRzO)3cUpCxzJ4fO-29}SXg^#e8RI~bizF=`Pj9SSfpcYaHae_mOtHJPr)9=dOZ)L3wh8NUB47t>=|kq zdlJ9FykP%4L9;^$Z5Ar|D6OKT@Ouu@P56BjanlAc?o`~a+*mXVxv2@El8ucZGtX`J-Dj7vZD!>Om1%s7g?+59 zbg%}mS_L+Fd*?W>HFEy4ycq@qF1uQOxB@)kt|{WMi8y;g$FOF6G#lAU-Y{3_FJs?* zykWG}%+3x~7pz(weG_k(hiRsJ;*aSZq`9ZAog8WpZ`hwD0IhX!wi2aea5jUu!5QP6 zhKo@0hB@QS4JeE>oUM>T(vr)AGbbzKYD#aMZ{y+2nrl5(siIk}!j!yW6D4mLtDwS- z3!5y0{UQ9#plj?d-mqQW$Qu@}nMS1`#jz8yN9k?g;XHW5utXZixbx6TF2WOStcs}n z@{+<>k?Glq5G8MzL$51*8L~7jG;ez5l}^w_jCjToJn*bh-Y~%{jz@qL;rWZGB(zhlXU*^v3k(_lQkBG>n`byrgiq$CgA>t87dV@DCZ+?0)vrYaC z^-e6|n8_O!&eow{FJ;0(?D6%{LR`nqCwy(w&0(I7NQBN{E!GX#Gh)k!95k!1qxx05 z`jR&cMIj+{nQL6LC$((1@cX2(V=L0r*xD*%2fc_iP`q?#YfY)%KpFXnw3v7q+d6W1 z!-%%2IqD^Em=!+d%kJb2%bTTMA6>I0QEdmEoTu)ehzAKh_I`$2f}`khtYXF z$TNcY8zB>dx>7F092=2A9jGeC;=l~Y%_|W3wHv;6%S?3};!{zn<~Nl94Vg;bFgA&C zZX^&*8P>~|8>Y~`5X1MlAvJ)o(>FDav1Gt;BCT1Ghu}*ddU86lF!*yOdBYyY7{25U zJIPm96m3WROQ^+t?9UObsWXp$0#Rf-9iAtkEOL2yY{Bx6R@YT$Uwe7(c%N24C>qS5>UAcOz9op9=ave^X&E}8@~(qt%*`D*WA2eFss|T7n#&uOZ3|DbF!33kfY8KK z6W%?n0SdM(H5BZ1Je)6Wm^$~+rlbPxElqxX9h_y5DI z3l~Ss3-2>OceIw=y zV`azi%dt%)e&NSmixX%BAC;Fsmj`)@QGPQ1ml*v1>tO96%8w#KitR}>qyA83OF4l| z*yjw$8%Aut{mJ;F)vSUokJW-^Xrq#-${))j4$nEH=VC?=VS9qa`=%McMB=X$wSP zx5z3%qi|zbphJG5f&KP4mwo>_B#o3)Wz7-14!HY~OLiwjFnGyYJc^w{P2FqHdmlfp!m#GKEcMGKFD; zpQ(`@8%WISc?$i;Gbk8UwD&^4!7qmW#t$7Q`mE03i}+G!qy%$Oko49X9|0)om?zXhcv4-CP)*|*%eVdRh3@J6edODH}mtO zAn+L2_**&PG(yT}a3bB!w8BS?PrS@O);gZ|B~pGKN9=g+-*V58h)Q)wB+N-|^Zc2@ zwD&2Q!hA(U(cMA(CB%D+DXe#UpA4q3N{=vwVQIjT(TSDPaDD|_s@8X64>@NK52IB) z$Q>H-Gj^m)$mhLAzS_>-iTZjDq`IV+qPVXrfn^cd!BoZ7H_f;kuarz-ZtBP^$|T)O zafr&GgCSFXX_{@{=_2u9Xq}zH9aa6XDV0LECk@QQvA*?EuF*EsPpOZ}5%g5l3)lK$ zkL1lh8KzGQgW5=c4dbL;7;*H@IEh*Sj+6d}){3i~6%rxY*2sf-X%!(_dneK;ddYIU%Bvb|F?hlaR0;C z%|Ks9o!NqQ)wx%pF`I?PY&Lql`pJ1Ph0SyyQ`qQatC_;S7WiR%T^P_A!Mh1IJDy<0 zYo&LO7dHKw5lW^oEeF|BJYa}%+4XsnreEE=C5PtnUf9l7R#zj1e2sbtP9ks03%g_r zv(l$NsvDWY@@BXcF@+IV*>7kA3+)ct20H11?Vq@Ia0HArt!4`QeBgminU{aEQ*3Qo zQ^W4kkd-QG)7l{FWHU7&aK1LhjtaI*8AbeIY_&`7n`YeU?5Cgd>B}N&A~eskXkQRV z)Zd@i*?kyy>TsDUXxGO1qo_OmulwmqIz4URHJ z;gTsVbGfkgEjzXm-*FneZJepL+a1W025%c%7O5*55sUc-8VKI(D4?7m$Tr}uO)#cd zj9qf=MNQKQi=mqj*Y}xhjwy^DK(QX;73d+pj}f=}8}x#`mI@;3Ax?LC0;}zc7P@R{ zowq=F^4}o;u*zn|{INx0Vv>A>L&-$DVqK|7tH0q+9;O&wcNK zdlO7y3u>9dF5n!S1O3rS2QN7I7Z8|Uk9xV2htWAa$kRs~T@&(nUG#4T zo;n0-1j4ia7frHD0W{};bAv2lZ^J`RmPhkrHt0}kTJ53BA})k$k~O&`RI=`yW_%6) z5M&`-lej5aTYOg#XGU#s3#NIU-G_1KI3juqyEe{m(lk>DcZ4%_reO+?c#k;cJRD8> zl%wl#BP{~&k_`4yDrobwv`;b4XCGn_Xwz=Z5bH9knjmTV<=&M@`4o--+ScqediD10 z_YS&b#)n+|vIp<>Bo(<1IJgyY9XrABYwo`1nk^58DeJdyyWuS@LSUj?XTU^R&VY$=({6sr zrTaH* zzT|6=gI+2a5u56p`Pt8$^g2`EpttkP1uoJPa#5~uOh&jT(-dh}DVe2&{_v)D^b@5XETT!oH1T$ z@b?_N<@X`0UKo1Id#WYgs9me{gme)0z_sBTX)I+r`p_{3g|~r+#Y>{uZIBbetyTUL zW6fz={#t~a*ie->)M`jB>DUR=Gd+k9y4v*2%CgTu-c~kjfD8&=Y}VG4C0RDskc(uo zr0JQLIXM?G4n}Xn9&qOCzn(Fg895vsqJ)-55ysQX!Bb-i%A2EEGK8^a5Da%1H(fO2 z6r$e+xLHwvYo?cGepdUhHjQi3SoQmT)z_mf)qjkxtNw-H9JQetICmeaUmR=sw2lCs zJrN9H@ID_HTFEENV!wnsE|-U|hu*4P#A*xb{2XAQgv@9G&|-itdE@2oZ1=rY%VFlGp=hj?5itkxrEI1llL zhZBdqOIQpRC68R`w zV!~xzhOkNGP0dX&8N#gapGTxS8N%{rr`Jc8*)xAihA^!lHVZ>&vkdYK z72xe<2%G6ahOp4L=Twvs1zV@MyN-wRWe8K(9{Rbfqh!etrVzFeazt&I-{RJ+t#q&! zub{{_p9aMh?y@5F>Kd0vU3)IW5dg0#hA_gHiK(6;EF=i4n786+p6+xgIh*kb=uYo| z45r;?FX&F$;Zt{Nj9*sy6<504*#vvWzl*;aWcmZw+o>5LU(&o1`7c7=F(;W?U56NG zT_EpIz6`FsQ5!7()B{oU?zy$#o;AjrR~KG8cja97F@+7$g=f;OzszC=a4A(-z!c`p z;+OMuv02Grc-V`r_c{@+odjTg+@OwFk z^CElJfKOM!?=+q~22AGs2CUu7FOrS5dd0YGo)`}D8REG+P8lp|3xq8PsOQ^89jzww zDOp$+SD0|i)LM;l*D@X*NpQY!E#ndVNE$yQAjH#AxSWV2VpFuTL%1GPQT{1+GVGHq zf7X7+C2qRz=eFE`SDfQUMEO254w(#eDsh(RLqYs7;%`ExCtdz5X;23!9aaktVsFdl` z?z>Mi@O)055K~yv3;U#j z*=2suT47L`m&jmfAjz^ZEGX&^E^^u9{(zE$1`hifI4IJHY2jt}E1 z?9R&UK}h1E^+Cyqp5Uxd?ZaFL#mw51=?&#Lr@Jc9D!&y!hK-QU9_$Qk zpmA*wCu~{zR>ZZl+KiZiWpXf5L3+D=*mm&Y=(t9(vB3)y>_b$~i=*4&u-zE&@ZB^R zjA(~LAhCD095HlghhsyH_&j52AGR@{!8)7`sg#=&Dfi-tT~MP8Vv>=DL5XxOa%bS@sHaZ^mM9-lo`XS1zcY31FqKMfOEpfGM z4Wi;JB8q~cPxKPfKaQSgz004~6R8xbH~0p21L#?Hx%_UI=!wn@p2f!W=Veb+-MeJ{ zwO3U4p161M!6h|JVj$Mue?f0BiH(5!z%z-lsj;8>RqWB?W_dV2Cb3uB-BVd#hQ2Fv zfYsq1i-Q2`vDnLNkJ4H;F|J95Fin*1)*g#3$N-8jtHIz#dn^KufsEydWQj-~74=x} zblKw}(prB5>#?p#rQDK8xgST?V>QMmCY{p}k%@67MX2YzIn~=9MzCIDrag5yX?yq_ zdaYxRP3#h1F}=bjwr3t(VvkpUwd>f#hKIvgj&*N#oT z2Xlo4jw-nBj1Dejrwh?EkJJ=hY^<;paT{kK>JUW74JR@IBHeOqnU8UzrHVf3Rk}5O zS;VDiEKWJv;)weDvsCOpjMMiSp=1-&a!`{4Z4U@BF0XQDnWn0%(L@SIia=p&NCmcy z#{9H#Bk!giqideG%5YLU^_xJ~FG8a2oiRZ_ijQN0zt*yKMV!=5y~h`L6j3|XeH>zY z=Z&TZ@O$*9hjs{U1O`m)GDL*aqWu#wQ;p{>DFN?nGhl*Q`dX$5%z+fq5FRd==%3Pg{~V>m_*kp zr{!=U8&!Ofqp*Yci-`X{^55+8>p)OHFa2cfv(t;HdfbhhzUJ~G#+Dm1_6bl^kMfAs!lT4~N+A#a!u5lb+PN^T?%`t|DhG#*#xU z+eX_qJ1)O(`=;$%ioZ}*Qt%tK?=sF~Uu7P6i!GHLUvjmHzG-3jVt-5Kxd}%AZ=x)P zmqK9}nHpyfBf(7yw6P`v~*DOLFRlxc%SkC4zLzPv)@W63k)msAUf8 zKRs%aI}BH3vxhD3TK2HvL1-h4J&ct|*_rMTsGB=^SgegO8Yd}X=d<$)&>666lCxMx zMTk~Z=2rhBPYx^>Xpr$W6a(n0_J9OB-e{VEPFtY+`zCs00Z#;afO_2sy*P>Tov; z(}}+pu0*6CdH<)&Z;i+>n)&##SRkhFD8O{%48x>Ztg(B2b*Q>v)#7MBuF{J_eTAoH z;>|muuCND!lxHxPH0*MD*K@JW(@AmVD9?gmz~gO)ZP~ z+3`chdkJsYfW-5?()ZxJ=GS4l-JjRleHcH@-DlXRhxv_m@#sPzzk+mN8)Z-kWJ|Wz zE6K94wwnim%)~a$pz7Nx#DHnOjtj(5F3`q&CbAl@VMrS0F={MN8#_3Vz^MJesIz+t zqu4_0VN^T@P+Ql7z^E@c9Ld5cRny_d2pjQt7V`d`%Wt*J`nPM@gQ8uykz z#;B7VKJCR>y&%LVTXvM!b^@N<^VSXxkLJ>bt(P}F2ish93SZkasekFgsabCU{&<59 zerWnBs!V6lL|c>9G=XG`;#^1)1&eoL9-yP7TWuPw_ zZ>{+%G;PEQYqW75YqI=hS!;aDU>cRlD-@b&Ljp8e1?MA^JLB<4=1SN2F6XbAHkn#8 z?LPsJ6m5G!W@2&I(_d0yY=PFHP=9HdVtB!PrrKtlHS!$b;yWl62CLdI|2y=QY>7uj z`pd@n!oU@FB37B0=L!=sU)bZ|3)|UKoMFSmnB`)eVXRz^k1xj_eaO8$EcPXixt@^M zi)(+Z`b!-nV+@Rc-00p7k9pE%;Apz}f$|&iJRNInmhVSlAw5twP^}=pf$GDE6B;P* zG0p)h!V$BEu?OLOIBL-Qcb~i`l`O9rZtNRWP~}%>UtXNczB~T1EKp_63tV;uRUXuH z{JjHt2)vE1IUyNoUTTUo4ANvs85T>9`5McFZ|@#Rj_0CCdIza*MY$5GKkks!gtiLO zEnH<0><{3t2#kooJ9;s}oqhVe#gw&C5H~ zPn!{$!WMX@uy5gFeZ^2ypu{6yWyA+`LSc}6EHs(}ZK4YM@47ad!YZZYrV)}wqIHzi za8i?DNcbq?Dv|b0Gw#04=}?n7>+>v&z8S<3_4ns>b|1zo_(PbU#75J*PvYhGk`AZ3 zB$arpII?yg=e1VOUzR8F4!G=!gf#F#noYJI(_!YV&>rWuoT6P=Gci1-m{x;qc{1zZ z80Jhfs72-lAlp?vg=}m)^^naBZ!Gp#@JFVw-%;4`8p{x=-olJ7+<-kfC{8axwiT8c zdm`I!xO)f5b&!qr8Dk22376>&(wJttCf>PokmjBWEhxwjM<-Xx?_$AILS(_AJg?

nRjH<}_q-+7L9NnZBNbNjdF7pxMRvZdLy81zjm6N}}1b4nYu=P;qQiXZl;!xfU%%OpVZt-Ct+l@ViY?PgeY~LwBHddj9=Mnil^1oJqY+<+d9^{`w z-jxN&X4+^zgO&d4O(R<^SC}H*0o+S(6-sO|+Y+DG5vVhMC#(iJ5VM7`=!tdg?@^*x z^03%OlYDgpyJyvlk){`#VcG$B6}+1XZ0)kRxK_~B78h1o8t|;WE8wxkrvcB}coE>$ zv$))ZI}`A%IhjpCXOMbm^!GQ zYtdxGXDs{j8-G)5|7GExS9!J1tvtUfhZkX=rW8LkLZR zca3GqRsJDn8~Ph6XrL&GW}uJTJjO?{Au z#qy`W5war0vuITE6ew*4s`48*RHaa*Bg(Wx(20Btd=wRImokbt#Zy(cq#c4ZeVHt+ zXz_hMzkXbbFAJvG+t_^=AHW}ih^KZf6AX{KlY>#}n6H@#`b!N}x8R)pia1*<1XkYd zQh!ULDjfW{wqC$k7A-M$ z4SQLHER3z{DcMph+5H@0&VzGlYdFF_U43=uh1CPcM>A946VKCrdXF`hQ%3|{N6Um+ z=U5S>#T;S(d!tU9&YkD^W~JU{9X30mFMYQ(@$S}_@`JUHR9~0dq`q`JQqpML3VkV` zbqO~Th{m@eMl^1aBaHco#oYS^Sb30~YwjT3uf!Tsgn3k^MJN-M2gjVHTrJMPSi-dUFEL!qrT1iPO(n_S8QgsG#ssZkMmkH&r_<3dn2lrSLn!p9b!PdWOe7updplPx^8$t z7Ws6lQnPyJu5dIunHa-!g`=mL43rI$vTgsPzo+};__Pshxu(7!u&+Cz3yFjY{Bw3&u&m@E4#t71>6SD2FwP} zg4f`C4_tJNa2gDaj>Mb>Y(hlhk719N^c5Z!>lpMCGxdn+82&%=L{fdNYHkINMc*LP zkGM%jjtMNHW@=2d0W{SZfJKv^<*aNw4gOamc;zegUYLL&s-NdPoecyu~CR2(Y8%eCLM`oSZP+(e$ zz0mjUL>aU1`KN-u=Wbssk?dOIYhC!jt}n^zr&LnZy1W&;dvNc2U4Cm(VLxRCa9$z( zlzSH*Td@3x`#=2d!~H849`674?;h@d__~<~qUd}0Td=M=_bR-GXQQq7d%XIod91p< zINFQH>BB>hJGKZD=sTeqa?e{kI7%-P$6vsTBHpjY9_4?Fyy-bS=!>pjiY@jGt5@H0 z-;S-f;M)mb+r}YJ_QhT#Hl83jBM_+huUYjFTY!xXmLkrYQZE<74^U*bX8#ane*-A{`JO`A^H8Eh*}p76*=v1mD3igr zkbgk|%4#2@7jb-k8}5Bu0m|Cwl2;IAzt;fDhUgj%K3@IgyioN3o|cKKu4CsLbqH7W ziE9V3GN9)%VC4{5&&3{P{(c@7>v**BT9;th`dP(R2c|0Y9s#cMD>q!_w_gueE68KG z+Ab#&C)xFw6NywXN+%iY`%zrw7nH_T`(}!8wGoZXdjDu5?FVqA{d0qot+cnsu{9(z zFl-&ovsaEJSz?|9wjO&t2ApbR;YCFL9^ZL4@fe(0@)!t@!QkjUAz-VxPg3+L_hS6a5wFCXpNe3@D_!xB)Z}^kh zom;CrqdiOZdJV;{>WR@m%`g6Jx%?Z&z&As}GJe`EC%g)#9 zgzW5|2gw;a31cx}#Zht|!yfgqm50Tvd4;cSa`UePo2e%jS=nuI#Q)SsxY&GD6L=@5 zirXBWiulR+%Ti6K$+I&I23*epK^E*Xah(Y!e5whPDHQ%Wi<$#=3aQFqKyfopp=dkm zQ;zQP-O?KHF3DgYqKeu46z!MB`RwCcf}}j9GR@QsvHGH_36iE?>s^VIPvHnaZB0(2 z^JOp)EXS>g<=BZ0^qRZxxn|3QVaodL+wQo-rZu{Cd4~sN#i*KfdFi{IY55!+f)<29 z{Rd|ukM{$&w2AftnxBATCz{uWN|3-NYvCXw)2PX*ofVE$oo$&zcnXA zXXY|@Q^twr)Iiq;%Wvz1FHdk8>_c|FDAWXZeC;oL;M(!wTq=Y0@~Y=z+n1*bw%ceK z=)9NfJ>F)@xdp^9yo;84(jkzxA+xSMgg8HEyp-@5tdV#${Ur99zAXA`5Z@idnbqz; z;M4o28GkEJ0zRp`wEHl@T0u8>fba`Q2evl`1;UMp**ie#m*oK=+cSd#;U$Ox z*?a}pQ_?bH0-!K|dU$~A>DUBnlQ+kJL)i$GWbNj9wB(}d9fV>Vt%p#tZaj)+k^ey; z)Z-3CvJgr&b;yXY0e>ry_itQ&t7k(T<}r;u@!C7bxvaVJm*oM|Dwkb> ziKZj~lhtlLTtdDCED0*f#16$JLnSgjWunqB8UGkmZkhoq{X3wNqHZt9O_!m-h)Qem z)(i#+6*PT5k^*TN_T_y+0 zJgFH(joB=KHajt{g7-6ErOn9zk#V!ZKjqVP;kplOx%ts0>7Q49N@(rN?ruO(Ti*#-0O8pNm529hANmB}jshV!Eh91=oGdqdpa*Iku{TG5pzRmpWqGEbCLM z5J=mGp;U5gUnD|P{6#ooA~5&e{FHJTun3bPG*jYns3H9nlO-@^3t~X}2Dl7FgGsIg zM2Pl&8V3&wWxzlP{V3KHUqL6kljG}S^ov| z$_+xTfi9Bl6-Yea3FSfZv1=!Wa!C!YmDj!y+rB*gX7XnI2{!-v0}e+;Fh;ytiI{g% zsV#|z=OEoA-$xNQiIs7u-Jag<)0YW1u1T*i2I+|U`;YnbKAAn>WW%0kG+=vAOTN~^ zizMFx77v0-zSkf|th@JPn}&svRlKt6iMDZelY(_+hcy%9*|?S`yVk7iK$hu^J%wu= zkJQ68s%4P|jeJ(v*$?LLe<4PsZXUbHE>^^sI9$Vl&`K;MY zK7(h$X0Q)u^}-Or{F?B*Q76F59=H|@d=E`d5D>uTfIliOIdcbvw}FTAAT#*WNc?*s zfi)|9Ey5FRkcz0s7Ji9pWL+kcoDI7kLb_oN<2EooQls@$$Jm5nuO z#V$7MG?9{G7eoAPS z0$ekVG@rq0|BSmgk1Z7AS}mIaac&lu>WvaO=a+)#ojU?__QbW5BQcc$%biHakw1!) zT}K@gO}vOb^4ef?;h!7S&CB}I2;5chFoU~Vi^~At1TYnvufK)_g~X)T#*7LDx>T&e z<{;7?Aau3Gg*9eh2Y-tOYwHSkZ0%{dv-VvCcNe((#c-FjxV#tV33t|*>f;@A)&)GV zr(nt0lrPRO=09d4-Y{2(Wl*d4V?aEvFs0?t3z8h$8xilH9m*KkR9p>k7b4yP9RDxK zf2u>UEW}eeR&Q_{b~|v>2MQ3+4Nc?%BHo|aOXw|RYlxRO|NOXB3)XGMTCMeGpck*a zo#*e(R$&tkJAsq#d6CMd@7cGpAt{b;hvc6KVwQow1 zm0y+pia3*fM@7iG%4Ls{)s>RmQ9ry`2Sw4+VXd{KdP8L7BhF&VWNhHL`yP$EYi(uM z;Q?e$%|g%TjWKp-#ai;lJlRuN%d#id{;k6|gSm>U6Yj1J;#BQ?2l=_iAww3{YKzwM zw_`k&D~Pqm1kGa$wODJj&=q5g=AqZaR`wqHt3xSNTS14>)z3r^=F_l( zh_C(Fqug(iw>^&sd4`YVs~f^%MvdXCBI}W&E5CI^S0VswC~G1OH3gJDD%dV%6md$a z+HzV;Xs|}^-)n>hQpNh_!PdSaMb}$#CXKH4@ga!KeKQMk)Jk3gI!(DXfQaAwLx0UXmFrW z*G+Zae7@;5x~cs$O)0_Iz?uzBp(JU(J`?G0;7I^9HKha^69!l8#sSF9gypzIk9#`8Su2ghL%XHdEKC7|*Rknps* z^@5IpzBiP6YeOYSm<-}CBThzx@4J?fCHGSQWZ`;5HX`rY1#<5S%Zxpn#h2Z^gJf^_ zPBR)jlFMlDP250l6-umYv(Y@A=}>b1;uFBLJMiUdm)Q$=#?GF2_Nv1WL?u+*p1XGi@$Vu& zgG_(m@@vPhqqq>;?2;=Hxd?g33h>OjKVHKn4Sw0(o5vQ|jq?6e4?q~0o18nme1HG? zq1pcZ|M2R&; zK+m_0I(Wx?QQQPW6(%G(Hp>+9<*rsdI+Bp&xLPsSo2S(?0zy2U&^${bHbs(Cxaw0; z{wa4dq}H|kS^F867}D%A=|=qVeP$do8R%4a(gj*2EF4DUO~^z&EkhRaou#K_`%BpV zA@U#Rs@__FAsI8RmYlj_3%J7FJ4p7DT;Dq4-l6`!==;@0(V_mixf|#9E^m2Yas{D*xxVVYXeX>o zd$GRp-srjN&LxMIH+J;;l08$$|IGlNYv{Xo;j24WR1ZZPuu`((@NePewJZ}j%*NGG z9Ci;}J3KbDc6fYprIaZv9m1pF@X(};ctnmoj(){x3?Gx1F9zc9mlzQLXIb~&+o32- z8ZIM-fBrCzxeQD=GVJCrI2nJ`qOt{^;^N$CtJ49yN+s&%#D3of>?cTE2ke(fTyb2} zb--@%7jfR=uLN;kX3rvy+dUbl?HoY{?{+N{?2Ay_6;t?a&~rg;S69<~gs>EU9QH1b zt{#$vU@4=koyq5FpXcaWyrhBYO9orR1r>RT4EEdOOojzT{lP^pd#nVY-*LmX9d~cL@7f)=Z`)z=Z=QRV2rEJ!rk@M!VN6OJ!PtY` zzvZ4G>q1OJJDR5p7)!1e`Ze?*2T?4lzwU(|h~U4e2lPzjSP;(>|kt6RBL=3d$g%%cvw8MKjvIQUQ=l-d}iTN zbSy5oen`3?B=OKXqGUu*u%B}J5N6X(j91BDyvyval7owd;o#z}cs)WpJ1BMrHqf{> zh!eIfeJkSHS#3tlz%r?It{~mC&JQE51B$d+&;}YTP>b&i;)pshPCKvd;7N2`BiPur zOt25J8_QHC(dZ0;D=6XmWXFgBX-eB(+2KSX);PEYh%6ft|EC9amO zK~#K2z>^|~zl1nfFP6qcZU8;YE|=f!5fRIgrn$oUkB|0W&>LJ~BVaff8Fdpm*wolh{VMioakD&}A6M9S+TBxGUxtpW z8+t4b0<6bkFRwjHYYD@+A{jzg6Na$`89>R~%EsVEdn^KuflQpoAf~9tdZ)`C_gHKF z4XnqyB9(GWBISM@S&!8it%B=sjc+3h@zW)~V&K(^_z#f(6xXv@PZjoBDmLmxTd=zq_rA~Nw+0pFH$PKe!Cvc+ z-MjGEg5}Ti*G}?*@2yvpCeaCtP5 z!jU3S*cwuSZKDAfZD^-(BO4J^Vsy>ZP7NouQ@;sx{bEm{Yd?yQ==#?M==vUC;K~#B z3i2;1Kvx@9^0LkNqc&?>0lL;|r_2i`c&r~o7`mE=Hc>Si+%s=9Wp9y*rmjclJ9NU6 zMVlQE98(18pFOZrem$#)h0y&e4n)%`>ziz`*e)IM4 zw1PZ_r_{q3o-#g&KZNP0u+el~w$bAIf^=q7WKlhg-G}#B&67?KW7jglkf=K+zx3k` z-M7b=b-_L%#Z!Jn_A4w$>ohZ$`dboV-;X23)5c_4X>SdCXNN>#9$mTGSElSbGLYb8 z{|eCc*kcOY*}8L4bZ4}3km9GV&`S|MnSA7^;u5$5&%Wv(2U#R7Om*mvV`Plt8dx;?3@*f62*zpN|urq4- z!4CDG7Okr`!xF|TF05v8g}npoJ9Z~m*zf?f5yln9N~G+35%#E?J9$_M6eH2Wo>?%_Dkbz_AxF&QkE4| zbQdJ+lB*4_ul6^vln*6R9>Nje+M1n4=gSw?G)tH)z-pjw)=$p7$;9+Q@?bFNoE)x2 zc_GkC8)h$H`Uxm(VtQ?;1PL_ZTR4OWS;D^RaMy6zFqiolw{RsQ{mA=2U4CmsVSaur z7KrIwC!{u5e&gU-m|zLpkL-F;sQvBuTDtbYwL`t3)X1OpM^O>Ka&9mV$l?G8>?i|b0#tsf7Fls+AiZkST2cy_R>tR$p z22fiUdBVQna3l+(Y&3#fM;x!5g}i^~@>?w%<}i(6!`C)V>VNRy)U2$>m&k%9 z4z&%MXlvpJhBusMe2v79oao?f?mm=t^!_S!S_9|?A2lrlebIPp%~zp`4cOi}&SOoM zzbsceLuK*`g(j*n08LiG`N&i=`$hR}93q*_l)qNmq>55bX5w0D{|R`cXxj@i6N{U8 zG=;ZjFes?Vk#49kw(vY6q5d)pk4&}AYgi-C;ilhl_qVDwd|{q)3t6x9yyVb8R-3^ZHL($%ygL7LkFJ;fpm@{VfGx_J92v%Hsy!xr0VhMw#K4uAH z)FrwXLv_9w@7Pvn;A0zk%w*h!YwJs*H1hiXa9jO`ji67<&-jhoc6&4->2vcLS(O zCG({c!M;HSRepu`&T%&T?)b~HK$ST!aM=}9c~H;s_YUMC@HV>Mgk+?7Nh03OSB~;2 zWFSq3Bw?}Sn6I%+`1X=v_FNQ6?;!Q9C|4qN5lh%r$YbFEA|*>$jQD%e7tBU6w!gab z!s@Q-d#eYdTdGqy^RDWF)=niZ1IM#&k@pNn`sobQD2OsfilC`7vz=WoRensmmO)sPgPKZ(RN z&Nn1Hlf_G}Hbv$teSoCtbCbyL*3h&MB45A;v^TMo(9$&%lg=kVl#w3U^VbrZNZ6vd zmQWSaX7A_(-i$J?rxTd+wE z@N8}{+Kk8zw$O8feG3#`9^)o#=@Lh^R{6(=>E^s_aI_ffx zEWvvCJdo|GoPp^(Db;A{qQgCWMLy+fGZg^fYjz99ZW5J%MCpV!%a7^m=v(ABG> z*-%|y)wb5mbpX$Xo`y4P+Wf_NaJI(XP~q%K9CS%)BqN~pL!cN>E^?aQA)rf<0XS#p}{AM~P4*sVt1 zHx{6o+30u$(d-x8y?JcG&~g@f%nexEXG6sGe%@Q%8BO7jD<~`$?ohon#4*pc#9MU& z!t8;`Rnl0{)LT*|i1NFPhw~r_!>VYaii8-}>>za!9%+MAL_NOnYcvI9Ck)PS=fiaH$|Jz;uEX-3`RxjF$-Tk=f z$6S7E4TfRNWtv&WiFrS^mtcYmmfz+@9`674?;h@d_&S>(S<4cZH}AZd$EIlJxvd$; z7wQC3y5}Y5wR^ z5QRA@sm^qpZX*hlT1IImgMC&Ct^Ba;V~X?Hr<4b+;=he1!7E}}a+SY?eJ=C!eSY6wf(b6vVr&vy^Jkwof~o8`^pTv{MmLiP;i(6C5|tNapB@*kA9J&y-@9^L*%$b=BjqA^@;5vuYVH&o@9&q^v< z(W8R1OPK{92*p!vJZXm@O`qQk^Z~hluMvbv9qXG1TlItmO zb163xh^llbga{iqqyk*!SY0wUJOf=Ek4%s?4^DF0W@Bv9#_|X-_SoYGtGdGHj#|m? z=Ld5hoX6*TX%=~K*82KIiz&PLWHGnm!NVMLBLGuT9zGlLO_yN(%bbgcc%VE}anjcO&W{JrFxfYR88Ezl5W7f3Vu+Q9(DmKe)){ ziHH9p_ev@U`wScjX<*9FBFY|u*iL&yv&>-HQ&7luM0$wjF@ufB`uNs`SPxP%gIRsh z{?%K|V77MX{{Cnx`pWEUi>kZfak@MDdUfx@8|RF*>$&PId{MK{T{{IhhA{ zPA#zOUZ@@{WClB!UzTp6+-|;=d3aEi%wX-)H$MVUp+9pn zB&~nDa5CNDw95Lo!9Uu%pqmpZ_u`0MP=m~1+KW&JEm!y@1LUYdW-z^n`C?d4R5F8E zy->&7Tg+g+-xJO5JlOwlZavWdYX6;Bm0-62q~2i$!y18YU!(&5Aca!lj6->YWbc zF-p?Dc%q~f6C6>9sg0JORC*-Qh`K-H!38v6$F*oYuN*Sxi8 zOJ*?F077)NVI@!T6Kg*+Sl)b>-3w=`cUJdA3sxQY?1A$SE|C==7jnCM$>UX`=>fc- zHs{bYTN^=#@l<69ScAbp(`sh0{UtM)BbVv6*)ILQ0V3jqeL{+-{D{(c+A7V=rT(du ze4Sr*`~?&sDj=1BJ$+N7e%T`>Gnf>1#TPk-5JCJ!#KVgg{{sjJxN0S-s!~`?g=_zKgw>QlU_VyfR zurs=r8Ej}0+KARNgB{Q{H3D=dO1uB+2Cj#qs%Ta(fi_bzg9RTFqwRxhf@K=6ogM}> zlZ4_AW1EI+TcEHIu6v6aY(yA)YJJ$p2lHm*B$>euVm40645n&Cv>1dd@z)M!u;aR$ z8I0UJqi!9e6Ho-4ZL<`6Alv0UEMBwCvqmASpJ)@4?=)|c<8AcwO-`{n6X|AFdkAqg zne|OGPL(FY^p~;G^kvc0K|EYfml^H;yw2{!_-Q@8-nAsE8SCgq$>K$+2Vx zb9F(WSasC0aXsByZ9LBS8vG$lKY@*=tD~01>8NFKW>gGRM=iS#??I~y!cQ?X z7}1nPP~?_1#tagO^KD}Wo20ZI2a~}|W-u%L?qmj|&4|ok$Mps?*ziP~n8E%!L8L>8 zxLHY<^=wE*`OT2<9K;O?A4S{{jB)pEmds$z$Wuj`q$S?7kjlW4%d*My9QC{miiGoF z1{=v`1{-lJ{VKY7WXtpHFPXu#D*XCoJme||7Dx-yer7P*XL^7cYdL4bB*+_735Q*F-Cs!JLTf;Ot5iDhB5YQ1x}A;-lm<8wZ6fkp?b_5uxL; zA-JJg$qXh<7n^Qn20Pf5%wWMPX&fF>Z|N4*x{Qa#R%TBOC1vjxE61v6B{P^52sZ8W zxnXTVyId2J2IoyUn-<5KH#qYlBmPMohEfCoqWK0;#{_N6V3g7FnZZU%W-uw_iZ5yu zau9zW@m^pCBhpb1s`~M8{!dJ-#GloPHEjJ8!GZ`IO{w+N(oJA{7;zKW7$3wR!t_(vXu47_SbSfQ&Wv_{UT61V+}R{bW-uqPv8%TFF7BF zKD?9(2@;StXfK!tGZ<##5Ff>$!NnMGinz)?X_H1L=bk$$ zsmJD?OD&@WlR?YYmQCD>lWAG9ArB$6EZ(`u$l){(lB?y+V8qz;-1CwdjFrMbxw0FX z!SZIGH-f3z@~1WgbF}FYs`~lo!5o_NQRKwcRoDYpKgh#kX4>Sdn~xA?(HO3_2vzxw z8>-R_QV&%t$V2oknZbT;%l&srK?qK&p`)IQ&=y>fM%7li2wkeLBhT#b9-K>C!wmK--Oda)gcU(r%nbH}Mx8coQSxS`-ew&( zJ264$-P*{zdV&tIFpb7Zed%`ONuzNq^rbAIOSq9h4eD)(L7~v7zb5k$i@EpSnmovN z)}(d;G(2f<&5{|+)kE|OBHhId_T^q=1`EA2@RA61`eR9wLf2vj3yIrWGUyLHT9qa`z#6n90oy0OXg zJo+yFX7IfoU1qTH8fLJK-N+0!Hk!>0HrhI7uwTKjoXX8yKg5RFWmvcMEJQ^j-V|>D z3sK%2>=$s-tVJ&eabBb!{etNMpWY|&UYL*FOUz(`ZNdzuO)xn(QqsH-XZ}7Td2=I2 zN5K2aaO=|FL(P5`b0bGkk#A;&0wJDGFt$k|Hg^CyYD2{(gf0x0CoBJy<-hGdS!&es z=Iv+PiIBvXNjKt;_n+ZpECdtUD{`cp4+ZhVh#zfcu<!BOwhO{{JkZ82-(Xo%wSeiFCo%f%wWCW6V)<Yh4Csezz4_eswS!~li)+tD3&>rg>h^2ch zDj*s1Yymv?PHqrlFTk~$AZgk^U6D$;C6RJJjyPx{m!*1D+2pv7+3dy(ba~PylgZ6+RqG@H{Yc`nr3@uYa{5SXSRPLtifQQX*Dz0bFpW3OYoFmw|?`R zMHXZAYh~M)uM2bAY?lhow%adzHD3XE%2_YkEVUsT68-aB6x|t>%wSSV*chH(Y6+6^ zejGun_3g0;QK5ZNylm7jd$eQ*lftg}B1d5d@fQ*AHfFGik{L{y!3IX#!wmMKI%%tb zt5U9DG&bH0>>{SCD4D@jL_FGd+>Q8NO=5~arL5n+?T$O_Vp+NkuUj&MN!3(js~Zj-EpU$H!}vbG>RL>erbCCldc~F4 zwSyUKQI|7=fqSRL%wRG3PV*)?)`fn)B{LYorFI&)t|P21Hr`r0R`o4gavB1gpLjTh z`vB7#WCjyFs>P_18B8jvB3s?W3UOVJs2iBU7IiB#*x-1pnZf>#k{PT`7Jv2A3tGBF zlY?mvxYN+o&|tb1%wVI+Xj3wS1+_$lu?1R(Lj7fy%oJLO=t9wXW-zdVortw1=DDs! zk{Rq1J;n@%SuU++2K$$dE;50EvJ9g+0jAl3aU$Y4!cv9%MUb;BY^4INLTiDgtJD$ZOxA%6ojfG^n=6@%Iiq3o@bN zXdQz+$JCOMLs^OVwI<{!f3XQ%STcj5q@$=JTisk0#Hq0?nZb@3X0V}&Rx^XWE_zSk zHPPB3w=+mFk^dxJ_D&&6E0sUy+2(QnY_!WaNju#vtG%0(0h6-E^~;fNIRA@?8_qMn z27d@8Gni9teiDU|#`%VX=PqIf8-p)a9BkG`$qXiK9h>fC2BXc0%wUUpgc%G>6k~%c zrA*(9E!PmD?>Pjx>v8rPW$pFAUS-aLHqJ1v+6i>e!dt5ie=k%IbR#oZxJnv_hm^YtE7^8*9u(_{B!f5c}Lv8LNSaMq~t{HOLGmkVR!9Q7xYtY_wzslM=3IIm?z+ zXyJK8dVv{?NJl-Wf@Ie)gN=ciq1DV_pEa;+AK+C`k_LF~vbZ>#L{~4h!bNP;fS0tm zya##GfY%C(%T2g50k1)3Fom*ukVk0_{0r$>=fjx&h@~G9!Y#(Gn82oESzY(>Q;w(kYblBKw@QWr9=%=@u@r2=>I0USI~xn|EH1#U_8|IU7bNXG*%~0V9L? zIIJ$pgoD_l);Q~Q9?W2vi6auBm^+-=L*mZh0ei+g6n0cim>FX!;wt;_6%7QEb0ulg zU_O2>G-If0qi?#_q@n4{qNjYGWznu6j;NPRInJ~DFz%$J9-DhEwalND2wJu#OK!!v zG_*Eks*QMFsLF5LP?e*| zdZ=1K9z#`%r-p`%v)4cn;#x!1XOLj=eLYu4kT z-1R-iCPO*)5y-JWhD4~1trz527A@u2H3f1ktzj0ZmF#|IFz3N}{7(xr7*+&nF*Dfr z8g<&VIq1#mNSk%o?1aAb-P+2#T3^Z!)&`sQQ5xWwjJq8t(rDZYeJP)KiGM87_%<9t zp&+o?fWId55sSHx!MGkX*l5WNCWT({Men`WB;^%syNem@$)02e3%q)$rlVv_hXM4D z*YR+^%wX!&Bc>z~X>Tc+!34uHUESxk8YpWk9awh^Dx*^MnMTDGk|W;=E;F}V#|$=B zGJ{EhS6s1kXOrg{|1SP!@Vy;fX0WjuX0Xe`Mn5bgxC z>I-**ZL*TFHo1NDu$dlG?HU;FoZe?hjVG zJnAl$-5*@!^2GhY2fJv~@v8#0;jr2zAi&X9m-Im@kG|3C9MLes0ditui<^>gJ@Xx7)L@68;e7rG?lF zR>IGs3TP!<;%eC%M8#K46x|iXUqZaMn8A9#C#q!zo9ZEEu;F$vgY9j1PvtyTa+PBp z?y)!supaB^f$!p~>-9GlT69{Ij9<5}g=^69};*VWujq0I6B==0~^`@p^uQo$$`4 zpEE*_d1ur6QSnjU-firID)J+2#5;Qo;Kp0VxZI$3HbJqDZKDC#LD)BNBO4LKt22z` zdJdM%VA=xsK^eN*u##ss6z`HxOQj)GhSNF z4EEL7GrJ{tN~z26l;3HFchM(b-R4b`S?54<>j#j%YS(J<%>tF>#Dn#|7dRAU+uqn z?tuk!<0Uf~B@1}zV8-_F$Vw@*jo8AkaKRMzeG6z_!-(S^?CQ)%Wc#;nC31^}9Z)B2 z6>wF`6^zEln}J=#bQL)(F4B)@S>LCpPQ<`BDGUpk8c4qh?`hzTs0UO6IW9$578MD= zqmoBgTr`l*o1Qp}yq1TT8F;Vp>3!3Tujk3S!tlz$0m;Vk9wF^$+i|5C$Qy+lEnBnW z@*B19GR|dRWuB6Pwp5}euZY1rEev1mZ%H_(b0omqT3O*#MPy1Yt&1ljEptB27|Cng zdg!rKJdw9%*~suvIG^S_(3HOp)KTS4FKEhHs??O9>9EoUJQZKsQP(kpy*a@Q_VyGr z*jt-s277A`GuUa}%M3OFZA5FC!M>(zY6R#^jfDFz+6jyEpjo{H+L$vSZH~Ck&&krj zIA}7^Q0GcQw!yMNG_|-YQ>SN*o2*S(w)n39zrE`KjG}7(dw1k6hEPIRksKk^P;%*^ zrIJDo0gfU_4Mj@mVnaX_MLtCY6huE2qzfpDl_piCNm1z_7L;m16e0JY-z$52xw{lh z;^q6_gS?%coqfCa%Iv(Ed2ci@fr2UN8T*yxfE5e(5vG@r_uAG=3>M{$48|J6tTu_dVFJUfrrZ-EgBd+LG8kg-6meuQd+;4MK97#F ztwAI9vX+xFCgj<&3=_bNLVPwAzyk7NAd}FZfg#9cO7~vr1>LCaE>@;zZ`8)?gTJUf z=Q9H-v9_fP&MXj&9?2aG#I;7qC~+1TPZ0660!9X7{77mWMD)TaZ)7l3r($L~&+Kym z&xs6X^w`K?mZFXfcF-FctW-t@11rG*;;acO3}Q|B?|z$W^$U+^52?yp;azL9U1Jyf^ITF6J<7y z#>$t%PLvC~(S(_LmX!BkaFX&KU`$Xcv5kN@o*SGbyo@eN7=%)u#C;sEW19j=on?fI z=Y3nsPM+XKl}hjCJmr;R5E8OMhfyfsnLv?>$MJVCl@7*Rz?~+d7$M9{3{dx)U}ui% z%Uqn=8ySqXqgk{j4(&AXN`k$S!Txt5gM}4!WU#GF?@9a`+*)vMVUPk6{}`Sfg+dfo zD)k&!3(x24P`~8LPH$u|;>}bWuC~{3j`-b=D4qGdqa|uO(Kz#YsBDq&Wpm{&%Pdiz z6B*1B8cJp-HOW;Q-pF9A5h?S`$Y8J;Au^b;bVLRViz=qbU}qfy>42{mRuV=#^HJ=$ z??zq1ONnzK$EwyL0cr{okULI@%R*O7EdY}a3_K*w+GBm?=YtBX zzMa}Z+u6(#8b%wft4ZZ-?yT(I$Y7$qpuLuw2JCVmQx^h?KQb8XGo>IhSXe~yLJUY63XFE-80pgdr66|mp_I@PJ&S3aa*;)R&Q7##delR^e49ZpQ z1e{_?M0q2Fv8pw*oM)*T81`jPj10EI6C;CZcS*za5PLd8C8$%BHaNYF$Y8W98s@f` zvldna!@5K{NhMI_FC}eo_C^MCG&rLzpp4}S0vb3YakK(P24gG>%0|d&?jwUmc_V|d z8aDHKW_h{>h83tZLOan$K5E?fu@gpSjT#Sl zVD{M2*<<^U&l*I2NqF>DE7hnT z=(Ch7NimKKY#r&Uv%ppq7ME^RG8kR~BZF~PmLJQ5G>5IhoIJq2k-=m$gO8Mk$YAc) zo#z+D#{J53xn~?|q9iz_c%I{W9Qg1;CbZCz1|J-#^I3_beQnK393~MmbB8c{FjyEo z$ewW<3OlGKxFWtU^Tp=QcFsQD{zNBzy!`|WA8)SOaQ5-$cyDAdMRuazYVPcPr!5_keIFPN_j4~p>>j~^_p&QUS`92tn=D)Z)7l8<&Y~q zF*2CD)#nA_sjlTu>L5H$7yIcY#8vqdY5loo4NW6@0q|9f1mdfGaC$qD!Dtl?mpqy6 zn3;>gO1X{rwzw+Bxa6u3s`BHiW}=Z?72>Jns<|D4Bv-wi73jh^P|8-Ivo@w0aZHW^ zYk#`v%vFm*V8v4t)klM?!l96JRWSzg;H#Lcv%yl}73j?IND8vj#^Q|(CR+enNzacA zCOkO(iY7AH4C|&Djjbzvl_~MougOBVoa(??C!l()p{h!RB_oC%R-T7jXh)DDjturu zL7g_`8uY^INDJ$*8A!D%)dyIVBkeRrxj-ilO-J^gaLPQ@-UD99J0D(ECjNDk3v{vx z?aYm93gW!%J>d07b{W@EUy5r9$XEh59zYPdvFMD_%HwV$aL|Dl<7k(6>BPOWCbSE# zBZIlyiPaJn#m(e=C)W39eR+3sl`79(x-_gWhmHvA%X25Q2GL9dZy?ySB7?nH8Y6>g zy?W3DkZfT|rIzT7)7y;<#+`bYDT#@+-pF8_hq-cHZ0doL!N7i~{RLNSK@f2~!u1_I zdO~Mh0WN zjYS6IT`)K2gB~>Z%-S0nOt$Jq0{-pDV38gk84P^b<06BF#}t2LurJwkoJ){w#SJqx z!8b`LNdd7_dnPbIxSX69II1H=V7c*75W$sMmvuH!adj)-O9Olh#wtwD`JNJdFO39- z=X+_$y*FM_X#$jW8W^)0NrT%skJD#BjVj9o+yNKGwB4CryCD(yCY-ZuwlcJKrai2I zl>F!q6JDdzUhMS)$0>niA&oaO}XxfGhg?DxEYi*p|e@2Y`R9oIhgn17ao`sc(i2Q0kiji|@ui z-XLHsl|{*;-PInW7sMyiF$IWI{=vaI3+E3`QCa_z)kn)uP!9*pXgb3u2ys^O(Z%rT zF$kf9W_PGcXm*y?f5hO7bQR}rzf=AtlD-(yO6ZLYCfns50!mk8u+sk}${iVOO6iFV zMtcNCL<&vTEb2PYyFWum(gUu*DRZ>a>6A=AMMsHHieh(-W&>B_4kNwwUMub|mGD@> z)XNjTSeOLJFV|WROpYnhOj{|jSMDR0othz#EpIE8-m0gY2EMrh^cw;M+S4Z-X-tI zVBn_sTJY|yT^Yzb0s0eCNw@*3Pi!6*O%Z5{Ix^UNyJt4DF_5rJ$?lk4SjiWoTk2k* zJ&<}ER2LuleA^ni+Qm$GKU^fi1G*R9ZM>1e47vtX8_xXHQ8R-<jdZv7O+={JDu>Ii3rTkUy;RArsZ_6!UE>9} zlnreb6^=u?23|+7c4u8a5p?9P@>7f3pn5Fs$Y4?4$Y78x$V(@@cp`%>;ZE9|A#<)Q z?ZB!TSO8L2;bzB0O^5_KLQW%)3Cs zFmX$inwK!#3Ir^Hd3Pg-R1)B_`3l2C&c z#OI^)kcz`J^ur0BNgd}!K`;9U#3(6IYyBx{?x$RH?r2Qx0{zA}woI(y5E-n7Q)IAe zg^mnX%}r#mJ3Tlu7-=JlHZs^td`}GxcZSoB_zwYE{wEgghArn|^Q1oGjSNP0piRZc zuE8vwN0A(uoLysR%He2#D>)eR)LoRW$Y9al$Y88}&GuH-Y%8TGSR?5Pk-;`)N+q%WvL5*BwDDh;+S z^w9iP3^pVhnILygA{pWZ@l}(uqgIZTvk}~b`AQJc{wC;UD{JZH%mnmk&tcAAOjYjG zw^-GA)%|=y>)dyDyi{(1B&AwbRHho2PV!&1>1+ zm?*=BM64q1V@q{W8q|S*IL~<4BLB5w3Z)DBYyNf@gvS{O9MYjp=ts@ zY9;2Wk`!Y?;Q*}z+(Md^7iS`$@i;{V^QXNfZgXD=$H-vM z(XJAi*6!9_3U-yquwGYsT7Oj5y0t9v4pfqsCH0B4-z2SZk#WJ$wD8cv#=6vE&}QVb z=Z{(tuXP{R84T+Sy2S)^npoXJ^W?%>o66A>rPnW-n)3u$MI<+H6!y%7m%<*bO;Xqc zEX?Wu*y}fu%A(}aUcao3`Fm<|IRH6F#SoOk&Q2r;ojZ;S$`Ckv~y5YQO5=Qm}xyZzlMU7 zCuW5L690tmli`>a6cED;0y-%yqpw5tDj9t}g7ahawTMPC`iBUXj2>_^`lFQbB4r%U zH_?>vVhtXIoC)ePaGxv(Fl;K6GN2}u_W~iArYD4t=tu9v`y<{=CSH4TRzIE4@|`7x zq7+DU_N2IA5wu;9nxq8ojSD7Q^aBE(C3$YA=nk$V@M@Bnj#m0hA=-L*NZ>&ldPv}l zoV!|XjXIYDTxafT1;`ljyr_W0beaFheT6IP6Yw3ED&Tu zs!O@#gi{HY91O4!%e-;H#IgbOd1p>2dpT;(T_BxMx`xC>UaTf3an>H`D?g(<{H5&F z4!TZ?3l=5y24HV0XLIKp<&6u*TEfvcs;a=@(1rerKQ0)oGo>Idm?fro;({G@U}#0h z&Vs4&Bs-fzuw-X|p}V7$p%vhk5rWeMC~Gw^2qnA3eX<xoJ37sIxxlmu;PFyhB6OHL2Nd_yd2!?g^a*|4*%3rkNSV@?hy>Y=X89}mZ zARYI)g$O_#O?D*7qulIj8x1;W8zG~)j|&#|HlP(Ve5}bd?@U%;?dfivL6(^rWSRMzEHk^5 z{$!!)%q%qEbSvp*7o1KFtAw&kgw@F>60f6Oz>7LASdL_N+<&|{7@nDGN(yYnWpWX{ zz@tqr)uHdEi?~|s>tJlfyX+pJom;0ldS-`(i7u?xm$Z)5T5E<{^T8@BrVD6 z6Dcm3W(5sIZSYl$1mdfGaC$p&!DtPQit1 zr+m`G#XiZ8Jaaz}*2b*%w3(y8+Mh1TUty;z3V{`+C8|Y&&x-ZuYLCoMgk^*UUVqL! zkEBDnw6S>Og2@(uR?_q1f(idkU-$kzh4J!+j#|3-0piY}|H}b+ty@mDI zED3#S9Pj1cxL_I?*HK@J3QFL$L^-(e06LOFp`Z?%a_?^(Rd-FCyo){M_BEofCu$ZEY3-+5gE|~J~Zl)=m7&M~=AXjEczwNe! zab|2a#XX#{xsC&a?>drQrRgZ{p=1*73K$oR@irD0jCVn;!%uo=hEtbn%bB$|E*NV7 z$~My9za1AW!o%Z&fe(9LT(Gd>j|=t%n~tlNCsL0>Ln;hW1T!dCCJ2CaDQg25U{ z$&dcP0ljg-TC)1keh*Rv1~@(e#7u}MVD2XnUkFmNGT-*X#s%YF3JBTx#|4XF5g_Cz zM1Dac-R<=eWpUUW^i^70zluJSTyb3**495pb&Iw2r^PHCZiPr@mh)_o28R8sbj1ae zJBJomT(D(%#sypE5EpD2iwic7;(}HDUx^DA6IJwa!KM~>v=#bnx%^z^u}7XaE?DvH zhzBMl8IPUUa3(4zAdBgO^8}=*tbfVsW9294AH@aZUlG^?+2=%6LbJ01#s%YLNM8*3 zCGy4vlP&cQ0i`Q0Sn2-~<&F!c=$419GPLPL+W2y-j8Eq18yXcz2waNOuG?TeU&JRu z3zmeJp5~d&BP^EUhzqu`xW81wV+AuYPxxX5QPW9Vz+{4@EdX#h{ZaD91uLC#!Q}Vm zAAYqc5`&yQ+1C$8&@9RI-eeZBk%B!g*lRQsDLwNiSV%E{`cqgg#ld0zl)%OX&sNf5 zJJDAZ^DS3aROw8LJNnVzC@OTcpqC<$TxS9r=~xQ55&i9xF9C!|l73@@;c*)q1RFLs zcz^5029I=}GEreGRP-&ZwoSBVh3}QHqJ~X3#kQiyrWvWU`;4MrHDmtF7az|%j?EKp zccej=C`ms;@jUV(q*W~8VZp2l&`_|oHl-uge{Y5slwH|zXAjWqxCO%134ei@K)O0(G72P&`rHSx~X}kinlhP+6HgElm~C^Xm3O& zd3s({Fn6n6^5>@bR`8#$m85wmC}DoeC3lJnM$u=AIx5&~yI(dlI52(+djtDdc!rAM z%?Ev7CW&!FW?$A(_|PwTuWWpED3vm=Yz#nWS;A2-gL-vls70lhNkpx&1ig&#%C?Vy zJXk8}UO2xjs8@Cj;?+o}Y;|>^H!7HHfOQ0TT2!z|Z&WZy)+Fgh7f)2MSGkKemvFh5 zD~-acC0GDbQ{iU6MQ>Cv*Ac%;X;d(9OK^s~q~TVQbr4nYMForTMg?Q_Y*uTV@1reG zAw`}cDf-`x3Rcr0Dp+-=s9;qK9Tlvqo2XzlJU1#>G-)G>HY(U0wm&WyGKtDOqoerG zoxu4iv1m7JIS-2`^%-weFgc3EvG{DDV3y9ZHddP>aplEuf}CY->Drv9@}hJ_1&i@U z1!K)_W;xI7UbCJP70lPOqk;N4EC&e5PCQ}%a9$sHD{ZPMPB;r}OK0+( z?Np9_=&*q}CyC_}YdjHX%;i8bZF_ie7VFFc@);7HP6%o`O96^jJFq+e-H(=89n zyHst19>%`cNFskP56in$bAuk=mwz4=j3R>h)6NpNxvPXdcFc3uXRW0xDj2PBDe9 zqqnHUq7Uc!t{i||*uxNX=BRSe;TPZT7L|0Xl8lTcaNWTKf$J7k17^c{Kupd;kQ zdPFoo4?ZnFytr*T{T(3sKl0$y@*@m-@ae9C7UwddM&awSLiK`LwSC2oWOX0k?$)I& z4%ae@y%lNAv@WZS+%eAMvKLm*TOOY~(xc$%w;AcNv_}OCE$XOX?=h_>)SXPN3B@NR zW`)8L|Ag+7;g~uU5W@?C+fawrp}tX`b(X$LJvvGk1E4sQa@;nfBt&OyH$mzDaa1sH zQ&d4-cBm*2umncmogiZLB5a+U)Vub|D$EW-6gvk2z|_?2rRPD>|Jhc&}tYI4Xb>Jz4z|?c<@1@b zWDTBRu90(f_NHnkyE&i1qod1rR!NlF0?dn@3GK3AXKm>Y2yLSuOb-vsUo(om9t1ao zYE`Q!g&#c&#Uo8OlABp#-T2YxlG7d_Ijt4RXdUZD2i@Ys#Mz)3D?Oa88dV}V z+Xs1Ywsf?DNNeaghv+>$Di}B&^q~A_X;=T)gDT-CmBcD~^@(Jyjw$-6VAmzHr+c-|Al^Oh3N4o7V%FbT+50yiE&5QJRO8S`bvL^#} z;og{FtisJK=UFoiyn$foQ#~gp*u2sh6HM#V10@|KTi8*lW;^5bc4LBZmmaAwAlbIi z+>)LyMzo_1DVXq5r88x_f`#Xb36|uEF~P#4UB?8AExMRs z7rimTyfMKF921Q3HWm|%cR{VYPkLvDQw>CNX6=m$CYj$x0{-ooVBsDf6AXOV<6?q^ zMHPQcupMkVuC+WtLn;hW>WUf_$1iXKz%D1}-k4x87*X=0KUj6VF~M50`rx&}l?*8Y z102U-Cd3mk_Y+9d|J#lU#=jH=iwPFX0!heEi2Qj<#RQZ4h89;$u%&s% z1Y7D56KpAq2{xBvf>rvTi3t{3^fAHy=89o>I$#Ya_jzFJJo%~o2C+{NGVv{9pme8I zk)jY@iYUy@=PHjK^1Ly@if=!>$B3!?PsIe|UlHh_+2=&vF@T*FFeVr;L;7OKFOfGU znEVozzL;R8|4ZZ)6HH%fVuI2BfDw@~&}A#iEc%1q{TVuv9&iOt73N;zZY`}QyciKv z5({bPdSil7W#}>{Q!X9){!1{o5dG( zq-lKrQDHoyM?Pj#`MvpvUoAwyk*+POhjtz@!DwAEl07EaV)7c|jz6WrLmSS%@X-F7 zw~Cm*DvDWc46QMnduZ<@dbxWT_k4Blq1~U#8BJx6D};ykm*QPCub{3@cITn(7!z!Y z^>(6yP4~R0V9~Mms9sWP*0;U82_uZpk~eBX{NB7JdiT zXbhmT2jszBrGqK%XheTo3cy{pkroxp?efx<^fdl3tq&mY0+KD2gcG3pMB0spV$aB! zU}zlh(|UBII`75a7RbE#sSrhoN|m8!s(#r;!b~x=`GEJFkYGZfD`g?USOc?`(q?k} za3L2X$eEeSF=L{ut{h%aUI;Quc4i8JpC`#o6D5K%Q}i$rY1QtSpFqn93*?kdoYfl< zjMcSSt#PVr4ZMzEPm2f^;f)9;B7#|pCnDHOc0D{;Gvr&wqAAM_h?O;jc54R?&^;aR zPyE19$p0aXW9*@mZ5F2}h#OqsxUb#ivqFr6)QIDvpBiSfX*}-31baJtiVptT!SU zwW6cGA)8@%1{v}Ub-#ZzBAD4BB3L!2h+tI;9TBXGn}}f5JvSm)6lo%gHX_(8;?B}r zN7y*QnE8LEnUF9}T(V_HR&3D3ZDcHqi+X((?C?{G^{2ip*Ro}>Z0I4tmWjJF7B402ZzzOeZ1lCA7-KxMmm_FuI!T3S4fGz}77E$C)!Q z5N}(kn17dDx1#rOX4gUoBlO9`*}GEakXnl~ccM1jUce+lW*4>Ft7S-08-hGfz&uPK ziP~VUm}zpbeRlR}iv|u8aGOcP)P2`nEs#v_Oyw{eXoq2=I`p3ekz8Vuva<#cmV&&9 zwiD}(2*z5%%-e(I_9arD6A|nVkB$h&V(t`iL@;~Mox&@5(TtL@fhCn??HZuKAasX- zG3+pqNn*?Z%wUKZ>Vbh&vH zHl}p4b9p0zp^lMO(w`?p1iQmyBZ7q&bwsc&Y!6(L`3f!Tp}}0SCdhP>H9@A6tO+pW zF-qQuU_v@erOI$-O?R_Oa?hHWbcStf+1-%5pu!;5l>ffBxmLdLU^apyNpCT4L@-hR zr6eL4MFaDveI;%)dW<$A*sM|&5iBg0*0&UOM6hLCd&xAFOm_*TC7Tj+2xhTF!jV-ZDS>+>mpYo-41@ zs)81WF7#LY5y4=cDFqS1LZgZ&BG_IBhE{a!ESMTkva=}!OLhiWx*x%w&G7-sG7Y>| z0~4sSOWY^R0Sw`hl1J}`#x3>yMeVul<}h#>bm-{LGx*wq9KYBdI}_Sv!OmdzQQ2Ak zno*`yRl|olFf)oF5$lZz#u~uPa-OAX;MD|ABX0Iq9^9;=hCZF(rbJuLz>%`SK_fY# zw9tV9mbeE***KR;(yvgXaBrEYDBZ0ylz94EYhCJz5y7!B&vm!iCw= zu-+Ulp;!^A6VjFxq|B_Qd6uAo!ACwP`a1=^l*pvC1yZid<~I$b!+0w6K|$|Inv+fq zxC0-$ujNYsA(AZL-Foxf5y9N8IL|MBjr%p{=olrrN>V(JVuEQ_ZCl z&a2MzhzS-#!Pg{vGm9$5p`!+dT=@af`wE`vipOfz zCH;tgFcms94<0Ms9Pk+M*q!nvfDkD+kCm&=Id65h?z|uzbtOH4KTs=uQh(Ac-!2L1 zQ+*;?Jv8fQ&_Lj-4d_Vq-kZH`eVn+PX{!Yh5hWpg(h3@ts}chh*5rS{QZc|KOU1Cy zkENQ4MzU1Mro89qG63U~L5aBoaXfbilJGLRC}9wC=AzHQeX<PDf zgTL~T#_!0c!+c_2%kto_HD%#+1b_7rv>G%Uy%;f())v+k+uyUjXI-AN+*fZ~-eYzA z>K6`B{03+!Uz~}2#^b_w(|5^?f#kijbcV$?(7Hl-bB5iQXT?nS*K+&$czQgruvpp& zq=@5zEib6Urf}scbcCD2dTW-1t~8GKIL$72oXJVX<_WvqffaIbAouXVIcLTgbn>0; zRC1W*#f&lhknGIZQCEs<3CLIiGaf(?DH96ntO+`>VjS(fm`?Kc)bz#!V-;>@InRVF z!A>?%?pg7`=9b2IU|Nr!YE-2ft!ihS-flcF?$E<^2HYXCu*y}mvJ@&Y#-$H?Fu`}= zB2DS0P>!)pqIbp=%Edg?8xKryMW{WUxnga?BDv#=Y}Q{?@xaJ`Co+sr$XPDsOSmg? zWvDhco1Kxr#|9kbDF4i&Zf9s;5ZrXcg4DUYbv-YPp#<6G1 zndZN6#5Cm3MZVF#gYM}0aU;JVzhC^WT-;E$R_{mrD`zB>i`?o{{?*1mdQq2XUcGm3uz=QY1^a-ie<<1kePAqvQu)<%l=CBGs znqNLMr}px}t%7zh{2^%E#AoY-{T30t(C=7q`wfrQy>TV5-hj8a)XV(6Z~bNO+^XO9 zhXoCypN?oaY2Mz3b$zlL4Lf+F(WBR&4Ouy=cH{P8?=;@qGNH-Jr}i}&U9nfwP5aI@ zZL?{3vt37jX;!1=#L&Pge};agJZMQB+hRXd;aX> zvFEQHi#@-uS@XrirZqqR>A~i&er;~CeaVOxqv~&HvAy@L7Ji9|E$1Je-tuU`j+Wi8 z>szgv*1FZ4w;yP=f9jf6X}^5i>iVrJt*^Y9+`8wFV_Hw#vZ(cI&33d-4ZqO(+GpkC z+Wy)sE@x%OxO2bWANTF<>2ZIDEQ(9J`|Y^D=534X_41*(FB+YV+m&=N?#%bU$8D|n zcU+V0Igq&Gal|?BxDGnd<38Mva!?-1MfrFRo`>h+`FIb!58ey!hxf$$;=S?y_#OB? z_+9vY_?_(c((lIaM?J9mpn75TL-mCELcO8>P>-lj)GO*2^^E#Py`%oo4rmXw3)%o*LK;`t`zg_(JZ%zrmnm4N|Vc%w|?CC@|S-Nztrl= zs*58QU%asCo~9ROW{v*2&b0ME?SJU{`Tf?G=X>5W?Z-t&cK`6nlNEnB65aFrKd!v- zU4spm&JB4!_S}-Ep8R(A8;8%n^+TPr!S{|o^NVrk>3vsgoX!dyd8)^PPfx~V-Ffmq zPmejV&;N_#gRj*+{%-oTW5$YSj=tJ4?&zAbuYJ?AgZ`ThcMksgvx#4P_0;`gUmd@( z@W_ize2zTsJLa(U`BR79-P_?%__j?4tq)iZ&c5>Imx-2|Uw)i0_dsmD@(0eJdwT!b z$4vVh*`D0@!C>EgBR_s-Z#8|u-qCR{?FpJxd(Y-|tH1dCQtTIN!aw_b`;)ys&$w{u zvuRn6e>U;2yFLqB_3rLvlQVX&f8g@2dlo*s>&2f!cWoMWWM_?9kL;}BS9fO(%Yhwz z=0CclMyn<}1~fRmz2&_xY@hQ@`u3KK_1pj0xN+P4ArEh>f4TX#6~4DV&3tt0r=vPP z^{HiY=TAQHQo|=q}G<$PbzOQ-&J-?+?6t04zL2ZZ_CUL!eb7#5FSHxl5ABHd zM7yGW(avaZv^&}#{Q&&|{Q~_1{RI65{RaI9{RsUD{R;gH{S5sL{SN&P{Sf^T{Sy5X z{S^Hb{TBTf{TTfj{Tlrn{T%%r{T}@v;{f9U;{xLY;{@Xc;|Ajg;|Svk;|k*o;|${s z;|}8w;}GK!;}YW&;}qi+;}+u=;~3)^;~L`|;~e81;~wMR`~Cm_{r#sd5HH2S9Gi{x z3G@pB8N4NKOI+93#JHZdceZ}&V!PJAJa?$oHKk9hc9G{>{vI@;Wy>vwmLD4Cwn+J| zZVO${51Xg;?AZLn6W_%)KK@AThW6EB-)Q)D%-H)o#GEu;i2mZn)6v$JjiPt$_#$fl z>`_sJ=2wcc9e6*oZ}a;i-`L|5Sz+3mh>G2ML`1|JBAT^c8-66cclh1+`Gwb*_+glB z*08YPSMLh@W62(i?v=+Z7pI0>9_n;H^a~`|py*W8NCv_`u+X zjfd{O81mHqbs_(Ga6-tp+nR?MRx2SBn(b<|x81Xi-pc9L=+ic}8ttt0W5dZa);0Y2 z(T5t|YfEmJ>{qejutmok>|DRBLH~~98+5oop}`wI6&gHI>ty{p>sQr(XX``t$E3Bb zzpTw&^_RT=bG^-rKCaj6w^{X$e|TTLcP@w4v(7fuOMd06y80?B>)!L*qjl@WX4ZZG zyLxrU{Qh_Fjlo|A-)g=rxM}vI!EN+igLS_(3J#9f2S0fJXq|mOzg_3gHZ$uS_;Wy= z2z|>srv6pygjKl`^u}GE1*MH!9CX(`lY^>M?->-{FCyrX>lK2o9lua}mH+PAtDjm@ zyIiNKwZFUXzS6T}J-PS4U!1&ne(A{{zMXpVgIT>#-uHdf$$b|pp8V_8 zpHJ+$we3Wx>6H_{A5AzBR<+}a8P)5ZII;QGahv~<;~(Ezb^PG$X~zvadK@<{XnOp) zvSp5^-+lDhv7K)nJLf;`Sk8rR$37X*@Yu@in@2ka>_1vJ<@KXW{l^_m7?^ytcUsk> zJwN*Xo9Ett@0*UTpZMlv`>x+Sd^YHt`)*wQdi}gjU;p>*XTEOUzQ@-u4h;VKlWSML zdQf9dqOrW-t*;oG;z-Q4DXa^|-8KCiy5tnH0YD~xXZ>7>f|X!^s)FTL)Tye4wf|N4LA%NB2J5ZQ9gk z-414d*R@rhg-eLV;?K&L(s&a=Hnw)6g;^va}feEA9 zzj7nGef9eK_BXfhX}9sZM(Rg zExoa6U;3ipSJKzKF(SRel$PlSKK4(4pzF!BD`{)e0$zG7ZDV}rv?B?1(h?S4OTCh| zJ9U5ims5`}8I|grk(k=6L$%aHFaMnKaP!S6eHzS7d1lbClre{OTF z^VT*MeP3!**Oc9+Z^x827f;;N=I^(!C4ahSZ}J0;mnL^TFgf|9_q!)gI~$tZy@OwJ z?;Gcmj{UeXDX{8GNe@gNn-tZ!L()`X#L{+qDw>>~;L*Y`?j`Eg9b{nx7{93FBl{+F_c<7V*K8vb8iGaal`iZlZ)f${P6l;^;TcE z1;6}t{Nx?=NR-Z>%iPG zHap-ZZrJ+;>)Mr9BTXNfk)e1UEk!g z-~3*-KAXO1b8*L(OLd=bZ+mY>wUqaK`&^3H*xL4Pk3K1f`{*x4C0K0FZ2oV`=2zEU z+?E_{i|TqZWzH)@F0Q>&-S+thRa5uZt$%UNFn`;;1!<`@Z(Y7%Jf^cXcxytc?cAmd zF+={$$#{2B>Pz$IU)U6NHRs0%H>PIpop52-h@Wy^JNR|#e_HjvU<>&!=lw+&Qd1YE zU+6jSOwRnxf2OXV+v>u(U8iz}h1gO*KM{T5%`>NRR(+F`dboDXg~xB4$yvGUdg|Fq ztuNGR`h5;rI#XNqO~3H%^A~agW*zv{4r;jD6mg{Gm^Z@zSdo|9)zn?eRJr+RQlq z<;C@(2W=m&?%$@tG2^Abv;MH1pXJ-e{7$P&H|pG@?7F!!xpT9LmwF9KQ6@&FC$}}P zyVNgmtkP`sxuj_8g-ds|e@(gLhX<2REvbLG!I=Zf#{K?Dv%Vd4dGY~+Zg|$BME~<| zT>h$JtZwY728qwkK6}|bceE~k%sUB-J~Ur>vi(Y(rAusrlGN|Y(;+|TMt!g`{+;r# zU8xcjtUq`tE`FPG=E_|2ApOCwHpeB|0>gV`gEFwp9R<66l#D zgurwCwW9ngyAp`*Co*`uc=tuP^FBeSN~S*B5y8^$E{mUXFMyQHj^*^p6Sr z6vD@In9;`x{1(ESHTXb*KSOx_`n(+b>)XWZbG-faZQ}Jg-v0VF@%kKZe|?*HeU2B8 z#mN)_<2^O6Z;RL9HLq_oYw()aw~5zhA~3V1^Lp zDmg*fX|TQAcMh2U5GIJK+D@~OFnU_=WXG%^jAO|go$mUAFqIt2IpcH}*u(idv?Z6J zhMMm1J~aq4+X2&F0p?jxh9S&C`D)Oht$OgJBxu zP#cwK5I1(f)Fn)^115$rzdQ7n_Jr|upy^8($5tLq7&!jfYhyZLZmO6U=`6kT$o}Jp zGJgdgg-nZpJ3~aS#bAVrbVfM_ptWyT)n?Qn6cXcnNA5*txjiSON1G_YRZLs^W2E1O zqpO9sNKs69sPmgxqFvykT;N>%Zi|cRv4lI{>x{94IpZkafzvN=vDp{>E{nzaZdqff z42z53>3D~z5Q~d;2y;~-E}AgRMJ0u~s3g@PkzOp!MTODNW*tzxQkaYS3v*FhVJ_+* z%*F4Pj~B(ur=gl$l9G+5)Fi$pgQutRMT$(lX`C)l_L9O zvG~|T(|BL}{bu@PXfdQ+sN#qT=i5nW?jr9x)V>Bo zf*bS}8cY-qwxGd8D@uwZO$(gfuFSIE{cjXC>O?}U^R=DCQO->3lpwP%Y}(x zL7TOAMJn@i(L^b)shE=VUZ;oVl9(}SoKsza!mrS?8Yd^l{*no@#cJAbd}jZV;Djmx zTpnfE1h(WcKTn?6&~V}R!?_PUc`nl!<8v8LbBWz?;j*R%tLhlb2??&=^R_#U-il_b8gw5f5t~?u=j>-ZI+*M`uy*O-l4zP z*YxM|TF1(4?a=3nxo2nJ%=f#WJpI#&a!E^ndf%4Vv>N?{DU%1asf}aK6TKVbcuO2V zI{!x5y?gffKYK2wJmD+O2~Mv>+_&n&1q+~jG_P8T^&3h&{ZSv|iE|LZ;0&lyK8i|u zgvfTqdl__i59dV8iX}cm0Lpo~9RsgO$uFpRDGheQJU|%vOZCb#bfz6USQSbGOO7Q7 z04~OzysRa4j$gttLWYpH@SrA|M=%74XvK2J@!9>IS1iZGxRxLyBV#nH>3o$>Xbd;6 zD0fbCH-_hn@j*XaO=bbP^2T#TA1~=|!y9jg=K0HMzK!yyK}Al9K3Xi%k6?-*UiAV= zhm-Wznr2k{gvv!0Www(jnp&Fl0rhvN!f$4hGdO0XC#>? zMm7y?Y9Y+%2geQ@GIYGT!N7)Q3SAP_BrG&E#@sb)QvY%0^iku+kDV|wYt(qa1GC4D z&K}!;eAXaE=SQ6k9jfn;tnqyjrlRjaS_B7m0enbvUoou4kG(@)Vy}nl(EW$-eN}Ys zUlHf@yLRjJy596o!$u8J0`M>a>vi`H&K^tiR;4zu0@mv?CMiqsh)IfGKfV8$iTy`R z$Wqut1zc7?eX@)42>pnQ0tx+)S|XiHnm{Eg_;Gz1M5u`aCJY`uek^}G0TX&Sfl7V6 z8vsJwKQMa&ZNJang@c3~mNj;4_E?VOAR&j2${NB^00=Q;*aO1`jUUQ!0w(m}K^nAx z37s`=VE+-~M{}@zQuE%)G!LQff|-8%VFNS}br0E%h+Q=gP6}>siD_It+bTOE@3QC2uYmQAvu~&D*u0A#Ile+qDz*>( zRY2AsKpJIM`YUuLnGj1tdx4#sOe3;s zr0O*{a0I_#W+!EGT@_f9Y4C__8qoSOra{>g22d9!2sfC;X_+#)UcF2;@E?C`ZDy0Us;jDAWvT}DEC$~z~dQJ$FrxJw4$t_hi;bm-QDAFTiMBVf@>{!o=v-(}Srcj0GXEz`K z$A+1q?HQsG0YHRghNdx~F#$j{$+U2arUU@dEYrd%LJ0uEk{QM+!UzB&JTr__L=XT( zWM(+0h#~-p=*)0V5kmkFv6&H^qB#LTw8)I$6fFq=qE%)jr)W(85OJB2oFbk8AgJ;= zMIr$}BxOc%iev(SXp5vT1ky0qz*+zDWN4l=3^ z)=rG7V^VsXzL{;hCQvxQoRnJ0uO%+;9?~NudFJ#vbu*Kfm$|54c*V9~NuIfVPSeaX zmvFXQv4(86-mB{wQYqW&mpt>{COs=npL<|Y^75YZ?``52dGCDd9DQb)EYQ9q?!0)Z z=bW+vw_H&&%M8TT#WbvS)?`M*%U&qT?xmL9OO)NqsqE?OzQLJ37x8u}nddL{nq#1H zAIMIgsXLLpeES>&z5VFy6r*uqim|ILrPgL^4_%6}Zig|C+uSi_JRrL~qBLv2erdOiCoy0T>} zmrW~P#~n?HFhEyH7w6B4dOY5DdVJX@;>$i6?>i&D>{Gbe4>T?P1qCfsi_kvW zf67!HE2`Wy0`N}s<$rRjj_%=wQ8Dzzo?N=Vid_ z2U;^MgTpe{rUHI}j_9qxuhzhC6Wo~5=rRC5YhWiCAFKEPWwQp}POvP8p(!krOePJ=Dxd@9+CHux2!UQtBlJO25W%(NjmhX(q^cs}(8BHjc_X1uA zG^u7oDRZWm`+bn?!V*^T=!A`D%p>e~p%v{IR)*)g~)jB4z-N>h@0Nv-aQh9>DH z@x`VW%$216h*Uj-hL1iinbdjVia`gh7d3LOB=t)42_l*^xvuil*Tv&eV;G%^vPyj+ zVBpyy6iiTLQUxY=4{jf;w97&W?dna!EiS1E?UFjeHFX40yV&!GZQ&#E{Ra#fn>A6RNOLv!7qq0S8=0k$ zJsFB$HL2PiH*2$LDYqc!d#im&+TbVy=h=$lP8*E9%yK8QK)BKdyP}Vm^o7(0YeyK0 zfYjuwd^0YJ1l}#vCIZIN`!D4~LAnmAd-H$}-yWIT6A((YMyeGgIZi7Qj8TVFj~`eL zbIBv3YzaagFyJaO?IGYV8iOswMcI;CjwErorxX3{poSlw2R-JSGC@YHBHl&faFpfy z<`}+B(;L1`(HXu?R@Q!-LVwA+xj&Hh;VnZ}iZQv?+HcdexPfU5m#jQRx|h!MYJ%tK zg@%GP`9SulVzq6R>5C_^=b#VhKA}qQ%W;lxQq$yk9!wUn*&zuEyCH#;aI>3bWRK&g z00xi?77y+PI7^Se~dy^*QnjZ779WU6>0Q^gy( zD&8nm@kSj}#T$hx-pEz)Mxlx~>X<6tC{*!Au8KDbRlJd_;*CNTZ{(_Yqfo^gxhmc$ zRPjcpiZ?P zcmkLzo{n4E zA7uP)@~dF*!<6%nlr97CYxGAcV;W@~AD}#`fuA8*Dy}}!z+Y(K6B_t}2EL(z%M#C* z#W*W7gldl{WYP*S_|zKccjiu7p#?J=S2VbXzdxU58FUaOBnDS`lEMtG7<3S4 lD#%OfQ3@DbxP*w|n8bIOA@SSw3e<2e#7GzOV}}{={{hp1^fUkf literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build.lib b/v120/DSP2833x_common/lib/SFO_TI_Build.lib new file mode 100644 index 0000000000000000000000000000000000000000..1956f36aa57077f5e0b6397d302e1f41bff4a68e GIT binary patch literal 5822 zcmchbYiwM_701u@+H128V5gWyYcOl$plzd=_z@*lBG~wa0$8@z_O_*R*UvmC#A)oh zkb<*CG0H>WunOiO-U4HTK#EnhLa3z)3qn=Y_!B~HBm`BZd}y&0sT9?)x92|(``o?D zBS`I)cJA+H;^uTA1nvn(T#%}v&!KSV?U{v9MLy$`=+ zcY9~DV`P8p-Z8S=wvTaqbbt5wz=3goPsGK>_Kw!N(ZM@a=k@jVO^r>Pn;IG;5!siG zq+!eEExOPC&>1SCbJIU-ey@aR9d}Js<~&Vx<0JQst0!GJ1w=uIXls#v-f7-N%)M@S zV0^&vSKVUPe{gK$%+0WgAuFMR4@lM;T z7f){RdRCv$gt=>v*Y%4hqp_#L6D?CT9VS&X>d=z=hLhV*4SQ}^?V| zfL?i|o?c-qr0@jBNE;~K5HA{{5bj?LJKGRR%ao3#fMXf+#lmAdTSjlYe@xus_{O+y z+4b2tLyj*)9Q_fDJE%u9DY){&7Z=>eISQIC)o(+&84CHLLWchHf6q`MXXsBx72(K^ljO#$axNXp79~PQdyFOkIHxXS3m=F*$VgZ zpA~;i`A3wbHC)1{koxFyzOUsU>}Uh_Alu=475`wzd)Q0ZezjrPBZ4;wZWMeob20zI z?0>7U_XzG2JS=#hVBUsQJH+Gq)e83!Z%xMDM~4Kb1Rpkx7)~%_EQtSU!7mFwCHPHd z#2;k;(}MqGxRmXShSC0CnQi-j7yOCfe+hO4m-4QLzA(l$E6j5wxJ+=l;0nWtp_&6XZymuI`VD2}J_V)n_;qI6?{AD9{%)i*hE>L;N2b#gBAh~ zRE$+F@FSACgLL3aGui zwzi||$J(@F>FKoNus+?r&B6z$zdRuL;Hp$53TwH+XW8Ph^w!q)bhdXJo2_Mg((NF^ z9j&dx2bR{I31LZ&bp5cy(=wi{qE+g)t?QR}*T+Y8v(N=LXzXa~N_Gzo+%?iZFf=}T zK)-8Tb!$=>f&%XDX!9#z*4B9y@YaR~sel(*0Vnv=tygqD1svrRLILl>)bV9=5>Zdy zm1InLZ!zmHR#jd{V@z3pvBF?lF!tPA%1palZScV!mEhQK#RkQfUFb3O#51Y%@7YV! zzdjARs))ThknKL@1KYpdoZUR1hBX>H%sanT6-vFPm!HbaKzC?u6G)I_Ek;)=J$={_ zT4_U#(%VL<9PviUDsqzbIIEzG4%EboF5<~wa{GO%lNEfW%S!l>9G$m*v1RHcYZ$H1 zS~iC2GgGe?({#$O<)Q)lxzcA+%Nb6G;%kO-)n(23Oz3r0!;TRubZwq78pZdG$5_Pe zeBx8HdW_fo)0?ThQsU;Mz9%|W$IZ9Ee zo;bTog;r9keD|snrF7=xygFx?^VK9pS(EW;Clvo^*xODlx1GJKD{HkKb0YDy(=rv~ zQC)?k z(UcIdBB!_agShSBEz%r=GxnO(jvI!QWed{FmM;q$!UdE@z|IRS# zz9oF#5qyr>_WObG|48^;FpP063IETSZJf)-2YnUuhGN@XD>%%o^;(i@49D1?Kh4UH zx(&hydfECzFWWY66aGDhF&Din+(!w)KQWA){8ZR?8Akr^6!v|Fp+m=n9r_ya5YP04 z;Clr_cUzxBhB3wmg#DOd>8Ia1>YOHH+D8o?0UPdLQ~Va z=C$kAt!Ztoujdk7aZLy{d_m>IYNl%V`MbMsU!~L{R6wcO-tDUK;OILJYM(j0%OR4<8)1d^#uT;_o_e;B@g^*dZ5xWNdtlDl`xFFPABGbHYSG)$}iE z-Nw;y0lTa{*Euvhu#^U<`jO#N$UpZd(JQQR4h3GbP^ncjl)By4=Vcql@fTD4&ER|M zmAV+cE@Po9XObx0|8lREMJTUI1*i%oT|>^xdGuz19Kle%e>>bypWuI#)< z-L%w{qd93=^2o-il$8IrJB7G)CVYjbel`8UyqYdWS#Q>52eog=tL3sh%M#QZlP6Sf zv6U)Q@8*HBkxta2dEn%3seheHnfkBrQID;8^+3-&I$J$5{os}#( zeCLFAEWZ2m66?;zcdt;%yH+e(-?8}4aSswZ=JRW51ygVJ7>cZ$>G!YtyM@t4~?J5~~Xv>Ugg=76G568(>*(0@^{2jiLpjb&-D$53F3_vfR9uy;=$-xM z>bF*7rZ*xS{yJ}t_vguq_av*XNmeB*{~}p^ZL;FJWZB_l)my83ah)m6CiHQ$Dl2o@ zh_C$cRi3Kzu1{8%;QBGc_}-gD_7&G&<)Hwba~ZP3E#x{KcMh(wl@wTYT@tmcYCyJc zsj322&-Z#~OO0#Fl$1Zqv;Nv8XxnV#lZbUo)G9c079gofF}D^eT40-Z2xUp)`EA-+ zFc)=^G?5zkb-UM9Hp3r{*noxEfaLD6n4AwWj1%H z@;jYxV|tq^|5Pa5JuXb=d7tyOcXq1s`<-vFzgNw8QG6Atvv+j%r#5fwy0U4<@apEZ zO)cx1cJ%e9+WRuF431vBf5%|&x;5*XR-fH>*4a&G2MaekBe$vB)XaM1*ML7&`D*fP zE0*VFm(9ExnH|I5tIM&uSdL@kGqDm?1Cpbv8XG^T%DiehF@B94)hx}mYIa6!b#=4V ztP6x{)tt?U-LytsDBii3;kcmc((wahd&Wn1*Gon-ym^OUoj)Z(T^Qg)16}Jg>deS} zloxqMTQh?hv5Mm-JTI~ktFyt5bdR=*<0pJCB9)P(115(7SWBHX zJQDy~rT)O>Io;N?6xV%(I6i z*eboqgNWC@3CR)Dx_+XH?1-)H62IDu{6@#mbPuG&u3bM-<3$p<@FJcIFyJReAUU(1kV{$4|_5)^1}J$4}IGk?WAd;PyOFT*ve2%dnD0g6GbQKlzV%`j$4@NqB7NGL>XWmwT^v6V z@gi54xYBUMh2tlpUgR^db`9#f8OKj7^ddje)-+Cb*C395BIZSEasBQZ)MXjRPsF`Q zQd@OdU4y2qMPB3*6IaSYTwT@~UgV>&rc=6Y#_E<4JL>T`r&>1)Q}wXl<7jHcH#MINDg9=1eiKS6Kun+Jud-f6`CsZ zbNxX7=Ctx7>yU4_r0*c%-r;>0;#w|8QA6(2s1YQ| zX_uK~MN>={N}*?8(Ij`&<`tqRX3+#M<|okeuxNsFvE<2V1}4&AU(o~~#tk|zflSk) zDSlok1twR~1Q|Rp=M{koS2V#F3njo@ESexPH?IVJNhq4&ib4s}#YcTRUOVJ8L0?IV z7En3AK!Ve?`Ea2Gr)zV?g1i#+rKxC@uFp?kE>A^MEQ;h6VJ~1slN`%SqHppo&FZaD z+~gOSt5HWUZqD99xg6mRys^Kt3pYj!vwXQU=rCMXy3SQY#;NfF`#@(O?q0Y*!>JDJ znQiB$`t=PVOO-)xnXTPo#w#=nGlP^pnRKdegRJd_0xU1dmgoYlTM~qza-F@nU0K%; z^33#iMOZ1;U-}mRU`F~5>Z`y6_q=KZ=N1L8z7xqNrzjaaVo;;+PgRRVQr(!(>Nm> z-VuZwEDypZL)?{(qsmRs((NheSTRb!S~uIR;x|^?spb|%eY$-BuYBb|{is)`a-hCT zwQoj7IM8@cwPTLRp(5zxRENaFp`2|JucK3y1~zGwX&Rp1Ov~)ukSf=n8q9Rd;?=lR z#eNfD92$%|rYvhEMTe>i3Y4e_Fbqq3r}_Uu_D(;x+ubr^{GD6WP*Q}J&JHq)9W1S(ZTIF@p7QEG`Jn7 zT@E?t#|?IS&drkwUz0;!6Fxz@AMut-hKs&$^=EM5mjey`aFyM4Se|^i6#bYahd*8k zvgn{rc@0XCRSK2xn)H-e&QU37hn{ZMtqJbPu*j;xI5ZJL^{UWUHGQ@+cq?NT4Hn9R zyd+FAvn~x;SUOxP4PGc!hfO7}yU)u5DR&fVsITSLrBMn?N*oM424tNmZ%(wEGZ?Z%-<=HiJVGUB`npp+8%zPjRKBrh2HOWP$Jj&l z=PB!rcmQv+~XpFWhbLwkU7Ac;UVc-d5%95HH-F@U|)MeDT5^ zf_IJbE)Xx=VR+XnZIx)kYP7!DW4GJ~kd9ylm?Z!Dcs-dJovoVUli z5%;24Cyx7Kne#R(@8Vb*$MIPI7B~~Jbo=_Q)yh9oA2Ta@|HzV9Z#SMOjx3G!c8Qy? zZbK}c>Dt`c57RP>J>WBATl(<^@yPO6s<#VIn}c|fdSr!?H~+pm14lfAR94~$SAM}~ z4DBt`Uuw#{lD0~Gu4?hyJbzJbNsXWMN|yLHc^*Pm_)p-m%tIDtLF>EczVp*XA;*D-1o=s#whq#M)6Y<-?Qcvm6 zVaw9bW0s{qCoD@n|BU#MWl1Yvgz&-vzab^xgJPEd!p4z2<;#$ZBj1Hw9Qi7QcO^Ql zd=ru_Cz6kR5pwb6dytDSUxV;*P{)yPK{AFU{sUmV4$=Gw*qyuYfL-7InCw6s$9(*g zts$k#PvfhG!s}H0>XeKVyc5)XD~{9niT!VgKL?h)a7+tdiphY#^!LOfX2h2OOGH^8H}! z3DNc!!SAqK55C-T1NhsPZ$_QJYxx*>5ng3Uo^9ZI%LCv>uxoEC@!7;3#C^nXBOWIH zGvdpM-$(p0;`@oeNBr-^zbCH4z;kteJ@Gljn~2AVuOhyc_zT3}BK`^S?})3gU%=I2 z3GrIue&SK$%ZP6#{si$?i2s53KZs8f&&4Ek^?5yUJMr6yFD1T-_+!K;h<`}@JK`Dm z=;z99Bu*0VB0fm`0pd>)KSul$;%VYKe71AtHWPOej}Tu7_%Y&N5ZBaKSw-GybK=?T^-IL-b6e~ zd;{^vi60<-ocK4yRaktwvX&E{OT3r(YT^$Ne~I`9#J?ntV&Uq_`V-<#;_bxyiH{S1 zlK5fbCy0MZya0=BSMD2#JBhaw?@g_h2zksdo0Qj2gAhH+2zC=?XgfooLw#`f%v&criuthcq1{R@i>(|d{%56Rj;z-W2JuqyMPt1YEY}d2~U7xM+H0~bVb?Kg= z;a$5XN2i=`Z2ZCr$NR>{M;%`{IehUb-a~~pcjoO8mDeMgja~UVk+vc_k(SmrNJ#Lz zKZPVR{kB#0*5#pTO$D8#i%-L}U_@&?++MSAwQ1qhPw$Ve01?kPqiOUK_&77t$Ao?m55eVge+Ozh}p;9 zZWSTWlVtb#v+V_|i*Pp4mxNPd2fS6HgzZo^3P`cALJprk-@w^M6Khqmp?Q8C8#twCsvKP-dXm2slhFW{Xhc({XkGc2}(GsbS*3W zql*WsM???8xh{S3MCCmbQvZ3T{wqYUG1Kc<*@5^mt<*`X4x@C5AD&yYCupnW+i~>7 zEgdT`+KzWrN{VN8b6#c0>t9XzwwFp?buWoZ;UTRb;d+~1O6(1{rcfU>yh0z%fcoQC z(??!qFIA|iiK2ZpCVgO9%6;U8`Up2cD61sgJE}f(;&_n8)8jAbXEPpye)T?Z;&@8y zgn}`90(sO9bRI9=b$9$X(qD}m;b`eV-7Zmq%+>mkgw}_ASnET+cB%yS zU!1C*D1-a@>2e%GJ0% za?*OMvFWQ(n!Jvb-}JP(!2N1kmJYA{dwM$g%8^bRhT9{~7@?zvJ z3!N4wmJJBBFmckt+=!bQ?)Uf^EsQKJ{!eIOZ`$Y$MY$%<&vjFT9w zZjCgex}k)5msY}9*4CDJ|%ggc=&wD0vB7R)RwTEzMdRDl-XnuxTwoX=BpL!lE=Y0`btuUR^9! zh2(=?M_w+Ml_U|*sAr@`P|ti21}`i#E^kCTa%?kR7Tf<$*>cwER#CPztz*$h8+Gxs z>ep)KVPtqS{$|QSzPikm!$$EM`Y;xxdWWs-)x^hjy@NCQTW!se z#Y7vhqRf-UM5Qv46uT9TBeEE4)%!#OS&X)Zc4&w!COU+Cv9VD~mkp1m7Bjr)&BiW! z@tiD1=Kvpee(0mfVxr$cJiQMRF|8}In81$M+HPbq(U*06r+&%GVxo;$Y$KivFd(v+ z=rBU^WHGufd9oO5&5^}Kk0OUWSxmM+u)|Hd#mHi!kLb9%JM<1UoRfK8^uM$1#pn`D2zD7d5Lt{lUtw8{vth$vAd6Y3=ZD$Gt|NrRD$z7572fZU1X)>3fdsqp zjyo?wu*urWVxlSJ8!qXGNSG^&S!m`>(b_?(np>F6sjw`jKv}Et!aA=kJ(r3WHI5`X z?P6I>fu5+uo9et2diE79~G*~Au;d$3c(SQewh0xe9QEJlYHl*Q-}R4!i@W6H~w#b|53ECziN$YM-sMh+ug63Ajqp82vE zmm*&lqeH@5^vrf_lo(vGwR%IJe5Zy9$zp;KStucyQE)`;m7C6FpoJL<&}>H3H4$SG zS&V60RtsZfDtcq1*=(5K60?^-o34l~CYvt1hu+9yvgwM*VzS{yWHH%%aaWcOZoylB zz4=kP#oeBQjum5$EJk;$*t4rd&r=a|i=sZwk;Uk8_3Bg(X1BDq<;Y^JEhLLEwy-S5 z+Cs7zZIecsrr}Y`v@9fx(UGhiCM=85Aq8YHK?+&cvMeT>0s$n5R_8eJEHlG|>jJ8WXvs2n`){n3(M#svL z#aJ6odmxL+=H>>wJ?9}=Og0j_!1R#Wd9Ll~Zr$g6dU9kj+4Mn`-F28`F*+7>5WK_x zk5PgwI_Qe>8kCST;X;GxkJVEwi*Y@bFN<*@vT8s>;h4?r+8(NxQIu%A=ro+bMT5}* zWWyvgi3690tmrsgDw4&xR0U))5t7B|XsDsSmRpyuC9venVsx6*H9}`5H5D+j7+0M_ zvKSXuNEVX~DC;6%$iBHTRSSlg7?Xmc_ib zr56;XNbAFQn1Zb@B#Ut^{ol90a1G2lpC)wyS&S}AF0=(?F*>Y>EXIWulEvt-(0R48 zm`F$#qoX-B%#Z^b-gq80_fQA4wl64)DNwK-4DNY^I)kJzR`Zg3t9G)MBC;4=np49J zIiM?vOP|4r)fyam;4rj^CSwJavCWifFri-~JlOx(y~;!vwVm9iOL zk;RBtWHIoHEJnN{i-A{UG2#_j47`xT><};9o$!h*M!X`6fmdWP;uTp8ydsMcugGHJ zS{4)6vY5EYV&X;?14m>raV?998(BU5PH{m&$)0|3_Q-f0wNC z-z6?&F?0MKMiqm|@&+8H_xY9nnmJl3gSVDhX$0PPWLe}4c#g(zNXd5y$E%3f5zDq1 z7iS~!7UCh|F)-d>B5%k);NqqA_G>NsNPAtDcdF|x zOa3>5UESo*wyW4)-GvZuq=7XJ}uW*WtOF{Dzm&3|B0T7BWaz?L+Tl`c3OX8*^4v%9MN%T|lKA7q2f?mx zS6I8GeXnK7^QdKM%U@ddPzRBkNS+?@{3zIrt0DD?tbJJBmF1o4Zp#YsMGhosB~Ot9 zxqR-mEMrL|D`J=Ue`i_h_6XRO^{p%qtM6oar}`nq_b_o?8>@)t5uZVPCNZ+Hb=a-S zEPHCVwn^RQfkja#oCM2Hc1!&+q(@QI1Apnqke}2;q(uK<`6RYE{ub=EOX5jC%QI}- zCH{P}$E_Xz=cH;Q`xfYU1mN|BCoC#3zVqq03VbSd^;t~ZO58_$ zA@L#N4-kKb_zL#{v7f5iJvC+aglN5&LeIi?jqhzJVktr_!GomCw_wXdE$!7pbpE4&mumL`0d2+ zCH^4s-x5Dc{Bz<{#IM8mP}dJl#2bjuCw>?4QQ}V$f0Ov%h)YR^w3v7u@wvp4#5WS( zLHt$XXNgNllC*-jhj=gXVd4)HKS=xp@r%S!e4=%I*g?FV_;TVS#CH&XnfOuSr-=WH zcp<*px^i2HHxQ2!UqSqr#9t$RocK9n{HL+mvX&FK6Yn9ug82Q!cN2e&_;KRrh)eL0 z)a%M!Ox#S|O}vlz5b-UK_&?h$9LTry8*VaIlMC|FF0~oG~0FcKG)O>&49t%1 z0Tn19f(3e)QUw=W<>6Ani-?N6qM`y9uZUMguMbq#6$}ar3#4=Z-+r9)KQoi2Dy+Ni zEPKvxfBW_AefHUBpPc>2*{Ajl^=><@@|2qJua<&_`B+o4$WO4jQYjV1ze|*=|DF8n z&a`!Puj)T9xqWB%+9uVV*)@1xW>?S9F4z$=k*xy~rx1Eq+p6Tk!7cCAF4Wa6ZK!W- zsBb{|T%)V5u6{{lz4mQ$y=Q3Fit1XWrojQFCV8Jy3wQNjuuF%`VM0Wy1D;Y9 zb4+-#jjOTeg?&A{dMvxsJ*AFfj4SgC^)^KdSfAjg=C*Xy;*7jUwelLAO)FrtIY^D zSAIAzHa_!?dnDCoXWlViHQzpe#)|mN&z6a$eP+k}i@XkZtSV8UtHI)1k~A;Xz9#|E!%(Yc^fy@);2ZP*3~VWo0!|VbXnap_i(IV z>OVJo)xm?4PsWtIP@W6_P{~cBmHfdEPX1REdXu#IA1b+iw34?EOqR#6JbKiWHFM`? zyV^49I<&x>(w3P!H`%dP-Kaw@?&eV3ZGI@TCa!MxL#t9}sk=k@?(^fM%&+^QmSj>r z;)k+b9coxYQ^(7tRaILC2Y28SSMA)sb)dhmrgvKpMod}N?tze@qUwB!>E0!AJGTuE z0ZM~J)>2-zeLy0-h+O_k6(rF1@`^P$*DX?!5-g&sb_@<|RS_!17)+{$dKEdzrK-^} zC3#7$wY=(_9fLi)P-s=(;O;Fu`h_GzjSZHRlxO3KY-e}8Bb!lPG?7iO>Pog^YghRW;eQA(}bs%tTkFwNq6Fh55EE)VLs@ zGez4osYK^Wxm0CQzqY^_wUN;v(plhAvLme`L7~2S0y-P(#v?ORQF zoavKv>k8$S^z4u^V4Ey~k}X)5iRGixJrYpp#7s6rohVLB42ne`ibZ!xhnf&XNEdV{ z-R&*wxo@S{VTlgy+|yU55aT?s2Dm6Sj^*MHu#EFvL|1gTr!lkXY>|>|9G3QU&^l)@ zF=F@h5YTp|P-jrYigeeS6o!-Qo@LS*x_h?u>^Mi4xeLqNZXHtPiB%~YW}RIv$(HVT4fMtdQImuQzNJUp=my6y3I_ zvs0A^ae>j4tK-YU@o{a`H1vmBe;Oe%YzHpvYM{nhIAKC5fYSXK+)BbU^LOPhVOm}!j@DO!Bv%DG!b8;%E*Qw zY)MtZHl&lwh($xF8_|o#x3N0$%hDRti7l%$ZRv!&Ut1E{Oj`>#$XcRZI)bJ=V~Fbb zxT*@=vlg8ru4v>*j<|}ZJClh_8#mlq>{!L1%fG{|lVdgO61*+?%|abPyATMqN{6F3 z#`!|&u=Aq2h!;qJGRJab-8kQkBtKE|?{XcErn)-i$-v{qSVnimlsc9hzX;sOZa@|8 z8Ykk3y3mX)VT`dvJx|9vEY^n5Tr6R+Hu6(WhsD~YXcE$4u`c34pu@IlH1_SR)Rk$^ z*73|@3{g4NW76=ii7{w6y z0bu%?p2@cJacS~KfOJfjufGJfSLlQAgV=P6u4XL9`m4#Yw$2sKFSy9#Qi9R9z$d9; zESCJS;mFEy0)_(J#5XbzfB|PKF)Y6(glH2$W z{K?hMx2@SRZsWJa-G1{pAb+g|4j;))zCK0{(|QG?rC=%?lA`N)hPD>z%OmgM!?}DU z6TrC1zRRfuJ<}5HDcn)?R51qqXkC|WS5?7{E>BxAMUe!rnX6SraML=I#3k2c&*Evo zne0u3=RQ9e@oqTIcr@0i{zlM*_H^RRHvb9Knp}~;NOLB2s&TgBv0S})ir?G#%N#1KbC0G>XIr9uWxl&)jT+8mThgItIGdx%j+PZN zZPN7YOn&|huj*XxjJa9S=~V?+!Ff7X<4&IHH?Gybi)Yjcc;!Yr^=tDj^3HC8u;MLW zzr`iw70?8O*Yn7I#){W+rAyE+^CkAB9e+a*tIUedwi#>8S|wPb*RWE;h`v$A{@>(oYBDw!axvfvZ*QI8w54#SSwTFggpmQ{=iN*SH{svPsOu}Vr8vZn2dUOIuFVc=< zCBFKmS~_uD-O`R@IwhP*31c#-#c9oYb6(qmiY9sM5R@}c^*Ehn&l_6O4G5l%pqw|h zq#JSCgrJflP z-uEVX+fxY~-<#H__qCd3hrZE1;`*U_raC#;pwi5ZL-f%yPApOmh}pR)ib1LV9QUE8kVod7Ys zD_v(&ECh(*lysd*Q40`5UAo?+s0WClAzg1$Gy=rXlx{F776HVtINe}UECGmNX}Zy* zSOyTo@^qs~aVkIz?@l+F6sG~iaC*AQq-X|+0iADB!~tSRq!*bKNq`ty(~C`tHh>sb zq!*hM?Eo=!q~ki`jC5RrD^r=)HOVf)PJ=qtsFOO)bvXETQt5k;1_%#(!o-E9>CD{qD_^hD%ucP>_uiwj3keV&W>E~;rl`KZ_JiT3dR6hZI!d(Th&}dR8^gZG}Q|c5%VT{r&l+dnm*iI z@sZ}L%bKe$Z?3qaxoTf?)yJAKOOD6iAu3L-KE2wyGoeX|-xDvn)YCBOLjY+4zA;^X zsfSWcK`270$yXp!YQblseL$)5Dk*iUgks*6!U_)x^$z^QJftu~_&k$%KJgN;u zrIC+E$yZ9+sLP10QYqNw90z zGho+;za$=^G?ER=Is782G92+($1kSK!@$=3Q5_&DMP#7l`+5U(NbC4N8g#l+VT z-$eWw;zMB9#^dnC$#H`CcH&2fe@grp;>ox`uAExpRm59~FDAZ`_+H}g5WhfNiuJmy zYbNnx;`PMuCBB~cF5;(&e@`64fOB=#5w9jbm-tHJeOTFYyh;cM?BD{0#96#8FI8uHNay4a6&ndx<|td_D19 z#E%pIf>_~U?&_UNd=ha7@!7xhSlZy^3G@%M(FYMf_#r?-RdB zEbj-d-q~1GI9@`WB0h(BFYztJ_Yglr{1S0B7CEl2`NVPJUgF)v2Z_H*{6pdwh$mp7 zS`oDgLpIX9^#J@-%5Nx@e{%>nJ|B<)? z3ufoTEaC>@(}|PBXAq}|W$lT_AAWuMh~*Q0k<^JensuqC`CZzsQYZWNn6g_Xb<80w zg13fr0FpcE$-d3SCa*p6-hV_QO(a(ni%kU<*RwO{y?9+aPlIwDH8UdmQT z^An5Pei>LKjcmFMTV%&xU=dns!{WUuSvF^ypR>p&%)nx{+ggLpbp`?p`}()+-rBum z`#`_r?E~iwI_}xBWvG8o{w~~tZN2iBmdvWwLX}C~C@PbNy2TAO^4qLcCf!h(+*aq_ z7!Rj1NzE}WSZNzlW6wO&tVydt9J_O~1s-)SuGsk!GP+SArYo(=&Mk zuQGWzY|CquT7p)}&yBfe9SV_6ku}rlVqcJ((lhly~bM~}AK`>7%Fr>cWeNu-} zxWKEu)AqFN-=1sU^CM4o+*29Qg{&!PF}$8W>BQ%AUx6xweP_jkYxBIP#Dg35MFNe- zUh!qBt{q-RM{@g>_Oddve`dP6SM(lS>YQhXE59@t$^#unr59fiNBU`6k<+Z=Mv*gp z-<0uNgSJY!@%_U$Jh(PKQyqv`N{;9ILS>bXE+l6yq!LfCK9OUG{u zx29Mh%^jR0bUtHcUM?J!E2m`)xj*>cD9Kjr54B1L4L)_AxPH@v?j9or&Gj>$REc&yYKkDIl| zM4n_LjjPm0BUhG~A z-+gk2hAk+`S5q_52;V3SFL>KqHsAuuTJ!|Hp#U6*t~8%>TOks$hA9+LgXPt zkF5~-txILKAa9F8Qn) z%{motdVaHvn!{ct1l*o{U9b+bLd03^E>*m>=}mokUYIh+a$^eqsAJt2O(CMoEus+7 zcB>f)?Jf*CQcNMD6NE1ECj&P|Q;6tH*fJbeh&U_mcEmY_h_i+jBF>6k4@m12BF+l! z1*}dX;;f6@=0c+o(Pld<$=*??5YcvH(A!L%Ld3VjKZ$k<5#OGt5b^EsQPMkwh;PqR zi1>EvXFc9vv0F=NyZ8x1QH6+35V{1j@s-Jr1ih!u-DZJ8MCZv!ArE5~-d zF=xu#@TtkKd^ClKU#uAdcK@-q;>xi?MB54!B7T0;DMb__Iz_lw@cqemtmw9Lok#W_ z%JBJTeJb2qUg*--*d=TxbQdbvsr{C^BsGjRi>$)evY?lWD@3$Y_SShTda6MFR@hU& z4BQ%BA>ukq_8x~6A}&G}%f{~ty>XlyBKzF~g@}%ECcPIPd5uEEkCM_vVGt-pTvQQ- zh#!Sq#T6ntMQFsHk1vS!T4-T~eX3w|$g`cEmevwhi0JYVBg%}!wpt1^3K8dIF@=a9 zr^}OeOFp9zadE{IB7WSc3K5+m)bJhngy}bYj9b-QPooggCE0-~7tbn0oC_`Hdf9#H z&YGtX@yn2@MQ{8a^PcI)pG$pr$GDB(5_ef{Vf;OuLPVzs_3zXeIV}2&U}Rabh0Y_> zP&A|v2`aOisw3{5YZ_@ zt}e&7XFH8wmDD78cM$l z8dqE)vQggIvsy5M7jdT$$r-BzgV*!OPI)oZujOJDNeC8gCE70&l(d*AVJ)>*36es@ zZv%Gko3~L(T>dS2^|N9BRkETWS|hy1;C~iA6TLpg-DgWl@w8k1op5({$)pv*2rESP$qLFU zMo1wtLzW8#3Xv}wt5$6U3XwK>$`&X@mdhh3Um?;Y6Meoy_S)dT{`ys3l`FBZNOd)a|K86=pi0G1vDnuxT6(ZW4rx0;AJQgQC zimE2Qj(rNHN9S<#A|?0}dnI;?i$Wx(6(TXM5Q%ApNX#fiVpbs%^Rz-FW)&haqY#N% zg-FcP3Xzyqh{TLSBxV&NF{2QPS%pZx&enf(7mhEnRwP*|@5t&A3#lsdJFpKL;7SgkVAs8uF8wMr~dt4uCXt4s;h zDq5f7t5uF-wTkS%FvFl5`|ksuPJ9CKDa4D2o56U{;n%I&aK!A3UyoYh^Cl%bXk3~U z*)wF{WI2Mova3VVN7N>Sg1pI@p+T_jAd!d z=ZL@Lr|D65`@BirL;O{+^X*}4mvWvY{xR{hKKH0!`MgQ}-sf)hl4bGpPd;x_uTYvd zz^-2T;OP3K0_^&HD%ho&MSLQ0txYd=)%(0jHCUFmEG16(X?j%B=S`}WcqQ1?o3(Z+ zXEX73;sMJZd~iw~4`V=-I%ZsTtG$%wVxKpuODrp-|FF;9>IzE3%ARZeG@I1*K6k5| zz^<;(_}rsz^?8%}0;T^6*tPLD#4iy4h4>ILE}h-s^v|nvHlSSmQV-)`Fs8mm`~=wT zlsrT{nmR|Wkt?T!<8S#t6Q}J@=>N=TtHE|#D6~s3Yf06i6;vWxtJBzn}Oj;#-No zLHr})SBb}A0(bQ;Bu)~aO}v-*I^r)Af1mg{;!=DQadjO-yo@+Sd=BwN#QTYFCw`Fl z$HXJV<#>m6KFlIsOx#7hm3SZVCyBp7{1owTiAza&a}4pR#A)Jlh%X}kH1U^+|C9K4 z#IF-i!n?O?dmV9txS#k!;%kU+B_1YzhWK^jNqD<=^~!%{%JDMdvx(0o-cNiN@uS2) zCw`513jTiJ>RL#gBHluLIq@yT_Y?n+c!anLe}Qmyok%PSaA!Z8_+N;xC%%*TA!1hi zyhip)EUaDm?<9^BpG7=KdUQfJ>_*&xIiN8nuEO9v&TCRNg&)7IVgLoV9M~FX1d_VC|iC-cvBel&8 z;(FqC;%?&I#8(pEOne{le-J-UEHZ7^#-oW@@e?Qedg1}%%ZLvWv*PD5vj2kkW#S6_ zEz9{clem%i4C2ki=M!H?d?)cR@z01yh~FRg`=~t-!DXyS!xv&UAU0ZRKz6<{_(dnP0je4T=c-dNllhaaQQG+y%MOvnm s^rm?m5JissmguAOv9q*Ui?kIGIl~n`_k_xV`ene#z@S_!>3RqbDh>O_S-~T-B{oR>KQ(4&0 zXYZ%E_j~^5^}pwyd+xb&&kv@Z-m|H9!x`nL)`YiO3L55pP0c(%!J2ZVR1|+#DOLAz z`RmTKb#^c9yQrmqb9Yyx>dtH#yePA!XVVtg5i*gj0}`hYI;CxC%bdZr7ibsi>P~B@ zpWDz-H@~KaYjoAs)z3YxQTw*0{M)KbeQnd!#TBP2bp#xM3*H@S&X&GQx9E`BRYsKB z=_z&hG!w3~aW(chXI;;h9?S0VF*{uo=?5uI2;ONpv_dOabJDAv+oP8koqBnh8v@7AM9q_yB9yPqZ2~_jk@b}-& zMN-2%CC=;mXSL_rX?rEjr)L|BOF0cG-^`V9%I!1u-gaWsuF2b)XEzVU(^GoAMNK=F zspjjY9JOP*+A~}D9@Vs?NeycjyYlU@l}pYS)+Mf2JL1}}-Ce`pf!r7Ky}fq2_G)+6 zr%(6&x^`y1r`OKPx9GDJ-`~zfL%xgcFS!_O#{c?sNw0WQpZ@DQZ;^PD(7wZ;$bsD2 ze1Eo2+k4yhtJM>^$GU#03fmQ>AN`k{-=^EAJtwU#UU=k%LTe?i-!m+2G;^=C-Oi!m zol-BZ!!i5+TD?KqrAfC-6FeF&H*veW_MnYEhrHBk(F3`EPEn5A7A+eLwOGmIZCkZvnQmckzj}Lk->}!T4Y|<+q#n64 zKYB5yI4-jP*9&T1QeOFf+l9J=XXf9@;$z7;D~8!+x+D8?2mb)$Z-4o9*}GY$2% z$@<#b+M494$=S1Ol7s8|*7pt6q>?q;8t2r`sco)@?V`&z^{?NsrRK!m_tn&$cG|pC zkYj#Lw(ruO%{5B~HgDOq^}@b^EyBHnn=TsM)U%~;o${)dwx+r>y*(TI+Io7o3~o}M zcRL*E&No-}rOsW7$XAa-q~=Qdtg;U>aaNutUgWwhw@C@%=-{LpO9K9m=S95KfYKQT zR6MzG)vA`xbB64-gRggg2$CNF{v2LD<+>Pjpje`U0RfI}0 z29v6xUPYdAscLjgEHA0Gj;T0*<6zGg6^T`>8{E2fW1o;@sIkFVY)rN}neFIqUXsly zFPhAzmv*+as&Nr7GDAIxO1hmXnrhFqo};SJ$83x-L{sUOjuur(c5R4eK5$O5Gt=6k z%7emuTQqZSn*`L@AfGcu+cT+T$JuhJN~3;lfiY?$qd}yzz@?TYX%z_ywU%h6vn`7o z&M!`fqiyNdR$OY|YQkepo1|M8D=*fwQTl*AWeLRAV#*|z*_erTOF*F!GuaF^qBt== zC>Cuf7TqLE)VLr*nqZ02&7N4nZ7Zz~OLWubZR;?Ltnxju2Dm6Sj^^S;m|^)YqA9xD z(-?Skwn!}73`=`DI6G%BF=F?07tnU4P-jrY;&kWo6uOgZo}Wu!(ap1=XXE+0%!!zJ zcI%KDlU$mjZr0J6Xi4OEw7?h@Y}WCWLEj0C(M)^Gxh8)FwWV*gtyUhynO4*JOu5|c zkk1%(zIs&_&R37?CPlX`@90otg1EqF%GL3u;rM24)a5oPRT{dAFpRa$GTLSQq_m{z zX~>ZXT}3hQMYQ3V9D_@!L%Kef`!FuxFG_<8m{>;FZ)LiZhX@JEFn}kPe})o_CKJo~ z?w25JEvhU?C&6g4dATYj8-lR4s2JOjPA(&!>3$_9Jl6O&S|g^%_>GuYmT5~T-Tj(K zW;1OGJ|Sy~cIpTk@{A#>kGSkKW?+G;d6{uH>;!cUa^yIhB(sm>00 zGH`z}mXRGXrHj zqoP4bhs8RNJAn?{Q=`6bN2Sh8d$x{87GsFYp&o;Ve@%=*+Z$9#*bWaRdM@scQ2M#X z-l(EsI}DN@6OOQbp1I5FF@g5W5kFxVYg%-)OAy14H13(Rk_L_J%202VU^Kfj)E6bF zn+cQOQ0=;MDQmRKZ>*roTbG=ZbsfO8H9eDUKYOl}+;Rms46kW|| zj>Rg;v9^xI&M&yg{ZfL_cflvAVKkTSV3(2|>G#+rsbMsiYOA=Ff+6}nyn2T-xIGcL z)taSI1y@Ukv8rGqYAsP5FoXBV=-Z`F5e3V<&bWEDj+hIjq zjyHwJgtmfQJERvNsW)`}q?^B+V7g3G16_4iXl!?Bp_~8r{*11PhrlT#{ zes;dQWQ`imWE1JoGn~!QmL-YBGHlZD>`Z?C4A1IZ?u@xv@j_lva21@Vqn+G$gOh8u z@8TJCJYKnRp8B=JK51NCAp)m9UfS4Qi^n0w{b&xZY1$+Dy66-vKKimh1+DAxt(P)xsv>6gxm zKS)X&Hg=u5GO#x**yYtiN~s!_*9RMx^e$rDSu&w_hM0Z{kPPFW7P|?;nr_wSSgoBg zL0H?2HEyjEjOjV7lrW)7riv!0+heX+C;IJynRHgBuVS6_v`H&LSY^T|<|95NGbkH| z9iz3FkIWgf1f`4)eN~Pcl1YRKN?LQ`N54;=vL+bQ&t)m$@21Ej$OK_c=`Jw&Xc;$k z2sT^SG2bypU6&qyCI7LP$arOflGfC9+(|M7m|#o~8j^O(t70`l-42ano$9wkql%f^ zR?Ib@k=|>=G27)OV%lbWJCvWf(L{C1#^@e4U6*8H>Rn8O4 z5~!%!I~PGY;!uyn2kdcWBHe)Cc?imJRU$nXht&wm@q>wUBM#jN%5hC1Jr9Q-1m(Ck zk)Dr3FM@Jhmq}sYw<3%E`LbJ|$%-QzGI-ys_WDyv>@P^`!-v{Z%i9wxVc6Ivxh`yx z{Xk~LQXB?T*hg-y>Fmac@pBg7B!C=er)%3aoD2}dDd{?sVh%tIr>5&niduje>eBTlMLj?a4e5H5 zVlF@ojp+uHVje&Y^V1C`#R7mBPD{@VhOwyl^)W)t|fp2NL%7+VTyBI-EoJx?7|F26`;88k;D=OnZ7(01FC4P^;>S|9z^)&!F1$+Uz;c5@1nu1V-QWI`Oq|}0sI5z>M%I#9>Bnid6 zj|pQ0fB}CPhZKfSpJhRTv(F?x4UC5fwr+I>aSQQT#9hQaU{~gP;){ttOneRT9bi}Q zePn-#_?yJvA>Ipid7mNPM~ttrewx>b-v&FM(R+NZBtC-pIN}9hS8og1Q^d=O*AQO- zc6l!*zMS|f;_bwrB9_l~cvNBQR(FzJKHxdKe7wIV= zUP9bWd^Pc>h`&bsUE=47-yoiZ_a|5H@x<-KtB5ZmzJd4)#NQx(p7;&oF?d6B^&Urj z262jbEAc0YKTrG^@w3E#B93DcY z4&pBnKS}&+;s_=ouC7VMi-^x9-b8#e@xK!9CjLEf6(%;Wu2YE5CSFgxop=}Vqr^`W z|Bg6Ed<51+yLx96HxsWQ-bj26@n?x2ApRclZ;1b!cswR&&WBmVi-?yIZy^3C@u!Ku zMEp4M&xl_p_V7!D^WiAsQ;3tqD~UG~-$MKa;%^cEnE02(zajn|@d09)8{%<>ZJpj@ zI)p8fIstn#Z}c>uqU|bml5dYIyIN4k9K?imeP|iHkVY1*7jDvmvU#W@qTEtMV-t&P@oIqUk?Ze8EKv45b? zasR;igN}RFuHDqPEq}Ra!TQs3`OzV>w6#zRv0wx(1XL0YHL|TK7cIm?&_djUD~$UO zTQM!fIGmGcAyU(I5_PsYs2Y3Z4q;8|0lA`iTayiQ=g3PE3SLDack#sZF|BHKt>i1kSOwHl>1*z(<}JAb4o z*Rh1>qAib|CKTRW`k2*06e_E$S5VGX$QUf;Dxum8VC86CtWp5%+np1w_1uFtYc0Nh4atuZ{b zXZ!TMw?V^@80yb8ZTqPwtHUSRT8wsKIo6mloWS0M6k+9p z@w!PxtV&@PR0@+wrLene4|E4ZN_$xz8Jd!=?9H!j`g6nO_v>}`lXU&?3fh2jPgEmQ z(vzVY5siaUiVPof)5NOv!MRGg%|pYt?e1!xqIQZtV@i6zR*U#$l^n>uVCuK66#d&< zsq{eZ+XY$$(@HZogxhZPHWDRAUK@>>yzM~llYeU~m0dD8VjJ~K8<{iZHu6Gkq;!o& zfrGR|>dv6Qp)aBT?XkU0JP!9qg&w%a6UBj1K}apbC}DiMWoK;deaF0>JFyqBky%=g z;CkHfP%Ir^E2@JDT90tH)+5}d^$6cO7=`_ngO!6NIG&g*#eQ*a4E9@dW$Bw=>CYvH zt~*$&BDhnhZS5$P z)`yTOLJslauSx-Ueu?bQ#JY!BuWHk3 z2y=Q^FJt5oI>UgPaM*H)y7_hWP7bkvr3DN0kM*Ybm;Y;GH$2*azlpNjA|Sg<@%PRu z8?mm39-a6D6#6s#O_bd}0olEXKQ$?=dfWt)muD-1Pu>wfk-e%4X(XjpQyc@t%k!_M(#FVhJ6CmGf9B z5)w-odr`53jv7fUVIr-5qChO6V@DE8=*XgC2^|9`jZPsDOPI`J%m_7$A`oc z?U)a^RiPt_C3Lo8VhQ6#5wV2JQ6QGk5oWoQ2p0;)5;{T1#al4N^IZ&-4zi#lESAt& z^{NXjybo4mc!3>nS32IV)X!gQ|0n4yVX;Il=6{DLme92vLM-9OTTw&4SVG4KM!Q5`MlSVhKNA5wV1y&nPGg#1ejd5wV0{ZUb7>EJw*(zNb@!E~5yZ?PZju zDkF&{bVf-a*HDhK_P|_19Xg~~qR0i5pW)pF)C*tSnx#N2p{vXjOK6*3xEP2fjB8=B zgtdjl62=x5OITZ2ETN5ZS<#Bdx9}<@9Up4MLA(>&Ml`E(+}T)ZgjxQn^I1zsETJQc zi6w#@SomnP5!CaFi6wN7Vqys$;qGwjG`LEzb*6=4ftA#BVRwjgiC>y4)gS32nFXiO@p3kR!#!5;{TXB7Zh;V;%-Nr6H7R2SS;bJSO9>uPAuW9kRib8#1hUrPuWv5VhL@wqmnG6bYcl@ zHwL}p(upN}JN%PqCzkN-d149Q4j(1G6HEB^Jh6mtw|>@Rc8$S9X}kCdLs7AWP7t~T z)9`V}_5{7!%-v>zSVHH?6H8cISS;b!t}DkntWihGd+=4quY4r2gkP-b0(L2`w&KdM zSVG$h#1ejf(;G=mMTz!6}t7Sz^#$R60Wgi8E!}{;UZ+RZ2T_MYpD4| zWa)Pxme4WIq?d&wuMtc5QBs;LwhzP-E~SVEWYEFp`y3dIuIFDW4;matYC zH%Tnvp92=M<0a9m1IFx;S3eu}UnR>Lxxa{DAC6EKwnECHlQAA)*M_ zjaVYEhs6@VHtDrSA|#erFB5tcU}6HX#A{+N5KCxh3d9oDnkSanEK|h-v4r0qA+f}3 zCats%izRN78C0QI;#iq380`d!CB9;;qMabIM4LQi3&awOH8)M89 zOWY>oRe@Myu?ztPVu^C;kOg81za7G2iGP#C#l#Y~;$uW{v4k$Es91txSS+E?SiC2%xi34j($;Aq4W04_7r zECJAB2^@`B0-(hbI2y48K#L`C)M5!7MJ$1X6H5Snu>@F)C2%CMgshg9EtivzBqE+b z_dJYkU#{seQXMLZeD3n)7pLXPFM{u3%9me!M~VL8H5K`R=S7aLj(qqu>@lBMeXP-5 zAfABU*1!;)EN1vT^uLgoPX9jc}vd2{+<_aAQJ& zaARU1+|W`DU$}7u3pZr-h3N*}3In{)M-tB*gBV~>X(wr;hUcnR2~ zS*<$Bo+kThYmcBDS=AxsMAT}8f-?KS&gV^Fv*@c^ZKX6*wrf^99^4~f!(#31a@hr63--_W7A7rr&<>O>wNoaHIM8`-`=A{oZ_xmEAiQ2 zS8vwZrOY+N{lo*7J@~NM=hf;mu<1YD$_ZE`%||Kk)s+4k-@aPi=ySLF7^T@k_D}k} zT73rW>iQ?2d(_=NuU237(|4<%gWWm)iuh&XKNA0y7?=sELBt933UHbEgU@9LHq{sB)osQdXFdWBwkN^EAidLKOlaUxC*afuKf2A zw-WadUqO5a@i&N{C4QB75?=0HT_+JQBVI>*Bk}FTUm<>i_!;7tiDjvxtG9-@o_GcE z#l+i*?gt_C+(LXF@s-545nOLOYlv^)pZo{LgEzh`NWqK z4-wx>yqowL;seBE@DA&Im`XgKxRZE2@lC{^C4Pi>FY#}QOYoBH>OG41bmBDe`NWqK z-${Hw@sEjLBz}vy8t>lDhdSaUaUbzz#J3RNO*~BeGvc?1t1^Z#3|yn#5WNCBk?zgpC&#)T!CL8TwNy+ix}G3&m+Eq_*2AR zBz}ze8R9<^m*Y1MSN_Sw&BPxd9wfez_&(xq5 zh+iN+NIVr2CwIPe#4Cum5bq$qm-s)3pCcZFiIyw>B;vD(HxOS(`~~7~5dVVsHR4hd zxg1MePux!2O}v%(W5jn6|2y%Ii1!nV^4Xp5k;EqxHxsWQ9w5G+co*>l#7`0blK2hc zG7_^)A)ZTo7V#S5ONehJ{vz=(@w3D%qWKHi6@FE7?NdrzNi6e6Jm#>iQ<%2+EH-C9 zju`0A$xi^A`KJ-)G)W}pnI~cA=A~KUTC;{#(x{O{I?D<0Q$rYmH+?% literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib b/v120/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib new file mode 100644 index 0000000000000000000000000000000000000000..e35f7f812d4edf7db050bf37ffd74221ebede393 GIT binary patch literal 26016 zcmdU&33MFAna8VVMu&CS8eb3tM!tYxaCBIIFy1Kf$r~YQj={=j)tUsgdBh}%phN6afUtK-N&#pWj|7->e~+uwf$w5QWM|+T<~sFv$phJwnfLxE)r2{ zm#5UuDJEWH)2eMaYi-Y#9?LGcrN~hbHd>sudh_PMIy_xTNmaxfCMhN5|9YA+9*dv0(gIT54840u+xQs1-XyENyI zWIa}PcB_N~S5>=M5W4)){XdA69%|Z^n0YY!oHun_w5!QeJK=ZN-D+q@BdGehpN6Q4MJpyYlU@mC2DWt!=tm?Tl-`_H+$-2eV(!^>+JI?bV*H zFP`rEwS9W7r`u=bTJ%|p@9$=#A>YOJw`>eH<9}VMXpMMNm-_o!Z-IEzq26US1kMGt2GMde)Mpw-^_KX0|z!R!xm z{qb8Z@!ETDv#Ez|voX5OOdro_vuNo+sKtsVZM#TYmgpAt4ybpB_78cD+i)~`fYc*b z=GQOB6sJWFyfCl&Ps%GhfZOj+7$+``?r&2IPrBS2+P_fUzrW3vu=9X=OnUogUskrH zd-seTGqfwzx6rR7kAHR0Q-+RyH#=$Dp00#<>;U(~p}}Zs^y+Bp@vhNXh5d&PdDvfk zD1!Zihl&Sc2p46GQeS#CF?ijfzU=+`e;6xP>oLY**u@qrb|d^69gk!dr|au#5_L5- zHPwlaBxcU6P7JK=UDw-RolI13YnW9ttERaYwv8X()VFT^mgK|*<8J-fAf}2TQBbI-y*zbVAIBdO+8zB*D9}aaciRs-7s9qpZw(5e@3CZ<)q(J$#uh(+}A&L9tvG5C68-M zPoLhhs7u|7Gw}S_y`k9mB{trZmRIGg2L?9a3Y2f|Ti4&awtCI_9$e7k@~!vs~R2gBGc4EsHEGOqRIAj>p7|teaxm9Lo}Ic>1a_EWY>mh`n+=zo$1yNRTdQH z+oI`n+a#h!1;;s4v^||nbet`hsyOP`78s*8F&ZQ~3tVbhlv0tPP-}^%JKHk2;r!xs zJld9OZN;VbttLLov`MOUq4Huq8>A1|QmnTc6vw?q^gF`Y?MBZ?Daf@0Bz zV$n^qNR18>qzM)&-Rw=vxNW7?VTo?qylri*LW=Xi8sMVTIFgGSF`M#TL{oIPr!es7 z!y>UvGc4_?;Ov~iq=?MQ7jHcUL&NauEQ(O8*+iGP&nrStCoGF*P9gZ_b zeO#R?4IfvB>n26FE$!$~B|%zXH0A2_;&6JiHtKTgF^vvgMHoieW*O-+eqLJA^fVmN z6uOFH;EQPEF$sf9sAIZ5ck~flz-Nks3)r-TuHW)hCl3)4m0>{9)skp5(X^EBeu=`? zqDq6SD$!`7d8sNU8=|nas2JOjPc9>#>7iysD;nQMYQ$8D--u01(ru}PyI-3UnRHtd zpOCdgJ9PpLdBzac>CLJyAeo!0S~ zjM=_{cHr|uBy?6f9>u>XJRIw|SnES$vBbqXo1bzzF4hJ`gOHAk zbq;p|9k-`Oecz5so$2;WEsre55S5?~gNA=ij6vJ$RZ-Xu4<&gv?v7CY*~Z?WqG3A> zk{=U}uzilX%jz)w^ve-HVHjmvbfilV!v`7n%vnx@MrL`aH%c^`Ssv<(64lM5(9(QA z=*p$6kt)BooGNc!bWX-~0Mpj=Oty`WOOw+Bq+v3A{UxfsLK}o1#HLYnH6u9|t02eP zIu<&=;3D@+iALWCpQMJ7T)K^2N_3rX=nwGf9m(MKMBr9yhDH@! zEg8ltgNdlML=j@LOp{_`aAQFD5r&Z{jaM=$swgPRnRFToqZ?b2V3Cw&Im!zirA;~w zd1!Jgxy3TdoWn@hV)&R#<_|655l@De*36OI#_jm>X~)~v%m}yf`{Hh|c^r_x)&hr*6=tt|hnRZnk-01SO6;l*h z@S3?ql?FGhGf7&@(#&~03^ec6u^-rNal{lx(e*(3(EXhZdNpUdEQlUo{n^KKMhW<)xL|T z)d_gz#(C=3<}>A;-9%x z8#i{HyCSeRE7;}LLQ1I|lGg_tm;5ea^jR{YcZQgL36KNEJSBD$g*DZx&#_87W1_IO z8Ef2HB^uLnSSev_mrNB+RJX@$v5xcG12gH2Okc%1{wb4JqOi(@Ps|f8k{OhZ!;aBf z%oDT5EKw<=LtmAn24xaqqLSB~_|YGhr>u#_^mAEC_|Rl|1eqwTN!rn@(ciyDWqK1+rV0&WI!H(|F&j^7@hq>@Q5|;G(wV()On1Fl=a(qb_cdeSdn{ zVgv(8>?1c-cXsJ;O0sETD+-F-G}U|s15HDp)QQsHuP>Pt}A5zh^y=X&Ok&4zw z=6R80$3$9=icX2#>f!f;=t+@Zc^+oWx&&`r`67$}ks=i-iwk*eG5!M%C*>i{oCjw5oVq`Ha#V8Zpe3j6=K}P&yGunBqqrWo>0s;9L20 zB$St*fjkwnkP!FAdS_NNnwqvZmVTzO{OZQ?YZ^UUSe_YdSQ$J zFyIg4kizikvn(EP_UXi@f$Rm2y9-LaPt zUru}_@eblI5X;YYcvNBQR=1N~e!z2f`T5TA<6u0kbpD@H{-?mM9rlx5a$=H&Et16S zNB1H0Ml}(PPKYh8K8t-8o3LCv#}9!~l; z1@VK#4-;2luyFaSh$j=DLOh?ik@z;S^XL1-`-vCg=PsA0hxp^fHxqx8_}9d*5*MSv zU73@KXA@_LFCe~w_-^7K5dV(&ZQ@awH@kZ4h|eP4OneRT1H}7?Unj0W2Xf_~MBGBW ziug+6-NZj6-beg4aV4hOuCCd{3yCiz{uJ>b@mGl-CH@uhi^MWkyLu-OFCfkkUrc-r z@g2n9C4PqZRpK}X6Ibtv#Aguq5N{^lMf?ropAa7)euwxtJYZbC^~8&ayNS0F-#~mP z@uS4QA%2B8g2BhtJBhfC_$=a!h_4{NgZLrhCy5Ubze9XH9OFzDop=TDM&fITzefBB@$DuOblGT#}S`Nyo7iw@lN9Vh<`%-0&xTr z4_DWC;swO#5^o~Df%xBv_Yl8AT#3nytLs$avx(Oc?;zey`~%{ri2qESC7ysa&#vB? z#LdLZh&K>lMSKhKgTy~4ev$aUiN|1a=6skzynuKK@p|HaBK{)reZ-Fw|Bm=C#2&sr zI3JE8K9x8@yqtJ5@r}e^BmN=rZ;1au{37w6i4PLXJQ0sGY-{x%(;;k;q5)il1a6H3+*Ue1n*Vc|TqBps71 zrWV=gDC2EI~F5R(g|^s3!~N4_HeOxFzYBm>`cV zO3&Y<1!eP4M?|^hhsGur+2k$MY+^BMLD_N^BD2=^uHL$?dqZD;uj9V{3kDqbtX{pT zcU$ff(Y!UMW%8jRy|^`B>i|JRL9Ii5eGQVZt+n(7Zmd@7 z(OLjD*EJe-EZoV&^f7DC4TjS?tV70g@$Bcb9&z!XF z_-#1Xoips(@y4AP5(eMc?eqa^=Xk6dSKb@D_iDw!-O4B@F7@QN$jqtRWUc!Qs~y0N zY4sgLgL`*O-FGuo4^4x8*~V>$JXvEt-qvE&4oh>}P?R3WRGoMr`>-xYR;&jalCajn zc-^QXR@X2Cx`y$jYuMAZ7fOXerM)bR3{Fl}tjSR=?3nu8P}u`|W&U_w54?h!pv)7U z$>h`|=uAWvVYDSf$6PnAa$Rt)Qf~9$(9L_gnkTDWqUe~MI-vC>epy8avoD$YZ7W6p z@m4B6nEg?ny1}&4wDr=~|418&_9Lf_N+xYPnEm`e+DfID4h-8yebPqeOu3D`P#Y;- zqtWaj@1VLp=x^vt=zp%aiO1posL%uVdZJq}x(TUe2qlb3wd{(mzW10nvL~%UYGj61 zHMkx(G#E?8SBrLGtX4Hl)vAU&w5s8UhoZ2*dZ=Qc2;oWDV(b@YOR(RXElu6Ne>WuAh@?iSOq8do5ovlz)ecCd1bX^<}R@jaTQWD&$$RMh{INu&QD- zem%-jReTpun!G36XsfCyI~s{0RfSdi!P!F?QX#7N#5bh?JP}1GXj0wdagA!znhJAz zSRQ9Y75adFHTH-_74@gp*EvzeJQgU_=}-Qq_&>is?mBq%dHju&-E9K0`&azEx5|dC z>s#L&_ZAA3?~UVRS1xtQZj975KCF|x6(%poHVgT@34fQpstla-q{hl8biC z2i)4yVI>#(utJgx<3$02Mg|_MCkAdXExE7XNSX)SP zVQgW^g|&qx7uqP76|HD|3$Jz3>7hm(z+1L$M6E_6a6$whDk zmQNam1@*i_k_&xAA<2bKaCf+Ma-`Eb9q*3*X&HG$v(?W9k_%lh5}UB%FOXa~t6lbq z_dvZ$F2@T~=16Xg!`B?^#&D7gU2Xx%g|=G}MrgTS$dN*l3!Nc!k#7my7*2Ab55gMU zu;jv7aknGQNiLiF&_{EwoU>EdiE3O<%F0?IA za^W9u8l`~bLgxs#3VulP9m4`S*DAp}V||Q7rThGEeUchRx@8|_mkO@ceqUY6UyYsL zN{jKcSI|m@B^UZAd+WR(EtRJy%XjNP0=I^jT)4)P#k?WOg-ejhvhllAuf*mPkp<*| zF%|jx&-AmsUt};inBNxzIU6C%yr{OZq21!mVnq zr;%Lfl5EG6i)SSl&V?p(z3f77XU&mZ_+`k@Qb=;4Glbmj#Rpj5-4Sl%_r+b-FBpFh zC%MRXcszaw^&J+$gPpGw8VW;_i=Z+qQaa)mKAg+q!AL{p-oWKyB^TN|2qfgjlt*qL zxzH)jlq0!tM`;yCj^x6nX%&W>8EMIdPB9m=u;fB#2z8Uo#`>*(ILU=Ra2Uyj@yDt# z!jcP}R7i566P%|7B^NqJ$W{4a+IA4Th}(4$5?9c4ovglOB9L6@@||cx%sG+^oj$DO zB6M_)Nlvao!~h4xEI2uUuiRmM${ zT=?gJ<13++sv{= z#c6~j7uU%QDqnJOtV|b-0)r$M_ZzDyFi3LICQsQs$;ASB1m#LD8f2i)m0Y}Nj5(5v zn`OMplUyv6As|n3Q6?QSPjcb6Ls)Y0Ey-L+a&Z%Wj3_L*&?Oa=Tu=&2F0?sEa^Y-v zELJ^%s>Zy7#RNqYv)Fr)7(TI=Vd=F5BA+-7d(0_ zK-O_%q%1OT?Ee#8N0G1VU;zlkCt9^pGp?!iBm;_NG-c5~dV zK4e+^oaFOLCDIgE&J?h#SAL*$ZBk2lK1zAoi5C-}Yx7H8BExXyFZb;$RX5o;`1T%k zvCk`2Kk*i@^X&?2mo~Ycc#!x@mOc2e+vk<)PO#}e-Rdj8y+_?+S<3vnZ(phI^X)6u z13q`F2Pw~Y$^NL%E7fCQSJ%&c?oq$+d8K;V&)L?sA|6kC9PtUn=o;^vX6yJeb(h~>JwJm(XyB3?_}M=aMJ|6z-(Cy0MSEbZp<>?8gy@$ZRW zBR2mIp((!v?S>>>SEbKhQn*XoRq`0$9#_W`F9o}EUrF{y$u9qZo6D0WUW=bxo&8h9 zyNFrp^DDBm)Mpglrd&DGh!+qqA-;roJMlflj}t#b{3h{uysx=>Pay6jUPpWr@m<8f zBz}#!60dEp{0|ei688{aL3|tWBgD@VzeYSBFN3bGlZlrQuO+^g_*UZkiJu^Tn)olo zvRKm9TTNU?yo~q~;vK|y5r3cfx5RG~kHR4A>YYX0LVP~)r-*MNeu((z#4iySl?8Pj zMLeH4NqhnE<-~);_Ym(Pewz3oaS7ge-T59*JeRnWcpdR|#J3QCpLiefABl_bQtj$J ziuiQm6!8VbmlNMk`~dN9h+igthqwyw>duE+;skLo@yCg8B)*Gyi1>HJ?+{mEvgqoa zPCTFZeBz6V2Z`?^euDUU;{PHZhwlxp-dV&+;?>005PzBY5#pza4-%K-i-oJ}L}HO( zJNx;>R}g=J`0K=v5kF1*U&LkjCgRFJg}9mcJmLZ3Yl-hA{vPr3#Q#ZLfv+yE-l@d% ziB}N!6Au#q8}XCGFA*OiJ{}V%S8pxxGU6@7JBjZh{u%Le#3h(ay7EsZK8tug@n?v? zM*IlzGsLeG7n989SmHY3cH(a0t;E+8-$DEx;$IUVAQtVlJKu@Krw}(2FC*?JzM6P9 z@q@%q690ktP2y5~`*QwFCZ0`v7V#?LONnnH{yOmx@w3D%TWtNQ9imr34`>K`_BAoF`8vBzg`^1!>Ed2^H3GxT7!$LS5^ym$nOU80hpSd83|a zP2RMYAaH69Olpuv^c?w{w5DE`3}5B^m71sb(#FoxW-W3)g=9kKBK=5ZLc{;>Q1Vt( Gm;Da_e(M@UpV`^D5@f zpEs`}7UQyPP0GqEB?{YRh0m!1Rr_*Z-P^O3It4{5wb{8x&0gQ}x%E0^KJr3J?RJ#< zam<7hZk!ubvsbjOZ*w)fyFbs8zprv}_VS({Umct_Q&b7@BdDt6|KU_49&+O(O#%L9 zw|91RQUgwg_Nhrq?LsSMlTMbcN`E4KN3cR?xO(<(^C(}5_^6t|S0Vo=-TZBwt&b#~ zKA|TI8d@^AM{6{ zjoT>gRkPI2@>E{CDwO?^70xFEbqXEs@5-*z_Q?l!eXm44-@m^(;SB5>Xo+RZM9$SozMSVxkv8ZH@diYci>vYbtq}PvxzIK z_v8=z$8DU@%~x&j&Twkv@^I?e=J$^(e2zWp;B(2*5I*ldn%^D4zOp|rwe?q9j&}Ax zdgz%*zS@J44udbYNWLBC+jTgUS)8sYFHMw}mX^j6XC-FMiY2;Nbgb&=iX{`Vjg_-Y zXO~u&LA&B_)^)C0y*@Ux{q$Jb*=Nr^6GzO8Wja3B))Q;!>RG>T!`hCn^}_Al>#pct z*S5Z6g>ptLu1&V4+uPQ3)U~y*?_Q@IXAdgUnk|p$NM5uUk*A-8NX;W^lUJ^-NOi30 zfjm)UU(j)Lvg3@Pi0MEiE7nzqMOUur zZd&(u}I>8832?kq1m9S+x}YHM+RJ=KJVn?6a^E>cdU zZH=6Gx5*NSEXO2Clv$V%wMsyt6VsVAb)r3%({5W4U`Re%mV0^U} zb-oo!}+hU&;Mm^Zr}8NZPFacQcFZx#v44WX#lBp6P_m+*ZcL1;Cq!0%lN zh7;9GR6c14LaR{`){suR6Hm85bI=-7x1k!dET0;au1h8Cl^aiF(sglekgJ57bOhb} zMhNTpY8CaX=PLS$YDHIo98s;psm7W_x{e#}D(*Fdlb?O9$1l{C9I9ET52I$G48L6n z1X`uTVSHBeiPB+Pi=rI0Kmz1BR5j#X%Dq%-cx=tS+jKabY-*G-lCKw|3|rmC$ z=2s)L6h+u`oTyHe1;!=`;~Gnp^T4FTqE-Y(B?*f1%pAxt)(wlXV41$7J~YOHkJeeGq&knNHEg3{|m_QL0#7<04xx zRFSVs35Gv{I!OsbRq3l-r9@-uW3G~vFjSQm6mc*4L)pi8_Ks(8`@UbT+6;{D=X7K z%o|#QBc2Q`wVC6&jZ?)`-63w{kEFUC=5avvbrn?jcy4kBUtPLmG+OB2oOjpT}Arx_=c!3)=g zs=&W#tt4?ZOEQ=6FkmJ3Cc<-{AB=cQ8g6Pd)K%Sq@1xybuTLc|sPmpcwKa>fCuvr~ zD_WzD8{tn9tQ4+K$(s>h&aPr>N*9PeiE6l8@K9BqIohl0;#zrsE3=QLbYoqj{`~Cf zk{ULg&csuJXE@8@nuhoy88&Hnwvu;znrC(P=(M?6(dp3vXTjEVsK))!Z(J?D4wKO+ ztxk*Rmv8-oy-?m>O%N*HcSUs$8C8N%@qS;Q5|?TqmFV_2}bm+S8^CFKf1M=pzfzRqK?sNrJpeO))QV)$Nt2m#lEfl^3XCts7Za% zjGH2l1|5RtmNou>5hV!KEo;JcGQydlq%~!oI!6W#6O8C#M#`G_o~S0M`=L_QNnSrx zs))JKMUFin*Si~zxHpMJOul9eBCO!X=qqoE&dJ1-D>tS>j+sg^6)I9wlPVK=nwE7) zG@Z$GtKmUf{1}QFc?!N>&O1@QWOfQeQ?bKWkR?ts-iXf&HbnLD^$hj@>2herY^af#9VG%6?fqH3z#E1ZDr}c&ZY+Rs>~#Sv)ltyEX)6 zzdW9rhg~~@vR{!-;Gnv5W~01?him6;T?0V150Dl;ic0V0&8%1w%LfCv?- za+6{XK!nOvg-J0NAi}&y2#ZqlOp1Dd2o0%f9r3ADwFJ*krfZkfGzm5u z)TtIXH|bRP&a)PyeI~Bd2mKfZX#1f51PV#~xIp-PghJ|6d^(OATPWY?;%j35kH&sP%tHSs< z0$*ShoKv*0$gR%EN+tC!-h7>-p=1j{nt)$UZoCfdbu&U1N{!xzNGSt9e%u6<0=G-9 zV@Qg7}E<+$Hk)SBvTYrqHe}9=E8i z#5WReBfiDsR`n&Yt@DG#dx`&%_!+P%w^j8KA0U2>_zmJ;fNfd7CjJ9)7^l{zi4so) z+xAZKxJAW?n>crEc~iT{>(E3y1UXU2q9 zbsOpOW1ZFSCH-r}PZ0kLvHY}WkNqzAMD(LvSFcc-e*@e0{+x74i5V!iP*Uy}%ptIi z(s|%U)BJgS_G1%$FY$ijgT(I>k40JbSUE5Fhs{X}&o+VNS)M*hRS+tbHx8e{Cnc@cuv`J%ZTfVKSO*C@%_Y4 z62C(H8{!BCB3srB;&X}9#GS;Oi0>f&8gVc2LE_&L7vUjl>oAS@9O4Y|2I6hRdx@VW zewFw)#1RZiw%pT+7ZRt5JBe>0zK3`p@ehgLB0fSq5t9a6hf?Ac@k-*Wh;JwU2J!R6 zZxJ6M9)%Y~TkZ_vdg7(Tn~3iuevJ4f;-3*KOonV(zLj_n@qXfi#P1W2 z#RJHeJD0eg_;TXS#9t!*I&m-Y&xqe6J_Qp#TkcuJb;Qev*Awq1ewg?r;x~!^m$(>{ zOIz*?;s)YNi8m47Mf^?TSBQT}T!hK6Eo&liEpZ$1)x>uY|1EG^afifIRl?&9_VPEsdbe+!_!A8cgdcPIf~ir zs=yj|IXa9*Y)U1}vF<0YYeyu~1fq3-*Ro@xmpcuuN5`ZIY2;l~Qu`aPLC2&9X{7!G zH`8jonj(Mc}KpI(*K5(-&a8QP{U#YoXBCEs) zD2)NdE>JY0J?f%B8nbZJN;b`EE9laD5SqQBWBGBY4JofVaXI4dg3%IC#oyG%PP7QtDO zS9UCC#awi&I4d5SY#N((+Z=QEd9d>_B{qQ@Z+Dxi5_~mzKhWMR3EcgKW+n@w+A6|es>u8OU(oF0Z8K8x)!<0uHY46OE^?>xxi#}M~}aczkA zqC`7B%qsUPtan#C-@n^>5W>yMdH?P{I1~Q}B`f3nAOi5}=yPU86(#N{jl|FC1jfK79KxPMVU`PgihGRk?ENl$>mT;^k-1oFv^iw9B|*Oj+Vn>f70S@7~Q4-h=BT zs=l+yTwii6_u^W%^^&9euC;L`fw;bF5BKjl%2#La&PZz1a&bw7`o%vnN&6>m)c%Qw zkA|VVcC@fN5Brn)^YK~JKMbGk{hj?=j^-=5^QUZ-{OsL8J}ACpkH^Kdb?SgILGEDd zUos_5kg-$`L&m!yPm*>W{_}e`CSbBL;8AD28~0)IMcxhT!Pq6TJU?@IFuXYPY#kxV z%tO<0yf`E1IO_-T;*4Ou8)9R`b_7EmtQ%Kb>jq@|2yR!#xnVl-F|1t>=f(-rtUt!N zQC>QKzU$m53s^TQsib=!8hs;b@^{a~mWlOFJUk*bkA~QAGihsC1`HFie-Sebn#O$F(2E^y*W=UL9L0 z$9`;%5jl6qa*UjY_`jTEWUgFU;$09ENx(6pV{$k~jGogmqN4_LjF?E*L^8lJqGJbh zjOfUmju9P`!!cqC69)-9Mznei$B2#(I7S|j?itE4q7OqK4seW^TI6ty*dqowMs$Q( z>4r7SIUFN8L7<9o2ihu{r7d>Bk#7z$3m)~MzBs@!;>Ekpj%>$>j`u}(sg&^x=r~jF z0ge&xxEziV@3BU;OHjJR6BF=Di!W5m^hju91IB zh|V{cV?;;fa*X&#VD+alh|m>~%Q2#l$mJN(5%yZo=@`)|0_W&Hd>!C5%eXt-b|GNb z=nZlbyuz8byY9&%c_ORbEw|ki1$Ia8iP4TbiVGW%8n7OyB?CjYQsQ9aydqH zfCB#9;h*fddARjbE%{WH1 z?2Znymee{%v~C2w?9@6&JRS9uXzLj9^eo4Sr=yON-a1A+J25vCF@eQeETwg+ zCxo1i5uG4#3a-bucJ7rhh+{+_ljRt3wV-3fD_s|k)pxSKlKhMV3m=A;7O(KZ93x(~ z<`Qt%BWo3BjvXUf8{io6jyIi>!!e>$1bc-mCJVvco77(>t&fqQTt5HbI!Osb_0_5P zmC5TXS?c}qR!K@2s!ES>m1HTmTP1U+n3dUH?|(FBPf8i8S_%9{=JwR!juCtQWG!;Q zF=8Xc<6#<7pcj&JLuCEC?-gnO81bTTRBp$JP7%0b z|D78>h+{+_g=o*uvo#&+S<*1ZYg}%}$T#KfRZJe@HSioG7t5=d z2^wFB>lo2>$hZ~~6C;c0!@e%LSjUK~W;sS|+Mr`ZtI|5G+BffulJT(n}vTi`0t9f^t;%i^ekjuBm% z0ge$@&2o&qjwMM09V0re^i#kwBFmAGHrp}sOCxIs2{}eK$-HNPV`Q{EfsKKL93y*; zDy9y2JM`lpj*)xip_T0zxl+K9r#i^??m|; z8jg{>u=}fH1W(+*I!68?ju8x^v|R@F93fat8E}O7KOX7-;7S}JGvEjLy$ZdFSM*p( zD6bfwm=-jjU<@HhCg1qJX6qe$6uG!KBS zj%5KJf1T1iN&54|-zEMbr58(q>o(zasuMrI+8pY&~TSiaoXnZ0mU<>Eno}P?|GI zUqE~w@uw(#n)GEJx2YD7ThynC**>zG^lpz^RS)q7k6Y9=#Pa)~X=97pL@d7X^M8=|VUJtYBgEeTo9nPueT(#c#9~{q=j;2# zVq3AggI^-;c`P6vLp*_aIx#K{cZuAe-{z7;8?YtC?qYD1Dkp9S+hvm9CVf9~AMuOC zKOlaUnC&lTq8|{24doK+Uxi)$lcX;sP7|*pUQ68Lv6B?e=sZ>OI!_;^ZXo^^*tYjs z(kJ2PM5`|(ewz44#D|G7f%A@?L0n6`ocL-x63gSlMwZxl< zA0~c*_-$hR@1I^-G2(NGFDCvR@h;+jB7TAR7sOZ}FM#7_{v zNc;xzyTnmUENr<`h!+s2h%YDJLi}ao$BADe{w47d;z@WBwRNZG1#NQ-- zk@yW_2a_jT))?YS;s)Xt;vV8%#CwQeAU;U^YvO#oHQPF{jpl69TZnszw-Mh%{0#8{ z;&+KhVzOwf%qQceZ*|3 zd6)EJeE(s~okhHem@PG1NZ&>L6!DLUe?uI_w@xUru~0@z;s}mG~{BkP5c?+t;BZ`KT6z3e31Be#D!#GnMgc`xRH1T@ioME5dQ=5v&26leup@W$*S$= zal~cBi-=o@dx&o$zK8e;Vz$w|LHfJIMVR#3`mkMQA?cS8UqO65@$JNS5dR(VSBPcK zh({H+75WoXAZ!DzHs@+RXtlWznw@i&nkA4r)nK+8nTw`PKJF)*9uNt8N+4PX*yw=C zVD2;nY&Ur9yLGcUvOxipAmo$VqF{Q!+HRy*FjdRiFevFw(uN(eQXF;_e`n1KQj=rZ zZsfZg-*z+K&A?X@UY6D_bHM;bz7a5+O(XU8mE5+Q4K|6k-E2nacx^Yl!jzWq>NUiF IvIpn?0GB_0e*gdg literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..7108ffa --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm @@ -0,0 +1,42 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;; $Release Date: August 1, 2008 $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/v120/DSP2833x_common/source/DSP2833x_Adc.c b/v120/DSP2833x_common/source/DSP2833x_Adc.c new file mode 100644 index 0000000..730415b --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Adc.c @@ -0,0 +1,65 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#define ADC_usDELAY 5000L + +//--------------------------------------------------------------------------- +// InitAdc: +//--------------------------------------------------------------------------- +// This function initializes ADC to a known state. +// +void InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + + + + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. + // Before the first conversion is performed a 5ms delay must be observed + // after power up to give all analog circuits time to power up and settle + + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01; + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +//pause_us(50L); +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm b/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm new file mode 100644 index 0000000..27eb60a --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm @@ -0,0 +1,67 @@ +;// TI File $Revision: /main/3 $ +;// Checkin $Date: June 26, 2007 16:41:07 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CSMPasswords.asm +;// +;// TITLE: DSP2833x Code Security Module Passwords. +;// +;// DESCRIPTION: +;// +;// This file is used to specify password values to +;// program into the CSM password locations in Flash +;// at 0x33FFF8 - 0x33FFFF. +;// +;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are +;// all programmed to 0x0000 +;// +;//########################################################################### +;// +;// Original source based on D.A. +;// +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + +; The "csmpasswords" section contains the actual CSM passwords that will be +; linked and programmed into to the CSM password locations (PWL) in flash. +; These passwords must be known in order to unlock the CSM module. +; All 0xFFFF's (erased) is the default value for the password locations (PWL). + +; It is recommended that all passwords be left as 0xFFFF during code +; development. Passwords of 0xFFFF do not activate code security and dummy +; reads of the CSM PWL registers is all that is required to unlock the CSM. +; When code development is complete, modify the passwords to activate the +; code security module. + + .sect "csmpasswds" + + .int 0xFFFF ;PWL0 (LSW of 128-bit password) + .int 0xFFFF ;PWL1 + .int 0xFFFF ;PWL2 + .int 0xFFFF ;PWL3 + .int 0xFFFF ;PWL4 + .int 0xFFFF ;PWL5 + .int 0xFFFF ;PWL6 + .int 0xFFFF ;PWL7 (MSW of 128-bit password) + +;---------------------------------------------------------------------- + +; For code security operation, all addresses between 0x33FF80 and +; 0X33fff5 cannot be used as program code or data. These locations +; must be programmed to 0x0000 when the code security password locations +; (PWL) are programmed. If security is not a concern, then these addresses +; can be used for code or data. + +; The section "csm_rsvd" can be used to program these locations to 0x0000. + + .sect "csm_rsvd" + .loop (33FFF5h - 33FF80h + 1) + .int 0x0000 + .endloop + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm b/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm new file mode 100644 index 0000000..430efa3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm @@ -0,0 +1,86 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:45:55 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example DSP2833x projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot.asm in RTS library + .endif + +;end codestart section + + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot.asm in RTS library + + .endif + +;end wd_disable + + + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..b0dfd76 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c @@ -0,0 +1,115 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 16, 2007 08:37:30 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS. +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// InitCpuTimers: +//--------------------------------------------------------------------------- +// This function initializes all three CPU timers to a known state. +// +void InitCpuTimers(void) +{ + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + CpuTimer0.RegsAddr = &CpuTimer0Regs; + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer0.InterruptCount = 0; + + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// Initialize address pointers to respective timer registers: + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + // Initialize timer period to maximum: + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + // Make sure timers are stopped: + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; + +} + +//--------------------------------------------------------------------------- +// ConfigCpuTimer: +//--------------------------------------------------------------------------- +// This function initializes the selected timer to the period specified +// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" +// and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // Initialize timer period: + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + Timer->RegsAddr->PRD.all = temp; + + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // Initialize timer control register: + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt + + // Reset interrupt counter: + Timer->InterruptCount = 0; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm b/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm new file mode 100644 index 0000000..7c226ce --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm @@ -0,0 +1,28 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:03 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Useage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + diff --git a/v120/DSP2833x_common/source/DSP2833x_DMA.c b/v120/DSP2833x_common/source/DSP2833x_DMA.c new file mode 100644 index 0000000..83c4f3c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DMA.c @@ -0,0 +1,590 @@ +//########################################################################### +// +// FILE: DSP2833x_DMA.c +// +// TITLE: DSP2833x Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // Perform a hard reset on DMA + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm (" nop"); // one NOP required after HARDRESET + + // Allow DMA to run free on emulation suspend + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + + +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + // Set up SOURCE address: + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH1.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH1.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 1. +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH2.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH2.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH2.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH2.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE + + EDIS; +} + + + +// This function starts DMA Channel 2. +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + + + +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH3.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH3.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH3.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 3. +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + + +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE + + EDIS; +} + + +// This function starts DMA Channel 4. +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + + +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + + // Set up BURST registers: + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + EDIS; +} + +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + + // Set up TRANSFER registers: + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + + // Set up WRAP registers: + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 5. +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + + + +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // Set up SOURCE address: + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // Set up DESTINATION address: + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + + EDIS; +} + +void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) +{ + EALLOW; + + // Set up BURST registers: + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred + + + EDIS; +} + +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // Set up TRANSFER registers: + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs + + EDIS; +} + +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep) +{ + EALLOW; + + // Set up WRAP registers: + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + + +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // Set up MODE Register: + DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source + DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer + DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable + + // Clear any spurious flags: + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // Initialize PIE vector for CPU interrupt: + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE + + EDIS; +} + +// This function starts DMA Channel 6. +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c b/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c new file mode 100644 index 0000000..df76fda --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c @@ -0,0 +1,1187 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: January 14, 2008 11:17:46 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.c +// +// TITLE: DSP2833x Device Default Interrupt Service Routines. +// +// This file contains shell ISR routines for the 2833x PIE vector table. +// Typically these shell ISR routines can be used to populate the entire PIE +// vector table during device debug. In this manner if an interrupt is taken +// during firmware development, there will always be an ISR to catch it. +// +// As develpment progresses, these ISR rotuines can be eliminated and replaced +// with the user's own ISR routines for each interrupt. Since these shell ISRs +// include infinite loops they will typically not be included as-is in the final +// production firmware. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// Note CPU-Timer2 is reserved for TI use. +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm(" ESTOP0"); + for(;;); + +} + + +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + + +} + +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// INT1.1 +interrupt void SEQ1INT_ISR(void) //SEQ1 ADC +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + + asm (" ESTOP0"); + for(;;); + +} + +// INT1.2 +interrupt void SEQ2INT_ISR(void) //SEQ2 ADC +{ + + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + + asm(" ESTOP0"); + for(;;); + +} +// INT1.3 - Reserved + +// INT1.4 +interrupt void XINT1_ISR(void) +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT1.5 +interrupt void XINT2_ISR(void) +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT1.6 +interrupt void ADCINT_ISR(void) // ADC +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT1.7 +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT1.8 +interrupt void WAKEINT_ISR(void) // WD, LOW Power +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// INT2.1 +interrupt void EPWM1_TZINT_ISR(void) // EPWM-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.2 +interrupt void EPWM2_TZINT_ISR(void) // EPWM-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.3 +interrupt void EPWM3_TZINT_ISR(void) // EPWM-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT2.4 +interrupt void EPWM4_TZINT_ISR(void) // EPWM-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// INT2.5 +interrupt void EPWM5_TZINT_ISR(void) // EPWM-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.6 +interrupt void EPWM6_TZINT_ISR(void) // EPWM-6 +{ + // Insert ISR Code here + + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT2.7 - Reserved +// INT2.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + +// INT 3.1 +interrupt void EPWM1_INT_ISR(void) // EPWM-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.2 +interrupt void EPWM2_INT_ISR(void) // EPWM-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.3 +interrupt void EPWM3_INT_ISR(void) // EPWM-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.4 +interrupt void EPWM4_INT_ISR(void) // EPWM-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.5 +interrupt void EPWM5_INT_ISR(void) // EPWM-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.6 +interrupt void EPWM6_INT_ISR(void) // EPWM-6 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT3.7 - Reserved +// INT3.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + +// INT 4.1 +interrupt void ECAP1_INT_ISR(void) // ECAP-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.2 +interrupt void ECAP2_INT_ISR(void) // ECAP-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.3 +interrupt void ECAP3_INT_ISR(void) // ECAP-3 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.4 +interrupt void ECAP4_INT_ISR(void) // ECAP-4 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT4.5 +interrupt void ECAP5_INT_ISR(void) // ECAP-5 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +// INT4.6 +interrupt void ECAP6_INT_ISR(void) // ECAP-6 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +// INT4.7 - Reserved +// INT4.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// INT 5.1 +interrupt void EQEP1_INT_ISR(void) // EQEP-1 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT5.2 +interrupt void EQEP2_INT_ISR(void) // EQEP-2 +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT5.3 - Reserved +// INT5.4 - Reserved +// INT5.5 - Reserved +// INT5.6 - Reserved +// INT5.7 - Reserved +// INT5.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// INT6.1 +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.2 +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.3 +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.4 +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.5 +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.6 +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT6.7 - Reserved +// INT6.8 - Reserved + + + + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// INT7.1 +interrupt void DINTCH1_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.2 +interrupt void DINTCH2_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.3 +interrupt void DINTCH3_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.4 +interrupt void DINTCH4_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.5 +interrupt void DINTCH5_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.6 +interrupt void DINTCH6_ISR(void) // DMA +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT7.7 - Reserved +// INT7.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// INT8.1 +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT8.2 +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +// INT8.3 - Reserved +// INT8.4 - Reserved + +// INT8.5 +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT8.6 +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT8.7 - Reserved +// INT8.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// INT9.1 +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.2 +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + + +// INT9.3 +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.4 +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.5 +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.6 +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.7 +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT9.8 +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU INT10 +// ----------------------------------------------------------- + +// INT10.1 - Reserved +// INT10.2 - Reserved +// INT10.3 - Reserved +// INT10.4 - Reserved +// INT10.5 - Reserved +// INT10.6 - Reserved +// INT10.7 - Reserved +// INT10.8 - Reserved + + +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU INT11 +// ----------------------------------------------------------- + +// INT11.1 - Reserved +// INT11.2 - Reserved +// INT11.3 - Reserved +// INT11.4 - Reserved +// INT11.5 - Reserved +// INT11.6 - Reserved +// INT11.7 - Reserved +// INT11.8 - Reserved + +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU INT12 +// ----------------------------------------------------------- + +// INT12.1 +interrupt void XINT3_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.2 +interrupt void XINT4_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.3 +interrupt void XINT5_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +// INT12.4 +interrupt void XINT6_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.5 +interrupt void XINT7_ISR(void) // External Interrupt +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +// INT12.6 - Reserved +// INT12.7 +interrupt void LVF_ISR(void) // Latched overflow +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +// INT12.8 +interrupt void LUF_ISR(void) // Latched underflow +{ + // Insert ISR Code here + + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_common/source/DSP2833x_DisInt.asm b/v120/DSP2833x_common/source/DSP2833x_DisInt.asm new file mode 100644 index 0000000..2e8e35c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_DisInt.asm @@ -0,0 +1,65 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:09 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DisInt.asm +;// +;// TITLE: Disable and Restore INTM and DBGM +;// +;// Function Prototypes: +;// +;// Uint16 DSP28x_DisableInt(); +;// and void DSP28x_RestoreInt(Uint16 Stat0); +;// +;// Usage: +;// +;// DSP28x_DisableInt() sets both the INTM and DBGM +;// bits to disable maskable interrupts. Before doing +;// this, the current value of ST1 is stored on the stack +;// so that the values can be restored later. The value +;// of ST1 before the masks are set is returned to the +;// user in AL. This is then used to restore their state +;// via the DSP28x_RestoreInt(Uint16 ST1) function. +;// +;// Example +;// +;// Uint16 StatusReg1 +;// StatusReg1 = DSP28x_DisableInt(); +;// +;// ... May also want to disable INTM here +;// +;// ... code here +;// +;// DSP28x_RestoreInt(StatusReg1); +;// +;// ... Restore INTM enable +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + + + + .def _DSP28x_DisableInt + .def _DSP28x_RestoreInt + + +_DSP28x_DisableInt: + PUSH ST1 + SETC INTM,DBGM + MOV AL, *--SP + LRETR + +_DSP28x_RestoreInt: + MOV *SP++, AL + POP ST1 + LRETR + + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/v120/DSP2833x_common/source/DSP2833x_ECan.c b/v120/DSP2833x_common/source/DSP2833x_ECan.c new file mode 100644 index 0000000..612ccb1 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ECan.c @@ -0,0 +1,404 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: June 25, 2008 15:19:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.c +// +// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + + +//--------------------------------------------------------------------------- +// InitECan: +//--------------------------------------------------------------------------- +// This function initializes the eCAN module to a known state. +// +void InitECan(void) +{ + InitECana(); +#if DSP28_ECANB + InitECanb(); +#endif // if DSP28_ECANB +} + +void InitECana(void) // Initialize eCAN-A module +{ +/* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + +struct ECAN_REGS ECanaShadow; + + EALLOW; // EALLOW enables access to protected bits + +/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + +/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + +/* Initialize all bits of 'Master Control Field' to zero */ +// Some bits of MSGCTRL register come up in an unknown state. For proper operation, +// all bits (including reserved bits) of MSGCTRL must be initialized to zero + + ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; + +// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again +// as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ + + ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ + + ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFF; + + +/* Configure bit timing parameters for eCANA*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0; + + #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps + See Note at End of File */ + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 2; + ECanaShadow.CANBTC.bit.TSEG1REG = 10; + #endif + #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps + See Note at End of File */ + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 1; + ECanaShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + + ECanaShadow.CANBTC.bit.SAM = 1; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. + +/* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} + + +#if (DSP28_ECANB) +void InitECanb(void) // Initialize eCAN-B module +{ +/* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + +struct ECAN_REGS ECanbShadow; + + EALLOW; // EALLOW enables access to protected bits + +/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + +/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + +/* Initialize all bits of 'Master Control Field' to zero */ +// Some bits of MSGCTRL register come up in an unknown state. For proper operation, +// all bits (including reserved bits) of MSGCTRL must be initialized to zero + + ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000; + +// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again +// as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ + + ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ + + ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFF; + + +/* Configure bit timing parameters for eCANB*/ + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared.. + + + ECanbShadow.CANBTC.all = 0; + + #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps + See Note at end of file */ + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 2; + ECanbShadow.CANBTC.bit.TSEG1REG = 10; + #endif + #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps + See Note at end of file */ + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 1; + ECanbShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanbShadow.CANBTC.bit.SAM = 1; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. + + +/* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} +#endif // if DSP28_ECANB + + +//--------------------------------------------------------------------------- +// Example: InitECanGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as eCAN pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for CANTXA/B operation. +// Only one GPIO pin shoudl be enabled for CANRXA/B operation. +// Comment out other unwanted lines. + + +void InitECanGpio(void) +{ + InitECanaGpio(); +#if (DSP28_ECANB) + InitECanbGpio(); +#endif // if DSP28_ECANB +} + +void InitECanaGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected CAN pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) +// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA) + + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA) +// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA) + +/* Set qualification for selected CAN pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA) + + +/* Configure eCAN-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation + + EDIS; +} + +#if (DSP28_ECANB) +void InitECanbGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected CAN pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB) + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB) +// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB) + +/* Set qualification for selected CAN pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB) + +/* Configure eCAN-B pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation + + EDIS; +} +#endif // if DSP28_ECANB + +/* +Note: Bit timing parameters must be chosen based on the network parameters such +as the sampling point desired and the propagation delay of the network. +The propagation delay is a function of length of the cable, delay introduced by +the transceivers and opto/galvanic-isolators (if any). + +The parameters used in this file must be changed taking into account the above +mentioned factors in order to arrive at the bit-timing parameters suitable +for a network. + +*/ diff --git a/v120/DSP2833x_common/source/DSP2833x_ECap.c b/v120/DSP2833x_common/source/DSP2833x_ECap.c new file mode 100644 index 0000000..cd1d24d --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ECap.c @@ -0,0 +1,255 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 15, 2007 16:54:36 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.c +// +// TITLE: DSP2833x eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitECap: +//--------------------------------------------------------------------------- +// This function initializes the eCAP(s) to a known state. +// +void InitECap(void) +{ + // Initialize eCAP1/2/3 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitECapGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ECAP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. + +void InitECapGpio() +{ + + InitECap1Gpio(); +#if (DSP28_ECAP2) + InitECap2Gpio(); +#endif // endif DSP28_ECAP2 +#if (DSP28_ECAP3) + InitECap3Gpio(); +#endif // endif DSP28_ECAP3 +#if (DSP28_ECAP4) + InitECap4Gpio(); +#endif // endif DSP28_ECAP4 +#if (DSP28_ECAP5) + InitECap5Gpio(); +#endif // endif DSP28_ECAP5 +#if (DSP28_ECAP6) + InitECap6Gpio(); +#endif // endif DSP28_ECAP6 +} + +void InitECap1Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1) + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1) +// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1) + + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; // Synch to SYSCLKOUT GPIO5 (CAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Synch to SYSCLKOUT GPIO34 (CAP1) + +/* Configure eCAP-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP1 functional pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1 + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1 +// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1 + + EDIS; +} + +#if DSP28_ECAP2 +void InitECap2Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2) +// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2) +// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT GPIO7 (CAP2) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Synch to SYSCLKOUT GPIO25 (CAP2) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Synch to SYSCLKOUT GPIO37 (CAP2) + +/* Configure eCAP-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2 +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2 +// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2 + + EDIS; +} +#endif // endif DSP28_ECAP2 + +#if DSP28_ECAP3 +void InitECap3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3) + +/* Configure eCAP-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3 +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3 + + EDIS; +} +#endif // endif DSP28_ECAP3 + + +#if DSP28_ECAP4 +void InitECap4Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4) + +/* Configure eCAP-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4 + + EDIS; +} +#endif // endif DSP28_ECAP4 + + +#if DSP28_ECAP5 +void InitECap5Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5) +// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5 +// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5 + + EDIS; +} +#endif // endif DSP28_ECAP5 + + +#if DSP28_ECAP6 +void InitECap6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6) +// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6 +// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6 + + EDIS; +} +#endif // endif DSP28_ECAP6 + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_EPwm.c b/v120/DSP2833x_common/source/DSP2833x_EPwm.c new file mode 100644 index 0000000..64f0e0f --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_EPwm.c @@ -0,0 +1,316 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:19 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.c +// +// TITLE: DSP2833x ePWM Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitEPwm: +//--------------------------------------------------------------------------- +// This function initializes the ePWM(s) to a known state. +// +void InitEPwm(void) +{ + // Initialize ePWM1/2/3/4/5/6 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitEPwmGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ePWM pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); +#if DSP28_EPWM4 + InitEPwm4Gpio(); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 + InitEPwm5Gpio(); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 + InitEPwm6Gpio(); +#endif // endif DSP28_EPWM6 +} + +void InitEPwm1Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B) + +/* Configure ePWM-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM1 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + + EDIS; +} + +void InitEPwm2Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B) + +/* Configure ePWM-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + + EDIS; +} + +void InitEPwm3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B) + +/* Configure ePWM-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + + EDIS; +} + + +#if DSP28_EPWM4 +void InitEPwm4Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B) + +/* Configure ePWM-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + + EDIS; +} +#endif // endif DSP28_EPWM4 + + +#if DSP28_EPWM5 +void InitEPwm5Gpio(void) +{ + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B) + +/* Configure ePWM-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + + EDIS; +} +#endif // endif DSP28_EPWM5 + + +#if DSP28_EPWM6 +void InitEPwm6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B) + +/* Configure ePWM-6 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be ePWM6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + + EDIS; +} +#endif // endif DSP28_EPWM6 + +//--------------------------------------------------------------------------- +// Example: InitEPwmSyncGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as ePWM Synch pins +// + +void InitEPwmSyncGpio(void) +{ + + EALLOW; + +/* Configure EPWMSYNCI */ + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO32 (EPWMSYNCI) + +/* Set qualification for selected pins to asynch only */ +// This will select synch to SYSCLKOUT for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI) + +/* Configure EPwmSync pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be EPwmSync functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; // Enable pull-up on GPIO6 (EPWMSYNCI) +// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2; // Enable pull-up on GPIO32 (EPWMSYNCI) + + + +/* Configure EPWMSYNC0 */ + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNC0) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO33 (EPWMSYNC0) + +// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Enable pull-up on GPIO6 (EPWMSYNC0) + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Enable pull-up on GPIO33 (EPWMSYNC0) + +} + + + +//--------------------------------------------------------------------------- +// Example: InitTzGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as Trip Zone (TZ) pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +void InitTzGpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4) + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5) +// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5) + + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6) +// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6) + + +/* Configure TZ pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be TZ functional pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4 + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5 +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5 + + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6 +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6 + + EDIS; +} + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_EQep.c b/v120/DSP2833x_common/source/DSP2833x_EQep.c new file mode 100644 index 0000000..cb6ad92 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_EQep.c @@ -0,0 +1,154 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: July 27, 2007 11:55:20 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.c +// +// TITLE: DSP2833x eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitEQep: +//--------------------------------------------------------------------------- +// This function initializes the eQEP(s) to a known state. +// +void InitEQep(void) +{ + // Initialize eQEP1/2 + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitEQepGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as eQEP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. + +void InitEQepGpio() +{ +#if DSP28_EQEP1 + InitEQep1Gpio(); +#endif // endif DSP28_EQEP1 +#if DSP28_EQEP2 + InitEQep2Gpio(); +#endif // endif DSP28_EQEP2 +} + +#if DSP28_EQEP1 +void InitEQep1Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I) + + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync to SYSCLKOUT GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync to SYSCLKOUT GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync to SYSCLKOUT GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync to SYSCLKOUT GPIO53 (EQEP1I) + +/* Configure eQEP-1 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eQEP1 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + +// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A +// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B +// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S +// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + + + EDIS; +} +#endif // if DSP28_EQEP1 + + + +#if DSP28_EQEP2 +void InitEQep2Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S) + +/* Configure eQEP-2 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eQEP2 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S + + + EDIS; +} +#endif // endif DSP28_EQEP2 + + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Gpio.c b/v120/DSP2833x_common/source/DSP2833x_Gpio.c new file mode 100644 index 0000000..c615f0d --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Gpio.c @@ -0,0 +1,69 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:25 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.c +// +// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitGpio: +//--------------------------------------------------------------------------- +// This function initializes the Gpio to a known (default) state. +// +// For more details on configuring GPIO's as peripheral functions, +// refer to the individual peripheral examples and/or GPIO setup example. +void InitGpio(void) +{ + EALLOW; + + // Each GPIO pin can be: + // a) a GPIO input/output + // b) peripheral function 1 + // c) peripheral function 2 + // d) peripheral function 3 + // By default, all are GPIO Inputs + GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 + GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 + GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 + GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 + GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 + GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 + + GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs + GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs + GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs + + // Each input can have different qualification + // a) input synchronized to SYSCLKOUT + // b) input qualified by a sampling window + // c) input sent asynchronously (valid for peripheral inputs only) + GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT + + // Pull-ups can be enabled or disabled. + GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 + GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 + GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 + + //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 + //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 + //GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79 + + EDIS; + +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_I2C.c b/v120/DSP2833x_common/source/DSP2833x_I2C.c new file mode 100644 index 0000000..fda73d3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_I2C.c @@ -0,0 +1,76 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:27 $ +//########################################################################### +// +// FILE: DSP2833x_I2C.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitI2C: +//--------------------------------------------------------------------------- +// This function initializes the I2C to a known state. +// +void InitI2C(void) +{ + // Initialize I2C-A: + + //tbd... +} + +//--------------------------------------------------------------------------- +// Example: InitI2CGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SDAA operation. +// Only one GPIO pin shoudl be enabled for SCLA operation. +// Comment out other unwanted lines. + +void InitI2CGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + +/* Configure SCI pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be I2C functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation + + EDIS; +} + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c b/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c new file mode 100644 index 0000000..302c330 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c @@ -0,0 +1,349 @@ + // TI File $Revision: /main/16 $ +// Checkin $Date: October 3, 2007 14:50:19 $ +//########################################################################### +// +// FILE: DSP2833x_McBSP.c +// +// TITLE: DSP2833x Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY +// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT. +// +// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h +//--------------------------------------------------------------------------- + +#if CPU_FRQ_150MHZ // For 150 MHz SYSCLKOUT(default) + #define CPU_SPD 150E6 + #define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples +#endif +#if CPU_FRQ_100MHZ // For 100 MHz SYSCLKOUT + #define CPU_SPD 100E6 + #define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples +#endif + +#define CLKGDV_VAL 1 +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) // # of CPU cycles in 2 SRG cycles-init delay +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay +//--------------------------------------------------------------------------- +// InitMcbsp: +//--------------------------------------------------------------------------- +// This function initializes the McBSP to a known state. +// + +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +void InitMcbsp(void) +{ + InitMcbspa(); + #if DSP28_MCBSPB + InitMcbspb(); + #endif // end DSP28_MCBSPB +} + +void InitMcbspa(void) +{ +// McBSP-A register settings + + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode. + + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspaRegs.RCR1.all=0x0; + + McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + + McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1) + + delay_loop(); // Wait at least 2 SRG clock cycles + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset + +} + + +#if (DSP28_MCBSPB) +void InitMcbspb(void) +{ + +// McBSP-B register settings + + McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode. + + McbspbRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspbRegs.RCR1.all=0x0; + + McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspbRegs.XCR1.all=0x0; + + McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1) + + McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + delay_loop(); // Wait at least 2 SRG clock cycles + McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset + +} + + +#endif // end DSP28_MCBSPB + +// McBSP-A Data Lengths +void InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +void InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +void InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +void InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +void InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +void InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +// McBSP-B Data Lengths +#if (DSP28_MCBSPB) + +void InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +void InitMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +void InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +void InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +void InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +void InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +#endif //end DSP28_MCBSPB + + + +void InitMcbspGpio(void) +{ + InitMcbspaGpio(); + #if DSP28_MCBSPB + InitMcbspbGpio(); + #endif // end DSP28_MCBSPB +} + +void InitMcbspaGpio(void) +{ + EALLOW; + +/* Configure McBSP-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be McBSP functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed) + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed) + +/* Set qualification for selected input pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed) + + EDIS; +} + +#if DSP28_MCBSPB +void InitMcbspbGpio(void) +{ + EALLOW; +/* Configure McBSP-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be McBSP functional pins. +// Comment out other unwanted lines. + + //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin (Comment as needed) + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin (Comment as needed) + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin (Comment as needed) + //GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin (Comment as needed) + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (MDXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (MDXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (MDRB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (MDRB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (MCLKXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (MCLKRB) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (MCLKRB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (MFSXB) (Comment as needed) + //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (MFSXB) (Comment as needed) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (MFSRB) (Comment as needed) + //GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (MFSRB) (Comment as needed) + + +/* Set qualification for selected input pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed) + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) (Comment as needed) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed) + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) (Comment as needed) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed) + + + EDIS; +} +#endif // end DSP28_MCBSPB + +void delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles +} + +void clkg_delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles +} +//=========================================================================== +// No more. +//=========================================================================== + + + + + + + + + + + diff --git a/v120/DSP2833x_common/source/DSP2833x_MemCopy.c b/v120/DSP2833x_common/source/DSP2833x_MemCopy.c new file mode 100644 index 0000000..f7cba01 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_MemCopy.c @@ -0,0 +1,45 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:33 $ +//########################################################################### +// +// FILE: DSP2833x_MemCopy.c +// +// TITLE: Memory Copy Utility +// +// ASSUMPTIONS: +// +// +// +// DESCRIPTION: +// +// This function will copy the specified memory contents from +// one location to another. +// +// Uint16 *SourceAddr Pointer to the first word to be moved +// SourceAddr < SourceEndAddr +// Uint16* SourceEndAddr Pointer to the last word to be moved +// Uint16* DestAddr Pointer to the first destination word +// +// No checks are made for invalid memory locations or that the +// end address is > then the first start address. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) +{ + while(SourceAddr < SourceEndAddr) + { + *DestAddr++ = *SourceAddr++; + } + return; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..f1eafe3 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:35 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitPieCtrl: +//--------------------------------------------------------------------------- +// This function initializes the PIE control registers to a known state. +// +void InitPieCtrl(void) +{ + // Disable Interrupts at the CPU level: + DINT; + + // Disable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // Clear all PIEIER registers: + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // Clear all PIEIFR registers: + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; + + +} + +//--------------------------------------------------------------------------- +// EnableInterrupts: +//--------------------------------------------------------------------------- +// This function enables the PIE module and CPU interrupts +// +void EnableInterrupts() +{ + + // Enable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enables PIE to drive a pulse into the CPU + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // Enable Interrupts at the CPU level + EINT; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_PieVect.c b/v120/DSP2833x_common/source/DSP2833x_PieVect.c new file mode 100644 index 0000000..d163c54 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_PieVect.c @@ -0,0 +1,204 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:38 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + +// Non-Peripheral Interrupts + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + +// Group 2 PIE Vectors + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + +// Group 3 PIE Vectors + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + +// Group 4 PIE Vectors + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + +// Group 5 PIE Vectors + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + +// Group 6 PIE Vectors + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + +// Group 7 PIE Vectors + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + +// Group 8 PIE Vectors + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + +// Group 9 PIE Vectors + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + +// Group 10 PIE Vectors + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + +// Group 11 PIE Vectors + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + +// Group 12 PIE Vectors + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + *Dest++ = *Source++; + EDIS; + + // Enable the PIE Vector Table + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..bf821e1 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c @@ -0,0 +1,1863 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 14, 2008 11:28:12 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines. +// +//########################################################################### +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +#if (INT13PL != 0) +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + IER |= MINT13; // Set "global" priority + EINT; + + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT14 of CPU (use MINT14 mask): +#if (INT14PL != 0) +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + IER |= MINT14; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT15 of CPU (use MINT15 mask): +#if (INT15PL != 0) +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + IER |= MINT15; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT16 of CPU (use MINT16 mask): +#if (INT16PL != 0) +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + IER |= MINT16; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to EMUINT of CPU (non-maskable): +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// Connected to NMI of CPU (non-maskable): +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// Connected to PIEIER1_1 (use MINT1 and MG11 masks): +#if (G11PL != 0) +interrupt void SEQ1INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_2 (use MINT1 and MG12 masks): +#if (G12PL != 0) +interrupt void SEQ2INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER1_4 (use MINT1 and MG14 masks): +#if (G14PL != 0) +interrupt void XINT1_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_5 (use MINT1 and MG15 masks): +#if (G15PL != 0) +interrupt void XINT2_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// Connected to PIEIER1_6 (use MINT1 and MG16 masks): +#if (G16PL != 0) +interrupt void ADCINT_ISR(void) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_7 (use MINT1 and MG17 masks): +#if (G17PL != 0) +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_8 (use MINT1 and MG18 masks): +#if (G18PL != 0) +interrupt void WAKEINT_ISR(void) // WD/LPM +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// Connected to PIEIER2_1 (use MINT2 and MG21 masks): +#if (G21PL != 0) +interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_2 (use MINT2 and MG22 masks): +#if (G22PL != 0) +interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_3 (use MINT2 and MG23 masks): +#if (G23PL != 0) +interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_4 (use MINT2 and MG24 masks): +#if (G24PL != 0) +interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_5 (use MINT2 and MG25 masks): +#if (G25PL != 0) +interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_6 (use MINT2 and MG26 masks): +#if (G26PL != 0) +interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + + +// Connected to PIEIER3_1 (use MINT3 and MG31 masks): +#if (G31PL != 0) +interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER3_2 (use MINT3 and MG32 masks): +#if (G32PL != 0) +interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_3 (use MINT3 and MG33 masks): +#if (G33PL != 0) +interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_4 (use MINT3 and MG34 masks): +#if (G34PL != 0) +interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_5 (use MINT3 and MG35 masks): +#if (G35PL != 0) +interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_6 (use MINT3 and MG36 masks): +#if (G36PL != 0) +interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + + +// Connected to PIEIER4_1 (use MINT4 and MG41 masks): +#if (G41PL != 0) +interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_2 (use MINT4 and MG42 masks): +#if (G42PL != 0) +interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_3 (use MINT4 and MG43 masks): +#if (G43PL != 0) +interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_4 (use MINT4 and MG44 masks): +#if (G44PL != 0) +interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_5 (use MINT4 and MG45 masks): +#if (G45PL != 0) +interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_6 (use MINT4 and MG46 masks): +#if (G46PL != 0) +interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// Connected to PIEIER5_1 (use MINT5 and MG51 masks): +#if (G51PL != 0) +interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER5_2 (use MINT5 and MG52 masks): +#if (G52PL != 0) +interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// Connected to PIEIER6_1 (use MINT6 and MG61 masks): +#if (G61PL != 0) +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_2 (use MINT6 and MG62 masks): +#if (G62PL != 0) +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER6_3 (use MINT6 and MG63 masks): +#if (G63PL != 0) +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_4 (use MINT6 and MG64 masks): +#if (G64PL != 0) +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER6_5 (use MINT6 and MG65 masks): +#if (G65PL != 0) +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_6 (use MINT6 and MG66 masks): +#if (G66PL != 0) +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// Connected to PIEIER7_1 (use MINT7 and MG71 masks): +#if (G71PL != 0) +interrupt void DINTCH1_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_2 (use MINT7 and MG72 masks): +#if (G72PL != 0) +interrupt void DINTCH2_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER7_3 (use MINT7 and MG73 masks): +#if (G73PL != 0) +interrupt void DINTCH3_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_4 (use MINT7 and MG74 masks): +#if (G74PL != 0) +interrupt void DINTCH4_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER7_5 (use MINT7 and MG75 masks): +#if (G75PL != 0) +interrupt void DINTCH5_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_6 (use MINT7 and MG76 masks): +#if (G76PL != 0) +interrupt void DINTCH6_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// Connected to PIEIER8_1 (use MINT8 and MG81 masks): +#if (G81PL != 0) +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_2 (use MINT8 and MG82 masks): +#if (G82PL != 0) +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_5 (use MINT8 and MG85 masks): +#if (G85PL != 0) +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_6 (use MINT8 and MG86 masks): +#if (G82PL != 0) +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT9 and MG91 masks): +#if (G91PL != 0) +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_2 (use MINT9 and MG92 masks): +#if (G92PL != 0) +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER9_3 (use MINT9 and MG93 masks): +#if (G93PL != 0) +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_4 (use MINT9 and MG94 masks): +#if (G94PL != 0) +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_5 (use MINT9 and MG95 masks): +#if (G95PL != 0) +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_6 (use MINT9 and MG96 masks): +#if (G96PL != 0) +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_7 (use MINT9 and MG97 masks): +#if (G97PL != 0) +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_8 (use MINT9 and MG98 masks): +#if (G98PL != 0) +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU INT10 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU INT11 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU INT12 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT12 and MG121 masks): +#if (G121PL != 0) +interrupt void XINT3_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_2 (use MINT12 and MG122 masks): +#if (G122PL != 0) +interrupt void XINT4_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER12_3 (use MINT12 and MG123 masks): +#if (G123PL != 0) +interrupt void XINT5_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_4 (use MINT12 and MG124 masks): +#if (G124PL != 0) +interrupt void XINT6_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_5 (use MINT12 and MG125 masks): +#if (G125PL != 0) +interrupt void XINT7_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_7 (use MINT12 and MG127 masks): +#if (G127PL != 0) +interrupt void LVF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_8 (use MINT12 and MG128 masks): +#if (G128PL != 0) +interrupt void LUF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c new file mode 100644 index 0000000..99379ea --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c @@ -0,0 +1,511 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:31 $ +//########################################################################### +// +// FILE: DSP2833x_SWPiroritizedPieVect.c +// +// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// +// Original Source by A.T. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // Reserved space + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + +// Non-Peripheral Interrupts: + #if (INT13PL != 0) + INT13_ISR, // XINT13 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + INT14_ISR, // CPU-Timer2 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOSINT_ISR, // RTOS interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, // reserved interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors: + #if (G11PL != 0) + SEQ1INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G12PL != 0) + SEQ2INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G14PL != 0) + XINT1_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G15PL != 0) + XINT2_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G16PL != 0) + ADCINT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G17PL != 0) + TINT0_ISR, // Timer 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G18PL != 0) + WAKEINT_ISR, // WD & Low Power + #else + INT_NOTUSED_ISR, + #endif + +// Group 2 PIE Vectors: + #if (G21PL != 0) + EPWM1_TZINT_ISR, // ePWM1 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G22PL != 0) + EPWM2_TZINT_ISR, // ePWM2 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G23PL != 0) + EPWM3_TZINT_ISR, // ePWM3 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G24PL != 0) + EPWM4_TZINT_ISR, // ePWM4 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G25PL != 0) + EPWM5_TZINT_ISR, // ePWM5 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G26PL != 0) + EPWM6_TZINT_ISR, // ePWM6 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 3 PIE Vectors: + #if (G31PL != 0) + EPWM1_INT_ISR, // ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G32PL != 0) + EPWM2_INT_ISR, // ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G33PL != 0) + EPWM3_INT_ISR, // ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G34PL != 0) + EPWM4_INT_ISR, // ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G35PL != 0) + EPWM5_INT_ISR, // ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G36PL != 0) + EPWM6_INT_ISR, // ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 4 PIE Vectors: + #if (G41PL != 0) + ECAP1_INT_ISR, // eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G42PL != 0) + ECAP2_INT_ISR, // eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G43PL != 0) + ECAP3_INT_ISR, // eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G44PL != 0) + ECAP4_INT_ISR, // eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G45PL != 0) + ECAP5_INT_ISR, // eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G46PL != 0) + ECAP6_INT_ISR, // eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 5 PIE Vectors: + #if (G51PL != 0) + EQEP1_INT_ISR, // eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G52PL != 0) + EQEP2_INT_ISR, // eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 6 PIE Vectors: + #if (G61PL != 0) + SPIRXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G62PL != 0) + SPITXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G63PL != 0) + MRINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G64PL != 0) + MXINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G65PL != 0) + MRINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G66PL != 0) + MXINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 7 PIE Vectors: + #if (G71PL != 0) + DINTCH1_ISR, // DMA-Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G72PL != 0) + DINTCH2_ISR, // DMA-Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G73PL != 0) + DINTCH3_ISR, // DMA-Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G74PL != 0) + DINTCH4_ISR, // DMA-Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G75PL != 0) + DINTCH5_ISR, // DMA-Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G76PL != 0) + DINTCH6_ISR, // DMA-Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 8 PIE Vectors: + #if (G81PL != 0) + I2CINT1A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G82PL != 0) + I2CINT2A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + #if (G85PL != 0) + SCIRXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + #if (G86PL != 0) + SCITXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 9 PIE Vectors: + #if (G91PL != 0) + SCIRXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G92PL != 0) + SCITXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G93PL != 0) + SCIRXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G94PL != 0) + SCITXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G95PL != 0) + ECAN0INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G96PL != 0) + ECAN1INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G97PL != 0) + ECAN0INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G98PL != 0) + ECAN1INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + +// Group 10 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 11 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 12 PIE Vectors + #if (G121PL != 0) + XINT3_ISR, // External interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G122PL != 0) + XINT4_ISR, // External interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G123PL != 0) + XINT5_ISR, // External interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G124PL != 0) + XINT6_ISR, // External interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G125PL != 0) + XINT7_ISR, // External interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G127PL != 0) + LVF_ISR, // Latched overflow flag + #else + INT_NOTUSED_ISR, + #endif + + #if (G128PL != 0) + LUF_ISR, // Latched underflow flag + #else + INT_NOTUSED_ISR, + #endif +}; + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) { + *Dest++ = *Source++; + } + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Sci.c b/v120/DSP2833x_common/source/DSP2833x_Sci.c new file mode 100644 index 0000000..d0a9e1c --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Sci.c @@ -0,0 +1,168 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 16:06:07 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitSci: +//--------------------------------------------------------------------------- +// This function initializes the SCI(s) to a known state. +// +void InitSci(void) +{ + // Initialize SCI-A: + + //tbd... + + + // Initialize SCI-B: + + //tbd... + + // Initialize SCI-C: + + //tbd... +} + +//--------------------------------------------------------------------------- +// Example: InitSciGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as SCI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SCITXDA/B operation. +// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. +// Comment out other unwanted lines. + +void InitSciGpio() +{ + InitSciaGpio(); +#if DSP28_SCIB + InitScibGpio(); +#endif // if DSP28_SCIB +#if DSP28_SCIC + InitScicGpio(); +#endif // if DSP28_SCIC +} + +void InitSciaGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. + + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) + +/* Configure SCI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation + + EDIS; +} + +#if DSP28_SCIB +void InitScibGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB) + + +// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB) +// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) + +/* Configure SCI-B pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. +// Comment out other unwanted lines. + +// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation + +// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation +// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation + + EDIS; +} +#endif // if DSP28_SCIB + +#if DSP28_SCIC +void InitScicGpio() +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled disabled by the user. +// This will enable the pullups for the specified pins. + + GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) + GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) + +/* Set qualification for selected pins to asynch only */ +// Inputs are synchronized to SYSCLKOUT by default. +// This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) + +/* Configure SCI-C pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SCI functional pins. + + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation + + EDIS; +} +#endif // if DSP28_SCIC + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Spi.c b/v120/DSP2833x_common/source/DSP2833x_Spi.c new file mode 100644 index 0000000..95a7b32 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Spi.c @@ -0,0 +1,107 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:44 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.c +// +// TITLE: DSP2833x SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitSPI: +//--------------------------------------------------------------------------- +// This function initializes the SPI(s) to a known state. +// +void InitSpi(void) +{ + // Initialize SPI-A/B/C/D + + //tbd... + +} + +//--------------------------------------------------------------------------- +// Example: InitSpiGpio: +//--------------------------------------------------------------------------- +// This function initializes GPIO pins to function as SPI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLKA operation. +// Only one GPIO pin should be enabled for SPISTEA operation. +// Comment out other unwanted lines. + +void InitSpiGpio() +{ + + InitSpiaGpio(); +} + +void InitSpiaGpio() +{ + + EALLOW; +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) + + +// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) +// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) +// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) +// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) + +/* Set qualification for selected pins to asynch only */ +// This will select asynch (no qualification) for the selected pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) + + +/* Configure SPI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SPI functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + +// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA +// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA +// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA +// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA + + EDIS; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..f49a3bd --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c @@ -0,0 +1,389 @@ +// TI File $Revision: /main/7 $ +// Checkin $Date: September 20, 2007 13:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. + +#pragma CODE_SECTION(InitFlash, "ramfuncs"); + +//--------------------------------------------------------------------------- +// InitSysCtrl: +//--------------------------------------------------------------------------- +// This function initializes the System Control registers to a known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals + +long SYSCLKOUT, LSPCLK, HSPCLK; + +void InitSysCtrl(void) +{ + + // Disable the watchdog + DisableDog(); + + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // Initialize the peripheral clocks + InitPeripheralClocks(); +} + + +//--------------------------------------------------------------------------- +// Example: InitFlash: +//--------------------------------------------------------------------------- +// This function initializes the Flash Control registers + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results + +void InitFlash(void) +{ + EALLOW; + //Enable Flash Pipeline mode to improve performance + //of code executed from Flash. + FlashRegs.FOPT.bit.ENPIPE = 1; + + // CAUTION + //Minimum waitstates required for the flash operating + //at a given CPU rate must be characterized by TI. + //Refer to the datasheet for the latest information. +#if CPU_FRQ_150MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // CAUTION + //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + asm(" RPT #7 || NOP"); +} + + +//--------------------------------------------------------------------------- +// Example: ServiceDog: +//--------------------------------------------------------------------------- +// This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application + +void ServiceDog(void) +{ + if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR) + if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL) + { + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; + return; +} } + +//--------------------------------------------------------------------------- +// Example: DisableDog: +//--------------------------------------------------------------------------- +// This function disables the watchdog timer. + +void DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: InitPll: +//--------------------------------------------------------------------------- +// This function initializes the PLLCR register. + +void InitPll(Uint16 val, Uint16 divsel) +{ + long Val; + +val = 10; +divsel = 2; + + // Make sure the PLL is not running in limp mode + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + asm(" ESTOP0"); + } + + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // Change the PLLCR +// if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + + EALLOW; + // Before setting PLLCR turn off missing clock detect logic + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + Val = (val)?val:1; + Val = XCLKIN * (Val / 2); + SYSCLKOUT = Val; + + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + + // Wait for the PLL lock bit to be set. + + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + + // Uncomment to disable the watchdog + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // Uncomment to service the watchdog + // ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // If switching to 1/2 + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); +// pause_us(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +//-------------------------------------------------------------------------- +// Example: InitPeripheralClocks: +//--------------------------------------------------------------------------- +// This function initializes the clocks to the peripheral modules. +// First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. +// To reduce power, leave clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral + +void InitPeripheralClocks(void) +{ + long Val; + + EALLOW; + +// HISPCP/LOSPCP prescale register settings, normally it will be set to default values + SysCtrlRegs.HISPCP.all = 0x0003; + SysCtrlRegs.LOSPCP.all = 0x0000; + + Val = (SysCtrlRegs.HISPCP.all)? + SysCtrlRegs.HISPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + + HSPCLK = Val; + + Val = (SysCtrlRegs.LOSPCP.all)? + SysCtrlRegs.LOSPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + LSPCLK = Val; + +// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + // Enable XCLKOUT + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + +// Peripheral clock enables set for the selected peripherals. +// If you are not using a peripheral leave the clock off +// to save on power. +// +// Note: not all peripherals are available on all 2833x derivates. +// Refer to the datasheet for your particular device. +// +// This function is not written to be an example of efficient code. + + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + ADC_cal(); + + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: CsmUnlock: +//--------------------------------------------------------------------------- +// This function unlocks the CSM. User must replace 0xFFFF's with current +// password for the DSP. Returns 1 if unlock is successful. + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 + +Uint16 CsmUnlock() +{ + volatile Uint16 temp; + + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the DSP. + + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // Perform a dummy read of the password locations + // if they match the key values, the CSM will unlock + + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // If the CSM unlocked, return succes, otherwise return + // failure. + if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; + else return STATUS_FAIL; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_Xintf.c b/v120/DSP2833x_common/source/DSP2833x_Xintf.c new file mode 100644 index 0000000..302ca91 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Xintf.c @@ -0,0 +1,242 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: August 16, 2007 11:06:26 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.c +// +// TITLE: DSP2833x Device External Interface Init & Support Functions. +// +// DESCRIPTION: +// +// Example initialization function for the external interface (XINTF). +// This example configures the XINTF to its default state. For an +// example of how this function being used refer to the +// examples/run_from_xintf project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitXINTF: +//--------------------------------------------------------------------------- +// This function initializes the External Interface the default reset state. +// +// Do not modify the timings of the XINTF while running from the XINTF. Doing +// so can yield unpredictable results + + +void InitXintf(void) +{ + // This shows how to write to the XINTF registers. The + // values used here are the default state after reset. + // Different hardware will require a different configuration. + + // For an example of an XINTF configuration used with the + // F28335 eZdsp, refer to the examples/run_from_xintf project. + + // Any changes to XINTF timing should only be made by code + // running outside of the XINTF. + + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // No write buffering + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + + // Zone 0------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING0.bit.XWRLEAD = 3; + XintfRegs.XTIMING0.bit.XWRACTIVE = 7; + XintfRegs.XTIMING0.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 7; + XintfRegs.XTIMING0.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING0.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING0.bit.USEREADY = 1; + XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING0.bit.XSIZE = 3; + + // Zone 6------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING6.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING6.bit.XSIZE = 3; + + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 7; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 1; + XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + + // Bank switching + // Assume Zone 7 is slow, so add additional BCYC cycles + // when ever switching from Zone 7 to another Zone. + // This will help avoid bus contention. + XintfRegs.XBANK.bit.BANK = 7; + XintfRegs.XBANK.bit.BCYC = 7; + EDIS; + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + InitXintf16Gpio(); +// InitXintf32Gpio(); + + asm(" RPT #7 || NOP"); + +} + +void InitXintf32Gpio() +{ + EALLOW; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 + GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 + GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 + GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 + + GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input + + + InitXintf16Gpio(); +} + +void InitXintf16Gpio() +{ + EALLOW; + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 + + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_usDelay.asm b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm new file mode 100644 index 0000000..d3878b4 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm @@ -0,0 +1,76 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + .def _DSP28x_usDelay + .sect ".text" + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c b/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c new file mode 100644 index 0000000..dab0e92 --- /dev/null +++ b/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: Example_2833xAdcToDMA.c +// +// TITLE: DSP2833x ADC To DMA +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect the signals to be converted to channel A0, A1, A2, and A3. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// DESCRIPTION: +// +// ADC is setup to convert 4 channels for each SOC received, with total of 10 SOCs. +// Each SOC initiates 4 conversions. +// DMA is set up to capture the data on each SEQ1_INT. DMA will re-sort +// the data by channel sequentially, i.e. all channel0 data will be together +// all channel1 data will be together. +// +// Code should stop in local_DINTCH1_ISR when complete +// +// Watch Variables: +// DMABuf1 +// +//########################################################################### +// +// Original source by: M.P. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// ADC start parameters +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz +#endif +#if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz +#endif +#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 40 // Sample buffer size + +// Global variable for this example +Uint16 j=0; + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +volatile Uint16 DMABuf1[40]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; +interrupt void local_DINTCH1_ISR(void); + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Specific clock setting for this example: + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Specific ADC setup for this example: + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x2; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x3; + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; // Set up ADC to perform 4 conversions for every SOC + +//Step 5. User specific code, enable interrupts: + // Initialize DMA + DMAInitialize(); + + // Clear Table + for (i=0; i>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)>>4); + +#endif //-- INLINE_SHIFT + +#if NO_SHIFT || POST_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)); + +#endif //-- NO_SHIFT || POST_SHIFT + + while (AdcRegs.ADCST.bit.INT_SEQ1== 0){} + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // Clear GPIO34 for monitoring -optional + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; + +#if INLINE_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)>>4); + +#endif //-- INLINE_SHIFT + +#if NO_SHIFT || POST_SHIFT + + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)); +#endif // -- NO_SHIFT || POST_SHIFT + + } + + +#if POST_SHIFT + // For post shifting, shift the ADC results + // in the SampleTable buffer after the buffer is full. + for (i=0; i>4); + } +#endif // -- POST_SHIFT + + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // Clear GPIO34 for monitoring -optional + } +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel new file mode 100644 index 0000000..4bf2af1 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:35 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC Seq_ovd Test" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSeq_ovdTest.pjt"); + GEL_ProjectBuild("Example_2833xAdcSeq_ovdTest.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSeq_ovdTest.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("SampleTable,x"); + GEL_WatchAdd("AdcRegs,x",); +} + + diff --git a/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt new file mode 100644 index 0000000..414d901 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSeq_ovdTest.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeq_ovdTest.map" -o".\Debug\Example_2833xAdcSeq_ovdTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSeq_ovdTest.out" -x + diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c new file mode 100644 index 0000000..70299a6 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c @@ -0,0 +1,164 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:40:57 $ +//########################################################################### +// +// FILE: Example_2833xAdcSeqModeTest.c +// +// TITLE: DSP2833x ADC Seq Mode Test. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect the signal to be converted to channel A0. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Channel A0 is converted forever and logged in a buffer (SampleTable) +// +// Open a memory window to SampleTable to observe the buffer +// RUN for a while and stop and see the table contents. +// +// Watch Variables: +// SampleTable - Log of converted values. +// +//########################################################################### +// +// Original source by: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// ADC start parameters +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz +#endif +#if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz +#endif +#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 2048 // Sample buffer size + +// Global variable for this example +Uint16 SampleTable[BUF_SIZE]; + +main() +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Specific clock setting for this example: + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Specific ADC setup for this example: + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run + + +// Step 5. User specific code, enable interrupts: + + +// Clear SampleTable + for (i=0; i>4) ); + } + } +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel new file mode 100644 index 0000000..6ea6c86 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:47 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC Seq Test" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSeqModeTest.pjt"); + GEL_ProjectBuild("Example_2833xAdcSeqModeTest.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSeqModeTest.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("SampleTable,x"); + GEL_WatchAdd("AdcRegs,x"); +} diff --git a/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt new file mode 100644 index 0000000..35d0116 --- /dev/null +++ b/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSeqModeTest.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeqModeTest.map" -o".\Debug\Example_2833xAdcSeqModeTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSeqModeTest.out" -x + diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c new file mode 100644 index 0000000..6a53322 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c @@ -0,0 +1,203 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: April 21, 2008 15:41:01 $ +//########################################################################### +// +// FILE: Example_2833xAdc.c +// +// TITLE: DSP2833x ADC Example Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make sure the CPU clock speed is properly defined in +// DSP2833x_Examples.h before compiling this example. +// +// Connect signals to be converted to A2 and A3. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example sets up the PLL in x10/2 mode. +// +// For 150 MHz devices (default) +// divides SYSCLKOUT by six to reach a 25.0Mhz HSPCLK +// (assuming a 30Mhz XCLKIN). +// +// For 100 MHz devices: +// divides SYSCLKOUT by four to reach a 25.0Mhz HSPCLK +// (assuming a 20Mhz XCLKIN). +// +// Interrupts are enabled and the ePWM1 is setup to generate a periodic +// ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2. +// +// Watch Variables: +// +// Voltage1[10] Last 10 ADCRESULT0 values +// Voltage2[10] Last 10 ADCRESULT1 values +// ConversionCount Current result number 0-9 +// LoopCount Idle loop counter +// +// +//########################################################################### +// +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +// Global variables used in this example: +Uint16 LoopCount; +Uint16 ConversionCount; +Uint16 Voltage1[10]; +Uint16 Voltage2[10]; + + +main() +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + + EALLOW; + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + EDIS; + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + +// Step 5. User specific code, enable interrupts: + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + LoopCount = 0; + ConversionCount = 0; + +// Configure ADC + AdcRegs.ADCMAXCONV.all = 0x0001; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // Setup ADCINA3 as 1st SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1 + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start + +// Wait for ADC interrupt + for(;;) + { + LoopCount++; + } + +} + + +interrupt void adc_isr(void) +{ + + Voltage1[ConversionCount] = AdcRegs.ADCRESULT0 >>4; + Voltage2[ConversionCount] = AdcRegs.ADCRESULT1 >>4; + + // If 40 conversions have been logged, start over + if(ConversionCount == 9) + { + ConversionCount = 0; + } + else ConversionCount++; + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + + return; +} + + + diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel new file mode 100644 index 0000000..2d14fe1 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:11:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ADC SOC Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xAdcSoc.pjt"); + GEL_ProjectBuild("Example_2833xAdcSoc.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xAdcSoc.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("Voltage1,x"); + GEL_WatchAdd("Voltage2,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("ConversionCount,d"); + GEL_WatchAdd("AdcRegs,x"); + GEL_WatchAdd("EPwm1Regs,x"); +} diff --git a/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt new file mode 100644 index 0000000..0c46c78 --- /dev/null +++ b/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP28" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" + +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xAdcSoc.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSoc.map" -o".\Debug\Example_2833xAdcSoc.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xAdcSoc.out" -x + diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c new file mode 100644 index 0000000..a4bfaff --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c @@ -0,0 +1,189 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: April 21, 2008 15:41:07 $ +//########################################################################### +// +// FILE: Example_2833xCpuTimer.c +// +// TITLE: DSP2833x Device Getting Started Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures CPU Timer0, 1, and 2 and increments +// a counter each time the timers assert an interrupt. +// +// Watch Variables: +// CpuTimer0.InterruptCount +// CpuTimer1.InterruptCount +// CpuTimer2.InterruptCount +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void cpu_timer0_isr(void); +interrupt void cpu_timer1_isr(void); +interrupt void cpu_timer2_isr(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize the Device Peripheral. This function can be +// found in DSP2833x_CpuTimers.c + InitCpuTimers(); // For this example, only initialize the Cpu Timers + +#if (CPU_FRQ_150MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 150MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); +#endif + +#if (CPU_FRQ_100MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 100MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); +#endif +// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any +// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the +// below settings must also be updated. + + CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + +// Step 5. User specific code, enable interrupts: + + +// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 +// which is connected to CPU-Timer 1, and CPU int 14, which is connected +// to CPU-Timer 2: + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + +// Enable TINT0 in the PIE: Group 1 interrupt 7 + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +interrupt void cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel new file mode 100644 index 0000000..cd7890d --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:12:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x CpuTimerExample" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xCpuTimer.pjt"); + GEL_ProjectBuild("Example_2833xCpuTimer.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xCpuTimer.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer0",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer0Regs,x"); + GEL_WatchAdd("CpuTimer1.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer1",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer1Regs,x"); + GEL_WatchAdd("CpuTimer2.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer2",,"CPU Timer Variables"); + GEL_WatchAdd("CpuTimer2Regs,x"); +} diff --git a/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt new file mode 100644 index 0000000..df3939c --- /dev/null +++ b/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xCpuTimer.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xCpuTimer.map" -o".\Debug\Example_2833xCpuTimer.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c b/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c new file mode 100644 index 0000000..ebee46e --- /dev/null +++ b/v120/DSP2833x_examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c @@ -0,0 +1,189 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: May 12, 2008 14:23:19 $ +//########################################################################### +// +// FILE: Example_2833xDMA_Ram_to_Ram.c +// +// TITLE: DSP2833x DMA Ram to Ram +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// DESCRIPTION: +// +// Code will perform a block copy from L5 SARAM to L4 SARAM of 1024 words. Transfer will be started +// by Timer0. Will use 32-bit datasize to decrease the transfer time. +// Code will end in local_DINTCH1_ISR once the transfer is complete +// +// Watch Variables: +// DMABuf1 +// DMABuf2 +// +//########################################################################### +// +// Original source by: M.P. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +#define BUF_SIZE 1024 // Sample buffer size + + + + +// DMA Defines +#define CH1_TOTAL DATA_POINTS_PER_CHANNEL +#define CH1_WORDS_PER_BURST ADC_CHANNELS_TO_CONVERT + + + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +#pragma DATA_SECTION(DMABuf2,"DMARAML5"); + +volatile Uint16 DMABuf1[1024]; +volatile Uint16 DMABuf2[1024]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; + +interrupt void local_DINTCH1_ISR(void); + + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + +// Step 2. Initialize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + CpuTimer0Regs.TCR.bit.TSS = 1; //Stop Timer0 for now + + +//Step 5. User specific code, enable interrupts: + // Initialize DMA + DMAInitialize(); + + // Initialize Tables + for (i=0; iMDL.all; // = 0x9555AAAn (n is the MBX number) + TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant) + TestMbox3 = Mailbox->MSGID.all;// = 0x9555AAAn (n is the MBX number) + +} // MSGID of a rcv MBX is transmitted as the MDL data. + + +void mailbox_check(int32 T1, int32 T2, int32 T3) +{ + if((T1 != T3) || ( T2 != 0x89ABCDEF)) + { + ErrorCount++; + } + else + { + PassCount++; + } +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel new file mode 100644 index 0000000..90f787e --- /dev/null +++ b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:12:48 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ECanBack2Back" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECanBack2Back.pjt"); + GEL_ProjectBuild("Example_2833xECanBack2Back.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECanBack2Back.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("MessageReceivedCount,x"); + GEL_WatchAdd("ErrorCount,x"); + GEL_WatchAdd("PassCount,x"); + GEL_WatchAdd("ECanaRegs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt new file mode 100644 index 0000000..cbe5cf6 --- /dev/null +++ b/v120/DSP2833x_examples/ecan_back2back/Example_2833xECanBack2Back.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECan.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECanBack2Back.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecan_back2back\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECanBack2Back.map" -o".\Debug\Example_2833xECanBack2Back.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xECanBack2Back.out" -x + diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c new file mode 100644 index 0000000..1d1693a --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.c @@ -0,0 +1,223 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:41:24 $ +//########################################################################### +// +// FILE: Example_2833xECap_apwm.c +// +// TITLE: DSP2833x ECAP APWM Example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor eCAP1 - eCAP4 pins on a oscilloscope as +// described below. +// +// eCAP1 on GPIO24 +// eCAP2 on GPIO7 +// eCAP3 on GPIO9 +// eCAP4 on GPIO11 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program sets up the eCAP pins in the APWM mode. +// This program runs at 150 MHz SYSCLKOUT assuming a 30 MHz +// XCLKIN or 100 MHz SYSCLKOUT assuming a 20 MHz XCLKIN. +// +// For 150 MHz devices: +// +// eCAP1 will come out on the GPIO24 pin +// This pin is configured to vary between 7.5 Hz and 15 Hz using +// the shadow registers to load the next period/compare values +// +// eCAP2 will come out on the GPIO7 pin +// this pin is configured as a 7.5 Hz output +// +// eCAP3 will come out on the GPIO9 pin +// this pin is configured as a 1.5 Hz output +// +// +// eCAP4 will come out on the GPIO11 pin +// this pin is configured as a 30 kHz output +// +// All frequencies assume a 30 Mhz input clock. The XCLKOUT pin +// should show 150Mhz. +// -------------------------------------------------------------- +// For 100 MHz devices: +// +// eCAP1 will come out on the GPIO24 pin +// This pin is configured to vary between 5 Hz and 10 Hz using +// the shadow registers to load the next period/compare values +// +// eCAP2 will come out on the GPIO7 pin +// this pin is configured as a 5 Hz output +// +// eCAP3 will come out on the GPIO9 pin +// this pin is configured as a 1 Hz output +// +// eCAP4 will come out on the GPIO11 pin +// this pin is configured as a 20kHz output +// +// All frequencies assume a 20 Mhz input clock. The XCLKOUT pin +// should show 100Mhz. +// +// +// Watch Variables: +// +// +// +//########################################################################### +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Global variables +Uint16 direction = 0; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Initialize the GPIO pins for eCAP. +// This function is found in the DSP2833x_ECap.c file + InitECapGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. +// No interrupts used for this example. + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code + + + // Setup APWM mode on CAP1, set period and compare registers + ECap1Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap1Regs.CAP1 = 0x01312D00; // Set Period value + ECap1Regs.CAP2 = 0x00989680; // Set Compare value + ECap1Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP2, set period and compare registers + ECap2Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap2Regs.CAP1 = 0x01312D00; // Set Period value + ECap2Regs.CAP2 = 0x00989680; // Set Compare value + ECap2Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP3, set period and compare registers + ECap3Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap3Regs.CAP1 = 0x05F5E100; // Set Period value + ECap3Regs.CAP2 = 0x02FAF080; // Set Compare value + ECap3Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Setup APWM mode on CAP4, set period and compare registers + ECap4Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap4Regs.CAP1 = 0x00001388; // Set Period value + ECap4Regs.CAP2 = 0x000009C4; // Set Compare value + ECap4Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // Start counters + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap4Regs.ECCTL2.bit.TSCTRSTOP = 1; + + for(;;) + { + // set next duty cycle to 50% + ECap1Regs.CAP4 = ECap1Regs.CAP1 >> 1; + + // vary freq between 7.5 Hz and 15 Hz (for 150MHz SYSCLKOUT) 5 Hz and 10 Hz (for 100 MHz SYSCLKOUT) + if(ECap1Regs.CAP1 >= 0x01312D00) + { + direction = 0; + } else if (ECap1Regs.CAP1 <= 0x00989680) + { + direction = 1; + } + + if(direction == 0) + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 - 500000; + } else + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 + 500000; + } + } + +} + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel new file mode 100644 index 0000000..15cb906 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:02 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eCAP Asym PWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECap_apwm.pjt"); + GEL_ProjectBuild("Example_2833xECap_apwm.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECap_apwm.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("ECap1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt new file mode 100644 index 0000000..d982655 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_apwm/Example_2833xECap_apwm.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECap.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECap_apwm.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_apwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECap_apwm.map" -o".\Debug\Example_2833xECap_apwm.out" -stack0x380 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xECap_apwm.out" -x + diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c new file mode 100644 index 0000000..22ecde8 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c @@ -0,0 +1,288 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:29 $ +//########################################################################### +// +// FILE: Example_2833xECap_Capture_Pwm.c +// +// TITLE: Capture EPWM3. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Make the following external connection: +// EPWM3 on GPIO4 should be connected to ECAP1 on GPIO24. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM3A for: +// - Up count +// - Period starts at 2 and goes up to 1000 +// - Toggle output on PRD +// +// eCAP1 is configured to capture the time between rising +// and falling edge of the PWM3A output. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +// Configure the start/end period for the timer +#define PWM3_TIMER_MIN 10 +#define PWM3_TIMER_MAX 8000 + +// Prototype statements for functions found within this file. +interrupt void ecap1_isr(void); +void InitECapture(void); +void InitEPwmTimer(void); +void Fail(void); + +// Global variables used in this example +Uint32 ECap1IntCount; +Uint32 ECap1PassCount; +Uint32 EPwm3TimerDirection; + +// To keep track of which way the timer value is moving +#define EPWM_TIMER_UP 1 +#define EPWM_TIMER_DOWN 0 + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + InitEPwm3Gpio(); + InitECap1Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.ECAP1_INT = &ecap1_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + InitECapture(); + + +// Step 5. User specific code, enable interrupts: + +// Initalize counters: + ECap1IntCount = 0; + ECap1PassCount = 0; + +// Enable CPU INT4 which is connected to ECAP1-4 INT: + IER |= M_INT4; + +// Enable eCAP INTn in the PIE: Group 3 interrupt 1-6 + PieCtrlRegs.PIEIER4.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = PWM3_TIMER_MIN; + EPwm3Regs.TBPHS.all = 0x00000000; + EPwm3Regs.AQCTLA.bit.PRD = AQ_TOGGLE; // Toggle on PRD + + // TBCLK = SYSCLKOUT + EPwm3Regs.TBCTL.bit.HSPCLKDIV = 1; + EPwm3Regs.TBCTL.bit.CLKDIV = 0; + + + EPwm3TimerDirection = EPWM_TIMER_UP; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +} + +void InitECapture() +{ + ECap1Regs.ECEINT.all = 0x0000; // Disable all capture interrupts + ECap1Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags + ECap1Regs.ECCTL1.bit.CAPLDEN = 0; // Disable CAP1-CAP4 register loads + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 0; // Make sure the counter is stopped + + // Configure peripheral registers + ECap1Regs.ECCTL2.bit.CONT_ONESHT = 1; // One-shot + ECap1Regs.ECCTL2.bit.STOP_WRAP = 3; // Stop at 4 events + ECap1Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP2POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CAP3POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP4POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CTRRST1 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation + ECap1Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable sync in + ECap1Regs.ECCTL2.bit.SYNCO_SEL = 0; // Pass through + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units + + + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter + ECap1Regs.ECCTL2.bit.REARM = 1; // arm one-shot + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable CAP1-CAP4 register loads + ECap1Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt + +} + + + +interrupt void ecap1_isr(void) +{ + + // Cap input is syc'ed to SYSCLKOUT so there may be + // a +/- 1 cycle variation + + if(ECap1Regs.CAP2 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP2 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP3 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP3 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP4 > EPwm3Regs.TBPRD*2+1 || ECap1Regs.CAP4 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + + ECap1IntCount++; + + if(EPwm3TimerDirection == EPWM_TIMER_UP) + { + if(EPwm3Regs.TBPRD < PWM3_TIMER_MAX) + { + EPwm3Regs.TBPRD++; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_DOWN; + EPwm3Regs.TBPRD--; + } + } + else + { + if(EPwm3Regs.TBPRD > PWM3_TIMER_MIN) + { + EPwm3Regs.TBPRD--; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_UP; + EPwm3Regs.TBPRD++; + } + } + + ECap1PassCount++; + + ECap1Regs.ECCLR.bit.CEVT4 = 1; + ECap1Regs.ECCLR.bit.INT = 1; + ECap1Regs.ECCTL2.bit.REARM = 1; + + // Acknowledge this interrupt to receive more interrupts from group 4 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; +} + + +void Fail() +{ + asm(" ESTOP0"); +} + + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel new file mode 100644 index 0000000..aefa65b --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.gel @@ -0,0 +1,46 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eCAP Capture PWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xECap_Capture_Pwm.pjt"); + GEL_ProjectBuild("Example_2833xECap_Capture_Pwm.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xECap_Capture_Pwm.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("ECap1IntCount,x"); + GEL_WatchAdd("ECap1PassCount,x"); + GEL_WatchAdd("EPwm3Regs.TBPRD,x"); + GEL_WatchAdd("ECap1Regs.CAP2,x"); + GEL_WatchAdd("ECap1Regs.CAP3,x"); + GEL_WatchAdd("ECap1Regs.CAP4,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("ECap1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt new file mode 100644 index 0000000..cae4269 --- /dev/null +++ b/v120/DSP2833x_examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.pjt @@ -0,0 +1,47 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ECap.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xECap_Capture_Pwm.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\ecap_capture_pwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xECap_Capture_Pwm.map" -o".\Debug\Example_2833xECap_Capture_Pwm.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c new file mode 100644 index 0000000..8e91544 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.c @@ -0,0 +1,457 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:33 $ +//########################################################################### +// +// FILE: Example_2833xEpwmDeadBand.c +// +// TITLE: Check PWM deadband generation +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1 - ePWM3 on an Oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2 and ePWM3 for: +// - Count up/down +// - Deadband +// +// 3 Examples are included: +// * ePWM1: Active low PWMs +// * ePWM2: Active low complementary PWMs +// * ePWM3: Active high complementary PWMs +// +// Each ePWM is configured to interrupt on the 3rd zero event +// when this happens the deadband is modified such that +// 0 <= DB <= DB_MAX. That is, the deadband will move up and +// down between 0 and the maximum value. +// +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint16 EPwm1_DB_Direction; +Uint16 EPwm2_DB_Direction; +Uint16 EPwm3_DB_Direction; + +// Maximum Dead Band values +#define EPWM1_MAX_DB 0x03FF +#define EPWM2_MAX_DB 0x03FF +#define EPWM3_MAX_DB 0x03FF + +#define EPWM1_MIN_DB 0 +#define EPWM2_MIN_DB 0 +#define EPWM3_MIN_DB 0 + +// To keep track of which way the Dead Band is moving +#define DB_UP 1 +#define DB_DOWN 0 + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_isr(void) +{ + if(EPwm1_DB_Direction == DB_UP) + { + if(EPwm1Regs.DBFED < EPWM1_MAX_DB) + { + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1_DB_Direction = DB_DOWN; + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + else + { + if(EPwm1Regs.DBFED == EPWM1_MIN_DB) + { + EPwm1_DB_Direction = DB_UP; + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + +interrupt void epwm2_isr(void) +{ + + if(EPwm2_DB_Direction == DB_UP) + { + if(EPwm2Regs.DBFED < EPWM2_MAX_DB) + { + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2_DB_Direction = DB_DOWN; + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + else + { + if(EPwm2Regs.DBFED == EPWM2_MIN_DB) + { + EPwm2_DB_Direction = DB_UP; + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + + EPwm2TimerIntCount++; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + +interrupt void epwm3_isr(void) +{ + if(EPwm3_DB_Direction == DB_UP) + { + if(EPwm3Regs.DBFED < EPWM3_MAX_DB) + { + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3_DB_Direction = DB_DOWN; + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + else + { + if(EPwm3Regs.DBFED == EPWM3_MIN_DB) + { + EPwm3_DB_Direction = DB_UP; + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + + + EPwm3TimerIntCount++; + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + +} + + + +void InitEPwm1Example() +{ + + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Setup compare + EPwm1Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active Low PWMs - Setup Deadband + EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO; + EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm1Regs.DBRED = EPWM1_MIN_DB; + EPwm1Regs.DBFED = EPWM1_MIN_DB; + EPwm1_DB_Direction = DB_UP; + + // Interrupt where we will change the Deadband + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + +} + + +void InitEPwm2Example() +{ + + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope + + // Setup compare + EPwm2Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active Low complementary PWMs - setup the deadband + EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; + EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm2Regs.DBRED = EPWM2_MIN_DB; + EPwm2Regs.DBFED = EPWM2_MIN_DB; + EPwm2_DB_Direction = DB_UP; + + // Interrupt where we will modify the deadband + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + +} + +void InitEPwm3Example() +{ + + EPwm3Regs.TBPRD = 6000; // Set timer period + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow so we can observe on the scope + + // Setup compare + EPwm3Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero + EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero + EPwm3Regs.AQCTLB.bit.CAD = AQ_SET; + + // Active high complementary PWMs - Setup the deadband + EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; + EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm3Regs.DBRED = EPWM3_MIN_DB; + EPwm3Regs.DBFED = EPWM3_MIN_DB; + EPwm3_DB_Direction = DB_UP; + + // Interrupt where we will change the deadband + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt new file mode 100644 index 0000000..08ffef5 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadBand.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmDeadBand.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_deadband\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmDeadBand.map" -o".\Debug\Example_2833xEPwmDeadBand.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwmDeadBand.map" -o".\Release\Example_2833xEPwmDeadBand.out" -x + diff --git a/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel new file mode 100644 index 0000000..4466bd1 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_deadband/Example_2833xEPwmDeadband.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:25 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM Deadband" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmDeadBand.pjt"); + GEL_ProjectBuild("Example_2833xEPwmDeadBand.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmDeadBand.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd new file mode 100644 index 0000000..2a2abf8 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:23:49 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ + +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd new file mode 100644 index 0000000..c107ade --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_nonBIOS.cmd @@ -0,0 +1,182 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:23:45 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ + +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 +} + + + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c new file mode 100644 index 0000000..9645539 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.c @@ -0,0 +1,455 @@ +//########################################################################### +// +// FILE: Example_2833xEPwm_DMA.c +// +// TITLE: DSP2833x Device DMA interface with ePWM example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example demonstrates several cases where the DMA is triggered from +// SOC signals generated by ePWM modules. +// +// DMA CH1 setup: +// Trigger = ADCSOCA from ePWM1 +// Datasize = 16 bits +// Source = VarA +// Dest = EPwm1Regs.TBPRD +// Burst = One word / burst +// Transfer = One burst / transfer +// CPU int = every transfer +// +// DMA CH2 setup: +// Trigger = ADCSOCB from ePWM2 +// Datasize = 32 bits +// Source = VarB +// Dest = EPwm1Regs.CMPA.all +// Burst = One 32-bit word / burst +// Transfer = One burst / transfer +// CPU int = none +// +// DMA CH3 setup: +// Trigger = ADC SEQ1INT +// Datasize = 32 bits +// Source = AdcMirror.ADCRESULT[0-5] +// Dest = ADCbuffer +// Burst = Three 32-bit words / burst +// Transfer = One burst / transfer +// CPU int = none +// +// Watch Variables: +// +// EPwm1Regs.TBPRD +// EPwm1Regs.CMPA.all +// ADCbuffer +// InterruptCount +// +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +// Prototype statements for functions found within this file. +void delay_loop(void); +void DMAInitialize(void); +void DMACH1Config(void); +void DMACH2Config(void); +void DMACH3Config(void); +void ConfigAdc(void); +void config_ePWM1_to_generate_ADCSOCA(void); +void config_ePWM2_to_generate_ADCSOCB(void); +interrupt void local_DINTCH1_ISR(void); + + +// Global Variables +#pragma DATA_SECTION(ADCbuffer,"DMARAML4"); +volatile Uint32 ADCbuffer[3]; + +Uint16 VarA; +Uint32 VarB; + +volatile Uint16 *MAPCNF = (Uint16 *)0x00702E; + +Uint16 InterruptCount; + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this example use the following configuration: + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + EALLOW; + // Initialize PIE vector for CPU interrupt: + PieVectTable.DINTCH1 = &local_DINTCH1_ISR; // Point to DMA CH1 ISR + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + + InterruptCount = 0; + + EALLOW; + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + SysCtrlRegs.MAPCNF.bit.MAPEPWM = 1; // Remap ePWMs for DMA access + EDIS; + + GpioDataRegs.GPASET.all = 0xFFFFFFFF; + delay_loop(); + GpioDataRegs.GPACLEAR.all = 0x00000002; + + for(i=0; i<3; i++) + { + ADCbuffer[i] = ((Uint32)i*0x00011000) + 0x00044000; + } + + VarA = 75; + VarB = 0x652000; + + // Enable and configure clocks to peripherals: + EALLOW; + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // Enable SYSCLK to DMA + EDIS; + + DMAInitialize(); + DMACH1Config(); + DMACH2Config(); + DMACH3Config(); + + // Enable all interrupts: + IER = M_INT7; // Enable INT7 (7.1 DMA Ch1) + EINT; + + InitAdc(); + ConfigAdc(); + + config_ePWM1_to_generate_ADCSOCA(); + config_ePWM2_to_generate_ADCSOCB(); + + + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + asm(" NOP"); + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EDIS; + + for(;;) {} + +} + + +//=========================================================================== +// DMA Functions +//=========================================================================== + +void DMAInitialize(void) +{ + EALLOW; + + // Perform a hard reset on DMA + DmaRegs.DMACTRL.bit.HARDRESET = 1; + + // always perform one NOP after a HARDRESET + asm(" NOP"); + + // Stop DMA on emulation suspend + DmaRegs.DEBUGCTRL.bit.FREE = 0; + + EDIS; +} + + +void DMACH1Config(void) +{ + EALLOW; + // Configure CH1: + // + // Reset selected channel via CONTROL Register: +// DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters) + + // Set up MODE Register: + DmaRegs.CH1.MODE.bit.PERINTSEL = 18; // ePWM1 SOCA as peripheral interrupt source + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers + DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // Generate interrupt to CPU at the beg of transfer + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enabled + + // Set up BURST registers: + DmaRegs.CH1.BURST_SIZE.all = 0; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH1.SRC_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + DmaRegs.CH1.DST_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + + // Set up TRANSFER registers: + DmaRegs.CH1.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH1.SRC_WRAP_STEP = 0; + DmaRegs.CH1.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &VarA; // Point to variable in RAM + + // Set up DESTINATION address: + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.TBPRD; // Point to ePWM1 TBPRD register remapped for DMA + // need to make sure .cmd file has ePWMs remapped + // Clear any spurious flags: + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + +void DMACH2Config(void) +{ + EALLOW; + // Configure CH2: + // + // Reset selected channel via CONTROL Register: +// DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters) + + // Set up MODE Register: + DmaRegs.CH2.MODE.bit.PERINTSEL = 21; // ePWM2 SOCB as peripheral interrupt source + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH2.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH2.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH2.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH2.MODE.bit.CHINTMODE = 0; + DmaRegs.CH2.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // Set up BURST registers: + DmaRegs.CH2.BURST_SIZE.all = 1; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH2.SRC_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst + DmaRegs.CH2.DST_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst + + // Set up TRANSFER registers: + DmaRegs.CH2.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH2.SRC_WRAP_STEP = 0; + DmaRegs.CH2.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &VarB; // Point to variable in RAM + + // Set up DESTINATION address: + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.CMPA.all; // Point to ePWM1 CMPAHR/CMPA registers + + // Clear any spurious flags: + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + +void DMACH3Config(void) +{ + EALLOW; + // Configure CH3: + // + + // Set up MODE Register: + DmaRegs.CH3.MODE.bit.PERINTSEL = 1; // ADC SEQ1INT as peripheral interrupt source + DmaRegs.CH3.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH3.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH3.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH3.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH3.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH3.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH3.MODE.bit.CHINTMODE = 0; + DmaRegs.CH3.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // Set up BURST registers: + DmaRegs.CH3.BURST_SIZE.all = 5; // Number (N-1) of 16-bit words transferred in a burst + DmaRegs.CH3.SRC_BURST_STEP = 2; // Increment source burst address by 2 (32-bit) + DmaRegs.CH3.DST_BURST_STEP = 2; // Increment destination burst address by 2 (32-bit) + + // Set up TRANSFER registers: + DmaRegs.CH3.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH3.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH3.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // Set up WRAP registers: + DmaRegs.CH3.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH3.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH3.SRC_WRAP_STEP = 0; + DmaRegs.CH3.DST_WRAP_STEP = 0; + + // Set up SOURCE address: + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32) &AdcMirror.ADCRESULT0; // Point to first RESULT reg + + // Set up DESTINATION address: + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32) &ADCbuffer[0]; // Point to beginning of ADCbuffer + + // Clear any spurious flags: + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + EDIS; +} + + + +interrupt void local_DINTCH1_ISR(void) // DMA INT7.1 +{ + GpioDataRegs.GPATOGGLE.all = 0x00000001; // Toggle GPIOA0 + + InterruptCount++; + + + if((DmaRegs.CH1.CONTROL.bit.OVRFLG == 1) || (DmaRegs.CH2.CONTROL.bit.OVRFLG == 1) || + (DmaRegs.CH3.CONTROL.bit.OVRFLG == 1)) + { + asm(" ESTOP0"); + } + + PieCtrlRegs.PIEACK.bit.ACK7 = 1; // Clear PIEIFR bit +} + + +void ConfigAdc(void) +{ + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 7; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // ADCINA0 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // ADCINA1 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // ADCINA2 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // ADCINA3 + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4; // ADCINA4 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5; // ADCINA5 + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable ADC to accept ePWM_SOCA trigger + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear interrupt flag + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt +} + + +void config_ePWM1_to_generate_ADCSOCA(void) +{ + // Configure ePWM1 Timer + // Interrupt triggers ADCSOCA + + EALLOW; + EPwm1Regs.TBPRD = 74; // Setup period (one off so DMA transfer will be obvious) + EPwm1Regs.CMPA.all = 0x501000; + EPwm1Regs.ETSEL.bit.SOCASEL = 2; // ADCSOCA on TBCTR=TBPRD + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate SOCA on 1st event + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA generation + EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + + +void config_ePWM2_to_generate_ADCSOCB(void) +{ + // Configure ePWM2 Timer + // Interrupt triggers ADCSOCB + + EALLOW; + EPwm2Regs.TBPRD = 150; // Setup periodSetup period + EPwm2Regs.CMPA.all = 0x200000; + EPwm2Regs.ETSEL.bit.SOCBSEL = 2; // ADCSOCB on TBCTR=TBPRD + EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate SOCB on 1st event + EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB generation + EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + + +void delay_loop() +{ + short i; + for (i = 0; i < 1000; i++) {} +} + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel new file mode 100644 index 0000000..f5ab59c --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel @@ -0,0 +1,43 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: June 19, 2008 10:25:20 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM DMA" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwm_DMA.pjt"); + GEL_ProjectBuild("Example_2833xEPwm_DMA.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwm_DMA.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs.TBPRD,x"); + GEL_WatchAdd("EPwm1Regs.CMPA.all,x"); + GEL_WatchAdd("ADCbuffer,x"); + GEL_WatchAdd("InterruptCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt new file mode 100644 index 0000000..69ca432 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwm_DMA.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="DSP2833x_EPWMDM_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwm_DMA.map" -o".\Debug\Example_2833xEPwm_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwm_DMA.map" -o".\Release\Example_2833xEPwm_DMA.out" -x + diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c new file mode 100644 index 0000000..58927b6 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c @@ -0,0 +1,360 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:38 $ +//########################################################################### +// +// FILE: Example_2833xEPwmTimerInt.c +// +// TITLE: DSP2833x ePWM Timer Interrupt example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures the ePWM Timers and increments +// a counter each time an interrupt is taken. +// +// As supplied: +// +// All ePWM's are initalized. Note that not all devices in the 2833x +// family have all 6 ePWMs. +// +// All timers have the same period +// The timers are started sync'ed +// An interrupt is taken on a zero event for each ePWM timer +// +// ePWM1: takes an interrupt every event +// ePWM2: takes an interrupt every 2nd event +// ePWM3: takes an interrupt every 3rd event +// ePWM4-ePWM6: take an interrupt every event +// +// Thus the Interrupt count for ePWM1, ePWM4-ePWM6 should be equal +// The interrupt count for ePWM2 should be about half that of ePWM1 +// and the interrupt count for ePWM3 should be about 1/3 that of ePWM1 +// +// Watch Variables: +// EPwm1TimerIntCount +// EPwm2TimerIntCount +// EPwm3TimerIntCount +// EPwm4TimerIntCount +// EPwm5TimerIntCount +// EPwm6TimerIntCount +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Configure which ePWM timer interrupts are enabled at the PIE level: +// 1 = enabled, 0 = disabled +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 +#define PWM4_INT_ENABLE 1 +#define PWM5_INT_ENABLE 1 +#define PWM6_INT_ENABLE 1 + +// Configure the period for each timer +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF +#define PWM4_TIMER_TBPRD 0x1FFF +#define PWM5_TIMER_TBPRD 0x1FFF +#define PWM6_TIMER_TBPRD 0x1FFF + + +// Prototype statements for functions found within this file. +interrupt void epwm1_timer_isr(void); +interrupt void epwm2_timer_isr(void); +interrupt void epwm3_timer_isr(void); +interrupt void epwm4_timer_isr(void); +interrupt void epwm5_timer_isr(void); +interrupt void epwm6_timer_isr(void); +void InitEPwmTimer(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 EPwm4TimerIntCount; +Uint32 EPwm5TimerIntCount; +Uint32 EPwm6TimerIntCount; + + +void main(void) +{ + int i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + PieVectTable.EPWM4_INT = &epwm4_timer_isr; + PieVectTable.EPWM5_INT = &epwm5_timer_isr; + PieVectTable.EPWM6_INT = &epwm6_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + +// Step 5. User specific code, enable interrupts: + +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + EPwm4TimerIntCount = 0; + EPwm5TimerIntCount = 0; + EPwm6TimerIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-6 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-6 + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx4 = PWM4_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx5 = PWM5_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx6 = PWM6_INT_ENABLE; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + for(i=1;i<=10;i++) + {} + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // Setup Sync + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // Allow each timer to be sync'ed + + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + EPwm4Regs.TBPHS.half.TBPHS = 400; + EPwm5Regs.TBPHS.half.TBPHS = 500; + EPwm6Regs.TBPHS.half.TBPHS = 600; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EPwm4Regs.TBPRD = PWM4_TIMER_TBPRD; + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm4Regs.ETSEL.bit.INTEN = PWM4_INT_ENABLE; // Enable INT + EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm5Regs.TBPRD = PWM5_TIMER_TBPRD; + EPwm5Regs.TBCTL.bit.CTRMODE= TB_COUNT_UP; // Count up + EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm5Regs.ETSEL.bit.INTEN = PWM5_INT_ENABLE; // Enable INT + EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm6Regs.TBPRD = PWM6_TIMER_TBPRD; + EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm6Regs.ETSEL.bit.INTEN = PWM6_INT_ENABLE; // Enable INT + EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; + + +} + + +// Interrupt routines uses in this example: +interrupt void epwm1_timer_isr(void) +{ + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_timer_isr(void) +{ + EPwm3TimerIntCount++; + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm4_timer_isr(void) +{ + EPwm4TimerIntCount++; + + // Clear INT flag for this timer + EPwm4Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm5_timer_isr(void) +{ + EPwm5TimerIntCount++; + + // Clear INT flag for this timer + EPwm5Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm6_timer_isr(void) +{ + EPwm6TimerIntCount++; + + // Clear INT flag for this timer + EPwm6Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel new file mode 100644 index 0000000..43d8f17 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.gel @@ -0,0 +1,47 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:37 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM Interrupt Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmTimerInt.pjt"); + GEL_ProjectBuild("Example_2833xEPwmTimerInt.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmTimerInt.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount",,"PWM1 ISR Count"); + GEL_WatchAdd("EPwm2TimerIntCount",,"PWM2 ISR Count"); + GEL_WatchAdd("EPwm3TimerIntCount",,"PWM3 ISR Count"); + GEL_WatchAdd("EPwm4TimerIntCount",,"PWM4 ISR Count"); + GEL_WatchAdd("EPwm5TimerIntCount",,"PWM5 ISR Count"); + GEL_WatchAdd("EPwm6TimerIntCount",,"PWM6 ISR Count"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + GEL_WatchAdd("EPwm5Regs,x"); + GEL_WatchAdd("EPwm6Regs,x"); +} diff --git a/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt new file mode 100644 index 0000000..6e0819d --- /dev/null +++ b/v120/DSP2833x_examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmTimerInt.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_timer_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmTimerInt.map" -o".\Debug\Example_2833xEPwmTimerInt.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x + diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c new file mode 100644 index 0000000..1415e49 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.c @@ -0,0 +1,305 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:42 $ +//########################################################################### +// +// FILE: Example_2833xEpwmTripZone.c +// +// TITLE: Check PWM Trip Zone Test +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Initially tie TZ1 (GPIO12) and TZ2 (GPIO13) high. +// +// During the test, monitor ePWM1 or ePWM2 outputs +// on a scope Pull TZ1 or TZ2 low to see the effect. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// ePWM1 will react as a 1 shot trip +// +// ePWM2 will react as a cycle by cycle trip and will be +// cleared if TZ1 and TZ2 are both pulled back high. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1 and ePWM2 +// +// 2 Examples are included: +// * ePWM1 has TZ1 and TZ2 as one shot trip sources +// * ePWM2 has TZ1 and TZ2 as cycle by cycle trip sources +// +// Each ePWM is configured to interrupt on the 3rd zero event +// when this happens the deadband is modified such that +// 0 <= DB <= DB_MAX. That is, the deadband will move up and +// down between 0 and the maximum value. +// +// +// View the EPWM1A/B, EPWM2A/B waveforms +// via an oscilloscope to see the effect of TZ1 and TZ2 +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +interrupt void epwm1_tzint_isr(void); +interrupt void epwm2_tzint_isr(void); + + +// Global variables used in this example +Uint32 EPwm1TZIntCount; +Uint32 EPwm2TZIntCount; + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, and TZ pins + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitTzGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_TZINT = &epwm1_tzint_isr; + PieVectTable.EPWM2_TZINT = &epwm2_tzint_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts +// Initalize counters: + EPwm1TZIntCount = 0; + EPwm2TZIntCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT2; + +// Enable EPWM INTn in the PIE: Group 2 interrupt 1-3 + PieCtrlRegs.PIEIER2.bit.INTx1 = 1; + PieCtrlRegs.PIEIER2.bit.INTx2 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_tzint_isr(void) +{ + EPwm1TZIntCount++; + +// Leave these flags set so we only take this +// interrupt once +// +// EALLOW; +// EPwm1Regs.TZCLR.bit.OST = 1; +// EPwm1Regs.TZCLR.bit.INT = 1; +// EDIS; + + // Acknowledge this interrupt to receive more interrupts from group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + +} + +interrupt void epwm2_tzint_isr(void) +{ + + EPwm2TZIntCount++; + +// Clear the flags - we will continue to take +// this interrupt until the TZ pin goes high +// + EALLOW; + EPwm2Regs.TZCLR.bit.CBC = 1; + EPwm2Regs.TZCLR.bit.INT = 1; + EDIS; + + // Acknowledge this interrupt to receive more interrupts from group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + +} + + +void InitEPwm1Example() +{ + // Enable TZ1 and TZ2 as one shot trip sources + EALLOW; + EPwm1Regs.TZSEL.bit.OSHT1 = 1; + EPwm1Regs.TZSEL.bit.OSHT2 = 1; + + // What do we want the TZ1 and TZ2 to do? + EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // Enable TZ interrupt + EPwm1Regs.TZEINT.bit.OST = 1; + EDIS; + + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Setup compare + EPwm1Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; + +} + + +void InitEPwm2Example() +{ + + // Enable TZ1 and TZ2 as one cycle-by-cycle trip sources + EALLOW; + EPwm2Regs.TZSEL.bit.CBC1 = 1; + EPwm2Regs.TZSEL.bit.CBC2 = 1; + + // What do we want the TZ1 and TZ2 to do? + EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // Enable TZ interrupt + EPwm2Regs.TZEINT.bit.CBC = 1; + EDIS; + + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope + + // Setup compare + EPwm2Regs.CMPA.half.CMPA = 3000; + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel new file mode 100644 index 0000000..a59442b --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:13:58 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM TripZone" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmTripZone.pjt"); + GEL_ProjectBuild("Example_2833xEPwmTripZone.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmTripZone.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt new file mode 100644 index 0000000..543de56 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_trip_zone/Example_2833xEPwmTripZone.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmTripZone.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_trip_zone\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmTripZone.map" -o".\Debug\Example_2833xEPwmTripZone.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -m".\Release\Example_2833xEPwmDeadBand.map" -o".\Release\Example_2833xEPwmTripZone.out" -x + diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c new file mode 100644 index 0000000..33b153a --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.c @@ -0,0 +1,490 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:41:47 $ +//########################################################################### +// +// FILE: Example_2833xEPwm3UpAQ.c +// +// TITLE: Action Qualifier Module Upcount mode. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor the ePWM1 - ePWM3 pins on a oscilloscope as +// described below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2, ePWM3 to produce an +// waveform with independant modulation on EPWMxA and +// EPWMxB. +// +// The compare values CMPA and CMPB are modified within the ePWM's ISR +// +// The TB counter is in upmode for this example. +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + + +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +}EPWM_INFO; + + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// Global variables used in this example +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// Configure the period for each timer +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + + +// To keep track of which way the compare value is moving +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + + + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + +interrupt void epwm1_isr(void) +{ + // Update the CMPA and CMPB values + update_compare(&epwm1_info); + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +interrupt void epwm2_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm2_info); + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm3_info); + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +void InitEPwm1Example() +{ + + // Setup TBCLK + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // Setup shadow register load on ZERO + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value + + // Set actions + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count + + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count + + // Interrupt where we will change the Compare Values + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & CMPB + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; + +} + + +void InitEPwm2Example() +{ + // Setup TBCLK + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // Setup shadow register load on ZERO + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value + + // Set actions + EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + + EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on Period + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2B on event B, up count + + // Interrupt where we will change the Compare Values + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; // Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; + +} + + +void InitEPwm3Example(void) +{ + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadow register load on ZERO + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // Set Actions + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on event B, up count + EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Clear PWM3A on event B, up count + + EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE; // Toggle EPWM3B on Zero + + // Interrupt where we will change the Compare Values + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Start by increasing the compare A and decreasing compare B + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; + // Start the cout at 0 + epwm3_info.EPwmTimerIntCount = 0; + epwm3_info.EPwmRegHandle = &EPwm3Regs; + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; +} + + +void update_compare(EPWM_INFO *epwm_info) +{ + + + // Every 10'th interrupt, change the CMPA/CMPB values + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // If we were increasing CMPA, check to see if + // we reached the max value. If not, increase CMPA + // else, change directions and decrease CMPA + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were decreasing CMPA, check to see if + // we reached the min value. If not, decrease CMPA + // else, change directions and increase CMPA + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were increasing CMPB, check to see if + // we reached the max value. If not, increase CMPB + // else, change directions and decrease CMPB + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // If we were decreasing CMPB, check to see if + // we reached the min value. If not, decrease CMPB + // else, change directions and increase CMPB + + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel new file mode 100644 index 0000000..6ac8e2c --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.gel @@ -0,0 +1,41 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:14:13 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM UP AQ" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmUpAQ.pjt"); + GEL_ProjectBuild("Example_2833xEPwmUpAQ.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmUpAQ.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt new file mode 100644 index 0000000..45a227e --- /dev/null +++ b/v120/DSP2833x_examples/epwm_up_aq/Example_2833xEPwmUpAQ.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmUpAQ.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\Debug" -fs"C:\tidcs\c28\DSP2833x\006\DSP2833x_examples\epwm_asymmetic_aq\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_up_aq\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmUpAQ.map" -o".\Debug\Example_2833xEPwmUpAQ.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEPwmUpAQ.out" -x + diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c new file mode 100644 index 0000000..6ccdbb7 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c @@ -0,0 +1,499 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:41:53 $ +//########################################################################### +// +// FILE: Example_2833xEPwmUpDownAQ.c +// +// TITLE: Action Qualifier Module - Using up/down count +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM3 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures ePWM1, ePWM2, ePWM3 to produce an +// waveform with independant modulation on EPWMxA and +// EPWMxB. +// +// The compare values CMPA and CMPB are modified within the ePWM's ISR +// +// The TB counter is in up/down count mode for this example. +// +// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms +// via an oscilloscope +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +}EPWM_INFO; + + +// Prototype statements for functions found within this file. +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +interrupt void epwm1_isr(void); +interrupt void epwm2_isr(void); +interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// Global variables used in this example +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// Configure the period for each timer +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + +// To keep track of which way the compare value is moving +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;) + { + asm(" NOP"); + } + +} + + +interrupt void epwm1_isr(void) +{ + // Update the CMPA and CMPB values + update_compare(&epwm1_info); + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +interrupt void epwm2_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm2_info); + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_isr(void) +{ + + // Update the CMPA and CMPB values + update_compare(&epwm3_info); + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + +void InitEPwm1Example() +{ + + // Setup TBCLK + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // Set Compare values + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value + + // Setup counter mode + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadowing + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + + // Set actions + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count + + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count + EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count + + // Interrupt where we will change the Compare Values + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; + +} + + +void InitEPwm2Example() +{ + + + // Setup TBCLK + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // Set Compare values + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value + + // Setup counter mode + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadowing + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + + // Set actions + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + EPwm2Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM2A on event B, down count + + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Clear PWM2B on zero + EPwm2Regs.AQCTLB.bit.PRD = AQ_SET ; // Set PWM2B on period + + // Interrupt where we will change the Compare Values + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_UP; // increasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; // Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; + +} + +void InitEPwm3Example(void) +{ + + + // Setup TBCLK + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up/down + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // Setup shadow register load on ZERO + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // Set Compare values + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // Set Actions + EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM3A on period + EPwm3Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM3A on event B, down count + + EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM3A on period + EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM3A on event A, up count + + // Interrupt where we will change the Compare Values + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // Information this example uses to keep track + // of the direction the CMPA/CMPB values are + // moving, the min and max allowed values and + // a pointer to the correct ePWM registers + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + epwm3_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm3_info.EPwmRegHandle = &EPwm3Regs; // Set the pointer to the ePWM module + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; + +} + + + +void update_compare(EPWM_INFO *epwm_info) +{ + + + // Every 10'th interrupt, change the CMPA/CMPB values + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // If we were increasing CMPA, check to see if + // we reached the max value. If not, increase CMPA + // else, change directions and decrease CMPA + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were decreasing CMPA, check to see if + // we reached the min value. If not, decrease CMPA + // else, change directions and increase CMPA + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // If we were increasing CMPB, check to see if + // we reached the max value. If not, increase CMPB + // else, change directions and decrease CMPB + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // If we were decreasing CMPB, check to see if + // we reached the min value. If not, decrease CMPB + // else, change directions and increase CMPB + + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel new file mode 100644 index 0000000..017de80 --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:14:28 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ePWM UpDown AQ" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEPwmUpDownAQ.pjt"); + GEL_ProjectBuild("Example_2833xEPwmUpDownAQ.pjt"); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEPwmUpDownAQ.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt new file mode 100644 index 0000000..56449fe --- /dev/null +++ b/v120/DSP2833x_examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xEPwmUpDownAQ.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\Debug" -fs"C:\tidcs\c28\DSP2833x\006\DSP2833x_examples\epwm_Symmetric_aq\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_updown_aq\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwmUpDownAQ.map" -o".\Debug\Example_2833xEPwmUpDownAQ.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEPwmUpDownAQ.out" -x + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c new file mode 100644 index 0000000..443b1b7 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.c @@ -0,0 +1,178 @@ +// TI File $Revision: /main/12 $ +// Checkin $Date: July 10, 2008 11:07:26 $ +//########################################################################### +// +// FILE: Example_2833xEqep_freqcal.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Test requires the following hardware connections +// +// GPIO20/EQEP1A <- External input - connect to GPIO0/EPWM1A +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This test will provide frequency measurement using capture unit (freqhz_pr) +// and unit time out (freqhz_fr). The EPWM1A frequency will be measured by the EQEP. +// +// By default, EPWM1A is configured to generate a frequency of 5 kHz - measured +// frequency found in freqhz_pr and freqhz_fr should be 5000. +// +// See DESCRIPTION in Example_freqcal.c for more details on the frequency calculation +// performed in this example. +// +// In addition to this file, the following files must be included in this project: +// Example_freqcal.c - includes all eQEP functions +// Example_EPwmSetup.c - sets up EPWM1A for use with this example +// Example_freqcalh - includes initialization values for frequency structure. +// +// * Maximum frequency is configured to 10Khz (BaseFreq) +// * Minimum frequency is assumed at 50Hz for capture pre-scalar selection +// +// SPEED_FR: High Frequency Measurement is obtained by counting the external input pulses +// for 10ms (unit timer set to 100Hz). +// +// SPEED_FR = { (Count Delta)/10ms } +// +// +// SPEED_PR: Low Frequency Measurement is obtained by measuring time period of input edges. +// Time measurement is averaged over 64edges for better results and +// capture unit performs the time measurement using pre-scaled SYSCLK +// +// Note that pre-scaler for capture unit clock is selected such that +// capture timer does not overflow at the required minimum frequency +// +// This example runs forever until the user stops it. +// +// +// Watch Variables: freq.freqhz_fr - Frequency measurement using position counter/unit time out +// freq.freqhz_pr - Frequency measurement using capture unit +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +void EPwmSetup(void); +interrupt void prdTick(void); + +FREQCAL freq=FREQCAL_DEFAULTS; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Only init the GPIO for EQep1 and EPwm1 in this case +// This function is found in DSP2833x_EQep.c + InitEQep1Gpio(); + InitEPwm1Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// Example specific ePWM setup. This function is found +// in Example_EPwmSetup.c + EPwmSetup(); + +// Step 5. User specific code, enable interrupts: +// Enable CPU INT1 which is connected to CPU-Timer 0: + IER |= M_INT3; + +// Enable TINT0 in the PIE: Group 3 interrupt 1 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + freq.init(&freq); // Initializes eQEP for frequency calculation in + // FREQCAL_Init(void)function in Example_EPwmSetup.c + for(;;) + { + } + +} + +interrupt void prdTick(void) // Interrupts once per ePWM period +{ + freq.calc(&freq); // Checks for event and calculates frequency in FREQCAL_Calc(FREQCAL *p) + // function in Example_EPwmSetup.c + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel new file mode 100644 index 0000000..e76a9e2 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:14:43 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// projectn. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eQEP Frequency Calc" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEqep_freqcal.pjt"); + GEL_ProjectBuild("Example_2833xEqep_freqcal.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEqep_freqcal.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("freq.freqhz_fr",,""); + GEL_WatchAdd("freq.freqhz_pr",,""); + GEL_WatchAdd("EQep1Regs,x"); +} diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt new file mode 100644 index 0000000..46676a4 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_2833xEqep_freqcal.pjt @@ -0,0 +1,49 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EQep.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="..\..\DSP2833x_common\lib\IQmath_fpu32.lib" +Source="Example_2833xEqep_freqcal.c" +Source="Example_EPwmSetup.c" +Source="Example_freqcal.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Debug" -i".." -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -i"..\..\DSP2833x_common\lib" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_freqcal\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEqep_freqcal.map" -o".\Debug\Example_2833xEqep_freqcal.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEqep_freqcal.out" -x \ No newline at end of file diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c b/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c new file mode 100644 index 0000000..9f5aa7f --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_EPwmSetup.c @@ -0,0 +1,76 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:03 $ +//########################################################################### +// +// FILE: Example_EpwmSetup.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file contains source for the ePWM initialization for the +// freq calculation module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif +#define PWM_CLK 5e3 // If diff freq. desired, change freq here. +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // Up-down cnt, timebase = SYSCLKOUT + + +void EPwmSetup() +{ + InitEPwm1Gpio(); + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS=0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // Immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA =SP/2; + EPwm1Regs.CMPB=0; + + EPwm1Regs.AQCTLA.all=0x60; // EPWMxA = 1 when CTR=CMPA and counter inc + // EPWMxA = 0 when CTR=CMPA and counter dec + EPwm1Regs.AQCTLB.all=0; + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.DBCTL.all=0xb; // EPWMxB is inverted + EPwm1Regs.DBRED=0; + EPwm1Regs.DBFED=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=9; // Interrupt when TBCTR = 0x0000 + EPwm1Regs.ETPS.all=1; // Interrupt on first event + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; + +} + + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c new file mode 100644 index 0000000..500705e --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.c @@ -0,0 +1,186 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:07 $ +//########################################################################### +// +// FILE: Example_freqcal.c +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file includes the EQEP initialization and frequency calcuation +// functions called by Example_2833xEqep_freqcal.c. The frequency calculation +// steps performed by FREQCAL_Calc()at SYSCLKOUT = 150 MHz and 100 MHz are +// described below: +// +// For 150 MHz Operation: +// ---------------------- +// +// 1. This program calculates: **freqhz_fr** +// freqhz_fr or v = (x2-x1)/T - Equation 1 +// +// If max/base freq = 10kHz: 10kHz = (x2-x1)/(2/100Hz) - Equation 2 +// max (x2-x1) = 200 counts = freqScaler_fr +// Note: T = 2/100Hz. 2 is from (x2-x1)/2 - because QPOSCNT counts 2 edges per cycle +// (rising and falling) +// +// If both sides of Equation 2 are divided by 10 kHz, then: +// 1 = (x2-x1)/[10kHz*(2/100Hz)] where [10kHz* (2/100Hz)] = 200 +// Because (x2-x1) must be <200 (max), +// (x2-x1)/200 < 1 for all frequencies less than max +// freq_fr = (x2-x1)/200 or (x2-x1)/[10kHz*(2/100Hz)] - Equation 3 +// +// To get back to original velocity equation, Equation 1, multiply Equation 3 by 10 kHz +// freqhz_fr (or velocity) = 10kHz*(x2-x1)/[10kHz*(2/100Hz)] +// = (x2-x1)/(2/100Hz) - Final equation +// +// 2. min freq = 1 count/(2/100Hz) = 50 Hz +// +// 3. **freqhz_pr** +// freqhz_pr or v = X/(t2-t1) - Equation 4 +// +// If max/base freq = 10kHz: 10kHz = (4/2)/T = 4/2T +// where 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) +// 2 = divide by 2 because QPOSCNT counts 2 edges per cycle (rising and falling) +// T = time in seconds +// = t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and +// 1 QCAPCLK cycle = 1/(150MHz/128) +// = QCPRDLAT +// +// So: 10 kHz = 4(150MHz/128)/2(t2-t1) +// t2-t1 = 4(150MHz/128)/(10kHz*2) = (150MHz/128)/(2*10kHz/4) - Equation 5 +// = 234 QCAPCLK cycles = maximum (t2-t1) = freqScaler_pr +// +// Divide both sides by (t2-t1), and: +// 1 = 234/(t2-t1) = [150MHz/128)/(2*10kHz/4)]/(t2-t1) +// Because (t2-t1) must be <234 (max). +// 234/(t2-t1) < 1 for all frequencies less than max +// freq_pr = 234/(t2-t1) or [150MHz/128)/(2*10kHz/4)]/(t2-t1) - Equation 6 +// Now within velocity limits, to get back to original velocity equation, Equation 1, +// multiply Equation 6 by 10 kHz: +// freqhz_fr (or velocity) = 10kHz*[150MHz/128)/(2*10kHz/4)]/(t2-t1) +// = (105MHz/128)*4/[2(t2-t1)] +// or 4/[2*(t2-t1)(QCPRDLAT)] - Final Equation +// +// +// For 100 MHz Operation: +// ---------------------- +// +// The same calculations as above are performed, but with 100 MHz +// instead of 150MHz when calculating freqhz_pr, and at UPPS of 8 instead of 4. +// The value for freqScaler_pr becomes: (100MHz/128)/(2*10kHz/8) = 313 +// More detailed calculation results can be found in the Example_freqcal.xls +// spreadsheet included in the example folder. +// +// +// This file contains source for the freq calculation module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +void FREQCAL_Init(void) +{ + #if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100MHz SYSCLKOUT + #endif + + EQep1Regs.QDECCTL.bit.QSRC=2; // Up count mode (freq. measurement) + EQep1Regs.QDECCTL.bit.XCR=0; // 2x resolution (cnt falling and rising edges) + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + EQep1Regs.QEPCTL.bit.PCRM=00; // QPOSCNT reset on index evnt + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timer Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + + #if (CPU_FRQ_150MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=2; // 1/4 for unit position at 150MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=3; // 1/8 for unit position at 100MHz SYSCLKOUT + #endif + + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable + +} + +void FREQCAL_Calc(FREQCAL *p) +{ + unsigned long tmp; + _iq newp,oldp; + + +//**** Freq Calcultation using QEP position counter ****// +// Check unit Time out-event for speed calculation: +// Unit Timer is configured for 100Hz in INIT function + +// For a more detailed explanation of the calculation, read +// the description at the top of this file + + if(EQep1Regs.QFLG.bit.UTO==1) // Unit Timeout event + { + /** Differentiator **/ + newp=EQep1Regs.QPOSLAT; // Latched POSCNT value + oldp=p->oldpos; + + if (newp>oldp) + tmp = newp - oldp; // x2-x1 in v=(x2-x1)/T equation + else + tmp = (0xFFFFFFFF-oldp)+newp; + + p->freq_fr = _IQdiv(tmp,p->freqScaler_fr); // p->freq_fr = (x2-x1)/(T*10KHz) + tmp=p->freq_fr; + + if (tmp>=_IQ(1)) // is freq greater than max freq (10KHz for this example)? + p->freq_fr = _IQ(1); + else + p->freq_fr = tmp; + + p->freqhz_fr = _IQmpy(p->BaseFreq,p->freq_fr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_fr = (p->freq_fr)*10kHz = (x2-x1)/T + + // Update position counter + p->oldpos = newp; + //======================================= + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + +//**** Freq Calcultation using QEP capture counter ****// + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit Position Event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + tmp=(unsigned long)EQep1Regs.QCPRDLAT; + else // Capture overflow, saturate the result + tmp=0xFFFF; + + p->freq_pr = _IQdiv(p->freqScaler_pr,tmp); // p->freq_pr = X/[(t2-t1)*10KHz] + tmp=p->freq_pr; + + if (tmp>_IQ(1)) + p->freq_pr = _IQ(1); + else + p->freq_pr = tmp; + + p->freqhz_pr = _IQmpy(p->BaseFreq,p->freq_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_pr =( p->freq_pr)*10kHz = X/(t2-t1) + EQep1Regs.QEPSTS.all=0x88; // Clear Unit position event flag + // Clear overflow error flag + } + + +} + + diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h new file mode 100644 index 0000000..874e66f --- /dev/null +++ b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.h @@ -0,0 +1,112 @@ +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:14:59 $ +//########################################################################### +// +// FILE: Example_freqcal.h +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: +// +// Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef __FREQCAL__ +#define __FREQCAL__ + +#include "IQmathLib.h" // Include header for IQmath library +/*----------------------------------------------------------------------------- +Define the structure of the FREQCAL Object +-----------------------------------------------------------------------------*/ +typedef struct { + Uint32 freqScaler_pr; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) - independently with global Q + Uint32 freqScaler_fr; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) - independently with global Q + Uint32 BaseFreq; // Parameter : Maximum Freq + _iq freq_pr; // Output : Freq in per-unit using capture unit + int32 freqhz_pr; // Output: Freq in Hz, measured using Capture unit + Uint32 oldpos; + _iq freq_fr; // Output : Freq in per-unit using position counter + int32 freqhz_fr; // Output: Freq in Hz, measured using Capture unit + void (*init)(); // Pointer to the init funcion + void (*calc)(); // Pointer to the calc funtion + } FREQCAL; + +/*----------------------------------------------------------------------------- +Define a QEP_handle +-----------------------------------------------------------------------------*/ +typedef FREQCAL *FREQCAL_handle; + +/*----------------------------------------------------------------------------- +Default initializer for the FREQCAL Object. +-----------------------------------------------------------------------------*/ + + +#if (CPU_FRQ_150MHZ) + #define FREQCAL_DEFAULTS {\ + 234,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define FREQCAL_DEFAULTS {\ + 313,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif + +/*----------------------------------------------------------------------------- +Prototypes for the functions in Example_freqcal.c +-----------------------------------------------------------------------------*/ +void FREQCAL_Init(void); +void FREQCAL_Calc(FREQCAL_handle); + +#endif /* __FREQCAL__ */ + +/* Notes: + +For 150 MHz Operation: +---------------------- +1. freqScaler_fr + v = (x2-x1)/T - Equation 1 + + If max/base freq = 10kHz: 10kHz = (x2-x1)/(2/100Hz) - Equation 2 + max (x2-x1) = 200 counts = freqScaler_fr + Note: T = 2/100Hz. 2 is from (x2-x1)/2 - because QPOSCNT counts 2 edges per cycle + (rising and falling) + freqhz_fr = 200 default + +2. min freq = 1 count/(2/100Hz) = 50 Hz + +3. freqScaler_pr + v = X/(t2-t1) - Equation 4 + + If max/base freq = 10kHz: 10kHz = 8/(2T) + where 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) + T = time in seconds = t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and + 1 QCAPCLK cycle = 1/(150MHz/128) + = QCPRDLAT + So: 10 kHz = 4(150MHz/128)/2(t2-t1) + t2-t1 = 4(150MHz/128)/(10kHz*2) = (150MHz/128)/(2*10kHz/4) - Equation 5 + = 234 seconds = maximum (t2-t1) = freqScaler_pr + freqhz_pr = 234 default + + +For 100 MHz Operation: +---------------------- + +The same calculations as above are performed, but with 100 MHz +instead of 150MHz when calculation freqhr_pr, and at UPPS of 8 instead of 4. +The value for freqScaler_pr becomes: (100MHz/128)/(2*10kHz/8) = 313 +More detailed calculation results can be found in the Example_freqcal.xls +spreadsheet included in the example folder. + +*/ diff --git a/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.xls b/v120/DSP2833x_examples/eqep_freqcal/Example_freqcal.xls new file mode 100644 index 0000000000000000000000000000000000000000..a7128d2d72eee8a03a556d932b7f015f12dbcc66 GIT binary patch literal 16896 zcmeHOdvH|M8UJ=Sn+GA}Wq9SmO(L)fuLP(>1=)}Qp(PSRqF9l*CO5c}&4%3#MzA$i zpqA>0)hRln0%feIXEz42({F!S?q%cW*Y?B#ND?t-WXG z+nbR%E2)&B^>C&qeJAF*yYio6ImyvtD6Om%%k@jj!jvm`^Nq?`!vm|S;u88irFm)hNm?`Cx^ zP}gC&+GMwqIjkt9GFtY7KYZOL4tJ44r>$H9;uVjy$TwTN73RLot_`)%5D_03eGMloLE>`(ol5%GM8CcR+JZ)k2uchQ-5i#-gH@CrUFTj+$huJlD>LSrmFE6 z3I(xTG1?-mGo)CiiZsxbV$Jj{Qe5Uzgk?qNM+gOz3gCBx%iRDglcfkhi1wB%)_MyS zYkeeU%S1V^uQ8(qeeEgNdYPO(J8JYCnSdUS8a3s6?3%*LbX4-FoP|yi`8cepyK(8# zNar9@^pDJ{FQ>D62jU-$POSs+f1l|#(b&95GVz>X;P6Q-y=V~n#6jrAgV2)(q;q{# z{$PSMlHm`Z72R!6C2ois4?XnD)6?CWTkA*f;ZGife=vH=ApAv zikBr<>UyY@l*W<0C{szfYE&=Ew3{Rj?X$^VTOu;%r#&|LLXOxmC8#|Mx~HP1UYi%t zSE0)mw6?W}g2{Yn_6K~Pkk{WjUS#py8clCnp$9ckHP7l5TFC3uHJ|PYwg+^d-WqaE zUB0pi6H^`OWD4pndSgg$(xS4SkmmEYYPB`hu3%B2p|zsCMr&;GH?Gt|ekk^Pn>7Dw zJ<#0ZzuHx`rU-L$wYSylYxgNV6^gShpic@mdRjbz2_lQyLvUI1M*Y=Vb-f9O=|!Wz zwb{F(J)jzrVwkK6=!SF_lzTdq@>+dWyEgzK;xI&HUhUk)4fS;ks^q*{#=X@W(iAjpdcf;%Vq>q+wYGqNMZn|p8P1lL zlvJ%53Lk+f$SCKS0@x{&)2dl5B zncbl1#fm;bU9VS^PVOHgX)I;~>~rL2sM#AwTXg9L#l22ltL4{VS%%*gu+@OwXFys} znl80K z-<-xjV^q=T4tC(!OJU+0j2auG_OAA%C5}>$h6q-T3YHr=Pp; z=3fLmo;dze(|hmKKN#L@o3#DaPj=mOyy-P5xa+3J#%_J{)|o%gsYqBnZPP`6n|Rgd z6Hgtz?7~CuGX68?dFu}6Khl){n@yhg6Q`$!4hnE>z`lrWXUH7W^GGv&$u^u>j%#4 zjej|QZRM11+eaI_r_{Gro!&Ha{qoyRkNd;e4>#<{pIdlK{@RCz9d=x}t?Hod!*v(@ z@r7yocOKh)`i`ZAj#mnI&3J?$P6oCYjrn52_`6Q- zzOQ9b$Cfv{m#=uEW#{8{4?Okai`{Eyl-9cHANW!6U!UE0a`EIBp4xfvs_yGY&p-9c zr*0fy>hE~rhHKwB`E=Q{-h1!aRem@>^(TR(b!`{y{VeU-x7X&mF8w&RXRPx79|GGj z<=WIN!WqSmIfSza)6v=H-6r*@NtB+_=T^ zaixi+Vei$C#$_y)4=Zjz8gYr`BQmixtj_&t83WKV2cU6Xiq*$;DwZ~U02&s{etg`l z#>!%&)sL1v01dmtetbBn_oMOsTW=eugvbk4YiebQnYMPy@#Yxg1IZQKkk5_=wN~ zH)R}<$&GMPhU1oWj>{}X=V;7QEuk)_(#4TNT~6>5*-P9;9lhb`FiLSKVe_I&Y+p9^ zFoqm`CHf1LT!N}IdU7nhwu^>3Ca)X&pUg*3rAj3l-j!z;XC-WQ#nV6noKICvVTk}` z35T^&qB#Z}-AsZ?HaSh1OHy(ium&gHWY@98PRUk{kC$;M(ap7IJv{%|njM&6lEofQ zlS-(gEAd&Cz|!!Au%;>~sD($dY=FbzFqTrPu_Et<%gVW1w1;6a9Ik}^u6UR(&sN5h zl@j7YB}0`GBkuDl1ShY4do_L+xrHc&lcf?vsH+kNy5iYsgxBb_6eY|}AKTBZBinzu zn~GDE83w0OV*44EEDcj~M(~}BlIgj)eQrU$JzN+u3Y}d*pr>01N_U{+KPG_GlbrDP3k9WI*X`hC?nI2P0IS83!X!rx79~#sNA5!=@4qH{t*`jj=aEnPXGvCf$g}!6>EDj03*3 zC7H24U#2VLkjeAaFV?;6t1hoaN!BC)`A6)Ud5pz8{euK^?V<| z^E^Mr;umK8>XcvK@zW^EpF-x{O5ZI4wc^JwBpSZ|YQ;Su*Pw^aJPpU!BW4RYj5A9U3NU(cVif1~|;7iZf47jCD` A3;+NC literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c new file mode 100644 index 0000000..9475939 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c @@ -0,0 +1,201 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: July 10, 2008 11:06:28 $ +//########################################################################### +// +// FILE: Example_2833xEqep_pos_speed_.c +// +// TITLE: EQEP Speed and Position measurement +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Test requires the following hardware connections from EPWM1 and +// GPIO pins (simulating QEP sensor) to QEP peripheral +// +// GPIO20/EQEP1A <- GPIO0/EPWM1A (simulates EQEP Phase A signal) +// GPIO21/EQEP1B <- GPIO1/EPWM1B (simulates EQEP Phase B signal) +// GPIO23/EQEP1I <- GPIO4 (simulates EQEP Index Signal) +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This test will provide position measurement, speed measurement using the capture unit, and +// speed measurement using unit time out. This example uses the IQMath library. It is used +// merely to simplify high-precision calculations. +// +// See DESCRIPTION in Example_posspeed.c for more details on the calculations +// performed in this example. +// +// In addition to this file, the following files must be included in this project: +// Example_posspeed.c - includes all eQEP functions +// Example_EPwmSetup.c - sets up EPWM1A and EPWM1B as simulated QA and QB encoder signals +// Example_posspeed.h - includes initialization values for pos and speed structure +// +// Notes: +// * Maximum speed is configured to 6000rpm(BaseRpm) +// * Minimum speed is assumed at 10rpm for capture pre-scalar selection +// * Pole pair is configured to 2 (pole_pairs) +// * QEP Encoder resolution is configured to 4000counts/revolution (mech_scaler) +// which means: 4000/4 = 1000 line/revolution quadrature encoder (simulated by EPWM1) +// * EPWM1 (simulating QEP encoder signals) is configured for 5kHz frequency or 300 rpm +// (=4*5000 cnts/sec * 60 sec/min)/4000 cnts/rev) +// * 300 rpm EPWM1 speed will be measured by EQEP. +// +// SPEEDRPM_FR: High Speed Measurement is obtained by counting the QEP input pulses +// for 10ms (unit timer set to 100Hz). +// +// SPEEDRPM_FR = { (Position Delta)/10ms } * 60 rpm +// +// +// SPEEDRPM_PR: Low Speed Measurement is obtained by measuring time period of QEP edges. +// Time measurement is averaged over 64edges for better results and +// capture unit performs the time measurement using pre-scaled SYSCLK +// +// Note that pre-scaler for capture unit clock is selected such that +// capture timer does not overflow at the required minimum RPM speed +// +// Watch Variables: qep_posspeed.SpeedRpm_fr - Speed meas. in rpm using QEP position counter +// qep_posspeed.SpeedRpm_pr - Speed meas. in rpm using capture unit +// qep_posspeed.theta_mech - Motor mechanical angle (Q15) +// qep_posspeed.theta_elec - Motor electrical angle (Q15) +// +//########################################################################### +// Original Author S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +void initEpwm(); +interrupt void prdTick(void); + +POSSPEED qep_posspeed=POSSPEED_DEFAULTS; +Uint16 Interrupt_Count = 0; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this case only init GPIO for eQEP1 and ePWM1 +// This function is found in DSP2833x_EQep.c + InitEQep1Gpio(); + InitEPwm1Gpio(); + EALLOW; + GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; // GPIO4 as output simulates Index signal + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; // Normally low + EDIS; +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: + initEpwm(); // This function exists in Example_EPwmSetup.c + +// Step 5. User specific code, enable interrupts: +// Enable CPU INT1 which is connected to CPU-Timer 0: + IER |= M_INT3; + +// Enable TINT0 in the PIE: Group 3 interrupt 1 + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + qep_posspeed.init(&qep_posspeed); + + for(;;) + { + } + +} + + +interrupt void prdTick(void) // EPWM1 Interrupts once every 4 QCLK counts (one period) +{ Uint16 i; + // Position and Speed measurement + qep_posspeed.calc(&qep_posspeed); + + // Control loop code for position control & Speed contol + Interrupt_Count++; + if (Interrupt_Count==1000) // Every 1000 interrupts(4000 QCLK counts or 1 rev.) + { + EALLOW; + GpioDataRegs.GPASET.bit.GPIO4 = 1; // Pulse Index signal (1 pulse/rev.) + for (i=0; i<700; i++){ + } + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; + Interrupt_Count = 0; // Reset count + EDIS; + } + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel new file mode 100644 index 0000000..eb40b6a --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:15:15 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x eQEP Posspeed" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xEqep_pos_speed.pjt"); + GEL_ProjectBuild("Example_2833xEqep_pos_speed.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xEqep_pos_speed.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("qep_posspeed.SpeedRpm_fr",,""); + GEL_WatchAdd("qep_posspeed.SpeedRpm_pr",,""); + GEL_WatchAdd("qep_posspeed.theta_mech",,""); + GEL_WatchAdd("qep_posspeed.theta_elec",,""); + GEL_WatchAdd("EQep1Regs,x"); +} diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt new file mode 100644 index 0000000..1463168 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_2833xEqep_pos_speed.pjt @@ -0,0 +1,56 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EQep.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="..\..\DSP2833x_common\lib\IQmath_fpu32.lib" +Source="Example_2833xEqep_pos_speed.c" +Source="Example_EPwmSetup.c" +Source="Example_posspeed.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Debug" -i".." -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -i"..\..\DSP2833x_common\lib" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\eqep_pos_speed\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xEqep_pos_speed.map" -o".\Debug\Example_2833xEqep_pos_speed.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xEqep_pos_speed.out" -x + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c new file mode 100644 index 0000000..9d4ef5a --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_EPwmSetup.c @@ -0,0 +1,69 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:18 $ +//########################################################################### +// +// FILE: Example_EpwmSetup.c +// +// TITLE: Pos speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file contains source for the ePWM initialization for the +// pos/speed module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif + +#define PWM_CLK 5e3 // 5kHz (300rpm) EPWM1 frequency. Freq. can be changed here +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // up-down count, timebase=SYSCLKOUT + + +void initEpwm() +{ + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS =0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA=SP/2; + EPwm1Regs.CMPB=0; + + EPwm1Regs.AQCTLA.all=0x60; // CTR=CMPA when inc->EPWM1A=1, when dec->EPWM1A=0 + EPwm1Regs.AQCTLB.all=0x09; // CTR=PRD ->EPWM1B=1, CTR=0 ->EPWM1B=0 + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=0x0A; // Interrupt on PRD + EPwm1Regs.ETPS.all=1; + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; +} + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c new file mode 100644 index 0000000..7b25307 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.c @@ -0,0 +1,245 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:23 $ +//########################################################################### +// +// FILE: Example_posspeed.c +// +// TITLE: Pos/speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// This file includes the EQEP initialization and position and speed calcuation +// functions called by Example_2833xEqep_posspeed.c. The position and +// speed calculation steps performed by POSSPEED_Calc() at SYSCLKOUT = 150 MHz +// and 100 MHz are described in detail below: +// +// For 150 MHz Operation: +// ---------------------- +// +// 1. This program calculates: **theta_mech** +// +// theta_mech = QPOSCNT/mech_Scaler = QPOSCNT/4000, where 4000 is the number of +// counts in 1 revolution.(4000/4 = 1000 line/rev. quadrature encoder) +// +// 2. This program calculates: **theta_elec** +// +// theta_elec = (# pole pairs) * theta_mech = 2*QPOSCNT/4000 for this example +// +// 3. This program calculates: **SpeedRpm_fr** +// +// SpeedRpm_fr = [(x2-x1)/4000]/T - Equation 1 +// Note (x2-x1) = difference in number of QPOSCNT counts. Dividing (x2-x1) by +// 4000 gives position relative to Index in one revolution. +// If base RPM = 6000 rpm: 6000 rpm = [(x2-x1)/4000]/10ms - Equation 2 +// = [(x2-x1)/4000]/(.01s*1 min/60 sec) +// = [(x2-x1)/4000]/(1/6000) min +// max (x2-x1) = 4000 counts, or 1 revolution in 10 ms +// +// +// If both sides of Equation 2 are divided by 6000 rpm, then: +// 1 = [(x2-x1)/4000] rev./[(1/6000) min * 6000rpm] +// Because (x2-x1) must be <4000 (max) for QPOSCNT increment, +// (x2-x1)/4000 < 1 for CW rotation +// And because (x2-x1) must be >-4000 for QPOSCNT decrement, +// (x2-x1)/4000>-1 for CCW rotation +// speed_fr = [(x2-x1)/4000]/[(1/6000) min * 6000rpm] +// = (x2-x1)/4000 - Equation 3 +// +// To convert speed_fr to RPM, multiply Equation 3 by 6000 rpm +// SpeedRpm_fr = 6000rpm *(x2-x1)/4000 - Final Equation +// +// +// 2. **min rpm ** = selected at 10 rpm based on CCPS prescaler options available (128 is greatest) +// +// 3. **SpeedRpm_pr** +// SpeedRpm_pr = X/(t2-t1) - Equation 4 +// where X = QCAPCTL [UPPS]/4000 rev. (position relative to Index in 1 revolution) +// If max/base speed = 6000 rpm: 6000 = (32/4000)/[(t2-t1)/(150MHz/128)] +// where 32 = QCAPCTL [UPPS] (Unit timeout - once every 32 edges) +// 32/4000 = position in 1 revolution (position as a fraction of 1 revolution) +// t2-t1/(150MHz/128), t2-t1= # of QCAPCLK cycles, and +// 1 QCAPCLK cycle = 1/(150MHz/128) +// = QCPRDLAT +// +// So: 6000 rpm = [32(150MHz/128)*60s/min]/[4000(t2-t1)] +// t2-t1 = [32(150MHz/128)*60 s/min]/(4000*6000rpm) - Equation 5 +// = 94 CAPCLK cycles = maximum (t2-t1) = SpeedScaler +// +// Divide both sides by (t2-t1), and: +// 1 = 94/(t2-t1) = [32(150MHz/128)*60 s/min]/(4000*6000rpm)]/(t2-t1) +// Because (t2-t1) must be < 94 for QPOSCNT increment: +// 94/(t2-t1) < 1 for CW rotation +// And because (t2-t1) must be >-94 for QPOSCNT decrement: +// 94/(t2-t1)> -1 for CCW rotation +// +// speed_pr = 94/(t2-t1) +// or [32(150MHz/128)*60 s/min]/(4000*6000rpm)]/(t2-t1) - Equation 6 +// +// To convert speed_pr to RPM: +// Multiply Equation 6 by 6000rpm: +// SpeedRpm_fr = 6000rpm * [32(150MHz/128)*60 s/min]/[4000*6000rpm*(t2-t1)] +// = [32(150MHz/128)*60 s/min]/[4000*(t2-t1)] +// or [(32/4000)rev * 60 s/min]/[(t2-t1)(QCPRDLAT)]- Final Equation +// +// +// For 100 MHz Operation: +// ---------------------- +// +// The same calculations as above are performed, but with 100 MHz +// instead of 150MHz when calculating SpeedRpm_pr. +// The value for freqScaler_pr becomes: [32*(100MHz/128)*60s/min]/(4000*6000rpm) = 63 +// More detailed calculation results can be found in the Example_freqcal.xls +// spreadsheet included in the example folder. +// +// +// +// This file contains source for the posspeed module +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +void POSSPEED_Init(void) +{ + + #if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150 MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100 MHz SYSCLKOUT + #endif + + EQep1Regs.QDECCTL.bit.QSRC=00; // QEP quadrature count mode + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + EQep1Regs.QEPCTL.bit.PCRM=00; // PCRM=00 mode - QPOSCNT reset on index event + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timeout Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + + EQep1Regs.QCAPCTL.bit.UPPS=5; // 1/32 for unit position + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable + + +} + +void POSSPEED_Calc(POSSPEED *p) +{ + long tmp; + unsigned int pos16bval,temp1; + _iq Tmp1,newp,oldp; + +//**** Position calculation - mechanical and electrical motor angle ****// + p->DirectionQep = EQep1Regs.QEPSTS.bit.QDF; // Motor direction: 0=CCW/reverse, 1=CW/forward + + pos16bval=(unsigned int)EQep1Regs.QPOSCNT; // capture position once per QA/QB period + p->theta_raw = pos16bval+ p->cal_angle; // raw theta = current pos. + ang. offset from QA + + // The following lines calculate p->theta_mech ~= QPOSCNT/mech_scaler [current cnt/(total cnt in 1 rev.)] + // where mech_scaler = 4000 cnts/revolution + tmp = (long)((long)p->theta_raw*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + p->theta_mech = (int)(tmp>>11); // Q26 -> Q15 + p->theta_mech &= 0x7FFF; + + // The following lines calculate p->elec_mech + p->theta_elec = p->pole_pairs*p->theta_mech; // Q0*Q15 = Q15 + p->theta_elec &= 0x7FFF; + +// Check an index occurrence + if (EQep1Regs.QFLG.bit.IEL == 1) + { + p->index_sync_flag = 0x00F0; + EQep1Regs.QCLR.bit.IEL=1; // Clear interrupt flag + } + + + +//**** High Speed Calcultation using QEP Position counter ****// +// Check unit Time out-event for speed calculation: +// Unit Timer is configured for 100Hz in INIT function + + if(EQep1Regs.QFLG.bit.UTO==1) // If unit timeout (one 100Hz period) + { + /** Differentiator **/ + // The following lines calculate position = (x2-x1)/4000 (position in 1 revolution) + pos16bval=(unsigned int)EQep1Regs.QPOSLAT; // Latched POSCNT value + tmp = (long)((long)pos16bval*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + tmp = (int)(tmp>>11); // Q26 -> Q15 + tmp &= 0x7FFF; + newp=_IQ15toIQ(tmp); + oldp=p->oldpos; + + if (p->DirectionQep==0) // POSCNT is counting down + { + if (newp>oldp) + Tmp1 = - (_IQ(1) - newp + oldp); // x2-x1 should be negative + else + Tmp1 = newp -oldp; + } + else if (p->DirectionQep==1) // POSCNT is counting up + { + if (newp_IQ(1)) + p->Speed_fr = _IQ(1); + else if (Tmp1<_IQ(-1)) + p->Speed_fr = _IQ(-1); + else + p->Speed_fr = Tmp1; + + // Update the electrical angle + p->oldpos = newp; + + // Change motor speed from pu value to rpm value (Q15 -> Q0) + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + p->SpeedRpm_fr = _IQmpy(p->BaseRpm,p->Speed_fr); + //======================================= + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + +//**** Low-speed computation using QEP capture counter ****// + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit position event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + temp1=(unsigned long)EQep1Regs.QCPRDLAT; // temp1 = t2-t1 + else // Capture overflow, saturate the result + temp1=0xFFFF; + + p->Speed_pr = _IQdiv(p->SpeedScaler,temp1); // p->Speed_pr = p->SpeedScaler/temp1 + Tmp1=p->Speed_pr; + + if (Tmp1>_IQ(1)) + p->Speed_pr = _IQ(1); + else + p->Speed_pr = Tmp1; + + // Convert p->Speed_pr to RPM + if (p->DirectionQep==0) // Reverse direction = negative + p->SpeedRpm_pr = -_IQmpy(p->BaseRpm,p->Speed_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + else // Forward direction = positive + p->SpeedRpm_pr = _IQmpy(p->BaseRpm,p->Speed_pr); // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + + + EQep1Regs.QEPSTS.all=0x88; // Clear Unit position event flag + // Clear overflow error flag + } + + +} + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h new file mode 100644 index 0000000..14d1761 --- /dev/null +++ b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.h @@ -0,0 +1,85 @@ +// TI File $Revision: /main/6 $ +// Checkin $Date: August 9, 2007 17:15:33 $ +//########################################################################### +// +// FILE: Example_posspeed.h +// +// TITLE: Pos/speed measurement using EQEP peripheral +// +// DESCRIPTION: +// +// Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// Original Author: SD +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef __POSSPEED__ +#define __POSSPEED__ + +#include "IQmathLib.h" // Include header for IQmath library +/*----------------------------------------------------------------------------- +Define the structure of the POSSPEED Object +-----------------------------------------------------------------------------*/ +typedef struct {int theta_elec; // Output: Motor Electrical angle (Q15) + int theta_mech; // Output: Motor Mechanical Angle (Q15) + int DirectionQep; // Output: Motor rotation direction (Q0) + int QEP_cnt_idx; // Variable: Encoder counter index (Q0) + int theta_raw; // Variable: Raw angle from Timer 2 (Q0) + int mech_scaler; // Parameter: 0.9999/total count, total count = 4000 (Q26) + int pole_pairs; // Parameter: Number of pole pairs (Q0) + int cal_angle; // Parameter: Raw angular offset between encoder and phase a (Q0) + int index_sync_flag; // Output: Index sync status (Q0) + + Uint32 SpeedScaler; // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q speed (Q0) - independently with global Q + _iq Speed_pr; // Output : speed in per-unit + Uint32 BaseRpm; // Parameter : Scaler converting GLOBAL_Q speed to rpm (Q0) speed - independently with global Q + int32 SpeedRpm_pr; // Output : speed in r.p.m. (Q0) - independently with global Q + + _iq oldpos; // Input: Electrical angle (pu) + _iq Speed_fr; // Output : speed in per-unit + int32 SpeedRpm_fr; // Output : Speed in rpm (Q0) - independently with global Q + void (*init)(); // Pointer to the init funcion + void (*calc)(); // Pointer to the calc funtion + } POSSPEED; + +/*----------------------------------------------------------------------------- +Define a POSSPEED_handle +-----------------------------------------------------------------------------*/ +typedef POSSPEED *POSSPEED_handle; + +/*----------------------------------------------------------------------------- +Default initializer for the POSSPEED Object. +-----------------------------------------------------------------------------*/ + +#if (CPU_FRQ_150MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 94,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 63,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif + + +/*----------------------------------------------------------------------------- +Prototypes for the functions in posspeed.c +-----------------------------------------------------------------------------*/ +void POSSPEED_Init(void); +void POSSPEED_Calc(POSSPEED_handle); + +#endif /* __POSSPEED__ */ + + + + diff --git a/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.xls b/v120/DSP2833x_examples/eqep_pos_speed/Example_posspeed.xls new file mode 100644 index 0000000000000000000000000000000000000000..367b4e9332573955b4be230d2648200896e1bccf GIT binary patch literal 16896 zcmeHOdvH|M8UOBXc9RewF9Mi^9uvcXV^S@IARG_JcBT*>Z+-Hpaq zjR@4Dj!>LpD^;M5irQLr3e@LfZ56B5kuq8=7Br%N=rAzaK@_&X@7#OY%_dRoRGsQQ z%Q^R+?|iTGo$ouZTweQI_JJ*r<{zY_G@HzHGL}x(1h|CvV!fV4XphCXsy~bH4v>-l zk1UX$hJmzN$X)zO>h36B%|r*uM88kjg_7tUf90Kn)QI?8w zG)jqf2%3EYQcd~vBJg83tYdd4+HaBSDMUVUQx|=`t(zh4i{wgZeTofY8mLuKN+DTj z98u|+rDapf%Bni;=Pa@5l_mC~loG^o;ehtVt%~>Jfk>s4N)zHp6;%WIpw6r&!4*oA zv68rHs57aYrV(|rD&?}SnO0q56M!Z5b2LEd)Kci(X>)W!N(I^R18E{%xtvH;E)Srn zqbYRuKw)YR2FeqvC5Wu6iwixACS!!-LUsC6a&=-MI!<|j#$Zs0K8eZVsTNV0;p{{L z{;}Tl#c&?pq40-;GuNT;zsqomWbU4pbbC%#?Qkp^ZXX6dWf*w*F!1yt;k-TyeK0|) zN!5qn1>B)RDP@H4hg0xNv$GwtLmmV_g`Y7D{&4V7!{FOBKg>||>H0FcIv)++tK(vwo{{Kt8f~rx67NCMiP~I^jm}P2t5YUw40wWGB_y{h z;b2!!#1{<6wi&$(8eQ^yUqA`lAzwwG+uFEbEGpfK;!VH~+giK*c8pa_~wew6rUDm96O- zJ0|dEU%=<@@e4i;0<$}$ObvV7UGC6iqL!WrRF-{ledPf93Bjy|Cm2}jThFytKpUqtQ>hJ9jm(Qj2H zwpDfI^l5N{26uM^L!jAE!+=u=jOuAM1^T!rjFk*?C^DNDeG?+YsC6qLU(m~xmnm|0 zD7Y--_WM;kR##OuT?0>%=eWZPyru*LJeT=x5!@1BS)ytqm(BtU|r4m83 z+}v~xzx`0W#jq5o(M~ukB+!Lu_${6l&~7DSW+sB<7Azc|v^-=qXem#7=5SQ18^Ejq z8^8>cx}Y(hjJzyzyHE(+H{E+~&4E9gZ+K=+YRRf#^nN*X$hy_^()mnZhm`x?N19EQWs2LcfsGMT=ChI69+Cnf6x1c-hG!_k6X@O zwXft6Z^>`gxj#sokr~^a;p~5_a9`7*l8m&6UCS<7R$RO1_>|Xr?%f?&{n>lXFIpo7 zkL6ZA<6P?tbzRp?MFMYhWzp^9HbaGwo z>Pt49{J|e5ezfM^lE$*zORjx*^gi?XTbf>%K3X;VxtFHDxb5JMlXosEGrv~0z3!b& zcR&B;xOXR7YCX44-Mq%Ub^ilLj)u0{i$9+{>8_(Y?(1sl-Sl?qF_Qx@Ye?p7r#**B03pf08^hM*aI|fi0MFB{7TejAFtZ!m|jc19kdSq7JmA z(e+|lCi?j(o-IwH&QyL|yv}g{h3<1j>0>*1lGCy9El40074uav}JqX6T+hp4OAz;{&48p@cZx9UU@%d=iviQzKb1))zFamcq+2t0qBtd zJ;sp}?4nMXO7t&J=w!*Ws^rX?t)bSKHG3M@_^4OFM=D`8u+q9%zjsDGZ!OtsMX{I@ zLZenVlGd*bVKue}GZ`tEsDWO>L~yx7_Fuhv(N&8bM8|Tsp2#34{4MH)fT+-Eq+q}? zz<$8pR>yRdV1-SmFcI%Mc`z<@u$WPThT~tYaX;9&T*E;V{oonWN_9Lm`cU;PbP(E2 zF}r3WZLnA!F<4Fri3-Pnx#B$>Erjue!R*^4)N+I{J&^b&vXEB2v9X@Jl0$kR z4B85bxRGTe4&RPNcln!J&<@Niw9DH z&?6p5m<>6Qz%J^9IkZ4xowPtI5Ulk;;;A$qNQHv69!Ov{Adn^qt8pMfXks803YK~x zO%P1+asa_q^BEd=zq$15kY9JK} z8aosg<}i|q+%hA1L+N_rRQ)I zEX3Ys27Yr8HY0GkK8NPgVrry%ymcaWhijW{%AxJ-*#u2ar3n}WGyVY};T3P@!*D4J z%>;x^IrK4C-Aw6RHe*n~xg#!bB>51`3o;g72`aPtNb!wiuC|fXH-c(Am%JX(` z2s5a!JjrnS>Snkfj`*#aK~-9mU!xfkqyr!ALfJ+wZJ zCQo|&A60-ofXq`aw>yw|{cA$z%bg|2yvlSV^Ad0~GEc#GAam$%Mm8b$gNWxS#%Z4? zH~PD~f>$fbDVY9;Ml=f;M`^Rq6AFfdOCxe)uSe-pga6`f=^Ov>yyRfSim?@yH@+Zg zA;b_P85S@sU|7JgfMEf{0)_<)3m6tKEMQo`uz+C!!vdNGzUcgK+WX4hO%(-M8#dzn zKjqWk@%jHlWWL|z^S=w3?-my!^X+jjGT&PFA@iA?&;NYxUx&;$$#)|2eZXd9KKt)R zPP`A`d+c_l*BzGU1;UX~4}VL=?;gPUT>nsUhTxCaVV^}1%(#3omCPp$WU|7JgfMEf{0)_<)3m6tKEMQo`uz+EK?~Dcb z9M8vKKJW71^7+F`{wB(DTrT$WPExRz%xWwV}wpWjm6g^ zdJou-k-azcVf=%9!Z R_-gvp{1^S_yEt9`e*jM}?#KWD literal 0 HcmV?d00001 diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c new file mode 100644 index 0000000..903a088 --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.c @@ -0,0 +1,260 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: May 5, 2008 15:25:49 $ +//########################################################################### +// +// FILE: Example_2833xExternalInterrupt.c +// +// TITLE: DSP2833x External Interrupt test program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Connect GPIO30 to GPIO0. GPIO0 will be assigned to Xint1 +// Connect GPIO31 to GPIO1. GPIO1 will be assigned to XINT2 +// +// Monitor GPIO34 with an oscilloscope. GPIO34 will be high outside of the +// ISRs and low within each ISR. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program sets up GPIO0 as Xint1 and GPIO1 as XINT2. Two other +// GPIO signals are used to trigger the interrupt (GPIO30 triggers +// Xint1 and GPIO31 triggers XINT2). The user is required to +// externally connect these signals for the program to work +// properly. +// +// Xint1 input is synched to SYSCLKOUT +// XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each. +// +// GPIO34 will go high outside of the interrupts and low within the +// interrupts. This signal can be monitored on a scope. +// +// Each interrupt is fired in sequence - Xint1 first and then XINT2 +// +// +// Watch Variables: +// Xint1Count for the number of times through Xint1 interrupt +// Xint2Count for the number of times through XINT2 interrupt +// LoopCount for the number of times through the idle loop +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void xint1_isr(void); +interrupt void xint2_isr(void); + +// Global variables for this example +volatile Uint32 Xint1Count; +volatile Uint32 Xint2Count; +Uint32 LoopCount; + +#define DELAY 35.700L + +void main(void) +{ + Uint32 TempX1Count; + Uint32 TempX2Count; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &xint1_isr; + PieVectTable.XINT2 = &xint2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + +// Clear the counters + Xint1Count = 0; // Count Xint1 interrupts + Xint2Count = 0; // Count XINT2 interrupts + LoopCount = 0; // Count times through idle loop + +// Enable Xint1 and XINT2 in the PIE: Group 1 interrupt 4 & 5 +// Enable int1 which is connected to WAKEINT: + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Gropu 1 INT4 + PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable PIE Gropu 1 INT5 + IER |= M_INT1; // Enable CPU int1 + EINT; // Enable Global Interrupts + +// GPIO30 & GPIO31 are outputs, start GPIO30 high and GPIO31 low + EALLOW; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO30 = 1; // output + + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; // output + EDIS; + +// GPIO0 and GPIO1 are inputs + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 0; // Xint1 Synch to SYSCLKOUT only + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 2; // XINT2 Qual using 6 samples + GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0xFF; // Each sampling window is 510*SYSCLKOUT + EDIS; + +// GPIO0 is XINT1, GPIO1 is XINT2 + EALLOW; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Xint1 is GPIO0 + GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 1; // XINT2 is GPIO1 + EDIS; + +// Configure XINT1 + XIntruptRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt + XIntruptRegs.XINT2CR.bit.POLARITY = 1; // Rising edge interrupt + +// Enable XINT1 and XINT2 + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable Xint1 + XIntruptRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2 + + +// GPIO34 will go low inside each interrupt. Monitor this on a scope + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // output + EDIS; + +// Step 6. IDLE loop: + for(;;) + { + + TempX1Count = Xint1Count; + TempX2Count = Xint2Count; + + // Trigger both XINT1 + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + GpioDataRegs.GPACLEAR.bit.GPIO30 = 1; // Lower GPIO30, trigger Xint1 + while(Xint1Count == TempX1Count) {} + + // Trigger both XINT2 + + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + DELAY_US(DELAY); // Wait for Qual period + GpioDataRegs.GPASET.bit.GPIO31 = 1; // Raise GPIO31, trigger XINT2 + while(Xint2Count == TempX2Count) {} + + // Check that the counts were incremented properly and get ready + // to start over. + if(Xint1Count == TempX1Count+1 && Xint2Count == TempX2Count+1) + { + LoopCount++; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // raise GPIO30 + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // lower GPIO31 + } + else + { + asm(" ESTOP0"); // stop here + } + + } + + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + // If local ISRs are used, reassign vector addresses in vector table as + // shown in Step 5 + +interrupt void xint1_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint1Count++; + + // Acknowledge this interrupt to get more from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void xint2_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint2Count++; + + // Acknowledge this interrupt to get more from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel new file mode 100644 index 0000000..f2542a3 --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.gel @@ -0,0 +1,41 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:15:49 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x ExternalInterrupt" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xExternalInterrupt.pjt"); + GEL_ProjectBuild("Example_2833xExternalInterrupt.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xExternalInterrupt.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("Xint1Count,x"); + GEL_WatchAdd("Xint2Count,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("XIntruptRegs,x"); + GEL_WatchAdd("GpioCtrlRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt new file mode 100644 index 0000000..0e88e0e --- /dev/null +++ b/v120/DSP2833x_examples/external_interrupt/Example_2833xExternalInterrupt.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xExternalInterrupt.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\external_interrupt\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x\DSP2833x_examples\external_interrupt\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xExternalInterrupt.map" -o".\Debug\Example_2833xExternalInterrupt.out" -stack0x200 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xExternalInterrupt.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28332_Flash.gel b/v120/DSP2833x_examples/flash/Example_28332_Flash.gel new file mode 100644 index 0000000..d254c08 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28332_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:15:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28332 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28332_Flash.pjt"); + GEL_ProjectBuild("Example_28332_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28332_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt new file mode 100644 index 0000000..1d116ed --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28332_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28332.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28332_Flash.map" -o".\Debug\Example_28332_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28334_Flash.gel b/v120/DSP2833x_examples/flash/Example_28334_Flash.gel new file mode 100644 index 0000000..df91989 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28334_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:06 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28334 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28334_Flash.pjt"); + GEL_ProjectBuild("Example_28334_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28334_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt new file mode 100644 index 0000000..74faf44 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28334_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28334.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28334_Flash.map" -o".\Debug\Example_28334_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_28335_Flash.gel b/v120/DSP2833x_examples/flash/Example_28335_Flash.gel new file mode 100644 index 0000000..daf0d95 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28335_Flash.gel @@ -0,0 +1,45 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:14 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28335 Flash Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_28335_Flash.pjt"); + GEL_ProjectBuild("Example_28335_Flash.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Symbols() +{ + GEL_SymbolLoad(".\\debug\\Example_28335_Flash.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("EPwm1TimerIntCount,x"); + GEL_WatchAdd("EPwm2TimerIntCount,x"); + GEL_WatchAdd("EPwm3TimerIntCount,x"); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); +} + + + + diff --git a/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt b/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt new file mode 100644 index 0000000..766eeb9 --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_28335_Flash.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CSMPasswords.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFlash.c" +Source="..\..\DSP2833x_common\cmd\F28335.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\flash\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_28335_Flash.map" -o".\Debug\Example_28335_Flash.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFlash.out" -x + diff --git a/v120/DSP2833x_examples/flash/Example_2833xFlash.c b/v120/DSP2833x_examples/flash/Example_2833xFlash.c new file mode 100644 index 0000000..7e7d4db --- /dev/null +++ b/v120/DSP2833x_examples/flash/Example_2833xFlash.c @@ -0,0 +1,342 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:42:33 $ +//########################################################################### +// +// FILE: Example_2833xFlash.c +// +// TITLE: DSP2833x ePWM Timer Interrupt From Flash Example. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to FLASH" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash <- "boot to Flash" +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example runs the ePWM interrupt example from flash. +// +// 1) Build the project +// 2) Flash the .out file into the device. +// 3) Set the hardware jumpers to boot to Flash +// 4) Use the included GEL file to load the project, symbols +// defined within the project and the variables into the watch +// window. +// +// Steps that were taken to convert the ePWM example from RAM +// to Flash execution: +// +// - Change the linker cmd file to reflect the flash memory map. +// - Make sure any initialized sections are mapped to Flash. +// In SDFlash utility this can be checked by the View->Coff/Hex +// status utility. Any section marked as "load" should be +// allocated to Flash. +// - Make sure there is a branch instruction from the entry to Flash +// at 0x33FFF6 to the beginning of code execution. This example +// uses the DSP2833x_CodeStartBranch.asm file to accomplish this. +// - Set boot mode Jumpers to "boot to Flash" +// - For best performance from the flash, modify the waitstates +// and enable the flash pipeline as shown in this example. +// Note: any code that manipulates the flash waitstate and pipeline +// control must be run from RAM. Thus these functions are located +// in their own memory section called ramfuncs. +// +// +// ePwm1 Interrupt will run from RAM and puts the flash into sleep mode +// ePwm2 Interrupt will run from RAM and puts the flash into standby mode +// ePWM3 Interrupt will run from FLASH +// +// As supplied: +// +// All timers have the same period +// The timers are started sync'ed +// An interrupt is taken on a zero event for each ePWM timer +// +// ePWM1: takes an interrupt every event +// ePWM2: takes an interrupt every 2nd event +// ePWM3: takes an interrupt every 3rd event +// +// Thus the Interrupt count for ePWM1, ePWM4-ePWM6 should be equal +// The interrupt count for ePWM2 should be about half that of ePWM1 +// and the interrupt count for ePWM3 should be about 1/3 that of ePWM1 +// +// Watch Variables: +// EPwm1TimerIntCount +// EPwm2TimerIntCount +// EPwm3TimerIntCount +// +// Toggle GPIO32 while in the background loop. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Configure which ePWM timer interrupts are enabled at the PIE level: +// 1 = enabled, 0 = disabled +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 + +// Configure the period for each timer +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF + +// Make this long enough so that we can see an LED toggle +#define DELAY 1000000L + +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped using +// the linker cmd file. +#pragma CODE_SECTION(epwm1_timer_isr, "ramfuncs"); +#pragma CODE_SECTION(epwm2_timer_isr, "ramfuncs"); + +// Prototype statements for functions found within this file. +interrupt void epwm1_timer_isr(void); +interrupt void epwm2_timer_isr(void); +interrupt void epwm3_timer_isr(void); +void InitEPwmTimer(void); + +// Global variables used in this example +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 LoopCount; + +// These are defined by the linker (see F28335.cmd) +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + +// Step 5. User specific code, enable interrupts: + +// Copy time critical code and Flash setup code to RAM +// This includes the following ISR functions: epwm1_timer_isr(), epwm2_timer_isr() +// epwm3_timer_isr and and InitFlash(); +// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart +// symbols are created by the linker. Refer to the F28335.cmd file. + MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); + +// Call Flash Initialization to setup flash waitstates +// This function must reside in RAM + InitFlash(); + +// Initalize counters: + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + LoopCount = 0; + +// Enable CPU INT3 which is connected to EPWM1-3 INT: + IER |= M_INT3; + +// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + EDIS; + + for(;;) + { + // This loop will be interrupted, so the overall + // delay between pin toggles will be longer. + DELAY_US(DELAY); + LoopCount++; + GpioDataRegs.GPBTOGGLE.bit.GPIO32 = 1; + } + +} + + +void InitEPwmTimer() +{ + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // Setup Sync + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // Allow each timer to be sync'ed + + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; + + +} + +// This ISR MUST be executed from RAM as it will put the Flash into Sleep +// Interrupt routines uses in this example: +interrupt void epwm1_timer_isr(void) +{ + + // Put the Flash to sleep + FlashRegs.FPWR.bit.PWR = FLASH_SLEEP; + + EPwm1TimerIntCount++; + + // Clear INT flag for this timer + EPwm1Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// This ISR MUST be executed from RAM as it will put the Flash into Standby +interrupt void epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // Put the Flash into standby + FlashRegs.FPWR.bit.PWR = FLASH_STANDBY; + + // Clear INT flag for this timer + EPwm2Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +interrupt void epwm3_timer_isr(void) +{ + Uint16 i; + + EPwm3TimerIntCount++; + + // Short Delay to simulate some ISR Code + for(i = 1; i < 0x01FF; i++) {} + + // Clear INT flag for this timer + EPwm3Regs.ETCLR.bit.INT = 1; + + // Acknowledge this interrupt to receive more interrupts from group 3 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + + + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU.c b/v120/DSP2833x_examples/fpu/Example_2833xFPU.c new file mode 100644 index 0000000..66654f2 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU.c @@ -0,0 +1,167 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 21, 2008 15:44:31 $ +//########################################################################### +// +// FILE: Example_2833xFPU.c +// +// TITLE: DSP2833x Device Getting Started Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Other then boot mode configuration, no other hardware configuration +// is required. +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// The code calculates two y=mx+b equations. The variables are all +// 32-bit floating-point. +// +// Two projects are supplied: +// +// Example_fpu_hardware.pjt (floating-point): +// +// If the Example_2833xFPU_hardware.pjt file is used then the compiler +// will generate floating point instructions to do these calculations. +// To compile the project for floating point, the following Build Options were used: +// 1. Project->Build Options-> Compiler Tab-> Advanced category: +// a. in textbox: compiler options -v28 --float_support=fpu32 are set +// b. OR the following is equivalent to "a.": pull-down menu next to +// "Floating Point Support"-> "fpu32" selected. +// 2. Project->Build Options-> Linker Tab-> Libraries category: +// a. runtime support library used is rts2800_fpu32.lib. +// 3. Not included in this example: If the project includes any other libraries, +// they must also be compiled with floating point instructions. +// +// Example_fpu_software.pjt (fixed-point emulates floating-point with software): +// +// If the Example_2833xFPU_software.pjt file is used, then the compiler +// will only used fixed point instructions. This means the runtime +// support library will be used to emulate floating point. +// This will also run on C28x devices without the floating point unit. +// To compile the project for fixed point, the following Build Options were used: +// 1. Project->Build Options-> Compiler Tab-> Advanced category: +// a. in textbox: compiler option --float_support=fpu32 is REMOVED +// -v28 should not be removed +// b. OR the following is equivalent to "a.": pull-down menu next to +// "Floating Point Support"-> "None" selected. +// 2. Project->Build Options-> Linker Tab-> Libraries category: +// a. runtime support library used is rts2800.lib or rts2800_ml.lib. +// 3. Not included in this example: If the project includes any other libraries, +// they must also be compiled with fixed point instructions. +// +// Watch Variables: +// y1 +// y2 +// FPU registers (optional) +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +float y1, y2; +float m1, m2; +float x1, x2; +float b1, b2; + + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + + +// Step 5. User specific code, enable interrupts: + +// +// Calculate two y=mx+b equations. + + y1 = 0; + y2 = 0; + m1 = .5; + m2 = .6; + x1 = 3.4; + x2 = 7.3; + b1 = 4.2; + b2 = 8.9; + + y1 = m1*x1 + b1; + y2 = m2*x2 + b2; + + + ESTOP0; // This is a software breakpoint +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel b/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel new file mode 100644 index 0000000..b6531eb --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU.gel @@ -0,0 +1,50 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: August 29, 2007 14:07:24 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x FPU Example" + +hotmenu Load_and_Build_Fixed_Point_Project() +{ + GEL_ProjectLoad("Example_2833xFPU_software.pjt"); + GEL_ProjectBuild("Example_2833xFPU_software.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_and_Build_Floating_Point_Project() +{ + GEL_ProjectLoad("Example_2833xFPU_hardware.pjt"); + GEL_ProjectBuild("Example_2833xFPU_hardware.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Fixed_Point_Code() +{ + GEL_Load(".\\debug\\Example_2833xFPU_software.out"); + Setup_WatchWindow(); +} + +hotmenu Load_Floating_Point_Code() +{ + GEL_Load(".\\debug\\Example_2833xFPU_hardware.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("y1,f"); + GEL_WatchAdd("y2,f"); + All_FPU_Single_Precision_Regs(); +} diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt b/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt new file mode 100644 index 0000000..863f8f7 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU_hardware.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFPU.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -al -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xFPU_hardware.map" -o".\Debug\Example_2833xFPU_hardware.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFPU_hardware.out" -x + diff --git a/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt b/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt new file mode 100644 index 0000000..c4cdc70 --- /dev/null +++ b/v120/DSP2833x_examples/fpu/Example_2833xFPU_software.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xFPU.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\fpu\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xFPU_software.map" -o".\Debug\Example_2833xFPU_software.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_ml.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xFPU_software.out" -x + diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c new file mode 100644 index 0000000..ff9c488 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.c @@ -0,0 +1,458 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:42:38 $ +//########################################################################### +// +// FILE: Example_2833xGpioSetup.c +// +// TITLE: DSP2833x Device GPIO Setup +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Two different examples are included. Select the example +// to execute before compiling using the #define statements +// found at the top of the code. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// Configures the 2833x GPIO into two different configurations +// This code is verbose to illustrate how the GPIO could be setup. +// In a real application, lines of code can be combined for improved +// code size and efficency. +// +// This example only sets-up the GPIO.. nothing is actually done with +// the pins after setup. +// +// In general: +// +// All pullup resistors are enabled. For ePWMs this may not be desired. +// Input qual for communication ports (eCAN, SPI, SCI, I2C) is asynchronous +// Input qual for Trip pins (TZ) is asynchronous +// Input qual for eCAP and eQEP signals is synch to SYSCLKOUT +// Input qual for some I/O's and interrupts may have a sampling window +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Select the example to compile in. Only one example should be set as 1 +// the rest should be set as 0. + +#define EXAMPLE1 1 // Basic pinout configuration example +#define EXAMPLE2 0 // Communication pinout example + +// Prototype statements for functions found within this file. +void Gpio_setup1(void); +void Gpio_setup2(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. + // InitGpio(); Skipped for this example + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + +#if EXAMPLE1 + + // This example is a basic pinout + Gpio_setup1(); + +#endif // - EXAMPLE1 + +#if EXAMPLE2 + + // This example is a communications pinout + Gpio_setup2(); + +#endif + +} + + +void Gpio_setup1(void) +{ + // Example 1: + // Basic Pinout. + // This basic pinout includes: + // PWM1-3, ECAP1, ECAP2, TZ1-TZ4, SPI-A, EQEP1, SCI-A, I2C + // and a number of I/O pins + + // These can be combined into single statements for improved + // code efficiency. + + // Enable PWM1-3 on GPIO0-GPIO5 + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // Enable an GPIO output on GPIO6, set it high + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // Enable eCAP1 on GPIO7 + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // Enable GPIO outputs on GPIO8 - GPIO11, set it high + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // Enable Trip Zone inputs on GPIO12 - GPIO15 + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13 + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // GPIO12 = TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // GPIO13 = TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // GPIO14 = TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // GPIO15 = TZ4 + + // Enable SPI-A on GPIO16 - GPIO19 + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // Enable EQEP1 on GPIO20 - GPIO23 + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // Enable eCAP1 on GPIO24 + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // Set input qualifcation period for GPIO25 & GPIO26 + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=2; // 6 samples + + // Make GPIO25 the input source for Xint1 + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // Make GPIO26 the input source for XINT2 + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; // Qualify GPIO27 by 2 OSCCLK + // cycles before waking the device + // from STANDBY + + // Enable SCI-A on GPIO28 - GPIO29 + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // Enable CAN-A on GPIO30 - GPIO31 + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + + // Enable I2C-A on GPIO32 - GPIO33 + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // Make GPIO34 an input + GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + EDIS; +} + +void Gpio_setup2(void) +{ + // Example 1: + // Communications Pinout. + // This basic communications pinout includes: + // PWM1-3, CAP1, CAP2, SPI-A, SPI-B, CAN-A, SCI-A and I2C + // and a number of I/O pins + + // Enable PWM1-3 on GPIO0-GPIO5 + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // Enable an GPIO output on GPIO6 + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // Enable eCAP1 on GPIO7 + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // Enable GPIO outputs on GPIO8 - GPIO11 + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioDataRegs.GPASET.bit.GPIO11 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // Enable SPI-B on GPIO12 - GPIO15 + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 (SPISIMOB) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO13 (SPISOMIB) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 (SPICLKB) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 (SPISTEB) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 = SPISIMOB + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 = SPISOMIB + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 = SPICLKB + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 = SPISTEB + + // Enable SPI-A on GPIO16 - GPIO19 + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 (SPIS0MIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 (SPISTEA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // Enable EQEP1 on GPIO20 - GPIO23 + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 (EQEP1I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // Enable eCAP1 on GPIO24 + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 (ECAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // Set input qualifcation period for GPIO25 & GPIO26 inputs + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=1; // 3 samples + + // Make GPIO25 the input source for Xint1 + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // Make GPIO26 the input source for XINT2 + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; // Qualify GPIO27 by 2 OSCCLK + // cycles before waking the device + // from STANDBY + + // Enable SCI-A on GPIO28 - GPIO29 + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // Enable CAN-A on GPIO30 - GPIO31 + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + // Enable I2C-A on GPIO32 - GPIO33 + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // Make GPIO34 an input + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + + EDIS; +} + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel new file mode 100644 index 0000000..84616d3 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.gel @@ -0,0 +1,35 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:35 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x GPIO Setup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xGpioSetup.pjt"); + GEL_ProjectBuild("Example_2833xGpioSetup.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xGpioSetup.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd(" GpioCtrlRegs,x"); +} diff --git a/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt new file mode 100644 index 0000000..246125c --- /dev/null +++ b/v120/DSP2833x_examples/gpio_setup/Example_2833xGpioSetup.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xGpioSetup.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_setup\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xGpioSetup.map" -o".\Debug\Example_2833xGpioSetup.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xGpioToggle.out" -x + diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c new file mode 100644 index 0000000..017a1f7 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.c @@ -0,0 +1,245 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 21, 2008 15:42:43 $ +//########################################################################### +// +// FILE: Example_2833xGpioToggle.c +// +// TITLE: DSP2833x Device GPIO toggle test program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// ALL OF THE I/O'S TOGGLE IN THIS PROGRAM. MAKE SURE +// THIS WILL NOT DAMAGE YOUR HARDWARE BEFORE RUNNING THIS +// EXAMPLE. +// +// Monitor desired pins on an oscilloscope. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Three different examples are included. Select the example +// (data, set/clear or toggle) to execute before compiling using +// the #define statements found at the top of the code. +// +// +// Toggle all of the GPIO PORT pins +// +// The pins can be observed using Oscilloscope. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Select the example to compile in. Only one example should be set as 1 +// the rest should be set as 0. +#define EXAMPLE1 1 // Use DATA registers to toggle I/O's +#define EXAMPLE2 0 // Use SET/CLEAR registers to toggle I/O's +#define EXAMPLE3 0 // Use TOGGLE registers to toggle I/O's + + +// Prototype statements for functions found within this file. +void delay_loop(void); +void Gpio_select(void); +void Gpio_example1(void); +void Gpio_example2(void); +void Gpio_example3(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + +// For this example use the following configuration: + Gpio_select(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + +#if EXAMPLE1 + + // This example uses DATA registers to toggle I/O's + Gpio_example1(); + +#endif // - EXAMPLE1 + +#if EXAMPLE2 + + // This example uses SET/CLEAR registers to toggle I/O's + Gpio_example2(); + +#endif + +#if EXAMPLE3 + + // This example uses TOGGLE registers to toggle I/O's + Gpio_example3(); + +#endif + +} + +void delay_loop() +{ + short i; + for (i = 0; i < 1000; i++) {} +} + + +void Gpio_example1(void) +{ + // Example 1: + // Toggle I/Os using DATA registers + + for(;;) + { + GpioDataRegs.GPADAT.all =0xAAAAAAAA; + GpioDataRegs.GPBDAT.all =0x0000000A; + + delay_loop(); + + GpioDataRegs.GPADAT.all =0x55555555; + GpioDataRegs.GPBDAT.all =0x00000005; + + delay_loop(); + } +} + +void Gpio_example2(void) +{ + // Example 2: + // Toggle I/Os using SET/CLEAR registers + for(;;) + { + + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + delay_loop(); + + GpioDataRegs.GPACLEAR.all =0xAAAAAAAA; + GpioDataRegs.GPASET.all =0x55555555; + + GpioDataRegs.GPBCLEAR.all =0x0000000A; + GpioDataRegs.GPBSET.all =0x00000005; + + delay_loop(); + + } +} + +void Gpio_example3(void) +{ + // Example 2: + // Toggle I/Os using TOGGLE registers + + // Set pins to a known state + + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + // Use TOGGLE registers to flip the state of + // the pins. + // Any bit set to a 1 will flip state (toggle) + // Any bit set to a 0 will not toggle. + + for(;;) + { + GpioDataRegs.GPATOGGLE.all =0xFFFFFFFF; + GpioDataRegs.GPBTOGGLE.all =0x0000000F; + delay_loop(); + } +} + + + +void Gpio_select(void) +{ + + + EALLOW; + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX2.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + GpioCtrlRegs.GPBDIR.all = 0x0000000F; // All outputs + EDIS; + +} +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel new file mode 100644 index 0000000..5e49d74 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.gel @@ -0,0 +1,36 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:16:50 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x GPIO Toggle Test" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xGpioToggle.pjt"); + GEL_ProjectBuild("Example_2833xGpioToggle.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xGpioToggle.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("GpioDataRegs,x"); + GEL_WatchAdd("GpioCtrlRegs,x"); +} diff --git a/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt new file mode 100644 index 0000000..ae80e72 --- /dev/null +++ b/v120/DSP2833x_examples/gpio_toggle/Example_2833xGpioToggle.pjt @@ -0,0 +1,44 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xGpioToggle.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\gpio_toggle\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xGpioToggle.map" -o".\Debug\Example_2833xGpioToggle.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xGpioToggle.out" -x + diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c new file mode 100644 index 0000000..66c2b43 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.c @@ -0,0 +1,376 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: May 5, 2008 15:25:53 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM.c +// +// TITLE: DSP2833x Device HRPWM example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module +// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine edge movement +// due to HRPWM logic +// +// 1. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1A toggle low/high with MEP control on rising edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1B toggle low/high with NO HRPWM control +// +// 2. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2A toggle low/high with MEP control on rising edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2B toggle low/high with NO HRPWM control +// +// 3. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3A toggle as high/low with MEP control on falling edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3B toggle low/high with NO HRPWM control +// +// 4. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4A toggle as high/low with MEP control on falling edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4B toggle low/high with NO HRPWM control +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + + +// Declare your function prototypes here +//--------------------------------------------------------------- + +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// General System nets - Useful for debug +Uint16 i,j, DutyFine, n,update; + +Uint32 temp; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(10); // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(20); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(10); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(20); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + + { + + for(DutyFine =1; DutyFine <256 ;DutyFine ++) + { + + // Example, write to the HRPWM extension of CMPA + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + + // Example, 32-bit write to CMPA:CMPAHR + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + + for (i=0;i<10000;i++){} // Dummy delay between MEP changes + } + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm2Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel new file mode 100644 index 0000000..5ccf383 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.gel @@ -0,0 +1,42 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:09 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM.out"); + Setup_WatchWindow(); +} + + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("DutyFine,x"); + GEL_WatchAdd("update,x"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + +} diff --git a/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt new file mode 100644 index 0000000..b92acda --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm/Example_2833xHRPWM.pjt @@ -0,0 +1,51 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -cr -ecode_start -m".\Debug\Example_2833xHRPWM.map" -o".\Debug\Example_2833xHRPWM.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c new file mode 100644 index 0000000..9e092f6 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c @@ -0,0 +1,546 @@ +// TI File $Revision: /main/15 $ +// Checkin $Date: May 5, 2008 15:25:56 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO.c +// +// TITLE: DSP2833x Device HRPWM example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files, which include the +// SFO_TI_Build_fpu.lib (or SFO_TI_Build.lib for fixed-point) and SFO.h +// files required by this example. +// +// !!NOTE!! +// By default, this example project is configured for floating-point math. All +// included libraries must be pre-compiled for floating-point math. +// +// Therefore, SFO_TI_Build_fpu.lib (compiled for floating-point) is included in the +// project instead of the SFO_TI_Build.lib (compiled for fixed-point). +// +// To convert the example for fixed-point math, follow the instructions in sfo_readme.txt +// in the /doc directory of the header files and peripheral examples package. +// +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM2A is on GPIO2 +// EPWM3A is on GPIO4 +// EPWM4A is on GPIO6 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module. +// +// This example calls the following TI's MEP Scale Factor Optimizer (SFO) +// software library functions: +// +// void SFO_MepEn(int i); +// initialize MEP_Scalefactor[i] dynamically when HRPWM is in use. +// +// void SFO_MepDis(int i); +// initialize MEP_Scalefactor[i] when HRPWM is not used +// +// Where MEP_ScaleFactor[5] is a global array variable used by the SFO library +// +// This example is intended to explain the HRPWM capabilities. The code can be +// optimized for code efficiency. Refer to TI's Digital power application +// examples and TI Digital Power Supply software libraries for details. +// +// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine +// edge movement due to the HRPWM logic +// +// 1. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz), ePWM1A toggle low/high with MEP control on falling edge +// +// 2. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM2A toggle low/high with MEP control on falling edge +// +// 3. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM3A toggle high/low with MEP control on falling edge +// +// 4. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM4A toggle high/low with MEP control on falling edge +// +// To load and run this example: +// 1. Run this example at 150MHz SYSCLKOUT (or 100 MHz SYSCLKOUT for 100 MHz devices) +// 2. Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch window +// 3. Activate Real time mode +// 4. Run the code +// 5. Watch ePWM1A-4A waveforms on a Oscillosope +// 6. In the watch window: +// Set the variable UpdateFine = 1 to observe the ePWMxA output +// with HRPWM capabilites (default) +// Observe the duty cycle of the waveform changes in fine MEP steps +// 7. In the watch window: +// Change the variable UpdateFine to 0, to observe the +// ePWMxA output without HRPWM capabilites +// Observe the duty cycle of the waveform changes in coarse steps of 10nsec. +// +// +// Watch Variables: +// UpdateFine +// MEP_ScaleFactor +// EPwm1Regs.CMPA.all +// EPwm2Regs.CMPA.all +// EPwm3Regs.CMPA.all +// EPwm4Regs.CMPA.all +// +// +// IMPORTANT NOTE!!!!! +// +// THE SFO.H FUNCTIONS INCLUDED WITH THIS EXAMPLE ONLY SUPPORTS EPWM1-EPWM4. FOR +// SUPPORT FOR MORE THAN 4 EPWMS, USE SFO_V5.H WITH THE SFO_TI_BUILD_V5.LIB LIBRARY. +// SEE THE HRPWM REFERENCE GUIDE (SPRU924) FOR USAGE INFORMATION AND DIFFERENCES +// BETWEEN VERSIONS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization +#include "SFO.h" // SFO library headerfile + +// Declare your function prototypes here +//--------------------------------------------------------------- +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + + +// General System nets - Useful for debug +Uint16 j,duty, DutyFine, n, UpdateFine; +volatile int i; +Uint32 temp; + +// Global array used by the SFO library +int16 MEP_ScaleFactor[5]; + + +volatile struct EPWM_REGS *ePWM[] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; + + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + UpdateFine = 1; + DutyFine = 0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// MEP_ScaleFactor variables iitialization for SFO library functions + MEP_ScaleFactor[0] = 0; //Common Variables for SFO functions + MEP_ScaleFactor[1] = 0; //SFO for HRPWM1 + MEP_ScaleFactor[2] = 0; //SFO for HRPWM2 + MEP_ScaleFactor[3] = 0; //SFO for HRPWM3 + MEP_ScaleFactor[4] = 0; //SFO for HRPWM4 + +// MEP_ScaleFactor variables initialized using function SFO_MepDis + while ( MEP_ScaleFactor[1] == 0 ) SFO_MepDis(1); //SFO for HRPWM1 + while ( MEP_ScaleFactor[2] == 0 ) SFO_MepDis(2); //SFO for HRPWM2 + while ( MEP_ScaleFactor[3] == 0 ) SFO_MepDis(3); //SFO for HRPWM3 + while ( MEP_ScaleFactor[4] == 0 ) SFO_MepDis(4); //SFO for HRPWM4 + +// Initialize a common seed variable MEP_ScaleFactor[0] required for all SFO functions + MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; //Common Variable for SFO library functions + +/// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 30 5.0 MHz 3.33 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(30); // ePWM1 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(30); // ePWM2 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(30); // ePWM3 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(30); // ePWM4 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + + EDIS; + + for(;;) + { + // Sweep DutyFine as a Q15 number from 0.2 - 0.999 + for(DutyFine = 0x2300; DutyFine < 0x7000; DutyFine++) + { + // Variables + int16 CMPA_reg_val, CMPAHR_reg_val; + int32 temp; + + if(UpdateFine) + { + /* + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // Add the offset and rounding + CMPAHR_reg_val += 0x0180; + + // Write the values to the registers as one 32-bit or two 16-bits + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + */ + + // All the above operations may be condensed into + // the following form: + // EPWM1 calculations + + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // Example for a 32 bit write to CMPA:CMPAHR + EPwm1Regs.CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val; + + + // EPWM2 calculations + CMPA_reg_val = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm2Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[2])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + // Example as a 16 bit write to CMPA and then a 16-bit write to CMPAHR + EPwm2Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm2Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // EPWM3 calculations + CMPA_reg_val = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm3Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[3])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm3Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm3Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // EPWM4 calculations + CMPA_reg_val = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm4Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[4])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm4Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm4Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + } + else + { + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + EPwm1Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm1Regs.TBPRD>>15); + EPwm2Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + EPwm3Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + EPwm4Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + + } + + + for (i=0;i<300;i++) + { + // Call the scale factor optimizer lib + SFO_MepEn(1); + SFO_MepEn(2); + SFO_MepEn(3); + SFO_MepEn(4); + + } + + + } + + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// No more diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel new file mode 100644 index 0000000..520f385 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.gel @@ -0,0 +1,54 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:23 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +//########################################################################### +// Test Description: Run this GEL on F28335 or F2801. +// The Watch window should give a Scale factor value of 67-70 for the HRPWM +// modules in the device. F28335/6 will have four entries. F2801 will have three +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM SFO" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_SFO.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_SFO.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_SFO.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("UpdateFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("MEP_ScaleFactor[1]"); + GEL_WatchAdd("MEP_ScaleFactor[2]"); + GEL_WatchAdd("MEP_ScaleFactor[3]"); + GEL_WatchAdd("MEP_ScaleFactor[4]"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); +} diff --git a/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt new file mode 100644 index 0000000..ba907e6 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo/Example_2833xHRPWM_SFO.pjt @@ -0,0 +1,59 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\lib\SFO_TI_Build_fpu.lib" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_SFO.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -pdr -pdv -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHRPWM_SFO.map" -o".\Debug\Example_2833xHRPWM_SFO.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_SFO.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c new file mode 100644 index 0000000..6635f1c --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c @@ -0,0 +1,477 @@ +// TI File $Revision: /main/14 $ +// Checkin $Date: June 23, 2008 08:58:36 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO_V5.c +// +// TITLE: DSP2833x Device HRPWM SFO V5 example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files, which include +// the following files required for this example: +// SFO_V5.h and SFO_TI_Build_V5B_fpu.lib (or SFO_TI_Build_V5B.lib for fixed point) +// +// +// !!NOTE!! +// By default, this example project is configured for floating-point math. All included libraries +// must be pre-compiled for floating-point math. +// +// Therefore, SFO_TI_Build_V5B_fpu.lib (compiled for floating-point) is included in the +// project instead of the SFO_TI_Build_V5B.lib (compiled for fixed-point). +// +// To convert the example for fixed-point math, follow the instructions in sfo_readme.txt +// in the /doc directory of the header files and peripheral examples package. +// +// +// Monitor the following pins on an oscilloscope: +// ePWM1A (GPIO0) +// ePWM2A (GPIO2) +// ePWM3A (GPIO4) +// ePWM4A (GPIO6) +// ePWM5A (GPIO8) +// ePWM6A (GPIO10) +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example modifies the MEP control registers to show edge displacement +// due to the HRPWM control extension of the respective ePWM module. +// +// This example calls the following TI's MEP Scale Factor Optimizer (SFO) +// software library V5 functions: +// +// +// int SFO_MepEn_V5(int i); +// updates MEP_ScaleFactor[i] dynamically when HRPWM is in use. +// - returns 1 when complete for the specified channel +// - returns 0 if not complete for the specified channel +// - returns 2 if there is a scale factor out-of-range error +// (MEP_ScaleFactor[n] differs from seed MEP_ScaleFactor[0] +// by more than +/-15). To remedy this: +// 1. Check your software to make sure MepEn completes for +// 1 channel before calling MepEn for another channel. +// 2. Re-run MepDis and re-seed MEP_ScaleFactor[0]. Then +// try again. +// 3. If reason is known and acceptable, treat return of "2" +// like a return of "1", indicating calibration complete. +// +// int SFO_MepDis_V5(int i); +// updates MEP_ScaleFactor[i] when HRPWM is not used +// - returns 1 when complete for the specified channel +// - returns 0 if not complete for the specified channel +// +// MEP_ScaleFactor[PWM_CH] is a global array variable used by the SFO library +// +// ======================================================================= +// NOTE: For more information on using the SFO software library, see the +// High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (spru924) +// ======================================================================= +// +// This example is intended to explain the HRPWM capabilities. The code can be +// optimized for code efficiency. Refer to TI's Digital power application +// examples and TI Digital Power Supply software libraries for details. +// +// All ePWM1A-6A channels will have fine +// edge movement due to the HRPWM logic +// +// 5MHz PWM (for 150 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP control on rising edge +// 3.33MHz PWM (for 100 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP control on rising edge +// +// To load and run this example: +// 1. **!!IMPORTANT!!** - in SFO_V5.h, set PWM_CH to the max number of +// HRPWM channels plus one. For example, for the F28335, the +// maximum number of HRPWM channels is 6. 6+1=7, so set +// #define PWM_CH 7 in SFO_V5.h. (Default is 7) +// 2. Run this example at 150/100MHz SYSCLKOUT +// 3. Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch window +// 4. Activate Real time mode +// 5. Run the code +// 6. Watch ePWM1-6 waveforms on a Oscillosope +// 7. In the watch window: +// Set the variable UpdateFine = 1 to observe the ePWMxA output +// with HRPWM capabilites (default) +// Observe the duty cycle of the waveform changes in fine MEP steps +// 8. In the watch window: +// Change the variable UpdateFine to 0, to observe the +// ePWMxA output without HRPWM capabilites +// Observe the duty cycle of the waveform changes in coarse steps of 10nsec. +// +// Watch Variables: +// UpdateFine +// MEP_ScaleFactor +// EPwm1Regs.CMPA.all +// EPwm2Regs.CMPA.all +// EPwm3Regs.CMPA.all +// EPwm4Regs.CMPA.all +// EPwm5Regs.CMPA.all +// EPwm6Regs.CMPA.all +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization +#include "SFO_V5.h" // SFO V5 library headerfile - required to use SFO library functions + +// **!!IMPORTANT!!** +// UPDATE NUMBER OF HRPWM CHANNELS + 1 USED IN SFO_V5.H +// i.e. #define PWM_CH // F28335 has a maximum of 6 HRPWM channels (7=6+1) + +// Declare your function prototypes here +//--------------------------------------------------------------- +void HRPWM_Config(int); +void error (void); + +// General System nets - Useful for debug +Uint16 UpdateFine, DutyFine, status, nMepChannel; + +//==================================================================== +// The following declarations are required in order to use the SFO +// library functions: +// +int MEP_ScaleFactor[PWM_CH]; // Global array used by the SFO library + // For n HRPWM channels + 1 for MEP_ScaleFactor[0] + +// Array of pointers to EPwm register structures: +// *ePWM[0] is defined as dummy value not used in the example +volatile struct EPWM_REGS *ePWM[PWM_CH] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; +//==================================================================== + +void main(void) +{ + // Local variables + int i; + Uint32 temp; + int16 CMPA_reg_val, CMPAHR_reg_val; + + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// For this case just init GPIO pins for ePWM1-ePWM6 +// This function is in the DSP2833x_EPwm.c file + InitEPwmGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + UpdateFine = 1; + DutyFine = 0; + nMepChannel=1; // HRPWM diagnostics start on ePWM channel 1 + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// MEP_ScaleFactor variables intialization for SFO library functions + for(i=0;i>15; + + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // Add the offset and rounding + CMPAHR_reg_val += 0x0180; + + // Write the values to the registers as one 32-bit or two 16-bits + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + */ + + // All the above operations may be condensed into + // the following form for each channel: + + // EPWM calculations where EPwm1Regs are accessed + // by (*ePWM[1]), EPwm2Regs are accessed by (*ePWM[2]), + // etc.: + + for(i=1;i>15; + temp = ((long)DutyFine * (*ePWM[i]).TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[i])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // Example for a 32 bit write to CMPA:CMPAHR + (*ePWM[i]).CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val; + } + + } + else + { + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + + for(i=1;i>15); + } + } + + +// Call the scale factor optimizer lib function SFO_MepEn_V5() +// periodically to track for any changes due to temp/voltage. +// SFO_MepEn_V5 Calibration must be finished on one channel (return 1) before +// moving on to the next channel. +// +// *NOTE*: In this example, SFO_MepEn_V5 is called 700 times in a loop. For example +// purposes, this allows the CMPAHR and CMPA registers to change in such +// a way that when watching in "Continuous Refresh" mode, the user +// can see the CMPAHR register increment in fine steps to a certain point +// before the CMPA register increments in a coarse step. Normally, +// SFO_MepEn_V5 can be called once every so often in the background for +// a slow update with no for-loop. + + for (i=0; i<700; i++) // Call SFO_MepEn_V5 700 times. + { + status = SFO_MepEn_V5(nMepChannel); + if (status == SFO_COMPLETE) // Once SFO_MepEn_V5 complete (returns 1)- + nMepChannel++; // move on to next channel + else if (status == SFO_OUTRANGE_ERROR) // If MEP_ScaleFactor[nMepChannel] differs + { // from seed Mep_ScaleFactor[0] by more than + error(); // +/-15, status = 2 (out of range error) + } + if(nMepChannel==PWM_CH) + nMepChannel =1; // Once max channels reached, loop back to channel 1 + } + + } // end DutyFine for loop + + } // end infinite for loop + +} // end SFO_MepEn_V5 + +//============================================================= +// FUNCTION: HRPWM_Config +// DESCRIPTION: Configures all ePWM channels and sets up HRPWM +// on ePWMxA channels +// +// PARAMETERS: period - desired PWM period in TBCLK counts +// RETURN: N/A +//============================================================= + +void HRPWM_Config(period) +{ +Uint16 j; +// ePWM channel register configuration with HRPWM +// ePWMxA toggle low/high with MEP control on Rising edge + for (j=1;j +/- 15 +// from the Seed Value in MEP_ScaleFactor[0]. +// SFO_MepEn_V5 returned a "2" (SFO_OUTRANGE_ERROR). +// The user should: +// (1) Re-run SFO_MepDis_V5 to re-calibrate +// an appropriate seed value. +// (2) Ensure the code is not calling Mep_En_V5 +// on a different channel when it is currently +// still running on a channel. (Repetitively +// call Mep_En_V5 on current channel until an +// SFO_COMPLETE ( i.e. 1) is returned. +// (3) If the out-of-range condition is acceptable +// for the application, ignore the "2" and +// treat it as a "1" or SFO_COMPLETE. +// +// PARAMETERS: N/A +// RETURN: N/A +//============================================================= + +void error (void) +{ + ESTOP0; // Error - MEP_ScaleFactor out of range of Seed - rerun MepDis calibration. +} + + +// No more + diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel new file mode 100644 index 0000000..d76daae --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.gel @@ -0,0 +1,58 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:25:04 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +//########################################################################### +// Test Description: Run this GEL on F28334 +// The Watch window should give a Scale factor value of 67-70 for the HRPWM +// modules in the device. F28335 will have a maximum of 6 entries + 1 for +// MEP_ScaleFactor[0]. +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM SFO V5" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_SFO_V5.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_SFO_V5.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_SFO_V5.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("UpdateFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("EPwm5Regs.CMPA.all"); + GEL_WatchAdd("EPwm6Regs.CMPA.all"); + GEL_WatchAdd("MEP_ScaleFactor"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); + GEL_WatchAdd("EPwm5Regs,x"); + GEL_WatchAdd("EPwm6Regs,x"); + + +} diff --git a/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt new file mode 100644 index 0000000..45731df --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.pjt @@ -0,0 +1,53 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\lib\SFO_TI_Build_V5B_fpu.lib" +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_SFO_V5.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -pdv -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_sfo_v5\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHRPWM_SFO_V5.map" -o".\Debug\Example_2833xHRPWM_SFO_V5.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_SFO_V5.out" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c new file mode 100644 index 0000000..ba2dd87 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.c @@ -0,0 +1,381 @@ +// TI File $Revision: /main/13 $ +// Checkin $Date: May 5, 2008 15:26:01 $ +//########################################################################### +// +// FILE: Example_2833xHRPWM_slider.c +// +// TITLE: DSP2833x Device HRPWM with Slider example +// +// ASSUMPTIONS: +// +// +// This program requires the DSP2833x header files. +// +// Monitor ePWM1-ePWM4 pins on an oscilloscope as described +// below. +// +// EPWM1A is on GPIO0 +// EPWM1B is on GPIO1 +// +// EPWM2A is on GPIO2 +// EPWM2B is on GPIO3 +// +// EPWM3A is on GPIO4 +// EPWM3B is on GPIO5 +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// This example modifies the MEP control registers to show edge displacement +// due to HRPWM control blocks of the respective ePWM module, ePWM1A, 2A, 3A, +// and 4A channels (GPIO0, GPIO2, GPIO4, and GPIO6) will have fine edge movement +// due to HRPWM logic. Load the Example_2833xHRPWM_slider.gel file. +// Select the HRPWM FineDutySlider from the GEL menu. A FineDuty slider +// graphics will show up in CCS. +// Load the program and run. Use the Slider to and observe the epwm edge displacement +// for each slider step change. This explains the MEP control on the ePWMxA channels +// +// 1. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1A toggle low/high with MEP control on rising edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM1B toggle low/high with NO HRPWM control +// +// 2. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2A toggle low/high with MEP control on rising edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM2B toggle low/high with NO HRPWM control +// +// 3. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3A toggle as high/low with MEP control on falling edge +// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT), +// ePWM3B toggle low/high with NO HRPWM control +// +// 4. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4A toggle as high/low with MEP control on falling edge +// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT), +// ePWM4B toggle low/high with NO HRPWM control +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + + +// Declare your function prototypes here +//--------------------------------------------------------------- + +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// General System nets - Useful for debug +Uint16 i,j, duty, DutyFine, n,update; + +Uint32 temp; + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this case, just init GPIO for ePWM1-ePWM4 + +// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 +// These functions are in the DSP2833x_EPwm.c file + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// For this example, only initialize the ePWM +// Step 5. User specific code, enable interrupts: + + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + +// Some useful Period vs Frequency values +// SYSCLKOUT = 150MHz 100 MHz +// ----------------------------------------- +// Period Frequency Frequency +// 1000 150 kHz 100 KHz +// 800 187 kHz 125 KHz +// 600 250 kHz 167 KHz +// 500 300 kHz 200 KHz +// 250 600 kHz 400 KHz +// 200 750 kHz 500 KHz +// 100 1.5 MHz 1.0 MHz +// 50 3.0 MHz 2.0 MHz +// 25 6.0 MHz 4.0 MHz +// 20 7.5 MHz 5.0 MHz +// 12 12.5 MHz 8.33 MHz +// 10 15.0 MHz 10.0 MHz +// 9 16.7 MHz 11.1 MHz +// 8 18.8 MHz 12.5 MHz +// 7 21.4 MHz 14.3 MHz +// 6 25.0 MHz 16.7 MHz +// 5 30.0 MHz 20.0 MHz + +//==================================================================== +// ePWM and HRPWM register initializaition +//==================================================================== + HRPWM1_Config(10); // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(20); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + HRPWM3_Config(10); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + HRPWM4_Config(20); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + + { + +// for(DutyFine =1; DutyFine <256 ;DutyFine ++) + { + + // Example, write to the HRPWM extension of CMPA + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits + + // Example, 32-bit write to CMPA:CMPAHR + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8); + +// for (i=0;i<10000;i++){} // Dummy delay between MEP changes + } + } + +} + + +void HRPWM1_Config(period) +{ +// ePWM1 register configuration with HRPWM +// ePWM1A toggle low/high with MEP control on Rising edge + + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM2_Config(period) +{ +// ePWM2 register configuration with HRPWM +// ePWM2A toggle low/high with MEP control on Rising edge + + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; + +} +void HRPWM3_Config(period) +{ +// ePWM3 register configuration with HRPWM +// ePWM3A toggle high/low with MEP control on falling edge + + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +void HRPWM4_Config(period) +{ +// ePWM4 register configuration with HRPWM +// ePWM4A toggle high/low with MEP control on falling edge + + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel new file mode 100644 index 0000000..0c5556a --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.gel @@ -0,0 +1,51 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:17:42 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM Slider" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHRPWM_slider.pjt"); + GEL_ProjectBuild("Example_2833xHRPWM_slider.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHRPWM_slider.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + + GEL_WatchReset(); + GEL_WatchAdd("DutyFine"); + GEL_WatchAdd("EPwm1Regs.CMPA.all"); + GEL_WatchAdd("EPwm2Regs.CMPA.all"); + GEL_WatchAdd("EPwm3Regs.CMPA.all"); + GEL_WatchAdd("EPwm4Regs.CMPA.all"); + GEL_WatchAdd("EPwm1Regs,x"); + GEL_WatchAdd("EPwm2Regs,x"); + GEL_WatchAdd("EPwm3Regs,x"); + GEL_WatchAdd("EPwm4Regs,x"); +} + +menuitem "DSP2833x HRPWM FineDutySlider" +slider FineDutySlider(1, 255, 1, 1, finedutyvalue) +{ + + DutyFine = finedutyvalue; +} diff --git a/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt new file mode 100644 index 0000000..dc610c8 --- /dev/null +++ b/v120/DSP2833x_examples/hrpwm_slider/Example_2833xHRPWM_slider.pjt @@ -0,0 +1,51 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_EPwm.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHRPWM_slider.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -k -q -al -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\hrpwm_slider\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -cr -ecode_start -m".\Debug\Example_2833xHRPWM_slider.map" -o".\Debug\Example_2833xHRPWM_slider.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHRPWM_slider" -x + +["..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c new file mode 100644 index 0000000..d602c08 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.c @@ -0,0 +1,473 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: April 21, 2008 15:43:02 $ +//########################################################################### +// +// FILE: Example_2833xI2c_eeprom.c +// +// TITLE: DSP2833x I2C EEPROM Example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// This program requires an external I2C EEPROM connected to +// the I2C bus at address 0x50. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program will write 1-14 words to EEPROM and read them back. +// The data written and the EEPROM address written to are contained +// in the message structure, I2cMsgOut1. The data read back will be +// contained in the message structure I2cMsgIn1. +// +// This program will work with the on-board I2C EEPROM supplied on +// the F2833x eZdsp. +// +// +//########################################################################### +// Original Author: D.F. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Note: I2C Macros used in this example can be found in the +// DSP2833x_I2C_defines.h file + +// Prototype statements for functions found within this file. +void I2CA_Init(void); +Uint16 I2CA_WriteData(struct I2CMSG *msg); +Uint16 I2CA_ReadData(struct I2CMSG *msg); +interrupt void i2c_int1a_isr(void); +void pass(void); +void fail(void); + +#define I2C_SLAVE_ADDR 0x50 +#define I2C_NUMBYTES 4 +#define I2C_EEPROM_HIGH_ADDR 0x00 +#define I2C_EEPROM_LOW_ADDR 0x30 + +// Global variables +// Two bytes will be used for the outgoing address, +// thus only setup 14 bytes maximum +struct I2CMSG I2cMsgOut1={I2C_MSGSTAT_SEND_WITHSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR, + 0x12, // Msg Byte 1 + 0x34, // Msg Byte 2 + 0x56, // Msg Byte 3 + 0x78, // Msg Byte 4 + 0x9A, // Msg Byte 5 + 0xBC, // Msg Byte 6 + 0xDE, // Msg Byte 7 + 0xF0, // Msg Byte 8 + 0x11, // Msg Byte 9 + 0x10, // Msg Byte 10 + 0x11, // Msg Byte 11 + 0x12, // Msg Byte 12 + 0x13, // Msg Byte 13 + 0x12}; // Msg Byte 14 + + +struct I2CMSG I2cMsgIn1={ I2C_MSGSTAT_SEND_NOSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR}; + +struct I2CMSG *CurrentMsgPtr; // Used in interrupts +Uint16 PassCount; +Uint16 FailCount; + +void main(void) +{ + Uint16 Error; + Uint16 i; + + CurrentMsgPtr = &I2cMsgOut1; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); +// Setup only the GP I/O only for I2C functionality + InitI2CGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.I2CINT1A = &i2c_int1a_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + I2CA_Init(); + +// Step 5. User specific code + + // Clear Counters + PassCount = 0; + FailCount = 0; + + // Clear incoming message buffer + for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++) + { + I2cMsgIn1.MsgBuffer[i] = 0x0000; + } + +// Enable interrupts required for this example + +// Enable I2C interrupt 1 in the PIE: Group 8 interrupt 1 + PieCtrlRegs.PIEIER8.bit.INTx1 = 1; + +// Enable CPU INT8 which is connected to PIE group 8 + IER |= M_INT8; + EINT; + + // Application loop + for(;;) + { + ////////////////////////////////// + // Write data to EEPROM section // + ////////////////////////////////// + + // Check the outgoing message to see if it should be sent. + // In this example it is initialized to send with a stop bit. + if(I2cMsgOut1.MsgStatus == I2C_MSGSTAT_SEND_WITHSTOP) + { + Error = I2CA_WriteData(&I2cMsgOut1); + // If communication is correctly initiated, set msg status to busy + // and update CurrentMsgPtr for the interrupt service routine. + // Otherwise, do nothing and try again next loop. Once message is + // initiated, the I2C interrupts will handle the rest. Search for + // ICINTR1A_ISR in the i2c_eeprom_isr.c file. + if (Error == I2C_SUCCESS) + { + CurrentMsgPtr = &I2cMsgOut1; + I2cMsgOut1.MsgStatus = I2C_MSGSTAT_WRITE_BUSY; + } + } // end of write section + + /////////////////////////////////// + // Read data from EEPROM section // + /////////////////////////////////// + + // Check outgoing message status. Bypass read section if status is + // not inactive. + if (I2cMsgOut1.MsgStatus == I2C_MSGSTAT_INACTIVE) + { + // Check incoming message status. + if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // EEPROM address setup portion + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // Maybe setup an attempt counter to break an infinite while + // loop. The EEPROM will send back a NACK while it is performing + // a write operation. Even though the write communique is + // complete at this point, the EEPROM could still be busy + // programming the data. Therefore, multiple attempts are + // necessary. + } + // Update current message pointer and message status + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_SEND_NOSTOP_BUSY; + } + + // Once message has progressed past setting up the internal address + // of the EEPROM, send a restart to read the data bytes from the + // EEPROM. Complete the communique with a stop bit. MsgStatus is + // updated in the interrupt service routine. + else if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_RESTART) + { + // Read data portion + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // Maybe setup an attempt counter to break an infinite while + // loop. + } + // Update current message pointer and message status + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_READ_BUSY; + } + } // end of read section + + } // end of for(;;) +} // end of main + + +void I2CA_Init(void) +{ + // Initialize I2C + I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code + + #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) + #endif + #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT + I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) + #endif + + I2caRegs.I2CCLKL = 10; // NOTE: must be non zero + I2caRegs.I2CCLKH = 5; // NOTE: must be non zero + I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts + + I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset + // Stop I2C when suspended + + I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO + I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT, + + return; +} + + +Uint16 I2CA_WriteData(struct I2CMSG *msg) +{ + Uint16 i; + + // Wait until the STP bit is cleared from any previous master communication. + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + // Setup slave address + I2caRegs.I2CSAR = msg->SlaveAddress; + + // Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + + // Setup number of bytes to send + // MsgBuffer + Address + I2caRegs.I2CCNT = msg->NumOfBytes+2; + + // Setup data to send + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; +// for (i=0; iNumOfBytes-2; i++) + for (i=0; iNumOfBytes; i++) + + { + I2caRegs.I2CDXR = *(msg->MsgBuffer+i); + } + + // Send start as master transmitter + I2caRegs.I2CMDR.all = 0x6E20; + + return I2C_SUCCESS; +} + + +Uint16 I2CA_ReadData(struct I2CMSG *msg) +{ + // Wait until the STP bit is cleared from any previous master communication. + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + I2caRegs.I2CSAR = msg->SlaveAddress; + + if(msg->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // Check if bus busy + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + I2caRegs.I2CCNT = 2; + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; + I2caRegs.I2CMDR.all = 0x2620; // Send data to setup EEPROM address + } + else if(msg->MsgStatus == I2C_MSGSTAT_RESTART) + { + I2caRegs.I2CCNT = msg->NumOfBytes; // Setup how many bytes to expect + I2caRegs.I2CMDR.all = 0x2C20; // Send restart as master receiver + } + + return I2C_SUCCESS; +} + +interrupt void i2c_int1a_isr(void) // I2C-A +{ + Uint16 IntSource, i; + + // Read interrupt source + IntSource = I2caRegs.I2CISRC.all; + + // Interrupt source = stop condition detected + if(IntSource == I2C_SCD_ISRC) + { + // If completed message was writing data, reset msg to inactive state + if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_WRITE_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + } + else + { + // If a message receives a NACK during the address setup portion of the + // EEPROM read, the code further below included in the register access ready + // interrupt source code will generate a stop condition. After the stop + // condition is received (here), set the message status to try again. + // User may want to limit the number of retries before generating an error. + if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_SEND_NOSTOP; + } + // If completed message was reading EEPROM data, reset msg to inactive state + // and read data from FIFO. + else if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_READ_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + for(i=0; i < I2C_NUMBYTES; i++) + { + CurrentMsgPtr->MsgBuffer[i] = I2caRegs.I2CDRR; + } + { + // Check recieved data + for(i=0; i < I2C_NUMBYTES; i++) + { + if(I2cMsgIn1.MsgBuffer[i] == I2cMsgOut1.MsgBuffer[i]) + { + PassCount++; + } + else + { + FailCount++; + } + } + if(PassCount == I2C_NUMBYTES) + { + pass(); + } + else + { + fail(); + } + + + } + + } + } + } // end of stop condition detected + + // Interrupt source = Register Access Ready + // This interrupt is used to determine when the EEPROM address setup portion of the + // read data communication is complete. Since no stop bit is commanded, this flag + // tells us when the message has been sent instead of the SCD flag. If a NACK is + // received, clear the NACK bit and command a stop. Otherwise, move on to the read + // data portion of the communication. + else if(IntSource == I2C_ARDY_ISRC) + { + if(I2caRegs.I2CSTR.bit.NACK == 1) + { + I2caRegs.I2CMDR.bit.STP = 1; + I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT; + } + else if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_RESTART; + } + } // end of register access ready + + else + { + // Generate some error due to invalid interrupt source + asm(" ESTOP0"); + } + + // Enable future I2C (PIE Group 8) interrupts + PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; +} + +void pass() +{ + asm(" ESTOP0"); + for(;;); +} + +void fail() +{ + asm(" ESTOP0"); + for(;;); +} + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel new file mode 100644 index 0000000..3a11875 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.gel @@ -0,0 +1,39 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:18:05 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x I2C EEPROM Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xI2C_eeprom.pjt"); + GEL_ProjectBuild("Example_2833xI2C_eeprom.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xI2C_eeprom.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("PassCount",,"Correct Bytes"); + GEL_WatchAdd("FailCount",,"Incorrect Bytes"); + GEL_WatchAdd("I2cMsgIn1.MsgBuffer",,"Input Buffer"); + GEL_WatchAdd("I2cMsgOut1.MsgBuffer",,"Output Buffer"); + GEL_WatchAdd("I2caRegs,x"); +} diff --git a/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt new file mode 100644 index 0000000..06c13e7 --- /dev/null +++ b/v120/DSP2833x_examples/i2c_eeprom/Example_2833xI2C_eeprom.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_I2C.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xI2C_eeprom.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\i2c_eeprom\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xI2C_eeprom.map" -o".\Debug\Example_2833xI2C_eeprom.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xI2C_eeprom.out" -x + diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c new file mode 100644 index 0000000..dd70f78 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.c @@ -0,0 +1,167 @@ +// TI File $Revision: /main/13 $ +// Checkin $Date: June 19, 2008 17:08:02 $ +//########################################################################### +// +// FILE: Example_2833xHaltWake.c +// +// TITLE: Device Halt Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as the LPM wakeup pin to trigger a +// WAKEINT interrupt upon detection of a low pulse. +// Initially, pull GPIO0 high externally. To wake device +// from halt mode, pull GPIO0 low for at least the crystal +// startup time + 2 OSCLKS, then pull it high again. +// +// To observe when device wakes from HALT mode, monitor +// GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into HALT mode. If the lowest +// possible current consumption in HALT mode is desired, the +// JTAG connector must be removed from the device board while +// the device is in HALT mode. +// +// The example then wakes up the device from HALT using GPIO0. +// GPIO0 wakes the device from HALT mode when a low pulse +// (signal goes high->low->high)is detected on the pin. +// This pin must be pulsed by an external agent for wakeup. +// +// As soon as GPIO0 goes high again after the pulse, the device +// should wake up, and GPIO1 can be observed to toggle. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void WAKE_ISR(void); // ISR for WAKEINT + +void main() + +{ + + asm(" EALLOW"); + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Enable all pull-ups + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; + GpioCtrlRegs.GPBPUD.all = 0; + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 set in the ISR to indicate device woken up. + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + +/// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable WAKEINT in the PIE: Group 1 interrupt 8 + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter low power mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0002; // LPM mode = Halt + } + EDIS; +// Force device into HALT + + asm(" IDLE"); // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from halt mode. + for(;;){} // Loop here after wake-up. + +} + +/* ----------------------------------------------- */ +/* ISR for WAKEINT - Will be executed when */ +/* low pulse triggered on GPIO0 pin */ +/* ------------------------------------------------*/ +interrupt void WAKE_ISR(void) +{ + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; // Toggle GPIO1 in the ISR - monitored with oscilloscope + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +} diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel new file mode 100644 index 0000000..584ec59 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.gel @@ -0,0 +1,29 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:32 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Halt Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xHaltWake.pjt"); + GEL_ProjectBuild("Example_2833xHaltWake.pjt"); + +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xHaltWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt new file mode 100644 index 0000000..266e087 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_haltwake/Example_2833xHaltWake.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xHaltWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_haltwake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xHaltWake.map" -o".\Debug\Example_2833xHaltWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xHaltWake.out" -x + diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c new file mode 100644 index 0000000..f9167ce --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.c @@ -0,0 +1,175 @@ +// TI File $Revision: /main/10 $ +// Checkin $Date: May 12, 2008 14:23:32 $ +//########################################################################### +// +// FILE: Example_2833xIdleWake.c +// +// TITLE: Device Idle Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as an XINT1 pin to trigger a +// XINT1 interrupt upon detection of a falling edge. +// Initially, pull GPIO0 high externally. To wake device +// from idle mode by triggering an XINT1 interrupt, +// pull GPIO0 low (falling edge) +// +// To observe when device wakes from IDLE mode, monitor +// GPIO1 with an oscilloscope (set to 1 in XINT1 ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into IDLE mode. +// +// The example then wakes up the device from IDLE using XINT1 +// which triggers on a falling edge from GPIO0. +// This pin must be pulled from high to low by an external agent for +// wakeup. +// +// To observe the device wakeup from IDLE mode, monitor GPIO1 with +// an oscilloscope, which goes high in the XINT_1_ISR. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +interrupt void XINT_1_ISR(void); // ISR + +void main() + +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Choose GPIO0 as the XINT1 pin. + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFE; // All pins are outputs except 0 + GpioDataRegs.GPADAT.all = 0x00000000; // All I/O pins are driven low + EDIS; + + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 pin + XIntruptRegs.XINT1CR.bit.POLARITY = 0; // Interrupt triggers on falling edge + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &XINT_1_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable XINT1 in the PIE: Group 1 interrupt 4 + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter Idle mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0000; // LPM mode = Idle + } + EDIS; + asm(" IDLE"); // Device waits in IDLE until XINT1 interrupts + for(;;){} +} + + +interrupt void XINT_1_ISR(void) +{ + GpioDataRegs.GPASET.bit.GPIO1 = 1; // GPIO1 is driven high upon exiting IDLE. + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + EINT; + return; +} + + + + + + + + + + + + + + + + + diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel new file mode 100644 index 0000000..97129a8 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.gel @@ -0,0 +1,28 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:43 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Idle Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xIdleWake.pjt"); + GEL_ProjectBuild("Example_2833xIdleWake.pjt"); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xIdleWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt new file mode 100644 index 0000000..88e5a28 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_idlewake/Example_2833xIdleWake.pjt @@ -0,0 +1,46 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xIdleWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_idlewake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xIdleWake.map" -o".\Debug\Example_2833xIdleWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xIdleWake.out" -x + diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c new file mode 100644 index 0000000..2a30112 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.c @@ -0,0 +1,169 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 19, 2008 17:08:04 $ +//########################################################################### +// +// FILE: Example_2833xStandbyWake.c +// +// TITLE: Device Standby Mode and Wakeup Program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// GPIO0 is configured as the LPM wakeup pin to trigger a +// WAKEINT interrupt upon detection of a low pulse. +// Initially, pull GPIO0 high externally. To wake device +// from standby mode, pull GPIO0 low for at least (2+QUALSTDBY) +// OSCLKS, then pull it high again. +// +// To observe when device wakes from STANDBY mode, monitor +// GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example puts the device into STANDBY mode. If the lowest +// possible current consumption in STANDBY mode is desired, the +// JTAG connector must be removed from the device board while +// the device is in STANDBY mode. +// +// The example then wakes up the device from STANDBY using GPIO0. +// GPIO0 wakes the device from STANDBY mode when a low pulse +// (signal goes high->low->high)is detected on the pin. +// This pin must be pulsed by an external agent for wakeup. +// +// As soon as GPIO0 goes high again after the pulse, the device +// should wake up, and GPIO1 can be observed to toggle. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void WAKE_ISR(void); // ISR for WAKEINT + +void main() + +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 set in the ISR to indicate device woken up. + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + +// Step 4. Initialize all the Device Peripherals: +// Not applicable for this example. + +// Step 5. User specific code, enable interrupts: + +// Enable CPU INT1 which is connected to WakeInt: + IER |= M_INT1; + +// Enable WAKEINT in the PIE: Group 1 interrupt 8 + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +// Enable global Interrupts: + EINT; // Enable Global interrupt INTM + +// Choose qualification cycles in LPMCR0 register + SysCtrlRegs.LPMCR0.bit.QUALSTDBY = 0; // The wakeup signal should be (2+QUALSTDBY) OSCCLKs wide. + +// Write the LPM code value + EALLOW; + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter Standby mode when PLL is not in limp mode. + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0001; // LPM mode = Standby + } + EDIS; +// Force device into STANDBY + + asm(" IDLE"); // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from Standby mode. + for(;;){} // Loop here after wake-up. + +} + +/* ----------------------------------------------- */ +/* ISR for WAKEINT - Will be executed when */ +/* low pulse triggered on GPIO0 pin */ +/* ------------------------------------------------*/ +interrupt void WAKE_ISR(void) +{ + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; // Toggle GPIO1 in the ISR - monitored with oscilloscope + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + +} diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel new file mode 100644 index 0000000..cfec4cc --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.gel @@ -0,0 +1,29 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:24:54 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x Low Power Standby Mode Wakeup Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xStandbyWake.pjt"); + GEL_ProjectBuild("Example_2833xStandbyWake.pjt"); + +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xStandbyWake.out"); + +} diff --git a/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt new file mode 100644 index 0000000..7ed3469 --- /dev/null +++ b/v120/DSP2833x_examples/lpm_standbywake/Example_2833xStandbyWake.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xStandbyWake.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\lpm_standbywake\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xStandbyWake.map" -o".\Debug\Example_2833xStandbyWake.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xStandbyWake.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c new file mode 100644 index 0000000..84f748e --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c @@ -0,0 +1,244 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_FFDLB.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back program. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// Digital loopback tests for the McBSP peripheral. +// +// Three different serial word sizes can be tested. +// +// Before compiling this project: +// * Select the serial word size (8/16/32) by using +// the #define statements at the beginning of the code. +// + +// +// This example does not use interrupts. Instead, a polling +// method is used to check the receive data. The incoming +// data is checked for accuracy. If an error is found the error() +// function is called and execution stops. +// +// This program will execute until terminated by the user. +// +// Watch Variables: +// sdata1 +// sdata2 +// rdata1 +// rdata2 +// rdata1_point +// rdata2_point +// +//########################################################################### +// +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Choose a word size. Uncomment one of the following lines +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + + +// Prototype statements for functions found within this file. +void mcbsp_xmit(int a, int b); +void error(void); + +// Global data for this example +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Recieved Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Recieved Data + +Uint16 rdata1_point; +Uint16 rdata2_point; + + +void main(void) +{ + Uint16 datasize; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this example, only enable the GPIO for McBSP-A + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + datasize = WORD_SIZE; + InitMcbspa(); // Initalize the Mcbsp-A in loopback test mode + +// Step 5. User specific code, enable interrupts: + + if(datasize == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + sdata2 = 0x0000; // value is a don't care for 8-bit mode + sdata1 = 0x0000; // 8-bit value to send + rdata2_point = 0x0000; // value is a don't care for 8-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata1 = sdata1 & 0x00FF; // Keep it to 8-bits + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + if(rdata1 != rdata1_point) error(); + rdata1_point++; + rdata1_point = rdata1_point & 0x00FF; // Keep it to 8-bits + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + } + } + + + else if(datasize == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + sdata2 = 0x0000; // value is a don't care for 16-bit mode + sdata1 = 0x0000; // 16-bit value to send + rdata2_point = 0x0000; // value is a don't care for 16-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + if(rdata1 != rdata1_point) error(); + rdata1_point++; + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + } + } + + + else if(datasize == 32) // Run a loopback test in 16-bit mode + { + InitMcbspa32bit(); + sdata1 = 0x0000; + sdata2 = 0xFFFF; + rdata1_point = sdata1; + rdata2_point = sdata2; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata2--; + + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive + rdata2 = McbspaRegs.DRR2.all; + rdata1 = McbspaRegs.DRR1.all; + if(rdata1 != rdata1_point) error(); + if(rdata2 != rdata2_point) error(); + rdata1_point++; + rdata2_point--; + + asm(" nop"); // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + // rdata2 = sdata2 + 1 + } + } +} + + + +// Some Useful local functions + +void error(void) +{ + asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + +void mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel new file mode 100644 index 0000000..52976d1 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.gel @@ -0,0 +1,27 @@ +menuitem "DSP2833x McBSP loopback" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB.pjt"); + Setup_WatchWindow(); +} + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata1,x"); + GEL_WatchAdd("rdata1,x"); + GEL_WatchAdd("sdata2,x"); + GEL_WatchAdd("rdata2,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt new file mode 100644 index 0000000..aa6cf7a --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback/Example_2833xMcBSP_DLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB.map" -o".\Debug\Example_2833xMcBSP_DLB.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c new file mode 100644 index 0000000..345e7d6 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c @@ -0,0 +1,403 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_DLB_DMA.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back with DMA program +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a McBSP example that uses the internal loopback of +// the peripheral and utilizes the DMA to transfer data from one buffer +// to the McBSP, and then from the McBSP to another buffer. +// +// Initially, sdata[] is filled with values from 0x0000- 0x007F. The DMA +// moves the values in sdata[] one by one to the DXRx registers of the McBSP. +// These values are transmitted and subsequently received by the McBSP. +// Then, the DMA moves each data value to rdata[] as it is received by the McBSP. +// +// Three different serial word sizes can be tested. +// +// Before compiling this project: +// * Select the serial word size (8/16/32) by using +// the #define statements at the beginning of the code. +// +// The program loops forever after all values have been transferred to sdata. +// It is up to the user to stop the program. +// +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata +// rdata +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Choose a word size. Uncomment one of the following lines +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + +// Prototype statements for functions found within this file. + +interrupt void local_D_INTCH1_ISR(void); +interrupt void local_D_INTCH2_ISR(void); +void mcbsp_init_dlb(void); +void init_dma(void); +void init_dma_32(void); +void start_dma(void); +void error(void); + + +// Place sdata and rdata buffers in DMA-accessible RAM (L4 for this example) +#pragma DATA_SECTION(sdata, "DMARAML4") +#pragma DATA_SECTION(rdata, "DMARAML4") +Uint16 sdata[128]; // Sent Data +Uint16 rdata[128]; // Recieved Data +Uint16 data_size; // Word Length variable + +void main(void) +{ + Uint16 i; +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for McBSP-A functionality + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_D_INTCH1_ISR; + PieVectTable.DINTCH2= &local_D_INTCH2_ISR; + EDIS; // Disable access to EALLOW protected registers + + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code, enable interrupts: + data_size = WORD_SIZE; + for (i=0; i<128; i++) + { + sdata[i] = i; // Fill sdata with values between 0 and 0x007F + rdata[i] = 0; // Initialize rdata to all 0x0000. + } + if (data_size == 32) + { + init_dma_32(); // DMA Initialization for 32-bit transfers + } else + { + init_dma(); // 1. When using DMA, initialize DMA with peripheral interrupts first. + } + start_dma(); + mcbsp_init_dlb(); // 2. Then initialize and release peripheral (McBSP) from Reset. + + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5 + PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6 + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable PIE Group 7, INT 1 (DMA CH1) + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable PIE Group 7, INT 2 (DMA CH2) + + IER=0x60; // Enable CPU INT groups 6 and 7 + EINT; // Enable Global Interrupts + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +void mcbsp_init_dlb() +{ + + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + McbspaRegs.SPCR1.bit.DLB = 1; // Enable DLB mode. Comment out for non-DLB mode. + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive) + McbspaRegs.RCR1.all=0x0; + + McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit) + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = 0; // CLKG frequency = LSPCLK/(CLKGDV+1) + + McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source + McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source + + + + //*************** Initialize McBSP Data Length + if(data_size == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + } + if(data_size == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + } + if(data_size == 32) // Run a loopback test in 32-bit mode + { + InitMcbspa32bit(); + } + + //************* Enable Sample rate generator + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// DMA Initialization for data size <= 16-bit + +void init_dma() +{ + EALLOW; + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm(" NOP"); // Only 1 NOP needed per Design + DmaRegs.CH1.MODE.bit.CHINTE = 0; + // Channel 1, McBSPA transmit + DmaRegs.CH1.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH1.DST_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH1.TRANSFER_SIZE = 127; // Interrupt every frame (127 bursts/transfer) + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Don't move destination address + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Start address = McBSPA DXR + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Not needed unless using wrap function + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + + // Channel 2, McBSPA Receive + DmaRegs.CH2.MODE.bit.CHINTE = 0; + DmaRegs.CH2.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH2.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.DST_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.TRANSFER_SIZE = 127; // Interrupt every 127 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Don't move source address + DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Start address = McBSPA DRR + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Not needed unless using wrap function + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A) + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + EDIS; +} + +// DMA Initialization for data size > 16-bit and <= 32-bit. + +void init_dma_32() +{ + EALLOW; + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm(" NOP"); // Only 1 NOP needed per Design + + // Channel 1, McBSPA transmit + DmaRegs.CH1.BURST_SIZE.all = 1; // 2 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.DST_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH1.DST_TRANSFER_STEP = 0xFFFF; // Go back to DXR2 + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Start address = McBSPA DXR2 + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Not needed unless using wrap function + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + + // Channel 2, McBSPA Receive + DmaRegs.CH2.BURST_SIZE.all = 1; // 2 words/burst + DmaRegs.CH2.SRC_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.DST_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0xFFFF; // Decrement back to DRR2 + DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Start address = McBSPA DRR + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Not needed unless using wrap function + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A) + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags + EDIS; +} +void start_dma (void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start DMA Transmit from McBSP-A + DmaRegs.CH2.CONTROL.bit.RUN = 1; // Start DMA Receive from McBSP-A + + EDIS; +} +// INT7.1 +interrupt void local_D_INTCH1_ISR(void) // DMA Ch1 +{ + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + DmaRegs.CH1.CONTROL.bit.RUN=0; // Re-enable DMA CH1. Should be done every transfer + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt + + EDIS; + return; +} + +// INT7.2 +interrupt void local_D_INTCH2_ISR(void) // DMA Ch2 +{ + Uint16 i; + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + DmaRegs.CH2.CONTROL.bit.RUN = 0; // Re-enable DMA CH2. Should be done every transfer + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt + for (i=0; i<128; i++) + { + if(data_size == 8) + { + if( (rdata[i]&0x00FF) !=(sdata[i]&0x00FF)) error( ); // Check for correct received data + } + else if (data_size == 16) + { + if (rdata[i] != sdata[i]) error(); // STOP if there is an error !! + } + else if (data_size == 32) + { + if ((rdata[i])!=(sdata[i])) error (); + } + } + EDIS; + return; + +} + +//=========================================================================== +// No more. +//=========================================================================== + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel new file mode 100644 index 0000000..1c54abc --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.gel @@ -0,0 +1,22 @@ +menuitem "DSP2833x McBSP DMA" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB_DMA.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB_DMA.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB_DMA.out"); + Setup_WatchWindow(); +} +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("sdata,x"); +} + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt new file mode 100644 index 0000000..4194aa8 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.pjt @@ -0,0 +1,52 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB_DMA.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_DMA.map" -o".\Debug\Example_2833xMcBSP_DLB_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB_DMA.out" -x + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c new file mode 100644 index 0000000..9f0a646 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c @@ -0,0 +1,221 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_FFDLB_int.c +// +// TITLE: DSP2833x Device McBSP Digital Loop Back porgram +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This program is a McBSP example that uses the internal loopback of +// the peripheral. Both Rx and Tx interrupts are enabled. +// +// Incrementing values from 0x0000 to 0x00FF are being sent and received. +// +// This pattern is repeated forever. +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata +// rdata +// rdata_point +// +//########################################################################### +// +// Original Source by S.D. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +interrupt void Mcbsp_TxINTA_ISR(void); +interrupt void Mcbsp_RxINTA_ISR(void); +void mcbsp_init_dlb(void); +void error(void); + +// Global data variables used for this example +Uint16 sdata; // Sent Data +Uint16 rdata; // Recieved Data +Uint16 rdata_point; // Keep track of where we + // are in the data stream + + +void main(void) +{ +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// Setup only the GP I/O only for McBSP-A functionality + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.MRINTA= &Mcbsp_RxINTA_ISR; + PieVectTable.MXINTA= &Mcbsp_TxINTA_ISR; + EDIS; // Disable access to EALLOW protected registers + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + mcbsp_init_dlb(); // For this example, only initialize the Mcbsp + + +// Step 5. User specific code, enable interrupts: + + sdata = 0; + rdata_point = sdata; + +// Enable interrupts required for this example + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5 + PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6 + IER=0x20; // Enable CPU INT6 + EINT; // Enable Global Interrupts + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: + + +void error(void) +{ + asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +void mcbsp_init_dlb() +{ + +//*************** RESET MCBSP + McbspaRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset + McbspaRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset + McbspaRegs.SPCR2.bit.XRST=0; // Transmitter reset + McbspaRegs.SPCR1.bit.RRST=0; // Receiver reset + +//*************** Initialize McBSP Registers +// McBSP register settings for Digital loop back + McbspaRegs.SPCR2.all=0x0000; // XRST =0 + McbspaRegs.SPCR1.all=0x8000; // RRST =0, DLB enabled + McbspaRegs.RCR2.all=0x0001; // RDATDLY = 1 + McbspaRegs.RCR1.all=0x0; + McbspaRegs.XCR2.all=0x0001; // XDATDLY = 1 + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.SRGR2.all=0x3140; + McbspaRegs.SRGR1.all=0x010f; + McbspaRegs.MCR2.all=0x0; + McbspaRegs.MCR1.all=0x0; + McbspaRegs.PCR.all=0x0A00; + + McbspaRegs.MFFINT.bit.XINT = 1; // Enable Transmit Interrupts + McbspaRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts + +//************* Enable Sample rate generator + McbspaRegs.SPCR2.bit.GRST=1; + delay_loop(); // Wait at least 2 SRG clock cycles + +//************ Enable TX/RX unit + McbspaRegs.SPCR2.bit.XRST=1; + McbspaRegs.SPCR1.bit.RRST=1; + +//************ Frame Sync generator reset + McbspaRegs.SPCR2.bit.FRST=1; +} + +interrupt void Mcbsp_TxINTA_ISR(void) +{ + McbspaRegs.DXR1.all= sdata; + sdata = (sdata+1)& 0x00FF ; + // To receive more interrupts from this PIE group, acknowledge this interrupt + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +interrupt void Mcbsp_RxINTA_ISR(void) +{ + rdata=McbspaRegs.DRR1.all; + if (rdata != ( (rdata_point) & 0x00FF) ) error(); + rdata_point = (rdata_point+1) & 0x00FF; + // To receive more interrupts from this PIE group, acknowledge this interrupt + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel new file mode 100644 index 0000000..b3cd28b --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.gel @@ -0,0 +1,27 @@ +menuitem "DSP2833x McBSP Int" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_DLB_int.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_DLB_int.pjt"); + Setup_WatchWindow(); +} + + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_DLB_int.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata,x"); + GEL_WatchAdd("rdata,x"); + GEL_WatchAdd("rdata_point,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt new file mode 100644 index 0000000..1f8f3a6 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_DLB_int.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_interrupts\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_int.map" -o".\Debug\Example_2833xMcBSP_DLB_int.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_DLB.out" -x + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c new file mode 100644 index 0000000..46f35d8 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: Example_2833xMCBSP_SPIX.c +// +// TITLE: DSP28133x Device McBSP using SPI mode +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// SPI master mode transfer of 32-bit word size with digital loopback enabled. +// +// McBSP Signals SPI equivalent +// ------------------------------------- +// MCLKX SPICLK (master) +// MFSX SPISTE (master) +// MDX SPISIMO +// MCLKR SPICLK (slave - not used for this example) +// MFSR SPISTE (slave - not used for this example) +// MDR SPISOMI (not used for this example) +// +// This program will execute and transmit words until terminated by the user. +// +// By default for the McBSP examples, the McBSP sample rate generator (SRG) input +// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or +// 100 MHz respectively. If while testing, the SRG input frequency +// is changed, the #define MCBSP_SRG_FREQ (CPU_SPD/4) in the Mcbsp.c file must +// also be updated accordingly. This define is used to determine the Mcbsp initialization +// delay after the SRG is enabled, which must be at least 2 SRG clock cycles. +// +// Watch Variables: +// sdata1 +// sdata2 +// rdata1 +// rdata2 +// +// +//########################################################################### +// +// Original Author: S.S. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. + +void init_mcbsp_spi(void); +void mcbsp_xmit(int a, int b); +void error(void); + +// Global data for this example +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Recieved Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Recieved Data + + +void main(void) +{ + +// Uint16 i; + + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example +// For this example, only enable the GPIO for McBSP-A + InitMcbspaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP281x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + + +// Step 5. User specific code, + + init_mcbsp_spi(); + sdata1 = 0x55aa; + sdata2 = 0xaa55; +// Main loop to transfer 32-bit words through MCBSP in SPI mode periodically + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {} // Master waits until RX data is ready + rdata2 = McbspaRegs.DRR2.all; // Read DRR2 first. + rdata1 = McbspaRegs.DRR1.all; // Then read DRR1 to complete receiving of data + if((rdata2 != sdata2)&&(rdata1 != sdata1)) error( ); // Check that correct data is received. + delay_loop(); + sdata1^=0xFFFF; + sdata2^=0xFFFF; + asm(" nop"); // Good place for a breakpoint + + } +} + + + +// Some Useful local functions + +void error(void) +{ + asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + + + + +void init_mcbsp_spi() +{ + // McBSP-A register settings + McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis. + McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1) + McbspaRegs.SPCR1.bit.DLB = 1; + McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme + McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay + McbspaRegs.PCR.bit.CLKRP = 0; + McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive) + McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit) + + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word + + McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods + McbspaRegs.SRGR1.all= 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16 + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +void mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel new file mode 100644 index 0000000..f0a701d --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.gel @@ -0,0 +1,28 @@ +menuitem "DSP2833x McBSP SPI DLB" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xMcBSP_SPI_DLB.pjt"); + GEL_ProjectBuild("Example_2833xMcBSP_SPI_DLB.pjt"); + Setup_WatchWindow(); +} + + + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xMcBSP_SPI_DLB.out"); + Setup_WatchWindow(); +} + +Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("sdata1,x"); + GEL_WatchAdd("rdata1,x"); + GEL_WatchAdd("sdata2,x"); + GEL_WatchAdd("rdata2,x"); +} + + + diff --git a/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt new file mode 100644 index 0000000..2f8e650 --- /dev/null +++ b/v120/DSP2833x_examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xMcBSP_SPI_DLB.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_spi_loopback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_int.map" -o".\Debug\Example_2833xMcBSP_SPI_DLB.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xMcBSP_SPI_DLB.out" -x + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c new file mode 100644 index 0000000..6d93eff --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.c @@ -0,0 +1,390 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: April 21, 2008 15:43:14 $ +//########################################################################### +// +// FILE: Example_2833xSci_Autobaud_.c +// +// TITLE: DSP2833x SCI Autobaud detect example +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// Test requires the following hardware connections: +// +// GPIO29/SCITXDA <-> GPIO19/SCIRXDB +// GPIO28/SCIRXDA <-> GPIO18/SCITXDB +// +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// +// This test will perform autobaud lock at a variety of baud rates, including +// very high baud rates. +// +// For this test to properly run, connect the SCI-A pins to the +// SCI-B pins without going through a transciever. +// +// At higher baud rates, the slew rate of the incoming data bits can be +// affected by transceiver and connector performance. This slew rate may +// limit reliable autobaud detection at higher baud rates. +// +// SCIA: Slave, autobaud locks, receives characters and +// echos them back to the host. Uses the RX interrupt +// to receive characters. +// +// SCIB: Host, known baud rate, sends characters to the slave +// and checks that they are echoed back. +// +// DESCRIPTION: +// +// Internal Loopback test for ever through SCIA using interrupts, +// FIFOs are disabled. +// +// Watch Variables: BRRVal - current BRR value used for SCIB +// ReceivedAChar - character received by SCIA +// ReceivedBChar - character received by SCIB +// SendChar - character being sent by SCIB +// SciaRegs.SCILBAUD - SCIA baud registers - set +// SciaRegs.SCIHBAUD by autobaud lock +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +#define BAUDSTEP 100 // Amount BRR will be incremented between each + // autobaud lock + +// Prototype statements for functions found within this file. +void scia_init(void); +void scib_init(void); +void scia_xmit(int a); +void scib_xmit(int a); +void scia_AutobaudLock(void); +void error(); +interrupt void rxaint_isr(void); + + +// Global counts used in this example +Uint16 LoopCount; +//Uint16 xmitCount; +Uint16 ReceivedCount; +Uint16 ErrorCount; +Uint16 SendChar; +Uint16 ReceivedAChar; // scia received character +Uint16 ReceivedBChar; // scib received character +Uint16 BRRVal; +Uint16 Buff[10] = {0x55, 0xAA, 0xF0, 0x0F, 0x00, 0xFF, 0xF5, 0x5F, 0xA5, 0x5A}; + +void main(void) +{ + Uint16 i; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + InitSciGpio(); + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SCIRXINTA = &rxaint_isr; + EDIS; // This is needed to disable write to EALLOW protected register + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + scia_init(); // Initalize SCIA + scib_init(); // Initalize SCIB + +// Step 5. User specific code, enable interrupts: + + LoopCount = 0; + ErrorCount = 0; + +// Enable interrupts + PieCtrlRegs.PIEIER9.all = 0x0001; // Enable all SCIA RXINT interrupt + IER |= 0x0100; // enable PIEIER9, and INT9 + EINT; + + // Start with BRR = 1, work through each baud rate setting + // incrementing BRR by BAUDSTEP + for (BRRVal = 0x0000; BRRVal < (Uint32)0xFFFF; BRRVal+=BAUDSTEP) + { + + // SCIB has a known baud rate. SCIA will autobaud to match + ScibRegs.SCIHBAUD = (BRRVal >> 8); + ScibRegs.SCILBAUD = (BRRVal); + + // Initiate an autobaud lock with scia. Check + // returned character against baud lock character 'A' + scia_AutobaudLock(); + while(ScibRegs.SCIRXST.bit.RXRDY != 1) { } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + if(ReceivedBChar != 'A') + { + error(0); + } + + // Send/echoback characters + // 55 AA F0 0F 00 FF F5 5F A5 5A + for(i= 0; i<=9; i++) + { + SendChar = Buff[i]; + scib_xmit(SendChar); // Initiate interrupts and xmit data in isr + // Wait to get the character back and check + // against the sent character. + while(ScibRegs.SCIRXST.bit.RXRDY != 1) + { + asm(" NOP"); + } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + if(ReceivedBChar != SendChar) error(1); + } + + } // Repeat for next BRR setting + + // Stop here, no more + for(;;) + { + asm(" NOP"); + } + + +} + + +/* --------------------------------------------------- */ +/* ISR for PIE INT9.1 */ +/* Connected to RXAINT SCI-A */ +/* ----------------------------------------------------*/ + +interrupt void rxaint_isr(void) // SCI-A +{ + // Insert ISR Code here + + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // If autobaud detected, we must clear CDC + if(SciaRegs.SCIFFCT.bit.ABD == 1) + { + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 0; + // Check received character - should be 'A' + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + if(ReceivedAChar != 'A') + { + error(2); + } + else scia_xmit(ReceivedAChar); + } + + // This was not autobaud detect + else + { + // Check received character against sendchar + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + if(ReceivedAChar != SendChar) + { + error(3); + } + else scia_xmit(ReceivedAChar); + } + + SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // clear Receive interrupt flag + ReceivedCount++; +} + + +void error() +{ + ErrorCount++; + asm(" ESTOP0"); // Uncomment to stop the test here + for (;;); + +} + +// SCIA 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity +void scia_init() +{ + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + + // Reset FIFO's + SciaRegs.SCIFFTX.all=0x8000; + + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + + +} + +// SCIB 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity + +void scib_init() +{ + // Reset FIFO's + ScibRegs.SCIFFTX.all=0x8000; + + // 1 stop bit, No parity, 8-bit character + // No loopback + ScibRegs.SCICCR.all = 0x0007; + + // Enable TX, RX, Use internal SCICLK + ScibRegs.SCICTL1.all = 0x0003; + + // Disable RxErr, Sleep, TX Wake, + // Diable Rx Interrupt, Tx Interrupt + ScibRegs.SCICTL2.all = 0x0000; + + // Relinquish SCI-A from reset + ScibRegs.SCICTL1.all = 0x0023; + + return; +} + + + + +// Transmit a character from the SCI-A' +void scia_xmit(int a) +{ + SciaRegs.SCITXBUF=a; +} + +// Transmit a character from the SCI-B' +void scib_xmit(int a) +{ + ScibRegs.SCITXBUF=a; +} + + +//------------------------------------------------ +// Perform autobaud lock with the host. +// Note that if autobaud never occurs +// the program will hang in this routine as there +// is no timeout mechanism included. +//------------------------------------------------ + +void scia_AutobaudLock() +{ + + SciaRegs.SCICTL1.bit.SWRESET = 0; + SciaRegs.SCICTL1.bit.SWRESET = 1; + + // Must prime baud register with >= 1 + SciaRegs.SCIHBAUD = 0; + SciaRegs.SCILBAUD = 1; + + // Prepare for autobaud detection + // Make sure the ABD bit is clear by writing a 1 to ABDCLR + // Set the CDC bit to enable autobaud detection + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 1; + + // Wait until we correctly read an + // 'A' or 'a' and lock + // + // As long as Autobaud calibration is enabled (CDC = 1), + // SCI-B (host) will continue transmitting 'A'. This will + // continue until interrupted by the SCI-A RX ISR, where + // SCI-A RXBUF receives 'A', autobaud-locks (ABDCLR=1 + // CDC=0),and returns an 'A' back to the host. Then control + // is returned to this loop and the loop is exited. + // + // NOTE: ABD will become set sometime between + // scib_xmit and the DELAY_US loop, and + // the SCI-A RX ISR will be triggered. + // Upon returning and reaching the if-statement, + // ABD will have been cleared again by the ISR. + + while(SciaRegs.SCIFFCT.bit.CDC== 1) + { + // Note the lower the baud rate the longer + // this delay has to be to allow the other end + // to echo back a character (about 4 characters long) + // Make this really long since we are going through all + // the baud rates. + DELAY_US(280000L); + + if(SciaRegs.SCIFFCT.bit.CDC == 1) + scib_xmit('A'); // host transmits 'A' + + } + + return; +} + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel new file mode 100644 index 0000000..20a2117 --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.gel @@ -0,0 +1,48 @@ +/* +// TI File $Revision: /main/6 $ +// Checkin $Date: August 15, 2007 09:42:26 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI Autobaud" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSci_Autobaud.pjt"); + GEL_ProjectBuild("Example_2833xSci_Autobaud.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSci_Autobaud.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("BRRVal,x"); + GEL_WatchAdd("ReceivedAChar,x"); + GEL_WatchAdd("ReceivedBChar,x"); + GEL_WatchAdd("ReceivedCount,x"); + GEL_WatchAdd("SendChar,x"); + GEL_WatchAdd("SciaRegs.SCIHBAUD,x"); + GEL_WatchAdd("SciaRegs.SCILBAUD,x"); + GEL_WatchAdd("ScibRegs.SCIHBAUD,x"); + GEL_WatchAdd("ScibRegs.SCILBAUD,x"); + GEL_WatchAdd("SciaRegs,x"); + GEL_WatchAdd("ScibRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt new file mode 100644 index 0000000..d4ef177 --- /dev/null +++ b/v120/DSP2833x_examples/sci_autobaud/Example_2833xSci_Autobaud.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSci_Autobaud.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_autobaud\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSci_Autobaud.map" -o".\Debug\Example_2833xSci_Autobaud.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSci_Autobaud.out" -x + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c new file mode 100644 index 0000000..4fe5cf7 --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.c @@ -0,0 +1,236 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: April 21, 2008 15:43:19 $ +//########################################################################### +// +// FILE: Example_2833xSci_Echoback.c +// +// TITLE: DSP2833x Device SCI Echoback. +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// As supplied, this project is configured for "boot to SARAM" operation. +// +// Connect the SCI-A port to a PC via a transciever and cable. +// The PC application 'hypterterminal' can be used to view the data +// from the SCI and to send information to the SCI. Characters recieved +// by the SCI port are sent back to the host. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// +// This test recieves and echo-backs data through the SCI-A port. +// +// 1) Configure hyperterminal: +// Use the included hyperterminal configuration file SCI_96.ht. +// To load this configuration in hyperterminal: file->open +// and then select the SCI_96.ht file. +// 2) Check the COM port. +// The configuration file is currently setup for COM1. +// If this is not correct, disconnect Call->Disconnect +// Open the File-Properties dialog and select the correct COM port. +// 3) Connect hyperterminal Call->Call +// and then start the 2833x SCI echoback program execution. +// 4) The program will print out a greeting and then ask you to +// enter a character which it will echo back to hyperterminal. +// +// As is, the program configures SCI-A for 9600 baud with +// SYSCLKOUT = 150MHz and LSPCLK = 37.5 MHz +// SYSCLKOUT = 100MHz and LSPCLK = 25.0 Mhz +// +// +// Watch Variables: +// LoopCount for the number of characters sent +// ErrorCount +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// Prototype statements for functions found within this file. +void scia_echoback_init(void); +void scia_fifo_init(void); +void scia_xmit(int a); +void scia_msg(char *msg); + +// Global counts used in this example +Uint16 LoopCount; +Uint16 ErrorCount; + +void main(void) +{ + + Uint16 ReceivedChar; + char *msg; + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. + // InitGpio(); Skipped for this example + +// For this example, only init the pins for the SCI-A port. +// This function is found in the DSP2833x_Sci.c file. + InitSciaGpio(); + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Step 4. Initialize all the Device Peripherals: +// This function is found in DSP2833x_InitPeripherals.c +// InitPeripherals(); // Not required for this example + +// Step 5. User specific code: + + LoopCount = 0; + ErrorCount = 0; + + scia_fifo_init(); // Initialize the SCI FIFO + scia_echoback_init(); // Initalize SCI for echoback + + msg = "\r\n\n\nHello World!\0"; + scia_msg(msg); + + msg = "\r\nYou will enter a character, and the DSP will echo it back! \n\0"; + scia_msg(msg); + + for(;;) + { + msg = "\r\nEnter a character: \0"; + scia_msg(msg); + + // Wait for inc character + while(SciaRegs.SCIFFRX.bit.RXFFST !=1) { } // wait for XRDY =1 for empty state + + // Get character + ReceivedChar = SciaRegs.SCIRXBUF.all; + + // Echo character back + msg = " You sent: \0"; + scia_msg(msg); + scia_xmit(ReceivedChar); + + LoopCount++; + } + +} + + +// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity +void scia_echoback_init() +{ + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + #if (CPU_FRQ_150MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 37.5MHz. + SciaRegs.SCILBAUD =0x00E7; + #endif + #if (CPU_FRQ_100MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 20MHz. + SciaRegs.SCILBAUD =0x0044; + #endif + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// Transmit a character from the SCI +void scia_xmit(int a) +{ + while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {} + SciaRegs.SCITXBUF=a; + +} + +void scia_msg(char * msg) +{ + int i; + i = 0; + while(msg[i] != '\0') + { + scia_xmit(msg[i]); + i++; + } +} + +// Initalize the SCI FIFO +void scia_fifo_init() +{ + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x204f; + SciaRegs.SCIFFCT.all=0x0; + +} + + + + + + +//=========================================================================== +// No more. +//=========================================================================== + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel new file mode 100644 index 0000000..33e7cb5 --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.gel @@ -0,0 +1,40 @@ +/* +// TI File $Revision: /main/5 $ +// Checkin $Date: August 9, 2007 17:20:59 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP2833x SCI Echoback" + + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xSci_Echoback.pjt"); + GEL_ProjectBuild("Example_2833xSci_Echoback.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xSci_Echoback.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("LoopCount,x"); + GEL_WatchAdd("ErrorCount,x"); + GEL_WatchAdd("SciaRegs,x"); +} + + diff --git a/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt new file mode 100644 index 0000000..89b00df --- /dev/null +++ b/v120/DSP2833x_examples/sci_echoback/Example_2833xSci_Echoback.pjt @@ -0,0 +1,45 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_Sci.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xSci_Echoback.c" +Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sci_echoback\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -m".\Debug\Example_2833xSci_echoback.map" -o".\Debug\Example_2833xSci_echoback.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xSci_echoback.out" -x + diff --git a/v120/DSP2833x_examples/sci_echoback/SCI_96.ht b/v120/DSP2833x_examples/sci_echoback/SCI_96.ht new file mode 100644 index 0000000000000000000000000000000000000000..9c7ebe3fb38fd18574df04d45400d7ecb014a374 GIT binary patch literal 23333 zcmeHPOK%)S5H35(CNWyDLlBQs=V^#Y@Y+tW5fYfqf)r8sV7=>%$4Q(E zh#L}E9CGD9aNx*K0Eq(!4jd5T8gdLbQ`MCWiQQvWPq#PL(leUfnwtKq>g%qVp6TA5 z+0~^ec|S@P<4(P;DyPQO$&+gK0cEqE*42F6j>GN(`a!iRcTi( zcAN41s!A8)WnEM?<0NXN?bTD|AzGh-9l8v_Zj3C#ZI70&e>izy7!Kn8>;?5Ul1<)< zQZ=bA#_HV1Faom!TpGV%5I0)(<3{^=3mw~dd>86w&R={JzNxi-yj6nVZBp+w1G=gxauZUA4QC#8INKW;Pt=-6Mc*H!VkXlugvnXo+HdO-tib z6{vDsoMkF2hc3OI6?#KUWN%itSoNKA725m1F7I+xy{D_?NvwtE2B`gMJE0}2+3|tP zA5euwkbr_ZZVgz#?*z97q+0)yK2nD{T${KyaHa1E*Lhr9xRQl7u3aqq5q>5pH{p=A zULm3j*R;n3Z7NvRHWf-ccP+yTyrSbP>(9K}FtfXdwdcp)>~Z<=+1tuT6pb$5qA53u z*IvG#yd(Y@<#}4nJ#+F9z0>!u7PjK_uybLn*z%5*ty`54o3Dpk<$N(8=Bsx;j~aCD z_6}S38f4)UWUzwYQHF`IZ%~L|&{z1p9w*PcPkk9=Oy=};y%-b5`i$CSOUk6-z=W|T z?>==>CX_=(vx~7lqc+)+GNJpNqD&ZT^6pb7Wis!;gt0!OHrbLgX*n=qtjW7ios`Lf z0~5yjjM`*N$|QDR!dR1cpE@a%PaT*r)@RfvTT&*UIWS?Y$-7UTlu6rx31fXmZL%e0 zvgp8su_o_6by6lB2PTa58MVollnITD6z$^~Yx3?>CuOqaz=W|rqc+)+GP&Zwgs~>? zK6O$iGCuMTg zfeB-MMs2bsWkO@*Mcah2ChtCVQYP0Om@w97)FxX}CaVri7;EzGQzvC|!+{B7eMW7v zC1pZ$T1C$j#+tnQ)Jd6yF-V$;3}cXXxhKu8Fa}B46~-X9C%eKJBxP3^gWR6%>Yp*l z{uw1Ide3E-AvUF@Jt6(liGJZ^V_QKPe=$X$W&HILt&A=*8!wxY4)?WmMGbT7wpl96 zu5dRP?gs5Li%Ltcu;Fen+zoDDcJI;O~2+ibBdFU_us0~5yD zMrK=H%4FPu31e*|vn?-WGU334v9^)fmX|V_bYQ|*+sJIoOPQQ@V8U42$ZX3?nVfN8 z!dTnLY|BfTyy(D$v9^)fmX|V_a$v$(+sJIoOPNeNFk!51WVYp{OvW6TFxECQ+wxK- z)8LX{y=fKscsA)xYf4QOQ^8~_%0#T znBCiuCd9w3s@&}*i#@MZ#D0qR7ZVtvwEbPYNPYC`taQ1??6ewlxhl(Ztbc0Eg^B#! z4_<8hmtNG^>FjN*XEF%}={>9iv}p+i7|e9LGTrV$DpTH*DN0(}hswQ~ZeJ$t&!izO z5%`fzSI(qIwM14P%XA~d6w(*R01jx0jy|p>6yRVcJ&{RIXOhaK!&-VC5l1rVsFr@i zwOkS_(ruvKE{UWmBP2ouN0=Dm6;^Q7hTV^(\DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + xintffuncs : LOAD = RAML1, + RUN = ZONE7A, + LOAD_START(_XintffuncsLoadStart), + LOAD_END(_XintffuncsLoadEnd), + RUN_START(_XintffuncsRunStart), + PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c new file mode 100644 index 0000000..2902cff --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.c @@ -0,0 +1,256 @@ +//########################################################################### +// +// FILE: Example_2833xCodeRunFromXintf.c +// +// TITLE: Example Program That Executes From XINTF +// +// ASSUMPTIONS: +// +// This program requires the DSP2833x header files. +// +// As supplied, this project is configured for "boot to SARAM" +// operation. The 2833x Boot Mode table is shown below. +// For information on configuring the boot mode of an eZdsp, +// please refer to the documentation included with the eZdsp, +// +// $Boot_Table: +// +// GPIO87 GPIO86 GPIO85 GPIO84 +// XA15 XA14 XA13 XA12 +// PU PU PU PU +// ========================================== +// 1 1 1 1 Jump to Flash +// 1 1 1 0 SCI-A boot +// 1 1 0 1 SPI-A boot +// 1 1 0 0 I2C-A boot +// 1 0 1 1 eCAN-A boot +// 1 0 1 0 McBSP-A boot +// 1 0 0 1 Jump to XINTF x16 +// 1 0 0 0 Jump to XINTF x32 +// 0 1 1 1 Jump to OTP +// 0 1 1 0 Parallel GPIO I/O boot +// 0 1 0 1 Parallel XINTF boot +// 0 1 0 0 Jump to SARAM <- "boot to SARAM" +// 0 0 1 1 Branch to check boot mode +// 0 0 1 0 Boot to flash, bypass ADC cal +// 0 0 0 1 Boot to SARAM, bypass ADC cal +// 0 0 0 0 Boot to SCI-A, bypass ADC cal +// Boot_Table_End$ +// +// DESCRIPTION: +// +// This example configures CPU Timer0 and increments +// a counter each time the timer asserts an interrupt. +// +// The code is loaded into SARAM. The XINTF Zone 7 is +// configured for x16-bit data bus. A porition of the code +// is copied to XINTF for execution there. +// +// Watch Variables: +// CpuTimer0.InterruptCount +// CpuTimer1.InterruptCount +// CpuTimer2.InterruptCount +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// These two functions will be loaded into SARAM and copied to +// XINTF zone 7 for execution +#pragma CODE_SECTION(cpu_timer0_isr,"xintffuncs"); +#pragma CODE_SECTION(cpu_timer1_isr,"xintffuncs"); + +// Prototype statements for functions found within this file: +void init_zone7(void); +interrupt void cpu_timer0_isr(void); +interrupt void cpu_timer1_isr(void); +interrupt void cpu_timer2_isr(void); + +void main(void) +{ + +// Step 1. Initialize System Control: +// PLL, WatchDog, enable Peripheral Clocks +// This example function is found in the DSP2833x_SysCtrl.c file. + InitSysCtrl(); + +// Step 2. Initalize GPIO: +// This example function is found in the DSP2833x_Gpio.c file and +// illustrates how to set the GPIO to it's default state. +// InitGpio(); // Skipped for this example + + +// Step 3. Clear all interrupts and initialize PIE vector table: +// Disable CPU interrupts + DINT; + +// Initialize the PIE control registers to their default state. +// The default state is all PIE interrupts disabled and flags +// are cleared. +// This function is found in the DSP2833x_PieCtrl.c file. + InitPieCtrl(); + +// Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + +// Initialize the PIE vector table with pointers to the shell Interrupt +// Service Routines (ISR). +// This will populate the entire table, even if the interrupt +// is not used in this example. This is useful for debug purposes. +// The shell ISR routines are found in DSP2833x_DefaultIsr.c. +// This function is found in DSP2833x_PieVect.c. + InitPieVectTable(); + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + +// Step 4. Initialize the Device Peripheral. This function can be +// found in DSP2833x_CpuTimers.c + InitCpuTimers(); // For this example, only initialize the Cpu Timers + +#if (CPU_FRQ_150MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 150MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); +#endif + +#if (CPU_FRQ_100MHZ) +// Configure CPU-Timer 0, 1, and 2 to interrupt every second: +// 100MHz CPU Freq, 1 second Period (in uSeconds) + + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); +#endif + +// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any +// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the +// below settings must also be updated. + + CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 + +// Step 5. User specific code, enable interrupts: + +// Initalize XINTF Zone 7 + init_zone7(); + +// Copy non-time critical code to XINTF +// This includes the following ISR functions: cpu_timer0_isr(), cpu_timer1_isr() +// The XintffuncsLoadStart, XintffuncsLoadEnd, and XintffuncsRunStart +// symbols are created by the linker. Refer to the F28335_ram_xintf.cmd file. + MemCopy(&XintffuncsLoadStart, &XintffuncsLoadEnd, &XintffuncsRunStart); + +// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 +// which is connected to CPU-Timer 1, and CPU int 14, which is connected +// to CPU-Timer 2: + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + +// Enable TINT0 in the PIE: Group 1 interrupt 7 + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + +// Enable global Interrupts and higher priority real-time debug events: + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + +// Step 6. IDLE loop. Just sit and loop forever (optional): + for(;;); + +} + + +interrupt void cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +interrupt void cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + // The CPU acknowledges the interrupt. + EDIS; +} + +// Configure the timing paramaters for Zone 7. +// Notes: +// This function should not be executed from XINTF +// Adjust the timing based on the data manual and +// external device requirements. +void init_zone7(void) +{ + + // Make sure the XINTF clock is enabled + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; + + // Configure the GPIO for XINTF with a 16-bit data bus + // This function is in DSP2833x_Xintf.c + InitXintf16Gpio(); + + EALLOW; + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = SYSCLKOUT + XintfRegs.XINTCNF2.bit.XTIMCLK = 0; + // Buffer up to 3 writes + XintfRegs.XINTCNF2.bit.WRBUFF = 3; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK + XintfRegs.XINTCNF2.bit.CLKMODE = 0; + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 1; + XintfRegs.XTIMING7.bit.XWRACTIVE = 2; + XintfRegs.XTIMING7.bit.XWRTRAIL = 1; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 1; + XintfRegs.XTIMING7.bit.XRDACTIVE = 3; + XintfRegs.XTIMING7.bit.XRDTRAIL = 0; + + // don't double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 0; + + // Zone will not sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 0; + XintfRegs.XTIMING7.bit.READYMODE = 0; + + // 1,1 = x16 data bus + // 0,1 = x32 data bus + // other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt new file mode 100644 index 0000000..e71b210 --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xCodeRunFromXintf.pjt @@ -0,0 +1,62 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectName="DSP2833x" +ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="..\..\DSP2833x_common\source\DSP2833x_DBGIER.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c" +Source="..\..\DSP2833x_common\source\DSP2833x_MemCopy.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c" +Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="..\..\DSP2833x_common\source\DSP2833x_Xintf.c" +Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Example_2833xCodeRunFromXintf.c" +Source="Example_2833xRunFromXintf.gel" +Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" +Source="28335_RAM_xintf_lnk.cmd" + +["Compiler" Settings: "Debug"] +Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -mf -ml -mn -mt -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\xintf_run_from\Release" -d"LARGE_MODEL" -ml -v28 + +["DspBiosBuilder" Settings: "Debug"] +Options=-v28 + +["DspBiosBuilder" Settings: "Release"] +Options=-v28 + +["Linker" Settings: "Debug"] +Options=-q -c -ecode_start -heap0x800 -m".\Debug\Example_2833xCodeRunFromXintf.map" -o".\Debug\Example_2833xCodeRunFromXintf.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-q -c -o".\Release\Example_2833xCodeRunFromXintf.out" -x + +["Example_2833xRunFromXintf.gel" Settings: "Debug"] +ExcludeFromBuild=true + +["Example_2833xRunFromXintf.gel" Settings: "Release"] +ExcludeFromBuild=true + +["28335_RAM_xintf_lnk.cmd" Settings: "Debug"] +LinkOrder=1 + +["28335_RAM_xintf_lnk.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel b/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel new file mode 100644 index 0000000..04e0f4f --- /dev/null +++ b/v120/DSP2833x_examples/xintf_run_from/Example_2833xRunFromXintf.gel @@ -0,0 +1,37 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: August 29, 2007 14:08:07 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +menuitem "DSP28335 XINTF Run Example" + +hotmenu Load_and_Build_Project() +{ + GEL_ProjectLoad("Example_2833xCodeRunFromXintf.pjt"); + GEL_ProjectBuild("Example_2833xCodeRunFromXintf.pjt"); + Setup_WatchWindow(); +} + +hotmenu Load_Code() +{ + GEL_Load(".\\debug\\Example_2833xCodeRunFromXintf.out"); + Setup_WatchWindow(); +} + +hotmenu Setup_WatchWindow() +{ + GEL_WatchReset(); + GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer1.InterruptCount",,"CPU ISR Count"); + GEL_WatchAdd("CpuTimer2.InterruptCount",,"CPU ISR Count"); +} diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd new file mode 100644 index 0000000..fe2d6c5 --- /dev/null +++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: August 8, 2008 11:09:25 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ \ No newline at end of file diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..9da1026 --- /dev/null +++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: June 2, 2008 11:12:24 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel b/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel new file mode 100644 index 0000000..e08455b --- /dev/null +++ b/v120/DSP2833x_headers/gel/DSP2833x_DualMap_EPWM.gel @@ -0,0 +1,237 @@ +/* +/* TI File $Revision: /main/1 $ */ +/* Checkin $Date: May 7, 2008 13:07:07 $ */ +/***********************************************************************/ +/* File: DSP2833x_DualMap_EPWM.gel +/* +/* Description: +/* Adds dual-mapped EPWM registers to the GEL menu in +/* Code Composer Studio and allows user to enable dual-mapping of +/* EPWM registers to Peripheral Frame 3 (DMA-accessible) register +/* space +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +/********************************************************************/ +/* Dual-Mapped Enhanced PWM Registers */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "___________________________________"; +hotmenu ___() {} + +menuitem "Dual-Mapped ePWM Registers"; +hotmenu Enable_ePWM_Dual_Mapping () +{ + *0x702E = (*0x702E) | 0x0001; /* MAPCNF[MAPEPWM] = 1 */ +} +hotmenu ePWM1_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x5801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x5802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x5803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x5804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x5805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x5807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x5808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x5809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x580A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x580B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x580C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x580D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x580E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x580F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x5810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x5811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x5812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x5813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x5814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x5815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x5816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x5817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x5818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x5819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x581A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x581B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x581C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x581D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x581E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x5820,x","ePWM1 HRCNFG"); +} + +hotmenu ePWM2_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x5841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x5842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x5843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x5844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x5845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x5847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x5848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x5849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x584A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x584B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x584C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x584D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x584E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x584F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x5850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x5851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x5852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x5853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x5854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x5855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x5856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x5857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x5858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x5859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x585A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x585B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x585C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x585D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x585E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x5860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM3_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x5881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x5882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x5883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x5884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x5885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x5887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x5888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x5889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x588A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x588B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x588C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x588D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x588E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x588F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x5890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x5891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x5892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x5893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x5894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x5895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x5896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x5897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x5898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x5899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x589A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x589B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x589C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x589D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x589E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x58A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM4_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x58C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x58C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x58C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x58C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x58C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x58C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x58C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x58C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x58C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x58CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x58CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x58CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x58CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x58CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x58CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x58D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x58D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x58D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x58D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x58D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x58D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x58D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x58D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x58D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x58D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x58DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x58DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x58DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x58DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x58DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x58E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM5_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x5901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x5902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x5903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x5904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x5905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x5907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x5908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x5909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x590A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x590B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x590C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x590D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x590E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x590F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x5910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x5911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x5912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x5913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x5914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x5915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x5916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x5917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x5918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x5919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x591A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x591B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x591C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x591D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x591E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x5920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM6_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x5941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x5942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x5943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x5944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x5945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x5947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x5948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x5949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x594A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x594B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x594C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x594D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x594E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x594F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x5950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x5951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x5952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x5953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x5954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x5955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x5956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x5957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x5958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x5959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x595A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x595B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x595C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x595D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x595E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x5960,x","ePWM6 HRCNFG"); + +} + diff --git a/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel b/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel new file mode 100644 index 0000000..c51afd1 --- /dev/null +++ b/v120/DSP2833x_headers/gel/DSP2833x_Peripheral.gel @@ -0,0 +1,249 @@ +/* +/* TI File $Revision: /main/7 $ */ +/* Checkin $Date: June 2, 2008 11:12:27 $ */ +/******************************************************************* */ +/* File: DSP2833x_peripheral.gel */ +/* Description: Adds '2833x registers to the GEL menu in */ +/* Code Composer Studio using the structures defined in the DSP2833x */ +/* header files. The user must have the symbols (.out file) */ +/* loaded from a project using the DSP28 structures in order for */ +/* these menu items to work. If symbols are not loaded, the */ +/* watch window will report "Identifier not found." */ +/* +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +/* Add a space line to the GEL menu */ +menuitem "____________________________________"; +hotmenu _() {} + +menuitem "Watch DSP2833x Peripheral Structures"; + +hotmenu All_Peripherals_Regs() +{ + GEL_WatchAdd("AdcRegs"); + GEL_WatchAdd("AdcMirror"); + GEL_WatchAdd("CsmRegs"); + GEL_WatchAdd("CsmPwl"); + GEL_WatchAdd("CpuTimer0Regs"); + GEL_WatchAdd("CpuTimer1Regs"); + GEL_WatchAdd("CpuTimer2Regs"); + GEL_WatchAdd("DevEmuRegs"); + GEL_WatchAdd("DmaRegs"); + GEL_WatchAdd("ECanaRegs"); + GEL_WatchAdd("ECanaMboxes"); + GEL_WatchAdd("ECanaLAMRegs"); + GEL_WatchAdd("ECanaMOTSRegs"); + GEL_WatchAdd("ECanbRegs"); + GEL_WatchAdd("ECanbMboxes"); + GEL_WatchAdd("ECanbLAMRegs"); + GEL_WatchAdd("ECanbMOTSRegs"); + GEL_WatchAdd("EPwm1Regs"); + GEL_WatchAdd("EPwm2Regs"); + GEL_WatchAdd("EPwm3Regs"); + GEL_WatchAdd("EPwm4Regs"); + GEL_WatchAdd("EPwm5Regs"); + GEL_WatchAdd("EPwm6Regs"); + GEL_WatchAdd("ECap1Regs"); + GEL_WatchAdd("ECap2Regs"); + GEL_WatchAdd("ECap3Regs"); + GEL_WatchAdd("ECap4Regs"); + GEL_WatchAdd("ECap5Regs"); + GEL_WatchAdd("ECap6Regs"); + GEL_WatchAdd("EQep1Regs"); + GEL_WatchAdd("EQep2Regs"); + GEL_WatchAdd("FlashRegs"); + GEL_WatchAdd("XIntruptRegs"); + GEL_WatchAdd("FlashRegs"); + GEL_WatchAdd("GpioCtrlRegs"); + GEL_WatchAdd("GpioDataRegs"); + GEL_WatchAdd("GpioIntRegs"); + GEL_WatchAdd("I2caRegs"); + GEL_WatchAdd("McbspaRegs"); + GEL_WatchAdd("McbspbRegs"); + GEL_WatchAdd("PartIdRegs"); + GEL_WatchAdd("PieCtrlRegs"); + GEL_WatchAdd("PieVectTable"); + GEL_WatchAdd("SciaRegs"); + GEL_WatchAdd("ScibRegs"); + GEL_WatchAdd("ScicRegs"); + GEL_WatchAdd("SpiaRegs"); + GEL_WatchAdd("SysCtrlRegs"); + GEL_WatchAdd("XintfRegs"); +} +hotmenu _______________________() {} +hotmenu ADC_Regs() +{ + GEL_WatchAdd("AdcRegs"); + GEL_WatchAdd("AdcMirror"); +} +hotmenu Code_Security_Module_Regs() +{ + GEL_WatchAdd("CsmRegs"); + GEL_WatchAdd("CsmPwl"); +} +hotmenu CPU_Timer0_Regs() +{ + GEL_WatchAdd("CpuTimer0Regs"); +} +hotmenu CPU_Timer1_Regs() +{ + GEL_WatchAdd("CpuTimer1Regs"); +} +hotmenu CPU_Timer2_Regs() +{ + GEL_WatchAdd("CpuTimer2Regs"); +} +hotmenu Device_Emulation_Regs() +{ + GEL_WatchAdd("DevEmuRegs"); +} +hotmenu DMA_Regs() +{ + GEL_WatchAdd("DMARegs"); +} +hotmenu eCANA_Regs() +{ + GEL_WatchAdd("ECanaRegs"); + GEL_WatchAdd("ECanaMboxes"); + GEL_WatchAdd("ECanaLAMRegs"); + GEL_WatchAdd("ECanaMOTSRegs"); +} +hotmenu eCANB_Regs() +{ + GEL_WatchAdd("ECanbRegs"); + GEL_WatchAdd("ECanbMboxes"); + GEL_WatchAdd("ECanbLAMRegs"); + GEL_WatchAdd("ECanbMOTSRegs"); +} +hotmenu EPWM1_Regs() +{ + GEL_WatchAdd("EPwm1Regs"); +} +hotmenu EPWM2_Regs() +{ + GEL_WatchAdd("EPwm2Regs"); +} +hotmenu EPWM3_Regs() +{ + GEL_WatchAdd("EPwm3Regs"); +} +hotmenu EPWM4_Regs() +{ + GEL_WatchAdd("EPwm4Regs"); +} +hotmenu EPWM5_Regs() +{ + GEL_WatchAdd("EPwm5Regs"); +} +hotmenu EPWM6_Regs() +{ + GEL_WatchAdd("EPwm6Regs"); +} +hotmenu ECAP1_Regs() +{ + GEL_WatchAdd("ECap1Regs"); +} +hotmenu ECAP2_Regs() +{ + GEL_WatchAdd("ECap2Regs"); +} +hotmenu ECAP3_Regs() +{ + GEL_WatchAdd("ECap3Regs"); +} +hotmenu ECAP4_Regs() +{ + GEL_WatchAdd("ECap4Regs"); +} +hotmenu ECAP5_Regs() +{ + GEL_WatchAdd("ECap5Regs"); +} +hotmenu ECAP6_Regs() +{ + GEL_WatchAdd("ECap6Regs"); +} +hotmenu EQEP1_Regs() +{ + GEL_WatchAdd("EQep1Regs"); +} +hotmenu EQEP2_Regs() +{ + GEL_WatchAdd("EQep2Regs"); +} +hotmenu External_Interface_Regs() +{ + GEL_WatchAdd("XintfRegs"); +} +hotmenu External_Interrupt_Regs() +{ + GEL_WatchAdd("XIntruptRegs"); +} +hotmenu Flash_and_OTP_Regs() +{ + GEL_WatchAdd("FlashRegs"); +} +hotmenu GPIO_CTRL_Regs() +{ + GEL_WatchAdd("GpioCtrlRegs"); +} +hotmenu GPIO_DATA_Regs() +{ + GEL_WatchAdd("GpioDataRegs"); +} +hotmenu GPIO_INT_Regs() +{ + GEL_WatchAdd("GpioIntRegs"); +} +hotmenu I2CA_Regs() +{ + GEL_WatchAdd("I2caRegs"); +} +hotmenu McBSPA_Regs() +{ + GEL_WatchAdd("McbspaRegs"); +} +hotmenu McBSPB_Regs() +{ + GEL_WatchAdd("McbspbRegs"); +} +hotmenu PartId_Regs() +{ + GEL_WatchAdd("PartIdRegs"); +} +hotmenu PIE_Control_Regs() +{ + GEL_WatchAdd("PieCtrlRegs"); +} +hotmenu SCIA_Regs() +{ + GEL_WatchAdd("SciaRegs"); +} +hotmenu SCIB_Regs() +{ + GEL_WatchAdd("ScibRegs"); +} +hotmenu SPIA_Regs() +{ + GEL_WatchAdd("SpiaRegs"); +} +hotmenu System_and_Control_Regs() +{ + GEL_WatchAdd("SysCtrlRegs"); +} + + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + + + + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Adc.h b/v120/DSP2833x_headers/include/DSP2833x_Adc.h new file mode 100644 index 0000000..5c8467a --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Adc.h @@ -0,0 +1,264 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; // ADC Control 1 + union ADCTRL2_REG ADCTRL2; // ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; // Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; // Autosequence status register + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; // ADC Control 3 + union ADCST_REG ADCST; // ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; // Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register +}; + + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of DSP2833x_ADC_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..3475801 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h @@ -0,0 +1,190 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// CPU Timer Register Bit Definitions: +// +// +// TCR: Control register bit definitions: +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// TPR: Pre-scale low bit definitions: +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// TPRH: Pre-scale high bit definitions: +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// TIM, TIMH: Timer register definitions: +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// PRD, PRDH: Period register definitions: +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +//--------------------------------------------------------------------------- +// CPU Timer Register File: +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +//--------------------------------------------------------------------------- +// CPU Timer Support Variables: +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +//--------------------------------------------------------------------------- +// Function prototypes and external definitions: +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// Usefull Timer Operations: +// +// Start Timer: +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// Stop Timer: +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. + +// Start Timer: +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + + +// Stop Timer: +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DMA.h b/v120/DSP2833x_headers/include/DSP2833x_DMA.h new file mode 100644 index 0000000..e8b0d59 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DMA.h @@ -0,0 +1,295 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Channel MODE register bit definitions: +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single burst transfer + // 1 first interrupt triggers burst, continue until transfer count is zero + Uint16 CONTINUOUS:1; // 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap counter + // 1 sync signal controls destination wrap counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +//---------------------------------------------------- +// Channel CONTROL register bit definitions: +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +//---------------------------------------------------- +// DMACTRL register bit definitions: +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +//---------------------------------------------------- +// DEBUGCTRL register bit definitions: +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYCTRL1 register bit definitions: +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYSTAT register bit definitions: +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active and interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// Burst Size +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// Burst Count +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + + + +//---------------------------------------------------- +// DMA Channel Registers: +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +//---------------------------------------------------- +// DMA Registers: +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h new file mode 100644 index 0000000..3a765c6 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h @@ -0,0 +1,97 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: June 2, 2008 11:12:30 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// Device Emulation Register Bit Definitions: +// +// Device Configuration Register Bit Definitions +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 MONPRIV:1; // 20 MONPRIV enable bit + Uint16 rsvd5:1; // 21 reserved + Uint16 EMU0SEL:2; // 23,22 EMU0 Mux select + Uint16 EMU1SEL:2; // 25,24 EMU1 Mux select + Uint16 MCBSPCON:1; // 26 McBSP-B to EMU0/EMU1 pins control + Uint16 rsvd6:5; // 31:27 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// CLASSID +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// PARTID +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + + + +//--------------------------------------------------------------------------- +// Device Emulation Register References & Function Declarations: +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Device.h b/v120/DSP2833x_headers/include/DSP2833x_Device.h new file mode 100644 index 0000000..027aec2 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Device.h @@ -0,0 +1,366 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define TARGET 1 +//--------------------------------------------------------------------------- +// User To Select Target Device: + +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28332 0 // Selects '28332/'28232 + + +//--------------------------------------------------------------------------- +// Common CPU Definitions: +// + +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + + + +//--------------------------------------------------------------------------- +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// + +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + + } qua; + + unsigned short all; + +} BAITE; + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bitA: 1; + unsigned int bitB: 1; + unsigned int bitC: 1; + unsigned int bitD: 1; + unsigned int bitE: 1; + unsigned int bitF: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + + } byt; + + int all; + +} WORDE; + +typedef union +{ + struct + { + unsigned int bit00: 1; + unsigned int bit01: 1; + unsigned int bit02: 1; + unsigned int bit03: 1; + unsigned int bit04: 1; + unsigned int bit05: 1; + unsigned int bit06: 1; + unsigned int bit07: 1; + unsigned int bit08: 1; + unsigned int bit09: 1; + unsigned int bit0A: 1; + unsigned int bit0B: 1; + unsigned int bit0C: 1; + unsigned int bit0D: 1; + unsigned int bit0E: 1; + unsigned int bit0F: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + unsigned int bit16: 1; + unsigned int bit17: 1; + unsigned int bit18: 1; + unsigned int bit19: 1; + unsigned int bit1A: 1; + unsigned int bit1B: 1; + unsigned int bit1C: 1; + unsigned int bit1D: 1; + unsigned int bit1E: 1; + unsigned int bit1F: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + unsigned int quad_4 :4; + unsigned int quad_5 :4; + unsigned int quad_6 :4; + unsigned int quad_7 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + unsigned int byte_2 :8; + unsigned int byte_3 :8; + + } byt; + + struct + { + unsigned int word_0 :16; + unsigned int word_1 :16; + + } wrd; + + unsigned long all; + +} LONGE; + +#define XCLKIN 30000000 // external oscillator frequency +extern long SYSCLKOUT, LSPCLK, HSPCLK; + +#define LOWORD(l)((short int)( (long int)(l) &0xFFFF)) +#define HIWORD(l)((short int)(((long int)(l)>>16)&0xFFFF)) + +#define LOBYTE(w)((char)( (short int)(w) &0xFF)) +#define HIBYTE(w)((char)(((short int)(w)>>8)&0xFF)) + +#define BYTE3(l)((char)(((long int)(l)>>24)&0xFF)) +#define BYTE2(l)((char)(((long int)(l)>>16)&0xFF)) +#define BYTE1(l)((char)(((long int)(l)>> 8)&0xFF)) +#define BYTE0(l)((char)( (long int)(l) &0xFF)) + +//--------------------------------------------------------------------------- +// Include All Peripheral Header Files: +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_McBSP.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + +#if DSP28_28335 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECan.h b/v120/DSP2833x_headers/include/DSP2833x_ECan.h new file mode 100644 index 0000000..65988ca --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECan.h @@ -0,0 +1,1161 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* --------------------------------------------------- */ +/* eCAN Control & Status Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Mailbox enable register (CANME) bit definitions */ +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +/* eCAN Mailbox direction register (CANMD) bit definitions */ +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx + +}; + +/* Allow access to the bit fields or entire register */ +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +/* eCAN Transmit Request Set register (CANTRS) bit definitions */ +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +/* eCAN Transmit Request Reset register (CANTRR) bit definitions */ +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +/* eCAN Transmit Acknowledge register (CANTA) bit definitions */ +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */ +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +/* eCAN Received Message Pending register (CANRMP) bit definitions */ +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +/* eCAN Received Message Lost register (CANRML) bit definitions */ +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +/* eCAN Remote Frame Pending register (CANRFP) bit definitions */ +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */ +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +/* Allow access to the bit fields or entire register */ +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + + +/* eCAN Master Control register (CANMC) bit definitions */ +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +/* eCAN Bit -timing configuration register (CANBTC) bit definitions */ +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +/* eCAN Error & Status register (CANES) bit definitions */ +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + + +/* eCAN Transmit Error Counter register (CANTEC) bit definitions */ +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +/* eCAN Receive Error Counter register (CANREC) bit definitions */ +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */ +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */ +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + + +/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */ +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + + +/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */ +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */ +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + + +/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */ +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + + +/* eCAN TX I/O Control Register (CANTIOC) bit definitions */ +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +/* eCAN RX I/O Control Register (CANRIOC) bit definitions */ +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + + +/* eCAN Time-out Control register (CANTOC) bit definitions */ +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + + +/* eCAN Time-out Status register (CANTOS) bit definitions */ +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +/**************************************/ +/* eCAN Control & Status register file */ +/**************************************/ + +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status + +}; + +/* --------------------------------------------------- */ +/* eCAN Mailbox Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Message ID (MSGID) bit definitions */ +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +/* eCAN Message Control Register (MSGCTRL) bit definitions */ +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +/* eCAN Message Data Register low (MDR_L) word definitions */ +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_L) byte definitions */ +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + + +/* Allow access to the bit fields or entire register */ + +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + + + +/* eCAN Message Data Register high (MDR_H) word definitions */ +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_H) byte definitions */ +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +/* Allow access to the bit fields or entire register */ +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +/**************************************/ +/* eCAN Mailboxes */ +/**************************************/ + +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +/* eCAN Local Acceptance Mask (LAM) bit definitions */ +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +/* Allow access to the bit fields or entire register */ +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + + +/**************************************/ +/* eCAN Local Acceptance Masks */ +/**************************************/ + +/* eCAN LAM File */ +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +/* Mailbox MOTS File */ + +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +/* Mailbox MOTO File */ + +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + + +//--------------------------------------------------------------------------- +// eCAN External References & Function Declarations: +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECap.h b/v120/DSP2833x_headers/include/DSP2833x_ECap.h new file mode 100644 index 0000000..b82bd7f --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECap.h @@ -0,0 +1,151 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture control register 1 bit definitions */ +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + + +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +//---------------------------------------------------- +// Capture control register 2 bit definitions */ +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + + +//---------------------------------------------------- +// ECAP interrupt enable register bit definitions */ +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +//---------------------------------------------------- +// ECAP interrupt flag register bit definitions */ +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + + +//---------------------------------------------------- + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_EPwm.h b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h new file mode 100644 index 0000000..9195752 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h @@ -0,0 +1,423 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Time base control register bit definitions */ +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +//---------------------------------------------------- +// Time base status register bit definitions */ +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +//---------------------------------------------------- +// Compare control register bit definitions */ +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier register bit definitions */ +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier SW force register bit definitions */ +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier continuous SW force register bit definitions */ +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + + +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +//---------------------------------------------------- +// Dead-band generator control register bit definitions +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone select register bit definitions +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone flag register bit definitions */ +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag clear register bit definitions */ +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag force register bit definitions */ +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger select register bit definitions */ +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger pre-scale register bit definitions */ +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Flag register bit definitions */ +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger Clear register bit definitions */ +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Force register bit definitions */ +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; +//---------------------------------------------------- +// PWM chopper control register bit definitions */ +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + + +struct TBPHS_HRPWM_REG { // bits description + Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) + Uint16 TBPHS; // 31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_EQep.h b/v120/DSP2833x_headers/include/DSP2833x_EQep.h new file mode 100644 index 0000000..c330165 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_EQep.h @@ -0,0 +1,242 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture decoder control register bit definitions */ +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + + +//---------------------------------------------------- +// QEP control register bit definitions */ +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Quadrature capture control register bit definitions */ +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + + + +//---------------------------------------------------- +// Position compare control register bit definitions */ +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt control register bit definitions */ +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + + +//---------------------------------------------------- +// QEP interrupt status register bit definitions */ +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt force register bit definitions */ +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +//---------------------------------------------------- +// QEP status register bit definitions */ +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +//---------------------------------------------------- + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Gpio.h b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h new file mode 100644 index 0000000..5759c81 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h @@ -0,0 +1,391 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// GPIO A control register bit definitions */ +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO B control register bit definitions */ +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A Qual/MUX select register bit definitions */ +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */ +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + + + + +//---------------------------------------------------- +// GPIO Xint1/XINT2/XNMI select register bit definitions */ +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) + union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) + union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63) + union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63) + union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95) + union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95) + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select +}; + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_I2c.h b/v120/DSP2833x_headers/include/DSP2833x_I2c.h new file mode 100644 index 0000000..382c12d --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_I2c.h @@ -0,0 +1,193 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//---------------------------------------------------- +// I2C interrupt vector register bit definitions */ +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +//---------------------------------------------------- +// I2C interrupt mask register bit definitions */ +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +//---------------------------------------------------- +// I2C status register bit definitions */ +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + + +//---------------------------------------------------- +// I2C mode control register bit definitions */ +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +//---------------------------------------------------- +// I2C pre-scaler register bit definitions */ +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + + +//---------------------------------------------------- +// TX FIFO control register bit definitions */ +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved + +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +//---------------------------------------------------- +// RX FIFO control register bit definitions */ +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + + +//---------------------------------------------------- + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + Uint16 rsvd1; // reserved + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct I2C_REGS I2caRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h new file mode 100644 index 0000000..05e4af9 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h @@ -0,0 +1,715 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// McBSP Individual Register Bit Definitions: +// +// McBSP DRR2 register bit definitions: +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// McBSP DRR1 register bit definitions: +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// McBSP DXR2 register bit definitions: +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// McBSP DXR1 register bit definitions: +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// SPCR2 control register bit definitions: +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// SPCR1 control register bit definitions: +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 ABIS:1; // 6 ABIS mode select + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// RCR2 control register bit definitions: +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// RCR1 control register bit definitions: +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// XCR2 control register bit definitions: + +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// XCR1 control register bit definitions: +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// SRGR2 Sample rate generator control register bit definitions: +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// SRGR1 control register bit definitions: +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// MCR2 Multichannel control register bit definitions: +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// MCR1 Multichannel control register bit definitions: +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// RCERA control register bit definitions: +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// RCERB control register bit definitions: +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// XCERA control register bit definitions: +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// XCERB control register bit definitions: +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// PCR control register bit definitions: +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// RCERC control register bit definitions: +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// RCERD control register bit definitions: +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// XCERC control register bit definitions: +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// XCERD control register bit definitions: +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// RCERE control register bit definitions: +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// RCERF control register bit definitions: +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// XCERF control register bit definitions: +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// RCERG control register bit definitions: +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// XCERG control register bit definitions: +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// XCERH control register bit definitions: +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + + +// McBSP Interrupt enable register for RINT/XINT +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// McBSP Register File: +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT + Uint16 rsvd2; // reserved +}; + +//--------------------------------------------------------------------------- +// McBSP External References & Function Declarations: +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h new file mode 100644 index 0000000..1ab6e9d --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h @@ -0,0 +1,153 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Control Register Bit Definitions: +// +// PIECTRL: Register bit definitions: +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// PIEIER: Register bit definitions: +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// PIEIFR: Register bit definitions: +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// PIEACK: Register bit definitions: +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +//--------------------------------------------------------------------------- +// PIE Control Register File: +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +//--------------------------------------------------------------------------- +// PIE Control Registers External References & Function Declarations: +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieVect.h b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h new file mode 100644 index 0000000..acddab7 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h @@ -0,0 +1,208 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// +// Create a user type called PINT (pointer to interrupt): + +typedef interrupt void(*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + +// Reset is never fetched from this table. +// It will always be fetched from 0x3FFFC0 in +// boot ROM + + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + +// Non-Peripheral Interrupts: + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + +// Group 1 PIE Peripheral Vectors: + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + +// Group 2 PIE Peripheral Vectors: + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + +// Group 3 PIE Peripheral Vectors: + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + +// Group 4 PIE Peripheral Vectors: + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + +// Group 5 PIE Peripheral Vectors: + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + +// Group 6 PIE Peripheral Vectors: + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + +// Group 7 PIE Peripheral Vectors: + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + +// Group 8 PIE Peripheral Vectors: + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + +// Group 9 PIE Peripheral Vectors: + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + +// Group 10 PIE Peripheral Vectors: + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + +// Group 11 PIE Peripheral Vectors: + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + +// Group 12 PIE Peripheral Vectors: + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table External References & Function Declarations: +// +extern struct PIE_VECT_TABLE PieVectTable; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Sci.h b/v120/DSP2833x_headers/include/DSP2833x_Sci.h new file mode 100644 index 0000000..7c17822 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Sci.h @@ -0,0 +1,235 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions + +//---------------------------------------------------------- +// SCICCR communication control register bit definitions: +// + +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +//------------------------------------------- +// SCICTL1 control register 1 bit definitions: +// + +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved + +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +//--------------------------------------------- +// SCICTL2 control register 2 bit definitions: +// + +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved + +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +//--------------------------------------------------- +// SCIRXST Receiver status register bit definitions: +// + +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +//---------------------------------------------------- +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions: +// + +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +//-------------------------------------------------- +// SCIPRI Priority control register bit definitions: +// +// + +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +//------------------------------------------------- +// SCI FIFO Transmit register bit definitions: +// +// + +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels + +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +//------------------------------------------------ +// SCI FIFO recieve register bit definitions: +// +// + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// SCI FIFO control register bit definitions: +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SCI Register File: +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Spi.h b/v120/DSP2833x_headers/include/DSP2833x_Spi.h new file mode 100644 index 0000000..1325c59 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Spi.h @@ -0,0 +1,183 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: +// +// SPI FIFO Transmit register bit definitions: +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO recieve register bit definitions: +// +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO control register bit definitions: +// +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +//--------------------------------------------- +// SPI configuration register bit definitions: +// +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +//------------------------------------------------- +// SPI operation control register bit definitions: +// +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +//-------------------------------------- +// SPI status register bit definitions: +// +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +//------------------------------------------------ +// SPI priority control register bit definitions: +// +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SPI Register File: +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h new file mode 100644 index 0000000..f8bc343 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h @@ -0,0 +1,383 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// System Control Individual Register Bit Definitions: +// + + +// PLL Status Register +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// High speed peripheral clock register bit definitions: +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// Low speed peripheral clock register bit definitions: +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// Peripheral clock control register 0 bit definitions: +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// Peripheral clock control register 1 bit definitions: +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + + +// Peripheral clock control register 2 bit definitions: +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + + + +// PLL control register bit definitions: +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// Low Power Mode 0 control register bit definitions: +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// Dual-mapping configuration register bit definitions: +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +//--------------------------------------------------------------------------- +// System Control Register File: +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + Uint16 SCSR; // 18: System control and status register + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + Uint16 WDCR; // 25: WD timer control register + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + + +/* --------------------------------------------------- */ +/* CSM Registers */ +/* */ +/* ----------------------------------------------------*/ + +/* CSM Status & Control register bit definitions */ +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit + +}; + +/* Allow access to the bit fields or entire register */ +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +/* CSM Register File */ +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +/* Password locations */ +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + + + +/* Flash Registers */ + +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + + +/* Flash Option Register bit definitions */ +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +/* Flash Power Modes Register bit definitions */ +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + + +/* Flash Status Register bit definitions */ +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +/* Flash Sleep to Standby Wait Counter Register bit definitions */ +struct FSTDBYWAIT_BITS { // bit description + Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +/* Flash Standby to Active Wait Counter Register bit definitions */ +struct FACTIVEWAIT_BITS { // bit description + Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +/* Bank Read Access Wait State Register bit definitions */ +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +/* OTP Read Access Wait State Register bit definitions */ +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register + union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +//--------------------------------------------------------------------------- +// System Control External References & Function Declarations: +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h new file mode 100644 index 0000000..6f860f6 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + + + + +//--------------------------------------------------------------------------- +// External Interrupt Register File: +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +//--------------------------------------------------------------------------- +// External Interrupt References & Function Declarations: +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/v120/DSP2833x_headers/include/DSP2833x_Xintf.h b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h new file mode 100644 index 0000000..cb68744 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h @@ -0,0 +1,120 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 20, 2007 16:34:08 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +// XINTF timing register bit definitions: +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// XINTF control register bit definitions: +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// XINTF bank switching register bit definitions: +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// XINTF Register File: +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +//--------------------------------------------------------------------------- +// XINTF External References & Function Declarations: +// +extern volatile struct XINTF_REGS XintfRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..d7cd332 --- /dev/null +++ b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,444 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: June 2, 2008 11:12:33 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + + + + + + + +