Изменили блок памяти RAM в соответствие с диаграммой на странице 571 технического описания GD32F403_User_Manual. После синтеза quartus распознал блок как асинхронную память. Вывели на светодиоды синхросигналы из блока PLL для проверки на осциллографе.
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@ -121,6 +121,40 @@ applicable agreement for further details.
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(annotation_block (location)(rect 1320 40 1376 56))
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)
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(pin
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(output)
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(rect 1144 64 1320 80)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8))
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(line (pt 52 4)(pt 78 4))
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(line (pt 52 12)(pt 78 12))
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(line (pt 52 12)(pt 52 4))
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(line (pt 78 4)(pt 82 8))
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 1320 64 1376 80))
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)
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(pin
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||||
(output)
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(rect 1144 88 1320 104)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8))
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(line (pt 52 4)(pt 78 4))
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(line (pt 52 12)(pt 78 12))
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(line (pt 52 12)(pt 52 4))
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(line (pt 78 4)(pt 82 8))
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 1320 88 1376 104))
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)
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(pin
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(bidir)
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(rect 368 232 544 248)
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@ -206,9 +240,9 @@ applicable agreement for further details.
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)
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)
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(symbol
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||||
(rect 952 176 1152 352)
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||||
(rect 952 176 1152 384)
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(text "RAM" (rect 5 0 28 12)(font "Arial" ))
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(text "inst1" (rect 8 160 31 172)(font "Arial" ))
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(text "inst3" (rect 8 192 31 204)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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@ -226,38 +260,52 @@ applicable agreement for further details.
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(port
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||||
(pt 0 64)
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(input)
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(text "wr0" (rect 0 0 16 12)(font "Arial" ))
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(text "wr0" (rect 21 59 37 71)(font "Arial" ))
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(text "we0" (rect 0 0 18 12)(font "Arial" ))
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(text "we0" (rect 21 59 39 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "clk0" (rect 0 0 20 12)(font "Arial" ))
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(text "clk0" (rect 21 75 41 87)(font "Arial" ))
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(text "oe0" (rect 0 0 17 12)(font "Arial" ))
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(text "oe0" (rect 21 75 38 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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(port
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(input)
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(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
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(text "address1[7..0]" (rect 21 91 91 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 3))
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(text "ce0" (rect 21 91 38 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96))
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(port
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(pt 0 112)
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(input)
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(text "wr1" (rect 0 0 16 12)(font "Arial" ))
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(text "wr1" (rect 21 107 37 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112))
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(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
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(text "address1[7..0]" (rect 21 107 91 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 3))
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)
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(port
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(pt 0 128)
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(input)
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(text "clk1" (rect 0 0 20 12)(font "Arial" ))
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(text "clk1" (rect 21 123 41 135)(font "Arial" ))
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(text "we1" (rect 0 0 18 12)(font "Arial" ))
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(text "we1" (rect 21 123 39 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128))
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)
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(port
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(pt 0 144)
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(input)
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(text "oe1" (rect 0 0 17 12)(font "Arial" ))
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(text "oe1" (rect 21 139 38 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144))
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)
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(port
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(pt 0 160)
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(input)
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(text "ce1" (rect 0 0 17 12)(font "Arial" ))
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(text "ce1" (rect 21 155 38 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160))
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)
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(port
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(pt 200 32)
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(bidir)
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@ -273,7 +321,7 @@ applicable agreement for further details.
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(line (pt 200 48)(pt 184 48)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 184 160))
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(rectangle (rect 16 16 184 192))
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)
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)
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(connector
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@ -302,34 +350,10 @@ applicable agreement for further details.
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(pt 784 136)
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(pt 832 136)
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)
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(connector
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(pt 832 192)
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(pt 848 192)
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)
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(connector
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(pt 832 136)
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(pt 832 192)
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)
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(connector
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(pt 544 272)
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(pt 848 272)
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)
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(connector
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(pt 544 256)
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(pt 560 256)
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)
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(connector
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(pt 560 256)
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(pt 848 256)
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)
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(connector
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(pt 608 48)
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(pt 608 152)
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)
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(connector
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(pt 608 152)
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(pt 608 624)
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)
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(connector
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(pt 608 48)
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(pt 632 48)
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@ -338,36 +362,6 @@ applicable agreement for further details.
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(pt 752 48)
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(pt 1144 48)
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)
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(connector
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(pt 544 224)
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(pt 592 224)
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(bus)
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)
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(connector
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(pt 592 224)
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(pt 952 224)
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(bus)
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)
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(connector
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(pt 936 240)
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(pt 936 160)
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(bus)
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)
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(connector
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(pt 544 240)
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(pt 576 240)
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(bus)
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)
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(connector
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(pt 576 240)
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(pt 936 240)
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(bus)
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)
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(connector
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(pt 936 160)
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(pt 1168 160)
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(bus)
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)
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(connector
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(pt 1168 160)
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(pt 1168 208)
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@ -379,10 +373,109 @@ applicable agreement for further details.
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(bus)
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)
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(connector
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(pt 544 224)
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(pt 592 224)
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(bus)
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)
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(connector
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(pt 592 224)
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(pt 952 224)
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(bus)
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)
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(connector
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(pt 952 208)
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(pt 832 208)
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)
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(connector
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(pt 544 256)
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(pt 560 256)
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)
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(connector
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(pt 560 256)
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(pt 952 256)
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)
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(connector
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(pt 544 272)
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(pt 904 272)
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)
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(connector
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(pt 904 272)
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(pt 904 240)
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)
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(connector
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(pt 952 240)
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(pt 904 240)
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)
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(connector
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(pt 920 288)
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(pt 544 288)
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(pt 848 288)
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)
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(connector
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(pt 920 288)
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(pt 920 272)
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)
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(connector
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(pt 920 272)
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(pt 952 272)
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)
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(connector
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(pt 888 240)
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(pt 888 160)
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(bus)
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)
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(connector
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(pt 1168 160)
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(pt 888 160)
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(bus)
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)
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(connector
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(pt 544 240)
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(pt 576 240)
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(bus)
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)
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(connector
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(pt 576 240)
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(pt 888 240)
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(bus)
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)
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(connector
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(pt 832 72)
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(pt 1144 72)
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)
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(connector
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(pt 832 136)
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(pt 832 72)
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)
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(connector
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(pt 784 152)
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(pt 856 152)
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)
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(connector
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(pt 856 152)
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(pt 856 96)
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)
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(connector
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(pt 856 96)
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(pt 1144 96)
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)
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(connector
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(pt 832 208)
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(pt 832 304)
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)
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(connector
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(pt 832 304)
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(pt 608 304)
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)
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(connector
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(pt 608 152)
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(pt 608 304)
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)
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(connector
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(pt 608 304)
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(pt 608 624)
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)
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(junction (pt 608 152))
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(junction (pt 592 224))
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(junction (pt 560 256))
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(junction (pt 576 240))
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(junction (pt 608 304))
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@ -99,4 +99,8 @@ set_location_assignment PIN_217 -to nOE
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set_location_assignment PIN_218 -to nWE
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set_location_assignment PIN_219 -to nCE
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set_location_assignment PIN_31 -to FPGA_CLK
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set_location_assignment PIN_167 -to FPGA_LED_2
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set_location_assignment PIN_168 -to FPGA_LED_3
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_2
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_3
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -20,9 +20,9 @@ applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 216 192)
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(rect 16 16 216 224)
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(text "RAM" (rect 5 0 29 12)(font "Arial" ))
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(text "inst" (rect 8 160 20 172)(font "Arial" ))
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(text "inst" (rect 8 192 20 204)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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@ -40,38 +40,52 @@ applicable agreement for further details.
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(port
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||||
(pt 0 64)
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||||
(input)
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(text "wr0" (rect 0 0 14 12)(font "Arial" ))
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(text "wr0" (rect 21 59 35 71)(font "Arial" ))
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(text "we0" (rect 0 0 15 12)(font "Arial" ))
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(text "we0" (rect 21 59 36 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "clk0" (rect 0 0 15 12)(font "Arial" ))
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(text "clk0" (rect 21 75 36 87)(font "Arial" ))
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(text "oe0" (rect 0 0 14 12)(font "Arial" ))
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(text "oe0" (rect 21 75 35 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
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(text "address1[7..0]" (rect 21 91 76 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 3))
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(text "ce0" (rect 0 0 14 12)(font "Arial" ))
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(text "ce0" (rect 21 91 35 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "wr1" (rect 0 0 12 12)(font "Arial" ))
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(text "wr1" (rect 21 107 33 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 1))
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(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
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(text "address1[7..0]" (rect 21 107 76 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 3))
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)
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(port
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(pt 0 128)
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(input)
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(text "clk1" (rect 0 0 14 12)(font "Arial" ))
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(text "clk1" (rect 21 123 35 135)(font "Arial" ))
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(text "we1" (rect 0 0 14 12)(font "Arial" ))
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(text "we1" (rect 21 123 35 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128)(line_width 1))
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)
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(port
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(pt 0 144)
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(input)
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(text "oe1" (rect 0 0 12 12)(font "Arial" ))
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(text "oe1" (rect 21 139 33 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144)(line_width 1))
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)
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(port
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(pt 0 160)
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(input)
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(text "ce1" (rect 0 0 12 12)(font "Arial" ))
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(text "ce1" (rect 21 155 33 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 1))
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)
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(port
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(pt 200 32)
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(bidir)
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@ -87,6 +101,6 @@ applicable agreement for further details.
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(line (pt 200 48)(pt 184 48)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 184 160)(line_width 1))
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(rectangle (rect 16 16 184 192)(line_width 1))
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)
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)
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@ -10,13 +10,15 @@ entity RAM is
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data0 : inout std_logic_vector(7 downto 0);
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address0 : in std_logic_vector(7 downto 0);
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wr0 : in std_logic;
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clk0 : in std_logic;
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we0 : in std_logic;
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oe0 : in std_logic;
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ce0 : in std_logic;
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data1 : inout std_logic_vector(7 downto 0);
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address1 : in std_logic_vector(7 downto 0);
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wr1 : in std_logic;
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clk1 : in std_logic
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we1 : in std_logic;
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oe1 : in std_logic;
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ce1 : in std_logic
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);
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end entity;
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@ -25,46 +27,134 @@ architecture behavorial of RAM is
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type mem is array (255 downto 0) of std_logic_vector(7 downto 0);
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signal memory : mem;
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signal clk0Prev : std_logic := '0';
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signal clk1Prev : std_logic := '0';
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signal we0Prev : std_logic := '0';
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signal oe0Prev : std_logic := '0';
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signal ce0Prev : std_logic := '0';
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signal we1Prev : std_logic := '0';
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signal oe1Prev : std_logic := '0';
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signal ce1Prev : std_logic := '0';
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type MemoryMachine is (Waiting, Writing, Reading);
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signal stateMM0 : MemoryMachine := Waiting;
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signal stateMM1 : MemoryMachine := Waiting;
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begin
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-- автомат для работы с памятью со стороны контроллера
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process(clk)
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variable addr0 : integer range 0 to 255;
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variable addr1 : integer range 0 to 255;
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variable addr : integer range 0 to 255 := 0;
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begin
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if rising_edge(clk) then
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if clk1 = '1' and clk1Prev = '0' then
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addr1 := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов.
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if (wr1 = '0') then
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memory(addr1) <= data1; -- тут уже новое значение переменной addr1
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case stateMM0 is
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when Waiting =>
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if ce0 = '0' and ce0Prev = '1' then
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addr := conv_integer(address0);
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if oe0 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
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stateMM0 <= Reading;
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else
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data1 <= memory(addr1);
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stateMM0 <= Writing;
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end if;
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end if;
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if clk1 = '0' and clk1Prev = '1' then
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data1 <= (others => 'Z');
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end if;
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clk1Prev <= clk1;
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if clk0 = '1' and clk0Prev = '0' then
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addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов.
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if (wr0 = '0') then
|
||||
memory(addr0) <= data0; -- тут уже новое значение переменной addr0
|
||||
else
|
||||
data0 <= memory(addr0);
|
||||
end if;
|
||||
end if;
|
||||
if clk0 = '0' and clk0Prev = '1' then
|
||||
addr := 0;
|
||||
data0 <= (others => 'Z');
|
||||
end if;
|
||||
|
||||
clk0Prev <= clk0;
|
||||
|
||||
when Reading =>
|
||||
data0 <= memory(addr);
|
||||
if oe0 = '1' and oe0Prev = '0' then
|
||||
stateMM0 <= Waiting;
|
||||
elsif ce0 = '1' then
|
||||
stateMM0 <= Waiting;
|
||||
end if;
|
||||
when Writing =>
|
||||
if we0 = '0' and we0Prev = '1' then
|
||||
memory(addr) <= data0;
|
||||
stateMM0 <= Waiting;
|
||||
elsif ce0 = '1' then
|
||||
stateMM0 <= Waiting;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
oe0Prev <= oe0;
|
||||
ce0Prev <= ce0;
|
||||
we0Prev <= we0;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- автомат для работы с памятью со стороны контроллера
|
||||
process(clk)
|
||||
variable addr : integer range 0 to 255 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case stateMM1 is
|
||||
when Waiting =>
|
||||
if ce1 = '0' and ce1Prev = '1' then
|
||||
addr := conv_integer(address1);
|
||||
if oe1 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
|
||||
stateMM1 <= Reading;
|
||||
else
|
||||
stateMM1 <= Writing;
|
||||
end if;
|
||||
else
|
||||
addr := 0;
|
||||
data1 <= (others => 'Z');
|
||||
end if;
|
||||
when Reading =>
|
||||
data1 <= memory(addr);
|
||||
if oe1 = '1' and oe1Prev = '0' then
|
||||
stateMM1 <= Waiting;
|
||||
elsif ce0 = '1' then
|
||||
stateMM1 <= Waiting;
|
||||
end if;
|
||||
when Writing =>
|
||||
if we1 = '0' and we1Prev = '1' then
|
||||
memory(addr) <= data1;
|
||||
stateMM1 <= Waiting;
|
||||
elsif ce0 = '1' then
|
||||
stateMM1 <= Waiting;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
oe1Prev <= oe1;
|
||||
ce1Prev <= ce1;
|
||||
we1Prev <= we1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- process(clk)
|
||||
-- variable addr : integer range 0 to 255;
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if clk = '1' and clkPrev = '0' then
|
||||
-- addr := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов.
|
||||
-- if (wr1 = '0') then
|
||||
-- memory(addr1) <= data1; -- тут уже новое значение переменной addr1
|
||||
-- else
|
||||
-- data1 <= memory(addr1);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if clk1 = '0' and clk1Prev = '1' then
|
||||
-- data1 <= (others => 'Z');
|
||||
-- end if;
|
||||
--
|
||||
-- clk1Prev <= clk1;
|
||||
--
|
||||
-- if clk0 = '1' and clk0Prev = '0' then
|
||||
-- addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов.
|
||||
-- if (wr0 = '0') then
|
||||
-- memory(addr0) <= data0; -- тут уже новое значение переменной addr0
|
||||
-- else
|
||||
-- data0 <= memory(addr0);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if clk0 = '0' and clk0Prev = '1' then
|
||||
-- data0 <= (others => 'Z');
|
||||
-- end if;
|
||||
--
|
||||
-- clk0Prev <= clk0;
|
||||
--
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
end behavorial;
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1 +1 @@
|
||||
d1187c24d5e18b5b14f48701f0f8928b
|
||||
5609c04c14c15587f66e4a304a24bc35
|
||||
Binary file not shown.
Binary file not shown.
@ -1 +1 @@
|
||||
Tue Mar 12 16:24:29 2024
|
||||
Tue Mar 12 17:46:57 2024
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
EDA Netlist Writer report for MainController
|
||||
Tue Mar 12 16:24:29 2024
|
||||
Tue Mar 12 17:46:57 2024
|
||||
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||
|
||||
|
||||
@ -36,7 +36,7 @@ applicable agreement for further details.
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 12 16:24:29 2024 ;
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 12 17:46:57 2024 ;
|
||||
; Revision Name ; MainController ;
|
||||
; Top-level Entity Name ; MainController ;
|
||||
; Family ; Cyclone III ;
|
||||
@ -88,7 +88,7 @@ applicable agreement for further details.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit EDA Netlist Writer
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||
Info: Processing started: Tue Mar 12 16:24:28 2024
|
||||
Info: Processing started: Tue Mar 12 17:46:56 2024
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController
|
||||
Info (204019): Generated file MainController_8_1200mv_85c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file MainController_8_1200mv_0c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
|
||||
@ -99,8 +99,8 @@ Info (204019): Generated file MainController_8_1200mv_0c_vhd_slow.sdo in folder
|
||||
Info (204019): Generated file MainController_min_1200mv_0c_vhd_fast.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file MainController_vhd.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
|
||||
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 4567 megabytes
|
||||
Info: Processing ended: Tue Mar 12 16:24:29 2024
|
||||
Info: Peak virtual memory: 4577 megabytes
|
||||
Info: Processing ended: Tue Mar 12 17:46:57 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,16 +1,16 @@
|
||||
Fitter Status : Successful - Tue Mar 12 16:24:21 2024
|
||||
Fitter Status : Successful - Tue Mar 12 17:46:50 2024
|
||||
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||
Revision Name : MainController
|
||||
Top-level Entity Name : MainController
|
||||
Family : Cyclone III
|
||||
Device : EP3C25Q240C8
|
||||
Timing Models : Final
|
||||
Total logic elements : 34 / 24,624 ( < 1 % )
|
||||
Total combinational functions : 34 / 24,624 ( < 1 % )
|
||||
Dedicated logic registers : 25 / 24,624 ( < 1 % )
|
||||
Total registers : 25
|
||||
Total pins : 21 / 149 ( 14 % )
|
||||
Total logic elements : 95 / 24,624 ( < 1 % )
|
||||
Total combinational functions : 67 / 24,624 ( < 1 % )
|
||||
Dedicated logic registers : 80 / 24,624 ( < 1 % )
|
||||
Total registers : 80
|
||||
Total pins : 23 / 149 ( 15 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 608,256 ( 0 % )
|
||||
Total memory bits : 2,048 / 608,256 ( < 1 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
|
||||
Total PLLs : 0 / 4 ( 0 % )
|
||||
Total PLLs : 1 / 4 ( 25 % )
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Flow report for MainController
|
||||
Tue Mar 12 16:24:29 2024
|
||||
Tue Mar 12 17:46:57 2024
|
||||
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||
|
||||
|
||||
@ -40,22 +40,22 @@ applicable agreement for further details.
|
||||
+----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Mar 12 16:24:29 2024 ;
|
||||
; Flow Status ; Successful - Tue Mar 12 17:46:57 2024 ;
|
||||
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
|
||||
; Revision Name ; MainController ;
|
||||
; Top-level Entity Name ; MainController ;
|
||||
; Family ; Cyclone III ;
|
||||
; Device ; EP3C25Q240C8 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 34 / 24,624 ( < 1 % ) ;
|
||||
; Total combinational functions ; 34 / 24,624 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 25 / 24,624 ( < 1 % ) ;
|
||||
; Total registers ; 25 ;
|
||||
; Total pins ; 21 / 149 ( 14 % ) ;
|
||||
; Total logic elements ; 95 / 24,624 ( < 1 % ) ;
|
||||
; Total combinational functions ; 67 / 24,624 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 80 / 24,624 ( < 1 % ) ;
|
||||
; Total registers ; 80 ;
|
||||
; Total pins ; 23 / 149 ( 15 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
|
||||
; Total memory bits ; 2,048 / 608,256 ( < 1 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 4 ( 0 % ) ;
|
||||
; Total PLLs ; 1 / 4 ( 25 % ) ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
@ -64,7 +64,7 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/12/2024 16:24:14 ;
|
||||
; Start date & time ; 03/12/2024 17:46:43 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; MainController ;
|
||||
+-------------------+---------------------+
|
||||
@ -75,7 +75,7 @@ applicable agreement for further details.
|
||||
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
|
||||
; COMPILER_SIGNATURE_ID ; 30902508249626.171024985402028 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 30902508249626.171025480308064 ; -- ; -- ; -- ;
|
||||
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
|
||||
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
|
||||
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
|
||||
@ -97,12 +97,12 @@ applicable agreement for further details.
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4707 MB ; 00:00:02 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 5391 MB ; 00:00:06 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 4590 MB ; 00:00:01 ;
|
||||
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4712 MB ; 00:00:02 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 5391 MB ; 00:00:05 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 4585 MB ; 00:00:01 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4700 MB ; 00:00:01 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4550 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:09 ; -- ; -- ; 00:00:11 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4565 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="9c3406557f2dade88a26"/>
|
||||
<hash md5_digest_80b="0d51c70841a35edea1b2"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP3C25Q240C8" path="MainController.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,14 +1,14 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Mar 12 16:24:16 2024
|
||||
Analysis & Synthesis Status : Successful - Tue Mar 12 17:46:44 2024
|
||||
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||
Revision Name : MainController
|
||||
Top-level Entity Name : MainController
|
||||
Family : Cyclone III
|
||||
Total logic elements : 34
|
||||
Total combinational functions : 34
|
||||
Dedicated logic registers : 25
|
||||
Total registers : 25
|
||||
Total pins : 21
|
||||
Total logic elements : 102
|
||||
Total combinational functions : 67
|
||||
Dedicated logic registers : 80
|
||||
Total registers : 80
|
||||
Total pins : 23
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Total memory bits : 2,048
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total PLLs : 0
|
||||
Total PLLs : 1
|
||||
|
||||
@ -234,8 +234,8 @@ VCCINT : 163 : power : : 1.2V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 164 : : : : 6 :
|
||||
GND : 165 : gnd : : : :
|
||||
FPGA_LED_1 : 166 : output : 3.3-V LVTTL : : 6 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 167 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 168 : : : : 6 :
|
||||
FPGA_LED_2 : 167 : output : 3.3-V LVTTL : : 6 : Y
|
||||
FPGA_LED_3 : 168 : output : 3.3-V LVTTL : : 6 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 169 : : : : 6 :
|
||||
VCCIO6 : 170 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 171 : : : : 6 :
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'FPGA_CLK'
|
||||
Slack : -3.954
|
||||
TNS : -84.790
|
||||
Slack : 33.637
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'FPGA_CLK'
|
||||
Slack : 0.435
|
||||
Slack : 0.454
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'FPGA_CLK'
|
||||
Slack : -3.000
|
||||
TNS : -40.175
|
||||
Slack : 19.618
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'FPGA_CLK'
|
||||
Slack : -3.662
|
||||
TNS : -77.889
|
||||
Slack : 34.094
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'FPGA_CLK'
|
||||
Slack : 0.384
|
||||
Slack : 0.402
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
|
||||
Slack : -3.000
|
||||
TNS : -40.175
|
||||
Slack : 19.600
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'FPGA_CLK'
|
||||
Slack : -1.072
|
||||
TNS : -20.939
|
||||
Slack : 37.258
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'FPGA_CLK'
|
||||
Slack : 0.179
|
||||
Slack : 0.186
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
|
||||
Slack : -3.000
|
||||
TNS : -35.949
|
||||
Slack : 19.206
|
||||
TNS : 0.000
|
||||
|
||||
------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -16,7 +16,20 @@ source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst
|
||||
source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altsyncram.tdf
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_mux.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_decode.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altrom.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altram.inc
|
||||
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altdpram.inc
|
||||
source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_lkc1.tdf
|
||||
source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_8bi1.tdf
|
||||
design_name = MainController
|
||||
instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
|
||||
instance = comp, \FPGA_LED_2~output\, FPGA_LED_2~output, MainController, 1
|
||||
instance = comp, \FPGA_LED_3~output\, FPGA_LED_3~output, MainController, 1
|
||||
instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1
|
||||
instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1
|
||||
instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1
|
||||
@ -25,10 +38,164 @@ instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1
|
||||
instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1
|
||||
instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1
|
||||
instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1
|
||||
instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
|
||||
instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1
|
||||
instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1
|
||||
instance = comp, \nCE~input\, nCE~input, MainController, 1
|
||||
instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
|
||||
instance = comp, \inst3|ce0Prev\, inst3|ce0Prev, MainController, 1
|
||||
instance = comp, \inst3|addr~5\, inst3|addr~5, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[12]~feeder\, inst3|memory_rtl_0_bypass[12]~feeder, MainController, 1
|
||||
instance = comp, \nWE~input\, nWE~input, MainController, 1
|
||||
instance = comp, \inst3|we0Prev\, inst3|we0Prev, MainController, 1
|
||||
instance = comp, \nOE~input\, nOE~input, MainController, 1
|
||||
instance = comp, \inst3|Selector3~3\, inst3|Selector3~3, MainController, 1
|
||||
instance = comp, \inst3|Selector3~2\, inst3|Selector3~2, MainController, 1
|
||||
instance = comp, \inst3|stateMM0.Writing\, inst3|stateMM0.Writing, MainController, 1
|
||||
instance = comp, \inst3|memory~48\, inst3|memory~48, MainController, 1
|
||||
instance = comp, \inst3|oe0Prev\, inst3|oe0Prev, MainController, 1
|
||||
instance = comp, \inst3|Selector3~0\, inst3|Selector3~0, MainController, 1
|
||||
instance = comp, \inst3|Selector3~1\, inst3|Selector3~1, MainController, 1
|
||||
instance = comp, \inst3|Selector2~0\, inst3|Selector2~0, MainController, 1
|
||||
instance = comp, \inst3|stateMM0.Waiting\, inst3|stateMM0.Waiting, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[12]\, inst3|memory_rtl_0_bypass[12], MainController, 1
|
||||
instance = comp, \inst3|addr[5]\, inst3|addr[5], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[11]~feeder\, inst3|memory_rtl_0_bypass[11]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[11]\, inst3|memory_rtl_0_bypass[11], MainController, 1
|
||||
instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~4\, inst3|addr~4, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[10]\, inst3|memory_rtl_0_bypass[10], MainController, 1
|
||||
instance = comp, \inst3|addr[4]\, inst3|addr[4], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[9]\, inst3|memory_rtl_0_bypass[9], MainController, 1
|
||||
instance = comp, \inst3|memory~37\, inst3|memory~37, MainController, 1
|
||||
instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~2\, inst3|addr~2, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[6]~feeder\, inst3|memory_rtl_0_bypass[6]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[6]\, inst3|memory_rtl_0_bypass[6], MainController, 1
|
||||
instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~3\, inst3|addr~3, MainController, 1
|
||||
instance = comp, \inst3|addr[3]\, inst3|addr[3], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[7]\, inst3|memory_rtl_0_bypass[7], MainController, 1
|
||||
instance = comp, \inst3|addr[2]\, inst3|addr[2], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[5]\, inst3|memory_rtl_0_bypass[5], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[8]\, inst3|memory_rtl_0_bypass[8], MainController, 1
|
||||
instance = comp, \inst3|memory~35\, inst3|memory~35, MainController, 1
|
||||
instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~0\, inst3|addr~0, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[2]~feeder\, inst3|memory_rtl_0_bypass[2]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[2]\, inst3|memory_rtl_0_bypass[2], MainController, 1
|
||||
instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~1\, inst3|addr~1, MainController, 1
|
||||
instance = comp, \inst3|addr[1]\, inst3|addr[1], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[3]\, inst3|memory_rtl_0_bypass[3], MainController, 1
|
||||
instance = comp, \inst3|addr[0]\, inst3|addr[0], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[1]\, inst3|memory_rtl_0_bypass[1], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[4]~feeder\, inst3|memory_rtl_0_bypass[4]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[4]\, inst3|memory_rtl_0_bypass[4], MainController, 1
|
||||
instance = comp, \inst3|memory~34\, inst3|memory~34, MainController, 1
|
||||
instance = comp, \inst3|memory~36\, inst3|memory~36, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[0]\, inst3|memory_rtl_0_bypass[0], MainController, 1
|
||||
instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~7\, inst3|addr~7, MainController, 1
|
||||
instance = comp, \inst3|addr[7]\, inst3|addr[7], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[15]\, inst3|memory_rtl_0_bypass[15], MainController, 1
|
||||
instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
|
||||
instance = comp, \inst3|addr~6\, inst3|addr~6, MainController, 1
|
||||
instance = comp, \inst3|addr[6]\, inst3|addr[6], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[13]~feeder\, inst3|memory_rtl_0_bypass[13]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[13]\, inst3|memory_rtl_0_bypass[13], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[14]\, inst3|memory_rtl_0_bypass[14], MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[16]~feeder\, inst3|memory_rtl_0_bypass[16]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[16]\, inst3|memory_rtl_0_bypass[16], MainController, 1
|
||||
instance = comp, \inst3|memory~38\, inst3|memory~38, MainController, 1
|
||||
instance = comp, \inst3|memory~39\, inst3|memory~39, MainController, 1
|
||||
instance = comp, \inst3|stateMM0.Waiting~_wirecell\, inst3|stateMM0.Waiting~_wirecell, MainController, 1
|
||||
instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1
|
||||
instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
|
||||
instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
|
||||
instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
|
||||
instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
|
||||
instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
|
||||
instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
|
||||
instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0|auto_generated|ram_block1a0\, inst3|memory_rtl_0|auto_generated|ram_block1a0, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[24]~feeder\, inst3|memory_rtl_0_bypass[24]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[24]\, inst3|memory_rtl_0_bypass[24], MainController, 1
|
||||
instance = comp, \inst3|memory~40\, inst3|memory~40, MainController, 1
|
||||
instance = comp, \inst3|Selector4~0\, inst3|Selector4~0, MainController, 1
|
||||
instance = comp, \inst3|stateMM0.Reading\, inst3|stateMM0.Reading, MainController, 1
|
||||
instance = comp, \inst3|Selector74~0\, inst3|Selector74~0, MainController, 1
|
||||
instance = comp, \inst3|data0[7]~reg0\, inst3|data0[7]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[7]~enfeeder\, inst3|data0[7]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[7]~en\, inst3|data0[7]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[23]~feeder\, inst3|memory_rtl_0_bypass[23]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[23]\, inst3|memory_rtl_0_bypass[23], MainController, 1
|
||||
instance = comp, \inst3|memory~41\, inst3|memory~41, MainController, 1
|
||||
instance = comp, \inst3|data0[6]~reg0\, inst3|data0[6]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[6]~enfeeder\, inst3|data0[6]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[6]~en\, inst3|data0[6]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[22]~feeder\, inst3|memory_rtl_0_bypass[22]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[22]\, inst3|memory_rtl_0_bypass[22], MainController, 1
|
||||
instance = comp, \inst3|memory~42\, inst3|memory~42, MainController, 1
|
||||
instance = comp, \inst3|data0[5]~reg0\, inst3|data0[5]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[5]~enfeeder\, inst3|data0[5]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[5]~en\, inst3|data0[5]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[21]~feeder\, inst3|memory_rtl_0_bypass[21]~feeder, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[21]\, inst3|memory_rtl_0_bypass[21], MainController, 1
|
||||
instance = comp, \inst3|memory~43\, inst3|memory~43, MainController, 1
|
||||
instance = comp, \inst3|data0[4]~reg0\, inst3|data0[4]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[4]~enfeeder\, inst3|data0[4]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[4]~en\, inst3|data0[4]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[20]\, inst3|memory_rtl_0_bypass[20], MainController, 1
|
||||
instance = comp, \inst3|memory~44\, inst3|memory~44, MainController, 1
|
||||
instance = comp, \inst3|data0[3]~reg0\, inst3|data0[3]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[3]~enfeeder\, inst3|data0[3]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[3]~en\, inst3|data0[3]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[19]\, inst3|memory_rtl_0_bypass[19], MainController, 1
|
||||
instance = comp, \inst3|memory~45\, inst3|memory~45, MainController, 1
|
||||
instance = comp, \inst3|data0[2]~reg0\, inst3|data0[2]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[2]~enfeeder\, inst3|data0[2]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[2]~en\, inst3|data0[2]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[18]\, inst3|memory_rtl_0_bypass[18], MainController, 1
|
||||
instance = comp, \inst3|memory~46\, inst3|memory~46, MainController, 1
|
||||
instance = comp, \inst3|data0[1]~reg0\, inst3|data0[1]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[1]~enfeeder\, inst3|data0[1]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[1]~en\, inst3|data0[1]~en, MainController, 1
|
||||
instance = comp, \inst3|memory_rtl_0_bypass[17]\, inst3|memory_rtl_0_bypass[17], MainController, 1
|
||||
instance = comp, \inst3|memory~47\, inst3|memory~47, MainController, 1
|
||||
instance = comp, \inst3|data0[0]~reg0\, inst3|data0[0]~reg0, MainController, 1
|
||||
instance = comp, \inst3|data0[0]~enfeeder\, inst3|data0[0]~enfeeder, MainController, 1
|
||||
instance = comp, \inst3|data0[0]~en\, inst3|data0[0]~en, MainController, 1
|
||||
instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1
|
||||
instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
|
||||
instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
|
||||
instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
|
||||
instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
|
||||
instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
|
||||
instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
|
||||
instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
|
||||
instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
|
||||
instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
|
||||
instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
|
||||
instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
|
||||
instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
|
||||
instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
|
||||
instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
|
||||
instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
|
||||
instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
|
||||
instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
|
||||
instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
|
||||
instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
|
||||
instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
|
||||
instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
|
||||
instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
|
||||
instance = comp, \inst2|LessThan0~9\, inst2|LessThan0~9, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~10\, inst2|LessThan0~10, MainController, 1
|
||||
instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1
|
||||
instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1
|
||||
instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1
|
||||
@ -54,55 +221,11 @@ instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1
|
||||
instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1
|
||||
instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1
|
||||
instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1
|
||||
instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
|
||||
instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1
|
||||
instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
|
||||
instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
|
||||
instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
|
||||
instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
|
||||
instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
|
||||
instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
|
||||
instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
|
||||
instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
|
||||
instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
|
||||
instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
|
||||
instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
|
||||
instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
|
||||
instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
|
||||
instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
|
||||
instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
|
||||
instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
|
||||
instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
|
||||
instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
|
||||
instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
|
||||
instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
|
||||
instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
|
||||
instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1
|
||||
instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
|
||||
instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1
|
||||
instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1
|
||||
instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
|
||||
instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
|
||||
instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
|
||||
instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
|
||||
instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
|
||||
instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
|
||||
instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
|
||||
instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
|
||||
instance = comp, \nOE~input\, nOE~input, MainController, 1
|
||||
instance = comp, \nWE~input\, nWE~input, MainController, 1
|
||||
instance = comp, \nCE~input\, nCE~input, MainController, 1
|
||||
instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
|
||||
instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
|
||||
instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
|
||||
instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
|
||||
instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
|
||||
instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
|
||||
instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
|
||||
instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1
|
||||
instance = comp, \inst|altpll_component|auto_generated|pll1\, inst|altpll_component|auto_generated|pll1, MainController, 1
|
||||
instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, MainController, 1
|
||||
instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, MainController, 1
|
||||
|
||||
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Reference in New Issue
Block a user