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Added the compatibility another cores

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Stanislav
2023-05-03 12:18:32 +03:00
parent aa9291d7ba
commit 8550416724
1098 changed files with 118701 additions and 17685 deletions
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IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml
+17 -2
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@@ -993,13 +993,14 @@
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>IP_AXI_ADC_v2.0</xilinx:displayName>
<xilinx:coreRevision>18</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-09-10T09:11:34Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>20</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2023-04-27T15:23:05Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@54e67f7c_ARCHIVE_LOCATION">d:/GITEA/IP/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f9b0e0_ARCHIVE_LOCATION">d:/GITEA/IP/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
@@ -1199,6 +1200,20 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@10fac931_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@704f3371_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@513ab4f0_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3b05f49f_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@9543d56_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5e6706b0_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e6d697b_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3e09642b_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@63cb7369_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@370750c_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@65ee75fc_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4bda784a_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4faf27fd_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ebe40d5_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@25599cd_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@953d961_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@65ba1a1b_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
IP_AXI_INVERTER/IP_AXI_INVERTER_1.0/component.xml
+12 -2
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@@ -1451,6 +1451,7 @@
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
@@ -1458,11 +1459,11 @@
<xilinx:displayName>IP_AXI_INVERTER_v1.0</xilinx:displayName>
<xilinx:vendorDisplayName>S7DNRJ</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://ssevendenergy.com</xilinx:vendorURL>
<xilinx:coreRevision>5</xilinx:coreRevision>
<xilinx:coreRevision>6</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>setcorp:user:IP_AXI_INVERTER:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2021-06-10T13:27:55Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2023-05-03T08:03:05Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ccdc994_ARCHIVE_LOCATION">d:/Projects/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f332270_ARCHIVE_LOCATION">d:/Projects/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
@@ -1527,6 +1528,15 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@48e5f9b1_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66637786_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4da22e32_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7554dd40_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e90aeb_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f6b3f3c_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1da3d9a1_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7019d7c_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@582d89c2_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@547af692_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@29dec428_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e73dc17_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml
+13 -3
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@@ -877,13 +877,14 @@
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>IP_AXI_PWM_v1.0</xilinx:displayName>
<xilinx:coreRevision>7</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-08-12T12:22:11Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>8</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2023-05-03T07:39:26Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3b39cc3d_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@37855da7_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
@@ -946,6 +947,15 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@51fb18ad_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@387cc00b_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2c018a5d_ARCHIVE_LOCATION">d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3159d168_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@699b7e6d_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@791697f5_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6171b2e9_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@550f09a8_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6fa9fc1d_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66a8c848_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5405792_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c527381_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
@@ -953,7 +963,7 @@
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e494fdcc"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c9435b48"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="065aa120"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="3b6845ca"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="9b41a2a2"/>
</xilinx:packagingInfo>
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/362e20292c8426d9.xci
+37
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@@ -0,0 +1,37 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>362e20292c8426d9</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>AckChecker_BusBlock16IN_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="ssevendenergy.com" spirit:library="user" spirit:name="BusBlock16IN" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">AckChecker_BusBlock16IN_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">362e20292c8426d9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">8a237664</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">35</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0.dcp
BIN
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LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_sim_netlist.v
+142
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@@ -0,0 +1,142 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:54 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_sim_netlist.v
// Design : AckChecker_BusBlock16IN_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "BusBlock16IN,Vivado 2019.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(Bus_16IN,
Out0,
Out1,
Out2,
Out3,
Out4,
Out5,
Out6,
Out7,
Out8,
Out9,
Out10,
Out11,
Out12,
Out13,
Out14,
Out15);
input [15:0]Bus_16IN;
output Out0;
output Out1;
output Out2;
output Out3;
output Out4;
output Out5;
output Out6;
output Out7;
output Out8;
output Out9;
output Out10;
output Out11;
output Out12;
output Out13;
output Out14;
output Out15;
wire [15:0]Bus_16IN;
assign Out0 = Bus_16IN[0];
assign Out1 = Bus_16IN[1];
assign Out10 = Bus_16IN[10];
assign Out11 = Bus_16IN[11];
assign Out12 = Bus_16IN[12];
assign Out13 = Bus_16IN[13];
assign Out14 = Bus_16IN[14];
assign Out15 = Bus_16IN[15];
assign Out2 = Bus_16IN[2];
assign Out3 = Bus_16IN[3];
assign Out4 = Bus_16IN[4];
assign Out5 = Bus_16IN[5];
assign Out6 = Bus_16IN[6];
assign Out7 = Bus_16IN[7];
assign Out8 = Bus_16IN[8];
assign Out9 = Bus_16IN[9];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl
+69
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@@ -0,0 +1,69 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:54 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl
-- Design : AckChecker_BusBlock16IN_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
Out0 : out STD_LOGIC;
Out1 : out STD_LOGIC;
Out2 : out STD_LOGIC;
Out3 : out STD_LOGIC;
Out4 : out STD_LOGIC;
Out5 : out STD_LOGIC;
Out6 : out STD_LOGIC;
Out7 : out STD_LOGIC;
Out8 : out STD_LOGIC;
Out9 : out STD_LOGIC;
Out10 : out STD_LOGIC;
Out11 : out STD_LOGIC;
Out12 : out STD_LOGIC;
Out13 : out STD_LOGIC;
Out14 : out STD_LOGIC;
Out15 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "BusBlock16IN,Vivado 2019.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
Out0 <= \^bus_16in\(0);
Out1 <= \^bus_16in\(1);
Out10 <= \^bus_16in\(10);
Out11 <= \^bus_16in\(11);
Out12 <= \^bus_16in\(12);
Out13 <= \^bus_16in\(13);
Out14 <= \^bus_16in\(14);
Out15 <= \^bus_16in\(15);
Out2 <= \^bus_16in\(2);
Out3 <= \^bus_16in\(3);
Out4 <= \^bus_16in\(4);
Out5 <= \^bus_16in\(5);
Out6 <= \^bus_16in\(6);
Out7 <= \^bus_16in\(7);
Out8 <= \^bus_16in\(8);
Out9 <= \^bus_16in\(9);
\^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0);
end STRUCTURE;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:54 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_stub.v
// Design : AckChecker_BusBlock16IN_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "BusBlock16IN,Vivado 2019.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7,
Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15)
/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */;
input [15:0]Bus_16IN;
output Out0;
output Out1;
output Out2;
output Out3;
output Out4;
output Out5;
output Out6;
output Out7;
output Out8;
output Out9;
output Out10;
output Out11;
output Out12;
output Out13;
output Out14;
output Out15;
endmodule
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:54 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_stub.vhdl
-- Design : AckChecker_BusBlock16IN_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
Out0 : out STD_LOGIC;
Out1 : out STD_LOGIC;
Out2 : out STD_LOGIC;
Out3 : out STD_LOGIC;
Out4 : out STD_LOGIC;
Out5 : out STD_LOGIC;
Out6 : out STD_LOGIC;
Out7 : out STD_LOGIC;
Out8 : out STD_LOGIC;
Out9 : out STD_LOGIC;
Out10 : out STD_LOGIC;
Out11 : out STD_LOGIC;
Out12 : out STD_LOGIC;
Out13 : out STD_LOGIC;
Out14 : out STD_LOGIC;
Out15 : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1";
begin
end;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/stats.txt
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NumberHits:7
Timestamp: Wed May 03 08:37:41 UTC 2023
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/620c0a6afb1e6b3a.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>620c0a6afb1e6b3a</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>AckChecker_BusBlock16OUT_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="ssevendenergy.com" spirit:library="user" spirit:name="BusBlock16OUT" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">AckChecker_BusBlock16OUT_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">620c0a6afb1e6b3a</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">33b49d5e</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">35</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0.dcp
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LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:54 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_sim_netlist.v
// Design : AckChecker_BusBlock16OUT_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(Bus_16OUT,
In0,
In1,
In2,
In3,
In4,
In5,
In6,
In7,
In8,
In9,
In10,
In11,
In12,
In13,
In14,
In15,
Mask);
output [15:0]Bus_16OUT;
input In0;
input In1;
input In2;
input In3;
input In4;
input In5;
input In6;
input In7;
input In8;
input In9;
input In10;
input In11;
input In12;
input In13;
input In14;
input In15;
input [15:0]Mask;
wire [15:0]Bus_16OUT;
wire In0;
wire In1;
wire In10;
wire In11;
wire In12;
wire In13;
wire In14;
wire In15;
wire In2;
wire In3;
wire In4;
wire In5;
wire In6;
wire In7;
wire In8;
wire In9;
wire [15:0]Mask;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT U0
(.Bus_16OUT(Bus_16OUT),
.In0(In0),
.In1(In1),
.In10(In10),
.In11(In11),
.In12(In12),
.In13(In13),
.In14(In14),
.In15(In15),
.In2(In2),
.In3(In3),
.In4(In4),
.In5(In5),
.In6(In6),
.In7(In7),
.In8(In8),
.In9(In9),
.Mask(Mask));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT
(Bus_16OUT,
In0,
Mask,
In1,
In2,
In3,
In4,
In5,
In6,
In7,
In8,
In9,
In10,
In11,
In12,
In13,
In14,
In15);
output [15:0]Bus_16OUT;
input In0;
input [15:0]Mask;
input In1;
input In2;
input In3;
input In4;
input In5;
input In6;
input In7;
input In8;
input In9;
input In10;
input In11;
input In12;
input In13;
input In14;
input In15;
wire [15:0]Bus_16OUT;
wire In0;
wire In1;
wire In10;
wire In11;
wire In12;
wire In13;
wire In14;
wire In15;
wire In2;
wire In3;
wire In4;
wire In5;
wire In6;
wire In7;
wire In8;
wire In9;
wire [15:0]Mask;
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[0]_INST_0
(.I0(In0),
.I1(Mask[0]),
.O(Bus_16OUT[0]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[10]_INST_0
(.I0(In10),
.I1(Mask[10]),
.O(Bus_16OUT[10]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[11]_INST_0
(.I0(In11),
.I1(Mask[11]),
.O(Bus_16OUT[11]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[12]_INST_0
(.I0(In12),
.I1(Mask[12]),
.O(Bus_16OUT[12]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[13]_INST_0
(.I0(In13),
.I1(Mask[13]),
.O(Bus_16OUT[13]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[14]_INST_0
(.I0(In14),
.I1(Mask[14]),
.O(Bus_16OUT[14]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[15]_INST_0
(.I0(In15),
.I1(Mask[15]),
.O(Bus_16OUT[15]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[1]_INST_0
(.I0(In1),
.I1(Mask[1]),
.O(Bus_16OUT[1]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[2]_INST_0
(.I0(In2),
.I1(Mask[2]),
.O(Bus_16OUT[2]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[3]_INST_0
(.I0(In3),
.I1(Mask[3]),
.O(Bus_16OUT[3]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[4]_INST_0
(.I0(In4),
.I1(Mask[4]),
.O(Bus_16OUT[4]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[5]_INST_0
(.I0(In5),
.I1(Mask[5]),
.O(Bus_16OUT[5]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[6]_INST_0
(.I0(In6),
.I1(Mask[6]),
.O(Bus_16OUT[6]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[7]_INST_0
(.I0(In7),
.I1(Mask[7]),
.O(Bus_16OUT[7]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[8]_INST_0
(.I0(In8),
.I1(Mask[8]),
.O(Bus_16OUT[8]));
LUT2 #(
.INIT(4'h8))
\Bus_16OUT[9]_INST_0
(.I0(In9),
.I1(Mask[9]),
.O(Bus_16OUT[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:54 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl
-- Design : AckChecker_BusBlock16OUT_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT is
port (
Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
In0 : in STD_LOGIC;
Mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
In1 : in STD_LOGIC;
In2 : in STD_LOGIC;
In3 : in STD_LOGIC;
In4 : in STD_LOGIC;
In5 : in STD_LOGIC;
In6 : in STD_LOGIC;
In7 : in STD_LOGIC;
In8 : in STD_LOGIC;
In9 : in STD_LOGIC;
In10 : in STD_LOGIC;
In11 : in STD_LOGIC;
In12 : in STD_LOGIC;
In13 : in STD_LOGIC;
In14 : in STD_LOGIC;
In15 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT is
begin
\Bus_16OUT[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In0,
I1 => Mask(0),
O => Bus_16OUT(0)
);
\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In10,
I1 => Mask(10),
O => Bus_16OUT(10)
);
\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In11,
I1 => Mask(11),
O => Bus_16OUT(11)
);
\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In12,
I1 => Mask(12),
O => Bus_16OUT(12)
);
\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In13,
I1 => Mask(13),
O => Bus_16OUT(13)
);
\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In14,
I1 => Mask(14),
O => Bus_16OUT(14)
);
\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In15,
I1 => Mask(15),
O => Bus_16OUT(15)
);
\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In1,
I1 => Mask(1),
O => Bus_16OUT(1)
);
\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In2,
I1 => Mask(2),
O => Bus_16OUT(2)
);
\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In3,
I1 => Mask(3),
O => Bus_16OUT(3)
);
\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In4,
I1 => Mask(4),
O => Bus_16OUT(4)
);
\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In5,
I1 => Mask(5),
O => Bus_16OUT(5)
);
\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In6,
I1 => Mask(6),
O => Bus_16OUT(6)
);
\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In7,
I1 => Mask(7),
O => Bus_16OUT(7)
);
\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In8,
I1 => Mask(8),
O => Bus_16OUT(8)
);
\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => In9,
I1 => Mask(9),
O => Bus_16OUT(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
In0 : in STD_LOGIC;
In1 : in STD_LOGIC;
In2 : in STD_LOGIC;
In3 : in STD_LOGIC;
In4 : in STD_LOGIC;
In5 : in STD_LOGIC;
In6 : in STD_LOGIC;
In7 : in STD_LOGIC;
In8 : in STD_LOGIC;
In9 : in STD_LOGIC;
In10 : in STD_LOGIC;
In11 : in STD_LOGIC;
In12 : in STD_LOGIC;
In13 : in STD_LOGIC;
In14 : in STD_LOGIC;
In15 : in STD_LOGIC;
Mask : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "BusBlock16OUT,Vivado 2019.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT
port map (
Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0),
In0 => In0,
In1 => In1,
In10 => In10,
In11 => In11,
In12 => In12,
In13 => In13,
In14 => In14,
In15 => In15,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => In7,
In8 => In8,
In9 => In9,
Mask(15 downto 0) => Mask(15 downto 0)
);
end STRUCTURE;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:54 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_stub.v
// Design : AckChecker_BusBlock16OUT_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9,
In10, In11, In12, In13, In14, In15, Mask)
/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */;
output [15:0]Bus_16OUT;
input In0;
input In1;
input In2;
input In3;
input In4;
input In5;
input In6;
input In7;
input In8;
input In9;
input In10;
input In11;
input In12;
input In13;
input In14;
input In15;
input [15:0]Mask;
endmodule
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:54 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_stub.vhdl
-- Design : AckChecker_BusBlock16OUT_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
In0 : in STD_LOGIC;
In1 : in STD_LOGIC;
In2 : in STD_LOGIC;
In3 : in STD_LOGIC;
In4 : in STD_LOGIC;
In5 : in STD_LOGIC;
In6 : in STD_LOGIC;
In7 : in STD_LOGIC;
In8 : in STD_LOGIC;
In9 : in STD_LOGIC;
In10 : in STD_LOGIC;
In11 : in STD_LOGIC;
In12 : in STD_LOGIC;
In13 : in STD_LOGIC;
In14 : in STD_LOGIC;
In15 : in STD_LOGIC;
Mask : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1";
begin
end;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/stats.txt
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NumberHits:3
Timestamp: Wed May 03 08:37:26 UTC 2023
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/9fc500b6c8c4592a.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>9fc500b6c8c4592a</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>AckChecker_AckCheckerConcept_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="ssevendenergy.com" spirit:library="user" spirit:name="AckCheckerConcept" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">AckChecker_AckCheckerConcept_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">9fc500b6c8c4592a</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">29f83029</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">36</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0.dcp
BIN
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LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:55 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v
// Design : AckChecker_AckCheckerConcept_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept
(AckPr,
currentPr,
reset,
acknowledge_in,
Clk,
line,
currentPr_en,
Ready,
ackTime,
AckPr_en);
output AckPr;
output currentPr;
input reset;
input acknowledge_in;
input Clk;
input line;
input currentPr_en;
input Ready;
input [31:0]ackTime;
input AckPr_en;
wire AckPr;
wire AckPr_en;
wire AckPr_i_1_n_0;
wire Clk;
wire \FSM_sequential_acknowledge[0]_i_1_n_0 ;
wire \FSM_sequential_acknowledge[1]_i_1_n_0 ;
wire Ready;
wire \TimeCnt[0]_i_1_n_0 ;
wire \TimeCnt[1]_i_1_n_0 ;
wire \TimeCnt[3]_i_1_n_0 ;
wire \TimeCnt[3]_i_2_n_0 ;
wire \TimeCnt[5]_i_1_n_0 ;
wire \TimeCnt[7]_i_1_n_0 ;
wire \TimeCnt[7]_i_2_n_0 ;
wire \TimeCnt[7]_i_4_n_0 ;
wire \TimeCnt_reg_n_0_[0] ;
wire \TimeCnt_reg_n_0_[1] ;
wire \TimeCnt_reg_n_0_[2] ;
wire \TimeCnt_reg_n_0_[3] ;
wire \TimeCnt_reg_n_0_[4] ;
wire \TimeCnt_reg_n_0_[5] ;
wire \TimeCnt_reg_n_0_[6] ;
wire \TimeCnt_reg_n_0_[7] ;
wire [31:0]ackTime;
wire [1:0]acknowledge;
wire acknowledge_in;
wire currentPr;
wire currentPr1__0;
wire currentPr_en;
wire currentPr_i_1_n_0;
wire currentPr_i_2_n_0;
wire currentPr_i_3_n_0;
wire currentPr_i_4_n_0;
wire line;
wire line_prev;
wire ltOp__15;
wire ltOp_carry__0_n_0;
wire ltOp_carry__0_n_1;
wire ltOp_carry__0_n_2;
wire ltOp_carry__0_n_3;
wire ltOp_carry__1_n_0;
wire ltOp_carry__1_n_1;
wire ltOp_carry__1_n_2;
wire ltOp_carry__1_n_3;
wire ltOp_carry__2_n_1;
wire ltOp_carry__2_n_2;
wire ltOp_carry__2_n_3;
wire ltOp_carry_i_1__0_n_0;
wire ltOp_carry_i_1__1_n_0;
wire ltOp_carry_i_1__2_n_0;
wire ltOp_carry_i_1_n_0;
wire ltOp_carry_i_2__0_n_0;
wire ltOp_carry_i_2__1_n_0;
wire ltOp_carry_i_2__2_n_0;
wire ltOp_carry_i_2_n_0;
wire ltOp_carry_i_3__0_n_0;
wire ltOp_carry_i_3__1_n_0;
wire ltOp_carry_i_3__2_n_0;
wire ltOp_carry_i_3_n_0;
wire ltOp_carry_i_4__0_n_0;
wire ltOp_carry_i_4__1_n_0;
wire ltOp_carry_i_4__2_n_0;
wire ltOp_carry_i_4_n_0;
wire ltOp_carry_i_5__0_n_0;
wire ltOp_carry_i_5__1_n_0;
wire ltOp_carry_i_5__2_n_0;
wire ltOp_carry_i_5_n_0;
wire ltOp_carry_i_6__0_n_0;
wire ltOp_carry_i_6__1_n_0;
wire ltOp_carry_i_6__2_n_0;
wire ltOp_carry_i_6_n_0;
wire ltOp_carry_i_7__0_n_0;
wire ltOp_carry_i_7__1_n_0;
wire ltOp_carry_i_7__2_n_0;
wire ltOp_carry_i_7_n_0;
wire ltOp_carry_i_8__0_n_0;
wire ltOp_carry_i_8__1_n_0;
wire ltOp_carry_i_8__2_n_0;
wire ltOp_carry_i_8_n_0;
wire ltOp_carry_n_0;
wire ltOp_carry_n_1;
wire ltOp_carry_n_2;
wire ltOp_carry_n_3;
wire [7:2]plusOp;
wire reset;
wire [3:0]NLW_ltOp_carry_O_UNCONNECTED;
wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED;
wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED;
wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED;
LUT5 #(
.INIT(32'hFFFF0400))
AckPr_i_1
(.I0(ltOp__15),
.I1(acknowledge[0]),
.I2(acknowledge[1]),
.I3(AckPr_en),
.I4(AckPr),
.O(AckPr_i_1_n_0));
FDRE #(
.INIT(1'b0))
AckPr_reg
(.C(Clk),
.CE(1'b1),
.D(AckPr_i_1_n_0),
.Q(AckPr),
.R(reset));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hD3D0C3C0))
\FSM_sequential_acknowledge[0]_i_1
(.I0(acknowledge_in),
.I1(acknowledge[1]),
.I2(acknowledge[0]),
.I3(currentPr1__0),
.I4(ltOp__15),
.O(\FSM_sequential_acknowledge[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h48))
\FSM_sequential_acknowledge[0]_i_2
(.I0(line_prev),
.I1(Ready),
.I2(line),
.O(currentPr1__0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hE8C0))
\FSM_sequential_acknowledge[1]_i_1
(.I0(acknowledge_in),
.I1(acknowledge[1]),
.I2(acknowledge[0]),
.I3(ltOp__15),
.O(\FSM_sequential_acknowledge[1]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_acknowledge_reg[0]
(.C(Clk),
.CE(1'b1),
.D(\FSM_sequential_acknowledge[0]_i_1_n_0 ),
.Q(acknowledge[0]),
.R(reset));
(* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_acknowledge_reg[1]
(.C(Clk),
.CE(1'b1),
.D(\FSM_sequential_acknowledge[1]_i_1_n_0 ),
.Q(acknowledge[1]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\TimeCnt[0]_i_1
(.I0(\TimeCnt_reg_n_0_[0] ),
.O(\TimeCnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00D0FFFFD0000000))
\TimeCnt[1]_i_1
(.I0(acknowledge[1]),
.I1(acknowledge_in),
.I2(ltOp__15),
.I3(\TimeCnt_reg_n_0_[0] ),
.I4(\TimeCnt[7]_i_2_n_0 ),
.I5(\TimeCnt_reg_n_0_[1] ),
.O(\TimeCnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\TimeCnt[2]_i_1
(.I0(\TimeCnt_reg_n_0_[1] ),
.I1(\TimeCnt_reg_n_0_[0] ),
.I2(\TimeCnt_reg_n_0_[2] ),
.O(plusOp[2]));
LUT6 #(
.INIT(64'h00D0FFFFD0000000))
\TimeCnt[3]_i_1
(.I0(acknowledge[1]),
.I1(acknowledge_in),
.I2(ltOp__15),
.I3(\TimeCnt[3]_i_2_n_0 ),
.I4(\TimeCnt[7]_i_2_n_0 ),
.I5(\TimeCnt_reg_n_0_[3] ),
.O(\TimeCnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h80))
\TimeCnt[3]_i_2
(.I0(\TimeCnt_reg_n_0_[2] ),
.I1(\TimeCnt_reg_n_0_[1] ),
.I2(\TimeCnt_reg_n_0_[0] ),
.O(\TimeCnt[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TimeCnt[4]_i_1
(.I0(\TimeCnt_reg_n_0_[3] ),
.I1(\TimeCnt_reg_n_0_[2] ),
.I2(\TimeCnt_reg_n_0_[1] ),
.I3(\TimeCnt_reg_n_0_[0] ),
.I4(\TimeCnt_reg_n_0_[4] ),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h4044FFFF80880000))
\TimeCnt[5]_i_1
(.I0(\TimeCnt[7]_i_4_n_0 ),
.I1(ltOp__15),
.I2(acknowledge_in),
.I3(acknowledge[1]),
.I4(\TimeCnt[7]_i_2_n_0 ),
.I5(\TimeCnt_reg_n_0_[5] ),
.O(\TimeCnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\TimeCnt[6]_i_1
(.I0(\TimeCnt_reg_n_0_[5] ),
.I1(\TimeCnt[7]_i_4_n_0 ),
.I2(\TimeCnt_reg_n_0_[6] ),
.O(plusOp[6]));
LUT5 #(
.INIT(32'h01110404))
\TimeCnt[7]_i_1
(.I0(reset),
.I1(acknowledge[0]),
.I2(ltOp__15),
.I3(acknowledge_in),
.I4(acknowledge[1]),
.O(\TimeCnt[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'h06))
\TimeCnt[7]_i_2
(.I0(acknowledge[1]),
.I1(acknowledge[0]),
.I2(reset),
.O(\TimeCnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\TimeCnt[7]_i_3
(.I0(\TimeCnt_reg_n_0_[6] ),
.I1(\TimeCnt[7]_i_4_n_0 ),
.I2(\TimeCnt_reg_n_0_[5] ),
.I3(\TimeCnt_reg_n_0_[7] ),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\TimeCnt[7]_i_4
(.I0(\TimeCnt_reg_n_0_[4] ),
.I1(\TimeCnt_reg_n_0_[3] ),
.I2(\TimeCnt_reg_n_0_[2] ),
.I3(\TimeCnt_reg_n_0_[1] ),
.I4(\TimeCnt_reg_n_0_[0] ),
.O(\TimeCnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[0]
(.C(Clk),
.CE(\TimeCnt[7]_i_2_n_0 ),
.D(\TimeCnt[0]_i_1_n_0 ),
.Q(\TimeCnt_reg_n_0_[0] ),
.R(\TimeCnt[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[1]
(.C(Clk),
.CE(1'b1),
.D(\TimeCnt[1]_i_1_n_0 ),
.Q(\TimeCnt_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[2]
(.C(Clk),
.CE(\TimeCnt[7]_i_2_n_0 ),
.D(plusOp[2]),
.Q(\TimeCnt_reg_n_0_[2] ),
.R(\TimeCnt[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[3]
(.C(Clk),
.CE(1'b1),
.D(\TimeCnt[3]_i_1_n_0 ),
.Q(\TimeCnt_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[4]
(.C(Clk),
.CE(\TimeCnt[7]_i_2_n_0 ),
.D(plusOp[4]),
.Q(\TimeCnt_reg_n_0_[4] ),
.R(\TimeCnt[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[5]
(.C(Clk),
.CE(1'b1),
.D(\TimeCnt[5]_i_1_n_0 ),
.Q(\TimeCnt_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[6]
(.C(Clk),
.CE(\TimeCnt[7]_i_2_n_0 ),
.D(plusOp[6]),
.Q(\TimeCnt_reg_n_0_[6] ),
.R(\TimeCnt[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\TimeCnt_reg[7]
(.C(Clk),
.CE(\TimeCnt[7]_i_2_n_0 ),
.D(plusOp[7]),
.Q(\TimeCnt_reg_n_0_[7] ),
.R(\TimeCnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBFFBF88880080))
currentPr_i_1
(.I0(currentPr_i_2_n_0),
.I1(currentPr_i_3_n_0),
.I2(acknowledge[1]),
.I3(ltOp__15),
.I4(currentPr_i_4_n_0),
.I5(currentPr),
.O(currentPr_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hC888))
currentPr_i_2
(.I0(acknowledge[1]),
.I1(currentPr_en),
.I2(acknowledge_in),
.I3(Ready),
.O(currentPr_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
currentPr_i_3
(.I0(currentPr_en),
.I1(acknowledge[0]),
.O(currentPr_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h40000400))
currentPr_i_4
(.I0(acknowledge[1]),
.I1(acknowledge_in),
.I2(line),
.I3(Ready),
.I4(line_prev),
.O(currentPr_i_4_n_0));
FDRE #(
.INIT(1'b0))
currentPr_reg
(.C(Clk),
.CE(1'b1),
.D(currentPr_i_1_n_0),
.Q(currentPr),
.R(reset));
FDRE #(
.INIT(1'b0))
line_prev_reg
(.C(Clk),
.CE(1'b1),
.D(line),
.Q(line_prev),
.R(1'b0));
CARRY4 ltOp_carry
(.CI(1'b0),
.CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}),
.CYINIT(1'b0),
.DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}),
.O(NLW_ltOp_carry_O_UNCONNECTED[3:0]),
.S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0}));
CARRY4 ltOp_carry__0
(.CI(ltOp_carry_n_0),
.CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}),
.O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]),
.S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0}));
CARRY4 ltOp_carry__1
(.CI(ltOp_carry__0_n_0),
.CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}),
.O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]),
.S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0}));
CARRY4 ltOp_carry__2
(.CI(ltOp_carry__1_n_0),
.CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}),
.CYINIT(1'b0),
.DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}),
.O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]),
.S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0}));
LUT4 #(
.INIT(16'h2F02))
ltOp_carry_i_1
(.I0(ackTime[6]),
.I1(\TimeCnt_reg_n_0_[6] ),
.I2(\TimeCnt_reg_n_0_[7] ),
.I3(ackTime[7]),
.O(ltOp_carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_1__0
(.I0(ackTime[14]),
.I1(ackTime[15]),
.O(ltOp_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_1__1
(.I0(ackTime[22]),
.I1(ackTime[23]),
.O(ltOp_carry_i_1__1_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_1__2
(.I0(ackTime[30]),
.I1(ackTime[31]),
.O(ltOp_carry_i_1__2_n_0));
LUT4 #(
.INIT(16'h2F02))
ltOp_carry_i_2
(.I0(ackTime[4]),
.I1(\TimeCnt_reg_n_0_[4] ),
.I2(\TimeCnt_reg_n_0_[5] ),
.I3(ackTime[5]),
.O(ltOp_carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_2__0
(.I0(ackTime[12]),
.I1(ackTime[13]),
.O(ltOp_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_2__1
(.I0(ackTime[20]),
.I1(ackTime[21]),
.O(ltOp_carry_i_2__1_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_2__2
(.I0(ackTime[28]),
.I1(ackTime[29]),
.O(ltOp_carry_i_2__2_n_0));
LUT4 #(
.INIT(16'h2F02))
ltOp_carry_i_3
(.I0(ackTime[2]),
.I1(\TimeCnt_reg_n_0_[2] ),
.I2(\TimeCnt_reg_n_0_[3] ),
.I3(ackTime[3]),
.O(ltOp_carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_3__0
(.I0(ackTime[10]),
.I1(ackTime[11]),
.O(ltOp_carry_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_3__1
(.I0(ackTime[18]),
.I1(ackTime[19]),
.O(ltOp_carry_i_3__1_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_3__2
(.I0(ackTime[26]),
.I1(ackTime[27]),
.O(ltOp_carry_i_3__2_n_0));
LUT4 #(
.INIT(16'h2F02))
ltOp_carry_i_4
(.I0(ackTime[0]),
.I1(\TimeCnt_reg_n_0_[0] ),
.I2(\TimeCnt_reg_n_0_[1] ),
.I3(ackTime[1]),
.O(ltOp_carry_i_4_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_4__0
(.I0(ackTime[8]),
.I1(ackTime[9]),
.O(ltOp_carry_i_4__0_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_4__1
(.I0(ackTime[16]),
.I1(ackTime[17]),
.O(ltOp_carry_i_4__1_n_0));
LUT2 #(
.INIT(4'hE))
ltOp_carry_i_4__2
(.I0(ackTime[24]),
.I1(ackTime[25]),
.O(ltOp_carry_i_4__2_n_0));
LUT4 #(
.INIT(16'h9009))
ltOp_carry_i_5
(.I0(\TimeCnt_reg_n_0_[7] ),
.I1(ackTime[7]),
.I2(\TimeCnt_reg_n_0_[6] ),
.I3(ackTime[6]),
.O(ltOp_carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_5__0
(.I0(ackTime[15]),
.I1(ackTime[14]),
.O(ltOp_carry_i_5__0_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_5__1
(.I0(ackTime[23]),
.I1(ackTime[22]),
.O(ltOp_carry_i_5__1_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_5__2
(.I0(ackTime[31]),
.I1(ackTime[30]),
.O(ltOp_carry_i_5__2_n_0));
LUT4 #(
.INIT(16'h9009))
ltOp_carry_i_6
(.I0(\TimeCnt_reg_n_0_[5] ),
.I1(ackTime[5]),
.I2(\TimeCnt_reg_n_0_[4] ),
.I3(ackTime[4]),
.O(ltOp_carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_6__0
(.I0(ackTime[13]),
.I1(ackTime[12]),
.O(ltOp_carry_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_6__1
(.I0(ackTime[21]),
.I1(ackTime[20]),
.O(ltOp_carry_i_6__1_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_6__2
(.I0(ackTime[29]),
.I1(ackTime[28]),
.O(ltOp_carry_i_6__2_n_0));
LUT4 #(
.INIT(16'h9009))
ltOp_carry_i_7
(.I0(\TimeCnt_reg_n_0_[3] ),
.I1(ackTime[3]),
.I2(\TimeCnt_reg_n_0_[2] ),
.I3(ackTime[2]),
.O(ltOp_carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_7__0
(.I0(ackTime[11]),
.I1(ackTime[10]),
.O(ltOp_carry_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_7__1
(.I0(ackTime[19]),
.I1(ackTime[18]),
.O(ltOp_carry_i_7__1_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_7__2
(.I0(ackTime[27]),
.I1(ackTime[26]),
.O(ltOp_carry_i_7__2_n_0));
LUT4 #(
.INIT(16'h9009))
ltOp_carry_i_8
(.I0(\TimeCnt_reg_n_0_[1] ),
.I1(ackTime[1]),
.I2(\TimeCnt_reg_n_0_[0] ),
.I3(ackTime[0]),
.O(ltOp_carry_i_8_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_8__0
(.I0(ackTime[9]),
.I1(ackTime[8]),
.O(ltOp_carry_i_8__0_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_8__1
(.I0(ackTime[17]),
.I1(ackTime[16]),
.O(ltOp_carry_i_8__1_n_0));
LUT2 #(
.INIT(4'h1))
ltOp_carry_i_8__2
(.I0(ackTime[25]),
.I1(ackTime[24]),
.O(ltOp_carry_i_8__2_n_0));
endmodule
(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(ackTime,
AckPr_en,
AckPr,
acknowledge_in,
Clk,
currentPr_en,
currentPr,
line,
Ready,
reset);
input [31:0]ackTime;
input AckPr_en;
output AckPr;
input acknowledge_in;
(* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk;
input currentPr_en;
output currentPr;
input line;
input Ready;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset;
wire AckPr;
wire AckPr_en;
wire Clk;
wire Ready;
wire [31:0]ackTime;
wire acknowledge_in;
wire currentPr;
wire currentPr_en;
wire line;
wire reset;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept U0
(.AckPr(AckPr),
.AckPr_en(AckPr_en),
.Clk(Clk),
.Ready(Ready),
.ackTime(ackTime),
.acknowledge_in(acknowledge_in),
.currentPr(currentPr),
.currentPr_en(currentPr_en),
.line(line),
.reset(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
+927
View File
@@ -0,0 +1,927 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:55 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
-- Design : AckChecker_AckCheckerConcept_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept is
port (
AckPr : out STD_LOGIC;
currentPr : out STD_LOGIC;
reset : in STD_LOGIC;
acknowledge_in : in STD_LOGIC;
Clk : in STD_LOGIC;
line : in STD_LOGIC;
currentPr_en : in STD_LOGIC;
Ready : in STD_LOGIC;
ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 );
AckPr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept is
signal \^ackpr\ : STD_LOGIC;
signal AckPr_i_1_n_0 : STD_LOGIC;
signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC;
signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC;
signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC;
signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC;
signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC;
signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^currentpr\ : STD_LOGIC;
signal \currentPr1__0\ : STD_LOGIC;
signal currentPr_i_1_n_0 : STD_LOGIC;
signal currentPr_i_2_n_0 : STD_LOGIC;
signal currentPr_i_3_n_0 : STD_LOGIC;
signal currentPr_i_4_n_0 : STD_LOGIC;
signal line_prev : STD_LOGIC;
signal \ltOp__15\ : STD_LOGIC;
signal \ltOp_carry__0_n_0\ : STD_LOGIC;
signal \ltOp_carry__0_n_1\ : STD_LOGIC;
signal \ltOp_carry__0_n_2\ : STD_LOGIC;
signal \ltOp_carry__0_n_3\ : STD_LOGIC;
signal \ltOp_carry__1_n_0\ : STD_LOGIC;
signal \ltOp_carry__1_n_1\ : STD_LOGIC;
signal \ltOp_carry__1_n_2\ : STD_LOGIC;
signal \ltOp_carry__1_n_3\ : STD_LOGIC;
signal \ltOp_carry__2_n_1\ : STD_LOGIC;
signal \ltOp_carry__2_n_2\ : STD_LOGIC;
signal \ltOp_carry__2_n_3\ : STD_LOGIC;
signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_1_n_0 : STD_LOGIC;
signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_2_n_0 : STD_LOGIC;
signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_3_n_0 : STD_LOGIC;
signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_4_n_0 : STD_LOGIC;
signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_5_n_0 : STD_LOGIC;
signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_6_n_0 : STD_LOGIC;
signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_7_n_0 : STD_LOGIC;
signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC;
signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC;
signal ltOp_carry_i_8_n_0 : STD_LOGIC;
signal ltOp_carry_n_0 : STD_LOGIC;
signal ltOp_carry_n_1 : STD_LOGIC;
signal ltOp_carry_n_2 : STD_LOGIC;
signal ltOp_carry_n_3 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 );
signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11";
attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11";
attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2";
begin
AckPr <= \^ackpr\;
currentPr <= \^currentpr\;
AckPr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0400"
)
port map (
I0 => \ltOp__15\,
I1 => acknowledge(0),
I2 => acknowledge(1),
I3 => AckPr_en,
I4 => \^ackpr\,
O => AckPr_i_1_n_0
);
AckPr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => AckPr_i_1_n_0,
Q => \^ackpr\,
R => reset
);
\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D3D0C3C0"
)
port map (
I0 => acknowledge_in,
I1 => acknowledge(1),
I2 => acknowledge(0),
I3 => \currentPr1__0\,
I4 => \ltOp__15\,
O => \FSM_sequential_acknowledge[0]_i_1_n_0\
);
\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"48"
)
port map (
I0 => line_prev,
I1 => Ready,
I2 => line,
O => \currentPr1__0\
);
\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E8C0"
)
port map (
I0 => acknowledge_in,
I1 => acknowledge(1),
I2 => acknowledge(0),
I3 => \ltOp__15\,
O => \FSM_sequential_acknowledge[1]_i_1_n_0\
);
\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => \FSM_sequential_acknowledge[0]_i_1_n_0\,
Q => acknowledge(0),
R => reset
);
\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => \FSM_sequential_acknowledge[1]_i_1_n_0\,
Q => acknowledge(1),
R => reset
);
\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \TimeCnt_reg_n_0_[0]\,
O => \TimeCnt[0]_i_1_n_0\
);
\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00D0FFFFD0000000"
)
port map (
I0 => acknowledge(1),
I1 => acknowledge_in,
I2 => \ltOp__15\,
I3 => \TimeCnt_reg_n_0_[0]\,
I4 => \TimeCnt[7]_i_2_n_0\,
I5 => \TimeCnt_reg_n_0_[1]\,
O => \TimeCnt[1]_i_1_n_0\
);
\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \TimeCnt_reg_n_0_[1]\,
I1 => \TimeCnt_reg_n_0_[0]\,
I2 => \TimeCnt_reg_n_0_[2]\,
O => plusOp(2)
);
\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00D0FFFFD0000000"
)
port map (
I0 => acknowledge(1),
I1 => acknowledge_in,
I2 => \ltOp__15\,
I3 => \TimeCnt[3]_i_2_n_0\,
I4 => \TimeCnt[7]_i_2_n_0\,
I5 => \TimeCnt_reg_n_0_[3]\,
O => \TimeCnt[3]_i_1_n_0\
);
\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \TimeCnt_reg_n_0_[2]\,
I1 => \TimeCnt_reg_n_0_[1]\,
I2 => \TimeCnt_reg_n_0_[0]\,
O => \TimeCnt[3]_i_2_n_0\
);
\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \TimeCnt_reg_n_0_[3]\,
I1 => \TimeCnt_reg_n_0_[2]\,
I2 => \TimeCnt_reg_n_0_[1]\,
I3 => \TimeCnt_reg_n_0_[0]\,
I4 => \TimeCnt_reg_n_0_[4]\,
O => plusOp(4)
);
\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4044FFFF80880000"
)
port map (
I0 => \TimeCnt[7]_i_4_n_0\,
I1 => \ltOp__15\,
I2 => acknowledge_in,
I3 => acknowledge(1),
I4 => \TimeCnt[7]_i_2_n_0\,
I5 => \TimeCnt_reg_n_0_[5]\,
O => \TimeCnt[5]_i_1_n_0\
);
\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \TimeCnt_reg_n_0_[5]\,
I1 => \TimeCnt[7]_i_4_n_0\,
I2 => \TimeCnt_reg_n_0_[6]\,
O => plusOp(6)
);
\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01110404"
)
port map (
I0 => reset,
I1 => acknowledge(0),
I2 => \ltOp__15\,
I3 => acknowledge_in,
I4 => acknowledge(1),
O => \TimeCnt[7]_i_1_n_0\
);
\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => acknowledge(1),
I1 => acknowledge(0),
I2 => reset,
O => \TimeCnt[7]_i_2_n_0\
);
\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \TimeCnt_reg_n_0_[6]\,
I1 => \TimeCnt[7]_i_4_n_0\,
I2 => \TimeCnt_reg_n_0_[5]\,
I3 => \TimeCnt_reg_n_0_[7]\,
O => plusOp(7)
);
\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \TimeCnt_reg_n_0_[4]\,
I1 => \TimeCnt_reg_n_0_[3]\,
I2 => \TimeCnt_reg_n_0_[2]\,
I3 => \TimeCnt_reg_n_0_[1]\,
I4 => \TimeCnt_reg_n_0_[0]\,
O => \TimeCnt[7]_i_4_n_0\
);
\TimeCnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => \TimeCnt[7]_i_2_n_0\,
D => \TimeCnt[0]_i_1_n_0\,
Q => \TimeCnt_reg_n_0_[0]\,
R => \TimeCnt[7]_i_1_n_0\
);
\TimeCnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => \TimeCnt[1]_i_1_n_0\,
Q => \TimeCnt_reg_n_0_[1]\,
R => '0'
);
\TimeCnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => \TimeCnt[7]_i_2_n_0\,
D => plusOp(2),
Q => \TimeCnt_reg_n_0_[2]\,
R => \TimeCnt[7]_i_1_n_0\
);
\TimeCnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => \TimeCnt[3]_i_1_n_0\,
Q => \TimeCnt_reg_n_0_[3]\,
R => '0'
);
\TimeCnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => \TimeCnt[7]_i_2_n_0\,
D => plusOp(4),
Q => \TimeCnt_reg_n_0_[4]\,
R => \TimeCnt[7]_i_1_n_0\
);
\TimeCnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => \TimeCnt[5]_i_1_n_0\,
Q => \TimeCnt_reg_n_0_[5]\,
R => '0'
);
\TimeCnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => \TimeCnt[7]_i_2_n_0\,
D => plusOp(6),
Q => \TimeCnt_reg_n_0_[6]\,
R => \TimeCnt[7]_i_1_n_0\
);
\TimeCnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => \TimeCnt[7]_i_2_n_0\,
D => plusOp(7),
Q => \TimeCnt_reg_n_0_[7]\,
R => \TimeCnt[7]_i_1_n_0\
);
currentPr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBFFBF88880080"
)
port map (
I0 => currentPr_i_2_n_0,
I1 => currentPr_i_3_n_0,
I2 => acknowledge(1),
I3 => \ltOp__15\,
I4 => currentPr_i_4_n_0,
I5 => \^currentpr\,
O => currentPr_i_1_n_0
);
currentPr_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => acknowledge(1),
I1 => currentPr_en,
I2 => acknowledge_in,
I3 => Ready,
O => currentPr_i_2_n_0
);
currentPr_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => currentPr_en,
I1 => acknowledge(0),
O => currentPr_i_3_n_0
);
currentPr_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"40000400"
)
port map (
I0 => acknowledge(1),
I1 => acknowledge_in,
I2 => line,
I3 => Ready,
I4 => line_prev,
O => currentPr_i_4_n_0
);
currentPr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => currentPr_i_1_n_0,
Q => \^currentpr\,
R => reset
);
line_prev_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => Clk,
CE => '1',
D => line,
Q => line_prev,
R => '0'
);
ltOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ltOp_carry_n_0,
CO(2) => ltOp_carry_n_1,
CO(1) => ltOp_carry_n_2,
CO(0) => ltOp_carry_n_3,
CYINIT => '0',
DI(3) => ltOp_carry_i_1_n_0,
DI(2) => ltOp_carry_i_2_n_0,
DI(1) => ltOp_carry_i_3_n_0,
DI(0) => ltOp_carry_i_4_n_0,
O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0),
S(3) => ltOp_carry_i_5_n_0,
S(2) => ltOp_carry_i_6_n_0,
S(1) => ltOp_carry_i_7_n_0,
S(0) => ltOp_carry_i_8_n_0
);
\ltOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ltOp_carry_n_0,
CO(3) => \ltOp_carry__0_n_0\,
CO(2) => \ltOp_carry__0_n_1\,
CO(1) => \ltOp_carry__0_n_2\,
CO(0) => \ltOp_carry__0_n_3\,
CYINIT => '0',
DI(3) => \ltOp_carry_i_1__0_n_0\,
DI(2) => \ltOp_carry_i_2__0_n_0\,
DI(1) => \ltOp_carry_i_3__0_n_0\,
DI(0) => \ltOp_carry_i_4__0_n_0\,
O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \ltOp_carry_i_5__0_n_0\,
S(2) => \ltOp_carry_i_6__0_n_0\,
S(1) => \ltOp_carry_i_7__0_n_0\,
S(0) => \ltOp_carry_i_8__0_n_0\
);
\ltOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ltOp_carry__0_n_0\,
CO(3) => \ltOp_carry__1_n_0\,
CO(2) => \ltOp_carry__1_n_1\,
CO(1) => \ltOp_carry__1_n_2\,
CO(0) => \ltOp_carry__1_n_3\,
CYINIT => '0',
DI(3) => \ltOp_carry_i_1__1_n_0\,
DI(2) => \ltOp_carry_i_2__1_n_0\,
DI(1) => \ltOp_carry_i_3__1_n_0\,
DI(0) => \ltOp_carry_i_4__1_n_0\,
O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \ltOp_carry_i_5__1_n_0\,
S(2) => \ltOp_carry_i_6__1_n_0\,
S(1) => \ltOp_carry_i_7__1_n_0\,
S(0) => \ltOp_carry_i_8__1_n_0\
);
\ltOp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ltOp_carry__1_n_0\,
CO(3) => \ltOp__15\,
CO(2) => \ltOp_carry__2_n_1\,
CO(1) => \ltOp_carry__2_n_2\,
CO(0) => \ltOp_carry__2_n_3\,
CYINIT => '0',
DI(3) => \ltOp_carry_i_1__2_n_0\,
DI(2) => \ltOp_carry_i_2__2_n_0\,
DI(1) => \ltOp_carry_i_3__2_n_0\,
DI(0) => \ltOp_carry_i_4__2_n_0\,
O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \ltOp_carry_i_5__2_n_0\,
S(2) => \ltOp_carry_i_6__2_n_0\,
S(1) => \ltOp_carry_i_7__2_n_0\,
S(0) => \ltOp_carry_i_8__2_n_0\
);
ltOp_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => ackTime(6),
I1 => \TimeCnt_reg_n_0_[6]\,
I2 => \TimeCnt_reg_n_0_[7]\,
I3 => ackTime(7),
O => ltOp_carry_i_1_n_0
);
\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(14),
I1 => ackTime(15),
O => \ltOp_carry_i_1__0_n_0\
);
\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(22),
I1 => ackTime(23),
O => \ltOp_carry_i_1__1_n_0\
);
\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(30),
I1 => ackTime(31),
O => \ltOp_carry_i_1__2_n_0\
);
ltOp_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => ackTime(4),
I1 => \TimeCnt_reg_n_0_[4]\,
I2 => \TimeCnt_reg_n_0_[5]\,
I3 => ackTime(5),
O => ltOp_carry_i_2_n_0
);
\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(12),
I1 => ackTime(13),
O => \ltOp_carry_i_2__0_n_0\
);
\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(20),
I1 => ackTime(21),
O => \ltOp_carry_i_2__1_n_0\
);
\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(28),
I1 => ackTime(29),
O => \ltOp_carry_i_2__2_n_0\
);
ltOp_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => ackTime(2),
I1 => \TimeCnt_reg_n_0_[2]\,
I2 => \TimeCnt_reg_n_0_[3]\,
I3 => ackTime(3),
O => ltOp_carry_i_3_n_0
);
\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(10),
I1 => ackTime(11),
O => \ltOp_carry_i_3__0_n_0\
);
\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(18),
I1 => ackTime(19),
O => \ltOp_carry_i_3__1_n_0\
);
\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(26),
I1 => ackTime(27),
O => \ltOp_carry_i_3__2_n_0\
);
ltOp_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => ackTime(0),
I1 => \TimeCnt_reg_n_0_[0]\,
I2 => \TimeCnt_reg_n_0_[1]\,
I3 => ackTime(1),
O => ltOp_carry_i_4_n_0
);
\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(8),
I1 => ackTime(9),
O => \ltOp_carry_i_4__0_n_0\
);
\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(16),
I1 => ackTime(17),
O => \ltOp_carry_i_4__1_n_0\
);
\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ackTime(24),
I1 => ackTime(25),
O => \ltOp_carry_i_4__2_n_0\
);
ltOp_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \TimeCnt_reg_n_0_[7]\,
I1 => ackTime(7),
I2 => \TimeCnt_reg_n_0_[6]\,
I3 => ackTime(6),
O => ltOp_carry_i_5_n_0
);
\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(15),
I1 => ackTime(14),
O => \ltOp_carry_i_5__0_n_0\
);
\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(23),
I1 => ackTime(22),
O => \ltOp_carry_i_5__1_n_0\
);
\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(31),
I1 => ackTime(30),
O => \ltOp_carry_i_5__2_n_0\
);
ltOp_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \TimeCnt_reg_n_0_[5]\,
I1 => ackTime(5),
I2 => \TimeCnt_reg_n_0_[4]\,
I3 => ackTime(4),
O => ltOp_carry_i_6_n_0
);
\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(13),
I1 => ackTime(12),
O => \ltOp_carry_i_6__0_n_0\
);
\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(21),
I1 => ackTime(20),
O => \ltOp_carry_i_6__1_n_0\
);
\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(29),
I1 => ackTime(28),
O => \ltOp_carry_i_6__2_n_0\
);
ltOp_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \TimeCnt_reg_n_0_[3]\,
I1 => ackTime(3),
I2 => \TimeCnt_reg_n_0_[2]\,
I3 => ackTime(2),
O => ltOp_carry_i_7_n_0
);
\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(11),
I1 => ackTime(10),
O => \ltOp_carry_i_7__0_n_0\
);
\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(19),
I1 => ackTime(18),
O => \ltOp_carry_i_7__1_n_0\
);
\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(27),
I1 => ackTime(26),
O => \ltOp_carry_i_7__2_n_0\
);
ltOp_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \TimeCnt_reg_n_0_[1]\,
I1 => ackTime(1),
I2 => \TimeCnt_reg_n_0_[0]\,
I3 => ackTime(0),
O => ltOp_carry_i_8_n_0
);
\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(9),
I1 => ackTime(8),
O => \ltOp_carry_i_8__0_n_0\
);
\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(17),
I1 => ackTime(16),
O => \ltOp_carry_i_8__1_n_0\
);
\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ackTime(25),
I1 => ackTime(24),
O => \ltOp_carry_i_8__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 );
AckPr_en : in STD_LOGIC;
AckPr : out STD_LOGIC;
acknowledge_in : in STD_LOGIC;
Clk : in STD_LOGIC;
currentPr_en : in STD_LOGIC;
currentPr : out STD_LOGIC;
line : in STD_LOGIC;
Ready : in STD_LOGIC;
reset : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckCheckerConcept,Vivado 2019.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute x_interface_info : string;
attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0";
attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST";
attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept
port map (
AckPr => AckPr,
AckPr_en => AckPr_en,
Clk => Clk,
Ready => Ready,
ackTime(31 downto 0) => ackTime(31 downto 0),
acknowledge_in => acknowledge_in,
currentPr => currentPr,
currentPr_en => currentPr_en,
line => line,
reset => reset
);
end STRUCTURE;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.v
+30
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@@ -0,0 +1,30 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Wed May 3 11:35:55 2023
// Host : STAS-W10 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_stub.v
// Design : AckChecker_AckCheckerConcept_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ackTime, AckPr_en, AckPr, acknowledge_in, Clk,
currentPr_en, currentPr, line, Ready, reset)
/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */;
input [31:0]ackTime;
input AckPr_en;
output AckPr;
input acknowledge_in;
input Clk;
input currentPr_en;
output currentPr;
input line;
input Ready;
input reset;
endmodule
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.vhdl
+39
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@@ -0,0 +1,39 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Wed May 3 11:35:55 2023
-- Host : STAS-W10 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_stub.vhdl
-- Design : AckChecker_AckCheckerConcept_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 );
AckPr_en : in STD_LOGIC;
AckPr : out STD_LOGIC;
acknowledge_in : in STD_LOGIC;
Clk : in STD_LOGIC;
currentPr_en : in STD_LOGIC;
currentPr : out STD_LOGIC;
line : in STD_LOGIC;
Ready : in STD_LOGIC;
reset : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1";
begin
end;
LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/stats.txt
+2
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@@ -0,0 +1,2 @@
NumberHits:31
Timestamp: Wed May 03 08:37:18 UTC 2023
LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/gui_handlers.wdf
+36 -16
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@@ -1,24 +1,39 @@
version:1
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@@ -29,19 +44,24 @@ version:1
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LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/java_command_handlers.wdf
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View File
@@ -1,20 +1,23 @@
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LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/project.wpc
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View File
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version:1
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LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/synthesis.wdf
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View File
@@ -33,7 +33,7 @@ version:1
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LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/webtalk_pa.xml
+46 -23
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Apr 29 14:13:24 2020">
<application name="pa" timeStamp="Wed May 3 11:42:31 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="d64baf41b06645d49baa029746b90ffb" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
@@ -18,45 +18,63 @@ This means code written to parse this file will need to be revisited each subseq
</item>
<item name="Java Command Handlers">
<property name="AutoConnectPort" value="7" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="CoreView" value="4" type="JavaHandler"/>
<property name="CreateBlockDesign" value="1" type="JavaHandler"/>
<property name="CreateTopHDL" value="1" type="JavaHandler"/>
<property name="DisconnectRSBPin" value="2" type="JavaHandler"/>
<property name="EditCopy" value="13" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="EditPaste" value="16" type="JavaHandler"/>
<property name="EditUndo" value="10" type="JavaHandler"/>
<property name="IPPackagerHandler" value="3" type="JavaHandler"/>
<property name="IPPackagerHandler" value="5" type="JavaHandler"/>
<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="OpenBlockDesign" value="2" type="JavaHandler"/>
<property name="OpenProject" value="2" type="JavaHandler"/>
<property name="RegenerateRSBLayout" value="4" type="JavaHandler"/>
<property name="ReportIPStatus" value="1" type="JavaHandler"/>
<property name="ReportIPStatus" value="3" type="JavaHandler"/>
<property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="2" type="JavaHandler"/>
<property name="SaveRSBDesign" value="12" type="JavaHandler"/>
<property name="UpgradeIP" value="2" type="JavaHandler"/>
<property name="ValidateRSBDesign" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AddRepositoryInfoDialog_OK" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="24" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="1" type="GuiHandlerData"/>
<property name="AddRepositoryInfoDialog_OK" value="2" type="GuiHandlerData"/>
<property name="AddRepositoryInfoDialog_REPOSITORY_TREE" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="28" type="GuiHandlerData"/>
<property name="BaseReportTab_RERUN" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
<property name="CoreAndInterfacesBaseTreeTablePanel_ADD_REPOSITORY" value="1" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="12" type="GuiHandlerData"/>
<property name="CoreAndInterfacesBaseTreeTablePanel_ADD_REPOSITORY" value="2" type="GuiHandlerData"/>
<property name="CoreAndInterfacesBaseTreeTablePanel_REFRESH_ALL_REPOSITORIES" value="5" type="GuiHandlerData"/>
<property name="CoreAndInterfacesBaseTreeTablePanel_REMOVE_FROM_PROJECT" value="1" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="55" type="GuiHandlerData"/>
<property name="CreateNewDiagramDialog_DESIGN_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateRSBPortDialog_PORT_NAME" value="20" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileGroupFacetTable_FILE_GROUP_FACET_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="19" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="3" type="GuiHandlerData"/>
<property name="FamilySupportTable_ADD_FAMILY_EXPLICITLY" value="1" type="GuiHandlerData"/>
<property name="FamilySupportTable_DEVICE_SUPPORT_TABLE" value="4" type="GuiHandlerData"/>
<property name="FileGroupFacetTable_COPY_TO" value="1" type="GuiHandlerData"/>
<property name="FileGroupFacetTable_FILE_GROUP_FACET_TABLE" value="11" type="GuiHandlerData"/>
<property name="FileGroupFacetTable_REFRESH" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="33" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="9" type="GuiHandlerData"/>
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="IPStatusSectionPanel_UPGRADE_SELECTED" value="2" type="GuiHandlerData"/>
<property name="IPStatusTablePanel_IP_STATUS_TABLE" value="5" type="GuiHandlerData"/>
<property name="IdentificationContentPanel_COMPANY_URL_DISPLAY_NAME" value="2" type="GuiHandlerData"/>
<property name="IdentificationContentPanel_VENDOR" value="1" type="GuiHandlerData"/>
<property name="IdentificationContentPanel_VENDOR_DISPLAY_NAME" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
<property name="InterfacesTreeTablePanel_INTERFACE_TREE_TABLE" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
<property name="ManualSelectionPanel_FPGA_PARTS" value="1" type="GuiHandlerData"/>
<property name="MessageBanner_CHANGES_DETECTED_IN_VIVADO_PROJECT_THAT" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="1" type="GuiHandlerData"/>
<property name="MsgView_CRITICAL_WARNINGS" value="1" type="GuiHandlerData"/>
@@ -67,19 +85,24 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_CREATE_TOP_HDL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_DISCONNECT_RSB_PIN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_REGENERATE_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_REPORT_IP_STATUS" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SAVE_RSB_DESIGN" value="12" type="GuiHandlerData"/>
<property name="PACommandNames_VALIDATE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="7" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
<property name="PackagerStepContentPanel_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="15" type="GuiHandlerData"/>
<property name="ProjectDashboardView_DASHBOARD" value="1" type="GuiHandlerData"/>
<property name="RSBExternalPortPropPanels_NAME" value="1" type="GuiHandlerData"/>
<property name="RefreshPackagerTableAction_REFRESH_ALL_ROWS_IN_TABLE" value="1" type="GuiHandlerData"/>
<property name="ReviewContentPanel_PACKAGE_IP" value="1" type="GuiHandlerData"/>
<property name="ReviewContentPanel_RE_PACKAGE_IP" value="1" type="GuiHandlerData"/>
<property name="ReviewContentPanel_RE_PACKAGE_IP" value="2" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="2" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_ADD_IP" value="2" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_CREATE_PORT" value="17" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
@@ -91,9 +114,9 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SystemTab_SHOW_IP_STATUS" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="72" type="GuiMode"/>
<property name="GuiMode" value="136" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="56" type="TclMode"/>
<property name="TclMode" value="132" type="TclMode"/>
</item>
</section>
</application>
LIB/AckCheckerBlock/AckCheckerBlock.runs/.jobs/vrs_config_5.xml
+179
View File
@@ -0,0 +1,179 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="AckChecker_AckCheckerConcept_0_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="AckChecker_AckCheckerConcept_0_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_0_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_0_3_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_0_4_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_1_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_2_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_3_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_4_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_5_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_6_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_7_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_4_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_5_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_6_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_7_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_12_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_13_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_14_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_15_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_12_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_13_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_14_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_15_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_12_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_13_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_14_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_15_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_12_3_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_13_3_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_14_3_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_AckCheckerConcept_15_3_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16OUT_0_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="AckChecker_BusBlock16OUT_0_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16OUT_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16OUT_0_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16OUT_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16OUT_1_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16OUT_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_0_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="AckChecker_BusBlock16IN_0_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_0_2_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_2_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_1_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_4_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_4_1_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="AckChecker_BusBlock16IN_6_0_synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado" IsOrderedIPRun="true">
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
</Run>
<Run Id="synth_1" LaunchDir="D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
<Parent Id="AckChecker_AckCheckerConcept_0_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_0_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_0_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_0_3_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_0_4_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_1_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_2_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_3_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_4_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_5_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_6_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_7_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_4_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_5_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_6_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_7_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_12_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_13_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_14_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_15_0_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_12_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_13_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_14_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_15_1_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_12_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_13_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_14_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_15_2_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_12_3_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_13_3_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_14_3_synth_1"/>
<Parent Id="AckChecker_AckCheckerConcept_15_3_synth_1"/>
<Parent Id="AckChecker_BusBlock16OUT_0_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16OUT_0_1_synth_1"/>
<Parent Id="AckChecker_BusBlock16OUT_0_2_synth_1"/>
<Parent Id="AckChecker_BusBlock16OUT_1_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_0_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_0_1_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_0_2_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_2_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_1_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_4_0_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_4_1_synth_1"/>
<Parent Id="AckChecker_BusBlock16IN_6_0_synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/.vivado.begin.rst
+1 -1
View File
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="stas" Host="STAS" Pid="5400" HostCore="12" HostMemory="016964153344">
<Process Command="vivado.bat" Owner="stud" Host="STAS-W10" Pid="5764" HostCore="8" HostMemory="034314457088">
</Process>
</ProcessHandle>
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp
BIN
View File
Binary file not shown.
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.tcl
+20 -20
View File
@@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project]
set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project]
set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project]
set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_repo_paths d:/Projects/IP [current_project]
set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project]
update_ip_catalog
set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project]
set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci
read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
@@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
}
set_param ips.enableIPCacheLiteLoad 1
set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 -new_name AckChecker_AckCheckerConcept_0_0 -ip [get_ips AckChecker_AckCheckerConcept_0_0]]
set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 -new_name AckChecker_AckCheckerConcept_0_0 -ip [get_ips AckChecker_AckCheckerConcept_0_0]]
if { $cached_ip eq {} } {
close [open __synthesis_is_running__ w]
@@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_0.dcp
create_report "AckChecker_AckCheckerConcept_0_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb"
if { [catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp
} _RESULT ] } {
send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v
write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl
write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v
write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
@@ -120,47 +120,47 @@ if { [catch {
if { [catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp
} _RESULT ] } {
send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
}; # end if cached_ip
if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} {
if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} {
catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0
}
}
if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} {
if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} {
catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0
}
}
file delete __synthesis_is_running__
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds
+43 -40
View File
@@ -2,44 +2,47 @@
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Apr 29 14:04:37 2020
# Process ID: 6832
# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1
# Start of session at: Wed May 3 11:35:16 2023
# Process ID: 2788
# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1
# Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl
# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds
# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou
# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds
# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou
#-----------------------------------------------------------
source AckChecker_AckCheckerConcept_0_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.)
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'.
Command: synth_design -top AckChecker_AckCheckerConcept_0_0 -part xc7z020clg484-3 -mode out_of_context
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 19012
INFO: Helper process launched with PID 11448
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 574.430 ; gain = 182.664
Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.355 ; gain = 181.930
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320
Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg484-3
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7z020clg484-3
INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module 'AckCheckerConcept'
@@ -53,7 +56,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'acknowledge_reg' using encoding 'sequential' in module 'AckCheckerConcept'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -117,7 +120,7 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 803.441 ; gain = 411.676
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.207 ; gain = 412.781
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -130,7 +133,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 806.750 ; gain = 414.984
Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.129 ; gain = 415.703
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -142,7 +145,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -166,7 +169,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -179,7 +182,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -191,25 +194,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -243,35 +246,35 @@ Report Instance Areas:
|2 | U0 |AckCheckerConcept | 69|
+------+---------+------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 924.840 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 924.840 ; gain = 538.379
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 924.840 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 928.266 ; gain = 541.242
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1360.527 ; gain = 435.688
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1366.223 ; gain = 437.957
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 75535be1b50c31fe
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1361.664 ; gain = 0.000
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 9fc500b6c8c4592a
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1367.215 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:08 2020...
INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:55 2023...
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt
+2 -2
View File
@@ -1,8 +1,8 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Wed Apr 29 14:05:08 2020
| Host : Stas running 64-bit major release (build 9200)
| Date : Wed May 3 11:35:55 2023
| Host : STAS-W10 running 64-bit major release (build 9200)
| Command : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb
| Design : AckChecker_AckCheckerConcept_0_0
| Device : 7z020clg484-3
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/gen_run.xml
+2 -4
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="AckChecker_AckCheckerConcept_0_0_synth_1" LaunchPart="xc7z020clg484-3" LaunchTime="1588158270">
<GenRun Id="AckChecker_AckCheckerConcept_0_0_synth_1" LaunchPart="xc7z020clg484-3" LaunchTime="1683102908">
<File Type="PA-TCL" Name="AckChecker_AckCheckerConcept_0_0.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="AckChecker_AckCheckerConcept_0_0_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="AckChecker_AckCheckerConcept_0_0_reports.tcl"/>
@@ -46,9 +46,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/project.wdf
-75
View File
@@ -1,75 +0,0 @@
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70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b3136494e5f76315f305f355c41636b436865636b65725f427573426c6f636b3136494e5f325f30:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b3136494e5f76315f305f355c41636b436865636b65725f427573426c6f636b3136494e5f345f30:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b3136494e5f76315f305f355c41636b436865636b65725f427573426c6f636b3136494e5f345f31:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b3136494e5f76315f305f355c41636b436865636b65725f427573426c6f636b3136494e5f365f30:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b31364f55545f76315f305f355c41636b436865636b65725f427573426c6f636b31364f55545f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b31364f55545f76315f305f355c41636b436865636b65725f427573426c6f636b31364f55545f305f31:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b31364f55545f76315f305f355c41636b436865636b65725f427573426c6f636b31364f55545f305f32:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c427573426c6f636b31364f55545f76315f305f355c41636b436865636b65725f427573426c6f636b31364f55545f315f30:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00
eof:95469607
LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.log → LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.log
+85 -79
View File
@@ -1,6 +1,6 @@
*** Running vivado
with args -log Inverter_3lvl_P0N_3lvl_0_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl
with args -log AckChecker_AckCheckerConcept_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl
****** Vivado v2019.1 (64-bit)
@@ -8,57 +8,54 @@
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source Inverter_3lvl_P0N_3lvl_0_4.tcl -notrace
source AckChecker_AckCheckerConcept_0_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1'.)
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'.
Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_4 -part xc7z020clg484-3 -mode out_of_context
Command: synth_design -top AckChecker_AckCheckerConcept_0_0 -part xc7z020clg484-3 -mode out_of_context
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 7672
INFO: Helper process launched with PID 11448
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 575.129 ; gain = 182.785
Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.355 ; gain = 181.930
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76]
INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:109]
INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61]
WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154]
WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155]
INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76]
INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.793 ; gain = 247.449
Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg484-3
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7z020clg484-3
INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98]
INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl'
INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module 'AckCheckerConcept'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
closed | 0000001 | 000
n | 0000010 | 110
tech_closed | 0000100 | 001
p | 0001000 | 101
zero_p | 0010000 | 011
zero | 0100000 | 010
zero_n | 1000000 | 100
waiting | 00 | 00
check | 01 | 01
waiting_strobe_end | 10 | 10
iSTATE | 11 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl'
INFO: [Synth 8-3354] encoded FSM with state register 'acknowledge_reg' using encoding 'sequential' in module 'AckCheckerConcept'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -71,13 +68,18 @@ No constraint files found.
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
1 Bit Registers := 19
8 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
7 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 16
2 Input 1 Bit Muxes := 47
7 Input 1 Bit Muxes := 10
2 Input 8 Bit Muxes := 3
4 Input 8 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
4 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
@@ -85,15 +87,20 @@ Finished RTL Component Statistics
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module P0N_3lvl
Module AckCheckerConcept
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
1 Bit Registers := 19
8 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
7 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 16
2 Input 1 Bit Muxes := 47
7 Input 1 Bit Muxes := 10
2 Input 8 Bit Muxes := 3
4 Input 8 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
4 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
@@ -112,7 +119,7 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 806.691 ; gain = 414.348
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.207 ; gain = 412.781
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -125,7 +132,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 813.012 ; gain = 420.668
Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.129 ; gain = 415.703
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -137,7 +144,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -161,7 +168,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -174,7 +181,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -186,25 +193,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -220,54 +227,53 @@ Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |CARRY4 | 36|
|2 |LUT1 | 4|
|3 |LUT2 | 7|
|4 |LUT3 | 4|
|5 |LUT4 | 108|
|6 |LUT5 | 7|
|7 |LUT6 | 23|
|8 |FDRE | 121|
|9 |FDSE | 1|
|1 |CARRY4 | 4|
|2 |LUT1 | 1|
|3 |LUT2 | 25|
|4 |LUT3 | 5|
|5 |LUT4 | 11|
|6 |LUT5 | 6|
|7 |LUT6 | 4|
|8 |FDRE | 13|
+------+-------+------+
Report Instance Areas:
+------+---------+---------+------+
| |Instance |Module |Cells |
+------+---------+---------+------+
|1 |top | | 311|
|2 | U0 |P0N_3lvl | 311|
+------+---------+---------+------+
+------+---------+------------------+------+
| |Instance |Module |Cells |
+------+---------+------------------+------+
|1 |top | | 69|
|2 | U0 |AckCheckerConcept | 69|
+------+---------+------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 930.840 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 930.840 ; gain = 543.824
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 930.840 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 928.266 ; gain = 541.242
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1388.254 ; gain = 457.414
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1366.223 ; gain = 437.957
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP Inverter_3lvl_P0N_3lvl_0_4, cache-ID = fdc8b3b6ee8afc45
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1389.293 ; gain = 0.000
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 9fc500b6c8c4592a
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1367.215 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:58 2021...
INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:55 2023...
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.sh
+1 -1
View File
@@ -24,7 +24,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'
HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.jou
+5 -5
View File
@@ -2,11 +2,11 @@
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Apr 29 14:04:37 2020
# Process ID: 6832
# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1
# Start of session at: Wed May 3 11:35:16 2023
# Process ID: 2788
# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1
# Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl
# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds
# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou
# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds
# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou
#-----------------------------------------------------------
source AckChecker_AckCheckerConcept_0_0.tcl -notrace
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.pb
BIN
View File
Binary file not shown.
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/.vivado.begin.rst
+1 -1
View File
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="stas" Host="STAS" Pid="10244" HostCore="12" HostMemory="016964153344">
<Process Command="vivado.bat" Owner="stud" Host="STAS-W10" Pid="2172" HostCore="8" HostMemory="034314457088">
</Process>
</ProcessHandle>
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp
BIN
View File
Binary file not shown.
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.tcl
+20 -20
View File
@@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project]
set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project]
set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project]
set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_repo_paths d:/Projects/IP [current_project]
set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project]
update_ip_catalog
set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project]
set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xci
read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xci
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
@@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
}
set_param ips.enableIPCacheLiteLoad 1
set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 -new_name AckChecker_AckCheckerConcept_0_1 -ip [get_ips AckChecker_AckCheckerConcept_0_1]]
set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 -new_name AckChecker_AckCheckerConcept_0_1 -ip [get_ips AckChecker_AckCheckerConcept_0_1]]
if { $cached_ip eq {} } {
close [open __synthesis_is_running__ w]
@@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_1.dcp
create_report "AckChecker_AckCheckerConcept_0_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_1_utilization_synth.pb"
if { [catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp
} _RESULT ] } {
send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v
write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl
write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v
write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl
write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
@@ -120,47 +120,47 @@ if { [catch {
if { [catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp
} _RESULT ] } {
send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl
file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
}; # end if cached_ip
if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} {
if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} {
catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1
}
}
if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} {
if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} {
catch {
file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1
file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1
}
}
file delete __synthesis_is_running__
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds
+9 -9
View File
@@ -2,17 +2,17 @@
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Apr 29 14:05:11 2020
# Process ID: 20660
# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1
# Start of session at: Wed May 3 11:35:58 2023
# Process ID: 1000
# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1
# Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl
# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds
# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou
# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds
# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou
#-----------------------------------------------------------
source AckChecker_AckCheckerConcept_0_1.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.)
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 75535be1b50c31fe.
INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:17 2020...
INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 9fc500b6c8c4592a.
INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023...
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/gen_run.xml
+2 -4
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="AckChecker_AckCheckerConcept_0_1_synth_1" LaunchPart="xc7z020clg484-3" LaunchTime="1588158270">
<GenRun Id="AckChecker_AckCheckerConcept_0_1_synth_1" LaunchPart="xc7z020clg484-3" LaunchTime="1683102908">
<File Type="PA-TCL" Name="AckChecker_AckCheckerConcept_0_1.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="AckChecker_AckCheckerConcept_0_1_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="AckChecker_AckCheckerConcept_0_1_reports.tcl"/>
@@ -46,9 +46,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/project.wdf
-75
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@@ -1,75 +0,0 @@
version:1
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eof:95469607
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.log
+17
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@@ -0,0 +1,17 @@
*** Running vivado
with args -log AckChecker_AckCheckerConcept_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl
****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source AckChecker_AckCheckerConcept_0_1.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 9fc500b6c8c4592a.
INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023...
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.sh
+1 -1
View File
@@ -24,7 +24,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'
HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.jou
+5 -5
View File
@@ -2,11 +2,11 @@
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Apr 29 14:05:11 2020
# Process ID: 20660
# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1
# Start of session at: Wed May 3 11:35:58 2023
# Process ID: 1000
# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1
# Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl
# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds
# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou
# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds
# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou
#-----------------------------------------------------------
source AckChecker_AckCheckerConcept_0_1.tcl -notrace

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